diff --git a/Common/sim/ModelSim SE .lnk b/Common/sim/ModelSim SE .lnk
deleted file mode 100644
index ecadd02..0000000
Binary files a/Common/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/Common/sim/compile_fixed.do b/Common/sim/compile_fixed.do
deleted file mode 100644
index 0c17180..0000000
--- a/Common/sim/compile_fixed.do
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Compile script for Modeltech
-#
-vlib ieee_proposed
-vmap ieee_proposedx ieee_proposed
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_additions_c.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/env_c.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/standard_textio_additions_c.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/std_logic_1164_additions.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_additions.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/numeric_std_unsigned_c.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/math_utility_pkg_c.vhdl"
-vcom -work ieee_proposed -93 "../../lib/fixed/modelsim/fixed_pkg_c.vhdl"
diff --git a/Common/sim/compile_simprim.do b/Common/sim/compile_simprim.do
deleted file mode 100644
index 9f7ba37..0000000
--- a/Common/sim/compile_simprim.do
+++ /dev/null
@@ -1,8 +0,0 @@
-vlib simprim
-
-set XILINX $env(XILINX)
-
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
-vcom -93 -work simprim  $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd
diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do
deleted file mode 100644
index 4aec199..0000000
--- a/Common/sim/compile_unisim.do
+++ /dev/null
@@ -1,8 +0,0 @@
-vlib unisim
-
-set XILINX $env(XILINX)
-
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_smodel.vhd
-vcom -93 -work unisim  $XILINX/vhdl/src/unisims/unisim_vital.vhd
diff --git a/Common/ucf/ml402.ucf b/Common/ucf/ml402.ucf
deleted file mode 100644
index 318e778..0000000
--- a/Common/ucf/ml402.ucf
+++ /dev/null
@@ -1,675 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#     
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-# Bus clock nets
-NET "sys_clk"  TNM_NET = "sys_clk";
-NET "tft_clk"  TNM_NET = "tft_clk";
-NET sys_clk_in TNM_NET = "sys_clk_in";
-TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
-
-NET sys_clk_in LOC = AE14;
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET sys_rst_in LOC = D6;
-NET sys_rst_in PULLUP;
-NET sys_rst_in TIG;
-
-NET uart_RX LOC = W2;
-NET uart_RX IOSTANDARD = LVCMOS33;
-NET uart_RX TIG;
-NET uart_TX LOC = W1;
-NET uart_TX IOSTANDARD = LVCMOS33;
-NET uart_TX TIG;
-
-NET ext_irq TIG;
-
-# Reset timing ignore - treat as async paths
-NET sys_rst TIG;
-NET opb_v20_0_OPB_Rst TIG;
-NET lmb_v10_1_OPB_Rst TIG;
-NET lmb_v10_0_OPB_Rst TIG;
-NET opb_v20_0_Debug_SYS_Rst TIG;
-NET Debug_Rst TIG;
-NET plb_v34_0_PLB_Rst TIG;
-NET dcm_locked TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
-INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
-INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
-
-INST dcm_0/dcm_0/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y0;
-INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
-INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
-
-INST dcm_1/dcm_1/CLK0_BUFG_INST  LOC = BUFGCTRL_X0Y31;
-INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches 
-////////////////////////////////////////////////////////////////////////////
-
-# GPLED 0-3
-NET gpio<0>  LOC = G5;  #GPLED0
-NET gpio<1>  LOC = G6;  #GPLED1
-NET gpio<2>  LOC = A11; #GPLED2
-NET gpio<3>  LOC = A12; #GPLED3
-# North-East-South-West-Center LEDs
-NET gpio<4>  LOC = C6;  # C LED
-NET gpio<5>  LOC = F9;  # W LED
-NET gpio<6>  LOC = A5;  # S LED
-NET gpio<7>  LOC = E10; # E LED
-NET gpio<8>  LOC = E2;  # N LED
-# North-East-South-West-Center Buttons
-NET gpio<9>  LOC = B6;  # C Button
-NET gpio<10> LOC = E9;  # W Button
-NET gpio<11> LOC = A6;  # S Button
-NET gpio<12> LOC = F10; # E Button
-NET gpio<13> LOC = E7;  # N Button
-# Dip Switches 1-8
-NET gpio<14> LOC = U24; # DIP SW 8
-NET gpio<15> LOC = U25; # DIP SW 7
-NET gpio<16> LOC = V23; # DIP SW 6
-NET gpio<17> LOC = U23; # DIP SW 5
-NET gpio<18> LOC = U26; # DIP SW 4
-NET gpio<19> LOC = T26; # DIP SW 3
-NET gpio<20> LOC = R19; # DIP SW 2
-NET gpio<21> LOC = R20; # DIP SW 1
-NET gpio<14> IOSTANDARD = LVCMOS33;
-NET gpio<15> IOSTANDARD = LVCMOS33;
-NET gpio<16> IOSTANDARD = LVCMOS33;
-NET gpio<17> IOSTANDARD = LVCMOS33;
-NET gpio<18> IOSTANDARD = LVCMOS33;
-NET gpio<19> IOSTANDARD = LVCMOS33;
-NET gpio<20> IOSTANDARD = LVCMOS33;
-NET gpio<21> IOSTANDARD = LVCMOS33;
-#SMA Connectors
-NET gpio<22> LOC = C12; # SMA_IN_N
-NET gpio<23> LOC = C13; # SMA_IN_P
-NET gpio<24> LOC = D7;  # SMA_OUT_N
-NET gpio<25> LOC = D8;  # SMA_OUT_P
-NET gpio<26> LOC = AD12;# USERCLK
-NET gpio<26> IOSTANDARD = LVCMOS33;
-
-NET "gpio<*>" PULLDOWN;
-NET "gpio<*>" TIG;
-NET "gpio<*>" SLEW = SLOW;
-NET "gpio<*>" DRIVE = 2;
-
-NET "gpio<22>" SLEW = FAST;
-NET "gpio<22>" DRIVE = 12;
-NET "gpio<23>" SLEW = FAST;
-NET "gpio<23>" DRIVE = 12;
-NET "gpio<24>" SLEW = FAST;
-NET "gpio<24>" DRIVE = 12;
-NET "gpio<25>" SLEW = FAST;
-NET "gpio<25>" DRIVE = 12;
-
-NET  "gpio2_d_out<*>" TIG;
-NET  "gpio2_t_out<*>" TIG;
-NET  "gpio2_in<*>" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for PS/2 Ports
-#------------------------------------------------------------------------------
-
-#Keyboard
-NET ps2_keyb_clk  LOC = D2;
-NET ps2_keyb_clk  SLEW = SLOW;
-NET ps2_keyb_clk  DRIVE = 2;
-NET ps2_keyb_clk  TIG;
-NET ps2_keyb_data LOC = G9;
-NET ps2_keyb_data SLEW = SLOW;
-NET ps2_keyb_data DRIVE = 2;
-NET ps2_keyb_data TIG;
-
-#Mouse
-NET ps2_mouse_clk  LOC = B14;
-NET ps2_mouse_clk  SLEW = SLOW;
-NET ps2_mouse_clk  DRIVE = 2;
-NET ps2_mouse_clk  TIG;
-NET ps2_mouse_data LOC = C14;
-NET ps2_mouse_data SLEW = SLOW;
-NET ps2_mouse_data DRIVE = 2;
-NET ps2_mouse_data TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for IIC Controller
-#------------------------------------------------------------------------------
-
-NET iic_scl    LOC = A17;
-NET iic_sda    LOC = B17;
-NET iic_scl    SLEW = SLOW;
-NET iic_scl    DRIVE = 6;
-NET iic_scl    TIG;
-NET iic_sda    SLEW = SLOW;
-NET iic_sda    DRIVE = 6;
-NET iic_sda    TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for AC97 Sound Controller
-#------------------------------------------------------------------------------
-
-NET ac97_bit_clk   LOC = AE10;
-NET ac97_bit_clk   IOSTANDARD = LVCMOS33;
-NET ac97_bit_clk   PERIOD = 80;
-NET ac97_sdata_in  LOC = AD16;
-NET ac97_sdata_in  IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   LOC = AD10;
-NET ac97_reset_n   IOSTANDARD = LVCMOS33;
-NET ac97_reset_n   TIG;
-NET ac97_sdata_out LOC = C8;
-NET ac97_sync      LOC = D9;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for System ACE MPU / USB
-#------------------------------------------------------------------------------
-
-NET sysace_clk_in   LOC        = AF11;
-NET sysace_clk_in   IOSTANDARD = LVCMOS33;
-NET sysace_clk_in   TNM_NET    = "sysace_clk_in";
-# Leave 1 ns margin
-TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
-
-NET sace_usb_a<0>   LOC        = U22;
-NET sace_usb_a<1>   LOC        = Y10;
-NET sace_usb_a<2>   LOC        = AA10;
-NET sace_usb_a<3>   LOC        = AC7;
-NET sace_usb_a<4>   LOC        = Y7;
-NET sace_usb_a<5>   LOC        = AA9;
-NET sace_usb_a<6>   LOC        = Y9;
-NET sace_usb_a<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_a<*>   SLEW       = FAST;
-NET sace_usb_a<*>   DRIVE      = 8;
-NET sace_mpce       LOC        = AD5;
-NET sace_mpce       IOSTANDARD = LVCMOS33;
-NET sace_mpce       SLEW       = FAST;
-NET sace_mpce       DRIVE      = 8;
-NET sace_usb_d<0>   LOC        = AB7;
-NET sace_usb_d<1>   LOC        = AC9;
-NET sace_usb_d<2>   LOC        = AB9;
-NET sace_usb_d<3>   LOC        = AE6;
-NET sace_usb_d<4>   LOC        = AD6;
-NET sace_usb_d<5>   LOC        = AF9;
-NET sace_usb_d<6>   LOC        = AE9;
-NET sace_usb_d<7>   LOC        = AD8;
-NET sace_usb_d<8>   LOC        = AC8;
-NET sace_usb_d<9>   LOC        = AF4;
-NET sace_usb_d<10>  LOC        = AE4;
-NET sace_usb_d<11>  LOC        = AD3;
-NET sace_usb_d<12>  LOC        = AC3;
-NET sace_usb_d<13>  LOC        = AF6;
-NET sace_usb_d<14>  LOC        = AF5;
-NET sace_usb_d<15>  LOC        = AA7;
-NET sace_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sace_usb_d<*>   SLEW       = FAST;
-NET sace_usb_d<*>   DRIVE      = 8;
-NET sace_usb_d<*>   PULLDOWN;
-NET sace_usb_oen    LOC        = AA8;
-NET sace_usb_oen    IOSTANDARD = LVCMOS33;
-NET sace_usb_oen    SLEW       = FAST;
-NET sace_usb_oen    DRIVE      = 8;
-NET sace_usb_wen    LOC        = Y8;
-NET sace_usb_wen    IOSTANDARD = LVCMOS33;
-NET sace_usb_wen    SLEW       = FAST;
-NET sace_usb_wen    DRIVE      = 8;
-NET sysace_mpirq    LOC        = AD4;
-NET sysace_mpirq    IOSTANDARD = LVCMOS33;
-NET sysace_mpirq    TIG;
-NET sysace_mpirq    PULLDOWN;
-
-NET usb_csn         LOC        = AF10;
-NET usb_csn         IOSTANDARD = LVCMOS33;
-NET usb_csn         SLEW       = FAST;
-NET usb_csn         DRIVE      = 8;
-NET usb_hpi_reset_n LOC        = A7;
-NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
-NET usb_hpi_reset_n TIG;
-NET usb_hpi_int     LOC        = V5;
-NET usb_hpi_int     IOSTANDARD = LVCMOS33;
-NET usb_hpi_int     TIG;
-NET usb_hpi_int     PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET ddr_ad<0>  LOC = C26; # DDR_A0
-NET ddr_ad<1>  LOC = E17; # DDR_A1
-NET ddr_ad<2>  LOC = D18; # DDR_A2
-NET ddr_ad<3>  LOC = C19; # DDR_A3
-NET ddr_ad<4>  LOC = F17; # DDR_A4
-NET ddr_ad<5>  LOC = B18; # DDR_A5
-NET ddr_ad<6>  LOC = B20; # DDR_A6
-NET ddr_ad<7>  LOC = C20; # DDR_A7
-NET ddr_ad<8>  LOC = D20; # DDR_A8
-NET ddr_ad<9>  LOC = C21; # DDR_A9
-NET ddr_ad<10> LOC = A18; # DDR_A10
-NET ddr_ad<11> LOC = B21; # DDR_A11
-NET ddr_ad<12> LOC = A24; # DDR_A12
-NET ddr_ba<0>  LOC = B12; # DDR_BA0
-NET ddr_ba<1>  LOC = A16; # DDR_BA1
-NET ddr_casb   LOC = F23; # DDR_CAS_N
-NET ddr_cke    LOC = G22; # DDR_CKE
-NET ddr_csb    LOC = G21; # DDR_CS_N
-NET ddr_rasb   LOC = F24; # DDR_RAS_N
-NET ddr_web    LOC = A23; # DDR_WE_N
-
-NET ddr_clk    LOC = A10; # DDR_CK1_P
-NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET ddr_clkb   LOC = B10; # DDR_CK1_N
-
-NET ddr_dm<0>  LOC = G19; # DDR_DM0
-NET ddr_dm<1>  LOC = G24; # DDR_DM1
-NET ddr_dm<2>  LOC = G20; # DDR_DM2
-NET ddr_dm<3>  LOC = C22; # DDR_DM3
-
-NET ddr_dqs<0> LOC = D25; # DDR_DQS0
-NET ddr_dqs<1> LOC = G18; # DDR_DQS1
-NET ddr_dqs<2> LOC = G17; # DDR_DQS2
-NET ddr_dqs<3> LOC = D26; # DDR_DQS3
-
-NET ddr_dq<0> LOC = H20; # DDR_D0
-NET ddr_dq<1> LOC = E23; # DDR_D1
-NET ddr_dq<2> LOC = H26; # DDR_D2
-NET ddr_dq<3> LOC = H22; # DDR_D3
-NET ddr_dq<4> LOC = E25; # DDR_D4
-NET ddr_dq<5> LOC = E26; # DDR_D5
-NET ddr_dq<6> LOC = F26; # DDR_D6
-NET ddr_dq<7> LOC = E24; # DDR_D7
-NET ddr_dq<8> LOC = E20; # DDR_D8
-NET ddr_dq<9> LOC = A22; # DDR_D9
-NET ddr_dq<10> LOC = C23; # DDR_D10
-NET ddr_dq<11> LOC = C24; # DDR_D11
-NET ddr_dq<12> LOC = A20; # DDR_D12
-NET ddr_dq<13> LOC = A21; # DDR_D13
-NET ddr_dq<14> LOC = D24; # DDR_D14
-NET ddr_dq<15> LOC = E18; # DDR_D15
-NET ddr_dq<16> LOC = F18; # DDR_D16
-NET ddr_dq<17> LOC = A19; # DDR_D17
-NET ddr_dq<18> LOC = F19; # DDR_D18
-NET ddr_dq<19> LOC = B23; # DDR_D19
-NET ddr_dq<20> LOC = E21; # DDR_D20
-NET ddr_dq<21> LOC = D22; # DDR_D21
-NET ddr_dq<22> LOC = D23; # DDR_D22
-NET ddr_dq<23> LOC = B24; # DDR_D23
-NET ddr_dq<24> LOC = E22; # DDR_D24
-NET ddr_dq<25> LOC = F20; # DDR_D25
-NET ddr_dq<26> LOC = H23; # DDR_D26
-NET ddr_dq<27> LOC = G25; # DDR_D27
-NET ddr_dq<28> LOC = G26; # DDR_D28
-NET ddr_dq<29> LOC = H25; # DDR_D29
-NET ddr_dq<30> LOC = H24; # DDR_D30
-NET ddr_dq<31> LOC = H21; # DDR_D31
-
-NET ddr_ad<*>  IOSTANDARD = SSTL2_I;
-NET ddr_ba<*>  IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_cke    IOSTANDARD = SSTL2_I;
-NET ddr_clk    IOSTANDARD = SSTL2_I;
-NET ddr_clk_fb IOSTANDARD = LVCMOS25;
-NET ddr_clkb   IOSTANDARD = SSTL2_I;
-NET ddr_casb   IOSTANDARD = SSTL2_I;
-NET ddr_csb    IOSTANDARD = SSTL2_I;
-NET ddr_rasb   IOSTANDARD = SSTL2_I;
-NET ddr_web    IOSTANDARD = SSTL2_I;
-
-NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
-NET ddr_dm<*>  IOSTANDARD = SSTL2_II;
-NET ddr_dq<*>  IOSTANDARD = SSTL2_II;
-
-// Timing Constraint for DDR Feedback Clock
-NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
-TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
-#------------------------------------------------------------------------------
-
-NET tft_lcd_b<0> LOC = L26; # VGA_B2
-NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_b<1> LOC = C5;  # VGA_B3
-NET tft_lcd_b<2> LOC = C7;  # VGA_B4
-NET tft_lcd_b<3> LOC = B7;  # VGA_B5
-NET tft_lcd_b<4> LOC = G8;  # VGA_B6
-NET tft_lcd_b<5> LOC = F8;  # VGA_B7
-NET tft_lcd_b<*> SLEW = FAST;
-NET tft_lcd_b<*> DRIVE = 8;
-
-NET tft_lcd_clk  LOC = AF8;
-NET tft_lcd_clk  IOSTANDARD = LVDCI_33;
-NET tft_lcd_clk  SLEW = FAST;
-NET tft_lcd_clk  DRIVE = 8;
-
-NET tft_lcd_g<0> LOC = M20; # VGA_G2
-NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_g<1> LOC = E4;  # VGA_G3
-NET tft_lcd_g<2> LOC = D3;  # VGA_G4
-NET tft_lcd_g<3> LOC = H7;  # VGA_G5
-NET tft_lcd_g<4> LOC = H8;  # VGA_G6
-NET tft_lcd_g<5> LOC = C1;  # VGA_G7
-NET tft_lcd_g<*> SLEW = FAST;
-NET tft_lcd_g<*> DRIVE = 8;
-
-NET tft_lcd_hsync LOC = C10;
-NET tft_lcd_hsync SLEW = FAST;
-NET tft_lcd_hsync DRIVE = 8;
-
-NET tft_lcd_r<0> LOC = N25; #VGA_R2
-NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
-NET tft_lcd_r<1> LOC = C2; #VGA_R3
-NET tft_lcd_r<2> LOC = G7; #VGA_R4
-NET tft_lcd_r<3> LOC = F7; #VGA_R5
-NET tft_lcd_r<4> LOC = E5; #VGA_R6
-NET tft_lcd_r<5> LOC = E6; #VGA_R7
-NET tft_lcd_r<*> SLEW = FAST;
-NET tft_lcd_r<*> DRIVE = 8;
-
-NET tft_lcd_vsync LOC = A8;
-NET tft_lcd_vsync SLEW = FAST;
-NET tft_lcd_vsync DRIVE = 8;
-
-TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
-TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET plb_error LOC = L24;
-NET plb_error IOSTANDARD = LVCMOS33;
-NET plb_error TIG;
-NET opb_error LOC = V6;
-NET opb_error IOSTANDARD = LVCMOS33;
-NET opb_error TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Ethernet
-#------------------------------------------------------------------------------
-
-NET phy_col        LOC = E3;
-NET phy_crs        LOC = D5;
-NET phy_dv         LOC = A9;
-NET phy_rx_clk     LOC = B15;
-NET phy_rx_data<3> LOC = C4;
-NET phy_rx_data<2> LOC = D4;
-NET phy_rx_data<1> LOC = E1;
-NET phy_rx_data<0> LOC = F1;
-
-NET phy_rx_er      LOC = B9;
-NET phy_tx_clk     LOC = C15;
-NET phy_mii_clk    LOC = D1;
-NET phy_mii_int_n  LOC = H4;
-NET phy_rst_n      LOC = D10;
-NET phy_tx_data<3> LOC = G1;
-NET phy_tx_data<2> LOC = H3;
-NET phy_tx_data<1> LOC = H2;
-NET phy_tx_data<0> LOC = H1;
-NET phy_tx_en      LOC = F4;
-NET phy_tx_er      LOC = F3;
-NET phy_mii_data   LOC = G4;
-
-NET phy_mii_int_n  PULLUP;
-
-NET phy_mii_int_n  TIG;
-NET phy_rst_n      TIG;
-
-# Timing Constraints (these are recommended in documentation and
-# are unaltered except for the TIG)
-NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
-NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
-TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
-TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
-
-NET "phy_tx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
-NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
-
-NET "phy_rx_data<3>" IOBDELAY=NONE;
-NET "phy_rx_data<2>" IOBDELAY=NONE;
-NET "phy_rx_data<1>" IOBDELAY=NONE;
-NET "phy_rx_data<0>" IOBDELAY=NONE;
-NET "phy_dv" IOBDELAY=NONE;
-NET "phy_rx_er" IOBDELAY=NONE;
-NET "phy_crs" IOBDELAY=NONE;
-NET "phy_col" IOBDELAY=NONE;
-
-# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/DVD_FF"   IOB=FALSE;
-INST "opb_ethernet_0/opb_ethernet_0/RER_FF"   IOB=FALSE;
-
-# Timing ignores (to specify unconstrained paths)
-TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
-TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
-TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for SRAM/FLASH
-#------------------------------------------------------------------------------
-
-NET sram_clk            LOC = AF7;
-NET sram_clk_fb         LOC = AD17;
-NET flash_a23           LOC = T21;
-NET sram_flash_addr<22> LOC = U20;
-NET sram_flash_addr<21> LOC = T19;
-NET sram_flash_addr<20> LOC = AC5;
-NET sram_flash_addr<19> LOC = AB5;
-NET sram_flash_addr<18> LOC = AC4;
-NET sram_flash_addr<17> LOC = AB4;
-
-NET sram_flash_addr<16> LOC = AB3;
-NET sram_flash_addr<15> LOC = AA4;
-NET sram_flash_addr<14> LOC = AA3;
-NET sram_flash_addr<13> LOC = W5;
-NET sram_flash_addr<12> LOC = W6;
-NET sram_flash_addr<11> LOC = W3;
-NET sram_flash_addr<10> LOC = AF3;
-NET sram_flash_addr<9>  LOC = AE3;
-NET sram_flash_addr<8>  LOC = AD2;
-NET sram_flash_addr<7>  LOC = AD1;
-NET sram_flash_addr<6>  LOC = AC2;
-NET sram_flash_addr<5>  LOC = AC1;
-NET sram_flash_addr<4>  LOC = AB2;
-NET sram_flash_addr<3>  LOC = AB1;
-NET sram_flash_addr<2>  LOC = AA1;
-NET sram_flash_addr<1>  LOC = Y2;
-NET sram_flash_addr<0>  LOC = Y1;
-NET sram_flash_data<31> LOC = F14;
-NET sram_flash_data<30> LOC = F13;
-NET sram_flash_data<29> LOC = F12;
-NET sram_flash_data<28> LOC = F11;
-NET sram_flash_data<27> LOC = F16;
-NET sram_flash_data<26> LOC = F15;
-NET sram_flash_data<25> LOC = D14;
-NET sram_flash_data<24> LOC = D13;
-NET sram_flash_data<23> LOC = D15;
-NET sram_flash_data<22> LOC = E14;
-NET sram_flash_data<21> LOC = C11;
-NET sram_flash_data<20> LOC = D11;
-NET sram_flash_data<19> LOC = D16;
-NET sram_flash_data<18> LOC = C16;
-NET sram_flash_data<17> LOC = E13;
-NET sram_flash_data<16> LOC = D12;
-NET sram_flash_data<15> LOC = AA14;
-NET sram_flash_data<14> LOC = AB14;
-NET sram_flash_data<13> LOC = AC12;
-NET sram_flash_data<12> LOC = AC11;
-NET sram_flash_data<11> LOC = AA16;
-NET sram_flash_data<10> LOC = AA15;
-NET sram_flash_data<9>  LOC = AB13;
-NET sram_flash_data<8>  LOC = AA13;
-NET sram_flash_data<7>  LOC = AC14;
-NET sram_flash_data<6>  LOC = AD14;
-NET sram_flash_data<5>  LOC = AA12;
-NET sram_flash_data<4>  LOC = AA11;
-NET sram_flash_data<3>  LOC = AC16;
-NET sram_flash_data<2>  LOC = AC15;
-NET sram_flash_data<1>  LOC = AC13;
-NET sram_flash_data<0>  LOC = AD13;
-NET sram_cen            LOC = V7;
-NET sram_flash_oe_n     LOC = AC6;
-NET sram_flash_we_n     LOC = AB6;
-NET sram_bw<3>          LOC = Y3; #Y4; 
-NET sram_bw<2>          LOC = Y4; #Y3;
-NET sram_bw<1>          LOC = Y5; #Y6;
-NET sram_bw<0>          LOC = Y6; #Y5;
-NET flash_ce            LOC = W7;
-NET sram_adv_ld_n       LOC = W4;
-NET sram_mode           LOC = V26;
-
-NET sram_clk           IOSTANDARD = LVCMOS33;
-NET sram_clk           DRIVE = 16;
-NET sram_clk           SLEW = FAST;
-NET sram_clk_fb        IOSTANDARD = LVCMOS33;
-
-NET flash_a23          IOSTANDARD = LVDCI_33;
-NET flash_a23  SLEW = FAST;
-NET flash_a23  DRIVE = 8;
-
-NET sram_mode          IOSTANDARD = LVDCI_33;
-NET sram_mode SLEW = FAST;
-NET sram_mode DRIVE = 8;
-
-NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
-NET sram_flash_addr<*>  SLEW = FAST;
-NET sram_flash_addr<*>  DRIVE = 8;
-
-NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
-NET sram_flash_data<*> DRIVE = 12;
-NET sram_flash_data<*> SLEW = FAST;
-NET sram_flash_data<*> PULLDOWN;
-
-NET sram_flash_oe_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_oe_n SLEW = FAST;
-NET sram_flash_oe_n DRIVE = 8;
-
-NET sram_flash_we_n    IOSTANDARD = LVDCI_33;
-NET sram_flash_we_n SLEW = FAST;
-NET sram_flash_we_n DRIVE = 8;
-
-NET sram_bw<*>         IOSTANDARD = LVDCI_33;
-NET sram_bw<*> SLEW = FAST;
-NET sram_bw<*> DRIVE = 8;
-
-NET flash_ce           IOSTANDARD = LVDCI_33;
-NET flash_ce SLEW = FAST;
-NET flash_ce DRIVE = 8;
-
-NET sram_cen           IOSTANDARD = LVDCI_33;
-NET sram_cen SLEW = FAST;
-NET sram_cen DRIVE = 8;
-
-NET sram_adv_ld_n      IOSTANDARD = LVDCI_33;
-NET sram_adv_ld_n SLEW = FAST;
-NET sram_adv_ld_n DRIVE = 8;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Expansion Header GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
-NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
-NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
-NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
-NET gpio_exp_hdr1<27> LOC = W20;  # HDR1_44
-NET gpio_exp_hdr1<26> LOC = W21;  # HDR1_48
-NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
-NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
-NET gpio_exp_hdr1<23> LOC = W22;  # HDR1_46
-NET gpio_exp_hdr1<22> LOC = V21;  # HDR1_56
-NET gpio_exp_hdr1<21> LOC = V22;  # HDR1_54
-NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
-NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
-NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
-NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
-NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
-NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
-NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
-NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
-NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
-NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
-NET gpio_exp_hdr1<10> LOC = Y25;  # HDR1_40
-NET gpio_exp_hdr1<9>  LOC = Y26;  # HDR1_38
-NET gpio_exp_hdr1<8>  LOC = W26;  # HDR1_50
-NET gpio_exp_hdr1<7>  LOC = AB23; # HDR1_12
-NET gpio_exp_hdr1<6>  LOC = Y24;  # HDR1_26
-NET gpio_exp_hdr1<5>  LOC = AB24; # HDR1_32
-NET gpio_exp_hdr1<4>  LOC = W25;  # HDR1_52
-NET gpio_exp_hdr1<3>  LOC = AC24; # HDR1_2
-NET gpio_exp_hdr1<2>  LOC = AC25; # HDR1_36
-NET gpio_exp_hdr1<1>  LOC = V20;  # HDR1_42
-NET gpio_exp_hdr1<0>  LOC = AA24; # HDR1_28
-NET gpio_exp_hdr1<*> TIG;
-NET gpio_exp_hdr1<*> PULLDOWN;
-
-NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
-NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
-NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
-NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
-NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
-NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
-NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
-NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
-NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
-NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
-NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
-NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
-NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
-NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
-NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
-NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
-NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
-NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
-NET gpio_exp_hdr2<13> LOC = Y17;  # HDR2_56
-NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
-NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
-NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
-NET gpio_exp_hdr2<9>  LOC = Y22;  # HDR2_8
-NET gpio_exp_hdr2<8>  LOC = Y23;  # HDR2_6
-NET gpio_exp_hdr2<7>  LOC = W23;  # HDR2_12
-NET gpio_exp_hdr2<6>  LOC = W24;  # HDR2_10
-NET gpio_exp_hdr2<5>  LOC = Y20;  # HDR2_20
-NET gpio_exp_hdr2<4>  LOC = Y21;  # HDR2_18
-NET gpio_exp_hdr2<3>  LOC = Y19;  # HDR2_28
-NET gpio_exp_hdr2<2>  LOC = W19;  # HDR2_26
-NET gpio_exp_hdr2<1>  LOC = AA18; # HDR2_4
-NET gpio_exp_hdr2<0>  LOC = Y18;  # HDR2_2
-NET gpio_exp_hdr2<*> TIG;
-NET gpio_exp_hdr2<*> PULLDOWN;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Character LCD GPIO
-#------------------------------------------------------------------------------
-
-NET gpio_char_lcd<6> LOC = AE13; # LCD_E
-NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
-NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
-NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
-NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
-NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
-NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
-NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
-NET gpio_char_lcd<*> TIG;
-NET gpio_char_lcd<*> PULLDOWN;
diff --git a/lib/CPUs/J1/doc/j1.pdf b/lib/CPUs/J1/doc/j1.pdf
deleted file mode 100644
index 188ac02..0000000
Binary files a/lib/CPUs/J1/doc/j1.pdf and /dev/null differ
diff --git a/lib/CPUs/J1/sim/tb_j1.do b/lib/CPUs/J1/sim/tb_j1.do
deleted file mode 100644
index 4fa1a55..0000000
--- a/lib/CPUs/J1/sim/tb_j1.do
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/ram_2c_2r_2w.vhd"
-vcom -explicit  -93 "../src/core/j1.vhd"
-vcom -explicit  -93 "../src/tb_j1.vhd"
-
-vmap work
-
-vsim -t 1ps   -lib work tb_j1
-do {tb_j1.wave.do}
-view wave
-view structure
-view signals
-run 1us
diff --git a/lib/CPUs/J1/sim/tb_j1.wave.do b/lib/CPUs/J1/sim/tb_j1.wave.do
deleted file mode 100644
index 58c0f66..0000000
--- a/lib/CPUs/J1/sim/tb_j1.wave.do
+++ /dev/null
@@ -1,58 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_j1/sys_clk_i
-add wave -noupdate -format Logic /tb_j1/sys_rst_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_din
-add wave -noupdate -format Logic /tb_j1/io_rd
-add wave -noupdate -format Logic /tb_j1/io_wr
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/io_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/inst_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/data_dout
-add wave -noupdate -format Logic /tb_j1/data_we
-add wave -noupdate -format Logic /tb_j1/data_en
-add wave -noupdate -divider {J1 internals}
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/insn
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/immediate
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/ramrd
-add wave -noupdate -format Literal /tb_j1/uut/dsp
-add wave -noupdate -format Literal /tb_j1/uut/dsp2
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st0
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st02
-add wave -noupdate -format Logic /tb_j1/uut/dstkw2
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc2
-add wave -noupdate -format Literal /tb_j1/uut/rsp
-add wave -noupdate -format Literal /tb_j1/uut/rsp2
-add wave -noupdate -format Logic /tb_j1/uut/rstkw2
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstkd2
-add wave -noupdate -format Logic /tb_j1/uut/ramwe2
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/pc_plus_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/dstack
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rstack
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/st1
-add wave -noupdate -format Literal -radix hexadecimal /tb_j1/uut/rst0
-add wave -noupdate -format Literal /tb_j1/uut/st0sel
-add wave -noupdate -format Logic /tb_j1/uut/is_alu
-add wave -noupdate -format Logic /tb_j1/uut/is_lit
-add wave -noupdate -format Literal /tb_j1/uut/dd
-add wave -noupdate -format Literal /tb_j1/uut/rd
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1600185 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/CPUs/J1/src/core/j1.v b/lib/CPUs/J1/src/core/j1.v
deleted file mode 100644
index 861cb3c..0000000
--- a/lib/CPUs/J1/src/core/j1.v
+++ /dev/null
@@ -1,187 +0,0 @@
-module j1(
-   input sys_clk_i, input sys_rst_i, input [15:0] io_din,
-   output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
-
-  wire [15:0] insn;
-  wire [15:0] immediate = { 1'b0, insn[14:0] };
-
-  wire [15:0] ramrd;
-
-  reg [4:0] dsp;  // Data stack pointer
-  reg [4:0] _dsp;
-  reg [15:0] st0; // Return stack pointer
-  reg [15:0] _st0;
-  wire _dstkW;     // D stack write
-
-  reg [12:0] pc;
-  reg [12:0] _pc;
-  reg [4:0] rsp;
-  reg [4:0] _rsp;
-  reg _rstkW;     // R stack write
-  reg [15:0] _rstkD;
-  wire _ramWE;     // RAM write enable
-
-  wire [15:0] pc_plus_1;
-  assign pc_plus_1 = pc + 1;
-
-  // The D and R stacks
-  reg [15:0] dstack[0:31];
-  reg [15:0] rstack[0:31];
-  always @(posedge sys_clk_i)
-  begin
-    if (_dstkW)
-      dstack[_dsp] = st0;
-    if (_rstkW)
-      rstack[_rsp] = _rstkD;
-  end
-  wire [15:0] st1 = dstack[dsp];
-  wire [15:0] rst0 = rstack[rsp];
-
-  // st0sel is the ALU operation.  For branch and call the operation
-  // is T, for 0branch it is N.  For ALU ops it is loaded from the instruction
-  // field.
-  reg [3:0] st0sel;
-  always @*
-  begin
-    case (insn[14:13])
-      2'b00: st0sel = 0;          // ubranch
-      2'b10: st0sel = 0;          // call
-      2'b01: st0sel = 1;          // 0branch
-      2'b11: st0sel = insn[11:8]; // ALU
-      default: st0sel = 4'bxxxx;
-    endcase
-  end
-
-`define RAMS 3
-
-  genvar i;
-
-`define w (16 >> `RAMS)
-`define w1 (`w - 1)
-
-  generate 
-    for (i = 0; i < (1 << `RAMS); i=i+1) begin : ram
-      // RAMB16_S18_S18
-      RAMB16_S2_S2
-      ram(
-        .DIA(0),
-        // .DIPA(0),
-        .DOA(insn[`w*i+`w1:`w*i]),
-        .WEA(0),
-        .ENA(1),
-        .CLKA(sys_clk_i),
-        .ADDRA({_pc}),
-
-        .DIB(st1[`w*i+`w1:`w*i]),
-        // .DIPB(2'b0),
-        .WEB(_ramWE & (_st0[15:14] == 0)),
-        .ENB(|_st0[15:14] == 0),
-        .CLKB(sys_clk_i),
-        .ADDRB(_st0[15:1]),
-        .DOB(ramrd[`w*i+`w1:`w*i]));
-    end
-  endgenerate
-
-  // Compute the new value of T.
-  always @*
-  begin
-    if (insn[15])
-      _st0 = immediate;
-    else
-      case (st0sel)
-        4'b0000: _st0 = st0;
-        4'b0001: _st0 = st1;
-        4'b0010: _st0 = st0 + st1;
-        4'b0011: _st0 = st0 & st1;
-        4'b0100: _st0 = st0 | st1;
-        4'b0101: _st0 = st0 ^ st1;
-        4'b0110: _st0 = ~st0;
-        4'b0111: _st0 = {16{(st1 == st0)}};
-        4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
-        4'b1001: _st0 = st1 >> st0[3:0];
-        4'b1010: _st0 = st0 - 1;
-        4'b1011: _st0 = rst0;
-        4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
-        4'b1101: _st0 = st1 << st0[3:0];
-        4'b1110: _st0 = {rsp, 3'b000, dsp};
-        4'b1111: _st0 = {16{(st1 < st0)}};
-        default: _st0 = 16'hxxxx;
-      endcase
-  end
-
-  wire is_alu = (insn[15:13] == 3'b011);
-  wire is_lit = (insn[15]);
-
-  assign io_rd = (is_alu & (insn[11:8] == 4'hc));
-  assign io_wr = _ramWE;
-  assign io_addr = st0;
-  assign io_dout = st1;
-
-  assign _ramWE = is_alu & insn[5];
-  assign _dstkW = is_lit | (is_alu & insn[7]);
-
-  wire [1:0] dd = insn[1:0];  // D stack delta
-  wire [1:0] rd = insn[3:2];  // R stack delta
-
-  always @*
-  begin
-    if (is_lit) begin                       // literal
-      _dsp = dsp + 1;
-      _rsp = rsp;
-      _rstkW = 0;
-      _rstkD = _pc;
-    end else if (is_alu) begin
-      _dsp = dsp + {dd[1], dd[1], dd[1], dd};
-      _rsp = rsp + {rd[1], rd[1], rd[1], rd};
-      _rstkW = insn[6];
-      _rstkD = st0;
-    end else begin                          // jump/call
-      // predicated jump is like DROP
-      if (insn[15:13] == 3'b001) begin
-        _dsp = dsp - 1;
-      end else begin
-        _dsp = dsp;
-      end
-      if (insn[15:13] == 3'b010) begin // call
-        _rsp = rsp + 1;
-        _rstkW = 1;
-        _rstkD = {pc_plus_1[14:0], 1'b0};
-      end else begin
-        _rsp = rsp;
-        _rstkW = 0;
-        _rstkD = _pc;
-      end
-    end
-  end
-
-  always @*
-  begin
-    if (sys_rst_i)
-      _pc = pc;
-    else
-      if ((insn[15:13] == 3'b000) |
-          ((insn[15:13] == 3'b001) & (|st0 == 0)) |
-          (insn[15:13] == 3'b010))
-        _pc = insn[12:0];
-      else if (is_alu & insn[12])
-        _pc = rst0[15:1];
-      else
-        _pc = pc_plus_1;
-  end
-
-  always @(posedge sys_clk_i)
-  begin
-    if (sys_rst_i) begin
-      pc <= 0;
-      dsp <= 0;
-      st0 <= 0;
-      rsp <= 0;
-    end else begin
-      dsp <= _dsp;
-      pc <= _pc;
-      st0 <= _st0;
-      rsp <= _rsp;
-    end
-  end
-
-endmodule // j1
diff --git a/lib/CPUs/J1/src/core/j1.vhd b/lib/CPUs/J1/src/core/j1.vhd
deleted file mode 100644
index d5c9f14..0000000
--- a/lib/CPUs/J1/src/core/j1.vhd
+++ /dev/null
@@ -1,282 +0,0 @@
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-entity j1 is
-	Generic
-	(
-		R_STACK_SIZE			: natural := 32;
-		D_STACK_SIZE			: natural := 32
-
-	);
-	Port
-	(
-		sys_clk_i	: in  std_logic;
-		sys_rst_i	: in  std_logic;
-		io_din		: in  unsigned(15 downto 0);
-		io_rd		: out std_logic;
-		io_wr		: out std_logic;
-		io_addr		: out unsigned(15 downto 0);
-		io_dout		: out unsigned(15 downto 0);
-		inst_din	: in  unsigned(15 downto 0);
-		inst_addr	: out unsigned(12 downto 0);
-		data_addr	: out unsigned(12 downto 0);
-		data_we		: out std_logic;
-		data_en		: out std_logic;
-		data_din	: in  unsigned(15 downto 0);
-		data_dout	: out unsigned(15 downto 0)
-		
-	);
-end j1;
-
-architecture behave of j1 is
-
-signal insn				: unsigned(15 downto 0);
-signal immediate		: unsigned(15 downto 0);
-signal ramrd			: unsigned(15 downto 0);
-	
-signal dsp				: unsigned(4 downto 0);		-- Data stack pointer (register)
-signal dsp2				: unsigned(4 downto 0);		-- register
-signal st0				: unsigned(15 downto 0);	-- Return stack pointer (register)
-signal st02				: unsigned(15 downto 0);	-- register
-
-signal dstkW2			: std_logic;				-- D stack write
-
-signal pc				: unsigned(12 downto 0);	-- register
-signal pc2				: unsigned(12 downto 0);	-- register
-signal rsp				: unsigned(4 downto 0);		-- register
-signal rsp2				: unsigned(4 downto 0);		-- register
-
-signal rstkW2			: std_logic;				-- register
-signal rstkD2			: unsigned(15 downto 0);	-- register
-signal ramWE2			: std_logic;				-- RAM write enable
-
-signal pc_plus_1		: unsigned(15 downto 0);
-
-type stack_t is array (integer range <>) of unsigned(15 downto 0);
-
-signal dstack			: stack_t(0 to D_STACK_SIZE-1);	-- register
-signal rstack			: stack_t(0 to R_STACK_SIZE-1);	-- register
-
-signal st1				: unsigned(15 downto 0);
-signal rst0				: unsigned(15 downto 0);
-
-signal st0sel			: unsigned(3 downto 0);
-
-signal is_alu			: BOOLEAN;
-signal is_lit			: BOOLEAN;
-
-signal dd				: unsigned(1 downto 0);		-- D stack delta
-signal rd				: unsigned(1 downto 0);		-- R stack delta
-
-signal stack_ram_en		: std_logic;				-- helper for RAM R/W
-signal stack_ram_we		: std_logic;				-- helper for RAM R/W
-
-begin
-
--- LINE 25:
-pc_plus_1	<= ("000" & pc)  + 1;
-
--- LINE 37:
-st1			<= dstack(to_integer(dsp));
-rst0		<= rstack(to_integer(rsp));
-immediate	<= '1' & insn(14 downto 0);
-
--- LINE 112:
-is_alu		<= (insn(15 downto 13) = "011");
-is_lit		<= (insn(15) = '1');
-
-
--- LINE 115:
-io_rd		<= '1' when (is_alu and (insn(11 downto 8) = X"C")) else '0';
-io_wr		<= ramWE2;
-io_addr		<= st0;
-io_dout		<= st1;
-ramWE2		<= '1' when (is_alu and (insn(5) = '1')) else '0';
-dstkW2		<= '1' when (is_lit or (is_alu and insn(7) = '1')) else '0';
-dd			<= insn(1 downto 0);	
-rd			<= insn(3 downto 2);
-
-
--- LINE 27:
--- The D and R stacks
-proc_d_and_r_stack:
-process(sys_clk_i)
-begin
-	if rising_edge(sys_clk_i) then
-		if dstkW2 = '1' then
-			dstack(to_integer(dsp2)) <= st0;
-		end if;
-		if rstkW2 = '1' then
-			rstack(to_integer(rsp2)) <= rstkD2;
-		end if;
-		
-	end if;
-end process;
-
-
--- LINE 40:
--- st0sel is the ALU operation.  For branch and call the operation
--- is T, for 0branch it is N.  For ALU ops it is loaded from the instruction
--- field.
-
-proc_aluop_sel:
-process(insn)
-begin
-
-	
-	case insn(14 downto 13) is
-	
-	when "00" => st0sel <= "0000";
-	when "10" => st0sel <= "0000";
-	when "01" => st0sel <= "0001";
-	when "11" => st0sel <= insn(11 downto 8);
-	when others => st0sel <= "XXXX";
-		
-	end case;
-end process;
-
-
--- LINE 55:
--- define RAMS outside this module
-insn		<= inst_din;
-inst_addr	<= pc2(12 downto 0);
-data_en		<= not (st02(15) or st02(14));
-data_we		<= ramWE2 and not (st02(15) or st02(14));
-ramrd		<= data_din;
-data_dout	<= st1;
-data_addr	<= st02(13 downto 1);
-
-
--- LINE 85:
--- Compute the new value of T.
-proc_alu:
-process(insn, immediate, st0sel, st0, st1, rst0, rsp, dsp)
-begin
-
-	if insn(15) = '1' then
-		st02 <= immediate;
-	else
-		case st0sel is
-		
-		when "0000" => st02 <= st0;
-		when "0001" => st02 <= st1;
-		when "0010" => st02 <= st0 + st1;
-		when "0011" => st02 <= st0 and st1;
-		when "0100" => st02 <= st0 or st1;
-		when "0101" => st02 <= st0 xor st1;
-		when "0110" => st02 <= not st0;
-		when "0111" => 
-			if st1 = st0 then
-				st02 <= X"FFFF";
-			else
-				st02 <= X"0000";
-			end if;
-		
-		when "1000" =>
-			if signed(st1) < signed(st0) then
-				st02 <= X"FFFF";
-			else
-				st02 <= X"0000";
-			end if;
-			
-		when "1001" => st02 <= st1 srl to_integer(st0(3 downto 0));
-		when "1010" => st02 <= st0 - 1;
-		when "1011" => st02 <= rst0;
-		when "1100" =>
-			if st0(15) = '1' or st0(14) = '1' then	-- LINE 104: ????
-				st02 <= io_din;
-			else
-				st02 <= ramrd;
-			end if;
-	
-		when "1101" => st02 <= st1 sll to_integer(st0(3 downto 0));
-		when "1110" => st02 <= "000" & rsp & "000" & dsp; -- LINE 106: ????
-		when "1111" => 
-			if st1 < st0 then
-				st02 <= X"FFFF";
-			else
-				st02 <= X"0000";
-			end if;
-		when others => st02 <= "XXXXXXXXXXXXXXXX";
-		
-		end case;
-	end if;
-end process;
-
--- LINE 126:
-proc_stack_ctrl:
-process(is_lit, is_alu, pc2, dd, rd, insn, st0, pc_plus_1, rsp, dsp)
-begin
-	if is_lit then			-- literal
-		dsp2 <= dsp + 1;
-		rsp2 <= rsp;
-		rstkW2 <= '0';
-		rstkD2 <= "000" & pc2;
-	elsif is_alu then
-		dsp2 <= dsp + (dd(1) & dd(1) & dd(1) & dd);
-		rsp2 <= rsp + (rd(1) & rd(1) & rd(1) & rd);
-		rstkW2 <= insn(6);
-		rstkD2 <= st0;
-	else					-- jump/call
-		-- predicated jump is like DROP
-		if insn(15 downto 13) = "001" then
-			dsp2	<= dsp - 1;
-		else
-			dsp2	<= dsp;		-- *default
-		end if;
-		if insn(15 downto 13) = "010" then	-- call
-			rsp2 <= rsp + 1;
-			rstkW2 <= '1';
-			rstkD2 <= pc_plus_1(14 downto 0) & '0';
-		else
-			rsp2 <= rsp;				-- *default
-			rstkW2 <= '0';				-- *default
-			rstkD2 <= "000" & pc2;		-- *default
-		end if;
-		
-	end if;
-end process;
-
--- LINE 157:
-proc_pc:
-process(sys_rst_i, is_alu, insn, pc, st0, rst0, pc_plus_1)
-begin
-
-	if sys_rst_i = '1' then
-		pc2 <= pc;
-	else
-		if  ((insn(15 downto 13) = "000") 
-		or  ((insn(15 downto 13) = "001")
-		and (st0 = X"0000")) 
-		or  (insn(15 downto 13) = "010")) then
-			pc2 <= insn(12 downto 0);
-		elsif is_alu and (insn(12) = '1') then	-- return
-			pc2 <= rst0(13 downto 1);		-- LINE 167: ????
-		else
-			pc2	<= pc_plus_1(12 downto 0);	-- LINE 169: truncation ????
-		end if;
-	end if;
-end process;
-
--- LINE 172:
-proc_next:
-process(sys_clk_i)
-begin
-
-	if rising_edge(sys_clk_i) then
-		if sys_rst_i = '1' then
-			pc	<= (others => '0');
-			dsp	<= (others => '0');
-			st0	<= (others => '0');
-			rsp	<= (others => '0');
-		else
-			dsp <= dsp2;
-			pc  <= pc2;
-			st0 <= st02;
-			rsp <= rsp2;
-		end if;
-	end if;
-end process;
-
-end behave;
diff --git a/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd b/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd
deleted file mode 100644
index 23d8118..0000000
--- a/lib/CPUs/J1/src/core/ram_2c_2r_2w.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
---------------------------------------------------------------------------
--- Project: Generic RAM. Infers BlockRAM for Xilinx
--- This file: On-chip RAM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity ram_2c_2r_2w is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end ram_2c_2r_2w;
-
-architecture Behavioral of ram_2c_2r_2w is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clka)
-begin
-if clka'event and clka = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clkb)
-begin
-if clkb'event and clkb = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/CPUs/J1/src/tb_j1.vhd b/lib/CPUs/J1/src/tb_j1.vhd
deleted file mode 100644
index 8aa4c3c..0000000
--- a/lib/CPUs/J1/src/tb_j1.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for embedded cpu with rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-
-ENTITY tb_j1 IS
-END tb_j1;
-
-ARCHITECTURE behavior OF tb_j1 IS 
-
-	constant CLK_PERIOD : time := 10 ns;
-	
-	-- Inputs
-	signal sys_clk_i	: std_logic := '0';
-	signal sys_rst_i	: std_logic := '1';
-	signal io_din		: unsigned(15 downto 0) := (others => '0');
-	signal inst_din		: unsigned(15 downto 0) := (others => '0');
-	signal data_din		: unsigned(15 downto 0) := (others => '0');
-
-	-- Outputs
-	signal io_rd		: std_logic;
-	signal io_wr		: std_logic;
-	signal io_addr		: unsigned(15 downto 0);
-	signal io_dout		: unsigned(15 downto 0);
-	signal data_dout	: unsigned(15 downto 0);
-	signal inst_addr	: unsigned(12 downto 0);
-	signal data_addr	: unsigned(12 downto 0);
-	signal data_we		: std_logic;
-	signal data_en		: std_logic;
-
-	type rom_t is array (integer range <>) of unsigned(15 downto 0);
-
-	signal rom : rom_t(0 to 15) := 
-	(
-		X"8123",	-- 0000
-		X"0002",	-- 0001
-		X"0005",	-- 0002
-		X"8456",	-- 0003
-		X"4008",	-- 0004
-		X"0003",	-- 0005
-		X"0000",	-- 0006
-		X"0000",	-- 0007
-		X"8456",	-- 0008
-		X"8451",	-- 0009
-		X"7000",	-- 000A
-		X"0000",	-- 000B
-		X"0000",	-- 000C
-		X"0000",	-- 000D
-		X"0000",	-- 000E
-		X"0000"		-- 000F
-	);
-
-BEGIN
-
-	-- Instruction rom
-process(sys_clk_i)
-begin
-	if rising_edge(sys_clk_i) then
-		inst_din	<= rom(to_integer(inst_addr(3 downto 0)));
-	end if;
-end process;
-
-uut: entity work.j1
-	PORT MAP
-	(
-		sys_clk_i		=> sys_clk_i,
-		sys_rst_i		=> sys_rst_i,
-		io_din			=> io_din,
-		io_rd			=> io_rd,
-		io_wr			=> io_wr,
-		io_addr			=> io_addr,
-		inst_din		=> inst_din,
-		inst_addr		=> inst_addr,
-		data_addr		=> data_addr,
-		data_we			=> data_we,
-		data_en			=> data_en,
-		data_din		=> data_din,
-		data_dout		=> data_dout
-	);
-
-inst_ram: entity work.ram_2c_2r_2w
-	GENERIC MAP
-	(
-		addr_width	=> 13,
-		data_width	=> 16
-	)
-	PORT MAP(
-		clka		=> sys_clk_i,
-		clkb		=> sys_clk_i,
-		en_a		=> '1',
-		en_b		=> data_en,
-		we_a		=> '0',
-		we_b		=> data_we,
-		addr_a		=> (others => '0'), --inst_addr
-		addr_b		=> data_addr,
-		din_a		=> (others => '0'),
-		din_b		=> data_dout,
-		dout_a		=> open, -- inst_din
-		dout_b		=> data_din
-	);
-
-	
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		sys_clk_i <= not sys_clk_i;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		sys_rst_i <= '0';
-		wait for 2*CLK_PERIOD;
-	
-	
-		wait for 1000*CLK_PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-end behavior;
diff --git a/lib/CPUs/JCpu/asm/dctest.jsm b/lib/CPUs/JCpu/asm/dctest.jsm
deleted file mode 100644
index 38d5947..0000000
--- a/lib/CPUs/JCpu/asm/dctest.jsm
+++ /dev/null
@@ -1,56 +0,0 @@
-; -------------------------------------------------	
-;			PROJECT	"dctest"
-; -------------------------------------------------	
-
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------	
-				xmem
-				org		4
-konst:			dc		0x01, 0x12,"A"
-gap1:			db		16
-mesg:			dc		"Hallo", 13,0x0A, 0
-name:			dc		"Jens",0
-msg1:			dc		"Welcome to JASM CPU",0
-msg2:			dc		"Ready",0
-msg3:			dc		"Testing",0
-msg4:			dc		"Passed",0
-msg5:			dc		"Error",0
-crlf:			dc		0x0D, 0x0A
-
-				org		0x00
-shit:			db		4	
-
-				cmem	0
-				org		8
-cram1:			db		16
-cram2:			db		6
-cram3:			db		4
-
-				cmem	1
-cram4:			db		8
-cram5:			db		8
-				org		0x20
-cram6:			db		8
-cram7:			db		4
-
-reg_revision:	equ		0x00			
-reg_testid:		equ		0x01			
-
-; -------------------------------------------------	
-				code
-				org		0x000
-reset:			jmp		start
-
-; -------------------------------------------------	
-				org		0x001
-int_vec:		jmp		isr
-
-; -------------------------------------------------	
-				org		0x010
-			
-start:			jmp		start
-
-; -------------------------------------------------	
-isr:			reti
-
diff --git a/lib/CPUs/JCpu/asm/dctest.tcl b/lib/CPUs/JCpu/asm/dctest.tcl
deleted file mode 100644
index ca88834..0000000
--- a/lib/CPUs/JCpu/asm/dctest.tcl
+++ /dev/null
@@ -1,212 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from dctest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x010
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
-
-# 0x001: JMP 0x011
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011"
-
-# 0x002:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
-
-# 0x003:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
-
-# 0x004:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
-
-# 0x005:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
-
-# 0x006:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
-
-# 0x007:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
-
-# 0x008:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
-
-# 0x009:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
-
-# 0x00A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
-
-# 0x00B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
-
-# 0x00C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
-
-# 0x00D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
-
-# 0x00E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
-
-# 0x00F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
-
-# 0x010: JMP 0x010
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010"
-
-# 0x011: RETI
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000"
-
-# Assembled from dctest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A"
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/lib/CPUs/JCpu/asm/itest.jsm b/lib/CPUs/JCpu/asm/itest.jsm
deleted file mode 100644
index 9666253..0000000
--- a/lib/CPUs/JCpu/asm/itest.jsm
+++ /dev/null
@@ -1,858 +0,0 @@
-; -------------------------------------------------	
-;			PROJECT	"itest"
-; -------------------------------------------------	
-
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------	
-				xmem
-msg:			dc		"Hallo", 0
-xram:			db		256
-
-				cmem	0
-cram:			db		256
-
-reg_revision:	equ		0x00			
-reg_testid:		equ		0x01			
-
-; -------------------------------------------------	
-			code
-			org		0x000
-reset:		jmp		start
-
-; -------------------------------------------------	
-			org		0x001
-int_vec:	jmp		isr
-
-; -------------------------------------------------	
-			org		0x010
-			
-start:		call	init
-			cin		R0, (cpu_revision)
-			xout	(reg_revision), R0
-			
-			; Test 0
-			call	test0
-			
-			; Test 1
-			mov		R0, 1
-			xout	(reg_testid), R0
-			call	test1
-			
-			; Test 2
-			mov		R0, 2
-			xout	(reg_testid), R0
-			call	test2
-
-			; Test 3
-			mov		R0, 3
-			xout	(reg_testid), R0
-			call	test3
-
-			; Test 4
-			mov		R0, 4
-			xout	(reg_testid), R0
-			call	test4
-
-			; Test 5
-			mov		R0, 5
-			xout	(reg_testid), R0
-			call	test5
-
-			; Test 6
-			mov		R0, 6
-			xout	(reg_testid), R0
-			call	test6
-
-			; Test 7
-			mov		R0, 7
-			xout	(reg_testid), R0
-			call	test7
-
-			; Test 8
-			mov		R0, 8
-			xout	(reg_testid), R0
-			call	test8
-
-			; Test 9
-			mov		R0, 9
-			xout	(reg_testid), R0
-			call	test9
-			
-			; Test 10
-			mov		R0, 10
-			xout	(reg_testid), R0
-			call	test10
-
-			; Test 11
-			mov		R0, 11
-			xout	(reg_testid), R0
-			call	test11
-
-			; Test 12
-			mov		R0, 12
-			xout	(reg_testid), R0
-			call	test12
-
-			; End of test
-			mov		R0, 0xFF
-			xout	(reg_testid), R0
-			
-			jmp		ok
-
-; -------------------------------------------------	
-init:		mov		R0, 0
-			mov		R1, 0
-			mov		R2, 0
-			mov		R3, 0
-			mov		R4, 0
-			mov		R5, 0
-			mov		R6, 0
-			mov		R7, 0
-			mov		R8, 0
-			mov		R9, 0
-			mov		R10, 0
-			mov		R11, 0
-			mov		R12, 0
-			mov		R13, 0
-			mov		R14, 0
-			mov		R15, 0
-			ret
-
-; -------------------------------------------------	
-; MOV|R|K
-; MOV|R|R
-test0:		mov		R0, 0x10
-			cmp		R0, 0x10
-			jne		error
-			add		R0, 1
-
-			mov		R1, R0
-			cmp		R1, 0x11
-			jne		error
-			add		R1, 1
-
-			mov		R2, R1
-			cmp		R2, 0x12
-			jne		error
-			add		R2, 1
-
-			mov		R3, R2
-			cmp		R3, 0x13
-			jne		error
-			add		R3, 1
-
-			mov		R4, R3
-			cmp		R4, 0x14
-			jne		error
-			add		R4, 1
-
-			mov		R5, R4
-			cmp		R5, 0x15
-			jne		error
-			add		R5, 1
-
-			mov		R6, R5
-			cmp		R6, 0x16
-			jne		error
-			add		R6, 1
-
-			mov		R7, R6
-			cmp		R7, 0x17
-			jne		error
-			add		R7, 1
-
-			mov		R8, R7
-			cmp		R8, 0x18
-			jne		error
-			add		R8, 1
-
-			mov		R9, R8
-			cmp		R9, 0x19
-			jne		error
-			add		R9, 1
-
-			mov		R10, R9
-			cmp		R10, 0x1A
-			jne		error
-			add		R10, 1
-
-			mov		R11, R10
-			cmp		R11, 0x1B
-			jne		error
-			add		R11, 1
-
-			mov		R12, R11
-			cmp		R12, 0x1C
-			jne		error
-			add		R12, 1
-
-			mov		R13, R12
-			cmp		R13, 0x1D
-			jne		error
-			add		R13, 1
-
-			mov		R14, R13
-			cmp		R14, 0x1E
-			jne		error
-			add		R14, 1
-
-			mov		R15, R14
-			cmp		R15, 0x1F
-			jne		error
-			add		R15, 1
-			
-			ret
-
-; -------------------------------------------------	
-; Instruction test
-; TST|R
-; CMP|R|K
-; JNZ|K
-; JC|K
-; JNE|K
-; JLT|K
-; JGT|K
-; JLE|K
-; JGE|K
-; JMP|K
-test1:		mov		R0, 0			; R0 <= 0
-			tst		R0
-			jnz		error	
-			jc		error	
-			cmp		R0, 0	
-			jne		error	
-			jlt		error	
-			jgt		error
-			jle		t1_ok10
-			jmp		error
-
-t1_ok10:	jeq		t1_ok20
-			jmp		error
-			
-t1_ok20:	jge		t1_ok30
-			jmp		error
-			
-t1_ok30:	cmp		R0, 0x55
-			jeq		error	
-			jlt		t1_ok40
-			jmp		error
-			
-t1_ok40:	jle		t1_ok50
-			jmp		error
-			
-t1_ok50:	jge		error
-			jgt		error
-			
-			mov		R0, 0x55		; R0 <= 0xAA
-			tst		R0
-			jz		error	
-			jc		error	
-			
-			cmp		R0, 0xAA
-			jeq		error	
-			jne		t1_ok60
-			jmp		error
-
-t1_ok60:	jlt		t1_ok70	
-			jmp		error
-
-t1_ok70:	jle		t1_ok80
-			jmp		error
-
-t1_ok80:	jgt		error
-
-			cmp		R0, 0x55
-			jeq		t1_ok90
-			jmp		error
-			
-t1_ok90:	jne		error
-			jlt		error
-			
-			jle		t1_ok100
-			jmp		error
-
-t1_ok100:	jgt		error
-			jge		t1_ok110
-			jmp		error
-			
-t1_ok110:	mov		R0, 0xAA		; R0 <= 0x55
-			tst		R0
-			jz		error	
-			jc		error	
-			
-			cmp		R0, 0x55
-			jeq		error	
-			jne		t1_ok120
-			jmp		error
-
-t1_ok120:	jgt		t1_ok130	
-			jmp		error
-
-t1_ok130:	jge		t1_ok140
-			jmp		error
-
-t1_ok140:	jlt		error
-			jle		error
-
-			ret
-			
-; -------------------------------------------------	
-; ADD|R|K
-; ADDC|R|K
-; ToDo: ADD|R|R
-; ToDo: ADDC|R|R
-; CMP|R|R
-test2:		mov		R0, 0
-			mov		R1, 0
-			mov		R2, R0
-			mov		R3, R1
-
-t2_loop:	add		R0, 0x01
-			addc	R1, 0x00
-			add		R2, 1
-			cmp		R2, 0
-			jne		t2_L1
-			add		R3, 1
-			cmp		R3, 0x02
-t2_L1:		jne		t2_loop
-			cmp		R0, R2
-			jne		error
-			cmp		R1, R3
-			jne		error
-			mov		R0, 0
-
-			ret
-
-; -------------------------------------------------	
-; SUB|R|K
-; SUBC|R|K
-; ToDo: SUB|R|R
-; ToDo: SUBC|R|R
-; CMP|R|R
-test3:		mov		R0, 0x00
-			mov		R1, 0x03
-			mov		R2, R0
-			mov		R3, R1
-
-t3_loop:	sub		R0, 0x01
-			subc	R1, 0x00
-			sub		R2, 1
-			cmp		R2, 0xFF
-			jne		t3_L1
-			sub		R3, 1
-			cmp		R3, 0x00
-t3_L1:		jne		t3_loop
-			cmp		R0, R2
-			jne		error
-			cmp		R1, R3
-			jne		error
-			mov		R0, 0
-
-			ret
-; -------------------------------------------------	
-; SUB|K|R
-; SUB|R|R
-; SUBC|R|R
-; SUBC|K|R
-; CMP|R|R
-test4:		mov		R0, 0x03
-			mov		R1, 0x05
-			sub		0x05, R0
-			sub		R1, 0x03
-			cmp		R0, R1
-			jne		error
-			mov		R0, 0x03
-			mov		R1, 0x05
-			sub		R0, R1
-			subc	0, R0
-			cmp		R0, 0x01
-			jne		error
-			add		R0, 0	
-			subc	R1, R0
-			cmp		R1, 0x04
-			jne		error
-			mov		R0, 0
-
-			ret
-						
-; -------------------------------------------------	
-; MOVC|R|Ri
-; MOVC|R|Ki
-; MOVC|Ri|R
-; MOVC|Ri|K
-; MOVC|Ki|R
-test5:		mov		R0, 1
-			movc	(cram+0x5A), R0
-			dec		R0			
-			movc	(cram+0), R0
-			movc	R1, (cram+0x5A)
-			movc	(R1), 0xA5
-			movc	R0, (R1)
-			movc	R1, (R1)
-			add		R1, 0xFF-0xA5
-			movc	R0, (R1)
-t5_loop1:	movc	(R0), R0
-			movc	R2, (R0)
-			cmp		R2, R0
-			jne		error
-			movc	(R2), R1
-			movc	R2, (R2)
-			cmp		R2, R1
-			jne		error
-			dec		R1
-			inc		R0
-			jnz		t5_loop1
-			
-			ret
-
-; -------------------------------------------------	
-; MOVX|R|Ri
-; MOVX|R|Ki
-; MOVX|Ri|R
-; MOVX|Ri|K
-; MOVX|Ki|R
-test6:		mov		R0, 1
-			movx	(xram+0x5A), R0
-			dec		R0			
-			movx	(xram+0), R0
-			movx	R1, (xram+0x5A)
-			movx	(R1), 0xA5
-			movx	R0, (R1)
-			movx	R1, (R1)
-			add		R1, 0xFF-0xA5
-			movx	R0, (R1)
-t6_loop1:	movx	(R0), R0
-			movx	R2, (R0)
-			cmp		R2, R0
-			jne		error
-			movx	(R2), R1
-			movx	R2, (R2)
-			cmp		R2, R1
-			jne		error
-			dec		R1
-			inc		R0
-			jnz		t6_loop1
-			
-			ret
-
-; -------------------------------------------------	
-; PUSH|R
-; POP|R
-test7:		mov		R0, 0xAA
-			mov		R1, 0
-t7_loop1:	push	R0
-			inc		R0
-			dec		R1
-			jnz		t7_loop1
-t7_loop2:	pop		R0
-			dec		R1
-			jnz		t7_loop2
-			cmp		R0, 0xAA
-			jne		error
-			
-			ret
-
-; -------------------------------------------------	
-; JMP|K
-; CALL|K
-; RET
-test8:		mov		R0, 0x55
-			push	R0
-			mov		R0, 0
-			mov		R1, 0xFF
-			call	t8_rec
-			pop		R0
-			cmp		R0, 0x55
-			jne		error
-
-			; Stack manipulations 1
-			mov		R0, return1'high
-			mov		R1, return1'low
-			cout	(cpu_stack_high), R0
-			push	R1
-
-			mov		R0, init'high
-			mov		R1, init'low
-			cout	(cpu_stack_high), R0
-			push	R1
-			ret
-			
-			; Stack manipulations 2
-return1:	mov		R0, return2'high
-			mov		R1, return2'low
-			cout	(cpu_stack_high), R0
-			push	R1
-
-			mov		R0, init'high
-			mov		R1, init'low
-			cout	(cpu_stack_high), R0
-			push	R1
-return2:	ret
-
-t8_rec:		cmp		R0, R1
-			jeq		ex_t8_rec
-			inc		R0
-			jmp		t8_rstub
-ex_t8_rec:	dec		R0
-			dec		R1
-			ret
-
-t8_rstub:	call	t8_rec
-			jmp		ex_t8_rec
-
-; -------------------------------------------------	
-; SWAP|R
-; SHL|R  
-; SHR|R  
-; ROL|R  
-; ROR|R  
-; ROLC|R 
-; RORC|R 
-test9:		mov		R0, 0xA5	; SWAP test
-			mov		R1, 0x5A
-			swap	R0
-			cmp		R0, 0x5A
-			jne		error
-			swap	R0
-			cmp		R0, 0xA5
-			jne		error
-			mov		R0, 0xD2
-			swap	R0
-			cmp		R0, 0x2D
-			jne		error
-			swap	R1
-			cmp		R0, 0x2D
-			jne		error
-			cmp		R1, 0xA5
-			jne		error
-			
-			mov		R0, 0x2D
-			shl		R0			; SHL test
-			cmp		R0, 0x5A
-			jne		error
-			shl		R0
-			cmp		R0, 0xB4
-			jne		error
-			shl		R0
-			cmp		R0, 0x68
-			jne		error
-			shl		R0
-			cmp		R0, 0xD0
-			jne		error
-			shl		R0
-			cmp		R0, 0xA0
-			jne		error
-			shl		R0
-			cmp		R0, 0x40
-			jne		error
-			shl		R0
-			cmp		R0, 0x80
-			jne		error
-			shl		R0
-			cmp		R0, 0x00
-			jne		error
-
-			mov		R1, 0x84
-			shr		R1			; SHR test
-			cmp		R1, 0x42
-			jne		error
-			shr		R1
-			cmp		R1, 0x21
-			jne		error
-			shr		R1
-			cmp		R1, 0x10
-			jne		error
-			shr		R1
-			cmp		R1, 0x08
-			jne		error
-			shr		R1
-			cmp		R1, 0x04
-			jne		error
-			shr		R1
-			cmp		R1, 0x02
-			jne		error
-			shr		R1
-			cmp		R1, 0x01
-			jne		error
-			shr		R1
-			cmp		R1, 0x00
-			jne		error
-
-			mov		R0, 0xC5	; ROL test
-			rol		R0			
-			cmp		R0, 0x8B
-			jne		error
-			rol		R0			
-			cmp		R0, 0x17
-			jne		error
-			rol		R0			
-			cmp		R0, 0x2E
-			jne		error
-			rol		R0			
-			cmp		R0, 0x5C
-			jne		error
-			rol		R0			
-			cmp		R0, 0xB8
-			jne		error
-			rol		R0			
-			cmp		R0, 0x71
-			jne		error
-			rol		R0			
-			cmp		R0, 0xE2
-			jne		error
-			rol		R0			
-			cmp		R0, 0xC5
-			jne		error
-
-			mov		R1, 0x63	; ROR test
-			ror		R1
-			cmp		R1, 0xB1
-			jne		error
-			ror		R1
-			cmp		R1, 0xD8
-			jne		error
-			ror		R1
-			cmp		R1, 0x6C
-			jne		error
-			ror		R1
-			cmp		R1, 0x36
-			jne		error
-			ror		R1
-			cmp		R1, 0x1B
-			jne		error
-			ror		R1
-			cmp		R1, 0x8D
-			jne		error
-			ror		R1
-			cmp		R1, 0xC6
-			jne		error
-			ror		R1
-			cmp		R1, 0x63
-			jne		error
-
-
-			xor		R0, R0		; ROLC generate
-			mov		R0, 0xC5	
-			rolc	R0		
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-			push	R0
-			rolc	R0			
-
-			cmp		R0, 0xC5	; ROLC verify
-			jne		error
-			pop		R0
-			cmp		R0, 0x62
-			jne		error
-			pop		R0
-			cmp		R0, 0xB1
-			jne		error
-			pop		R0
-			cmp		R0, 0x58
-			jne		error
-			pop		R0
-			cmp		R0, 0xAC
-			jne		error
-			pop		R0
-			cmp		R0, 0x56
-			jne		error
-			pop		R0
-			cmp		R0, 0x2B
-			jne		error
-			pop		R0
-			cmp		R0, 0x15
-			jne		error
-			pop		R0
-			cmp		R0, 0x8A
-			jne		error
-
-			xor		R1, R1		; RORC generate
-			mov		R1, 0x63
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-			push	R1
-			rorc	R1
-
-			cmp		R1, 0x63	; RORC verify
-			jne		error
-			pop		R1
-			cmp		R1, 0xC6
-			jne		error
-			pop		R1
-			cmp		R1, 0x8C
-			jne		error
-			pop		R1
-			cmp		R1, 0x19
-			jne		error
-			pop		R1
-			cmp		R1, 0x33
-			jne		error
-			pop		R1
-			cmp		R1, 0x66
-			jne		error
-			pop		R1
-			cmp		R1, 0xCC
-			jne		error
-			pop		R1
-			cmp		R1, 0x98
-			jne		error
-			pop		R1
-			cmp		R1, 0x31
-			jne		error
-
-			ret
-			
-; -------------------------------------------------
-; AND|R|R
-; AND|R|K
-; OR|R|R 
-; OR|R|K 
-; XOR|R|R
-; XOR|R|K
-test10:		mov		R0, 0xA5	; AND
-			swap	R0
-			push	R0
-			and		R0, 0x0F
-			cmp		R0, 0x0A
-			jne		error
-			pop		R0
-			push	R0
-			and		R0, 0x0F
-			cmp		R0, 0x0A
-			pop		R1
-			jne		error
-			swap	R1
-			mov		R2, 0x0F
-			and		R1, R2
-			cmp		R1, 0x05
-			jne		error
-			
-			mov		R0, 0x05	; OR
-			mov		R2, 0xA0
-			swap	R0
-			or		R2, R0
-			cmp		R2, 0xF0
-			jne		error
-			swap	R0
-			or		R0, 0x50
-			cmp		R0, 0x55
-			jne		error
-			
-			mov		R1, 0x01
-			mov		R0, 0x01
-			xor		R0, 0x01
-			jnz		error
-			xor		R0, R1
-			cmp		R0, 0x01
-			jne		error
-			
-			ret
-			
-; -------------------------------------------------	
-test11:
-			mov		R0, 0x03
-			cout	(cpu_int_ctrl), R0
-			
-			xin		R0, (2)
-			or		R0, 1
-			xout	(2), R0
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			xin		R0, (2)
-			and		R0, 0xFE
-			xout	(2), R0
-			nop
-			nop
-			nop
-			nop
-			
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			cin		R0, (cpu_int_ctrl)
-			or		R0, 0x80
-			cout	(cpu_int_ctrl), R0
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			nop
-			ret
-
-; -------------------------------------------------	
-; Tests clrc, setc
-test12:		sub		R0, 0
-			jc		error
-			setc
-			jnc		error
-			nop
-			sub		R0, 0
-			jc		error
-			
-			mov		R0, 0
-			clrc
-			jc		error
-			setc
-			jnc		error
-			nop
-			clrc
-			jc		error
-			ret
-
-; -------------------------------------------------	
-isr:		inc		R14
-			reti
-
-; -------------------------------------------------	
-			org		0x3FF
-error:		jmp		error
-
-; -------------------------------------------------	
-			org		0x2FF
-ok:			jmp		ok
-
-; -------------------------------------------------	
-			
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/asm/itest.tcl b/lib/CPUs/JCpu/asm/itest.tcl
deleted file mode 100644
index 3724ca6..0000000
--- a/lib/CPUs/JCpu/asm/itest.tcl
+++ /dev/null
@@ -1,3407 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from itest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x010
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010"
-
-# 0x001: JMP 0x288
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130288"
-
-# 0x002:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000"
-
-# 0x003:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000"
-
-# 0x004:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000"
-
-# 0x005:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
-
-# 0x006:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000"
-
-# 0x007:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
-
-# 0x008:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000"
-
-# 0x009:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
-
-# 0x00A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000"
-
-# 0x00B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
-
-# 0x00C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000"
-
-# 0x00D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
-
-# 0x00E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000"
-
-# 0x00F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
-
-# 0x010: CALL 0x03B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103B03B"
-
-# 0x011: CIN R00, (0x00)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01129000"
-
-# 0x012: XOUT (0x00), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01224000"
-
-# 0x013: CALL 0x04C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B04C"
-
-# 0x014: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403010"
-
-# 0x015: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01524010"
-
-# 0x016: CALL 0x08D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163B08D"
-
-# 0x017: MOV R00, 0x02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01703020"
-
-# 0x018: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010"
-
-# 0x019: CALL 0x0C9
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193B0C9"
-
-# 0x01A: MOV R00, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03030"
-
-# 0x01B: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B24010"
-
-# 0x01C: CALL 0x0DB
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C3B0DB"
-
-# 0x01D: MOV R00, 0x04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D03040"
-
-# 0x01E: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E24010"
-
-# 0x01F: CALL 0x0ED
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B0ED"
-
-# 0x020: MOV R00, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003050"
-
-# 0x021: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124010"
-
-# 0x022: CALL 0x0FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0223B0FF"
-
-# 0x023: MOV R00, 0x06
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02303060"
-
-# 0x024: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02424010"
-
-# 0x025: CALL 0x115
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B115"
-
-# 0x026: MOV R00, 0x07
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02603070"
-
-# 0x027: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02724010"
-
-# 0x028: CALL 0x12B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283B12B"
-
-# 0x029: MOV R00, 0x08
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02903080"
-
-# 0x02A: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A24010"
-
-# 0x02B: CALL 0x137
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B3B137"
-
-# 0x02C: MOV R00, 0x09
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03090"
-
-# 0x02D: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D24010"
-
-# 0x02E: CALL 0x15A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B15A"
-
-# 0x02F: MOV R00, 0x0A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F030A0"
-
-# 0x030: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03024010"
-
-# 0x031: CALL 0x22A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0313B22A"
-
-# 0x032: MOV R00, 0x0B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "032030B0"
-
-# 0x033: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03324010"
-
-# 0x034: CALL 0x24D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0343B24D"
-
-# 0x035: MOV R00, 0x0C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "035030C0"
-
-# 0x036: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010"
-
-# 0x037: CALL 0x278
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B278"
-
-# 0x038: MOV R00, 0xFF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803FF0"
-
-# 0x039: XOUT (0x01), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03924010"
-
-# 0x03A: JMP 0x2FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A302FF"
-
-# 0x03B: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B03000"
-
-# 0x03C: MOV R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C03001"
-
-# 0x03D: MOV R02, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03002"
-
-# 0x03E: MOV R03, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E03003"
-
-# 0x03F: MOV R04, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F03004"
-
-# 0x040: MOV R05, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04003005"
-
-# 0x041: MOV R06, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103006"
-
-# 0x042: MOV R07, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04203007"
-
-# 0x043: MOV R08, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303008"
-
-# 0x044: MOV R09, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04403009"
-
-# 0x045: MOV R10, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0450300A"
-
-# 0x046: MOV R11, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460300B"
-
-# 0x047: MOV R12, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0470300C"
-
-# 0x048: MOV R13, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0480300D"
-
-# 0x049: MOV R14, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490300E"
-
-# 0x04A: MOV R15, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A0300F"
-
-# 0x04B: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B3E000"
-
-# 0x04C: MOV R00, 0x10
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03100"
-
-# 0x04D: CMP R00, 0x10
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D0F100"
-
-# 0x04E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3A3FF"
-
-# 0x04F: ADD R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010"
-
-# 0x050: MOV R01, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05002001"
-
-# 0x051: CMP R01, 0x11
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0510F111"
-
-# 0x052: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0523A3FF"
-
-# 0x053: ADD R01, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05311011"
-
-# 0x054: MOV R02, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05402012"
-
-# 0x055: CMP R02, 0x12
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550F122"
-
-# 0x056: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563A3FF"
-
-# 0x057: ADD R02, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05711012"
-
-# 0x058: MOV R03, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05802023"
-
-# 0x059: CMP R03, 0x13
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590F133"
-
-# 0x05A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A3FF"
-
-# 0x05B: ADD R03, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11013"
-
-# 0x05C: MOV R04, R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C02034"
-
-# 0x05D: CMP R04, 0x14
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D0F144"
-
-# 0x05E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3A3FF"
-
-# 0x05F: ADD R04, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F11014"
-
-# 0x060: MOV R05, R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06002045"
-
-# 0x061: CMP R05, 0x15
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610F155"
-
-# 0x062: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623A3FF"
-
-# 0x063: ADD R05, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06311015"
-
-# 0x064: MOV R06, R05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06402056"
-
-# 0x065: CMP R06, 0x16
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0650F166"
-
-# 0x066: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663A3FF"
-
-# 0x067: ADD R06, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06711016"
-
-# 0x068: MOV R07, R06
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06802067"
-
-# 0x069: CMP R07, 0x17
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0690F177"
-
-# 0x06A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3A3FF"
-
-# 0x06B: ADD R07, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B11017"
-
-# 0x06C: MOV R08, R07
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C02078"
-
-# 0x06D: CMP R08, 0x18
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D0F188"
-
-# 0x06E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3A3FF"
-
-# 0x06F: ADD R08, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F11018"
-
-# 0x070: MOV R09, R08
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07002089"
-
-# 0x071: CMP R09, 0x19
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0710F199"
-
-# 0x072: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723A3FF"
-
-# 0x073: ADD R09, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07311019"
-
-# 0x074: MOV R10, R09
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0740209A"
-
-# 0x075: CMP R10, 0x1A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750F1AA"
-
-# 0x076: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0763A3FF"
-
-# 0x077: ADD R10, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0771101A"
-
-# 0x078: MOV R11, R10
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "078020AB"
-
-# 0x079: CMP R11, 0x1B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0790F1BB"
-
-# 0x07A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3A3FF"
-
-# 0x07B: ADD R11, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B1101B"
-
-# 0x07C: MOV R12, R11
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C020BC"
-
-# 0x07D: CMP R12, 0x1C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D0F1CC"
-
-# 0x07E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E3A3FF"
-
-# 0x07F: ADD R12, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F1101C"
-
-# 0x080: MOV R13, R12
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "080020CD"
-
-# 0x081: CMP R13, 0x1D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0810F1DD"
-
-# 0x082: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823A3FF"
-
-# 0x083: ADD R13, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0831101D"
-
-# 0x084: MOV R14, R13
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "084020DE"
-
-# 0x085: CMP R14, 0x1E
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0850F1EE"
-
-# 0x086: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863A3FF"
-
-# 0x087: ADD R14, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0871101E"
-
-# 0x088: MOV R15, R14
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "088020EF"
-
-# 0x089: CMP R15, 0x1F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0890F1FF"
-
-# 0x08A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A3A3FF"
-
-# 0x08B: ADD R15, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B1101F"
-
-# 0x08C: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C3E000"
-
-# 0x08D: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D03000"
-
-# 0x08E: TST R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E0F000"
-
-# 0x08F: JNZ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F323FF"
-
-# 0x090: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "090333FF"
-
-# 0x091: CMP R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0910F000"
-
-# 0x092: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923A3FF"
-
-# 0x093: JLT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "093353FF"
-
-# 0x094: JGT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "094363FF"
-
-# 0x095: JLE 0x097
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09537097"
-
-# 0x096: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "096303FF"
-
-# 0x097: JEQ 0x099
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09739099"
-
-# 0x098: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098303FF"
-
-# 0x099: JGE 0x09B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0993809B"
-
-# 0x09A: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A303FF"
-
-# 0x09B: CMP R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B0F550"
-
-# 0x09C: JEQ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C393FF"
-
-# 0x09D: JLT 0x09F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3509F"
-
-# 0x09E: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E303FF"
-
-# 0x09F: JLE 0x0A1
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F370A1"
-
-# 0x0A0: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A0303FF"
-
-# 0x0A1: JGE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A1383FF"
-
-# 0x0A2: JGT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A2363FF"
-
-# 0x0A3: MOV R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A303550"
-
-# 0x0A4: TST R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A40F000"
-
-# 0x0A5: JZ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A5313FF"
-
-# 0x0A6: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A6333FF"
-
-# 0x0A7: CMP R00, 0xAA
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A70FAA0"
-
-# 0x0A8: JEQ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A8393FF"
-
-# 0x0A9: JNE 0x0AB
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A93A0AB"
-
-# 0x0AA: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AA303FF"
-
-# 0x0AB: JLT 0x0AD
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AB350AD"
-
-# 0x0AC: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AC303FF"
-
-# 0x0AD: JLE 0x0AF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AD370AF"
-
-# 0x0AE: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AE303FF"
-
-# 0x0AF: JGT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AF363FF"
-
-# 0x0B0: CMP R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B00F550"
-
-# 0x0B1: JEQ 0x0B3
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B1390B3"
-
-# 0x0B2: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B2303FF"
-
-# 0x0B3: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B33A3FF"
-
-# 0x0B4: JLT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B4353FF"
-
-# 0x0B5: JLE 0x0B7
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B5370B7"
-
-# 0x0B6: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B6303FF"
-
-# 0x0B7: JGT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B7363FF"
-
-# 0x0B8: JGE 0x0BA
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B8380BA"
-
-# 0x0B9: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B9303FF"
-
-# 0x0BA: MOV R00, 0xAA
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BA03AA0"
-
-# 0x0BB: TST R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BB0F000"
-
-# 0x0BC: JZ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BC313FF"
-
-# 0x0BD: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BD333FF"
-
-# 0x0BE: CMP R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BE0F550"
-
-# 0x0BF: JEQ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BF393FF"
-
-# 0x0C0: JNE 0x0C2
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C03A0C2"
-
-# 0x0C1: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C1303FF"
-
-# 0x0C2: JGT 0x0C4
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C2360C4"
-
-# 0x0C3: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C3303FF"
-
-# 0x0C4: JGE 0x0C6
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C4380C6"
-
-# 0x0C5: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C5303FF"
-
-# 0x0C6: JLT 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C6353FF"
-
-# 0x0C7: JLE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C7373FF"
-
-# 0x0C8: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C83E000"
-
-# 0x0C9: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C903000"
-
-# 0x0CA: MOV R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CA03001"
-
-# 0x0CB: MOV R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CB02002"
-
-# 0x0CC: MOV R03, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CC02013"
-
-# 0x0CD: ADD R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CD11010"
-
-# 0x0CE: ADDC R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CE13001"
-
-# 0x0CF: ADD R02, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CF11012"
-
-# 0x0D0: CMP R02, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D00F002"
-
-# 0x0D1: JNE 0x0D4
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D13A0D4"
-
-# 0x0D2: ADD R03, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D211013"
-
-# 0x0D3: CMP R03, 0x02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D30F023"
-
-# 0x0D4: JNE 0x0CD
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D43A0CD"
-
-# 0x0D5: CMP R00, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D50E020"
-
-# 0x0D6: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D63A3FF"
-
-# 0x0D7: CMP R01, R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D70E031"
-
-# 0x0D8: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D83A3FF"
-
-# 0x0D9: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D903000"
-
-# 0x0DA: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DA3E000"
-
-# 0x0DB: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DB03000"
-
-# 0x0DC: MOV R01, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DC03031"
-
-# 0x0DD: MOV R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DD02002"
-
-# 0x0DE: MOV R03, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DE02013"
-
-# 0x0DF: SUB R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DF15010"
-
-# 0x0E0: SUBC R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E017001"
-
-# 0x0E1: SUB R02, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E115012"
-
-# 0x0E2: CMP R02, 0xFF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E20FFF2"
-
-# 0x0E3: JNE 0x0E6
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E33A0E6"
-
-# 0x0E4: SUB R03, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E415013"
-
-# 0x0E5: CMP R03, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E50F003"
-
-# 0x0E6: JNE 0x0DF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E63A0DF"
-
-# 0x0E7: CMP R00, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E70E020"
-
-# 0x0E8: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E83A3FF"
-
-# 0x0E9: CMP R01, R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E90E031"
-
-# 0x0EA: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EA3A3FF"
-
-# 0x0EB: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EB03000"
-
-# 0x0EC: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EC3E000"
-
-# 0x0ED: MOV R00, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0ED03030"
-
-# 0x0EE: MOV R01, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EE03051"
-
-# 0x0EF: SUB 0x05, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EF2E050"
-
-# 0x0F0: SUB R01, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F015031"
-
-# 0x0F1: CMP R00, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F10E010"
-
-# 0x0F2: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F23A3FF"
-
-# 0x0F3: MOV R00, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F303030"
-
-# 0x0F4: MOV R01, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F403051"
-
-# 0x0F5: SUB R00, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F514010"
-
-# 0x0F6: SUBC 0x00, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F62F000"
-
-# 0x0F7: CMP R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F70F010"
-
-# 0x0F8: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F83A3FF"
-
-# 0x0F9: ADD R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F911000"
-
-# 0x0FA: SUBC R01, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FA16001"
-
-# 0x0FB: CMP R01, 0x04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FB0F041"
-
-# 0x0FC: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FC3A3FF"
-
-# 0x0FD: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FD03000"
-
-# 0x0FE: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FE3E000"
-
-# 0x0FF: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FF03010"
-
-# 0x100: MOVC (0x5A), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1000D5A0"
-
-# 0x101: DEC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10115010"
-
-# 0x102: MOVC (0x00), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1020D000"
-
-# 0x103: MOVC R01, (0x5A)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1030A5A1"
-
-# 0x104: MOVC (R01), 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1040CA51"
-
-# 0x105: MOVC R00, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10509010"
-
-# 0x106: MOVC R01, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10609011"
-
-# 0x107: ADD R01, 0x5A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "107115A1"
-
-# 0x108: MOVC R00, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10809010"
-
-# 0x109: MOVC (R00), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1090B000"
-
-# 0x10A: MOVC R02, (R00)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10A09002"
-
-# 0x10B: CMP R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10B0E002"
-
-# 0x10C: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10C3A3FF"
-
-# 0x10D: MOVC (R01), R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10D0B021"
-
-# 0x10E: MOVC R02, (R02)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10E09022"
-
-# 0x10F: CMP R02, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10F0E012"
-
-# 0x110: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1103A3FF"
-
-# 0x111: DEC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11115011"
-
-# 0x112: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11211010"
-
-# 0x113: JNZ 0x109
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11332109"
-
-# 0x114: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1143E000"
-
-# 0x115: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11503010"
-
-# 0x116: MOVX (0x60), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11608600"
-
-# 0x117: DEC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11715010"
-
-# 0x118: MOVX (0x06), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11808060"
-
-# 0x119: MOVX R01, (0x60)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11905601"
-
-# 0x11A: MOVX (R01), 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11A07A51"
-
-# 0x11B: MOVX R00, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11B04010"
-
-# 0x11C: MOVX R01, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11C04011"
-
-# 0x11D: ADD R01, 0x5A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11D115A1"
-
-# 0x11E: MOVX R00, (R01)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11E04010"
-
-# 0x11F: MOVX (R00), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11F06000"
-
-# 0x120: MOVX R02, (R00)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12004002"
-
-# 0x121: CMP R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1210E002"
-
-# 0x122: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1223A3FF"
-
-# 0x123: MOVX (R01), R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12306021"
-
-# 0x124: MOVX R02, (R02)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12404022"
-
-# 0x125: CMP R02, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1250E012"
-
-# 0x126: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1263A3FF"
-
-# 0x127: DEC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12715011"
-
-# 0x128: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12811010"
-
-# 0x129: JNZ 0x11F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1293211F"
-
-# 0x12A: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12A3E000"
-
-# 0x12B: MOV R00, 0xAA
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12B03AA0"
-
-# 0x12C: MOV R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12C03001"
-
-# 0x12D: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12D3C000"
-
-# 0x12E: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12E11010"
-
-# 0x12F: DEC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12F15011"
-
-# 0x130: JNZ 0x12D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1303212D"
-
-# 0x131: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1313D000"
-
-# 0x132: DEC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13215011"
-
-# 0x133: JNZ 0x131
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13332131"
-
-# 0x134: CMP R00, 0xAA
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1340FAA0"
-
-# 0x135: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1353A3FF"
-
-# 0x136: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1363E000"
-
-# 0x137: MOV R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13703550"
-
-# 0x138: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1383C000"
-
-# 0x139: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13903000"
-
-# 0x13A: MOV R01, 0xFF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13A03FF1"
-
-# 0x13B: CALL 0x151
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13B3B151"
-
-# 0x13C: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13C3D000"
-
-# 0x13D: CMP R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13D0F550"
-
-# 0x13E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13E3A3FF"
-
-# 0x13F: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13F03010"
-
-# 0x140: MOV R01, 0x48
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14003481"
-
-# 0x141: COUT (0x05), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14126050"
-
-# 0x142: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1423C001"
-
-# 0x143: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14303000"
-
-# 0x144: MOV R01, 0x3B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "144033B1"
-
-# 0x145: COUT (0x05), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14526050"
-
-# 0x146: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1463C001"
-
-# 0x147: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1473E000"
-
-# 0x148: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14803010"
-
-# 0x149: MOV R01, 0x50
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14903501"
-
-# 0x14A: COUT (0x05), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14A26050"
-
-# 0x14B: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14B3C001"
-
-# 0x14C: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14C03000"
-
-# 0x14D: MOV R01, 0x3B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14D033B1"
-
-# 0x14E: COUT (0x05), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14E26050"
-
-# 0x14F: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14F3C001"
-
-# 0x150: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1503E000"
-
-# 0x151: CMP R00, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1510E010"
-
-# 0x152: JEQ 0x155
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15239155"
-
-# 0x153: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15311010"
-
-# 0x154: JMP 0x158
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15430158"
-
-# 0x155: DEC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15515010"
-
-# 0x156: DEC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15615011"
-
-# 0x157: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1573E000"
-
-# 0x158: CALL 0x151
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1583B151"
-
-# 0x159: JMP 0x155
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15930155"
-
-# 0x15A: MOV R00, 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15A03A50"
-
-# 0x15B: MOV R01, 0x5A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15B035A1"
-
-# 0x15C: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15C2A000"
-
-# 0x15D: CMP R00, 0x5A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15D0F5A0"
-
-# 0x15E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15E3A3FF"
-
-# 0x15F: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15F2A000"
-
-# 0x160: CMP R00, 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1600FA50"
-
-# 0x161: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1613A3FF"
-
-# 0x162: MOV R00, 0xD2
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16203D20"
-
-# 0x163: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1632A000"
-
-# 0x164: CMP R00, 0x2D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1640F2D0"
-
-# 0x165: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1653A3FF"
-
-# 0x166: SWAP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1662A001"
-
-# 0x167: CMP R00, 0x2D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1670F2D0"
-
-# 0x168: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1683A3FF"
-
-# 0x169: CMP R01, 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1690FA51"
-
-# 0x16A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16A3A3FF"
-
-# 0x16B: MOV R00, 0x2D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16B032D0"
-
-# 0x16C: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16C1E000"
-
-# 0x16D: CMP R00, 0x5A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16D0F5A0"
-
-# 0x16E: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16E3A3FF"
-
-# 0x16F: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16F1E000"
-
-# 0x170: CMP R00, 0xB4
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1700FB40"
-
-# 0x171: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1713A3FF"
-
-# 0x172: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1721E000"
-
-# 0x173: CMP R00, 0x68
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1730F680"
-
-# 0x174: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1743A3FF"
-
-# 0x175: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1751E000"
-
-# 0x176: CMP R00, 0xD0
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1760FD00"
-
-# 0x177: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1773A3FF"
-
-# 0x178: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1781E000"
-
-# 0x179: CMP R00, 0xA0
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1790FA00"
-
-# 0x17A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17A3A3FF"
-
-# 0x17B: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17B1E000"
-
-# 0x17C: CMP R00, 0x40
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17C0F400"
-
-# 0x17D: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17D3A3FF"
-
-# 0x17E: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17E1E000"
-
-# 0x17F: CMP R00, 0x80
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17F0F800"
-
-# 0x180: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1803A3FF"
-
-# 0x181: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1811E000"
-
-# 0x182: CMP R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1820F000"
-
-# 0x183: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1833A3FF"
-
-# 0x184: MOV R01, 0x84
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18403841"
-
-# 0x185: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1851F001"
-
-# 0x186: CMP R01, 0x42
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1860F421"
-
-# 0x187: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1873A3FF"
-
-# 0x188: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1881F001"
-
-# 0x189: CMP R01, 0x21
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1890F211"
-
-# 0x18A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18A3A3FF"
-
-# 0x18B: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18B1F001"
-
-# 0x18C: CMP R01, 0x10
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18C0F101"
-
-# 0x18D: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18D3A3FF"
-
-# 0x18E: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18E1F001"
-
-# 0x18F: CMP R01, 0x08
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18F0F081"
-
-# 0x190: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1903A3FF"
-
-# 0x191: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1911F001"
-
-# 0x192: CMP R01, 0x04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1920F041"
-
-# 0x193: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1933A3FF"
-
-# 0x194: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1941F001"
-
-# 0x195: CMP R01, 0x02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1950F021"
-
-# 0x196: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1963A3FF"
-
-# 0x197: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1971F001"
-
-# 0x198: CMP R01, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1980F011"
-
-# 0x199: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1993A3FF"
-
-# 0x19A: SHR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19A1F001"
-
-# 0x19B: CMP R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19B0F001"
-
-# 0x19C: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19C3A3FF"
-
-# 0x19D: MOV R00, 0xC5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19D03C50"
-
-# 0x19E: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19E20000"
-
-# 0x19F: CMP R00, 0x8B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19F0F8B0"
-
-# 0x1A0: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A03A3FF"
-
-# 0x1A1: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A120000"
-
-# 0x1A2: CMP R00, 0x17
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A20F170"
-
-# 0x1A3: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A33A3FF"
-
-# 0x1A4: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A420000"
-
-# 0x1A5: CMP R00, 0x2E
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A50F2E0"
-
-# 0x1A6: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A63A3FF"
-
-# 0x1A7: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A720000"
-
-# 0x1A8: CMP R00, 0x5C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A80F5C0"
-
-# 0x1A9: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A93A3FF"
-
-# 0x1AA: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AA20000"
-
-# 0x1AB: CMP R00, 0xB8
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AB0FB80"
-
-# 0x1AC: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AC3A3FF"
-
-# 0x1AD: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AD20000"
-
-# 0x1AE: CMP R00, 0x71
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AE0F710"
-
-# 0x1AF: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AF3A3FF"
-
-# 0x1B0: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B020000"
-
-# 0x1B1: CMP R00, 0xE2
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B10FE20"
-
-# 0x1B2: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B23A3FF"
-
-# 0x1B3: ROL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B320000"
-
-# 0x1B4: CMP R00, 0xC5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B40FC50"
-
-# 0x1B5: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B53A3FF"
-
-# 0x1B6: MOV R01, 0x63
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B603631"
-
-# 0x1B7: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B721001"
-
-# 0x1B8: CMP R01, 0xB1
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B80FB11"
-
-# 0x1B9: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B93A3FF"
-
-# 0x1BA: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BA21001"
-
-# 0x1BB: CMP R01, 0xD8
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BB0FD81"
-
-# 0x1BC: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BC3A3FF"
-
-# 0x1BD: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BD21001"
-
-# 0x1BE: CMP R01, 0x6C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BE0F6C1"
-
-# 0x1BF: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BF3A3FF"
-
-# 0x1C0: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C021001"
-
-# 0x1C1: CMP R01, 0x36
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C10F361"
-
-# 0x1C2: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C23A3FF"
-
-# 0x1C3: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C321001"
-
-# 0x1C4: CMP R01, 0x1B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C40F1B1"
-
-# 0x1C5: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C53A3FF"
-
-# 0x1C6: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C621001"
-
-# 0x1C7: CMP R01, 0x8D
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C70F8D1"
-
-# 0x1C8: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C83A3FF"
-
-# 0x1C9: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C921001"
-
-# 0x1CA: CMP R01, 0xC6
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CA0FC61"
-
-# 0x1CB: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CB3A3FF"
-
-# 0x1CC: ROR R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CC21001"
-
-# 0x1CD: CMP R01, 0x63
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CD0F631"
-
-# 0x1CE: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CE3A3FF"
-
-# 0x1CF: XOR R00, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CF1C000"
-
-# 0x1D0: MOV R00, 0xC5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D003C50"
-
-# 0x1D1: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D122000"
-
-# 0x1D2: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D23C000"
-
-# 0x1D3: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D322000"
-
-# 0x1D4: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D43C000"
-
-# 0x1D5: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D522000"
-
-# 0x1D6: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D63C000"
-
-# 0x1D7: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D722000"
-
-# 0x1D8: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D83C000"
-
-# 0x1D9: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D922000"
-
-# 0x1DA: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DA3C000"
-
-# 0x1DB: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DB22000"
-
-# 0x1DC: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DC3C000"
-
-# 0x1DD: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DD22000"
-
-# 0x1DE: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DE3C000"
-
-# 0x1DF: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DF22000"
-
-# 0x1E0: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E03C000"
-
-# 0x1E1: ROLC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E122000"
-
-# 0x1E2: CMP R00, 0xC5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E20FC50"
-
-# 0x1E3: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E33A3FF"
-
-# 0x1E4: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E43D000"
-
-# 0x1E5: CMP R00, 0x62
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E50F620"
-
-# 0x1E6: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E63A3FF"
-
-# 0x1E7: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E73D000"
-
-# 0x1E8: CMP R00, 0xB1
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E80FB10"
-
-# 0x1E9: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E93A3FF"
-
-# 0x1EA: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EA3D000"
-
-# 0x1EB: CMP R00, 0x58
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EB0F580"
-
-# 0x1EC: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EC3A3FF"
-
-# 0x1ED: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1ED3D000"
-
-# 0x1EE: CMP R00, 0xAC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EE0FAC0"
-
-# 0x1EF: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EF3A3FF"
-
-# 0x1F0: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F03D000"
-
-# 0x1F1: CMP R00, 0x56
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F10F560"
-
-# 0x1F2: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F23A3FF"
-
-# 0x1F3: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F33D000"
-
-# 0x1F4: CMP R00, 0x2B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F40F2B0"
-
-# 0x1F5: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F53A3FF"
-
-# 0x1F6: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F63D000"
-
-# 0x1F7: CMP R00, 0x15
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F70F150"
-
-# 0x1F8: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F83A3FF"
-
-# 0x1F9: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F93D000"
-
-# 0x1FA: CMP R00, 0x8A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FA0F8A0"
-
-# 0x1FB: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FB3A3FF"
-
-# 0x1FC: XOR R01, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FC1C011"
-
-# 0x1FD: MOV R01, 0x63
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FD03631"
-
-# 0x1FE: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FE23001"
-
-# 0x1FF: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FF3C001"
-
-# 0x200: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20023001"
-
-# 0x201: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2013C001"
-
-# 0x202: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20223001"
-
-# 0x203: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2033C001"
-
-# 0x204: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20423001"
-
-# 0x205: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2053C001"
-
-# 0x206: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20623001"
-
-# 0x207: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2073C001"
-
-# 0x208: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20823001"
-
-# 0x209: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2093C001"
-
-# 0x20A: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20A23001"
-
-# 0x20B: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20B3C001"
-
-# 0x20C: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20C23001"
-
-# 0x20D: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20D3C001"
-
-# 0x20E: RORC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20E23001"
-
-# 0x20F: CMP R01, 0x63
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20F0F631"
-
-# 0x210: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2103A3FF"
-
-# 0x211: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2113D001"
-
-# 0x212: CMP R01, 0xC6
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2120FC61"
-
-# 0x213: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2133A3FF"
-
-# 0x214: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2143D001"
-
-# 0x215: CMP R01, 0x8C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2150F8C1"
-
-# 0x216: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2163A3FF"
-
-# 0x217: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2173D001"
-
-# 0x218: CMP R01, 0x19
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2180F191"
-
-# 0x219: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2193A3FF"
-
-# 0x21A: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21A3D001"
-
-# 0x21B: CMP R01, 0x33
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21B0F331"
-
-# 0x21C: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21C3A3FF"
-
-# 0x21D: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21D3D001"
-
-# 0x21E: CMP R01, 0x66
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21E0F661"
-
-# 0x21F: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21F3A3FF"
-
-# 0x220: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2203D001"
-
-# 0x221: CMP R01, 0xCC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2210FCC1"
-
-# 0x222: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2223A3FF"
-
-# 0x223: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2233D001"
-
-# 0x224: CMP R01, 0x98
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2240F981"
-
-# 0x225: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2253A3FF"
-
-# 0x226: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2263D001"
-
-# 0x227: CMP R01, 0x31
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2270F311"
-
-# 0x228: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2283A3FF"
-
-# 0x229: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2293E000"
-
-# 0x22A: MOV R00, 0xA5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22A03A50"
-
-# 0x22B: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22B2A000"
-
-# 0x22C: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22C3C000"
-
-# 0x22D: AND R00, 0x0F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22D190F0"
-
-# 0x22E: CMP R00, 0x0A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22E0F0A0"
-
-# 0x22F: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22F3A3FF"
-
-# 0x230: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2303D000"
-
-# 0x231: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2313C000"
-
-# 0x232: AND R00, 0x0F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "232190F0"
-
-# 0x233: CMP R00, 0x0A
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2330F0A0"
-
-# 0x234: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2343D001"
-
-# 0x235: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2353A3FF"
-
-# 0x236: SWAP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2362A001"
-
-# 0x237: MOV R02, 0x0F
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "237030F2"
-
-# 0x238: AND R01, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23818021"
-
-# 0x239: CMP R01, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2390F051"
-
-# 0x23A: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23A3A3FF"
-
-# 0x23B: MOV R00, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23B03050"
-
-# 0x23C: MOV R02, 0xA0
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23C03A02"
-
-# 0x23D: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23D2A000"
-
-# 0x23E: OR R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23E1A002"
-
-# 0x23F: CMP R02, 0xF0
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23F0FF02"
-
-# 0x240: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2403A3FF"
-
-# 0x241: SWAP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2412A000"
-
-# 0x242: OR R00, 0x50
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2421B500"
-
-# 0x243: CMP R00, 0x55
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2430F550"
-
-# 0x244: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2443A3FF"
-
-# 0x245: MOV R01, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24503011"
-
-# 0x246: MOV R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24603010"
-
-# 0x247: XOR R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2471D010"
-
-# 0x248: JNZ 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "248323FF"
-
-# 0x249: XOR R00, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2491C010"
-
-# 0x24A: CMP R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24A0F010"
-
-# 0x24B: JNE 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24B3A3FF"
-
-# 0x24C: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24C3E000"
-
-# 0x24D: MOV R00, 0x03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24D03030"
-
-# 0x24E: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24E26030"
-
-# 0x24F: XIN R00, (0x02)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24F28020"
-
-# 0x250: OR R00, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2501B010"
-
-# 0x251: XOUT (0x02), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25124020"
-
-# 0x252: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25200000"
-
-# 0x253: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25300000"
-
-# 0x254: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25400000"
-
-# 0x255: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25500000"
-
-# 0x256: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25600000"
-
-# 0x257: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25700000"
-
-# 0x258: XIN R00, (0x02)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25828020"
-
-# 0x259: AND R00, 0xFE
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25919FE0"
-
-# 0x25A: XOUT (0x02), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25A24020"
-
-# 0x25B: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25B00000"
-
-# 0x25C: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25C00000"
-
-# 0x25D: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25D00000"
-
-# 0x25E: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25E00000"
-
-# 0x25F: CIN R00, (0x03)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25F29030"
-
-# 0x260: OR R00, 0x80
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2601B800"
-
-# 0x261: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26126030"
-
-# 0x262: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26200000"
-
-# 0x263: CIN R00, (0x03)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26329030"
-
-# 0x264: OR R00, 0x80
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2641B800"
-
-# 0x265: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26526030"
-
-# 0x266: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26600000"
-
-# 0x267: CIN R00, (0x03)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26729030"
-
-# 0x268: OR R00, 0x80
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2681B800"
-
-# 0x269: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26926030"
-
-# 0x26A: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26A00000"
-
-# 0x26B: CIN R00, (0x03)
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26B29030"
-
-# 0x26C: OR R00, 0x80
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26C1B800"
-
-# 0x26D: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26D26030"
-
-# 0x26E: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26E00000"
-
-# 0x26F: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26F00000"
-
-# 0x270: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27000000"
-
-# 0x271: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27100000"
-
-# 0x272: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27200000"
-
-# 0x273: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27300000"
-
-# 0x274: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27400000"
-
-# 0x275: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27500000"
-
-# 0x276: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27600000"
-
-# 0x277: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2773E000"
-
-# 0x278: SUB R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27815000"
-
-# 0x279: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "279333FF"
-
-# 0x27A: SETC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27A2B000"
-
-# 0x27B: JNC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27B343FF"
-
-# 0x27C: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27C00000"
-
-# 0x27D: SUB R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27D15000"
-
-# 0x27E: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27E333FF"
-
-# 0x27F: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27F03000"
-
-# 0x280: CLRC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28015000"
-
-# 0x281: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "281333FF"
-
-# 0x282: SETC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2822B000"
-
-# 0x283: JNC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "283343FF"
-
-# 0x284: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28400000"
-
-# 0x285: CLRC
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28515000"
-
-# 0x286: JC 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "286333FF"
-
-# 0x287: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2873E000"
-
-# 0x288: INC R14
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2881101E"
-
-# 0x289: RETI
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2893F000"
-
-# 0x28A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28A00000"
-
-# 0x28B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28B00000"
-
-# 0x28C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28C00000"
-
-# 0x28D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28D00000"
-
-# 0x28E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28E00000"
-
-# 0x28F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28F00000"
-
-# 0x290:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29000000"
-
-# 0x291:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29100000"
-
-# 0x292:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29200000"
-
-# 0x293:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29300000"
-
-# 0x294:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29400000"
-
-# 0x295:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29500000"
-
-# 0x296:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29600000"
-
-# 0x297:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29700000"
-
-# 0x298:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29800000"
-
-# 0x299:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29900000"
-
-# 0x29A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29A00000"
-
-# 0x29B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29B00000"
-
-# 0x29C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29C00000"
-
-# 0x29D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29D00000"
-
-# 0x29E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29E00000"
-
-# 0x29F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29F00000"
-
-# 0x2A0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A000000"
-
-# 0x2A1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A100000"
-
-# 0x2A2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A200000"
-
-# 0x2A3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A300000"
-
-# 0x2A4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A400000"
-
-# 0x2A5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A500000"
-
-# 0x2A6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A600000"
-
-# 0x2A7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A700000"
-
-# 0x2A8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A800000"
-
-# 0x2A9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A900000"
-
-# 0x2AA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AA00000"
-
-# 0x2AB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AB00000"
-
-# 0x2AC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AC00000"
-
-# 0x2AD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AD00000"
-
-# 0x2AE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AE00000"
-
-# 0x2AF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AF00000"
-
-# 0x2B0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B000000"
-
-# 0x2B1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B100000"
-
-# 0x2B2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B200000"
-
-# 0x2B3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B300000"
-
-# 0x2B4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B400000"
-
-# 0x2B5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B500000"
-
-# 0x2B6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B600000"
-
-# 0x2B7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B700000"
-
-# 0x2B8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B800000"
-
-# 0x2B9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B900000"
-
-# 0x2BA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BA00000"
-
-# 0x2BB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BB00000"
-
-# 0x2BC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BC00000"
-
-# 0x2BD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BD00000"
-
-# 0x2BE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BE00000"
-
-# 0x2BF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BF00000"
-
-# 0x2C0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C000000"
-
-# 0x2C1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C100000"
-
-# 0x2C2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C200000"
-
-# 0x2C3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C300000"
-
-# 0x2C4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C400000"
-
-# 0x2C5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C500000"
-
-# 0x2C6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C600000"
-
-# 0x2C7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C700000"
-
-# 0x2C8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C800000"
-
-# 0x2C9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C900000"
-
-# 0x2CA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CA00000"
-
-# 0x2CB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CB00000"
-
-# 0x2CC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CC00000"
-
-# 0x2CD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CD00000"
-
-# 0x2CE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CE00000"
-
-# 0x2CF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CF00000"
-
-# 0x2D0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D000000"
-
-# 0x2D1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D100000"
-
-# 0x2D2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D200000"
-
-# 0x2D3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D300000"
-
-# 0x2D4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D400000"
-
-# 0x2D5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D500000"
-
-# 0x2D6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D600000"
-
-# 0x2D7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D700000"
-
-# 0x2D8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D800000"
-
-# 0x2D9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D900000"
-
-# 0x2DA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DA00000"
-
-# 0x2DB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DB00000"
-
-# 0x2DC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DC00000"
-
-# 0x2DD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DD00000"
-
-# 0x2DE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DE00000"
-
-# 0x2DF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DF00000"
-
-# 0x2E0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E000000"
-
-# 0x2E1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E100000"
-
-# 0x2E2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E200000"
-
-# 0x2E3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E300000"
-
-# 0x2E4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E400000"
-
-# 0x2E5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E500000"
-
-# 0x2E6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E600000"
-
-# 0x2E7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E700000"
-
-# 0x2E8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E800000"
-
-# 0x2E9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E900000"
-
-# 0x2EA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EA00000"
-
-# 0x2EB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EB00000"
-
-# 0x2EC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EC00000"
-
-# 0x2ED:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2ED00000"
-
-# 0x2EE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EE00000"
-
-# 0x2EF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EF00000"
-
-# 0x2F0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F000000"
-
-# 0x2F1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F100000"
-
-# 0x2F2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F200000"
-
-# 0x2F3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F300000"
-
-# 0x2F4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F400000"
-
-# 0x2F5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F500000"
-
-# 0x2F6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F600000"
-
-# 0x2F7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F700000"
-
-# 0x2F8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F800000"
-
-# 0x2F9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F900000"
-
-# 0x2FA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FA00000"
-
-# 0x2FB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FB00000"
-
-# 0x2FC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FC00000"
-
-# 0x2FD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FD00000"
-
-# 0x2FE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FE00000"
-
-# 0x2FF: JMP 0x2FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FF302FF"
-
-# 0x300:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30000000"
-
-# 0x301:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30100000"
-
-# 0x302:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30200000"
-
-# 0x303:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30300000"
-
-# 0x304:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30400000"
-
-# 0x305:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30500000"
-
-# 0x306:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30600000"
-
-# 0x307:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30700000"
-
-# 0x308:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30800000"
-
-# 0x309:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30900000"
-
-# 0x30A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30A00000"
-
-# 0x30B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30B00000"
-
-# 0x30C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30C00000"
-
-# 0x30D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30D00000"
-
-# 0x30E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30E00000"
-
-# 0x30F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30F00000"
-
-# 0x310:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31000000"
-
-# 0x311:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31100000"
-
-# 0x312:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31200000"
-
-# 0x313:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31300000"
-
-# 0x314:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31400000"
-
-# 0x315:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31500000"
-
-# 0x316:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31600000"
-
-# 0x317:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31700000"
-
-# 0x318:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31800000"
-
-# 0x319:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31900000"
-
-# 0x31A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31A00000"
-
-# 0x31B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31B00000"
-
-# 0x31C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31C00000"
-
-# 0x31D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31D00000"
-
-# 0x31E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31E00000"
-
-# 0x31F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31F00000"
-
-# 0x320:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32000000"
-
-# 0x321:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32100000"
-
-# 0x322:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32200000"
-
-# 0x323:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32300000"
-
-# 0x324:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32400000"
-
-# 0x325:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32500000"
-
-# 0x326:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32600000"
-
-# 0x327:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32700000"
-
-# 0x328:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32800000"
-
-# 0x329:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32900000"
-
-# 0x32A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32A00000"
-
-# 0x32B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32B00000"
-
-# 0x32C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32C00000"
-
-# 0x32D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32D00000"
-
-# 0x32E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32E00000"
-
-# 0x32F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32F00000"
-
-# 0x330:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33000000"
-
-# 0x331:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33100000"
-
-# 0x332:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33200000"
-
-# 0x333:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33300000"
-
-# 0x334:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33400000"
-
-# 0x335:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33500000"
-
-# 0x336:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33600000"
-
-# 0x337:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33700000"
-
-# 0x338:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33800000"
-
-# 0x339:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33900000"
-
-# 0x33A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33A00000"
-
-# 0x33B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33B00000"
-
-# 0x33C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33C00000"
-
-# 0x33D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33D00000"
-
-# 0x33E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33E00000"
-
-# 0x33F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33F00000"
-
-# 0x340:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34000000"
-
-# 0x341:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34100000"
-
-# 0x342:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34200000"
-
-# 0x343:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34300000"
-
-# 0x344:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34400000"
-
-# 0x345:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34500000"
-
-# 0x346:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34600000"
-
-# 0x347:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34700000"
-
-# 0x348:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34800000"
-
-# 0x349:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34900000"
-
-# 0x34A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34A00000"
-
-# 0x34B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34B00000"
-
-# 0x34C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34C00000"
-
-# 0x34D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34D00000"
-
-# 0x34E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34E00000"
-
-# 0x34F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34F00000"
-
-# 0x350:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35000000"
-
-# 0x351:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35100000"
-
-# 0x352:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35200000"
-
-# 0x353:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35300000"
-
-# 0x354:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35400000"
-
-# 0x355:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35500000"
-
-# 0x356:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35600000"
-
-# 0x357:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35700000"
-
-# 0x358:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35800000"
-
-# 0x359:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35900000"
-
-# 0x35A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35A00000"
-
-# 0x35B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35B00000"
-
-# 0x35C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35C00000"
-
-# 0x35D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35D00000"
-
-# 0x35E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35E00000"
-
-# 0x35F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35F00000"
-
-# 0x360:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36000000"
-
-# 0x361:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36100000"
-
-# 0x362:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36200000"
-
-# 0x363:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36300000"
-
-# 0x364:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36400000"
-
-# 0x365:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36500000"
-
-# 0x366:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36600000"
-
-# 0x367:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36700000"
-
-# 0x368:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36800000"
-
-# 0x369:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36900000"
-
-# 0x36A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36A00000"
-
-# 0x36B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36B00000"
-
-# 0x36C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36C00000"
-
-# 0x36D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36D00000"
-
-# 0x36E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36E00000"
-
-# 0x36F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36F00000"
-
-# 0x370:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37000000"
-
-# 0x371:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37100000"
-
-# 0x372:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37200000"
-
-# 0x373:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37300000"
-
-# 0x374:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37400000"
-
-# 0x375:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37500000"
-
-# 0x376:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37600000"
-
-# 0x377:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37700000"
-
-# 0x378:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37800000"
-
-# 0x379:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37900000"
-
-# 0x37A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37A00000"
-
-# 0x37B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37B00000"
-
-# 0x37C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37C00000"
-
-# 0x37D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37D00000"
-
-# 0x37E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37E00000"
-
-# 0x37F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37F00000"
-
-# 0x380:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38000000"
-
-# 0x381:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38100000"
-
-# 0x382:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38200000"
-
-# 0x383:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38300000"
-
-# 0x384:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38400000"
-
-# 0x385:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38500000"
-
-# 0x386:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38600000"
-
-# 0x387:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38700000"
-
-# 0x388:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38800000"
-
-# 0x389:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38900000"
-
-# 0x38A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38A00000"
-
-# 0x38B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38B00000"
-
-# 0x38C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38C00000"
-
-# 0x38D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38D00000"
-
-# 0x38E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38E00000"
-
-# 0x38F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38F00000"
-
-# 0x390:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39000000"
-
-# 0x391:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39100000"
-
-# 0x392:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39200000"
-
-# 0x393:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39300000"
-
-# 0x394:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39400000"
-
-# 0x395:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39500000"
-
-# 0x396:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39600000"
-
-# 0x397:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39700000"
-
-# 0x398:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39800000"
-
-# 0x399:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39900000"
-
-# 0x39A:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39A00000"
-
-# 0x39B:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39B00000"
-
-# 0x39C:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39C00000"
-
-# 0x39D:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39D00000"
-
-# 0x39E:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39E00000"
-
-# 0x39F:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39F00000"
-
-# 0x3A0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A000000"
-
-# 0x3A1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A100000"
-
-# 0x3A2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A200000"
-
-# 0x3A3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A300000"
-
-# 0x3A4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A400000"
-
-# 0x3A5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A500000"
-
-# 0x3A6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A600000"
-
-# 0x3A7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A700000"
-
-# 0x3A8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A800000"
-
-# 0x3A9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A900000"
-
-# 0x3AA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AA00000"
-
-# 0x3AB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AB00000"
-
-# 0x3AC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AC00000"
-
-# 0x3AD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AD00000"
-
-# 0x3AE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AE00000"
-
-# 0x3AF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AF00000"
-
-# 0x3B0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B000000"
-
-# 0x3B1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B100000"
-
-# 0x3B2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B200000"
-
-# 0x3B3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B300000"
-
-# 0x3B4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B400000"
-
-# 0x3B5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B500000"
-
-# 0x3B6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B600000"
-
-# 0x3B7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B700000"
-
-# 0x3B8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B800000"
-
-# 0x3B9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B900000"
-
-# 0x3BA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BA00000"
-
-# 0x3BB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BB00000"
-
-# 0x3BC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BC00000"
-
-# 0x3BD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BD00000"
-
-# 0x3BE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BE00000"
-
-# 0x3BF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BF00000"
-
-# 0x3C0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C000000"
-
-# 0x3C1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C100000"
-
-# 0x3C2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C200000"
-
-# 0x3C3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C300000"
-
-# 0x3C4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C400000"
-
-# 0x3C5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C500000"
-
-# 0x3C6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C600000"
-
-# 0x3C7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C700000"
-
-# 0x3C8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C800000"
-
-# 0x3C9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C900000"
-
-# 0x3CA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CA00000"
-
-# 0x3CB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CB00000"
-
-# 0x3CC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CC00000"
-
-# 0x3CD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CD00000"
-
-# 0x3CE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CE00000"
-
-# 0x3CF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CF00000"
-
-# 0x3D0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D000000"
-
-# 0x3D1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D100000"
-
-# 0x3D2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D200000"
-
-# 0x3D3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D300000"
-
-# 0x3D4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D400000"
-
-# 0x3D5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D500000"
-
-# 0x3D6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D600000"
-
-# 0x3D7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D700000"
-
-# 0x3D8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D800000"
-
-# 0x3D9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D900000"
-
-# 0x3DA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DA00000"
-
-# 0x3DB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DB00000"
-
-# 0x3DC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DC00000"
-
-# 0x3DD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DD00000"
-
-# 0x3DE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DE00000"
-
-# 0x3DF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DF00000"
-
-# 0x3E0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E000000"
-
-# 0x3E1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E100000"
-
-# 0x3E2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E200000"
-
-# 0x3E3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E300000"
-
-# 0x3E4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E400000"
-
-# 0x3E5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E500000"
-
-# 0x3E6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E600000"
-
-# 0x3E7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E700000"
-
-# 0x3E8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E800000"
-
-# 0x3E9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E900000"
-
-# 0x3EA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EA00000"
-
-# 0x3EB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EB00000"
-
-# 0x3EC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EC00000"
-
-# 0x3ED:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3ED00000"
-
-# 0x3EE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EE00000"
-
-# 0x3EF:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EF00000"
-
-# 0x3F0:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F000000"
-
-# 0x3F1:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F100000"
-
-# 0x3F2:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F200000"
-
-# 0x3F3:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F300000"
-
-# 0x3F4:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F400000"
-
-# 0x3F5:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F500000"
-
-# 0x3F6:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F600000"
-
-# 0x3F7:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F700000"
-
-# 0x3F8:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F800000"
-
-# 0x3F9:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F900000"
-
-# 0x3FA:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FA00000"
-
-# 0x3FB:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FB00000"
-
-# 0x3FC:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FC00000"
-
-# 0x3FD:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FD00000"
-
-# 0x3FE:
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FE00000"
-
-# 0x3FF: JMP 0x3FF
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FF303FF"
-
-# Assembled from itest.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0048"
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-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CE00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CF00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D600"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D800"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D900"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DA00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DB00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DC00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DD00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DE00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DF00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E600"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E800"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E900"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EA00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EB00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EC00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "ED00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EE00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EF00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F500"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F600"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F700"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F800"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F900"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FA00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FB00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FC00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FD00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FE00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FF00"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10000"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10100"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10200"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10300"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10400"
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10500"
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/lib/CPUs/JCpu/asm/make b/lib/CPUs/JCpu/asm/make
deleted file mode 100644
index e7f598f..0000000
--- a/lib/CPUs/JCpu/asm/make
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/bin/sh
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: rom-file generation for cpu_core
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-TARGET=$2
-DSTDIR=$1
-
-JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
-
-$JASM_HOME/jasm.rb $TARGET.jsm
-
-irom_tcl_snippet="$TARGET.irom.tcl.snip"
-irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
-irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
-xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
-xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
-xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
-
-$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
-$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
-
-$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
-$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
-
-cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
-cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
-$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
-
-rm -f *.snip
diff --git a/lib/CPUs/JCpu/asm/mul8x8.jsm b/lib/CPUs/JCpu/asm/mul8x8.jsm
deleted file mode 100644
index c9b6c3b..0000000
--- a/lib/CPUs/JCpu/asm/mul8x8.jsm
+++ /dev/null
@@ -1,29 +0,0 @@
-; -------------------------------------------------
-; Constants
-; -------------------------------------------------
-
-; Chip register
-include "../../../jasm/cregs.inc.jsm"
-
-; -------------------------------------------------
-; Program
-; -------------------------------------------------
-				code
-				org		0x000
-reset:			jmp		init
-						
-; -------------------------------------------------
-; Main
-; -------------------------------------------------
-init:			mov		R0, 0x45
-				mov		R1, 0xF5
-				
-				call	mul8x8
-stop:			jmp		stop
-
-
-; -------------------------------------------------
-include "../../../jasm/mul8x8.inc.jsm"
-				
-				
-				
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/asm/mul8x8.tcl b/lib/CPUs/JCpu/asm/mul8x8.tcl
deleted file mode 100644
index 6bec87e..0000000
--- a/lib/CPUs/JCpu/asm/mul8x8.tcl
+++ /dev/null
@@ -1,154 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from mul8x8.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x001
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001"
-
-# 0x001: MOV R00, 0x45
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450"
-
-# 0x002: MOV R01, 0xF5
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51"
-
-# 0x003: CALL 0x005
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005"
-
-# 0x004: JMP 0x004
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004"
-
-# 0x005: PUSH R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002"
-
-# 0x006: PUSH R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003"
-
-# 0x007: PUSH R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004"
-
-# 0x008: MOV R04, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014"
-
-# 0x009: MOV R01, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001"
-
-# 0x00A: MOV R02, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002"
-
-# 0x00B: MOV R03, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003"
-
-# 0x00C: CMP R04, 0x01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014"
-
-# 0x00D: JEQ 0x015
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015"
-
-# 0x00E: SHR R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004"
-
-# 0x00F: JNC 0x012
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012"
-
-# 0x010: ADD R02, R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002"
-
-# 0x011: ADDC R03, R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013"
-
-# 0x012: SHL R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000"
-
-# 0x013: ROLC R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001"
-
-# 0x014: JMP 0x00C
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C"
-
-# 0x015: ADD R00, R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020"
-
-# 0x016: ADDC R01, R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031"
-
-# 0x017: POP R04
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004"
-
-# 0x018: POP R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
-
-# 0x019: POP R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002"
-
-# 0x01A: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000"
-
-# Assembled from mul8x8.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/lib/CPUs/JCpu/asm/reti_issue.jsm b/lib/CPUs/JCpu/asm/reti_issue.jsm
deleted file mode 100644
index 78edc49..0000000
--- a/lib/CPUs/JCpu/asm/reti_issue.jsm
+++ /dev/null
@@ -1,50 +0,0 @@
-; -------------------------------------------------
-; Constants
-; -------------------------------------------------
-
-; Chip register
-cpu_revision:	equ		0x00	; RO
-cpu_control:	equ		0x01	; R/W
-cpu_status:		equ		0x02	; RO
-cpu_int_ctrl:	equ		0x03	; R/W
-
-; -------------------------------------------------
-; Program
-; -------------------------------------------------
-				code
-reset:			jmp		init
-		
-				org		0x001
-;				nop
-				reti
-				
-; -------------------------------------------------
-; Main
-; -------------------------------------------------
-init:			mov		R0, 0x05
-				cout	(cpu_int_ctrl), R0
-				mov		R0, 0x00
-loop:			nop
-				inc		R0
-				nop
-				call	subr
-				nop
-				push	R3
-				nop
-				push	R2
-				nop
-				push	R1
-				nop
-				push	R0
-				nop
-				pop		R0
-				nop
-				pop		R1
-				nop
-				pop		R2
-				nop
-				pop		R3
-				nop
-				jmp		loop
-
-subr:			ret				
diff --git a/lib/CPUs/JCpu/asm/reti_issue.tcl b/lib/CPUs/JCpu/asm/reti_issue.tcl
deleted file mode 100644
index 5da9c56..0000000
--- a/lib/CPUs/JCpu/asm/reti_issue.tcl
+++ /dev/null
@@ -1,157 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-# Assembled from reti_issue.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA
-# User 1
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"]
-
-# 0x000: JMP 0x002
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002"
-
-# 0x001: RETI
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000"
-
-# 0x002: MOV R00, 0x05
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050"
-
-# 0x003: COUT (0x03), R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030"
-
-# 0x004: MOV R00, 0x00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000"
-
-# 0x005: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000"
-
-# 0x006: INC R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010"
-
-# 0x007: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000"
-
-# 0x008: CALL 0x01B
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B"
-
-# 0x009: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000"
-
-# 0x00A: PUSH R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003"
-
-# 0x00B: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000"
-
-# 0x00C: PUSH R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002"
-
-# 0x00D: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000"
-
-# 0x00E: PUSH R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001"
-
-# 0x00F: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000"
-
-# 0x010: PUSH R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000"
-
-# 0x011: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000"
-
-# 0x012: POP R00
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000"
-
-# 0x013: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000"
-
-# 0x014: POP R01
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001"
-
-# 0x015: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000"
-
-# 0x016: POP R02
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002"
-
-# 0x017: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000"
-
-# 0x018: POP R03
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003"
-
-# 0x019: NOP
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000"
-
-# 0x01A: JMP 0x005
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005"
-
-# 0x01B: RET
-::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000"
-
-# Assembled from reti_issue.jsm
-# ---------------------------------------------------------------
-# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA
-# User 2
-set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"]
-
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/lib/CPUs/JCpu/doc/block_diagram.png b/lib/CPUs/JCpu/doc/block_diagram.png
deleted file mode 100644
index 14bbb54..0000000
Binary files a/lib/CPUs/JCpu/doc/block_diagram.png and /dev/null differ
diff --git a/lib/CPUs/JCpu/doc/memory_map.png b/lib/CPUs/JCpu/doc/memory_map.png
deleted file mode 100644
index 30a22a0..0000000
Binary files a/lib/CPUs/JCpu/doc/memory_map.png and /dev/null differ
diff --git a/lib/CPUs/JCpu/gpl-3.0.txt b/lib/CPUs/JCpu/gpl-3.0.txt
deleted file mode 100644
index 94a9ed0..0000000
--- a/lib/CPUs/JCpu/gpl-3.0.txt
+++ /dev/null
@@ -1,674 +0,0 @@
-                    GNU GENERAL PUBLIC LICENSE
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-in a country, would infringe one or more identifiable patents in that
-country that you have reason to believe are valid.
-
-  If, pursuant to or in connection with a single transaction or
-arrangement, you convey, or propagate by procuring conveyance of, a
-covered work, and grant a patent license to some of the parties
-receiving the covered work authorizing them to use, propagate, modify
-or convey a specific copy of the covered work, then the patent license
-you grant is automatically extended to all recipients of the covered
-work and works based on it.
-
-  A patent license is "discriminatory" if it does not include within
-the scope of its coverage, prohibits the exercise of, or is
-conditioned on the non-exercise of one or more of the rights that are
-specifically granted under this License.  You may not convey a covered
-work if you are a party to an arrangement with a third party that is
-in the business of distributing software, under which you make payment
-to the third party based on the extent of your activity of conveying
-the work, and under which the third party grants, to any of the
-parties who would receive the covered work from you, a discriminatory
-patent license (a) in connection with copies of the covered work
-conveyed by you (or copies made from those copies), or (b) primarily
-for and in connection with specific products or compilations that
-contain the covered work, unless you entered into that arrangement,
-or that patent license was granted, prior to 28 March 2007.
-
-  Nothing in this License shall be construed as excluding or limiting
-any implied license or other defenses to infringement that may
-otherwise be available to you under applicable patent law.
-
-  12. No Surrender of Others' Freedom.
-
-  If conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License.  If you cannot convey a
-covered work so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you may
-not convey it at all.  For example, if you agree to terms that obligate you
-to collect a royalty for further conveying from those to whom you convey
-the Program, the only way you could satisfy both those terms and this
-License would be to refrain entirely from conveying the Program.
-
-  13. Use with the GNU Affero General Public License.
-
-  Notwithstanding any other provision of this License, you have
-permission to link or combine any covered work with a work licensed
-under version 3 of the GNU Affero General Public License into a single
-combined work, and to convey the resulting work.  The terms of this
-License will continue to apply to the part which is the covered work,
-but the special requirements of the GNU Affero General Public License,
-section 13, concerning interaction through a network will apply to the
-combination as such.
-
-  14. Revised Versions of this License.
-
-  The Free Software Foundation may publish revised and/or new versions of
-the GNU General Public License from time to time.  Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-  Each version is given a distinguishing version number.  If the
-Program specifies that a certain numbered version of the GNU General
-Public License "or any later version" applies to it, you have the
-option of following the terms and conditions either of that numbered
-version or of any later version published by the Free Software
-Foundation.  If the Program does not specify a version number of the
-GNU General Public License, you may choose any version ever published
-by the Free Software Foundation.
-
-  If the Program specifies that a proxy can decide which future
-versions of the GNU General Public License can be used, that proxy's
-public statement of acceptance of a version permanently authorizes you
-to choose that version for the Program.
-
-  Later license versions may give you additional or different
-permissions.  However, no additional obligations are imposed on any
-author or copyright holder as a result of your choosing to follow a
-later version.
-
-  15. Disclaimer of Warranty.
-
-  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
-APPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
-HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
-OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
-THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
-IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
-ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
-  16. Limitation of Liability.
-
-  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
-THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
-GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
-USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
-DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
-PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
-EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGES.
-
-  17. Interpretation of Sections 15 and 16.
-
-  If the disclaimer of warranty and limitation of liability provided
-above cannot be given local legal effect according to their terms,
-reviewing courts shall apply local law that most closely approximates
-an absolute waiver of all civil liability in connection with the
-Program, unless a warranty or assumption of liability accompanies a
-copy of the Program in return for a fee.
-
-                     END OF TERMS AND CONDITIONS
-
-            How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-state the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software: you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation, either version 3 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-
-Also add information on how to contact you by electronic and paper mail.
-
-  If the program does terminal interaction, make it output a short
-notice like this when it starts in an interactive mode:
-
-    <program>  Copyright (C) <year>  <name of author>
-    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
-  You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
-<http://www.gnu.org/licenses/>.
-
-  The GNU General Public License does not permit incorporating your program
-into proprietary programs.  If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.  But first, please read
-<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/lib/CPUs/JCpu/sim/ModelSim SE .lnk b/lib/CPUs/JCpu/sim/ModelSim SE .lnk
deleted file mode 100644
index 1fe4002..0000000
Binary files a/lib/CPUs/JCpu/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/CPUs/JCpu/sim/tb_cpu.fdo b/lib/CPUs/JCpu/sim/tb_cpu.fdo
deleted file mode 100644
index 86feedf..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu.fdo
+++ /dev/null
@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu.wdo}
-view wave
-view structure
-view signals
-run 50us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu.wdo b/lib/CPUs/JCpu/sim/tb_cpu.wdo
deleted file mode 100644
index 2ef036e..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu.wdo
+++ /dev/null
@@ -1,107 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu/rst
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/ce
-add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
-add wave -noupdate -format Logic /tb_cpu/int_in
-add wave -noupdate -format Logic /tb_cpu/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
-add wave -noupdate -format Logic /tb_cpu/xmem_we
-add wave -noupdate -format Logic /tb_cpu/xmem_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
-add wave -noupdate -format Logic /tb_cpu/uut/io_sel
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -divider CPU
-add wave -noupdate -format Literal /tb_cpu/reg
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
-add wave -noupdate -format Literal /tb_cpu/uut/status_reg
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
-add wave -noupdate -format Literal /tb_cpu/uut/alu_status
-add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
-add wave -noupdate -format Logic /tb_cpu/uut/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/stk_we
-add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
-add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
-add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
-add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/status_save
-add wave -noupdate -format Logic /tb_cpu/uut/status_restore
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
-add wave -noupdate -divider Stack
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -divider Chipram
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -divider Sequencer
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
-add wave -noupdate -divider {Chip register}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
-add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {136355 ps} 0}
-configure wave -namecolwidth 166
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {93532 ps} {206468 ps}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo
deleted file mode 100644
index bf718fb..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo
+++ /dev/null
@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/cpu_embedded.vhd"
-vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vsim -t 1ps   -lib work tb_cpu_embedded
-do {tb_cpu_embedded.wdo}
-view wave
-view structure
-view signals
-run 10us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo
deleted file mode 100644
index caec2d7..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo
+++ /dev/null
@@ -1,26 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu_embedded/rst
-add wave -noupdate -format Logic /tb_cpu_embedded/clk
-add wave -noupdate -format Logic /tb_cpu_embedded/ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram
-add wave -noupdate -format Logic /tb_cpu_embedded/int_in
-add wave -noupdate -format Logic /tb_cpu_embedded/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2168142 ps} 0}
-configure wave -namecolwidth 143
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {10500 ns}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo
deleted file mode 100644
index 77ca67d..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo
+++ /dev/null
@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/itest_irom.vhdl"
-vcom -explicit  -93 "../src/tb_cpu_itest.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu_itest.wdo}
-view wave
-view structure
-view signals
-run 400us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo
deleted file mode 100644
index c3e2205..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo
+++ /dev/null
@@ -1,122 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu/rst
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Logic /tb_cpu/ce
-add wave -noupdate -format Logic /tb_cpu/int_in
-add wave -noupdate -format Logic /tb_cpu/int_ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr
-add wave -noupdate -format Logic /tb_cpu/xmem_we
-add wave -noupdate -format Logic /tb_cpu/xmem_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg
-add wave -noupdate -format Logic /tb_cpu/uut/io_sel
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr
-add wave -noupdate -divider CPU
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal /tb_cpu/uut/cpu_status
-add wave -noupdate -format Literal /tb_cpu/uut/status_reg
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result
-add wave -noupdate -format Literal /tb_cpu/uut/alu_status
-add wave -noupdate -format Logic /tb_cpu/uut/pc_inc
-add wave -noupdate -format Logic /tb_cpu/uut/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/cpu_active
-add wave -noupdate -format Logic /tb_cpu/uut/stk_we
-add wave -noupdate -format Logic /tb_cpu/uut/cmem_we
-add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase
-add wave -noupdate -format Logic /tb_cpu/uut/was_pcld
-add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc
-add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/status_save
-add wave -noupdate -format Logic /tb_cpu/uut/status_restore
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr
-add wave -noupdate -divider Stack
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -divider Chipram
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/ram
-add wave -noupdate -divider Sequencer
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem
-add wave -noupdate -divider {Chip register}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout
-add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/clk
-add wave -noupdate -divider {Interrup Ctrl.}
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
-add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {107309645 ps} 0}
-configure wave -namecolwidth 166
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {420 us}
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo
deleted file mode 100644
index aba9eda..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo
+++ /dev/null
@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/reti_issue_irom.vhdl"
-vcom -explicit  -93 "../src/tb_cpu_irq.vhd"
-vsim -t 1ps   -lib work tb_cpu
-do {tb_cpu_reti_issue.wdo}
-view wave
-view structure
-view signals
-run 50us
diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo
deleted file mode 100644
index d6d7e7e..0000000
--- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo
+++ /dev/null
@@ -1,90 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines
-add wave -noupdate -format Literal /tb_cpu/reg
-add wave -noupdate -format Logic /tb_cpu/int_in
-add wave -noupdate -format Logic /tb_cpu/int_ack
-add wave -noupdate -format Literal /tb_cpu/xmem_din
-add wave -noupdate -format Literal /tb_cpu/xmem_dout
-add wave -noupdate -format Literal /tb_cpu/xmem_addr
-add wave -noupdate -format Logic /tb_cpu/xmem_we
-add wave -noupdate -format Logic /tb_cpu/xmem_re
-add wave -noupdate -format Logic /tb_cpu/io_sel
-add wave -noupdate -format Literal /tb_cpu/sram
-add wave -noupdate -divider {Chip RAM}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a
-add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b
-add wave -noupdate -divider {Interrupt controller}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state
-add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out
-add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out
-add wave -noupdate -divider PC
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc
-add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next
-add wave -noupdate -divider {Stack controller}
-add wave -noupdate -format Literal /tb_cpu/uut/iphase
-add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout
-add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {47421482 ps}
diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo
deleted file mode 100644
index 5a852a4..0000000
--- a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo
+++ /dev/null
@@ -1,22 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/core/cpu_pkg.vhd"
-vcom -explicit  -93 "../src/core/stack_ctrl.vhd"
-vcom -explicit  -93 "../src/core/reg_dual.vhd"
-vcom -explicit  -93 "../src/core/chipram.vhd"
-vcom -explicit  -93 "../src/core/chipreg.vhd"
-vcom -explicit  -93 "../src/core/pc.vhd"
-vcom -explicit  -93 "../src/core/dpath_ctrl.vhd"
-vcom -explicit  -93 "../src/core/int_ctrl.vhd"
-vcom -explicit  -93 "../src/core/alu.vhd"
-vcom -explicit  -93 "../src/core/cpu.vhd"
-vcom -explicit  -93 "../src/cpu_embedded.vhd"
-vcom -explicit  -93 "../src/tb_cpu_embedded.vhd"
-vcom -explicit  -93 "../src/mul8x8_irom.vhdl"
-vsim -t 1ps   -lib work tb_cpu_embedded
-do {tb_mul8x8.wdo}
-view wave
-view structure
-view signals
-run 10us
diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo
deleted file mode 100644
index 355e0a4..0000000
--- a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk
-add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status
-add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {529679 ps} 0}
-configure wave -namecolwidth 143
-configure wave -valuecolwidth 101
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {9002500 ps} {10052500 ps}
diff --git a/lib/CPUs/JCpu/src/core/alu.vhd b/lib/CPUs/JCpu/src/core/alu.vhd
deleted file mode 100644
index 19b3478..0000000
--- a/lib/CPUs/JCpu/src/core/alu.vhd
+++ /dev/null
@@ -1,236 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity alu is
-	Generic (
-		data_width : integer := 8
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		op_en		: in  STD_LOGIC;
-		cy_in		: in  STD_LOGIC;
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		opsel		: in  alu_op_t;
-		res_out		: out unsigned (data_width-1 downto 0);
-		stat_load	: in  STD_LOGIC;
-		stat_in		: in  alu_status_t;
-		stat_out	: out alu_status_t
-	);
-end alu;
-
-architecture Behavioral of alu is
-
-	signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC;
-	signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0);
-	signal status, stat_reg : alu_status_t;
-	
-	--------------------------------------------------------------------------
-	function test_zero(arg : unsigned) return STD_LOGIC is
-	variable result : STD_LOGIC;
-	begin
-			result := '0';
-			for i in arg'range loop
-				result := result or To_X01(arg(i));
-			end loop;
-
-			return not result;
-	end test_zero;
-
---------------------------------------------------------------------------
-begin
-
---------------------------------------------------------------------------
-proc_logic_func: 
-	process (op1_in, op2_in, opsel)
-	begin
-		
-		case opsel is
-		when op1_and_op2 =>
-			lf_res <= op1_in and op2_in;
-		when op1_or_op2 =>
-			lf_res <= op1_in or op2_in;
-		when op1_xor_op2 =>
-			lf_res <= op1_in xor op2_in;
-		when others =>
-			lf_res <= (others => '-');
-		end case;
-
-	end process;	
-
---------------------------------------------------------------------------
-proc_shift_func: 
-	process (op1_in, left_shift, sh_cy_in)
-	begin
-		if left_shift = '1' then
-			sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in;
-			sh_cy <= op1_in(op1_in'left);
-		else	
-			sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1);
-			sh_cy <= op1_in(op1_in'right);
-		end if;	
-		
-	end process;	
-
---------------------------------------------------------------------------
-proc_alu_out:
-	process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in)
-
-	begin
-		
-		case opsel is
-		
-		when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= sum_cy;
-			result <= sum_res;
-		when op1_and_op2 | op1_or_op2 | op1_xor_op2 =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= stat_reg.carry;
-			result <= lf_res;
-		when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op =>
-			status.zero <= test_zero(res_reg);
-			status.carry <= sh_cy;
-			result <= sh_res;
-		when swap_op =>
-			result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2);
-			status <= stat_reg;
-		when others =>
-			result <= op2_in;
-			status.zero <= stat_reg.zero;
-			status.carry <= stat_reg.carry or cy_in;
-		end case;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_alu_in:
-	process(opsel, op1_in, stat_reg)
-
-	begin
-		
-		add_subn <= '-';
-		sum_cy_in <= '-';
-		sh_cy_in <= '-';
-		left_shift <= '-';
-
-		case opsel is
-		
-		when op1_add_op2 =>
-			sum_cy_in <= '0';
-			add_subn <= '1';
-
-		when op1_sub_op2 =>
-			sum_cy_in <= '0';
-			add_subn <= '0';
-	
-		when op1_addc_op2 => 
-			sum_cy_in <= stat_reg.carry;
-			add_subn <= '1';
-
-		when op1_subc_op2 => 
-			sum_cy_in <= stat_reg.carry;
-			add_subn <= '0';
-
-		when shl_op =>
-			sh_cy_in <= '0';
-			left_shift <= '1';
-			
-		when shr_op =>
-			sh_cy_in <= '0';
-			left_shift <= '0';
-
-		when rol_op =>
-			sh_cy_in <= op1_in(op1_in'left);
-			left_shift <= '1';
-
-		when ror_op =>
-			sh_cy_in <= op1_in(op1_in'right);
-			left_shift <= '0';
-
-		when rolc_op =>
-			sh_cy_in <= stat_reg.carry;
-			left_shift <= '1';
-
-		when rorc_op =>
-			sh_cy_in <= stat_reg.carry;
-			left_shift <= '0';
-
-		when others => null;
-
-		end case;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_res_reg:
-	process(clk, rst, op_en, stat_load, res_reg, stat_reg)
-	begin
-		if rst = '1' then
-			res_reg <= (others => '0');
-			stat_reg <= (others => '0');
-		elsif rising_edge(clk) then
-			if op_en = '1' then
-				res_reg <= result;
-				stat_reg <= status;
-			elsif stat_load = '1' then
-				stat_reg  <= stat_in;
-			end if;	
-		end if;
-		res_out <= res_reg;
-		stat_out <= stat_reg;
-
-	end process;
-
---------------------------------------------------------------------------
-alu_addsub:
-	process(op1_in, op2_in, sum_cy_in, add_subn)
-	variable sum  : unsigned(data_width+1 downto 0);
-	variable op1, op2 : unsigned(data_width+1 downto 0);
-	begin
-		if add_subn = '1' then
-			op1 := '0' & op1_in & '1';
-			op2 := '0' & op2_in & sum_cy_in;
-			sum := op1 + op2; 
-		else
-			op1 := '0' & op1_in & not sum_cy_in;
-			op2 := '0' & op2_in & '1';
-			sum := op1 - op2; 
-		end if;
-
-		-- Form sum + carry
-		sum_res <= sum(data_width downto 1);
-		sum_cy <= sum(sum'left);
-		
-	end process;	
-
---------------------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/chipram.vhd b/lib/CPUs/JCpu/src/core/chipram.vhd
deleted file mode 100644
index a954a77..0000000
--- a/lib/CPUs/JCpu/src/core/chipram.vhd
+++ /dev/null
@@ -1,85 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-chip RAM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity chipram is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end chipram;
-
-architecture Behavioral of chipram is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clka)
-begin
-if clka'event and clka = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clkb)
-begin
-if clkb'event and clkb = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd
deleted file mode 100644
index 6c5b9f1..0000000
--- a/lib/CPUs/JCpu/src/core/chipreg.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-Chip registers
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity chipreg is
-	Port (
-		rst			: in  STD_LOGIC; 
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		din			: in  dmem_data_t;
-		dout		: out dmem_data_t;
-		ctrl_in		: in  creg_ctrl_in_t;
-		ctrl_out	: out creg_ctrl_out_t
-	);
-end chipreg;
-
-architecture Behavioral of chipreg is
-
-	signal reg_bank_sel		: bank_sel_t;
-	signal reg_int_ctrl		: int_ctrl_in_t;
-	signal reg_stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-	signal reg_cmem_high	: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-
-begin
-
-proc_assign_ctrl_lines:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			ctrl_out.bank_sel	<= reg_bank_sel;
-			ctrl_out.int_ctrl	<= reg_int_ctrl;
-			ctrl_out.stk_high	<= reg_stk_high;
-			ctrl_out.cmem_high	<= reg_cmem_high;
-		end if;
-	end process;
-
-proc_reg_write:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			reg_stk_high <= (others => '0');
-			reg_cmem_high <= (others => '0');
-			reg_bank_sel <= (others => '0');
-			reg_int_ctrl.enable		<= '0';
-		elsif rising_edge(clk) then
-			if we = '1' then
-				case addr is
-				when X"01" =>
-					reg_bank_sel(bank_sel_t'range)	<= din(bank_sel_t'range);
-				when X"03" =>
-					reg_int_ctrl.enable		<= din(0);
-				when X"04" =>
-					reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-				when X"05" =>
-					reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-				when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-proc_reg_read:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			case addr is
-			when X"00" =>	-- Revison
-				dout <= to_unsigned(REVISION, dmem_data_t'length);
-			when X"01" =>	-- Control 0
-				dout <= (7 downto bank_sel_t'length => '0') & reg_bank_sel;
-			when X"02" =>	-- CPU status
-				dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
-			when X"03" =>	-- Interrupt control
-				dout <= "0000000" & reg_int_ctrl.enable;
-			when X"04" =>	-- Upper stack bits out
-				dout <= "0000" & reg_cmem_high;
-			when X"05" =>	-- Upper cmem bits out
-				dout <= "0000" & reg_stk_high;
-			when others => 
-				if addr(0) = '0' then
-					dout <= X"DE";
-				else
-					dout <= X"AD";
-				end if;
-			end case;
-			
-		end if;
-	end process;
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd
deleted file mode 100644
index 38e8686..0000000
--- a/lib/CPUs/JCpu/src/core/cpu.vhd
+++ /dev/null
@@ -1,563 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: JCPU top file 
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity cpu is
-	Generic (
-		use_instr_register	: boolean := false;
-		use_ctrl_rom		: boolean := true
-
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out std_logic
-	);
-end cpu;
-
-architecture rtl of cpu is
-
-	COMPONENT stack_ctrl
-	GENERIC (
-		addr_width	: integer
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		push		: in  STD_LOGIC;
-		pop			: in  STD_LOGIC;
-		din			: in  inst_addr_t;
-		dout		: out inst_addr_t;
-		mem_we		: out  STD_LOGIC;
-		ptr_out		: out unsigned (addr_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT pc
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		inc			: in  STD_LOGIC;
-		load		: in  STD_LOGIC;
-		pc_in		: in  inst_addr_t;
-		pc_out		: out inst_addr_t;
-		pc_next		: out inst_addr_t
-	);
-	END COMPONENT;
-
-	COMPONENT dpath_ctrl
-	GENERIC (
-		use_rom		: boolean
-	);
-	Port (
-		inst_in		: in  inst_t;
-		iphase_in	: in  iphase_t;
-		status_in	: in  cpu_status_t;
-		ctrl_out	: out dpath_ctrl_out_t;
-		idout		: out inst_addr_t;
-		ddout		: out dmem_data_t
-	);
-	END COMPONENT;
-
-	COMPONENT int_ctrl
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ctrl_in			: in  int_ctrl_in_t;
-		int_in			: in  STD_LOGIC;
-		int_exit		: in  STD_LOGIC;
-		iphase_in		: in  iphase_t;
-		int_ack_out		: out STD_LOGIC;
-		stat_save_out	: out STD_LOGIC; 
-		stat_rest_out	: out STD_LOGIC; 
-		pc_addr_out		: out inst_addr_t;
-		pc_load_out		: out STD_LOGIC;
-		stk_push_out	: out STD_LOGIC;
-		stk_pop_out		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	COMPONENT reg_dual
-	GENERIC (
-		addr_width	: integer;
-		data_width	: integer
-	);
-	Port (
-		clk			: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		ptr_a		: in  reg_ptr_t;
-		ptr_b		: in  reg_ptr_t;
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT chipram
-	GENERIC (
-		addr_width : integer;
-		data_width : integer
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT chipreg
-	Port (
-		rst			: in  STD_LOGIC; 
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		din			: in  dmem_data_t;
-		dout		: out dmem_data_t;
-		ctrl_in		: in  creg_ctrl_in_t;
-		ctrl_out	: out creg_ctrl_out_t
-	);
-	END COMPONENT;
-
-	COMPONENT alu
-	GENERIC (
-		data_width : integer := 8
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		op_en		: in  STD_LOGIC;
-		cy_in		: in  STD_LOGIC;
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		opsel		: in  alu_op_t;
-		res_out		: out unsigned (data_width-1 downto 0);
-		stat_load	: in  STD_LOGIC;
-		stat_in		: in  alu_status_t;
-		stat_out	: out alu_status_t
-	);
-	END COMPONENT;
-
-	signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0');
-	signal ctrl : dpath_ctrl_out_t;
-	signal stk_out : inst_addr_t;
-	signal stk_in : inst_addr_t;
-	signal stk_reg : inst_addr_t;
-	signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t;
-	signal iphase : iphase_t;
-	signal const_data, reg_a_dout, reg_b_dout : dmem_data_t;
-	signal reg_din : dmem_data_t;
-	signal alu_op1, alu_op2, alu_result : dmem_data_t;
-	signal alu_status : alu_status_t;
-	signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC;
-	signal ctrl_inst : inst_t;
-	signal ctrl_iphase : iphase_t;
-	signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC;
-	signal status_save, status_restore : STD_LOGIC;
-	signal creg_dout : dmem_data_t;
-	signal cmem_din, cmem_dout : inst_addr_t;
-	signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0);
-	signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0);
-	signal creg_ctrl_out : creg_ctrl_out_t;
-	signal creg_ctrl_in : creg_ctrl_in_t;
-	signal xio_sel, cio_sel : std_logic; 
-	signal mem_data : dmem_data_t;
-	signal mem_addr : dmem_data_t;
-	
-begin
-	io_sel <= xio_sel;
-	instr_addr <= pc_out;
-	pc_inc <= cpu_active and ctrl.lines.pc_inc;
-	stk_addr <= '0' & stk_ptr;
-	cpu_status.alu <= alu_status;
-	creg_ctrl_in.alu <= alu_status;
-
-	xmem_dout <= mem_data;
-	xmem_addr <= mem_addr;
-	cmem_din <= creg_ctrl_out.cmem_high & mem_data;
-	cmem_addr <= '1' & creg_ctrl_out.bank_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.bank_sel'length-1, mem_addr'length)-1 downto 0);
-
---------------------------------------------------------------------
-mem_ctrl_lines:
-	process(ctrl.lines)
-	begin
-		xio_sel <= '0';
-		xmem_re <= '0';
-		xmem_we <= '0';
-		cio_sel <= '0';
-		cmem_we <= '0';
-		creg_we <= '0';
-		
-		case ctrl.lines.mem_access is
-			when xmem_access =>
-				xmem_re <= ctrl.lines.mem_read;
-				xmem_we <= ctrl.lines.mem_write;
-			when xio_access =>
-				xio_sel <= '1';
-				xmem_re <= ctrl.lines.mem_read;
-				xmem_we <= ctrl.lines.mem_write;
-			when cmem_access =>
-				cmem_we <= ctrl.lines.mem_write;
-			when cio_access =>
-				cio_sel <= '1';
-				creg_we <= ctrl.lines.mem_write;
-			when others => null;
-		end case;
-	end process;
-
-iphase_counter:
-	process(rst, clk, ce)
-	variable pos : integer; 
-	begin
-		if rst = '1' then
-			iphase <= iphase_t'low;
-			cpu_active <= '0';
-		elsif rising_edge(clk) then
-			cpu_active <= '0';
-			if ce = '1' then
-				cpu_active <= '1';
-				if iphase = iphase_t'high then
-					iphase <= iphase_t'low;
-				else
-					iphase <= iphase + 1;
-				end if;
-			end if;	
-		end if;
-	end process;
-
-gen_instr_reg:
-if use_instr_register = true generate
-
-instr_reg:
-	process (rst, clk, ce)
-	begin
-		if rst = '1' then
-			ctrl_inst <= (others => '0');
-			ctrl_iphase <= 0;
-		elsif rising_edge(clk) and ce = '1' then
-			ctrl_inst <= instr_din;
-			ctrl_iphase <= iphase;
-		end if;
-	end process;
-
-end generate;
-	
-gen_instr_direct:
-if use_instr_register = false generate
-
-	ctrl_inst <= instr_din;
-	ctrl_iphase <= iphase;
-
-end generate;
-
-status_register:
-	process(clk, status_save)
-	begin
-		if rising_edge(clk) and status_save = '1' then
-			status_reg.alu <= alu_status;
-		end if;
-	end process;
-
-pc_pushpop:
-	process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc)
-	begin
-		pc_load <= ctrl.lines.pc_load or int_pc_load;
-		stk_push <= ctrl.lines.stk_push or (int_stk_push and not was_pop2pc);
-		stk_pop <= (ctrl.lines.stk_pop and not ctrl.lines.pc_load) or int_stk_pop or ((ctrl.lines.stk_pop and ctrl.lines.pc_load) and not int_pc_load);
-	end process;
-	
-lines_delay:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			was_pcld <= ctrl.lines.pc_load;
-			was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load;
-		end if;
-	end process;
-
-stk_mux:
-	process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out)
-	begin
-		if was_pcld = '1' and int_stk_push = '1' then 
-			stk_in <= idata;
-		elsif ctrl.lines.stk_push = '1' and ctrl.lines.pc_load = '0' then
-			stk_in <= creg_ctrl_out.stk_high & reg_a_dout;
-		else	
-			stk_in <= pc_next;
-		end if;	
-		
-	end process;
-
-pc_mux:
-	process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out)
-	begin
-		
-		pc_in <= stk_out;
-		if int_pc_load = '1' then 
-			if int_stk_pop = '0' then
-				pc_in <= int_pc_addr;
-			end if;	
-		elsif ctrl.lines.pc_load = '1' then
-			if ctrl.lines.stk_pop = '0' then
-				pc_in <= idata;
-			end if;	
-		end if;	
-
-	end process;
-
-mem_data_mux:
-	process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out)
-	begin
-		case ctrl.lines.ddata_src_sel is
-		when reg_a => 
-			mem_data <= reg_a_dout;
-		when reg_b =>
-			mem_data <= reg_b_dout;
-		when const =>
-			mem_data <= const_data;
-		when others =>
-			mem_data <= const_data;
-		end case;
-
-	end process;
-
-mem_addr_mux:
-	process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.bank_sel)
-	begin
-		case ctrl.lines.daddr_src_sel is
-		when reg_a => 
-			mem_addr <= reg_a_dout;
-		when reg_b =>
-			mem_addr <= reg_b_dout;
-		when const =>
-			mem_addr <= const_data;
-		when others =>
-			mem_addr <= const_data;
-		end case;
-
-	end process;
-
-reg_in_mux:
-	process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.reg_src_sel is
-		when xmem_src =>
-			data := xmem_din;
-		when cmem_src =>
-			if cio_sel = '0' then
-				data := cmem_dout(dmem_data_t'range);
-			else
-				data := creg_dout(dmem_data_t'range);
-			end if;
-		when stk_src =>
-			data := stk_out(dmem_data_t'range);
-		when others =>
-			data := alu_result;
-		end case;
-
-		reg_din <= data;
-
-	end process;
-
-alu_op1_mux:
-	process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.alu_op1_src_sel is
-		when reg_a =>
-			data := reg_a_dout;
-		when reg_b =>
-			data := reg_b_dout;
-		when others =>
-			data := const_data;
-		end case;
-
-		alu_op1 <= data;
-
-	end process;
-
-alu_op2_mux:
-	process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data)
-	variable data : dmem_data_t;
-	begin
-		case ctrl.lines.alu_op2_src_sel is
-		when reg_a =>
-			data := reg_a_dout;
-		when reg_b =>
-			data := reg_b_dout;
-		when others =>
-			data := const_data;
-		end case;
-
-		alu_op2 <= data;
-
-	end process;
-
---------------------------------------------------------------------
-	inst_stack_ctrl: stack_ctrl
-	GENERIC MAP (
-		addr_width	=> STACK_SIZE_BITS
-	)
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		push		=> stk_push,
-		pop			=> stk_pop,
-		dout		=> stk_reg,
-		din			=> stk_in,
-		ptr_out		=> stk_ptr,
-		mem_we		=> stk_we
-	);
-
-	inst_pc: pc
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		inc			=> pc_inc,
-		load		=> pc_load,
-		pc_in		=> pc_in,
-		pc_out		=> pc_out,
-		pc_next		=> pc_next
-	);
-
-	inst_dpath_ctrl: dpath_ctrl
-	GENERIC MAP (
-		use_rom		=> use_ctrl_rom
-	)
-	PORT MAP(
-		inst_in		=> ctrl_inst,
-		iphase_in   => ctrl_iphase,
-		status_in	=> cpu_status,
-		ctrl_out	=> ctrl,
-		ddout		=> const_data,
-		idout		=> idata
-	);
-	
-	inst_int_ctrl: int_ctrl
-	PORT MAP(
-		rst				=> rst,
-		clk				=> clk,
-		ctrl_in			=> creg_ctrl_out.int_ctrl,
-		int_in			=> int_in,
-		int_ack_out		=> int_ack,
-		int_exit		=> ctrl.lines.int_exit,
-		iphase_in		=> ctrl_iphase,
-		stat_save_out	=> status_save,
-		stat_rest_out	=> status_restore,
-		pc_addr_out		=> int_pc_addr,
-		pc_load_out		=> int_pc_load,
-		stk_push_out	=> int_stk_push,
-		stk_pop_out		=> int_stk_pop
-		
-	);
-	
-	inst_reg_ab: reg_dual
-	GENERIC MAP (
-		addr_width	=> REG_SIZE_BITS,
-		data_width	=> DMEM_DATA_WIDTH
-	)
-	PORT MAP(
-		clk			=> clk,
-		we_a		=> ctrl.lines.reg_we,
-		ptr_a		=> ctrl.reg_a_ptr,
-		ptr_b		=> ctrl.reg_b_ptr,
-		din_a		=> reg_din,
-		dout_a		=> reg_a_dout,
-		dout_b		=> reg_b_dout
-	);
-
-	inst_chipram: chipram
-	GENERIC MAP (
-		addr_width	=> CHIPRAM_SIZE_BITS,
-		data_width	=> IMEM_ADDR_WIDTH
-	)
-	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
-		en_a		=> cpu_active,
-		en_b		=> cpu_active,
-		we_a		=> stk_we,
-		we_b		=> cmem_we,
-		addr_a		=> stk_addr,
-		addr_b		=> cmem_addr,
-		din_a		=> stk_reg,
-		din_b		=> cmem_din,
-		dout_a		=> stk_out,
-		dout_b		=> cmem_dout
-	);
-
-	inst_chipreg: chipreg
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		we			=> creg_we,
-		addr		=> mem_addr,
-		din			=> mem_data,
-		dout		=> creg_dout,
-		ctrl_in		=> creg_ctrl_in,
-		ctrl_out	=> creg_ctrl_out
-	);
-
-	inst_alu: alu
-	GENERIC MAP (
-		data_width	=> DMEM_DATA_WIDTH
-	)
-	PORT MAP(
-		rst			=> rst,
-		clk			=> clk,
-		op_en		=> ctrl.lines.alu_load,
-		cy_in		=> ctrl.lines.alu_cy_in,
-		op1_in		=> alu_op1,
-		op2_in		=> alu_op2,
-		opsel		=> ctrl.lines.alu_opsel,
-		res_out		=> alu_result,
-		stat_load	=> status_restore,
-		stat_in		=> status_reg.alu,
-		stat_out	=> alu_status
-	);
-
-end rtl;
diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
deleted file mode 100644
index 91bdae2..0000000
--- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd
+++ /dev/null
@@ -1,852 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Types, constants and functions for JCPU
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-
-package cpu_pkg is
-
-	-- Revision of the CPU
-	constant REVISION : integer := 4;
-	
-	-- Chipram depth (valid values 9..floor(log2(BlockRamBytes)))
-	constant CHIPRAM_SIZE_BITS : integer := 10;
-	
-	-- Number of registers (16 registers fixed)
-	constant REG_SIZE_BITS : integer := 4;
-	
-	-- Instruction memory
-	constant IMEM_ADDR_WIDTH : integer := 12;
-	
-	-- Data memory
-	constant DMEM_DATA_WIDTH : integer := 8;
-	constant DMEM_ADDR_WIDTH : integer := 8;
-	
-	-- Instruction format
-	constant INST_OPCODE_WIDTH : integer := 6;
-	constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS;
-
-	-- Microcode ROM
-	constant MUCODE_ADDR_WIDTH : integer := 9;
-	
-	-- Stack depth (uses lower half of CHIPRAM)
-	constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1;
-
-	--Types
-	subtype iphase_t is integer range 0 to 1;
-	type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access);
-	type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src);
-	type alu_src_t is (reg_a, reg_b, const);
-	type ddata_src_t is (reg_a, reg_b, const);
-	type daddr_src_t is (reg_a, reg_b, const);
-	subtype instr_name_t is string(1 to 12);
-	type instr_name_array_t is array (0 to 63) of instr_name_t;
-	subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0);
-	subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0);
-	subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	subtype reg_ptr_t is unsigned (3 downto 0);
-	type dmem_array_t is array (natural range <>) of dmem_data_t;
-	type instr_addr_array is array (integer range <>) of inst_addr_t;
-	subtype bank_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0);
-	
-	type alu_op_t is
-	(
-		pass_op2,
-		op1_add_op2,
-		op1_sub_op2,
-		op1_addc_op2,
-		op1_subc_op2,
-		op1_and_op2,
-		op1_or_op2,
-		op1_xor_op2,
-		swap_op,
-		shl_op,
-		shr_op,
-		rol_op,
-		ror_op,
-		rolc_op,
-		rorc_op
-	);
-	
-	type alu_status_t is record
-		zero		: STD_LOGIC;
-		carry		: STD_LOGIC;
-	end record;
-
-	type cpu_status_t is record
-		alu			: alu_status_t;
-	end record;
-
-	type ctrl_lines_t is record
-		reg_we			: STD_LOGIC;
-		reg_src_sel		: reg_src_t;
-		alu_op1_src_sel	: alu_src_t;
-		alu_op2_src_sel	: alu_src_t;
-		alu_opsel		: alu_op_t;
-		alu_load		: STD_LOGIC;
-		alu_cy_in		: STD_LOGIC;
-		ddata_src_sel	: ddata_src_t;
-		daddr_src_sel	: daddr_src_t; 
-		pc_load			: STD_LOGIC;
-		pc_inc			: STD_LOGIC;
-		stk_push		: STD_LOGIC; 
-		stk_pop			: STD_LOGIC;
-		mem_access		: mem_access_t;
-		mem_read		: STD_LOGIC;
-		mem_write		: STD_LOGIC;
-		int_exit		: STD_LOGIC;
-	end record;
-
-	type dpath_ctrl_out_t is record
-		lines			: ctrl_lines_t;
-		reg_a_ptr		: reg_ptr_t;
-		reg_b_ptr		: reg_ptr_t;
-	end record;
-	
-	type int_ctrl_in_t is record
-		enable			: std_logic;
-	end record;
-	
-	type creg_ctrl_out_t is record
-		bank_sel		: bank_sel_t;
-		int_ctrl		: int_ctrl_in_t;
-		stk_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-		cmem_high		: unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
-	end record;
-	
-	type creg_ctrl_in_t is record
-		alu				: alu_status_t;
-	end record;
-
-	
-	type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t;
-
-	constant instr_name_array : instr_name_array_t := 
-	(
-		"NOP         ", -- 00
-		"HALT        ", -- 01
-		"MOV|R|R     ", -- 02
-		"MOV|R|K     ", -- 03
-		"MOVX|R|Ri   ", -- 04
-		"MOVX|R|Ki   ", -- 05
-		"MOVX|Ri|R   ", -- 06
-		"MOVX|Ri|K   ", -- 07
-		"MOVX|Ki|R   ", -- 08
-		"MOVC|R|Ri   ", -- 09
-		"MOVC|R|Ki   ", -- 0A
-		"MOVC|Ri|R   ", -- 0B
-		"MOVC|Ri|K   ", -- 0C
-		"MOVC|Ki|R   ", -- 0D
-		"CMP|R|R     ", -- 0E
-		"CMP|R|K     ", -- 0F
-		"ADD|R|R     ", -- 10
-		"ADD|R|K     ", -- 11
-		"ADDC|R|R    ", -- 12
-		"ADDC|R|K    ", -- 13
-		"SUB|R|R     ", -- 14
-		"SUB|R|K     ", -- 15
-		"SUBC|R|R    ", -- 16
-		"SUBC|R|K    ", -- 17
-		"AND|R|R     ", -- 18
-		"AND|R|K     ", -- 19
-		"OR|R|R      ", -- 1A
-		"OR|R|K      ", -- 1B
-		"XOR|R|R     ", -- 1C
-		"XOR|R|K     ", -- 1D
-		"SHL|R       ", -- 1E
-		"SHR|R       ", -- 1F
-		"ROL|R       ", -- 20
-		"ROR|R       ", -- 21
-		"ROLC|R      ", -- 22
-		"RORC|R      ", -- 23
-		"XOUT|Ki|R   ", -- 24
-		"XOUT|Ri|K   ", -- 25
-		"COUT|Ki|R   ", -- 26
-		"COUT|Ri|K   ", -- 27
-		"XIN|R|Ki    ", -- 28
-		"CIN|R|Ki    ", -- 29
-		"SWAP|R      ", -- 2A
-		"SETC        ", -- 2B
-		"UNDEF       ", -- 2C
-		"UNDEF       ", -- 2D
-		"SUB|K|R     ", -- 2E
-		"SUBC|K|R    ", -- 2F
-		"JMP|K       ", -- 30
-		"JZ|K        ", -- 31
-		"JNZ|K       ", -- 32
-		"JC|K        ", -- 33
-		"JNC|K       ", -- 34
-		"JLT|K       ", -- 35
-		"JGT|K       ", -- 36
-		"JLE|K       ", -- 37
-		"JGE|K       ", -- 38
-		"JEQ|K       ", -- 39
-		"JNE|K       ", -- 3A
-		"CALL|K      ", -- 3B
-		"PUSH|R      ", -- 3C
-		"POP|R       ", -- 3D
-		"RET         ", -- 3E
-		"RETI        "  -- 3F
-	);
-	-- Functions
-	function Instr(opcode : opcode_t) return inst_t;
-	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t;
-	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t;
-	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t;
-	function ctrl_lines_default return ctrl_lines_t;
-	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
-	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t;
-	function gen_murom return murom_t;
-	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned;
-	function MIN (X, Y: INTEGER) return INTEGER;
-	function MAX (X, Y: INTEGER) return INTEGER;
-
-end cpu_pkg;
-
-package body cpu_pkg is
-
-	function Instr(opcode : opcode_t) return inst_t is
-	variable inst : inst_t := (others => '0'); 
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is
-	variable inst : inst_t := (others => '0'); 
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data;
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data;
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is
-	variable inst : inst_t := (others => '0');
-	begin
-		inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode;
-		inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length));
-		inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length));
-		inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length));
-
-		return inst;
-
-	end Instr;
-
-	function ctrl_lines_default return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	begin
-		result.pc_load := '0';
-		result.pc_inc := '0';
-		result.stk_push := '0';
-		result.stk_pop := '0';
-		result.reg_we := '0';
-		result.reg_src_sel := alu_src;
-		result.ddata_src_sel := reg_a;
-		result.daddr_src_sel := reg_b;
-		result.alu_opsel := pass_op2;
-		result.alu_op1_src_sel := reg_a;
-		result.alu_op2_src_sel := reg_b;
-		result.alu_load := '0';
-		result.alu_cy_in := '0';
-		result.mem_access := cmem_access;
-		result.mem_read := '0';
-		result.mem_write := '0';
-		result.int_exit := '0';
-		return result;
-	
-	end ctrl_lines_default;
-
-	function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
-	variable instr_name : instr_name_t;
-	begin
-		instr_name := instr_name_array(to_integer(opcode));
-		return idecoder(instr_name, iphase, status);
-	end idecoder;
-
-	function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	variable ze, cy : STD_LOGIC;
-	
-	begin
-		ze			:= status.alu.zero;
-		cy			:= status.alu.carry;
-		
-		result := ctrl_lines_default;
-		if iphase = 0 then
-			result.pc_inc := '1';
-		end if;
-
-		case instr_name is
-
-		when "HALT        " =>
-			result.pc_inc := '0';
-		when "SETC        " => -- carry <= 1
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-			result.alu_cy_in := '1';
-		when "MOV|R|R     " => -- R(a) <= R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOV|R|K     " => -- R(a) <= #kk
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := pass_op2;
-			result.alu_op2_src_sel := const;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|Ri|R   " => -- [R(b)] <= R(a)
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := reg_b;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVC|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "COUT|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := cio_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVC|R|Ri   " => -- R(a) <= [R(b)]
-			result.mem_access := cmem_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := reg_b;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|R|Ki   " => -- R(a) <= [#addr]
-			result.mem_access := cmem_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CIN|R|Ki    " => -- R(a) <= [#addr]
-			result.mem_access := cio_access;
-			result.reg_src_sel := cmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "MOVC|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := cmem_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "COUT|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := cio_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|Ri|R   " => -- [R(b)] <= R(a)
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := reg_b;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "XOUT|Ri|K   " => -- [R(a)] <= kk
-			result.mem_access := xio_access;
-			result.daddr_src_sel := reg_a;
-			result.ddata_src_sel := const;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "MOVX|R|Ri   " => -- R(a) <= [R(b)]
-			result.mem_access := xmem_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := reg_b;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "MOVX|R|Ki   " => -- R(a) <= [#addr]
-			result.mem_access := xmem_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "XIN|R|Ki    " => -- R(a) <= [#addr]
-			result.mem_access := xio_access;
-			result.reg_src_sel := xmem_src;
-			result.daddr_src_sel := const;
-			if iphase = 0 then
-				result.mem_read := '1';
-			elsif iphase = 1 then
-					result.reg_we := '1';
-				end if;
-		when "MOVX|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := xmem_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "XOUT|Ki|R   " => -- [#addr] <= R(a)
-			result.mem_access := xio_access;
-			result.daddr_src_sel := const;
-			result.ddata_src_sel := reg_a;
-			if iphase = 0 then
-				result.mem_write := '1';
-			end if;
-		when "ADD|R|R     " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_add_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADD|R|K     " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_add_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADDC|R|R    " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_addc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ADDC|R|K    " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_addc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|R|R     " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|R|K     " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUB|K|R     " => -- R(a) <= k - R(a)
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := const;
-			result.alu_op2_src_sel := reg_a;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|R|R    " => -- R(a) <= R(a) + R(b)
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|R|K    " => -- R(a) <= R(a) + k
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SUBC|K|R    " => -- R(a) <= K - R(a)
-			result.alu_opsel := op1_subc_op2;
-			result.alu_op1_src_sel := const;
-			result.alu_op2_src_sel := reg_a;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "AND|R|R     " => -- R(a) <= R(a) and R(b)
-			result.alu_opsel := op1_and_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "AND|R|K     " => -- R(a) <= R(a) and k
-			result.alu_opsel := op1_and_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "OR|R|R      " => -- R(a) <= R(a) or R(b)
-			result.alu_opsel := op1_or_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "OR|R|K      " => -- R(a) <= R(a) or R(b)
-			result.alu_opsel := op1_or_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "XOR|R|R     " => -- R(a) <= R(a) xor R(b)
-			result.alu_opsel := op1_xor_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "XOR|R|K     " => -- R(a) <= R(a) xor R(b)
-			result.alu_opsel := op1_xor_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.reg_src_sel := alu_src;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SWAP|R      " => -- R(a) <= R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := swap_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SHL|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := shl_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "SHR|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := shr_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROL|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rol_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROR|R       " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := ror_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "ROLC|R      " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rolc_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "RORC|R      " => -- R(a) <= R(a) xor R(b)
-			result.reg_src_sel := alu_src;
-			result.alu_opsel := rorc_op;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_load := '1';
-			if iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CMP|R|R     " => -- 
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := reg_b;
-			result.alu_load := '1';
-		when "CMP|R|K     " => -- 
-			result.alu_opsel := op1_sub_op2;
-			result.alu_op1_src_sel := reg_a;
-			result.alu_op2_src_sel := const;
-			result.alu_load := '1';
-		when "JMP|K       " => -- PC <= #addr
-			if iphase = 0 then
-				result.pc_load := '1';
-			end if;
-		when "JZ|K        " => -- PC <= #addr, zero
-			if iphase = 0 then
-				if ze = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNZ|K       " => -- PC <= #addr, !zero
-			if iphase = 0 then
-				if ze = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JC|K        " => -- PC <= #addr, carry
-			if iphase = 0 then
-				if cy = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNC|K       " => -- PC <= #addr, !carry
-			if iphase = 0 then
-				if cy = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JLT|K       " => -- PC <= #addr, !carry
-			if iphase = 0 then
-				if cy = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JGT|K       " => -- 
-			if iphase = 0 then
-				if (cy or ze) = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JLE|K       " => -- 
-			if iphase = 0 then
-				if (cy xor ze) = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JGE|K       " => -- 
-			if iphase = 0 then
-				if (not cy or ze) = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JEQ|K       " => -- 
-			if iphase = 0 then
-				if ze = '1' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "JNE|K       " => -- 
-			if iphase = 0 then
-				if ze = '0' then
-					result.pc_load := '1';
-				end if;
-			end if;
-		when "PUSH|R      " => -- push
-			if iphase = 0 then
-				result.stk_push := '1';
-			end if;
-		when "POP|R       " => -- pop
-			result.reg_src_sel := stk_src;
-			if iphase = 0 then
-				result.stk_pop := '1';
-			elsif iphase = 1 then
-				result.reg_we := '1';
-			end if;
-		when "CALL|K      " => -- call
-			if iphase = 0 then
-				result.pc_load := '1';
-				result.stk_push := '1';
-			end if;
-		when "RET         " => -- return
-			if iphase = 0 then
-				result.pc_load := '1';
-				result.stk_pop := '1';
-			end if;
-		when "RETI        " => -- return
-			result.pc_inc := '0';
-			result.int_exit := '1';
-			
-		when others => null; -- nop
-		end case;
-
-		return result;
-
-	end idecoder;
-
-	function gen_murom return murom_t is
-	variable result : murom_t; 
-	variable opcode : opcode_t;
-	variable iphase : iphase_t;
-	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-	variable status : cpu_status_t;
-	variable pos : integer := 0;
-	
-	begin
-		for i in 0 to 2**addr'length-1 loop
-			addr := to_unsigned(i, addr'length);
-			opcode := addr(opcode'length-1 downto 0);
-			pos := opcode'length;
-			iphase := 0;
-			if addr(pos) = '1' then
-				iphase := 1;
-			end if;
-			pos := pos + 1;
-			status.alu.zero := addr(pos);
-			pos := pos + 1;
-			status.alu.carry := addr(pos);
-			
-			result(i) := idecoder(opcode, iphase, status);
-		end loop;
-
-		return result;
-	end gen_murom;
-
-	function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is
-	variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-	begin
-		addr := status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode;
-		return addr;
-		
-	end get_muromaddr;
-
-	-------------------------------------------------------------
-	function MIN (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y < X then
-		res := Y;
-	end if;
-
-	return res;
-
-	end MIN;
-
-	-------------------------------------------------------------
-	function MAX (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y > X then
-		res := Y;
-	end if;
-
-	return res;
-	
-	end MAX;
-
-
-end cpu_pkg;
-
diff --git a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd
deleted file mode 100644
index 1610d00..0000000
--- a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd
+++ /dev/null
@@ -1,87 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The datapath controller
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity dpath_ctrl is
-	Generic (
-		use_rom		: boolean := true
-	);
-	Port (
-		inst_in		: in  inst_t;
-		iphase_in	: in  iphase_t;
-		status_in	: in  cpu_status_t;
-		ctrl_out	: out dpath_ctrl_out_t;
-		idout		: out inst_addr_t;
-		ddout		: out dmem_data_t
-	);
-end dpath_ctrl;
-
-architecture Behavioral of dpath_ctrl is
-
-	signal opcode : opcode_t;
-	signal ctrl_lines : ctrl_lines_t;
-	signal dbg_iname : instr_name_t;
-	
-begin
-
-	idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0);
-	ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS);
-	opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH);
-
-	ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0);
-	ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length);
-	ctrl_out.lines <= ctrl_lines;
-
-	-- pragma translate_off
-	dbg_iname <= instr_name_array(to_integer(opcode));
-	-- pragma translate_on
-
-gen_ctrl_rom:
-if use_rom = true generate
-
-	i_dec:
-		process(opcode, iphase_in, status_in)
-		constant rom_data : murom_t := gen_murom;
-		variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0);
-		begin
-			addr := get_muromaddr(opcode, iphase_in, status_in);
-			ctrl_lines <= rom_data(to_integer(addr));
-		end process;
-end generate;
-
-gen_ctrl:
-if use_rom = false generate
-	i_dec:
-		process (opcode, iphase_in, status_in)
-		begin
-			ctrl_lines <= idecoder(opcode, iphase_in, status_in);
-		end process;
-end generate;
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd
deleted file mode 100644
index ebff3db..0000000
--- a/lib/CPUs/JCpu/src/core/int_ctrl.vhd
+++ /dev/null
@@ -1,138 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Interrupt controller 
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity int_ctrl is
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		ctrl_in			: in  int_ctrl_in_t;
-		int_in			: in  STD_LOGIC;
-		int_exit		: in  STD_LOGIC;
-		iphase_in		: in  iphase_t;
-		pc_addr_out		: out inst_addr_t;
-		int_ack_out		: out STD_LOGIC;
-		stat_save_out	: out STD_LOGIC; 
-		stat_rest_out	: out STD_LOGIC; 
-		pc_load_out		: out STD_LOGIC;
-		stk_push_out	: out STD_LOGIC;
-		stk_pop_out		: out STD_LOGIC
-	);
-end int_ctrl;
-
-architecture Behavioral of int_ctrl is
-
-	type int_state_t is (int_idle, int_inject, int_active, int_release);
-	
-	signal int_state, int_state_next : int_state_t;
-	signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
-	signal int_request : std_logic;
-	
-	
-begin
-
-	int_ack_out		<= int_ack;
-	pc_load_out		<= pc_load;
-	stk_push_out	<= stk_push;
-	stk_pop_out		<= stk_pop;
-	
------------------------------------------------------------------------
-irg_ctrl_fsm:
-	process (int_state, iphase_in, int_request, int_exit)
-	begin
-
-		pc_addr_out <= to_unsigned(1, inst_addr_t'length);
-		int_state_next <= int_state;
-		int_ack <= '0';
-		pc_load <= '0';
-		stk_push <= '0';
-		stk_pop <= '0';
-		case int_state is
-		
-		when int_idle =>
-			if int_request = '1' and iphase_in = 1 then
-				int_state_next <= int_inject;
-			end if;
-		when int_inject =>
-			if iphase_in = 0 then
-				int_ack <= '1';
-				pc_load <= '1';
-			elsif iphase_in = 1 then
-				stk_push <= '1';
-				int_state_next <= int_active;
-			end if;
-		when int_active =>
-			if int_exit = '1' and iphase_in = 1 then
-				int_state_next <= int_release;
-			end if;
-		when int_release =>
-			if iphase_in = 0 then
-				stk_pop <= '1';
-				pc_load <= '1';
-			elsif iphase_in = 1 then
-				int_state_next <= int_idle;
-			end if;	
-		when others => 	
-			int_state_next <= int_idle;
-		end case;	
-			
-	end process;
-	
-irq_ctrl_states:
-	process (rst, clk, int_state_next)
-	begin
-		if rst = '1' then
-			int_state <= int_idle;
-		elsif rising_edge(clk) then
-			int_state <= int_state_next;
-		end if;
-	end process;
-
------------------------------------------------------------------------
-pin_sample:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			int_request <= '0';
-			if ctrl_in.enable = '1' then
-				int_request <= int_in;
-			end if;	
-		end if;
-	end process;
-
------------------------------------------------------------------------
-stat_save_restore:
-	process (clk, stk_push, stk_pop)
-	begin
-		if rising_edge(clk) then
-			stat_save_out <= stk_push;
-			stat_rest_out <= stk_pop;
-		end if;
-	end process;
-
-end Behavioral;
diff --git a/lib/CPUs/JCpu/src/core/pc.vhd b/lib/CPUs/JCpu/src/core/pc.vhd
deleted file mode 100644
index 6b1d575..0000000
--- a/lib/CPUs/JCpu/src/core/pc.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Programm counter
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity pc is
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		inc			: in  STD_LOGIC;
-		load		: in  STD_LOGIC;
-		pc_in		: in  inst_addr_t;
-		pc_out		: out inst_addr_t;
-		pc_next		: out inst_addr_t
-	);
-end pc;
-
-architecture Behavioral of pc is
-
-begin
-
-proc_pc:
-	process(rst, clk, inc, load, pc_in)
-	variable vpc, vpc_reg: inst_addr_t;
-	begin
-		if rst = '1' then
-			vpc_reg := (others => '0');
-		elsif rising_edge(clk) then
-			if inc = '1' or load = '1' then
-				vpc_reg := vpc;
-			elsif inc = '0'	then
-				pc_next <= vpc;		
-			end if;
-		end if;
-		
-		if load = '1' then
-			vpc := pc_in;	
-		else
-			vpc := vpc_reg + 1;
-		end if;	
-		pc_out <= vpc_reg;
-		
-	end process;
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/reg_dual.vhd b/lib/CPUs/JCpu/src/core/reg_dual.vhd
deleted file mode 100644
index 6b7e4d8..0000000
--- a/lib/CPUs/JCpu/src/core/reg_dual.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: On-Chip work registers
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity reg_dual is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk			: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		ptr_a		: in  reg_ptr_t;
-		ptr_b		: in  reg_ptr_t;
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end reg_dual;
-
-architecture Behavioral of reg_dual is
-
-	constant depth : integer := 2**addr_width;
-	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0');
-
-	signal mem : mem_t;
-begin
-
-	addr_a <= TO_01(ptr_a(addr_width-1 downto 0));
-	addr_b <= TO_01(ptr_b(addr_width-1 downto 0));
-
-reg_in_ab:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if we_a = '1' then
-				mem(to_integer(addr_a)) <= din_a;
-			end if;
-		end if;	
-	end process;
-
-reg_out_a:
-	process(mem, addr_a)
-	begin
-		dout_a <= TO_01(mem(to_integer(addr_a)));
-	end process;
-
-reg_out_b:
-	process(mem, addr_b)
-	begin
-		dout_b <= TO_01(mem(to_integer(addr_b)));
-	end process;
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd
deleted file mode 100644
index 7eccae3..0000000
--- a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
---------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The call/return/data stack
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity stack_ctrl is
-Generic (
-	addr_width : integer := 3
-);
-Port (
-	rst			: in  STD_LOGIC;
-	clk			: in  STD_LOGIC;
-	push		: in  STD_LOGIC;
-	pop			: in  STD_LOGIC;
-	ptr_out		: out unsigned (addr_width-1 downto 0);
-	din			: in  inst_addr_t;
-	dout		: out inst_addr_t;
-	mem_we		: out STD_LOGIC
-	);
-end stack_ctrl;
-
-architecture Behavioral of stack_ctrl is
-
-	signal ptr : unsigned (addr_width-1 downto 0);
-
-begin
-
-	ptr_out <= ptr;
-
-stk_ptr:
-	process(rst, clk, ptr, push, pop)
-	begin
-		if rst = '1' then
-			ptr <= (others => '0');
-			dout <= (others => '0');
-			mem_we <= '0';
-		elsif rising_edge(clk) then
-			mem_we <= push;
-			if push = '1' then
-				ptr <= ptr + 1;
-				dout <= din;
-			elsif pop = '1' then
-				ptr <= ptr - 1;
-			end if;
-		end if;
-	end process;
-
-end Behavioral;
-
diff --git a/lib/CPUs/JCpu/src/cpu_embedded.vhd b/lib/CPUs/JCpu/src/cpu_embedded.vhd
deleted file mode 100644
index 56c6dec..0000000
--- a/lib/CPUs/JCpu/src/cpu_embedded.vhd
+++ /dev/null
@@ -1,106 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.cpu_pkg.all;
-
-entity cpu_embedded is
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-end cpu_embedded;
-
-architecture rtl of cpu_embedded is
-
-	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0);
-	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-
-	COMPONENT cpu
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-
-	COMPONENT irom
-		Port (
-			clk			: in  STD_LOGIC;
-			ce			: in  STD_LOGIC;
-			addr		: in  inst_addr_t;
-			dout		: out inst_t
-		);
-	END COMPONENT;
-
-begin
-
-inst_cpu: cpu
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		instr_din => irom_data,
-		instr_addr => irom_addr,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-inst_irom: irom
-	PORT MAP(
-		clk			=> clk,
-		ce			=> ce,
-		addr		=> irom_addr,
-		dout 		=> irom_data
-	);
-
-end rtl;
diff --git a/lib/CPUs/JCpu/src/dctest_irom.vhdl b/lib/CPUs/JCpu/src/dctest_irom.vhdl
deleted file mode 100644
index 7987a15..0000000
--- a/lib/CPUs/JCpu/src/dctest_irom.vhdl
+++ /dev/null
@@ -1,79 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE dctest OF irom IS 
-
-	type imem_rom_t is array (0 to 17) of inst_t;
-
-	-- Assembled from dctest.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"010", -- 0x000: JMP 0x010
-		"110000" & X"011", -- 0x001: JMP 0x011
-		"000000" & X"000", -- 0x002:
-		"000000" & X"000", -- 0x003:
-		"000000" & X"000", -- 0x004:
-		"000000" & X"000", -- 0x005:
-		"000000" & X"000", -- 0x006:
-		"000000" & X"000", -- 0x007:
-		"000000" & X"000", -- 0x008:
-		"000000" & X"000", -- 0x009:
-		"000000" & X"000", -- 0x00A:
-		"000000" & X"000", -- 0x00B:
-		"000000" & X"000", -- 0x00C:
-		"000000" & X"000", -- 0x00D:
-		"000000" & X"000", -- 0x00E:
-		"000000" & X"000", -- 0x00F:
-		"110000" & X"010", -- 0x010: JMP 0x010
-		"111111" & X"000"  -- 0x011: RETI
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end dctest;
-
diff --git a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl
deleted file mode 100644
index 223dd46..0000000
--- a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl
+++ /dev/null
@@ -1,1181 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from dctest.jsm
-	type imem_rom_t is array (0 to 1023) of inst_t;
-	signal imem_rom : imem_rom_t :=
-	(
-		"110000" & X"010", -- 0x000: JMP 0x010
-		"110000" & X"011", -- 0x001: JMP 0x011
-		"000000" & X"000", -- 0x002:
-		"000000" & X"000", -- 0x003:
-		"000000" & X"000", -- 0x004:
-		"000000" & X"000", -- 0x005:
-		"000000" & X"000", -- 0x006:
-		"000000" & X"000", -- 0x007:
-		"000000" & X"000", -- 0x008:
-		"000000" & X"000", -- 0x009:
-		"000000" & X"000", -- 0x00A:
-		"000000" & X"000", -- 0x00B:
-		"000000" & X"000", -- 0x00C:
-		"000000" & X"000", -- 0x00D:
-		"000000" & X"000", -- 0x00E:
-		"000000" & X"000", -- 0x00F:
-		"110000" & X"010", -- 0x010: JMP 0x010
-		"111111" & X"000", -- 0x011: RETI
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000"
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/dctest_xrom.vhdl b/lib/CPUs/JCpu/src/dctest_xrom.vhdl
deleted file mode 100644
index 24fe36c..0000000
--- a/lib/CPUs/JCpu/src/dctest_xrom.vhdl
+++ /dev/null
@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE dctest OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from dctest.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"01", -- 0x04
-		X"12", -- 0x05
-		X"41", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"48", -- 0x17
-		X"61", -- 0x18
-		X"6C", -- 0x19
-		X"6C", -- 0x1A
-		X"6F", -- 0x1B
-		X"0D", -- 0x1C
-		X"0A", -- 0x1D
-		X"00", -- 0x1E
-		X"4A", -- 0x1F
-		X"65", -- 0x20
-		X"6E", -- 0x21
-		X"73", -- 0x22
-		X"00", -- 0x23
-		X"57", -- 0x24
-		X"65", -- 0x25
-		X"6C", -- 0x26
-		X"63", -- 0x27
-		X"6F", -- 0x28
-		X"6D", -- 0x29
-		X"65", -- 0x2A
-		X"20", -- 0x2B
-		X"74", -- 0x2C
-		X"6F", -- 0x2D
-		X"20", -- 0x2E
-		X"4A", -- 0x2F
-		X"41", -- 0x30
-		X"53", -- 0x31
-		X"4D", -- 0x32
-		X"20", -- 0x33
-		X"43", -- 0x34
-		X"50", -- 0x35
-		X"55", -- 0x36
-		X"00", -- 0x37
-		X"52", -- 0x38
-		X"65", -- 0x39
-		X"61", -- 0x3A
-		X"64", -- 0x3B
-		X"79", -- 0x3C
-		X"00", -- 0x3D
-		X"54", -- 0x3E
-		X"65", -- 0x3F
-		X"73", -- 0x40
-		X"74", -- 0x41
-		X"69", -- 0x42
-		X"6E", -- 0x43
-		X"67", -- 0x44
-		X"00", -- 0x45
-		X"50", -- 0x46
-		X"61", -- 0x47
-		X"73", -- 0x48
-		X"73", -- 0x49
-		X"65", -- 0x4A
-		X"64", -- 0x4B
-		X"00", -- 0x4C
-		X"45", -- 0x4D
-		X"72", -- 0x4E
-		X"72", -- 0x4F
-		X"6F", -- 0x50
-		X"72", -- 0x51
-		X"00", -- 0x52
-		X"0D", -- 0x53
-		X"0A", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end dctest;
-
diff --git a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl
deleted file mode 100644
index 802ba50..0000000
--- a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl
+++ /dev/null
@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from dctest.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"01", -- 0x04
-		X"12", -- 0x05
-		X"41", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"48", -- 0x17
-		X"61", -- 0x18
-		X"6C", -- 0x19
-		X"6C", -- 0x1A
-		X"6F", -- 0x1B
-		X"0D", -- 0x1C
-		X"0A", -- 0x1D
-		X"00", -- 0x1E
-		X"4A", -- 0x1F
-		X"65", -- 0x20
-		X"6E", -- 0x21
-		X"73", -- 0x22
-		X"00", -- 0x23
-		X"57", -- 0x24
-		X"65", -- 0x25
-		X"6C", -- 0x26
-		X"63", -- 0x27
-		X"6F", -- 0x28
-		X"6D", -- 0x29
-		X"65", -- 0x2A
-		X"20", -- 0x2B
-		X"74", -- 0x2C
-		X"6F", -- 0x2D
-		X"20", -- 0x2E
-		X"4A", -- 0x2F
-		X"41", -- 0x30
-		X"53", -- 0x31
-		X"4D", -- 0x32
-		X"20", -- 0x33
-		X"43", -- 0x34
-		X"50", -- 0x35
-		X"55", -- 0x36
-		X"00", -- 0x37
-		X"52", -- 0x38
-		X"65", -- 0x39
-		X"61", -- 0x3A
-		X"64", -- 0x3B
-		X"79", -- 0x3C
-		X"00", -- 0x3D
-		X"54", -- 0x3E
-		X"65", -- 0x3F
-		X"73", -- 0x40
-		X"74", -- 0x41
-		X"69", -- 0x42
-		X"6E", -- 0x43
-		X"67", -- 0x44
-		X"00", -- 0x45
-		X"50", -- 0x46
-		X"61", -- 0x47
-		X"73", -- 0x48
-		X"73", -- 0x49
-		X"65", -- 0x4A
-		X"64", -- 0x4B
-		X"00", -- 0x4C
-		X"45", -- 0x4D
-		X"72", -- 0x4E
-		X"72", -- 0x4F
-		X"6F", -- 0x50
-		X"72", -- 0x51
-		X"00", -- 0x52
-		X"0D", -- 0x53
-		X"0A", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/itest_irom.vhdl b/lib/CPUs/JCpu/src/itest_irom.vhdl
deleted file mode 100644
index 0ed28f2..0000000
--- a/lib/CPUs/JCpu/src/itest_irom.vhdl
+++ /dev/null
@@ -1,1086 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port
-	(
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE itest OF irom IS 
-
-	type imem_rom_t is array (0 to 1023) of inst_t;
-
-	-- Assembled from itest.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"010", -- 0x000: JMP 0x010
-		"110000" & X"288", -- 0x001: JMP 0x288
-		"000000" & X"000", -- 0x002:
-		"000000" & X"000", -- 0x003:
-		"000000" & X"000", -- 0x004:
-		"000000" & X"000", -- 0x005:
-		"000000" & X"000", -- 0x006:
-		"000000" & X"000", -- 0x007:
-		"000000" & X"000", -- 0x008:
-		"000000" & X"000", -- 0x009:
-		"000000" & X"000", -- 0x00A:
-		"000000" & X"000", -- 0x00B:
-		"000000" & X"000", -- 0x00C:
-		"000000" & X"000", -- 0x00D:
-		"000000" & X"000", -- 0x00E:
-		"000000" & X"000", -- 0x00F:
-		"111011" & X"03B", -- 0x010: CALL 0x03B
-		"101001" & X"000", -- 0x011: CIN R00, (0x00)
-		"100100" & X"000", -- 0x012: XOUT (0x00), R00
-		"111011" & X"04C", -- 0x013: CALL 0x04C
-		"000011" & X"010", -- 0x014: MOV R00, 0x01
-		"100100" & X"010", -- 0x015: XOUT (0x01), R00
-		"111011" & X"08D", -- 0x016: CALL 0x08D
-		"000011" & X"020", -- 0x017: MOV R00, 0x02
-		"100100" & X"010", -- 0x018: XOUT (0x01), R00
-		"111011" & X"0C9", -- 0x019: CALL 0x0C9
-		"000011" & X"030", -- 0x01A: MOV R00, 0x03
-		"100100" & X"010", -- 0x01B: XOUT (0x01), R00
-		"111011" & X"0DB", -- 0x01C: CALL 0x0DB
-		"000011" & X"040", -- 0x01D: MOV R00, 0x04
-		"100100" & X"010", -- 0x01E: XOUT (0x01), R00
-		"111011" & X"0ED", -- 0x01F: CALL 0x0ED
-		"000011" & X"050", -- 0x020: MOV R00, 0x05
-		"100100" & X"010", -- 0x021: XOUT (0x01), R00
-		"111011" & X"0FF", -- 0x022: CALL 0x0FF
-		"000011" & X"060", -- 0x023: MOV R00, 0x06
-		"100100" & X"010", -- 0x024: XOUT (0x01), R00
-		"111011" & X"115", -- 0x025: CALL 0x115
-		"000011" & X"070", -- 0x026: MOV R00, 0x07
-		"100100" & X"010", -- 0x027: XOUT (0x01), R00
-		"111011" & X"12B", -- 0x028: CALL 0x12B
-		"000011" & X"080", -- 0x029: MOV R00, 0x08
-		"100100" & X"010", -- 0x02A: XOUT (0x01), R00
-		"111011" & X"137", -- 0x02B: CALL 0x137
-		"000011" & X"090", -- 0x02C: MOV R00, 0x09
-		"100100" & X"010", -- 0x02D: XOUT (0x01), R00
-		"111011" & X"15A", -- 0x02E: CALL 0x15A
-		"000011" & X"0A0", -- 0x02F: MOV R00, 0x0A
-		"100100" & X"010", -- 0x030: XOUT (0x01), R00
-		"111011" & X"22A", -- 0x031: CALL 0x22A
-		"000011" & X"0B0", -- 0x032: MOV R00, 0x0B
-		"100100" & X"010", -- 0x033: XOUT (0x01), R00
-		"111011" & X"24D", -- 0x034: CALL 0x24D
-		"000011" & X"0C0", -- 0x035: MOV R00, 0x0C
-		"100100" & X"010", -- 0x036: XOUT (0x01), R00
-		"111011" & X"278", -- 0x037: CALL 0x278
-		"000011" & X"FF0", -- 0x038: MOV R00, 0xFF
-		"100100" & X"010", -- 0x039: XOUT (0x01), R00
-		"110000" & X"2FF", -- 0x03A: JMP 0x2FF
-		"000011" & X"000", -- 0x03B: MOV R00, 0x00
-		"000011" & X"001", -- 0x03C: MOV R01, 0x00
-		"000011" & X"002", -- 0x03D: MOV R02, 0x00
-		"000011" & X"003", -- 0x03E: MOV R03, 0x00
-		"000011" & X"004", -- 0x03F: MOV R04, 0x00
-		"000011" & X"005", -- 0x040: MOV R05, 0x00
-		"000011" & X"006", -- 0x041: MOV R06, 0x00
-		"000011" & X"007", -- 0x042: MOV R07, 0x00
-		"000011" & X"008", -- 0x043: MOV R08, 0x00
-		"000011" & X"009", -- 0x044: MOV R09, 0x00
-		"000011" & X"00A", -- 0x045: MOV R10, 0x00
-		"000011" & X"00B", -- 0x046: MOV R11, 0x00
-		"000011" & X"00C", -- 0x047: MOV R12, 0x00
-		"000011" & X"00D", -- 0x048: MOV R13, 0x00
-		"000011" & X"00E", -- 0x049: MOV R14, 0x00
-		"000011" & X"00F", -- 0x04A: MOV R15, 0x00
-		"111110" & X"000", -- 0x04B: RET
-		"000011" & X"100", -- 0x04C: MOV R00, 0x10
-		"001111" & X"100", -- 0x04D: CMP R00, 0x10
-		"111010" & X"3FF", -- 0x04E: JNE 0x3FF
-		"010001" & X"010", -- 0x04F: ADD R00, 0x01
-		"000010" & X"001", -- 0x050: MOV R01, R00
-		"001111" & X"111", -- 0x051: CMP R01, 0x11
-		"111010" & X"3FF", -- 0x052: JNE 0x3FF
-		"010001" & X"011", -- 0x053: ADD R01, 0x01
-		"000010" & X"012", -- 0x054: MOV R02, R01
-		"001111" & X"122", -- 0x055: CMP R02, 0x12
-		"111010" & X"3FF", -- 0x056: JNE 0x3FF
-		"010001" & X"012", -- 0x057: ADD R02, 0x01
-		"000010" & X"023", -- 0x058: MOV R03, R02
-		"001111" & X"133", -- 0x059: CMP R03, 0x13
-		"111010" & X"3FF", -- 0x05A: JNE 0x3FF
-		"010001" & X"013", -- 0x05B: ADD R03, 0x01
-		"000010" & X"034", -- 0x05C: MOV R04, R03
-		"001111" & X"144", -- 0x05D: CMP R04, 0x14
-		"111010" & X"3FF", -- 0x05E: JNE 0x3FF
-		"010001" & X"014", -- 0x05F: ADD R04, 0x01
-		"000010" & X"045", -- 0x060: MOV R05, R04
-		"001111" & X"155", -- 0x061: CMP R05, 0x15
-		"111010" & X"3FF", -- 0x062: JNE 0x3FF
-		"010001" & X"015", -- 0x063: ADD R05, 0x01
-		"000010" & X"056", -- 0x064: MOV R06, R05
-		"001111" & X"166", -- 0x065: CMP R06, 0x16
-		"111010" & X"3FF", -- 0x066: JNE 0x3FF
-		"010001" & X"016", -- 0x067: ADD R06, 0x01
-		"000010" & X"067", -- 0x068: MOV R07, R06
-		"001111" & X"177", -- 0x069: CMP R07, 0x17
-		"111010" & X"3FF", -- 0x06A: JNE 0x3FF
-		"010001" & X"017", -- 0x06B: ADD R07, 0x01
-		"000010" & X"078", -- 0x06C: MOV R08, R07
-		"001111" & X"188", -- 0x06D: CMP R08, 0x18
-		"111010" & X"3FF", -- 0x06E: JNE 0x3FF
-		"010001" & X"018", -- 0x06F: ADD R08, 0x01
-		"000010" & X"089", -- 0x070: MOV R09, R08
-		"001111" & X"199", -- 0x071: CMP R09, 0x19
-		"111010" & X"3FF", -- 0x072: JNE 0x3FF
-		"010001" & X"019", -- 0x073: ADD R09, 0x01
-		"000010" & X"09A", -- 0x074: MOV R10, R09
-		"001111" & X"1AA", -- 0x075: CMP R10, 0x1A
-		"111010" & X"3FF", -- 0x076: JNE 0x3FF
-		"010001" & X"01A", -- 0x077: ADD R10, 0x01
-		"000010" & X"0AB", -- 0x078: MOV R11, R10
-		"001111" & X"1BB", -- 0x079: CMP R11, 0x1B
-		"111010" & X"3FF", -- 0x07A: JNE 0x3FF
-		"010001" & X"01B", -- 0x07B: ADD R11, 0x01
-		"000010" & X"0BC", -- 0x07C: MOV R12, R11
-		"001111" & X"1CC", -- 0x07D: CMP R12, 0x1C
-		"111010" & X"3FF", -- 0x07E: JNE 0x3FF
-		"010001" & X"01C", -- 0x07F: ADD R12, 0x01
-		"000010" & X"0CD", -- 0x080: MOV R13, R12
-		"001111" & X"1DD", -- 0x081: CMP R13, 0x1D
-		"111010" & X"3FF", -- 0x082: JNE 0x3FF
-		"010001" & X"01D", -- 0x083: ADD R13, 0x01
-		"000010" & X"0DE", -- 0x084: MOV R14, R13
-		"001111" & X"1EE", -- 0x085: CMP R14, 0x1E
-		"111010" & X"3FF", -- 0x086: JNE 0x3FF
-		"010001" & X"01E", -- 0x087: ADD R14, 0x01
-		"000010" & X"0EF", -- 0x088: MOV R15, R14
-		"001111" & X"1FF", -- 0x089: CMP R15, 0x1F
-		"111010" & X"3FF", -- 0x08A: JNE 0x3FF
-		"010001" & X"01F", -- 0x08B: ADD R15, 0x01
-		"111110" & X"000", -- 0x08C: RET
-		"000011" & X"000", -- 0x08D: MOV R00, 0x00
-		"001111" & X"000", -- 0x08E: TST R00
-		"110010" & X"3FF", -- 0x08F: JNZ 0x3FF
-		"110011" & X"3FF", -- 0x090: JC 0x3FF
-		"001111" & X"000", -- 0x091: CMP R00, 0x00
-		"111010" & X"3FF", -- 0x092: JNE 0x3FF
-		"110101" & X"3FF", -- 0x093: JLT 0x3FF
-		"110110" & X"3FF", -- 0x094: JGT 0x3FF
-		"110111" & X"097", -- 0x095: JLE 0x097
-		"110000" & X"3FF", -- 0x096: JMP 0x3FF
-		"111001" & X"099", -- 0x097: JEQ 0x099
-		"110000" & X"3FF", -- 0x098: JMP 0x3FF
-		"111000" & X"09B", -- 0x099: JGE 0x09B
-		"110000" & X"3FF", -- 0x09A: JMP 0x3FF
-		"001111" & X"550", -- 0x09B: CMP R00, 0x55
-		"111001" & X"3FF", -- 0x09C: JEQ 0x3FF
-		"110101" & X"09F", -- 0x09D: JLT 0x09F
-		"110000" & X"3FF", -- 0x09E: JMP 0x3FF
-		"110111" & X"0A1", -- 0x09F: JLE 0x0A1
-		"110000" & X"3FF", -- 0x0A0: JMP 0x3FF
-		"111000" & X"3FF", -- 0x0A1: JGE 0x3FF
-		"110110" & X"3FF", -- 0x0A2: JGT 0x3FF
-		"000011" & X"550", -- 0x0A3: MOV R00, 0x55
-		"001111" & X"000", -- 0x0A4: TST R00
-		"110001" & X"3FF", -- 0x0A5: JZ 0x3FF
-		"110011" & X"3FF", -- 0x0A6: JC 0x3FF
-		"001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA
-		"111001" & X"3FF", -- 0x0A8: JEQ 0x3FF
-		"111010" & X"0AB", -- 0x0A9: JNE 0x0AB
-		"110000" & X"3FF", -- 0x0AA: JMP 0x3FF
-		"110101" & X"0AD", -- 0x0AB: JLT 0x0AD
-		"110000" & X"3FF", -- 0x0AC: JMP 0x3FF
-		"110111" & X"0AF", -- 0x0AD: JLE 0x0AF
-		"110000" & X"3FF", -- 0x0AE: JMP 0x3FF
-		"110110" & X"3FF", -- 0x0AF: JGT 0x3FF
-		"001111" & X"550", -- 0x0B0: CMP R00, 0x55
-		"111001" & X"0B3", -- 0x0B1: JEQ 0x0B3
-		"110000" & X"3FF", -- 0x0B2: JMP 0x3FF
-		"111010" & X"3FF", -- 0x0B3: JNE 0x3FF
-		"110101" & X"3FF", -- 0x0B4: JLT 0x3FF
-		"110111" & X"0B7", -- 0x0B5: JLE 0x0B7
-		"110000" & X"3FF", -- 0x0B6: JMP 0x3FF
-		"110110" & X"3FF", -- 0x0B7: JGT 0x3FF
-		"111000" & X"0BA", -- 0x0B8: JGE 0x0BA
-		"110000" & X"3FF", -- 0x0B9: JMP 0x3FF
-		"000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA
-		"001111" & X"000", -- 0x0BB: TST R00
-		"110001" & X"3FF", -- 0x0BC: JZ 0x3FF
-		"110011" & X"3FF", -- 0x0BD: JC 0x3FF
-		"001111" & X"550", -- 0x0BE: CMP R00, 0x55
-		"111001" & X"3FF", -- 0x0BF: JEQ 0x3FF
-		"111010" & X"0C2", -- 0x0C0: JNE 0x0C2
-		"110000" & X"3FF", -- 0x0C1: JMP 0x3FF
-		"110110" & X"0C4", -- 0x0C2: JGT 0x0C4
-		"110000" & X"3FF", -- 0x0C3: JMP 0x3FF
-		"111000" & X"0C6", -- 0x0C4: JGE 0x0C6
-		"110000" & X"3FF", -- 0x0C5: JMP 0x3FF
-		"110101" & X"3FF", -- 0x0C6: JLT 0x3FF
-		"110111" & X"3FF", -- 0x0C7: JLE 0x3FF
-		"111110" & X"000", -- 0x0C8: RET
-		"000011" & X"000", -- 0x0C9: MOV R00, 0x00
-		"000011" & X"001", -- 0x0CA: MOV R01, 0x00
-		"000010" & X"002", -- 0x0CB: MOV R02, R00
-		"000010" & X"013", -- 0x0CC: MOV R03, R01
-		"010001" & X"010", -- 0x0CD: ADD R00, 0x01
-		"010011" & X"001", -- 0x0CE: ADDC R01, 0x00
-		"010001" & X"012", -- 0x0CF: ADD R02, 0x01
-		"001111" & X"002", -- 0x0D0: CMP R02, 0x00
-		"111010" & X"0D4", -- 0x0D1: JNE 0x0D4
-		"010001" & X"013", -- 0x0D2: ADD R03, 0x01
-		"001111" & X"023", -- 0x0D3: CMP R03, 0x02
-		"111010" & X"0CD", -- 0x0D4: JNE 0x0CD
-		"001110" & X"020", -- 0x0D5: CMP R00, R02
-		"111010" & X"3FF", -- 0x0D6: JNE 0x3FF
-		"001110" & X"031", -- 0x0D7: CMP R01, R03
-		"111010" & X"3FF", -- 0x0D8: JNE 0x3FF
-		"000011" & X"000", -- 0x0D9: MOV R00, 0x00
-		"111110" & X"000", -- 0x0DA: RET
-		"000011" & X"000", -- 0x0DB: MOV R00, 0x00
-		"000011" & X"031", -- 0x0DC: MOV R01, 0x03
-		"000010" & X"002", -- 0x0DD: MOV R02, R00
-		"000010" & X"013", -- 0x0DE: MOV R03, R01
-		"010101" & X"010", -- 0x0DF: SUB R00, 0x01
-		"010111" & X"001", -- 0x0E0: SUBC R01, 0x00
-		"010101" & X"012", -- 0x0E1: SUB R02, 0x01
-		"001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF
-		"111010" & X"0E6", -- 0x0E3: JNE 0x0E6
-		"010101" & X"013", -- 0x0E4: SUB R03, 0x01
-		"001111" & X"003", -- 0x0E5: CMP R03, 0x00
-		"111010" & X"0DF", -- 0x0E6: JNE 0x0DF
-		"001110" & X"020", -- 0x0E7: CMP R00, R02
-		"111010" & X"3FF", -- 0x0E8: JNE 0x3FF
-		"001110" & X"031", -- 0x0E9: CMP R01, R03
-		"111010" & X"3FF", -- 0x0EA: JNE 0x3FF
-		"000011" & X"000", -- 0x0EB: MOV R00, 0x00
-		"111110" & X"000", -- 0x0EC: RET
-		"000011" & X"030", -- 0x0ED: MOV R00, 0x03
-		"000011" & X"051", -- 0x0EE: MOV R01, 0x05
-		"101110" & X"050", -- 0x0EF: SUB 0x05, R00
-		"010101" & X"031", -- 0x0F0: SUB R01, 0x03
-		"001110" & X"010", -- 0x0F1: CMP R00, R01
-		"111010" & X"3FF", -- 0x0F2: JNE 0x3FF
-		"000011" & X"030", -- 0x0F3: MOV R00, 0x03
-		"000011" & X"051", -- 0x0F4: MOV R01, 0x05
-		"010100" & X"010", -- 0x0F5: SUB R00, R01
-		"101111" & X"000", -- 0x0F6: SUBC 0x00, R00
-		"001111" & X"010", -- 0x0F7: CMP R00, 0x01
-		"111010" & X"3FF", -- 0x0F8: JNE 0x3FF
-		"010001" & X"000", -- 0x0F9: ADD R00, 0x00
-		"010110" & X"001", -- 0x0FA: SUBC R01, R00
-		"001111" & X"041", -- 0x0FB: CMP R01, 0x04
-		"111010" & X"3FF", -- 0x0FC: JNE 0x3FF
-		"000011" & X"000", -- 0x0FD: MOV R00, 0x00
-		"111110" & X"000", -- 0x0FE: RET
-		"000011" & X"010", -- 0x0FF: MOV R00, 0x01
-		"001101" & X"5A0", -- 0x100: MOVC (0x5A), R00
-		"010101" & X"010", -- 0x101: DEC R00
-		"001101" & X"000", -- 0x102: MOVC (0x00), R00
-		"001010" & X"5A1", -- 0x103: MOVC R01, (0x5A)
-		"001100" & X"A51", -- 0x104: MOVC (R01), 0xA5
-		"001001" & X"010", -- 0x105: MOVC R00, (R01)
-		"001001" & X"011", -- 0x106: MOVC R01, (R01)
-		"010001" & X"5A1", -- 0x107: ADD R01, 0x5A
-		"001001" & X"010", -- 0x108: MOVC R00, (R01)
-		"001011" & X"000", -- 0x109: MOVC (R00), R00
-		"001001" & X"002", -- 0x10A: MOVC R02, (R00)
-		"001110" & X"002", -- 0x10B: CMP R02, R00
-		"111010" & X"3FF", -- 0x10C: JNE 0x3FF
-		"001011" & X"021", -- 0x10D: MOVC (R01), R02
-		"001001" & X"022", -- 0x10E: MOVC R02, (R02)
-		"001110" & X"012", -- 0x10F: CMP R02, R01
-		"111010" & X"3FF", -- 0x110: JNE 0x3FF
-		"010101" & X"011", -- 0x111: DEC R01
-		"010001" & X"010", -- 0x112: INC R00
-		"110010" & X"109", -- 0x113: JNZ 0x109
-		"111110" & X"000", -- 0x114: RET
-		"000011" & X"010", -- 0x115: MOV R00, 0x01
-		"001000" & X"600", -- 0x116: MOVX (0x60), R00
-		"010101" & X"010", -- 0x117: DEC R00
-		"001000" & X"060", -- 0x118: MOVX (0x06), R00
-		"000101" & X"601", -- 0x119: MOVX R01, (0x60)
-		"000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5
-		"000100" & X"010", -- 0x11B: MOVX R00, (R01)
-		"000100" & X"011", -- 0x11C: MOVX R01, (R01)
-		"010001" & X"5A1", -- 0x11D: ADD R01, 0x5A
-		"000100" & X"010", -- 0x11E: MOVX R00, (R01)
-		"000110" & X"000", -- 0x11F: MOVX (R00), R00
-		"000100" & X"002", -- 0x120: MOVX R02, (R00)
-		"001110" & X"002", -- 0x121: CMP R02, R00
-		"111010" & X"3FF", -- 0x122: JNE 0x3FF
-		"000110" & X"021", -- 0x123: MOVX (R01), R02
-		"000100" & X"022", -- 0x124: MOVX R02, (R02)
-		"001110" & X"012", -- 0x125: CMP R02, R01
-		"111010" & X"3FF", -- 0x126: JNE 0x3FF
-		"010101" & X"011", -- 0x127: DEC R01
-		"010001" & X"010", -- 0x128: INC R00
-		"110010" & X"11F", -- 0x129: JNZ 0x11F
-		"111110" & X"000", -- 0x12A: RET
-		"000011" & X"AA0", -- 0x12B: MOV R00, 0xAA
-		"000011" & X"001", -- 0x12C: MOV R01, 0x00
-		"111100" & X"000", -- 0x12D: PUSH R00
-		"010001" & X"010", -- 0x12E: INC R00
-		"010101" & X"011", -- 0x12F: DEC R01
-		"110010" & X"12D", -- 0x130: JNZ 0x12D
-		"111101" & X"000", -- 0x131: POP R00
-		"010101" & X"011", -- 0x132: DEC R01
-		"110010" & X"131", -- 0x133: JNZ 0x131
-		"001111" & X"AA0", -- 0x134: CMP R00, 0xAA
-		"111010" & X"3FF", -- 0x135: JNE 0x3FF
-		"111110" & X"000", -- 0x136: RET
-		"000011" & X"550", -- 0x137: MOV R00, 0x55
-		"111100" & X"000", -- 0x138: PUSH R00
-		"000011" & X"000", -- 0x139: MOV R00, 0x00
-		"000011" & X"FF1", -- 0x13A: MOV R01, 0xFF
-		"111011" & X"151", -- 0x13B: CALL 0x151
-		"111101" & X"000", -- 0x13C: POP R00
-		"001111" & X"550", -- 0x13D: CMP R00, 0x55
-		"111010" & X"3FF", -- 0x13E: JNE 0x3FF
-		"000011" & X"010", -- 0x13F: MOV R00, 0x01
-		"000011" & X"481", -- 0x140: MOV R01, 0x48
-		"100110" & X"050", -- 0x141: COUT (0x05), R00
-		"111100" & X"001", -- 0x142: PUSH R01
-		"000011" & X"000", -- 0x143: MOV R00, 0x00
-		"000011" & X"3B1", -- 0x144: MOV R01, 0x3B
-		"100110" & X"050", -- 0x145: COUT (0x05), R00
-		"111100" & X"001", -- 0x146: PUSH R01
-		"111110" & X"000", -- 0x147: RET
-		"000011" & X"010", -- 0x148: MOV R00, 0x01
-		"000011" & X"501", -- 0x149: MOV R01, 0x50
-		"100110" & X"050", -- 0x14A: COUT (0x05), R00
-		"111100" & X"001", -- 0x14B: PUSH R01
-		"000011" & X"000", -- 0x14C: MOV R00, 0x00
-		"000011" & X"3B1", -- 0x14D: MOV R01, 0x3B
-		"100110" & X"050", -- 0x14E: COUT (0x05), R00
-		"111100" & X"001", -- 0x14F: PUSH R01
-		"111110" & X"000", -- 0x150: RET
-		"001110" & X"010", -- 0x151: CMP R00, R01
-		"111001" & X"155", -- 0x152: JEQ 0x155
-		"010001" & X"010", -- 0x153: INC R00
-		"110000" & X"158", -- 0x154: JMP 0x158
-		"010101" & X"010", -- 0x155: DEC R00
-		"010101" & X"011", -- 0x156: DEC R01
-		"111110" & X"000", -- 0x157: RET
-		"111011" & X"151", -- 0x158: CALL 0x151
-		"110000" & X"155", -- 0x159: JMP 0x155
-		"000011" & X"A50", -- 0x15A: MOV R00, 0xA5
-		"000011" & X"5A1", -- 0x15B: MOV R01, 0x5A
-		"101010" & X"000", -- 0x15C: SWAP R00
-		"001111" & X"5A0", -- 0x15D: CMP R00, 0x5A
-		"111010" & X"3FF", -- 0x15E: JNE 0x3FF
-		"101010" & X"000", -- 0x15F: SWAP R00
-		"001111" & X"A50", -- 0x160: CMP R00, 0xA5
-		"111010" & X"3FF", -- 0x161: JNE 0x3FF
-		"000011" & X"D20", -- 0x162: MOV R00, 0xD2
-		"101010" & X"000", -- 0x163: SWAP R00
-		"001111" & X"2D0", -- 0x164: CMP R00, 0x2D
-		"111010" & X"3FF", -- 0x165: JNE 0x3FF
-		"101010" & X"001", -- 0x166: SWAP R01
-		"001111" & X"2D0", -- 0x167: CMP R00, 0x2D
-		"111010" & X"3FF", -- 0x168: JNE 0x3FF
-		"001111" & X"A51", -- 0x169: CMP R01, 0xA5
-		"111010" & X"3FF", -- 0x16A: JNE 0x3FF
-		"000011" & X"2D0", -- 0x16B: MOV R00, 0x2D
-		"011110" & X"000", -- 0x16C: SHL R00
-		"001111" & X"5A0", -- 0x16D: CMP R00, 0x5A
-		"111010" & X"3FF", -- 0x16E: JNE 0x3FF
-		"011110" & X"000", -- 0x16F: SHL R00
-		"001111" & X"B40", -- 0x170: CMP R00, 0xB4
-		"111010" & X"3FF", -- 0x171: JNE 0x3FF
-		"011110" & X"000", -- 0x172: SHL R00
-		"001111" & X"680", -- 0x173: CMP R00, 0x68
-		"111010" & X"3FF", -- 0x174: JNE 0x3FF
-		"011110" & X"000", -- 0x175: SHL R00
-		"001111" & X"D00", -- 0x176: CMP R00, 0xD0
-		"111010" & X"3FF", -- 0x177: JNE 0x3FF
-		"011110" & X"000", -- 0x178: SHL R00
-		"001111" & X"A00", -- 0x179: CMP R00, 0xA0
-		"111010" & X"3FF", -- 0x17A: JNE 0x3FF
-		"011110" & X"000", -- 0x17B: SHL R00
-		"001111" & X"400", -- 0x17C: CMP R00, 0x40
-		"111010" & X"3FF", -- 0x17D: JNE 0x3FF
-		"011110" & X"000", -- 0x17E: SHL R00
-		"001111" & X"800", -- 0x17F: CMP R00, 0x80
-		"111010" & X"3FF", -- 0x180: JNE 0x3FF
-		"011110" & X"000", -- 0x181: SHL R00
-		"001111" & X"000", -- 0x182: CMP R00, 0x00
-		"111010" & X"3FF", -- 0x183: JNE 0x3FF
-		"000011" & X"841", -- 0x184: MOV R01, 0x84
-		"011111" & X"001", -- 0x185: SHR R01
-		"001111" & X"421", -- 0x186: CMP R01, 0x42
-		"111010" & X"3FF", -- 0x187: JNE 0x3FF
-		"011111" & X"001", -- 0x188: SHR R01
-		"001111" & X"211", -- 0x189: CMP R01, 0x21
-		"111010" & X"3FF", -- 0x18A: JNE 0x3FF
-		"011111" & X"001", -- 0x18B: SHR R01
-		"001111" & X"101", -- 0x18C: CMP R01, 0x10
-		"111010" & X"3FF", -- 0x18D: JNE 0x3FF
-		"011111" & X"001", -- 0x18E: SHR R01
-		"001111" & X"081", -- 0x18F: CMP R01, 0x08
-		"111010" & X"3FF", -- 0x190: JNE 0x3FF
-		"011111" & X"001", -- 0x191: SHR R01
-		"001111" & X"041", -- 0x192: CMP R01, 0x04
-		"111010" & X"3FF", -- 0x193: JNE 0x3FF
-		"011111" & X"001", -- 0x194: SHR R01
-		"001111" & X"021", -- 0x195: CMP R01, 0x02
-		"111010" & X"3FF", -- 0x196: JNE 0x3FF
-		"011111" & X"001", -- 0x197: SHR R01
-		"001111" & X"011", -- 0x198: CMP R01, 0x01
-		"111010" & X"3FF", -- 0x199: JNE 0x3FF
-		"011111" & X"001", -- 0x19A: SHR R01
-		"001111" & X"001", -- 0x19B: CMP R01, 0x00
-		"111010" & X"3FF", -- 0x19C: JNE 0x3FF
-		"000011" & X"C50", -- 0x19D: MOV R00, 0xC5
-		"100000" & X"000", -- 0x19E: ROL R00
-		"001111" & X"8B0", -- 0x19F: CMP R00, 0x8B
-		"111010" & X"3FF", -- 0x1A0: JNE 0x3FF
-		"100000" & X"000", -- 0x1A1: ROL R00
-		"001111" & X"170", -- 0x1A2: CMP R00, 0x17
-		"111010" & X"3FF", -- 0x1A3: JNE 0x3FF
-		"100000" & X"000", -- 0x1A4: ROL R00
-		"001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E
-		"111010" & X"3FF", -- 0x1A6: JNE 0x3FF
-		"100000" & X"000", -- 0x1A7: ROL R00
-		"001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C
-		"111010" & X"3FF", -- 0x1A9: JNE 0x3FF
-		"100000" & X"000", -- 0x1AA: ROL R00
-		"001111" & X"B80", -- 0x1AB: CMP R00, 0xB8
-		"111010" & X"3FF", -- 0x1AC: JNE 0x3FF
-		"100000" & X"000", -- 0x1AD: ROL R00
-		"001111" & X"710", -- 0x1AE: CMP R00, 0x71
-		"111010" & X"3FF", -- 0x1AF: JNE 0x3FF
-		"100000" & X"000", -- 0x1B0: ROL R00
-		"001111" & X"E20", -- 0x1B1: CMP R00, 0xE2
-		"111010" & X"3FF", -- 0x1B2: JNE 0x3FF
-		"100000" & X"000", -- 0x1B3: ROL R00
-		"001111" & X"C50", -- 0x1B4: CMP R00, 0xC5
-		"111010" & X"3FF", -- 0x1B5: JNE 0x3FF
-		"000011" & X"631", -- 0x1B6: MOV R01, 0x63
-		"100001" & X"001", -- 0x1B7: ROR R01
-		"001111" & X"B11", -- 0x1B8: CMP R01, 0xB1
-		"111010" & X"3FF", -- 0x1B9: JNE 0x3FF
-		"100001" & X"001", -- 0x1BA: ROR R01
-		"001111" & X"D81", -- 0x1BB: CMP R01, 0xD8
-		"111010" & X"3FF", -- 0x1BC: JNE 0x3FF
-		"100001" & X"001", -- 0x1BD: ROR R01
-		"001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C
-		"111010" & X"3FF", -- 0x1BF: JNE 0x3FF
-		"100001" & X"001", -- 0x1C0: ROR R01
-		"001111" & X"361", -- 0x1C1: CMP R01, 0x36
-		"111010" & X"3FF", -- 0x1C2: JNE 0x3FF
-		"100001" & X"001", -- 0x1C3: ROR R01
-		"001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B
-		"111010" & X"3FF", -- 0x1C5: JNE 0x3FF
-		"100001" & X"001", -- 0x1C6: ROR R01
-		"001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D
-		"111010" & X"3FF", -- 0x1C8: JNE 0x3FF
-		"100001" & X"001", -- 0x1C9: ROR R01
-		"001111" & X"C61", -- 0x1CA: CMP R01, 0xC6
-		"111010" & X"3FF", -- 0x1CB: JNE 0x3FF
-		"100001" & X"001", -- 0x1CC: ROR R01
-		"001111" & X"631", -- 0x1CD: CMP R01, 0x63
-		"111010" & X"3FF", -- 0x1CE: JNE 0x3FF
-		"011100" & X"000", -- 0x1CF: XOR R00, R00
-		"000011" & X"C50", -- 0x1D0: MOV R00, 0xC5
-		"100010" & X"000", -- 0x1D1: ROLC R00
-		"111100" & X"000", -- 0x1D2: PUSH R00
-		"100010" & X"000", -- 0x1D3: ROLC R00
-		"111100" & X"000", -- 0x1D4: PUSH R00
-		"100010" & X"000", -- 0x1D5: ROLC R00
-		"111100" & X"000", -- 0x1D6: PUSH R00
-		"100010" & X"000", -- 0x1D7: ROLC R00
-		"111100" & X"000", -- 0x1D8: PUSH R00
-		"100010" & X"000", -- 0x1D9: ROLC R00
-		"111100" & X"000", -- 0x1DA: PUSH R00
-		"100010" & X"000", -- 0x1DB: ROLC R00
-		"111100" & X"000", -- 0x1DC: PUSH R00
-		"100010" & X"000", -- 0x1DD: ROLC R00
-		"111100" & X"000", -- 0x1DE: PUSH R00
-		"100010" & X"000", -- 0x1DF: ROLC R00
-		"111100" & X"000", -- 0x1E0: PUSH R00
-		"100010" & X"000", -- 0x1E1: ROLC R00
-		"001111" & X"C50", -- 0x1E2: CMP R00, 0xC5
-		"111010" & X"3FF", -- 0x1E3: JNE 0x3FF
-		"111101" & X"000", -- 0x1E4: POP R00
-		"001111" & X"620", -- 0x1E5: CMP R00, 0x62
-		"111010" & X"3FF", -- 0x1E6: JNE 0x3FF
-		"111101" & X"000", -- 0x1E7: POP R00
-		"001111" & X"B10", -- 0x1E8: CMP R00, 0xB1
-		"111010" & X"3FF", -- 0x1E9: JNE 0x3FF
-		"111101" & X"000", -- 0x1EA: POP R00
-		"001111" & X"580", -- 0x1EB: CMP R00, 0x58
-		"111010" & X"3FF", -- 0x1EC: JNE 0x3FF
-		"111101" & X"000", -- 0x1ED: POP R00
-		"001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC
-		"111010" & X"3FF", -- 0x1EF: JNE 0x3FF
-		"111101" & X"000", -- 0x1F0: POP R00
-		"001111" & X"560", -- 0x1F1: CMP R00, 0x56
-		"111010" & X"3FF", -- 0x1F2: JNE 0x3FF
-		"111101" & X"000", -- 0x1F3: POP R00
-		"001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B
-		"111010" & X"3FF", -- 0x1F5: JNE 0x3FF
-		"111101" & X"000", -- 0x1F6: POP R00
-		"001111" & X"150", -- 0x1F7: CMP R00, 0x15
-		"111010" & X"3FF", -- 0x1F8: JNE 0x3FF
-		"111101" & X"000", -- 0x1F9: POP R00
-		"001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A
-		"111010" & X"3FF", -- 0x1FB: JNE 0x3FF
-		"011100" & X"011", -- 0x1FC: XOR R01, R01
-		"000011" & X"631", -- 0x1FD: MOV R01, 0x63
-		"100011" & X"001", -- 0x1FE: RORC R01
-		"111100" & X"001", -- 0x1FF: PUSH R01
-		"100011" & X"001", -- 0x200: RORC R01
-		"111100" & X"001", -- 0x201: PUSH R01
-		"100011" & X"001", -- 0x202: RORC R01
-		"111100" & X"001", -- 0x203: PUSH R01
-		"100011" & X"001", -- 0x204: RORC R01
-		"111100" & X"001", -- 0x205: PUSH R01
-		"100011" & X"001", -- 0x206: RORC R01
-		"111100" & X"001", -- 0x207: PUSH R01
-		"100011" & X"001", -- 0x208: RORC R01
-		"111100" & X"001", -- 0x209: PUSH R01
-		"100011" & X"001", -- 0x20A: RORC R01
-		"111100" & X"001", -- 0x20B: PUSH R01
-		"100011" & X"001", -- 0x20C: RORC R01
-		"111100" & X"001", -- 0x20D: PUSH R01
-		"100011" & X"001", -- 0x20E: RORC R01
-		"001111" & X"631", -- 0x20F: CMP R01, 0x63
-		"111010" & X"3FF", -- 0x210: JNE 0x3FF
-		"111101" & X"001", -- 0x211: POP R01
-		"001111" & X"C61", -- 0x212: CMP R01, 0xC6
-		"111010" & X"3FF", -- 0x213: JNE 0x3FF
-		"111101" & X"001", -- 0x214: POP R01
-		"001111" & X"8C1", -- 0x215: CMP R01, 0x8C
-		"111010" & X"3FF", -- 0x216: JNE 0x3FF
-		"111101" & X"001", -- 0x217: POP R01
-		"001111" & X"191", -- 0x218: CMP R01, 0x19
-		"111010" & X"3FF", -- 0x219: JNE 0x3FF
-		"111101" & X"001", -- 0x21A: POP R01
-		"001111" & X"331", -- 0x21B: CMP R01, 0x33
-		"111010" & X"3FF", -- 0x21C: JNE 0x3FF
-		"111101" & X"001", -- 0x21D: POP R01
-		"001111" & X"661", -- 0x21E: CMP R01, 0x66
-		"111010" & X"3FF", -- 0x21F: JNE 0x3FF
-		"111101" & X"001", -- 0x220: POP R01
-		"001111" & X"CC1", -- 0x221: CMP R01, 0xCC
-		"111010" & X"3FF", -- 0x222: JNE 0x3FF
-		"111101" & X"001", -- 0x223: POP R01
-		"001111" & X"981", -- 0x224: CMP R01, 0x98
-		"111010" & X"3FF", -- 0x225: JNE 0x3FF
-		"111101" & X"001", -- 0x226: POP R01
-		"001111" & X"311", -- 0x227: CMP R01, 0x31
-		"111010" & X"3FF", -- 0x228: JNE 0x3FF
-		"111110" & X"000", -- 0x229: RET
-		"000011" & X"A50", -- 0x22A: MOV R00, 0xA5
-		"101010" & X"000", -- 0x22B: SWAP R00
-		"111100" & X"000", -- 0x22C: PUSH R00
-		"011001" & X"0F0", -- 0x22D: AND R00, 0x0F
-		"001111" & X"0A0", -- 0x22E: CMP R00, 0x0A
-		"111010" & X"3FF", -- 0x22F: JNE 0x3FF
-		"111101" & X"000", -- 0x230: POP R00
-		"111100" & X"000", -- 0x231: PUSH R00
-		"011001" & X"0F0", -- 0x232: AND R00, 0x0F
-		"001111" & X"0A0", -- 0x233: CMP R00, 0x0A
-		"111101" & X"001", -- 0x234: POP R01
-		"111010" & X"3FF", -- 0x235: JNE 0x3FF
-		"101010" & X"001", -- 0x236: SWAP R01
-		"000011" & X"0F2", -- 0x237: MOV R02, 0x0F
-		"011000" & X"021", -- 0x238: AND R01, R02
-		"001111" & X"051", -- 0x239: CMP R01, 0x05
-		"111010" & X"3FF", -- 0x23A: JNE 0x3FF
-		"000011" & X"050", -- 0x23B: MOV R00, 0x05
-		"000011" & X"A02", -- 0x23C: MOV R02, 0xA0
-		"101010" & X"000", -- 0x23D: SWAP R00
-		"011010" & X"002", -- 0x23E: OR R02, R00
-		"001111" & X"F02", -- 0x23F: CMP R02, 0xF0
-		"111010" & X"3FF", -- 0x240: JNE 0x3FF
-		"101010" & X"000", -- 0x241: SWAP R00
-		"011011" & X"500", -- 0x242: OR R00, 0x50
-		"001111" & X"550", -- 0x243: CMP R00, 0x55
-		"111010" & X"3FF", -- 0x244: JNE 0x3FF
-		"000011" & X"011", -- 0x245: MOV R01, 0x01
-		"000011" & X"010", -- 0x246: MOV R00, 0x01
-		"011101" & X"010", -- 0x247: XOR R00, 0x01
-		"110010" & X"3FF", -- 0x248: JNZ 0x3FF
-		"011100" & X"010", -- 0x249: XOR R00, R01
-		"001111" & X"010", -- 0x24A: CMP R00, 0x01
-		"111010" & X"3FF", -- 0x24B: JNE 0x3FF
-		"111110" & X"000", -- 0x24C: RET
-		"000011" & X"030", -- 0x24D: MOV R00, 0x03
-		"100110" & X"030", -- 0x24E: COUT (0x03), R00
-		"101000" & X"020", -- 0x24F: XIN R00, (0x02)
-		"011011" & X"010", -- 0x250: OR R00, 0x01
-		"100100" & X"020", -- 0x251: XOUT (0x02), R00
-		"000000" & X"000", -- 0x252: NOP
-		"000000" & X"000", -- 0x253: NOP
-		"000000" & X"000", -- 0x254: NOP
-		"000000" & X"000", -- 0x255: NOP
-		"000000" & X"000", -- 0x256: NOP
-		"000000" & X"000", -- 0x257: NOP
-		"101000" & X"020", -- 0x258: XIN R00, (0x02)
-		"011001" & X"FE0", -- 0x259: AND R00, 0xFE
-		"100100" & X"020", -- 0x25A: XOUT (0x02), R00
-		"000000" & X"000", -- 0x25B: NOP
-		"000000" & X"000", -- 0x25C: NOP
-		"000000" & X"000", -- 0x25D: NOP
-		"000000" & X"000", -- 0x25E: NOP
-		"101001" & X"030", -- 0x25F: CIN R00, (0x03)
-		"011011" & X"800", -- 0x260: OR R00, 0x80
-		"100110" & X"030", -- 0x261: COUT (0x03), R00
-		"000000" & X"000", -- 0x262: NOP
-		"101001" & X"030", -- 0x263: CIN R00, (0x03)
-		"011011" & X"800", -- 0x264: OR R00, 0x80
-		"100110" & X"030", -- 0x265: COUT (0x03), R00
-		"000000" & X"000", -- 0x266: NOP
-		"101001" & X"030", -- 0x267: CIN R00, (0x03)
-		"011011" & X"800", -- 0x268: OR R00, 0x80
-		"100110" & X"030", -- 0x269: COUT (0x03), R00
-		"000000" & X"000", -- 0x26A: NOP
-		"101001" & X"030", -- 0x26B: CIN R00, (0x03)
-		"011011" & X"800", -- 0x26C: OR R00, 0x80
-		"100110" & X"030", -- 0x26D: COUT (0x03), R00
-		"000000" & X"000", -- 0x26E: NOP
-		"000000" & X"000", -- 0x26F: NOP
-		"000000" & X"000", -- 0x270: NOP
-		"000000" & X"000", -- 0x271: NOP
-		"000000" & X"000", -- 0x272: NOP
-		"000000" & X"000", -- 0x273: NOP
-		"000000" & X"000", -- 0x274: NOP
-		"000000" & X"000", -- 0x275: NOP
-		"000000" & X"000", -- 0x276: NOP
-		"111110" & X"000", -- 0x277: RET
-		"010101" & X"000", -- 0x278: SUB R00, 0x00
-		"110011" & X"3FF", -- 0x279: JC 0x3FF
-		"101011" & X"000", -- 0x27A: SETC
-		"110100" & X"3FF", -- 0x27B: JNC 0x3FF
-		"000000" & X"000", -- 0x27C: NOP
-		"010101" & X"000", -- 0x27D: SUB R00, 0x00
-		"110011" & X"3FF", -- 0x27E: JC 0x3FF
-		"000011" & X"000", -- 0x27F: MOV R00, 0x00
-		"010101" & X"000", -- 0x280: CLRC
-		"110011" & X"3FF", -- 0x281: JC 0x3FF
-		"101011" & X"000", -- 0x282: SETC
-		"110100" & X"3FF", -- 0x283: JNC 0x3FF
-		"000000" & X"000", -- 0x284: NOP
-		"010101" & X"000", -- 0x285: CLRC
-		"110011" & X"3FF", -- 0x286: JC 0x3FF
-		"111110" & X"000", -- 0x287: RET
-		"010001" & X"01E", -- 0x288: INC R14
-		"111111" & X"000", -- 0x289: RETI
-		"000000" & X"000", -- 0x28A:
-		"000000" & X"000", -- 0x28B:
-		"000000" & X"000", -- 0x28C:
-		"000000" & X"000", -- 0x28D:
-		"000000" & X"000", -- 0x28E:
-		"000000" & X"000", -- 0x28F:
-		"000000" & X"000", -- 0x290:
-		"000000" & X"000", -- 0x291:
-		"000000" & X"000", -- 0x292:
-		"000000" & X"000", -- 0x293:
-		"000000" & X"000", -- 0x294:
-		"000000" & X"000", -- 0x295:
-		"000000" & X"000", -- 0x296:
-		"000000" & X"000", -- 0x297:
-		"000000" & X"000", -- 0x298:
-		"000000" & X"000", -- 0x299:
-		"000000" & X"000", -- 0x29A:
-		"000000" & X"000", -- 0x29B:
-		"000000" & X"000", -- 0x29C:
-		"000000" & X"000", -- 0x29D:
-		"000000" & X"000", -- 0x29E:
-		"000000" & X"000", -- 0x29F:
-		"000000" & X"000", -- 0x2A0:
-		"000000" & X"000", -- 0x2A1:
-		"000000" & X"000", -- 0x2A2:
-		"000000" & X"000", -- 0x2A3:
-		"000000" & X"000", -- 0x2A4:
-		"000000" & X"000", -- 0x2A5:
-		"000000" & X"000", -- 0x2A6:
-		"000000" & X"000", -- 0x2A7:
-		"000000" & X"000", -- 0x2A8:
-		"000000" & X"000", -- 0x2A9:
-		"000000" & X"000", -- 0x2AA:
-		"000000" & X"000", -- 0x2AB:
-		"000000" & X"000", -- 0x2AC:
-		"000000" & X"000", -- 0x2AD:
-		"000000" & X"000", -- 0x2AE:
-		"000000" & X"000", -- 0x2AF:
-		"000000" & X"000", -- 0x2B0:
-		"000000" & X"000", -- 0x2B1:
-		"000000" & X"000", -- 0x2B2:
-		"000000" & X"000", -- 0x2B3:
-		"000000" & X"000", -- 0x2B4:
-		"000000" & X"000", -- 0x2B5:
-		"000000" & X"000", -- 0x2B6:
-		"000000" & X"000", -- 0x2B7:
-		"000000" & X"000", -- 0x2B8:
-		"000000" & X"000", -- 0x2B9:
-		"000000" & X"000", -- 0x2BA:
-		"000000" & X"000", -- 0x2BB:
-		"000000" & X"000", -- 0x2BC:
-		"000000" & X"000", -- 0x2BD:
-		"000000" & X"000", -- 0x2BE:
-		"000000" & X"000", -- 0x2BF:
-		"000000" & X"000", -- 0x2C0:
-		"000000" & X"000", -- 0x2C1:
-		"000000" & X"000", -- 0x2C2:
-		"000000" & X"000", -- 0x2C3:
-		"000000" & X"000", -- 0x2C4:
-		"000000" & X"000", -- 0x2C5:
-		"000000" & X"000", -- 0x2C6:
-		"000000" & X"000", -- 0x2C7:
-		"000000" & X"000", -- 0x2C8:
-		"000000" & X"000", -- 0x2C9:
-		"000000" & X"000", -- 0x2CA:
-		"000000" & X"000", -- 0x2CB:
-		"000000" & X"000", -- 0x2CC:
-		"000000" & X"000", -- 0x2CD:
-		"000000" & X"000", -- 0x2CE:
-		"000000" & X"000", -- 0x2CF:
-		"000000" & X"000", -- 0x2D0:
-		"000000" & X"000", -- 0x2D1:
-		"000000" & X"000", -- 0x2D2:
-		"000000" & X"000", -- 0x2D3:
-		"000000" & X"000", -- 0x2D4:
-		"000000" & X"000", -- 0x2D5:
-		"000000" & X"000", -- 0x2D6:
-		"000000" & X"000", -- 0x2D7:
-		"000000" & X"000", -- 0x2D8:
-		"000000" & X"000", -- 0x2D9:
-		"000000" & X"000", -- 0x2DA:
-		"000000" & X"000", -- 0x2DB:
-		"000000" & X"000", -- 0x2DC:
-		"000000" & X"000", -- 0x2DD:
-		"000000" & X"000", -- 0x2DE:
-		"000000" & X"000", -- 0x2DF:
-		"000000" & X"000", -- 0x2E0:
-		"000000" & X"000", -- 0x2E1:
-		"000000" & X"000", -- 0x2E2:
-		"000000" & X"000", -- 0x2E3:
-		"000000" & X"000", -- 0x2E4:
-		"000000" & X"000", -- 0x2E5:
-		"000000" & X"000", -- 0x2E6:
-		"000000" & X"000", -- 0x2E7:
-		"000000" & X"000", -- 0x2E8:
-		"000000" & X"000", -- 0x2E9:
-		"000000" & X"000", -- 0x2EA:
-		"000000" & X"000", -- 0x2EB:
-		"000000" & X"000", -- 0x2EC:
-		"000000" & X"000", -- 0x2ED:
-		"000000" & X"000", -- 0x2EE:
-		"000000" & X"000", -- 0x2EF:
-		"000000" & X"000", -- 0x2F0:
-		"000000" & X"000", -- 0x2F1:
-		"000000" & X"000", -- 0x2F2:
-		"000000" & X"000", -- 0x2F3:
-		"000000" & X"000", -- 0x2F4:
-		"000000" & X"000", -- 0x2F5:
-		"000000" & X"000", -- 0x2F6:
-		"000000" & X"000", -- 0x2F7:
-		"000000" & X"000", -- 0x2F8:
-		"000000" & X"000", -- 0x2F9:
-		"000000" & X"000", -- 0x2FA:
-		"000000" & X"000", -- 0x2FB:
-		"000000" & X"000", -- 0x2FC:
-		"000000" & X"000", -- 0x2FD:
-		"000000" & X"000", -- 0x2FE:
-		"110000" & X"2FF", -- 0x2FF: JMP 0x2FF
-		"000000" & X"000", -- 0x300:
-		"000000" & X"000", -- 0x301:
-		"000000" & X"000", -- 0x302:
-		"000000" & X"000", -- 0x303:
-		"000000" & X"000", -- 0x304:
-		"000000" & X"000", -- 0x305:
-		"000000" & X"000", -- 0x306:
-		"000000" & X"000", -- 0x307:
-		"000000" & X"000", -- 0x308:
-		"000000" & X"000", -- 0x309:
-		"000000" & X"000", -- 0x30A:
-		"000000" & X"000", -- 0x30B:
-		"000000" & X"000", -- 0x30C:
-		"000000" & X"000", -- 0x30D:
-		"000000" & X"000", -- 0x30E:
-		"000000" & X"000", -- 0x30F:
-		"000000" & X"000", -- 0x310:
-		"000000" & X"000", -- 0x311:
-		"000000" & X"000", -- 0x312:
-		"000000" & X"000", -- 0x313:
-		"000000" & X"000", -- 0x314:
-		"000000" & X"000", -- 0x315:
-		"000000" & X"000", -- 0x316:
-		"000000" & X"000", -- 0x317:
-		"000000" & X"000", -- 0x318:
-		"000000" & X"000", -- 0x319:
-		"000000" & X"000", -- 0x31A:
-		"000000" & X"000", -- 0x31B:
-		"000000" & X"000", -- 0x31C:
-		"000000" & X"000", -- 0x31D:
-		"000000" & X"000", -- 0x31E:
-		"000000" & X"000", -- 0x31F:
-		"000000" & X"000", -- 0x320:
-		"000000" & X"000", -- 0x321:
-		"000000" & X"000", -- 0x322:
-		"000000" & X"000", -- 0x323:
-		"000000" & X"000", -- 0x324:
-		"000000" & X"000", -- 0x325:
-		"000000" & X"000", -- 0x326:
-		"000000" & X"000", -- 0x327:
-		"000000" & X"000", -- 0x328:
-		"000000" & X"000", -- 0x329:
-		"000000" & X"000", -- 0x32A:
-		"000000" & X"000", -- 0x32B:
-		"000000" & X"000", -- 0x32C:
-		"000000" & X"000", -- 0x32D:
-		"000000" & X"000", -- 0x32E:
-		"000000" & X"000", -- 0x32F:
-		"000000" & X"000", -- 0x330:
-		"000000" & X"000", -- 0x331:
-		"000000" & X"000", -- 0x332:
-		"000000" & X"000", -- 0x333:
-		"000000" & X"000", -- 0x334:
-		"000000" & X"000", -- 0x335:
-		"000000" & X"000", -- 0x336:
-		"000000" & X"000", -- 0x337:
-		"000000" & X"000", -- 0x338:
-		"000000" & X"000", -- 0x339:
-		"000000" & X"000", -- 0x33A:
-		"000000" & X"000", -- 0x33B:
-		"000000" & X"000", -- 0x33C:
-		"000000" & X"000", -- 0x33D:
-		"000000" & X"000", -- 0x33E:
-		"000000" & X"000", -- 0x33F:
-		"000000" & X"000", -- 0x340:
-		"000000" & X"000", -- 0x341:
-		"000000" & X"000", -- 0x342:
-		"000000" & X"000", -- 0x343:
-		"000000" & X"000", -- 0x344:
-		"000000" & X"000", -- 0x345:
-		"000000" & X"000", -- 0x346:
-		"000000" & X"000", -- 0x347:
-		"000000" & X"000", -- 0x348:
-		"000000" & X"000", -- 0x349:
-		"000000" & X"000", -- 0x34A:
-		"000000" & X"000", -- 0x34B:
-		"000000" & X"000", -- 0x34C:
-		"000000" & X"000", -- 0x34D:
-		"000000" & X"000", -- 0x34E:
-		"000000" & X"000", -- 0x34F:
-		"000000" & X"000", -- 0x350:
-		"000000" & X"000", -- 0x351:
-		"000000" & X"000", -- 0x352:
-		"000000" & X"000", -- 0x353:
-		"000000" & X"000", -- 0x354:
-		"000000" & X"000", -- 0x355:
-		"000000" & X"000", -- 0x356:
-		"000000" & X"000", -- 0x357:
-		"000000" & X"000", -- 0x358:
-		"000000" & X"000", -- 0x359:
-		"000000" & X"000", -- 0x35A:
-		"000000" & X"000", -- 0x35B:
-		"000000" & X"000", -- 0x35C:
-		"000000" & X"000", -- 0x35D:
-		"000000" & X"000", -- 0x35E:
-		"000000" & X"000", -- 0x35F:
-		"000000" & X"000", -- 0x360:
-		"000000" & X"000", -- 0x361:
-		"000000" & X"000", -- 0x362:
-		"000000" & X"000", -- 0x363:
-		"000000" & X"000", -- 0x364:
-		"000000" & X"000", -- 0x365:
-		"000000" & X"000", -- 0x366:
-		"000000" & X"000", -- 0x367:
-		"000000" & X"000", -- 0x368:
-		"000000" & X"000", -- 0x369:
-		"000000" & X"000", -- 0x36A:
-		"000000" & X"000", -- 0x36B:
-		"000000" & X"000", -- 0x36C:
-		"000000" & X"000", -- 0x36D:
-		"000000" & X"000", -- 0x36E:
-		"000000" & X"000", -- 0x36F:
-		"000000" & X"000", -- 0x370:
-		"000000" & X"000", -- 0x371:
-		"000000" & X"000", -- 0x372:
-		"000000" & X"000", -- 0x373:
-		"000000" & X"000", -- 0x374:
-		"000000" & X"000", -- 0x375:
-		"000000" & X"000", -- 0x376:
-		"000000" & X"000", -- 0x377:
-		"000000" & X"000", -- 0x378:
-		"000000" & X"000", -- 0x379:
-		"000000" & X"000", -- 0x37A:
-		"000000" & X"000", -- 0x37B:
-		"000000" & X"000", -- 0x37C:
-		"000000" & X"000", -- 0x37D:
-		"000000" & X"000", -- 0x37E:
-		"000000" & X"000", -- 0x37F:
-		"000000" & X"000", -- 0x380:
-		"000000" & X"000", -- 0x381:
-		"000000" & X"000", -- 0x382:
-		"000000" & X"000", -- 0x383:
-		"000000" & X"000", -- 0x384:
-		"000000" & X"000", -- 0x385:
-		"000000" & X"000", -- 0x386:
-		"000000" & X"000", -- 0x387:
-		"000000" & X"000", -- 0x388:
-		"000000" & X"000", -- 0x389:
-		"000000" & X"000", -- 0x38A:
-		"000000" & X"000", -- 0x38B:
-		"000000" & X"000", -- 0x38C:
-		"000000" & X"000", -- 0x38D:
-		"000000" & X"000", -- 0x38E:
-		"000000" & X"000", -- 0x38F:
-		"000000" & X"000", -- 0x390:
-		"000000" & X"000", -- 0x391:
-		"000000" & X"000", -- 0x392:
-		"000000" & X"000", -- 0x393:
-		"000000" & X"000", -- 0x394:
-		"000000" & X"000", -- 0x395:
-		"000000" & X"000", -- 0x396:
-		"000000" & X"000", -- 0x397:
-		"000000" & X"000", -- 0x398:
-		"000000" & X"000", -- 0x399:
-		"000000" & X"000", -- 0x39A:
-		"000000" & X"000", -- 0x39B:
-		"000000" & X"000", -- 0x39C:
-		"000000" & X"000", -- 0x39D:
-		"000000" & X"000", -- 0x39E:
-		"000000" & X"000", -- 0x39F:
-		"000000" & X"000", -- 0x3A0:
-		"000000" & X"000", -- 0x3A1:
-		"000000" & X"000", -- 0x3A2:
-		"000000" & X"000", -- 0x3A3:
-		"000000" & X"000", -- 0x3A4:
-		"000000" & X"000", -- 0x3A5:
-		"000000" & X"000", -- 0x3A6:
-		"000000" & X"000", -- 0x3A7:
-		"000000" & X"000", -- 0x3A8:
-		"000000" & X"000", -- 0x3A9:
-		"000000" & X"000", -- 0x3AA:
-		"000000" & X"000", -- 0x3AB:
-		"000000" & X"000", -- 0x3AC:
-		"000000" & X"000", -- 0x3AD:
-		"000000" & X"000", -- 0x3AE:
-		"000000" & X"000", -- 0x3AF:
-		"000000" & X"000", -- 0x3B0:
-		"000000" & X"000", -- 0x3B1:
-		"000000" & X"000", -- 0x3B2:
-		"000000" & X"000", -- 0x3B3:
-		"000000" & X"000", -- 0x3B4:
-		"000000" & X"000", -- 0x3B5:
-		"000000" & X"000", -- 0x3B6:
-		"000000" & X"000", -- 0x3B7:
-		"000000" & X"000", -- 0x3B8:
-		"000000" & X"000", -- 0x3B9:
-		"000000" & X"000", -- 0x3BA:
-		"000000" & X"000", -- 0x3BB:
-		"000000" & X"000", -- 0x3BC:
-		"000000" & X"000", -- 0x3BD:
-		"000000" & X"000", -- 0x3BE:
-		"000000" & X"000", -- 0x3BF:
-		"000000" & X"000", -- 0x3C0:
-		"000000" & X"000", -- 0x3C1:
-		"000000" & X"000", -- 0x3C2:
-		"000000" & X"000", -- 0x3C3:
-		"000000" & X"000", -- 0x3C4:
-		"000000" & X"000", -- 0x3C5:
-		"000000" & X"000", -- 0x3C6:
-		"000000" & X"000", -- 0x3C7:
-		"000000" & X"000", -- 0x3C8:
-		"000000" & X"000", -- 0x3C9:
-		"000000" & X"000", -- 0x3CA:
-		"000000" & X"000", -- 0x3CB:
-		"000000" & X"000", -- 0x3CC:
-		"000000" & X"000", -- 0x3CD:
-		"000000" & X"000", -- 0x3CE:
-		"000000" & X"000", -- 0x3CF:
-		"000000" & X"000", -- 0x3D0:
-		"000000" & X"000", -- 0x3D1:
-		"000000" & X"000", -- 0x3D2:
-		"000000" & X"000", -- 0x3D3:
-		"000000" & X"000", -- 0x3D4:
-		"000000" & X"000", -- 0x3D5:
-		"000000" & X"000", -- 0x3D6:
-		"000000" & X"000", -- 0x3D7:
-		"000000" & X"000", -- 0x3D8:
-		"000000" & X"000", -- 0x3D9:
-		"000000" & X"000", -- 0x3DA:
-		"000000" & X"000", -- 0x3DB:
-		"000000" & X"000", -- 0x3DC:
-		"000000" & X"000", -- 0x3DD:
-		"000000" & X"000", -- 0x3DE:
-		"000000" & X"000", -- 0x3DF:
-		"000000" & X"000", -- 0x3E0:
-		"000000" & X"000", -- 0x3E1:
-		"000000" & X"000", -- 0x3E2:
-		"000000" & X"000", -- 0x3E3:
-		"000000" & X"000", -- 0x3E4:
-		"000000" & X"000", -- 0x3E5:
-		"000000" & X"000", -- 0x3E6:
-		"000000" & X"000", -- 0x3E7:
-		"000000" & X"000", -- 0x3E8:
-		"000000" & X"000", -- 0x3E9:
-		"000000" & X"000", -- 0x3EA:
-		"000000" & X"000", -- 0x3EB:
-		"000000" & X"000", -- 0x3EC:
-		"000000" & X"000", -- 0x3ED:
-		"000000" & X"000", -- 0x3EE:
-		"000000" & X"000", -- 0x3EF:
-		"000000" & X"000", -- 0x3F0:
-		"000000" & X"000", -- 0x3F1:
-		"000000" & X"000", -- 0x3F2:
-		"000000" & X"000", -- 0x3F3:
-		"000000" & X"000", -- 0x3F4:
-		"000000" & X"000", -- 0x3F5:
-		"000000" & X"000", -- 0x3F6:
-		"000000" & X"000", -- 0x3F7:
-		"000000" & X"000", -- 0x3F8:
-		"000000" & X"000", -- 0x3F9:
-		"000000" & X"000", -- 0x3FA:
-		"000000" & X"000", -- 0x3FB:
-		"000000" & X"000", -- 0x3FC:
-		"000000" & X"000", -- 0x3FD:
-		"000000" & X"000", -- 0x3FE:
-		"110000" & X"3FF"  -- 0x3FF: JMP 0x3FF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end itest;
-
diff --git a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl
deleted file mode 100644
index d4371a1..0000000
--- a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl
+++ /dev/null
@@ -1,1181 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from itest.jsm
-	type imem_rom_t is array (0 to 1023) of inst_t;
-	signal imem_rom : imem_rom_t :=
-	(
-		"110000" & X"010", -- 0x000: JMP 0x010
-		"110000" & X"288", -- 0x001: JMP 0x288
-		"000000" & X"000", -- 0x002:
-		"000000" & X"000", -- 0x003:
-		"000000" & X"000", -- 0x004:
-		"000000" & X"000", -- 0x005:
-		"000000" & X"000", -- 0x006:
-		"000000" & X"000", -- 0x007:
-		"000000" & X"000", -- 0x008:
-		"000000" & X"000", -- 0x009:
-		"000000" & X"000", -- 0x00A:
-		"000000" & X"000", -- 0x00B:
-		"000000" & X"000", -- 0x00C:
-		"000000" & X"000", -- 0x00D:
-		"000000" & X"000", -- 0x00E:
-		"000000" & X"000", -- 0x00F:
-		"111011" & X"03B", -- 0x010: CALL 0x03B
-		"101001" & X"000", -- 0x011: CIN R00, (0x00)
-		"100100" & X"000", -- 0x012: XOUT (0x00), R00
-		"111011" & X"04C", -- 0x013: CALL 0x04C
-		"000011" & X"010", -- 0x014: MOV R00, 0x01
-		"100100" & X"010", -- 0x015: XOUT (0x01), R00
-		"111011" & X"08D", -- 0x016: CALL 0x08D
-		"000011" & X"020", -- 0x017: MOV R00, 0x02
-		"100100" & X"010", -- 0x018: XOUT (0x01), R00
-		"111011" & X"0C9", -- 0x019: CALL 0x0C9
-		"000011" & X"030", -- 0x01A: MOV R00, 0x03
-		"100100" & X"010", -- 0x01B: XOUT (0x01), R00
-		"111011" & X"0DB", -- 0x01C: CALL 0x0DB
-		"000011" & X"040", -- 0x01D: MOV R00, 0x04
-		"100100" & X"010", -- 0x01E: XOUT (0x01), R00
-		"111011" & X"0ED", -- 0x01F: CALL 0x0ED
-		"000011" & X"050", -- 0x020: MOV R00, 0x05
-		"100100" & X"010", -- 0x021: XOUT (0x01), R00
-		"111011" & X"0FF", -- 0x022: CALL 0x0FF
-		"000011" & X"060", -- 0x023: MOV R00, 0x06
-		"100100" & X"010", -- 0x024: XOUT (0x01), R00
-		"111011" & X"115", -- 0x025: CALL 0x115
-		"000011" & X"070", -- 0x026: MOV R00, 0x07
-		"100100" & X"010", -- 0x027: XOUT (0x01), R00
-		"111011" & X"12B", -- 0x028: CALL 0x12B
-		"000011" & X"080", -- 0x029: MOV R00, 0x08
-		"100100" & X"010", -- 0x02A: XOUT (0x01), R00
-		"111011" & X"137", -- 0x02B: CALL 0x137
-		"000011" & X"090", -- 0x02C: MOV R00, 0x09
-		"100100" & X"010", -- 0x02D: XOUT (0x01), R00
-		"111011" & X"15A", -- 0x02E: CALL 0x15A
-		"000011" & X"0A0", -- 0x02F: MOV R00, 0x0A
-		"100100" & X"010", -- 0x030: XOUT (0x01), R00
-		"111011" & X"22A", -- 0x031: CALL 0x22A
-		"000011" & X"0B0", -- 0x032: MOV R00, 0x0B
-		"100100" & X"010", -- 0x033: XOUT (0x01), R00
-		"111011" & X"24D", -- 0x034: CALL 0x24D
-		"000011" & X"0C0", -- 0x035: MOV R00, 0x0C
-		"100100" & X"010", -- 0x036: XOUT (0x01), R00
-		"111011" & X"278", -- 0x037: CALL 0x278
-		"000011" & X"FF0", -- 0x038: MOV R00, 0xFF
-		"100100" & X"010", -- 0x039: XOUT (0x01), R00
-		"110000" & X"2FF", -- 0x03A: JMP 0x2FF
-		"000011" & X"000", -- 0x03B: MOV R00, 0x00
-		"000011" & X"001", -- 0x03C: MOV R01, 0x00
-		"000011" & X"002", -- 0x03D: MOV R02, 0x00
-		"000011" & X"003", -- 0x03E: MOV R03, 0x00
-		"000011" & X"004", -- 0x03F: MOV R04, 0x00
-		"000011" & X"005", -- 0x040: MOV R05, 0x00
-		"000011" & X"006", -- 0x041: MOV R06, 0x00
-		"000011" & X"007", -- 0x042: MOV R07, 0x00
-		"000011" & X"008", -- 0x043: MOV R08, 0x00
-		"000011" & X"009", -- 0x044: MOV R09, 0x00
-		"000011" & X"00A", -- 0x045: MOV R10, 0x00
-		"000011" & X"00B", -- 0x046: MOV R11, 0x00
-		"000011" & X"00C", -- 0x047: MOV R12, 0x00
-		"000011" & X"00D", -- 0x048: MOV R13, 0x00
-		"000011" & X"00E", -- 0x049: MOV R14, 0x00
-		"000011" & X"00F", -- 0x04A: MOV R15, 0x00
-		"111110" & X"000", -- 0x04B: RET
-		"000011" & X"100", -- 0x04C: MOV R00, 0x10
-		"001111" & X"100", -- 0x04D: CMP R00, 0x10
-		"111010" & X"3FF", -- 0x04E: JNE 0x3FF
-		"010001" & X"010", -- 0x04F: ADD R00, 0x01
-		"000010" & X"001", -- 0x050: MOV R01, R00
-		"001111" & X"111", -- 0x051: CMP R01, 0x11
-		"111010" & X"3FF", -- 0x052: JNE 0x3FF
-		"010001" & X"011", -- 0x053: ADD R01, 0x01
-		"000010" & X"012", -- 0x054: MOV R02, R01
-		"001111" & X"122", -- 0x055: CMP R02, 0x12
-		"111010" & X"3FF", -- 0x056: JNE 0x3FF
-		"010001" & X"012", -- 0x057: ADD R02, 0x01
-		"000010" & X"023", -- 0x058: MOV R03, R02
-		"001111" & X"133", -- 0x059: CMP R03, 0x13
-		"111010" & X"3FF", -- 0x05A: JNE 0x3FF
-		"010001" & X"013", -- 0x05B: ADD R03, 0x01
-		"000010" & X"034", -- 0x05C: MOV R04, R03
-		"001111" & X"144", -- 0x05D: CMP R04, 0x14
-		"111010" & X"3FF", -- 0x05E: JNE 0x3FF
-		"010001" & X"014", -- 0x05F: ADD R04, 0x01
-		"000010" & X"045", -- 0x060: MOV R05, R04
-		"001111" & X"155", -- 0x061: CMP R05, 0x15
-		"111010" & X"3FF", -- 0x062: JNE 0x3FF
-		"010001" & X"015", -- 0x063: ADD R05, 0x01
-		"000010" & X"056", -- 0x064: MOV R06, R05
-		"001111" & X"166", -- 0x065: CMP R06, 0x16
-		"111010" & X"3FF", -- 0x066: JNE 0x3FF
-		"010001" & X"016", -- 0x067: ADD R06, 0x01
-		"000010" & X"067", -- 0x068: MOV R07, R06
-		"001111" & X"177", -- 0x069: CMP R07, 0x17
-		"111010" & X"3FF", -- 0x06A: JNE 0x3FF
-		"010001" & X"017", -- 0x06B: ADD R07, 0x01
-		"000010" & X"078", -- 0x06C: MOV R08, R07
-		"001111" & X"188", -- 0x06D: CMP R08, 0x18
-		"111010" & X"3FF", -- 0x06E: JNE 0x3FF
-		"010001" & X"018", -- 0x06F: ADD R08, 0x01
-		"000010" & X"089", -- 0x070: MOV R09, R08
-		"001111" & X"199", -- 0x071: CMP R09, 0x19
-		"111010" & X"3FF", -- 0x072: JNE 0x3FF
-		"010001" & X"019", -- 0x073: ADD R09, 0x01
-		"000010" & X"09A", -- 0x074: MOV R10, R09
-		"001111" & X"1AA", -- 0x075: CMP R10, 0x1A
-		"111010" & X"3FF", -- 0x076: JNE 0x3FF
-		"010001" & X"01A", -- 0x077: ADD R10, 0x01
-		"000010" & X"0AB", -- 0x078: MOV R11, R10
-		"001111" & X"1BB", -- 0x079: CMP R11, 0x1B
-		"111010" & X"3FF", -- 0x07A: JNE 0x3FF
-		"010001" & X"01B", -- 0x07B: ADD R11, 0x01
-		"000010" & X"0BC", -- 0x07C: MOV R12, R11
-		"001111" & X"1CC", -- 0x07D: CMP R12, 0x1C
-		"111010" & X"3FF", -- 0x07E: JNE 0x3FF
-		"010001" & X"01C", -- 0x07F: ADD R12, 0x01
-		"000010" & X"0CD", -- 0x080: MOV R13, R12
-		"001111" & X"1DD", -- 0x081: CMP R13, 0x1D
-		"111010" & X"3FF", -- 0x082: JNE 0x3FF
-		"010001" & X"01D", -- 0x083: ADD R13, 0x01
-		"000010" & X"0DE", -- 0x084: MOV R14, R13
-		"001111" & X"1EE", -- 0x085: CMP R14, 0x1E
-		"111010" & X"3FF", -- 0x086: JNE 0x3FF
-		"010001" & X"01E", -- 0x087: ADD R14, 0x01
-		"000010" & X"0EF", -- 0x088: MOV R15, R14
-		"001111" & X"1FF", -- 0x089: CMP R15, 0x1F
-		"111010" & X"3FF", -- 0x08A: JNE 0x3FF
-		"010001" & X"01F", -- 0x08B: ADD R15, 0x01
-		"111110" & X"000", -- 0x08C: RET
-		"000011" & X"000", -- 0x08D: MOV R00, 0x00
-		"001111" & X"000", -- 0x08E: TST R00
-		"110010" & X"3FF", -- 0x08F: JNZ 0x3FF
-		"110011" & X"3FF", -- 0x090: JC 0x3FF
-		"001111" & X"000", -- 0x091: CMP R00, 0x00
-		"111010" & X"3FF", -- 0x092: JNE 0x3FF
-		"110101" & X"3FF", -- 0x093: JLT 0x3FF
-		"110110" & X"3FF", -- 0x094: JGT 0x3FF
-		"110111" & X"097", -- 0x095: JLE 0x097
-		"110000" & X"3FF", -- 0x096: JMP 0x3FF
-		"111001" & X"099", -- 0x097: JEQ 0x099
-		"110000" & X"3FF", -- 0x098: JMP 0x3FF
-		"111000" & X"09B", -- 0x099: JGE 0x09B
-		"110000" & X"3FF", -- 0x09A: JMP 0x3FF
-		"001111" & X"550", -- 0x09B: CMP R00, 0x55
-		"111001" & X"3FF", -- 0x09C: JEQ 0x3FF
-		"110101" & X"09F", -- 0x09D: JLT 0x09F
-		"110000" & X"3FF", -- 0x09E: JMP 0x3FF
-		"110111" & X"0A1", -- 0x09F: JLE 0x0A1
-		"110000" & X"3FF", -- 0x0A0: JMP 0x3FF
-		"111000" & X"3FF", -- 0x0A1: JGE 0x3FF
-		"110110" & X"3FF", -- 0x0A2: JGT 0x3FF
-		"000011" & X"550", -- 0x0A3: MOV R00, 0x55
-		"001111" & X"000", -- 0x0A4: TST R00
-		"110001" & X"3FF", -- 0x0A5: JZ 0x3FF
-		"110011" & X"3FF", -- 0x0A6: JC 0x3FF
-		"001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA
-		"111001" & X"3FF", -- 0x0A8: JEQ 0x3FF
-		"111010" & X"0AB", -- 0x0A9: JNE 0x0AB
-		"110000" & X"3FF", -- 0x0AA: JMP 0x3FF
-		"110101" & X"0AD", -- 0x0AB: JLT 0x0AD
-		"110000" & X"3FF", -- 0x0AC: JMP 0x3FF
-		"110111" & X"0AF", -- 0x0AD: JLE 0x0AF
-		"110000" & X"3FF", -- 0x0AE: JMP 0x3FF
-		"110110" & X"3FF", -- 0x0AF: JGT 0x3FF
-		"001111" & X"550", -- 0x0B0: CMP R00, 0x55
-		"111001" & X"0B3", -- 0x0B1: JEQ 0x0B3
-		"110000" & X"3FF", -- 0x0B2: JMP 0x3FF
-		"111010" & X"3FF", -- 0x0B3: JNE 0x3FF
-		"110101" & X"3FF", -- 0x0B4: JLT 0x3FF
-		"110111" & X"0B7", -- 0x0B5: JLE 0x0B7
-		"110000" & X"3FF", -- 0x0B6: JMP 0x3FF
-		"110110" & X"3FF", -- 0x0B7: JGT 0x3FF
-		"111000" & X"0BA", -- 0x0B8: JGE 0x0BA
-		"110000" & X"3FF", -- 0x0B9: JMP 0x3FF
-		"000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA
-		"001111" & X"000", -- 0x0BB: TST R00
-		"110001" & X"3FF", -- 0x0BC: JZ 0x3FF
-		"110011" & X"3FF", -- 0x0BD: JC 0x3FF
-		"001111" & X"550", -- 0x0BE: CMP R00, 0x55
-		"111001" & X"3FF", -- 0x0BF: JEQ 0x3FF
-		"111010" & X"0C2", -- 0x0C0: JNE 0x0C2
-		"110000" & X"3FF", -- 0x0C1: JMP 0x3FF
-		"110110" & X"0C4", -- 0x0C2: JGT 0x0C4
-		"110000" & X"3FF", -- 0x0C3: JMP 0x3FF
-		"111000" & X"0C6", -- 0x0C4: JGE 0x0C6
-		"110000" & X"3FF", -- 0x0C5: JMP 0x3FF
-		"110101" & X"3FF", -- 0x0C6: JLT 0x3FF
-		"110111" & X"3FF", -- 0x0C7: JLE 0x3FF
-		"111110" & X"000", -- 0x0C8: RET
-		"000011" & X"000", -- 0x0C9: MOV R00, 0x00
-		"000011" & X"001", -- 0x0CA: MOV R01, 0x00
-		"000010" & X"002", -- 0x0CB: MOV R02, R00
-		"000010" & X"013", -- 0x0CC: MOV R03, R01
-		"010001" & X"010", -- 0x0CD: ADD R00, 0x01
-		"010011" & X"001", -- 0x0CE: ADDC R01, 0x00
-		"010001" & X"012", -- 0x0CF: ADD R02, 0x01
-		"001111" & X"002", -- 0x0D0: CMP R02, 0x00
-		"111010" & X"0D4", -- 0x0D1: JNE 0x0D4
-		"010001" & X"013", -- 0x0D2: ADD R03, 0x01
-		"001111" & X"023", -- 0x0D3: CMP R03, 0x02
-		"111010" & X"0CD", -- 0x0D4: JNE 0x0CD
-		"001110" & X"020", -- 0x0D5: CMP R00, R02
-		"111010" & X"3FF", -- 0x0D6: JNE 0x3FF
-		"001110" & X"031", -- 0x0D7: CMP R01, R03
-		"111010" & X"3FF", -- 0x0D8: JNE 0x3FF
-		"000011" & X"000", -- 0x0D9: MOV R00, 0x00
-		"111110" & X"000", -- 0x0DA: RET
-		"000011" & X"000", -- 0x0DB: MOV R00, 0x00
-		"000011" & X"031", -- 0x0DC: MOV R01, 0x03
-		"000010" & X"002", -- 0x0DD: MOV R02, R00
-		"000010" & X"013", -- 0x0DE: MOV R03, R01
-		"010101" & X"010", -- 0x0DF: SUB R00, 0x01
-		"010111" & X"001", -- 0x0E0: SUBC R01, 0x00
-		"010101" & X"012", -- 0x0E1: SUB R02, 0x01
-		"001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF
-		"111010" & X"0E6", -- 0x0E3: JNE 0x0E6
-		"010101" & X"013", -- 0x0E4: SUB R03, 0x01
-		"001111" & X"003", -- 0x0E5: CMP R03, 0x00
-		"111010" & X"0DF", -- 0x0E6: JNE 0x0DF
-		"001110" & X"020", -- 0x0E7: CMP R00, R02
-		"111010" & X"3FF", -- 0x0E8: JNE 0x3FF
-		"001110" & X"031", -- 0x0E9: CMP R01, R03
-		"111010" & X"3FF", -- 0x0EA: JNE 0x3FF
-		"000011" & X"000", -- 0x0EB: MOV R00, 0x00
-		"111110" & X"000", -- 0x0EC: RET
-		"000011" & X"030", -- 0x0ED: MOV R00, 0x03
-		"000011" & X"051", -- 0x0EE: MOV R01, 0x05
-		"101110" & X"050", -- 0x0EF: SUB 0x05, R00
-		"010101" & X"031", -- 0x0F0: SUB R01, 0x03
-		"001110" & X"010", -- 0x0F1: CMP R00, R01
-		"111010" & X"3FF", -- 0x0F2: JNE 0x3FF
-		"000011" & X"030", -- 0x0F3: MOV R00, 0x03
-		"000011" & X"051", -- 0x0F4: MOV R01, 0x05
-		"010100" & X"010", -- 0x0F5: SUB R00, R01
-		"101111" & X"000", -- 0x0F6: SUBC 0x00, R00
-		"001111" & X"010", -- 0x0F7: CMP R00, 0x01
-		"111010" & X"3FF", -- 0x0F8: JNE 0x3FF
-		"010001" & X"000", -- 0x0F9: ADD R00, 0x00
-		"010110" & X"001", -- 0x0FA: SUBC R01, R00
-		"001111" & X"041", -- 0x0FB: CMP R01, 0x04
-		"111010" & X"3FF", -- 0x0FC: JNE 0x3FF
-		"000011" & X"000", -- 0x0FD: MOV R00, 0x00
-		"111110" & X"000", -- 0x0FE: RET
-		"000011" & X"010", -- 0x0FF: MOV R00, 0x01
-		"001101" & X"5A0", -- 0x100: MOVC (0x5A), R00
-		"010101" & X"010", -- 0x101: DEC R00
-		"001101" & X"000", -- 0x102: MOVC (0x00), R00
-		"001010" & X"5A1", -- 0x103: MOVC R01, (0x5A)
-		"001100" & X"A51", -- 0x104: MOVC (R01), 0xA5
-		"001001" & X"010", -- 0x105: MOVC R00, (R01)
-		"001001" & X"011", -- 0x106: MOVC R01, (R01)
-		"010001" & X"5A1", -- 0x107: ADD R01, 0x5A
-		"001001" & X"010", -- 0x108: MOVC R00, (R01)
-		"001011" & X"000", -- 0x109: MOVC (R00), R00
-		"001001" & X"002", -- 0x10A: MOVC R02, (R00)
-		"001110" & X"002", -- 0x10B: CMP R02, R00
-		"111010" & X"3FF", -- 0x10C: JNE 0x3FF
-		"001011" & X"021", -- 0x10D: MOVC (R01), R02
-		"001001" & X"022", -- 0x10E: MOVC R02, (R02)
-		"001110" & X"012", -- 0x10F: CMP R02, R01
-		"111010" & X"3FF", -- 0x110: JNE 0x3FF
-		"010101" & X"011", -- 0x111: DEC R01
-		"010001" & X"010", -- 0x112: INC R00
-		"110010" & X"109", -- 0x113: JNZ 0x109
-		"111110" & X"000", -- 0x114: RET
-		"000011" & X"010", -- 0x115: MOV R00, 0x01
-		"001000" & X"600", -- 0x116: MOVX (0x60), R00
-		"010101" & X"010", -- 0x117: DEC R00
-		"001000" & X"060", -- 0x118: MOVX (0x06), R00
-		"000101" & X"601", -- 0x119: MOVX R01, (0x60)
-		"000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5
-		"000100" & X"010", -- 0x11B: MOVX R00, (R01)
-		"000100" & X"011", -- 0x11C: MOVX R01, (R01)
-		"010001" & X"5A1", -- 0x11D: ADD R01, 0x5A
-		"000100" & X"010", -- 0x11E: MOVX R00, (R01)
-		"000110" & X"000", -- 0x11F: MOVX (R00), R00
-		"000100" & X"002", -- 0x120: MOVX R02, (R00)
-		"001110" & X"002", -- 0x121: CMP R02, R00
-		"111010" & X"3FF", -- 0x122: JNE 0x3FF
-		"000110" & X"021", -- 0x123: MOVX (R01), R02
-		"000100" & X"022", -- 0x124: MOVX R02, (R02)
-		"001110" & X"012", -- 0x125: CMP R02, R01
-		"111010" & X"3FF", -- 0x126: JNE 0x3FF
-		"010101" & X"011", -- 0x127: DEC R01
-		"010001" & X"010", -- 0x128: INC R00
-		"110010" & X"11F", -- 0x129: JNZ 0x11F
-		"111110" & X"000", -- 0x12A: RET
-		"000011" & X"AA0", -- 0x12B: MOV R00, 0xAA
-		"000011" & X"001", -- 0x12C: MOV R01, 0x00
-		"111100" & X"000", -- 0x12D: PUSH R00
-		"010001" & X"010", -- 0x12E: INC R00
-		"010101" & X"011", -- 0x12F: DEC R01
-		"110010" & X"12D", -- 0x130: JNZ 0x12D
-		"111101" & X"000", -- 0x131: POP R00
-		"010101" & X"011", -- 0x132: DEC R01
-		"110010" & X"131", -- 0x133: JNZ 0x131
-		"001111" & X"AA0", -- 0x134: CMP R00, 0xAA
-		"111010" & X"3FF", -- 0x135: JNE 0x3FF
-		"111110" & X"000", -- 0x136: RET
-		"000011" & X"550", -- 0x137: MOV R00, 0x55
-		"111100" & X"000", -- 0x138: PUSH R00
-		"000011" & X"000", -- 0x139: MOV R00, 0x00
-		"000011" & X"FF1", -- 0x13A: MOV R01, 0xFF
-		"111011" & X"151", -- 0x13B: CALL 0x151
-		"111101" & X"000", -- 0x13C: POP R00
-		"001111" & X"550", -- 0x13D: CMP R00, 0x55
-		"111010" & X"3FF", -- 0x13E: JNE 0x3FF
-		"000011" & X"010", -- 0x13F: MOV R00, 0x01
-		"000011" & X"481", -- 0x140: MOV R01, 0x48
-		"100110" & X"050", -- 0x141: COUT (0x05), R00
-		"111100" & X"001", -- 0x142: PUSH R01
-		"000011" & X"000", -- 0x143: MOV R00, 0x00
-		"000011" & X"3B1", -- 0x144: MOV R01, 0x3B
-		"100110" & X"050", -- 0x145: COUT (0x05), R00
-		"111100" & X"001", -- 0x146: PUSH R01
-		"111110" & X"000", -- 0x147: RET
-		"000011" & X"010", -- 0x148: MOV R00, 0x01
-		"000011" & X"501", -- 0x149: MOV R01, 0x50
-		"100110" & X"050", -- 0x14A: COUT (0x05), R00
-		"111100" & X"001", -- 0x14B: PUSH R01
-		"000011" & X"000", -- 0x14C: MOV R00, 0x00
-		"000011" & X"3B1", -- 0x14D: MOV R01, 0x3B
-		"100110" & X"050", -- 0x14E: COUT (0x05), R00
-		"111100" & X"001", -- 0x14F: PUSH R01
-		"111110" & X"000", -- 0x150: RET
-		"001110" & X"010", -- 0x151: CMP R00, R01
-		"111001" & X"155", -- 0x152: JEQ 0x155
-		"010001" & X"010", -- 0x153: INC R00
-		"110000" & X"158", -- 0x154: JMP 0x158
-		"010101" & X"010", -- 0x155: DEC R00
-		"010101" & X"011", -- 0x156: DEC R01
-		"111110" & X"000", -- 0x157: RET
-		"111011" & X"151", -- 0x158: CALL 0x151
-		"110000" & X"155", -- 0x159: JMP 0x155
-		"000011" & X"A50", -- 0x15A: MOV R00, 0xA5
-		"000011" & X"5A1", -- 0x15B: MOV R01, 0x5A
-		"101010" & X"000", -- 0x15C: SWAP R00
-		"001111" & X"5A0", -- 0x15D: CMP R00, 0x5A
-		"111010" & X"3FF", -- 0x15E: JNE 0x3FF
-		"101010" & X"000", -- 0x15F: SWAP R00
-		"001111" & X"A50", -- 0x160: CMP R00, 0xA5
-		"111010" & X"3FF", -- 0x161: JNE 0x3FF
-		"000011" & X"D20", -- 0x162: MOV R00, 0xD2
-		"101010" & X"000", -- 0x163: SWAP R00
-		"001111" & X"2D0", -- 0x164: CMP R00, 0x2D
-		"111010" & X"3FF", -- 0x165: JNE 0x3FF
-		"101010" & X"001", -- 0x166: SWAP R01
-		"001111" & X"2D0", -- 0x167: CMP R00, 0x2D
-		"111010" & X"3FF", -- 0x168: JNE 0x3FF
-		"001111" & X"A51", -- 0x169: CMP R01, 0xA5
-		"111010" & X"3FF", -- 0x16A: JNE 0x3FF
-		"000011" & X"2D0", -- 0x16B: MOV R00, 0x2D
-		"011110" & X"000", -- 0x16C: SHL R00
-		"001111" & X"5A0", -- 0x16D: CMP R00, 0x5A
-		"111010" & X"3FF", -- 0x16E: JNE 0x3FF
-		"011110" & X"000", -- 0x16F: SHL R00
-		"001111" & X"B40", -- 0x170: CMP R00, 0xB4
-		"111010" & X"3FF", -- 0x171: JNE 0x3FF
-		"011110" & X"000", -- 0x172: SHL R00
-		"001111" & X"680", -- 0x173: CMP R00, 0x68
-		"111010" & X"3FF", -- 0x174: JNE 0x3FF
-		"011110" & X"000", -- 0x175: SHL R00
-		"001111" & X"D00", -- 0x176: CMP R00, 0xD0
-		"111010" & X"3FF", -- 0x177: JNE 0x3FF
-		"011110" & X"000", -- 0x178: SHL R00
-		"001111" & X"A00", -- 0x179: CMP R00, 0xA0
-		"111010" & X"3FF", -- 0x17A: JNE 0x3FF
-		"011110" & X"000", -- 0x17B: SHL R00
-		"001111" & X"400", -- 0x17C: CMP R00, 0x40
-		"111010" & X"3FF", -- 0x17D: JNE 0x3FF
-		"011110" & X"000", -- 0x17E: SHL R00
-		"001111" & X"800", -- 0x17F: CMP R00, 0x80
-		"111010" & X"3FF", -- 0x180: JNE 0x3FF
-		"011110" & X"000", -- 0x181: SHL R00
-		"001111" & X"000", -- 0x182: CMP R00, 0x00
-		"111010" & X"3FF", -- 0x183: JNE 0x3FF
-		"000011" & X"841", -- 0x184: MOV R01, 0x84
-		"011111" & X"001", -- 0x185: SHR R01
-		"001111" & X"421", -- 0x186: CMP R01, 0x42
-		"111010" & X"3FF", -- 0x187: JNE 0x3FF
-		"011111" & X"001", -- 0x188: SHR R01
-		"001111" & X"211", -- 0x189: CMP R01, 0x21
-		"111010" & X"3FF", -- 0x18A: JNE 0x3FF
-		"011111" & X"001", -- 0x18B: SHR R01
-		"001111" & X"101", -- 0x18C: CMP R01, 0x10
-		"111010" & X"3FF", -- 0x18D: JNE 0x3FF
-		"011111" & X"001", -- 0x18E: SHR R01
-		"001111" & X"081", -- 0x18F: CMP R01, 0x08
-		"111010" & X"3FF", -- 0x190: JNE 0x3FF
-		"011111" & X"001", -- 0x191: SHR R01
-		"001111" & X"041", -- 0x192: CMP R01, 0x04
-		"111010" & X"3FF", -- 0x193: JNE 0x3FF
-		"011111" & X"001", -- 0x194: SHR R01
-		"001111" & X"021", -- 0x195: CMP R01, 0x02
-		"111010" & X"3FF", -- 0x196: JNE 0x3FF
-		"011111" & X"001", -- 0x197: SHR R01
-		"001111" & X"011", -- 0x198: CMP R01, 0x01
-		"111010" & X"3FF", -- 0x199: JNE 0x3FF
-		"011111" & X"001", -- 0x19A: SHR R01
-		"001111" & X"001", -- 0x19B: CMP R01, 0x00
-		"111010" & X"3FF", -- 0x19C: JNE 0x3FF
-		"000011" & X"C50", -- 0x19D: MOV R00, 0xC5
-		"100000" & X"000", -- 0x19E: ROL R00
-		"001111" & X"8B0", -- 0x19F: CMP R00, 0x8B
-		"111010" & X"3FF", -- 0x1A0: JNE 0x3FF
-		"100000" & X"000", -- 0x1A1: ROL R00
-		"001111" & X"170", -- 0x1A2: CMP R00, 0x17
-		"111010" & X"3FF", -- 0x1A3: JNE 0x3FF
-		"100000" & X"000", -- 0x1A4: ROL R00
-		"001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E
-		"111010" & X"3FF", -- 0x1A6: JNE 0x3FF
-		"100000" & X"000", -- 0x1A7: ROL R00
-		"001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C
-		"111010" & X"3FF", -- 0x1A9: JNE 0x3FF
-		"100000" & X"000", -- 0x1AA: ROL R00
-		"001111" & X"B80", -- 0x1AB: CMP R00, 0xB8
-		"111010" & X"3FF", -- 0x1AC: JNE 0x3FF
-		"100000" & X"000", -- 0x1AD: ROL R00
-		"001111" & X"710", -- 0x1AE: CMP R00, 0x71
-		"111010" & X"3FF", -- 0x1AF: JNE 0x3FF
-		"100000" & X"000", -- 0x1B0: ROL R00
-		"001111" & X"E20", -- 0x1B1: CMP R00, 0xE2
-		"111010" & X"3FF", -- 0x1B2: JNE 0x3FF
-		"100000" & X"000", -- 0x1B3: ROL R00
-		"001111" & X"C50", -- 0x1B4: CMP R00, 0xC5
-		"111010" & X"3FF", -- 0x1B5: JNE 0x3FF
-		"000011" & X"631", -- 0x1B6: MOV R01, 0x63
-		"100001" & X"001", -- 0x1B7: ROR R01
-		"001111" & X"B11", -- 0x1B8: CMP R01, 0xB1
-		"111010" & X"3FF", -- 0x1B9: JNE 0x3FF
-		"100001" & X"001", -- 0x1BA: ROR R01
-		"001111" & X"D81", -- 0x1BB: CMP R01, 0xD8
-		"111010" & X"3FF", -- 0x1BC: JNE 0x3FF
-		"100001" & X"001", -- 0x1BD: ROR R01
-		"001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C
-		"111010" & X"3FF", -- 0x1BF: JNE 0x3FF
-		"100001" & X"001", -- 0x1C0: ROR R01
-		"001111" & X"361", -- 0x1C1: CMP R01, 0x36
-		"111010" & X"3FF", -- 0x1C2: JNE 0x3FF
-		"100001" & X"001", -- 0x1C3: ROR R01
-		"001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B
-		"111010" & X"3FF", -- 0x1C5: JNE 0x3FF
-		"100001" & X"001", -- 0x1C6: ROR R01
-		"001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D
-		"111010" & X"3FF", -- 0x1C8: JNE 0x3FF
-		"100001" & X"001", -- 0x1C9: ROR R01
-		"001111" & X"C61", -- 0x1CA: CMP R01, 0xC6
-		"111010" & X"3FF", -- 0x1CB: JNE 0x3FF
-		"100001" & X"001", -- 0x1CC: ROR R01
-		"001111" & X"631", -- 0x1CD: CMP R01, 0x63
-		"111010" & X"3FF", -- 0x1CE: JNE 0x3FF
-		"011100" & X"000", -- 0x1CF: XOR R00, R00
-		"000011" & X"C50", -- 0x1D0: MOV R00, 0xC5
-		"100010" & X"000", -- 0x1D1: ROLC R00
-		"111100" & X"000", -- 0x1D2: PUSH R00
-		"100010" & X"000", -- 0x1D3: ROLC R00
-		"111100" & X"000", -- 0x1D4: PUSH R00
-		"100010" & X"000", -- 0x1D5: ROLC R00
-		"111100" & X"000", -- 0x1D6: PUSH R00
-		"100010" & X"000", -- 0x1D7: ROLC R00
-		"111100" & X"000", -- 0x1D8: PUSH R00
-		"100010" & X"000", -- 0x1D9: ROLC R00
-		"111100" & X"000", -- 0x1DA: PUSH R00
-		"100010" & X"000", -- 0x1DB: ROLC R00
-		"111100" & X"000", -- 0x1DC: PUSH R00
-		"100010" & X"000", -- 0x1DD: ROLC R00
-		"111100" & X"000", -- 0x1DE: PUSH R00
-		"100010" & X"000", -- 0x1DF: ROLC R00
-		"111100" & X"000", -- 0x1E0: PUSH R00
-		"100010" & X"000", -- 0x1E1: ROLC R00
-		"001111" & X"C50", -- 0x1E2: CMP R00, 0xC5
-		"111010" & X"3FF", -- 0x1E3: JNE 0x3FF
-		"111101" & X"000", -- 0x1E4: POP R00
-		"001111" & X"620", -- 0x1E5: CMP R00, 0x62
-		"111010" & X"3FF", -- 0x1E6: JNE 0x3FF
-		"111101" & X"000", -- 0x1E7: POP R00
-		"001111" & X"B10", -- 0x1E8: CMP R00, 0xB1
-		"111010" & X"3FF", -- 0x1E9: JNE 0x3FF
-		"111101" & X"000", -- 0x1EA: POP R00
-		"001111" & X"580", -- 0x1EB: CMP R00, 0x58
-		"111010" & X"3FF", -- 0x1EC: JNE 0x3FF
-		"111101" & X"000", -- 0x1ED: POP R00
-		"001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC
-		"111010" & X"3FF", -- 0x1EF: JNE 0x3FF
-		"111101" & X"000", -- 0x1F0: POP R00
-		"001111" & X"560", -- 0x1F1: CMP R00, 0x56
-		"111010" & X"3FF", -- 0x1F2: JNE 0x3FF
-		"111101" & X"000", -- 0x1F3: POP R00
-		"001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B
-		"111010" & X"3FF", -- 0x1F5: JNE 0x3FF
-		"111101" & X"000", -- 0x1F6: POP R00
-		"001111" & X"150", -- 0x1F7: CMP R00, 0x15
-		"111010" & X"3FF", -- 0x1F8: JNE 0x3FF
-		"111101" & X"000", -- 0x1F9: POP R00
-		"001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A
-		"111010" & X"3FF", -- 0x1FB: JNE 0x3FF
-		"011100" & X"011", -- 0x1FC: XOR R01, R01
-		"000011" & X"631", -- 0x1FD: MOV R01, 0x63
-		"100011" & X"001", -- 0x1FE: RORC R01
-		"111100" & X"001", -- 0x1FF: PUSH R01
-		"100011" & X"001", -- 0x200: RORC R01
-		"111100" & X"001", -- 0x201: PUSH R01
-		"100011" & X"001", -- 0x202: RORC R01
-		"111100" & X"001", -- 0x203: PUSH R01
-		"100011" & X"001", -- 0x204: RORC R01
-		"111100" & X"001", -- 0x205: PUSH R01
-		"100011" & X"001", -- 0x206: RORC R01
-		"111100" & X"001", -- 0x207: PUSH R01
-		"100011" & X"001", -- 0x208: RORC R01
-		"111100" & X"001", -- 0x209: PUSH R01
-		"100011" & X"001", -- 0x20A: RORC R01
-		"111100" & X"001", -- 0x20B: PUSH R01
-		"100011" & X"001", -- 0x20C: RORC R01
-		"111100" & X"001", -- 0x20D: PUSH R01
-		"100011" & X"001", -- 0x20E: RORC R01
-		"001111" & X"631", -- 0x20F: CMP R01, 0x63
-		"111010" & X"3FF", -- 0x210: JNE 0x3FF
-		"111101" & X"001", -- 0x211: POP R01
-		"001111" & X"C61", -- 0x212: CMP R01, 0xC6
-		"111010" & X"3FF", -- 0x213: JNE 0x3FF
-		"111101" & X"001", -- 0x214: POP R01
-		"001111" & X"8C1", -- 0x215: CMP R01, 0x8C
-		"111010" & X"3FF", -- 0x216: JNE 0x3FF
-		"111101" & X"001", -- 0x217: POP R01
-		"001111" & X"191", -- 0x218: CMP R01, 0x19
-		"111010" & X"3FF", -- 0x219: JNE 0x3FF
-		"111101" & X"001", -- 0x21A: POP R01
-		"001111" & X"331", -- 0x21B: CMP R01, 0x33
-		"111010" & X"3FF", -- 0x21C: JNE 0x3FF
-		"111101" & X"001", -- 0x21D: POP R01
-		"001111" & X"661", -- 0x21E: CMP R01, 0x66
-		"111010" & X"3FF", -- 0x21F: JNE 0x3FF
-		"111101" & X"001", -- 0x220: POP R01
-		"001111" & X"CC1", -- 0x221: CMP R01, 0xCC
-		"111010" & X"3FF", -- 0x222: JNE 0x3FF
-		"111101" & X"001", -- 0x223: POP R01
-		"001111" & X"981", -- 0x224: CMP R01, 0x98
-		"111010" & X"3FF", -- 0x225: JNE 0x3FF
-		"111101" & X"001", -- 0x226: POP R01
-		"001111" & X"311", -- 0x227: CMP R01, 0x31
-		"111010" & X"3FF", -- 0x228: JNE 0x3FF
-		"111110" & X"000", -- 0x229: RET
-		"000011" & X"A50", -- 0x22A: MOV R00, 0xA5
-		"101010" & X"000", -- 0x22B: SWAP R00
-		"111100" & X"000", -- 0x22C: PUSH R00
-		"011001" & X"0F0", -- 0x22D: AND R00, 0x0F
-		"001111" & X"0A0", -- 0x22E: CMP R00, 0x0A
-		"111010" & X"3FF", -- 0x22F: JNE 0x3FF
-		"111101" & X"000", -- 0x230: POP R00
-		"111100" & X"000", -- 0x231: PUSH R00
-		"011001" & X"0F0", -- 0x232: AND R00, 0x0F
-		"001111" & X"0A0", -- 0x233: CMP R00, 0x0A
-		"111101" & X"001", -- 0x234: POP R01
-		"111010" & X"3FF", -- 0x235: JNE 0x3FF
-		"101010" & X"001", -- 0x236: SWAP R01
-		"000011" & X"0F2", -- 0x237: MOV R02, 0x0F
-		"011000" & X"021", -- 0x238: AND R01, R02
-		"001111" & X"051", -- 0x239: CMP R01, 0x05
-		"111010" & X"3FF", -- 0x23A: JNE 0x3FF
-		"000011" & X"050", -- 0x23B: MOV R00, 0x05
-		"000011" & X"A02", -- 0x23C: MOV R02, 0xA0
-		"101010" & X"000", -- 0x23D: SWAP R00
-		"011010" & X"002", -- 0x23E: OR R02, R00
-		"001111" & X"F02", -- 0x23F: CMP R02, 0xF0
-		"111010" & X"3FF", -- 0x240: JNE 0x3FF
-		"101010" & X"000", -- 0x241: SWAP R00
-		"011011" & X"500", -- 0x242: OR R00, 0x50
-		"001111" & X"550", -- 0x243: CMP R00, 0x55
-		"111010" & X"3FF", -- 0x244: JNE 0x3FF
-		"000011" & X"011", -- 0x245: MOV R01, 0x01
-		"000011" & X"010", -- 0x246: MOV R00, 0x01
-		"011101" & X"010", -- 0x247: XOR R00, 0x01
-		"110010" & X"3FF", -- 0x248: JNZ 0x3FF
-		"011100" & X"010", -- 0x249: XOR R00, R01
-		"001111" & X"010", -- 0x24A: CMP R00, 0x01
-		"111010" & X"3FF", -- 0x24B: JNE 0x3FF
-		"111110" & X"000", -- 0x24C: RET
-		"000011" & X"030", -- 0x24D: MOV R00, 0x03
-		"100110" & X"030", -- 0x24E: COUT (0x03), R00
-		"101000" & X"020", -- 0x24F: XIN R00, (0x02)
-		"011011" & X"010", -- 0x250: OR R00, 0x01
-		"100100" & X"020", -- 0x251: XOUT (0x02), R00
-		"000000" & X"000", -- 0x252: NOP
-		"000000" & X"000", -- 0x253: NOP
-		"000000" & X"000", -- 0x254: NOP
-		"000000" & X"000", -- 0x255: NOP
-		"000000" & X"000", -- 0x256: NOP
-		"000000" & X"000", -- 0x257: NOP
-		"101000" & X"020", -- 0x258: XIN R00, (0x02)
-		"011001" & X"FE0", -- 0x259: AND R00, 0xFE
-		"100100" & X"020", -- 0x25A: XOUT (0x02), R00
-		"000000" & X"000", -- 0x25B: NOP
-		"000000" & X"000", -- 0x25C: NOP
-		"000000" & X"000", -- 0x25D: NOP
-		"000000" & X"000", -- 0x25E: NOP
-		"101001" & X"030", -- 0x25F: CIN R00, (0x03)
-		"011011" & X"800", -- 0x260: OR R00, 0x80
-		"100110" & X"030", -- 0x261: COUT (0x03), R00
-		"000000" & X"000", -- 0x262: NOP
-		"101001" & X"030", -- 0x263: CIN R00, (0x03)
-		"011011" & X"800", -- 0x264: OR R00, 0x80
-		"100110" & X"030", -- 0x265: COUT (0x03), R00
-		"000000" & X"000", -- 0x266: NOP
-		"101001" & X"030", -- 0x267: CIN R00, (0x03)
-		"011011" & X"800", -- 0x268: OR R00, 0x80
-		"100110" & X"030", -- 0x269: COUT (0x03), R00
-		"000000" & X"000", -- 0x26A: NOP
-		"101001" & X"030", -- 0x26B: CIN R00, (0x03)
-		"011011" & X"800", -- 0x26C: OR R00, 0x80
-		"100110" & X"030", -- 0x26D: COUT (0x03), R00
-		"000000" & X"000", -- 0x26E: NOP
-		"000000" & X"000", -- 0x26F: NOP
-		"000000" & X"000", -- 0x270: NOP
-		"000000" & X"000", -- 0x271: NOP
-		"000000" & X"000", -- 0x272: NOP
-		"000000" & X"000", -- 0x273: NOP
-		"000000" & X"000", -- 0x274: NOP
-		"000000" & X"000", -- 0x275: NOP
-		"000000" & X"000", -- 0x276: NOP
-		"111110" & X"000", -- 0x277: RET
-		"010101" & X"000", -- 0x278: SUB R00, 0x00
-		"110011" & X"3FF", -- 0x279: JC 0x3FF
-		"101011" & X"000", -- 0x27A: SETC
-		"110100" & X"3FF", -- 0x27B: JNC 0x3FF
-		"000000" & X"000", -- 0x27C: NOP
-		"010101" & X"000", -- 0x27D: SUB R00, 0x00
-		"110011" & X"3FF", -- 0x27E: JC 0x3FF
-		"000011" & X"000", -- 0x27F: MOV R00, 0x00
-		"010101" & X"000", -- 0x280: CLRC
-		"110011" & X"3FF", -- 0x281: JC 0x3FF
-		"101011" & X"000", -- 0x282: SETC
-		"110100" & X"3FF", -- 0x283: JNC 0x3FF
-		"000000" & X"000", -- 0x284: NOP
-		"010101" & X"000", -- 0x285: CLRC
-		"110011" & X"3FF", -- 0x286: JC 0x3FF
-		"111110" & X"000", -- 0x287: RET
-		"010001" & X"01E", -- 0x288: INC R14
-		"111111" & X"000", -- 0x289: RETI
-		"000000" & X"000", -- 0x28A:
-		"000000" & X"000", -- 0x28B:
-		"000000" & X"000", -- 0x28C:
-		"000000" & X"000", -- 0x28D:
-		"000000" & X"000", -- 0x28E:
-		"000000" & X"000", -- 0x28F:
-		"000000" & X"000", -- 0x290:
-		"000000" & X"000", -- 0x291:
-		"000000" & X"000", -- 0x292:
-		"000000" & X"000", -- 0x293:
-		"000000" & X"000", -- 0x294:
-		"000000" & X"000", -- 0x295:
-		"000000" & X"000", -- 0x296:
-		"000000" & X"000", -- 0x297:
-		"000000" & X"000", -- 0x298:
-		"000000" & X"000", -- 0x299:
-		"000000" & X"000", -- 0x29A:
-		"000000" & X"000", -- 0x29B:
-		"000000" & X"000", -- 0x29C:
-		"000000" & X"000", -- 0x29D:
-		"000000" & X"000", -- 0x29E:
-		"000000" & X"000", -- 0x29F:
-		"000000" & X"000", -- 0x2A0:
-		"000000" & X"000", -- 0x2A1:
-		"000000" & X"000", -- 0x2A2:
-		"000000" & X"000", -- 0x2A3:
-		"000000" & X"000", -- 0x2A4:
-		"000000" & X"000", -- 0x2A5:
-		"000000" & X"000", -- 0x2A6:
-		"000000" & X"000", -- 0x2A7:
-		"000000" & X"000", -- 0x2A8:
-		"000000" & X"000", -- 0x2A9:
-		"000000" & X"000", -- 0x2AA:
-		"000000" & X"000", -- 0x2AB:
-		"000000" & X"000", -- 0x2AC:
-		"000000" & X"000", -- 0x2AD:
-		"000000" & X"000", -- 0x2AE:
-		"000000" & X"000", -- 0x2AF:
-		"000000" & X"000", -- 0x2B0:
-		"000000" & X"000", -- 0x2B1:
-		"000000" & X"000", -- 0x2B2:
-		"000000" & X"000", -- 0x2B3:
-		"000000" & X"000", -- 0x2B4:
-		"000000" & X"000", -- 0x2B5:
-		"000000" & X"000", -- 0x2B6:
-		"000000" & X"000", -- 0x2B7:
-		"000000" & X"000", -- 0x2B8:
-		"000000" & X"000", -- 0x2B9:
-		"000000" & X"000", -- 0x2BA:
-		"000000" & X"000", -- 0x2BB:
-		"000000" & X"000", -- 0x2BC:
-		"000000" & X"000", -- 0x2BD:
-		"000000" & X"000", -- 0x2BE:
-		"000000" & X"000", -- 0x2BF:
-		"000000" & X"000", -- 0x2C0:
-		"000000" & X"000", -- 0x2C1:
-		"000000" & X"000", -- 0x2C2:
-		"000000" & X"000", -- 0x2C3:
-		"000000" & X"000", -- 0x2C4:
-		"000000" & X"000", -- 0x2C5:
-		"000000" & X"000", -- 0x2C6:
-		"000000" & X"000", -- 0x2C7:
-		"000000" & X"000", -- 0x2C8:
-		"000000" & X"000", -- 0x2C9:
-		"000000" & X"000", -- 0x2CA:
-		"000000" & X"000", -- 0x2CB:
-		"000000" & X"000", -- 0x2CC:
-		"000000" & X"000", -- 0x2CD:
-		"000000" & X"000", -- 0x2CE:
-		"000000" & X"000", -- 0x2CF:
-		"000000" & X"000", -- 0x2D0:
-		"000000" & X"000", -- 0x2D1:
-		"000000" & X"000", -- 0x2D2:
-		"000000" & X"000", -- 0x2D3:
-		"000000" & X"000", -- 0x2D4:
-		"000000" & X"000", -- 0x2D5:
-		"000000" & X"000", -- 0x2D6:
-		"000000" & X"000", -- 0x2D7:
-		"000000" & X"000", -- 0x2D8:
-		"000000" & X"000", -- 0x2D9:
-		"000000" & X"000", -- 0x2DA:
-		"000000" & X"000", -- 0x2DB:
-		"000000" & X"000", -- 0x2DC:
-		"000000" & X"000", -- 0x2DD:
-		"000000" & X"000", -- 0x2DE:
-		"000000" & X"000", -- 0x2DF:
-		"000000" & X"000", -- 0x2E0:
-		"000000" & X"000", -- 0x2E1:
-		"000000" & X"000", -- 0x2E2:
-		"000000" & X"000", -- 0x2E3:
-		"000000" & X"000", -- 0x2E4:
-		"000000" & X"000", -- 0x2E5:
-		"000000" & X"000", -- 0x2E6:
-		"000000" & X"000", -- 0x2E7:
-		"000000" & X"000", -- 0x2E8:
-		"000000" & X"000", -- 0x2E9:
-		"000000" & X"000", -- 0x2EA:
-		"000000" & X"000", -- 0x2EB:
-		"000000" & X"000", -- 0x2EC:
-		"000000" & X"000", -- 0x2ED:
-		"000000" & X"000", -- 0x2EE:
-		"000000" & X"000", -- 0x2EF:
-		"000000" & X"000", -- 0x2F0:
-		"000000" & X"000", -- 0x2F1:
-		"000000" & X"000", -- 0x2F2:
-		"000000" & X"000", -- 0x2F3:
-		"000000" & X"000", -- 0x2F4:
-		"000000" & X"000", -- 0x2F5:
-		"000000" & X"000", -- 0x2F6:
-		"000000" & X"000", -- 0x2F7:
-		"000000" & X"000", -- 0x2F8:
-		"000000" & X"000", -- 0x2F9:
-		"000000" & X"000", -- 0x2FA:
-		"000000" & X"000", -- 0x2FB:
-		"000000" & X"000", -- 0x2FC:
-		"000000" & X"000", -- 0x2FD:
-		"000000" & X"000", -- 0x2FE:
-		"110000" & X"2FF", -- 0x2FF: JMP 0x2FF
-		"000000" & X"000", -- 0x300:
-		"000000" & X"000", -- 0x301:
-		"000000" & X"000", -- 0x302:
-		"000000" & X"000", -- 0x303:
-		"000000" & X"000", -- 0x304:
-		"000000" & X"000", -- 0x305:
-		"000000" & X"000", -- 0x306:
-		"000000" & X"000", -- 0x307:
-		"000000" & X"000", -- 0x308:
-		"000000" & X"000", -- 0x309:
-		"000000" & X"000", -- 0x30A:
-		"000000" & X"000", -- 0x30B:
-		"000000" & X"000", -- 0x30C:
-		"000000" & X"000", -- 0x30D:
-		"000000" & X"000", -- 0x30E:
-		"000000" & X"000", -- 0x30F:
-		"000000" & X"000", -- 0x310:
-		"000000" & X"000", -- 0x311:
-		"000000" & X"000", -- 0x312:
-		"000000" & X"000", -- 0x313:
-		"000000" & X"000", -- 0x314:
-		"000000" & X"000", -- 0x315:
-		"000000" & X"000", -- 0x316:
-		"000000" & X"000", -- 0x317:
-		"000000" & X"000", -- 0x318:
-		"000000" & X"000", -- 0x319:
-		"000000" & X"000", -- 0x31A:
-		"000000" & X"000", -- 0x31B:
-		"000000" & X"000", -- 0x31C:
-		"000000" & X"000", -- 0x31D:
-		"000000" & X"000", -- 0x31E:
-		"000000" & X"000", -- 0x31F:
-		"000000" & X"000", -- 0x320:
-		"000000" & X"000", -- 0x321:
-		"000000" & X"000", -- 0x322:
-		"000000" & X"000", -- 0x323:
-		"000000" & X"000", -- 0x324:
-		"000000" & X"000", -- 0x325:
-		"000000" & X"000", -- 0x326:
-		"000000" & X"000", -- 0x327:
-		"000000" & X"000", -- 0x328:
-		"000000" & X"000", -- 0x329:
-		"000000" & X"000", -- 0x32A:
-		"000000" & X"000", -- 0x32B:
-		"000000" & X"000", -- 0x32C:
-		"000000" & X"000", -- 0x32D:
-		"000000" & X"000", -- 0x32E:
-		"000000" & X"000", -- 0x32F:
-		"000000" & X"000", -- 0x330:
-		"000000" & X"000", -- 0x331:
-		"000000" & X"000", -- 0x332:
-		"000000" & X"000", -- 0x333:
-		"000000" & X"000", -- 0x334:
-		"000000" & X"000", -- 0x335:
-		"000000" & X"000", -- 0x336:
-		"000000" & X"000", -- 0x337:
-		"000000" & X"000", -- 0x338:
-		"000000" & X"000", -- 0x339:
-		"000000" & X"000", -- 0x33A:
-		"000000" & X"000", -- 0x33B:
-		"000000" & X"000", -- 0x33C:
-		"000000" & X"000", -- 0x33D:
-		"000000" & X"000", -- 0x33E:
-		"000000" & X"000", -- 0x33F:
-		"000000" & X"000", -- 0x340:
-		"000000" & X"000", -- 0x341:
-		"000000" & X"000", -- 0x342:
-		"000000" & X"000", -- 0x343:
-		"000000" & X"000", -- 0x344:
-		"000000" & X"000", -- 0x345:
-		"000000" & X"000", -- 0x346:
-		"000000" & X"000", -- 0x347:
-		"000000" & X"000", -- 0x348:
-		"000000" & X"000", -- 0x349:
-		"000000" & X"000", -- 0x34A:
-		"000000" & X"000", -- 0x34B:
-		"000000" & X"000", -- 0x34C:
-		"000000" & X"000", -- 0x34D:
-		"000000" & X"000", -- 0x34E:
-		"000000" & X"000", -- 0x34F:
-		"000000" & X"000", -- 0x350:
-		"000000" & X"000", -- 0x351:
-		"000000" & X"000", -- 0x352:
-		"000000" & X"000", -- 0x353:
-		"000000" & X"000", -- 0x354:
-		"000000" & X"000", -- 0x355:
-		"000000" & X"000", -- 0x356:
-		"000000" & X"000", -- 0x357:
-		"000000" & X"000", -- 0x358:
-		"000000" & X"000", -- 0x359:
-		"000000" & X"000", -- 0x35A:
-		"000000" & X"000", -- 0x35B:
-		"000000" & X"000", -- 0x35C:
-		"000000" & X"000", -- 0x35D:
-		"000000" & X"000", -- 0x35E:
-		"000000" & X"000", -- 0x35F:
-		"000000" & X"000", -- 0x360:
-		"000000" & X"000", -- 0x361:
-		"000000" & X"000", -- 0x362:
-		"000000" & X"000", -- 0x363:
-		"000000" & X"000", -- 0x364:
-		"000000" & X"000", -- 0x365:
-		"000000" & X"000", -- 0x366:
-		"000000" & X"000", -- 0x367:
-		"000000" & X"000", -- 0x368:
-		"000000" & X"000", -- 0x369:
-		"000000" & X"000", -- 0x36A:
-		"000000" & X"000", -- 0x36B:
-		"000000" & X"000", -- 0x36C:
-		"000000" & X"000", -- 0x36D:
-		"000000" & X"000", -- 0x36E:
-		"000000" & X"000", -- 0x36F:
-		"000000" & X"000", -- 0x370:
-		"000000" & X"000", -- 0x371:
-		"000000" & X"000", -- 0x372:
-		"000000" & X"000", -- 0x373:
-		"000000" & X"000", -- 0x374:
-		"000000" & X"000", -- 0x375:
-		"000000" & X"000", -- 0x376:
-		"000000" & X"000", -- 0x377:
-		"000000" & X"000", -- 0x378:
-		"000000" & X"000", -- 0x379:
-		"000000" & X"000", -- 0x37A:
-		"000000" & X"000", -- 0x37B:
-		"000000" & X"000", -- 0x37C:
-		"000000" & X"000", -- 0x37D:
-		"000000" & X"000", -- 0x37E:
-		"000000" & X"000", -- 0x37F:
-		"000000" & X"000", -- 0x380:
-		"000000" & X"000", -- 0x381:
-		"000000" & X"000", -- 0x382:
-		"000000" & X"000", -- 0x383:
-		"000000" & X"000", -- 0x384:
-		"000000" & X"000", -- 0x385:
-		"000000" & X"000", -- 0x386:
-		"000000" & X"000", -- 0x387:
-		"000000" & X"000", -- 0x388:
-		"000000" & X"000", -- 0x389:
-		"000000" & X"000", -- 0x38A:
-		"000000" & X"000", -- 0x38B:
-		"000000" & X"000", -- 0x38C:
-		"000000" & X"000", -- 0x38D:
-		"000000" & X"000", -- 0x38E:
-		"000000" & X"000", -- 0x38F:
-		"000000" & X"000", -- 0x390:
-		"000000" & X"000", -- 0x391:
-		"000000" & X"000", -- 0x392:
-		"000000" & X"000", -- 0x393:
-		"000000" & X"000", -- 0x394:
-		"000000" & X"000", -- 0x395:
-		"000000" & X"000", -- 0x396:
-		"000000" & X"000", -- 0x397:
-		"000000" & X"000", -- 0x398:
-		"000000" & X"000", -- 0x399:
-		"000000" & X"000", -- 0x39A:
-		"000000" & X"000", -- 0x39B:
-		"000000" & X"000", -- 0x39C:
-		"000000" & X"000", -- 0x39D:
-		"000000" & X"000", -- 0x39E:
-		"000000" & X"000", -- 0x39F:
-		"000000" & X"000", -- 0x3A0:
-		"000000" & X"000", -- 0x3A1:
-		"000000" & X"000", -- 0x3A2:
-		"000000" & X"000", -- 0x3A3:
-		"000000" & X"000", -- 0x3A4:
-		"000000" & X"000", -- 0x3A5:
-		"000000" & X"000", -- 0x3A6:
-		"000000" & X"000", -- 0x3A7:
-		"000000" & X"000", -- 0x3A8:
-		"000000" & X"000", -- 0x3A9:
-		"000000" & X"000", -- 0x3AA:
-		"000000" & X"000", -- 0x3AB:
-		"000000" & X"000", -- 0x3AC:
-		"000000" & X"000", -- 0x3AD:
-		"000000" & X"000", -- 0x3AE:
-		"000000" & X"000", -- 0x3AF:
-		"000000" & X"000", -- 0x3B0:
-		"000000" & X"000", -- 0x3B1:
-		"000000" & X"000", -- 0x3B2:
-		"000000" & X"000", -- 0x3B3:
-		"000000" & X"000", -- 0x3B4:
-		"000000" & X"000", -- 0x3B5:
-		"000000" & X"000", -- 0x3B6:
-		"000000" & X"000", -- 0x3B7:
-		"000000" & X"000", -- 0x3B8:
-		"000000" & X"000", -- 0x3B9:
-		"000000" & X"000", -- 0x3BA:
-		"000000" & X"000", -- 0x3BB:
-		"000000" & X"000", -- 0x3BC:
-		"000000" & X"000", -- 0x3BD:
-		"000000" & X"000", -- 0x3BE:
-		"000000" & X"000", -- 0x3BF:
-		"000000" & X"000", -- 0x3C0:
-		"000000" & X"000", -- 0x3C1:
-		"000000" & X"000", -- 0x3C2:
-		"000000" & X"000", -- 0x3C3:
-		"000000" & X"000", -- 0x3C4:
-		"000000" & X"000", -- 0x3C5:
-		"000000" & X"000", -- 0x3C6:
-		"000000" & X"000", -- 0x3C7:
-		"000000" & X"000", -- 0x3C8:
-		"000000" & X"000", -- 0x3C9:
-		"000000" & X"000", -- 0x3CA:
-		"000000" & X"000", -- 0x3CB:
-		"000000" & X"000", -- 0x3CC:
-		"000000" & X"000", -- 0x3CD:
-		"000000" & X"000", -- 0x3CE:
-		"000000" & X"000", -- 0x3CF:
-		"000000" & X"000", -- 0x3D0:
-		"000000" & X"000", -- 0x3D1:
-		"000000" & X"000", -- 0x3D2:
-		"000000" & X"000", -- 0x3D3:
-		"000000" & X"000", -- 0x3D4:
-		"000000" & X"000", -- 0x3D5:
-		"000000" & X"000", -- 0x3D6:
-		"000000" & X"000", -- 0x3D7:
-		"000000" & X"000", -- 0x3D8:
-		"000000" & X"000", -- 0x3D9:
-		"000000" & X"000", -- 0x3DA:
-		"000000" & X"000", -- 0x3DB:
-		"000000" & X"000", -- 0x3DC:
-		"000000" & X"000", -- 0x3DD:
-		"000000" & X"000", -- 0x3DE:
-		"000000" & X"000", -- 0x3DF:
-		"000000" & X"000", -- 0x3E0:
-		"000000" & X"000", -- 0x3E1:
-		"000000" & X"000", -- 0x3E2:
-		"000000" & X"000", -- 0x3E3:
-		"000000" & X"000", -- 0x3E4:
-		"000000" & X"000", -- 0x3E5:
-		"000000" & X"000", -- 0x3E6:
-		"000000" & X"000", -- 0x3E7:
-		"000000" & X"000", -- 0x3E8:
-		"000000" & X"000", -- 0x3E9:
-		"000000" & X"000", -- 0x3EA:
-		"000000" & X"000", -- 0x3EB:
-		"000000" & X"000", -- 0x3EC:
-		"000000" & X"000", -- 0x3ED:
-		"000000" & X"000", -- 0x3EE:
-		"000000" & X"000", -- 0x3EF:
-		"000000" & X"000", -- 0x3F0:
-		"000000" & X"000", -- 0x3F1:
-		"000000" & X"000", -- 0x3F2:
-		"000000" & X"000", -- 0x3F3:
-		"000000" & X"000", -- 0x3F4:
-		"000000" & X"000", -- 0x3F5:
-		"000000" & X"000", -- 0x3F6:
-		"000000" & X"000", -- 0x3F7:
-		"000000" & X"000", -- 0x3F8:
-		"000000" & X"000", -- 0x3F9:
-		"000000" & X"000", -- 0x3FA:
-		"000000" & X"000", -- 0x3FB:
-		"000000" & X"000", -- 0x3FC:
-		"000000" & X"000", -- 0x3FD:
-		"000000" & X"000", -- 0x3FE:
-		"110000" & X"3FF"  -- 0x3FF: JMP 0x3FF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/itest_xrom.vhdl b/lib/CPUs/JCpu/src/itest_xrom.vhdl
deleted file mode 100644
index 4206abc..0000000
--- a/lib/CPUs/JCpu/src/itest_xrom.vhdl
+++ /dev/null
@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE itest OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from itest.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"48", -- 0x00
-		X"61", -- 0x01
-		X"6C", -- 0x02
-		X"6C", -- 0x03
-		X"6F", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end itest;
-
diff --git a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl
deleted file mode 100644
index 60a84ac..0000000
--- a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl
+++ /dev/null
@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from itest.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"48", -- 0x00
-		X"61", -- 0x01
-		X"6C", -- 0x02
-		X"6C", -- 0x03
-		X"6F", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl
deleted file mode 100644
index 3b0de3b..0000000
--- a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE mul8x8 OF irom IS 
-
-	type imem_rom_t is array (0 to 26) of inst_t;
-
-	-- Assembled from mul8x8.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"001", -- 0x000: JMP 0x001
-		"000011" & X"450", -- 0x001: MOV R00, 0x45
-		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
-		"111011" & X"005", -- 0x003: CALL 0x005
-		"110000" & X"004", -- 0x004: JMP 0x004
-		"111100" & X"002", -- 0x005: PUSH R02
-		"111100" & X"003", -- 0x006: PUSH R03
-		"111100" & X"004", -- 0x007: PUSH R04
-		"000010" & X"014", -- 0x008: MOV R04, R01
-		"000011" & X"001", -- 0x009: MOV R01, 0x00
-		"000011" & X"002", -- 0x00A: MOV R02, 0x00
-		"000011" & X"003", -- 0x00B: MOV R03, 0x00
-		"001111" & X"014", -- 0x00C: CMP R04, 0x01
-		"111001" & X"015", -- 0x00D: JEQ 0x015
-		"011111" & X"004", -- 0x00E: SHR R04
-		"110100" & X"012", -- 0x00F: JNC 0x012
-		"010000" & X"002", -- 0x010: ADD R02, R00
-		"010010" & X"013", -- 0x011: ADDC R03, R01
-		"011110" & X"000", -- 0x012: SHL R00
-		"100010" & X"001", -- 0x013: ROLC R01
-		"110000" & X"00C", -- 0x014: JMP 0x00C
-		"010000" & X"020", -- 0x015: ADD R00, R02
-		"010010" & X"031", -- 0x016: ADDC R01, R03
-		"111101" & X"004", -- 0x017: POP R04
-		"111101" & X"003", -- 0x018: POP R03
-		"111101" & X"002", -- 0x019: POP R02
-		"111110" & X"000"  -- 0x01A: RET
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end mul8x8;
-
diff --git a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl
deleted file mode 100644
index 4303d08..0000000
--- a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl
+++ /dev/null
@@ -1,1181 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from mul8x8.jsm
-	type imem_rom_t is array (0 to 1023) of inst_t;
-	signal imem_rom : imem_rom_t :=
-	(
-		"110000" & X"001", -- 0x000: JMP 0x001
-		"000011" & X"450", -- 0x001: MOV R00, 0x45
-		"000011" & X"F51", -- 0x002: MOV R01, 0xF5
-		"111011" & X"005", -- 0x003: CALL 0x005
-		"110000" & X"004", -- 0x004: JMP 0x004
-		"111100" & X"002", -- 0x005: PUSH R02
-		"111100" & X"003", -- 0x006: PUSH R03
-		"111100" & X"004", -- 0x007: PUSH R04
-		"000010" & X"014", -- 0x008: MOV R04, R01
-		"000011" & X"001", -- 0x009: MOV R01, 0x00
-		"000011" & X"002", -- 0x00A: MOV R02, 0x00
-		"000011" & X"003", -- 0x00B: MOV R03, 0x00
-		"001111" & X"014", -- 0x00C: CMP R04, 0x01
-		"111001" & X"015", -- 0x00D: JEQ 0x015
-		"011111" & X"004", -- 0x00E: SHR R04
-		"110100" & X"012", -- 0x00F: JNC 0x012
-		"010000" & X"002", -- 0x010: ADD R02, R00
-		"010010" & X"013", -- 0x011: ADDC R03, R01
-		"011110" & X"000", -- 0x012: SHL R00
-		"100010" & X"001", -- 0x013: ROLC R01
-		"110000" & X"00C", -- 0x014: JMP 0x00C
-		"010000" & X"020", -- 0x015: ADD R00, R02
-		"010010" & X"031", -- 0x016: ADDC R01, R03
-		"111101" & X"004", -- 0x017: POP R04
-		"111101" & X"003", -- 0x018: POP R03
-		"111101" & X"002", -- 0x019: POP R02
-		"111110" & X"000", -- 0x01A: RET
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
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-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000"
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl
deleted file mode 100644
index 508e8cf..0000000
--- a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl
+++ /dev/null
@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE mul8x8 OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from mul8x8.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end mul8x8;
-
diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl
deleted file mode 100644
index a75d090..0000000
--- a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl
+++ /dev/null
@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from mul8x8.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl
deleted file mode 100644
index 9355a7d..0000000
--- a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl
+++ /dev/null
@@ -1,89 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY irom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  inst_addr_t;
-	dout		: out inst_t
-	);
-END irom;
-
-ARCHITECTURE reti_issue OF irom IS 
-
-	type imem_rom_t is array (0 to 27) of inst_t;
-
-	-- Assembled from reti_issue.jsm
-	constant imem_rom : imem_rom_t :=
-	(
-		"110000" & X"002", -- 0x000: JMP 0x002
-		"111111" & X"000", -- 0x001: RETI
-		"000011" & X"050", -- 0x002: MOV R00, 0x05
-		"100110" & X"030", -- 0x003: COUT (0x03), R00
-		"000011" & X"000", -- 0x004: MOV R00, 0x00
-		"000000" & X"000", -- 0x005: NOP
-		"010001" & X"010", -- 0x006: INC R00
-		"000000" & X"000", -- 0x007: NOP
-		"111011" & X"01B", -- 0x008: CALL 0x01B
-		"000000" & X"000", -- 0x009: NOP
-		"111100" & X"003", -- 0x00A: PUSH R03
-		"000000" & X"000", -- 0x00B: NOP
-		"111100" & X"002", -- 0x00C: PUSH R02
-		"000000" & X"000", -- 0x00D: NOP
-		"111100" & X"001", -- 0x00E: PUSH R01
-		"000000" & X"000", -- 0x00F: NOP
-		"111100" & X"000", -- 0x010: PUSH R00
-		"000000" & X"000", -- 0x011: NOP
-		"111101" & X"000", -- 0x012: POP R00
-		"000000" & X"000", -- 0x013: NOP
-		"111101" & X"001", -- 0x014: POP R01
-		"000000" & X"000", -- 0x015: NOP
-		"111101" & X"002", -- 0x016: POP R02
-		"000000" & X"000", -- 0x017: NOP
-		"111101" & X"003", -- 0x018: POP R03
-		"000000" & X"000", -- 0x019: NOP
-		"110000" & X"005", -- 0x01A: JMP 0x005
-		"111110" & X"000"  -- 0x01B: RET
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end reti_issue;
-
diff --git a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl
deleted file mode 100644
index d1b4bd1..0000000
--- a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl
+++ /dev/null
@@ -1,1181 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from reti_issue.jsm
-	type imem_rom_t is array (0 to 1023) of inst_t;
-	signal imem_rom : imem_rom_t :=
-	(
-		"110000" & X"002", -- 0x000: JMP 0x002
-		"111111" & X"000", -- 0x001: RETI
-		"000011" & X"050", -- 0x002: MOV R00, 0x05
-		"100110" & X"030", -- 0x003: COUT (0x03), R00
-		"000011" & X"000", -- 0x004: MOV R00, 0x00
-		"000000" & X"000", -- 0x005: NOP
-		"010001" & X"010", -- 0x006: INC R00
-		"000000" & X"000", -- 0x007: NOP
-		"111011" & X"01B", -- 0x008: CALL 0x01B
-		"000000" & X"000", -- 0x009: NOP
-		"111100" & X"003", -- 0x00A: PUSH R03
-		"000000" & X"000", -- 0x00B: NOP
-		"111100" & X"002", -- 0x00C: PUSH R02
-		"000000" & X"000", -- 0x00D: NOP
-		"111100" & X"001", -- 0x00E: PUSH R01
-		"000000" & X"000", -- 0x00F: NOP
-		"111100" & X"000", -- 0x010: PUSH R00
-		"000000" & X"000", -- 0x011: NOP
-		"111101" & X"000", -- 0x012: POP R00
-		"000000" & X"000", -- 0x013: NOP
-		"111101" & X"001", -- 0x014: POP R01
-		"000000" & X"000", -- 0x015: NOP
-		"111101" & X"002", -- 0x016: POP R02
-		"000000" & X"000", -- 0x017: NOP
-		"111101" & X"003", -- 0x018: POP R03
-		"000000" & X"000", -- 0x019: NOP
-		"110000" & X"005", -- 0x01A: JMP 0x005
-		"111110" & X"000", -- 0x01B: RET
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000",
-		"000000" & X"000"
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl
deleted file mode 100644
index a7a33f9..0000000
--- a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl
+++ /dev/null
@@ -1,317 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-ENTITY xrom IS
-	Port (
-	clk			: in  STD_LOGIC;
-	ce			: in  STD_LOGIC;
-	addr		: in  dmem_addr_t;
-	dout		: out dmem_data_t
-	);
-END xrom;
-
-ARCHITECTURE reti_issue OF xrom IS 
-
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-
-	-- Assembled from reti_issue.jsm
-	constant xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-begin
-
-PROM_READ:
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-end reti_issue;
-
diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl
deleted file mode 100644
index 244c1b5..0000000
--- a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl
+++ /dev/null
@@ -1,413 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	-- Assembled from reti_issue.jsm
-	type xmem_rom_t is array (0 to 255) of dmem_data_t;
-	signal xmem_rom : xmem_rom_t :=
-	(
-		X"00", -- 0x00
-		X"00", -- 0x01
-		X"00", -- 0x02
-		X"00", -- 0x03
-		X"00", -- 0x04
-		X"00", -- 0x05
-		X"00", -- 0x06
-		X"00", -- 0x07
-		X"00", -- 0x08
-		X"00", -- 0x09
-		X"00", -- 0x0A
-		X"00", -- 0x0B
-		X"00", -- 0x0C
-		X"00", -- 0x0D
-		X"00", -- 0x0E
-		X"00", -- 0x0F
-		X"00", -- 0x10
-		X"00", -- 0x11
-		X"00", -- 0x12
-		X"00", -- 0x13
-		X"00", -- 0x14
-		X"00", -- 0x15
-		X"00", -- 0x16
-		X"00", -- 0x17
-		X"00", -- 0x18
-		X"00", -- 0x19
-		X"00", -- 0x1A
-		X"00", -- 0x1B
-		X"00", -- 0x1C
-		X"00", -- 0x1D
-		X"00", -- 0x1E
-		X"00", -- 0x1F
-		X"00", -- 0x20
-		X"00", -- 0x21
-		X"00", -- 0x22
-		X"00", -- 0x23
-		X"00", -- 0x24
-		X"00", -- 0x25
-		X"00", -- 0x26
-		X"00", -- 0x27
-		X"00", -- 0x28
-		X"00", -- 0x29
-		X"00", -- 0x2A
-		X"00", -- 0x2B
-		X"00", -- 0x2C
-		X"00", -- 0x2D
-		X"00", -- 0x2E
-		X"00", -- 0x2F
-		X"00", -- 0x30
-		X"00", -- 0x31
-		X"00", -- 0x32
-		X"00", -- 0x33
-		X"00", -- 0x34
-		X"00", -- 0x35
-		X"00", -- 0x36
-		X"00", -- 0x37
-		X"00", -- 0x38
-		X"00", -- 0x39
-		X"00", -- 0x3A
-		X"00", -- 0x3B
-		X"00", -- 0x3C
-		X"00", -- 0x3D
-		X"00", -- 0x3E
-		X"00", -- 0x3F
-		X"00", -- 0x40
-		X"00", -- 0x41
-		X"00", -- 0x42
-		X"00", -- 0x43
-		X"00", -- 0x44
-		X"00", -- 0x45
-		X"00", -- 0x46
-		X"00", -- 0x47
-		X"00", -- 0x48
-		X"00", -- 0x49
-		X"00", -- 0x4A
-		X"00", -- 0x4B
-		X"00", -- 0x4C
-		X"00", -- 0x4D
-		X"00", -- 0x4E
-		X"00", -- 0x4F
-		X"00", -- 0x50
-		X"00", -- 0x51
-		X"00", -- 0x52
-		X"00", -- 0x53
-		X"00", -- 0x54
-		X"00", -- 0x55
-		X"00", -- 0x56
-		X"00", -- 0x57
-		X"00", -- 0x58
-		X"00", -- 0x59
-		X"00", -- 0x5A
-		X"00", -- 0x5B
-		X"00", -- 0x5C
-		X"00", -- 0x5D
-		X"00", -- 0x5E
-		X"00", -- 0x5F
-		X"00", -- 0x60
-		X"00", -- 0x61
-		X"00", -- 0x62
-		X"00", -- 0x63
-		X"00", -- 0x64
-		X"00", -- 0x65
-		X"00", -- 0x66
-		X"00", -- 0x67
-		X"00", -- 0x68
-		X"00", -- 0x69
-		X"00", -- 0x6A
-		X"00", -- 0x6B
-		X"00", -- 0x6C
-		X"00", -- 0x6D
-		X"00", -- 0x6E
-		X"00", -- 0x6F
-		X"00", -- 0x70
-		X"00", -- 0x71
-		X"00", -- 0x72
-		X"00", -- 0x73
-		X"00", -- 0x74
-		X"00", -- 0x75
-		X"00", -- 0x76
-		X"00", -- 0x77
-		X"00", -- 0x78
-		X"00", -- 0x79
-		X"00", -- 0x7A
-		X"00", -- 0x7B
-		X"00", -- 0x7C
-		X"00", -- 0x7D
-		X"00", -- 0x7E
-		X"00", -- 0x7F
-		X"00", -- 0x80
-		X"00", -- 0x81
-		X"00", -- 0x82
-		X"00", -- 0x83
-		X"00", -- 0x84
-		X"00", -- 0x85
-		X"00", -- 0x86
-		X"00", -- 0x87
-		X"00", -- 0x88
-		X"00", -- 0x89
-		X"00", -- 0x8A
-		X"00", -- 0x8B
-		X"00", -- 0x8C
-		X"00", -- 0x8D
-		X"00", -- 0x8E
-		X"00", -- 0x8F
-		X"00", -- 0x90
-		X"00", -- 0x91
-		X"00", -- 0x92
-		X"00", -- 0x93
-		X"00", -- 0x94
-		X"00", -- 0x95
-		X"00", -- 0x96
-		X"00", -- 0x97
-		X"00", -- 0x98
-		X"00", -- 0x99
-		X"00", -- 0x9A
-		X"00", -- 0x9B
-		X"00", -- 0x9C
-		X"00", -- 0x9D
-		X"00", -- 0x9E
-		X"00", -- 0x9F
-		X"00", -- 0xA0
-		X"00", -- 0xA1
-		X"00", -- 0xA2
-		X"00", -- 0xA3
-		X"00", -- 0xA4
-		X"00", -- 0xA5
-		X"00", -- 0xA6
-		X"00", -- 0xA7
-		X"00", -- 0xA8
-		X"00", -- 0xA9
-		X"00", -- 0xAA
-		X"00", -- 0xAB
-		X"00", -- 0xAC
-		X"00", -- 0xAD
-		X"00", -- 0xAE
-		X"00", -- 0xAF
-		X"00", -- 0xB0
-		X"00", -- 0xB1
-		X"00", -- 0xB2
-		X"00", -- 0xB3
-		X"00", -- 0xB4
-		X"00", -- 0xB5
-		X"00", -- 0xB6
-		X"00", -- 0xB7
-		X"00", -- 0xB8
-		X"00", -- 0xB9
-		X"00", -- 0xBA
-		X"00", -- 0xBB
-		X"00", -- 0xBC
-		X"00", -- 0xBD
-		X"00", -- 0xBE
-		X"00", -- 0xBF
-		X"00", -- 0xC0
-		X"00", -- 0xC1
-		X"00", -- 0xC2
-		X"00", -- 0xC3
-		X"00", -- 0xC4
-		X"00", -- 0xC5
-		X"00", -- 0xC6
-		X"00", -- 0xC7
-		X"00", -- 0xC8
-		X"00", -- 0xC9
-		X"00", -- 0xCA
-		X"00", -- 0xCB
-		X"00", -- 0xCC
-		X"00", -- 0xCD
-		X"00", -- 0xCE
-		X"00", -- 0xCF
-		X"00", -- 0xD0
-		X"00", -- 0xD1
-		X"00", -- 0xD2
-		X"00", -- 0xD3
-		X"00", -- 0xD4
-		X"00", -- 0xD5
-		X"00", -- 0xD6
-		X"00", -- 0xD7
-		X"00", -- 0xD8
-		X"00", -- 0xD9
-		X"00", -- 0xDA
-		X"00", -- 0xDB
-		X"00", -- 0xDC
-		X"00", -- 0xDD
-		X"00", -- 0xDE
-		X"00", -- 0xDF
-		X"00", -- 0xE0
-		X"00", -- 0xE1
-		X"00", -- 0xE2
-		X"00", -- 0xE3
-		X"00", -- 0xE4
-		X"00", -- 0xE5
-		X"00", -- 0xE6
-		X"00", -- 0xE7
-		X"00", -- 0xE8
-		X"00", -- 0xE9
-		X"00", -- 0xEA
-		X"00", -- 0xEB
-		X"00", -- 0xEC
-		X"00", -- 0xED
-		X"00", -- 0xEE
-		X"00", -- 0xEF
-		X"00", -- 0xF0
-		X"00", -- 0xF1
-		X"00", -- 0xF2
-		X"00", -- 0xF3
-		X"00", -- 0xF4
-		X"00", -- 0xF5
-		X"00", -- 0xF6
-		X"00", -- 0xF7
-		X"00", -- 0xF8
-		X"00", -- 0xF9
-		X"00", -- 0xFA
-		X"00", -- 0xFB
-		X"00", -- 0xFC
-		X"00", -- 0xFD
-		X"00", -- 0xFE
-		X"00"  -- 0xFF
-	);
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd
deleted file mode 100644
index dafb553..0000000
--- a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for embedded cpu with rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY tb_cpu_embedded IS
-END tb_cpu_embedded;
-
-ARCHITECTURE behavior OF tb_cpu_embedded IS 
-
-	COMPONENT cpu_embedded
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out  STD_LOGIC;
-		xmem_we		: out STD_LOGIC;
-		xmem_re		: out STD_LOGIC;
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
-		io_sel		: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	type sram_t is array (integer range <>) of dmem_data_t;
-	signal rst : std_logic := '1';
-	signal clk : std_logic := '1';
-	signal ce  : std_logic := '0';
-	signal int_in : std_logic := '0';
-	signal int_ack : std_logic;
-	signal xmem_din : dmem_data_t := (others => '-');
-	signal xmem_dout : dmem_data_t;
-	signal xmem_addr : dmem_addr_t;
-	signal xmem_we : std_logic;
-	signal xmem_re : std_logic;
-	signal io_sel : std_logic;
-	signal sram : sram_t(0 to 2**dmem_addr_t'length-1);
-	
-
-BEGIN
-
-uut: cpu_embedded
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-	
-		wait for 1000*CLK_PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we)
-	begin
-		if (rst = '1') then
-			xmem_din <= X"00";
-		elsif rising_edge(clk) then
-			if io_sel = '0' then
-				if xmem_we = '1' then	
-					sram(to_integer(xmem_addr)) <= xmem_dout;
-				end if;	
-				xmem_din <= to_01(sram(to_integer(xmem_addr)));
-			else
-				xmem_din <= X"FF";
-			end if;	
-		end if;
-	end process;
-	
-END;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_irq.vhd b/lib/CPUs/JCpu/src/tb_cpu_irq.vhd
deleted file mode 100644
index 8a19414..0000000
--- a/lib/CPUs/JCpu/src/tb_cpu_irq.vhd
+++ /dev/null
@@ -1,205 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Formal test of correct function of JCPU,
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.cpu_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cpu IS
-END tb_cpu;
-
-ARCHITECTURE behavior OF tb_cpu IS 
-
-	COMPONENT cpu
-	Generic (
-		use_instr_register	: boolean;
-		use_ctrl_rom		: boolean
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out  STD_LOGIC;
-		xmem_we		: out  STD_LOGIC;
-		xmem_re		: out  STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		io_sel		: out  STD_LOGIC
-		
-	);
-	END COMPONENT;
-
-	COMPONENT irom
-		Port (
-			clk			: in  STD_LOGIC;
-			ce			: in  STD_LOGIC;
-			addr		: in  inst_addr_t;
-			dout		: out inst_t
-		);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	type prom_t is array (integer range <>) of inst_t;
-	type sram_t is array (integer range <>) of dmem_data_t;
-	signal rst : std_logic := '1';
-	signal clk : std_logic := '1';
-	signal ce  : std_logic := '0';
-	signal int_in : std_logic := '0';
-	signal int_ack : std_logic;
-	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
-	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	signal xmem_din : dmem_data_t := (others => '-');
-	signal xmem_dout : dmem_data_t;
-	signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	signal xmem_we : std_logic;
-	signal xmem_re : std_logic;
-	signal io_sel : std_logic;
-	signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
-	
-	type reg_t is record
-		revision : dmem_data_t;
-		testid : dmem_data_t;
-		interrupt : std_logic;
-	end record;	
-	
-	signal reg : reg_t;
-	
-
-BEGIN
-
-uut: cpu
-	GENERIC MAP
-	(	
-		use_instr_register	=> false,
-		use_ctrl_rom		=> true
-	)
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		instr_din => irom_data,
-		instr_addr => irom_addr,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-the_irom: irom
-	PORT MAP(
-		clk			=> clk,
-		ce			=> ce,
-		addr		=> irom_addr,
-		dout 		=> irom_data
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-	file RESULT:        text open write_mode is "../tools/opc.list"; 
-	variable L:         line;
-
-	begin
-
-		for i in 0 to instr_name_array'length-1 loop
-			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
-		end loop;	
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-	
-		wait for 1000*CLK_PERIOD;
-		
-		for i in 1 to 100 loop
-			wait until rising_edge(clk);
-			int_in	<= '1';
-			wait until rising_edge(clk) and int_ack = '1';
-			int_in	<= '0';
-			wait for 300*CLK_PERIOD;
-		end loop;		
-		
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-SRAM_RW: process(rst, clk)
-	begin
-		if (rst = '1') then
-			reg.revision <= (others => '0');
-			reg.testid <= (others => '0');
-		elsif rising_edge(clk) then
-			if xmem_we = '1' then	
-				if io_sel = '0' then
-					sram(to_integer(xmem_addr)) <= xmem_dout;
-				else	
-					case xmem_addr is
-						when X"00" =>
-							reg.revision <= xmem_dout;
-						when X"01" =>
-							reg.testid <= xmem_dout;
-						when X"02" =>
-							reg.interrupt <= xmem_dout(0);
-						when others => null;
-					end case;
-				end if;	
-			else
-				if io_sel = '0' then
-					xmem_din <= to_01(sram(to_integer(xmem_addr)));
-				else
-					case xmem_addr is
-						when X"00" =>
-							xmem_din <= reg.revision;
-						when X"01" =>
-							xmem_din <= reg.testid;
-						when others =>
-							xmem_din <= X"BC";
-					end case;
-				end if;				
-			end if;	
-		end if;
-	end process;
-	
-END;
diff --git a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd
deleted file mode 100644
index 243ba8f..0000000
--- a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd
+++ /dev/null
@@ -1,200 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Formal test of correct function of JCPU,
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.cpu_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cpu IS
-END tb_cpu;
-
-ARCHITECTURE behavior OF tb_cpu IS 
-
-	COMPONENT cpu
-	Generic (
-		use_instr_register	: boolean;
-		use_ctrl_rom		: boolean
-	);
-	Port (
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		int_in		: in  STD_LOGIC;
-		int_ack		: out  STD_LOGIC;
-		xmem_we		: out  STD_LOGIC;
-		xmem_re		: out  STD_LOGIC;
-		instr_din	: in  unsigned (IMEM_DATA_WIDTH-1 downto 0);
-		instr_addr	: out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-		xmem_din	: in  unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_dout	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		xmem_addr	: out unsigned (DMEM_DATA_WIDTH-1 downto 0);
-		io_sel		: out  STD_LOGIC
-		
-	);
-	END COMPONENT;
-
-	COMPONENT irom
-		Port (
-			clk			: in  STD_LOGIC;
-			ce			: in  STD_LOGIC;
-			addr		: in  inst_addr_t;
-			dout		: out inst_t
-		);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	type prom_t is array (integer range <>) of inst_t;
-	type sram_t is array (integer range <>) of dmem_data_t;
-	signal rst : std_logic := '1';
-	signal clk : std_logic := '1';
-	signal ce  : std_logic := '0';
-	signal int_in : std_logic := '0';
-	signal int_ack : std_logic;
-	signal irom_data	: unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-');
-	signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
-	signal xmem_din : dmem_data_t := (others => '-');
-	signal xmem_dout : dmem_data_t;
-	signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0);
-	signal xmem_we : std_logic;
-	signal xmem_re : std_logic;
-	signal io_sel : std_logic;
-	signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1);
-	
-	type reg_t is record
-		revision : dmem_data_t;
-		testid : dmem_data_t;
-		interrupt : std_logic;
-	end record;	
-	
-	signal reg : reg_t;
-	
-
-BEGIN
-
-	int_in <= reg.interrupt;
-uut: cpu
-	GENERIC MAP
-	(	
-		use_instr_register	=> false,
-		use_ctrl_rom		=> true
-	)
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		int_in => int_in,
-		int_ack => int_ack,
-		xmem_we => xmem_we,
-		xmem_re => xmem_re,
-		instr_din => irom_data,
-		instr_addr => irom_addr,
-		xmem_din => xmem_din,
-		xmem_dout => xmem_dout,
-		xmem_addr => xmem_addr,
-		io_sel => io_sel
-	);
-
-the_irom: irom
-	PORT MAP(
-		clk			=> clk,
-		ce			=> ce,
-		addr		=> irom_addr,
-		dout 		=> irom_data
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-STIMULUS: process
-	file RESULT:        text open write_mode is "../tools/opc.list"; 
-	variable L:         line;
-
-	begin
-
-		for i in 0 to instr_name_array'length-1 loop
-			fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i));
-		end loop;	
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		wait until rising_edge(clk);
-		ce <= '1';
-	
-		assert false report "Test finished" severity error;
-		wait; 
-	
-	end process;
-
-SRAM_RW: process(rst, clk)
-	begin
-		if (rst = '1') then
-			reg.revision <= (others => '0');
-			reg.testid <= (others => '0');
-			reg.interrupt <= '0';
-		elsif rising_edge(clk) then
-			if int_ack = '1' then
---				reg.interrupt <= '0';
-			end if;	
-			if xmem_we = '1' then	
-				if io_sel = '0' then
-					sram(to_integer(xmem_addr)) <= xmem_dout;
-				else	
-					case xmem_addr is
-						when X"00" =>
-							reg.revision <= xmem_dout;
-						when X"01" =>
-							reg.testid <= xmem_dout;
-						when X"02" =>
-							reg.interrupt <= xmem_dout(0);
-						when others => null;
-					end case;
-				end if;	
-			else
-				if io_sel = '0' then
-					xmem_din <= to_01(sram(to_integer(xmem_addr)));
-				else
-					case xmem_addr is
-						when X"00" =>
-							xmem_din <= reg.revision;
-						when X"01" =>
-							xmem_din <= reg.testid;
-						when others =>
-							xmem_din <= X"BC";
-					end case;
-				end if;				
-			end if;	
-		end if;
-	end process;
-	
-END;
diff --git a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj
deleted file mode 100644
index 18718bf..0000000
--- a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj
+++ /dev/null
@@ -1,10 +0,0 @@
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd"
diff --git a/lib/CPUs/JCpu/tools/eval_scan.rb b/lib/CPUs/JCpu/tools/eval_scan.rb
deleted file mode 100644
index 0c38397..0000000
--- a/lib/CPUs/JCpu/tools/eval_scan.rb
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/env ruby
-
-str1 = %Q!lbl:		dc		"Hallo", ", ", 0, 1, " der","Jens"!
-
-i=0;
-
-def get_stri_lit (str)
-	res = [""];
-	state = "out"
-	
-	j = 0;
-	k = 0;
-	for i in (0..str.length-1)
-		c = str[i];
-		nstate = state
-		case state 
-		when "out"
-			if c == "\""[0]
-				nstate = "in"
-			end
-		when "in"	
-			if c == "\""[0]
-				nstate = "out"
-				if j > 0
-					k = k + 1;
-					res[k] = ""
-				end	
-			else
-				res[k] = res[k] + format("%c", c);
-				j = j + 1;
-			end
-		end
-		state = nstate
-	end;
-	return res
-end		
-	
-get_stri_lit(str1).each do |word|
-	puts word
-end	
- 	
- 
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/tools/insrom.rb b/lib/CPUs/JCpu/tools/insrom.rb
deleted file mode 100644
index 6713f9f..0000000
--- a/lib/CPUs/JCpu/tools/insrom.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: Insertion of code fragments into templates
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-rom_filename = arg[0].to_s
-tpl_filename = arg[1].to_s
-
-subst_pattern = "JASM_ROM_INSERT_HERE"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-romfile = File.open(rom_filename, "r")
-tplfile = File.open(tpl_filename, "r")
-re = Regexp.new(subst_pattern)
-
-while (line = tplfile.gets)
-	puts line
-	line.scan(re).each do |word|
-		romfile.each do |raw_line|
-			puts raw_line
-		end	
-	end
-end
diff --git a/lib/CPUs/JCpu/tools/irom.vhd.tpl b/lib/CPUs/JCpu/tools/irom.vhd.tpl
deleted file mode 100644
index 5f11f86..0000000
--- a/lib/CPUs/JCpu/tools/irom.vhd.tpl
+++ /dev/null
@@ -1,32 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-
diff --git a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl
deleted file mode 100644
index eaa41f3..0000000
--- a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl
+++ /dev/null
@@ -1,151 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: inst_addr_t;
-	signal jtag_ld_dout		: inst_t;
-	signal jtag_ld_din		: inst_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (31 downto 0);
-	constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1);
-	jtag_ld_din <= user_regi(inst_t'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/JCpu/tools/jasm.bak.rb b/lib/CPUs/JCpu/tools/jasm.bak.rb
deleted file mode 100644
index 4c9feb0..0000000
--- a/lib/CPUs/JCpu/tools/jasm.bak.rb
+++ /dev/null
@@ -1,494 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: A small assembler for the JCPU
-
-# Copyright (C) 2007 J. Ahrensfeld
-
-# This library is free software; you can redistribute it and/or
-# modify it under the terms of the GNU Lesser General Public
-# License as published by the Free Software Foundation; either
-# version 2.1 of the License, or (at your option) any later version.
-
-# This library is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-# Lesser General Public License for more details.
-
-# You should have received a copy of the GNU Lesser General Public
-# License along with this library; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
-# For questions and ideas, please contact the author at jens@jayfield.org
-
-# ---------------------------------------------------------------------
-
-arg = $*
-MAX_SIZE_ROM = 1024
-PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
-ENTITY_NAME = "rom"
-ENTITY_DATA_TYPE = "inst_t"
-ENTITY_ADDR_TYPE = "inst_addr_t"
-OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-filename = arg.to_s
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-# --------------------------------------------------------
-# Pass 1
-# --------------------------------------------------------
-lc = 0	# Line counter
-pc = 0	# Program counter
-chip_dc = [0,0,0,0]	# chip data counter
-xmem_dc = 0	# xmem data counter
-curr_segment = "UNDEF";
-page = 0
-
-label_list=[[],[]]
-instr_list=[nil]
-file = File.open(filename, "r")
-file.each do |raw_line|
-	lc += 1
-
-	# Make all upper case
-	iline = "#{raw_line}".strip.upcase
-	
-	# Remove comments
-	iline = iline.gsub(/;.*/, "")
-	
-	# Split instruction at spaces
-	iline_member = iline.split(" ")
-
-	if iline_member[0] == nil
-		next
-	end	
-	
-	mc = 0;
-	label = nil
-	clean_line = nil
-	if (iline_member[0] =~ /\w+:/)
-		mc += 1
-		label = iline_member[0].delete(":")
-		if label_list.rindex(label) != nil
-			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
-			exit 1
-		end
-	end
-	
-	case iline_member[mc]
-	when nil
-		value = format("0x%3.3X",pc)
-	when "EQU"
-		if 0 == (iline_member[mc+1] =~ /\d+/)
-			value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
-		else 	
-			value = iline_member[mc+1]
-		end 	
-	when "ORG", "CODE"
-		pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
-		value = format("0x%3.3X",pc)
-	when "CDATA", "CMEM"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
-			exit 1
-		end 	
-		curr_segment = "CMEM";
-		page = iline_member[mc+1].to_i(16)
-	when "XDATA", "XMEM"
-		curr_segment = "XMEM";
-	when "DC"
-		len = 0;
-		iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| 
-			len += 1
-		end	
-		if curr_segment == "CMEM"
-			STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
-			exit 1
-		else
-			value = format("0x%2.2X",xmem_dc)
-			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
-			xmem_dc += len
-		end	
-	when "DB"
-		len = iline_member[mc+1].to_i
-		if curr_segment == "CMEM"
-			value = format("0x%2.2X",chip_dc[page])
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
-			chip_dc[page] += len
-		else
-			value = format("0x%2.2X",xmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
-			xmem_dc += len
-		end	
-	else
-		op_line = iline_member[mc+1..iline_member.nitems].to_s
-		value = format("0x%3.3X",pc)
-		opc = iline_member[mc]
-		if iline_member[mc+1] != nil
-			op1 = op_line.gsub(/,+.*$/, "")
-		end	
-		if iline_member[mc+2] != nil
-			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
-		end	
-		if instr_list[pc] == nil
-			instr_list[pc] = [lc, pc, opc , op1 , op2]
-			pc += 1
-		else
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
-			exit 1
-		end
-	end;	
-
-	# Push labels
-	if label	
-		label_list = label_list + [label, value]
-	end
-end
-file.close
-
-# --------------------------------------------------------
-def instr(opcode)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
-end	
-
-def tcl_bits(pc, opcode)
-	return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
-end
-
-def instr_k(opcode, k)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
-end	
-
-def tcl_bits_k(pc, opcode, k)
-	return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
-end
-
-def instr_r(opcode, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
-end	
-
-def tcl_bits_r(pc, opcode, r)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
-end
-
-def instr_kr(opcode, k, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_kr(pc, opcode, k, r)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rk(opcode, r, k)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_rk(pc, opcode, r, k)
-	return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rr(opcode, ra, rb)
-	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
-end	
-
-def tcl_bits_rr(pc, opcode, ra, rb)
-	return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
-end
-
-# --------------------------------------------------------
-# Read mnemonic set
-# --------------------------------------------------------
-filename = OPC_LIST_NAME
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-mnemo_list = []
-num_opcodes = 0
-file = File.open(filename, "r")
-file.each do |raw_line|
-	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
-	num_opcodes += 1
-end
-
-# --------------------------------------------------------
-# Pass 2
-# --------------------------------------------------------
-pc = 0
-opc_start = 2
-num_errors = 0
-vhdl_trans_list = [nil]
-vhdl_comment_list = [nil]
-vhdl_tcl_list = [nil]
-instr_list.each do |instruct|
-		
-	# puts instruct
-	if instruct == nil
-		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
-		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
-		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
-		pc += 1
-		next
-	end
-		
-	# determine arglen of instruction
-	ilen = 0
-	if instruct[opc_start+1] == nil
-		arglen = 0
-	elsif instruct[opc_start+2] == nil
-		arglen = 1
-	elsif instruct[opc_start+3] == nil
-		arglen = 2
-	end	
-	
-	# Symbol substitution
-	error = false
-	for i in (1..3)
-		subst_pos = opc_start+i
-		if instruct[subst_pos] == nil
-			next
-		end	
-		expr_token = ""
-		expr_subst = nil
-		is_direct = true;
-		
-#		instruct[subst_pos] = instruct[subst_pos].delete(" ")
-
-		# checks R0 .. R16, Mnemonics
-		instr_str = instruct[subst_pos]
-		if 0 == (instr_str =~ /\(.+\)/)
-			instr_str = instr_str.delete("()")
-			is_direct = false;
-		end	
-
-		expr_token = instr_str.split(/\+|\-|\*|\//)[0]
-		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
-			idx = label_list.rindex(expr_token)
-			if idx != nil
-				expr_subst = label_list[idx+1]
-				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
-			else
-				STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
-				error = true
-			end
-		end	
-		
-		if expr_subst != nil
-			if 0 == (expr_subst =~ /\d+/) 
-				if is_direct == true
-					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
-				else
-					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
-				end	
-			else
-				if 0 != (expr_subst =~ /R[0-9]+/)
-					STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
-					error = true
-				end
-			end
-		end	
-	end
-	
-	# Parse operands
-	reg = [0,0]
-	kk = 0
-	format = instruct[opc_start]
-	for i in (0..1)
-		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
-			# Check indirect addressing
-			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
-			format += "|R"
-			if reg[i] > 15
-				STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
-				error = true
-			end
-		else
-			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
-				kk = instruct[opc_start+i+1].delete("()").to_i(16)
-				format += "|K"
-			end
-		end
-		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
-			format += "i";
-		end
-	end 
-	
-	# Output instruction
-	opcode = mnemo_list.rindex(format).to_i
-	mnemo = instruct[2];
-
-	case format
-	when "NOP", "HALT", "RET", "RETI"
-		vhdl_trans_list[pc] = instr(opcode)
-		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-	when "MOVC|R|Ri", "MOVX|R|Ri"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
-	when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
-	when "MOVC|Ri|R", "MOVX|Ri|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
-	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
-	when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
-	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
-		vhdl_trans_list[pc] = instr_k(opcode, kk)
-		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
-		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
-	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
-		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
-		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-	when "TST|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("CMP|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "INC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("ADD|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "DEC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	else
-		STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
-		error = true
-	end
-
-	if error
-		num_errors += 1
-		break
-	end
-	vhdl_comment_list[pc] = minstr_comment
-
-	puts vhdl_trans_list[pc] + " -- " + minstr_comment
-	
-	pc += 1
-end
-
-# --------------------------------------------------------
-# Output ROM file
-# --------------------------------------------------------
-if num_errors == 0
-
-	filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", ENTITY_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("ROM file written to \"%s\"\n",filename)
-	file.close
-end
-if num_errors == 0
-
-	filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	if pc < (MAX_SIZE_ROM-1)
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
-		for i in (pc..(MAX_SIZE_ROM-2))
-			file.puts "\t\t" + instr(0) + ",\n"
-		end;
-		file.puts "\t\t" + instr(0) + "\n"
-	else
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
-	end	
-	file.puts format("\t);\n")
-	puts format("PREINIT file written to \"%s\"\n",filename)
-	file.close
-end
-if num_errors == 0
-	filename = format("rom_%s.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	for i in (0..pc-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("\# %s", vhdl_comment_list[i]) 
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
-	end;
-	puts format("TCL snippet written to \"%s\"\n",filename)
-	file.close
-end
-
-# --------------------------------------------------------
-# Output final statistics
-# --------------------------------------------------------
-if num_errors == 0
-	puts "Program uses #{pc} instruction addresses"
-	puts "No errors found"
-	exit 0
-else
-	puts "#{num_errors} errors found"
-	exit 1
-end	
diff --git a/lib/CPUs/JCpu/tools/jasm.rb b/lib/CPUs/JCpu/tools/jasm.rb
deleted file mode 100644
index 0959ba9..0000000
--- a/lib/CPUs/JCpu/tools/jasm.rb
+++ /dev/null
@@ -1,814 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: A small assembler for the JCPU
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-FILE_SUFFIX = "jsm"
-IROM_MAX_SIZE = 1024
-IROM_ENTITY_NAME = "irom"
-IROM_DATA_TYPE = "inst_t"
-IROM_ADDR_TYPE = "inst_addr_t"
-XROM_MAX_SIZE = 256
-XROM_DATA_TYPE = "dmem_data_t"
-XROM_ADDR_TYPE = "dmem_addr_t"
-XROM_ENTITY_NAME = "xrom"
-OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
-
-# --------------------------------------------------------
-class Parser
-	def curr_segment
-		@curr_segment
-	end	
-	def curr_segment=(arg)
-		@curr_segment=arg
-	end	
-	def add_label(labelname, addr)
-		@label_list = @label_list + [labelname, addr]
-	end
-	def	getLabelIdByName(label)
-		return @label_list.rindex(label)
-	end
-	def	getLabelNameById(id)
-		return @label_list[id]
-	end
-	def put_instr(name, lc, opc , op1 , op2)
-		if get_instr != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc)
-			exit 1
-		end
-		@instr_list[@pc] = [lc, @pc, opc , op1 , op2, name]
-	end
-	def	get_instr
-		return @instr_list[@pc]
-	end
-	def put_xmem(value, lc)
-		if get_xmem != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment)
-			exit 1
-		end
-		@xmem[xmem_dc] = value
-		@xmem_dc = xmem_dc + 1
-	end	
-	def get_xmem
-		return @xmem[xmem_dc]
-	end	
-	def xmem
-		return @xmem
-	end	
-	def put_cmem(value, lc)
-		if get_cmem(page) != nil
-			STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment)
-			exit 1
-		end
-		@cmem[page][cmem_dc] = value
-		@cmem_dc[page] = cmem_dc + 1
-	end	
-	def get_cmem(pg)
-		return @cmem[pg][cmem_dc]
-	end	
-	def cmem(page)
-		return @cmem[page]
-	end	
-	def	cmem_dc=(addr)
-		@cmem_dc[page] = addr
-	end	
-	def	cmem_dc
-		@cmem_dc[page]
-	end	
-	def	xmem_dc=(addr)
-		@xmem_dc = addr
-	end	
-	def	xmem_dc
-		@xmem_dc
-	end	
-	def page=(page)
-		@page = page;
-	end	
-	def page
-		@page;
-	end	
-	def pc=(pc)
-		@pc = pc;
-		if (pc > @pc_max)
-			@pc_max = pc
-		end	
-	end	
-	def pc
-		@pc;
-	end	
-	def pc_max
-		@pc_max;
-	end	
-	def	instr_list
-		@instr_list
-	end
-	def	label_list
-		@label_list
-	end
-	
-	def initialize()
-		@pc_max = 0
-		@pc = 0					# Program counter
-		@cmem_dc = [0,0,0,0]	# chip data counter
-		@xmem_dc = 0			# xmem data counter
-		@curr_segment = "UNDEF";
-		@page = 0
-		@label_list=[[],[]]
-		@instr_list=[nil]
-		@cmem = [[],[]];
-		@xmem = [];
-	end
-	def method_missing(name, *args)
-		puts "I don't know the method #{name}"
-	end
-end	
-
-# --------------------------------------------------------
-def parse(name, obj)
-
-lc = 0	# Line counter
-file = File.open(name, "r")
-
-file.each do |raw_line|
-	lc += 1
-
-	# Make all upper case
-	iline = "#{raw_line}".strip
-	
-	# Remove comments
-	iline = iline.gsub(/;.*/, "")
-	
-	# Split instruction at spaces
-	iline_member = iline.split(" ")
-
-	if iline_member[0] == nil
-		next
-	end	
-	
-	mc = 0;
-	label = nil
-	clean_line = nil
-	if (iline_member[0] =~ /\w+:/)
-		mc += 1
-		label = iline_member[0].delete(":")
-		if obj.getLabelIdByName(label) != nil
-			STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
-			exit 1
-		end
-	end
-	
-	token = iline_member[mc]
-	if token
-		token = token.upcase
-	end
-	
-	case token
-	when nil
-		if obj.curr_segment == "CMEM"
-			curr_addr = format("0x%3.3X",obj.cmem_dc)
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%3.3X",obj.xmem_dc)
-		elsif obj.curr_segment == "CODE"
-			curr_addr = format("0x%3.3X",obj.pc)
-		else
-			STDERR.puts format("Error in line %d: Undefined segment", lc)
-			exit 1
-		end
-	when "INCLUDE"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		inc_name = iline_member[mc+1].delete("\"")
-		puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc);
-		parse(inc_name, obj)
-	when "EQU"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		if 0 == (iline_member[mc+1] =~ /\d+/)
-			curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
-		else 	
-			curr_addr = iline_member[mc+1]
-		end 	
-	when "ORG"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		offset = eval(iline_member[mc+1..iline_member.nitems].to_s)
-		case obj.curr_segment
-			when "CODE"
-			obj.pc = offset
-			curr_addr = format("0x%3.3X",obj.pc)
-			when "CMEM"
-			obj.cmem_dc = offset
-			when "XMEM"
-			obj.xmem_dc = offset
-			
-		end	
-	when "CODE"
-		curr_addr = format("0x%3.3X",obj.pc)
-		obj.curr_segment = "CODE";
-	when "CDATA", "CMEM"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		obj.curr_segment = "CMEM";
-		obj.page = iline_member[mc+1].to_i(16)
-	when "XDATA", "XMEM"
-		obj.curr_segment = "XMEM";
-	when "DC"
-		len = 0;
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		if obj.curr_segment == "CMEM"
-			STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment)
-			exit 1
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%2.2X",obj.xmem_dc)
-			dc_old = obj.xmem_dc;
-			val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",")
-			
-			# Parse string literals
-			val_array.each do |item| 
-				if 0 == (item =~ /.*\".*\"/)
-					str = item.delete("\"")
-					puts item
-					for nn in (0..str.length-1)
-						if str[nn] > 31
-							obj.put_xmem(str[nn], lc);
-						 	puts "S: " + str[nn].to_s
-							len += 1
-						end	
-					end;
-				else
-					argument = item
-					puts "B: " + argument
-					obj.put_xmem(eval(argument), lc);
-					len += 1
-				end	
-			end	
-			puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment);
-		else	
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end	
-	when "DB"
-		if iline_member[mc+1] == nil
-			STDERR.puts format("Error in line %d: %s needs argument!", lc, token)
-			exit 1
-		end 	
-		len = eval(iline_member[mc+1]).to_i
-		if obj.curr_segment == "CMEM"
-			curr_addr = format("0x%2.2X",obj.cmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page);
-			for nn in (1..len)
-				obj.put_cmem(0, lc)
-			end	
-		elsif obj.curr_segment == "XMEM"
-			curr_addr = format("0x%2.2X",obj.xmem_dc)
-			puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment);
-			for nn in (1..len)
-				obj.put_xmem(0, lc)
-			end	
-		else	
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end	
-	else
-		if obj.curr_segment != "CODE"
-			STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token)
-			exit 1
-		end			
-
-		op_line = iline_member[mc+1..iline_member.nitems].to_s
-		curr_addr = format("0x%3.3X",obj.pc)
-		opc = token
-		if iline_member[mc+1] != nil
-			op1 = op_line.gsub(/,+.*$/, "")
-		end	
-		if iline_member[mc+2] != nil
-			op2 = op_line.scan(/,.+$/).to_s.delete(", ")
-		end	
-		obj.put_instr(name, lc, opc, op1, op2)
-		obj.pc = obj.pc + 1
-	end;	
-
-	# Push labels
-	if label	
-		obj.add_label(label, curr_addr)
-	end
-end
-file.close
-return obj
-end
-
-# --------------------------------------------------------
-# Instruction formatting
-# --------------------------------------------------------
-def instr(opcode)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
-end	
-
-def tcl_bits(pc, opcode)
-	return format("%12.12B%8.8B%12.12B",pc, opcode ,0)
-end
-
-def instr_k(opcode, k)
-	return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
-end	
-
-def tcl_bits_k(pc, opcode, k)
-	return format("%12.12B%8.8B%12.12B",pc, opcode ,k)
-end
-
-def instr_r(opcode, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
-end	
-
-def tcl_bits_r(pc, opcode, r)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r)
-end
-
-def instr_kr(opcode, k, r)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_kr(pc, opcode, k, r)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rk(opcode, r, k)
-	return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
-end	
-
-def tcl_bits_rk(pc, opcode, r, k)
-	return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r)
-end
-
-def instr_rr(opcode, ra, rb)
-	return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
-end	
-
-def tcl_bits_rr(pc, opcode, ra, rb)
-	return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
-end
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-filename = arg.to_s
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX)
-
-# --------------------------------------------------------
-# Pass 1
-# --------------------------------------------------------
-first_pass = Parser.new();
-parse(filename, first_pass)
-
-# --------------------------------------------------------
-# Read mnemonic set
-# --------------------------------------------------------
-filename = OPC_LIST_NAME
-if !File.exists?(filename)
-	STDERR.puts "#{filename} does not exist"
-	exit 1
-end
-
-mnemo_list = []
-num_opcodes = 0
-file = File.open(filename, "r")
-file.each do |raw_line|
-	mnemo_list[num_opcodes] = raw_line.split(" ")[1]
-	num_opcodes += 1
-end
-
-# --------------------------------------------------------
-# Pass 2
-# --------------------------------------------------------
-pc = 0
-opc_start = 2
-num_errors = 0
-vhdl_trans_list = [nil]
-vhdl_comment_list = [nil]
-vhdl_tcl_list = [nil]
-
-# ToDo: Use class-methods
-label_list = first_pass.label_list
-instr_list = first_pass.instr_list
-
-instr_list.each do |instruct|
-		
-	# puts instruct
-	if instruct == nil
-		vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
-		vhdl_comment_list[pc] = format("0x%3.3X:", pc)
-		vhdl_tcl_list[pc] = tcl_bits(pc, 0)
-		pc += 1
-		next
-	end
-		
-	# determine arglen of instruction
-	ilen = 0
-	if instruct[opc_start+1] == nil
-		arglen = 0
-	elsif instruct[opc_start+2] == nil
-		arglen = 1
-	elsif instruct[opc_start+3] == nil
-		arglen = 2
-	end	
-	
-	# Symbol substitution
-	error = false
-	for i in (1..2)
-		subst_pos = opc_start+i
-		if instruct[subst_pos] == nil
-			next
-		end	
-		expr_token = ""
-		expr_subst = nil
-		is_direct = true;
-		
-		# checks R0 .. R16, Mnemonics
-		instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "")
-		if (nil != (instruct[subst_pos] =~ /'high/))
-			instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, ""))
-		end	
-		instr_str = instruct[subst_pos]
-		if 0 == (instr_str =~ /\(.+\)/)
-			instr_str = instr_str.delete("()")
-			is_direct = false;
-		end	
-
-		expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0]
-		if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
-			idx = label_list.rindex(expr_token)
-			if idx != nil
-				expr_subst = label_list[idx+1]
-				instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
-			else
-				STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token)
-				error = true
-			end
-		end	
-		
-		if expr_subst != nil
-			if 0 == (expr_subst =~ /\d+/) 
-				if is_direct == true
-					instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
-				else
-					instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
-				end	
-			else
-				if 0 != (expr_subst =~ /R[0-9]+/)
-					STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst)
-					error = true
-				end
-			end
-		end	
-	end
-	
-	# Parse operands
-	reg = [0,0]
-	kk = 0
-	format = instruct[opc_start]
-	for i in (0..1)
-		if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
-			# Check indirect addressing
-			reg[i] = instruct[opc_start+i+1].delete("R()").to_i
-			format += "|R"
-			if reg[i] > 15
-				STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i])
-				error = true
-			end
-		else
-			if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
-				kk = eval(instruct[opc_start+i+1].delete("()"))
-				format += "|K"
-			end
-		end
-		if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
-			format += "i";
-		end
-	end 
-	
-	if error
-		num_errors += 1
-		break
-	end
-
-	# Output instruction
-	opcode = mnemo_list.rindex(format).to_i
-	mnemo = instruct[2];
-
-	case format
-	# Native instructions
-	when "NOP", "HALT", "RET", "RETI", "SETC"
-		vhdl_trans_list[pc] = instr(opcode)
-		vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-	when "MOVC|R|Ri", "MOVX|R|Ri"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
-	when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
-		minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
-	when "MOVC|Ri|R", "MOVX|Ri|R"
-		vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
-		vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
-	when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
-	when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-		minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
-	when "SUB|K|R", "SUBC|K|R"
-		kk = kk % 256;
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1])
-	when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
-		vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
-		vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
-		minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
-	when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
-		vhdl_trans_list[pc] = instr_k(opcode, kk)
-		vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
-		minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
-	when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R"
-		vhdl_trans_list[pc] = instr_r(opcode, reg[0])
-		vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-	# Synthetic instructions
-	when "CLRC"
-		kk = 0;
-		minstr_comment = format("0x%3.3X: %s", pc, mnemo)
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "TST|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("CMP|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "NEG|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|K|R").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "NOT|R"
-		kk = 0
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("XOR|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "INC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("ADD|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	when "DEC|R"
-		kk = 1
-		minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
-		opcode = mnemo_list.rindex("SUB|R|K").to_i
-		vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
-		vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
-	else
-		STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format)
-		error = true
-	end
-
-	if error
-		num_errors += 1
-		break
-	end
-
-	vhdl_comment_list[pc] = minstr_comment
-
-	puts vhdl_trans_list[pc] + " -- " + minstr_comment
-	
-	pc += 1
-end
-
-# --------------------------------------------------------
-# Output ROM file
-# --------------------------------------------------------
-if num_errors == 0
-
-	# I-ROM VHDL-ROM
-	filename = format("%s.irom.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", IROM_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", IROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\tconstant imem_rom : imem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..[IROM_MAX_SIZE, pc].min-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("I-ROM file written to \"%s\"\n",filename)
-	file.close
-
-	# I-ROM VHDL-ROM (loadable)
-	filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE)
-	file.puts format("\tsignal imem_rom : imem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..pc-2)
-		file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
-	end;
-	if pc < (IROM_MAX_SIZE-1)
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
-		for i in (pc..(IROM_MAX_SIZE-2))
-			file.puts "\t\t" + instr(0) + ",\n"
-		end;
-		file.puts "\t\t" + instr(0) + "\n"
-	else
-		file.puts "\t\t" + vhdl_trans_list[pc-1] + "  -- " + vhdl_comment_list[pc-1] + "\n"
-	end	
-	file.puts format("\t);\n")
-	puts format("I-ROM (loadable) file written to \"%s\"\n",filename)
-	file.close
-
-	# I-ROM TCL-Loader
-	filename = format("%s.irom.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("# ---------------------------------------------------------------");
-	file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA");
-	file.puts format("# User 1")
-	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n")
-	for i in (0..pc-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("\# %s", vhdl_comment_list[i]) 
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
-	end;
-	puts format("I-ROM TCL-loader written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM VHDL-ROM
-	filename = format("%s.xrom.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME)
-	file.puts format("\tPort (\n")
-	file.puts format("\tclk\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\tce\t\t\t: in  STD_LOGIC;\n")
-	file.puts format("\taddr\t\t: in  %s;\n", XROM_ADDR_TYPE)
-	file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE)
-	file.puts format("\t);\n")
-	file.puts format("END %s;\n", XROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME)
-	file.puts format("\n")
-	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
-	file.puts format("\n")
-	file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..XROM_MAX_SIZE-2)
-		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
-	end;
-	i = XROM_MAX_SIZE-1
-	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
-	file.puts format("\t);\n")
-	file.puts format("\n")
-	file.puts format("begin")
-	file.puts format("\n")
-	file.puts format("PROM_READ:")
-	file.puts format("\tprocess(clk, ce)\n")
-	file.puts format("\tbegin\n")
-	file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
-	file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n")
-	file.puts format("\t\tend if;\n")
-	file.puts format("\tend process;\n")
-	file.puts format("\n")
-	file.puts format("end %s;\n", PROJECT_NAME)
-	puts format("X-ROM file written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM VHDL-ROM (loadable)
-	filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-
-	file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE)
-	file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n")
-	file.puts format("\t(\n");
-	for i in (0..XROM_MAX_SIZE-2)
-		file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i)
-	end;
-	i = XROM_MAX_SIZE-1
-	file.puts format("\t\tX\"%2.2X\"  -- 0x%2.2X\n", first_pass.xmem[i], i)
-	file.puts format("\t);\n")
-	puts format("X-ROM (loadable) file written to \"%s\"\n",filename)
-	file.close
-
-	# X-ROM JTAG-Loader
-	filename = format("%s.xrom.tcl.snip", PROJECT_NAME)
-	file = File.open(filename, "w")
-	file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX)
-	file.puts format("# ---------------------------------------------------------------");
-	file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA");
-	file.puts format("# User 2")
-	file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n")
-	for i in (0..first_pass.xmem.length-1)
-		# Chipscope 8.1
-#		file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
-
-		# Chipscope 9.1
-		file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]);
-	end;
-	puts format("X-ROM TCL-loader written to \"%s\"\n",filename)
-	file.close
-
-end
-
-# --------------------------------------------------------
-# Output final statistics
-# --------------------------------------------------------
-if num_errors == 0
-	puts "Program uses #{first_pass.pc_max} instruction addresses"
-	puts "No errors found"
-	exit 0
-else
-	puts "#{num_errors} errors found"
-	exit 1
-end	
-
diff --git a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm
deleted file mode 100644
index 01c36c4..0000000
--- a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm
+++ /dev/null
@@ -1,72 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xio-address equates for
-; reg_cg_char_addr:	equ		0xXX	; RW
-; reg_cg_line_addr:	equ		0xXX	; RW
-; reg_cg_data:		equ		0xXX	; RW
-; reg_cg_ctrl:		equ		0xXX	; WO
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-cg_clr_line:	push	R0
-				mov		R0, 2
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-cg_clr_screen:	push	R0
-				mov		R0, 1
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-; R0 : char address
-; R1 : line address
-cg_set_addr:	call	cg_wait_rdy
-				xout	(reg_cg_line_addr), R1
-				xout	(reg_cg_char_addr), R0
-				ret
-
-; -------------------------------------------------
-; R0 : character
-cg_putchar:		call	cg_wait_rdy
-				xout	(reg_cg_data), R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts:		push	R0
-cg_p_lp:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		ex_cgp
-				call	cg_putchar
-				jmp		cg_p_lp
-ex_cgp:			pop		R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_clr_puts:	call	cg_clr_line
-				call	cg_puts
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts_clr:	call	cg_puts
-				call	cg_clr_line
-				ret				
-
-; -------------------------------------------------
-cg_wait_rdy:	push	R0
-cg_wr_lp:		xin		R0, (reg_hwstat)
-				and		R0, 0x02
-				jz		cg_wr_lp
-				pop		R0
-				ret
-
-; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm
deleted file mode 100644
index 06d39d9..0000000
--- a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm
+++ /dev/null
@@ -1,7 +0,0 @@
-; JCPU On-Chip register
-cpu_revision:		equ		0x00	; RO
-cpu_control:		equ		0x01	; R/W
-cpu_status:			equ		0x02	; RO
-cpu_int_ctrl:		equ		0x03	; RW
-cpu_cmem_high:		equ		0x04	; RW
-cpu_stack_high:		equ		0x05	; RW
diff --git a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm
deleted file mode 100644
index 6f002ee..0000000
--- a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm
+++ /dev/null
@@ -1,64 +0,0 @@
-; -------------------------------------------------
-; Delays
-; -------------------------------------------------
-delay1s:		push	R15
-				mov		R15, 10
-loop1s:			call 	delay100ms		
-				dec		R15
-				jnz		loop1s
-				pop		R15
-				ret
-
-delay100ms:		push	R15
-				mov		R15, 10
-loop100ms:		call 	delay10ms		
-				dec		R15
-				jnz		loop100ms
-				pop		R15
-				ret
-			
-delay10ms:		push	R15
-				mov		R15, 10
-loop10ms:		call	delay1ms		
-				dec		R15
-				jnz		loop10ms
-				pop		R15
-				ret
-		
-delay1ms:		push	R15
-				mov		R15, 10
-loop1ms:		call	delay100us
-				dec		R15
-				jnz		loop1ms
-				pop		R15
-				ret
-
-delay100us:		push	R15
-				mov		R15, 10
-loop100us:		call	delay10us
-				dec		R15
-				jnz		loop100us
-				pop		R15
-				ret
-
-delay10us:		push	R15
-				mov		R15, 99
-loop10us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop10us
-				pop		R15
-				ret
-
-delay1us:		push	R15
-				mov		R15, 9
-loop1us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop1us
-				pop		R15
-				ret
-				
-; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm
deleted file mode 100644
index d2883fa..0000000
--- a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm
+++ /dev/null
@@ -1,208 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - lcd_port (LCD-Base)
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-lcd_cmd:		equ		0x00
-lcd_rd:			equ		0x20
-lcd_data:		equ		0x40
-lcd_enable:		equ		0x80
-
-LCD_CMD_Z1:		equ		0x80
-LCD_CMD_Z2:		equ		0xC0
-LCD_CMD_CLEAR:	equ		0x01
-
-; -------------------------------------------------
-; Init LCD
-; -------------------------------------------------
-LCD_init:		mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-				mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-
-				mov		R2, 0x00		
-				mov		R0, 0x02
-				call	_write_lcd
-				call	delay1ms
-
-				; 1. Function set: 4-Bit mode, two display lines
-				mov		R0, 0x28
-				call	LCD_writecmd
-
-				; 2. Display on, no cursor
-				mov		R0, 0x0C		
-				call	LCD_writecmd
-
-				; 3. Cursor shift during write
-				mov		R0, 0x06
-				call	LCD_writecmd
-
-				; 4. Display clear
-				mov		R0, 0x01
-				call	LCD_writecmd
-
-				ret
-				
-; -------------------------------------------------
-; LCD_waitbsy
-; -------------------------------------------------
-LCD_waitbsy:	push	R0
-bsy_loop:		call	LCD_readstat
-				and		R0, 0x80
-				jz		ex_bsy
-				call	delay1us
-				jmp		bsy_loop
-ex_bsy:			pop		R0
-				ret
-
-; -------------------------------------------------
-; LCD_writecmd
-; -------------------------------------------------
-; R0 = cmd
-LCD_writeaddr:
-LCD_writecmd:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_write
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_putsx
-; -------------------------------------------------
-; R1 = address of null-terminated string in XMEM
-LCD_putsx:		push	R0
-putsx_loop:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsx_ex
-				call	LCD_writechar
-				jmp		putsx_loop
-putsx_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_putsc
-; -------------------------------------------------
-; R1 = address of null-terminated string in CMEM
-LCD_putsc:		push	R0
-putsc_loop:		movc	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsc_ex
-				call	LCD_writechar
-				jmp		putsc_loop
-putsc_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_writechar
-; -------------------------------------------------
-; R0 = char
-LCD_writedata:
-LCD_writechar:	push	R2
-				mov		R2, lcd_data
-				call	LCD_write
-				pop		R2
-				ret
-				
-; -------------------------------------------------
-; LCD_write
-; -------------------------------------------------
-; R0 = input
-; R2 = register
-LCD_write:		call	LCD_waitbsy
-				push	R0
-				swap	R0
-				call	_write_lcd
-				pop		R0
-				call	_write_lcd
-				ret
-
-; -------------------------------------------------
-; LCD_readstat
-; -------------------------------------------------
-; R0 = status
-LCD_readstat:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_read
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_read
-; -------------------------------------------------
-; R0 = output
-; R2 = register
-LCD_read:		call	_read_lcd
-				swap	R0
-				push	R0
-				call	_read_lcd
-				pop		R2
-				or		R0, R2
-				ret
-				
-; -------------------------------------------------
-; _write
-; -------------------------------------------------
-; R0 = input
-_write_lcd:		push	R1
-
-				and		R0, 0x0F
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				or		R1, lcd_rd
-				xout	(lcd_port), R1
-
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; _read
-; -------------------------------------------------
-; R0 = output
-_read_lcd:		push	R1
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-				xin		R0, (lcd_port)
-				and		R0, 0x0F
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				pop		R1
-				ret
-
-				
\ No newline at end of file
diff --git a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm
deleted file mode 100644
index 2f66e2a..0000000
--- a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm
+++ /dev/null
@@ -1,42 +0,0 @@
-; -------------------------------------------------
-; mul8x8.inc.jsm
-; -------------------------------------------------
-
-; -------------------------------------------------
-; Parameter:
-; R0 : operand 1
-; R1 : operand 2
-; Return:
-; R0 : product low
-; R1 : product high
-mul8x8:			push	R2
-				push	R3
-				push	R4
-				
-				mov		R4, R1
-				mov		R1, 0
-				mov		R2, 0
-				mov		R3, 0
-				
-loop1:			cmp		R4, 0x01
-				jeq		ende1
-
-				shr		R4
-				jnc		next1
-
-				add		R2, R0
-				addc	R3, R1
-
-next1:			shl		R0
-				rolc	R1
-				jmp		loop1
-				
-ende1:			add		R0, R2
-				addc	R1, R3
-				
-				pop		R4
-				pop		R3
-				pop		R2
-				ret
-
-; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm
deleted file mode 100644
index 1733305..0000000
--- a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; uart.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - uart_status (Status register)
-; - uart_data	(Data register)
-
-; -------------------------------------------------
-; sout
-; -------------------------------------------------
-; R0 = input
-sout:			push 	R1
-sout1:			xin		R1, (uart_status)
-				and		R1, 0x02
-				jnz		sout1
-				xout	(uart_data), R0
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; sin
-; -------------------------------------------------
-; R0 = output
-sin:			push 	R1
-sin1:			xin		R1, (uart_status)
-				and		R1, 0x10
-				jnz		sin1
-				xin		R0, (uart_data)
-				pop		R1
-				ret
-
-; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm
deleted file mode 100644
index f354d7c..0000000
--- a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; utils.inc.jsm
-; -------------------------------------------------
-
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value in lower nibble
-; Return
-; R0 : Hex character representing lower nibble
-nibble2hex:		and		R0, 0x0F
-				cmp		R0, 0x0A
-				jlt		isNum1
-				add		R0, 0x07
-isNum1:			add		R0, 0x30
-				ret
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value
-; Return
-; R0 : Hex character high
-; R1 : Hex character low
-bin2hex:		push	R0
-				call	nibble2hex
-				mov		R1, R0
-				pop		R0
-				swap	R0
-				call	nibble2hex
-				ret
-
-; -------------------------------------------------
diff --git a/lib/CPUs/JCpu/tools/opc.list b/lib/CPUs/JCpu/tools/opc.list
deleted file mode 100644
index 59b3cfa..0000000
--- a/lib/CPUs/JCpu/tools/opc.list
+++ /dev/null
@@ -1,64 +0,0 @@
-0 NOP         
-1 HALT        
-2 MOV|R|R     
-3 MOV|R|K     
-4 MOVX|R|Ri   
-5 MOVX|R|Ki   
-6 MOVX|Ri|R   
-7 MOVX|Ri|K   
-8 MOVX|Ki|R   
-9 MOVC|R|Ri   
-10 MOVC|R|Ki   
-11 MOVC|Ri|R   
-12 MOVC|Ri|K   
-13 MOVC|Ki|R   
-14 CMP|R|R     
-15 CMP|R|K     
-16 ADD|R|R     
-17 ADD|R|K     
-18 ADDC|R|R    
-19 ADDC|R|K    
-20 SUB|R|R     
-21 SUB|R|K     
-22 SUBC|R|R    
-23 SUBC|R|K    
-24 AND|R|R     
-25 AND|R|K     
-26 OR|R|R      
-27 OR|R|K      
-28 XOR|R|R     
-29 XOR|R|K     
-30 SHL|R       
-31 SHR|R       
-32 ROL|R       
-33 ROR|R       
-34 ROLC|R      
-35 RORC|R      
-36 XOUT|Ki|R   
-37 XOUT|Ri|K   
-38 COUT|Ki|R   
-39 COUT|Ri|K   
-40 XIN|R|Ki    
-41 CIN|R|Ki    
-42 SWAP|R      
-43 SETC        
-44 UNDEF       
-45 UNDEF       
-46 SUB|K|R     
-47 SUBC|K|R    
-48 JMP|K       
-49 JZ|K        
-50 JNZ|K       
-51 JC|K        
-52 JNC|K       
-53 JLT|K       
-54 JGT|K       
-55 JLE|K       
-56 JGE|K       
-57 JEQ|K       
-58 JNE|K       
-59 CALL|K      
-60 PUSH|R      
-61 POP|R       
-62 RET         
-63 RETI        
diff --git a/lib/CPUs/JCpu/tools/regx.rb b/lib/CPUs/JCpu/tools/regx.rb
deleted file mode 100644
index 47775c9..0000000
--- a/lib/CPUs/JCpu/tools/regx.rb
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env ruby
-
-st = "\033[7m"
-en = "\033[m"
-
- while TRUE
-   print "str> "
-   STDOUT.flush
-   str = gets
-   break if not str
-   str.chop!
-   print "pat> "
-   STDOUT.flush
-   re = gets
-   break if not re
-   re.chop!
-   str.gsub! re, "#{st}\\&#{en}"
-   print str, "\n"
-end
-print "\n"
diff --git a/lib/CPUs/JCpu/tools/rom.tcl.tpl b/lib/CPUs/JCpu/tools/rom.tcl.tpl
deleted file mode 100644
index 9f5c0dc..0000000
--- a/lib/CPUs/JCpu/tools/rom.tcl.tpl
+++ /dev/null
@@ -1,61 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/lib/CPUs/JCpu/tools/templates.rb b/lib/CPUs/JCpu/tools/templates.rb
deleted file mode 100644
index 632f11c..0000000
--- a/lib/CPUs/JCpu/tools/templates.rb
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/usr/bin/env ruby
-
-
-template = <<'END'
-		-- (tv #1342) read output FIFO
-		(
-			cycles		=>	1,
-			cm_i		=>	bus_read_init(addr => ADDR_KS_OFIFO_DOUT),
-			sep			=>	msg(""),
-			cm_o 		=>	bus_no_ack,
-			irq			=>	(others => '0')
-		),
-
-		-- (tv #1343) wait while FIFO is read
-		(
-			cycles		=>	2,
-			cm_i		=>	bus_wait_ack,
-			sep			=>	msg(""),
-			cm_o 		=>	bus_no_ack,
-			irq			=>	(others => '0')
-		),
-
-		-- (tv #1343) wait for ack
-		(
-			cycles		=>	1,
-			cm_i		=>	bus_wait_ack,
-			sep			=>	msg(""),
-			cm_o 		=>	bus_read_ack(dat => #{exp_data}),
-			irq			=>	(others => '0')
-		),
-
-END
-
-puts "KS-128 testvectors:\n"
-puts "\n" * 3
-
-
-0.upto(10) { |sk_no|
-	3.downto(0) { |sl_no|
-		exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})"
-		t = template.gsub(/"/, '\\"')
-		puts eval("format(\"#{t}\")")
-	}
-}
diff --git a/lib/CPUs/JCpu/tools/xrom.vhd.tpl b/lib/CPUs/JCpu/tools/xrom.vhd.tpl
deleted file mode 100644
index 5f11f86..0000000
--- a/lib/CPUs/JCpu/tools/xrom.vhd.tpl
+++ /dev/null
@@ -1,32 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.cpu_pkg.all;
-
--- JASM_ROM_INSERT_HERE
-
diff --git a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl
deleted file mode 100644
index 696487f..0000000
--- a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl
+++ /dev/null
@@ -1,151 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-library work;
-use work.cpu_pkg.all;
-
-ENTITY xrom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		addr		: in  dmem_addr_t;
-		dout		: out dmem_data_t
-	);
-	
-END xrom;
-
-ARCHITECTURE loadable OF xrom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: dmem_addr_t;
-	signal jtag_ld_dout		: dmem_data_t;
-	signal jtag_ld_din		: dmem_data_t;
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (15 downto 0);
-	constant id : unsigned (15 downto 0) := X"BEEF";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
-	jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk, ce)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= xmem_rom(to_integer(addr));
-		end if;
-	end process;
-
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/lib/CPUs/MIPS/bsp/examples/.directory_history b/lib/CPUs/MIPS/bsp/examples/.directory_history
deleted file mode 100644
index b367532..0000000
--- a/lib/CPUs/MIPS/bsp/examples/.directory_history
+++ /dev/null
@@ -1,34 +0,0 @@
-VHDL/lib/CPUs/MIPS/bsp/examples/dbg.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/irq.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/irq.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/kernel.S
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/regdef.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/startup.S
-
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h
-
diff --git a/lib/CPUs/MIPS/bsp/examples/Bessel.c b/lib/CPUs/MIPS/bsp/examples/Bessel.c
deleted file mode 100644
index 080fe17..0000000
--- a/lib/CPUs/MIPS/bsp/examples/Bessel.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/************************************************************************/
-/* Ein Programm zur Berechnung der Bessel-Koeffizienten Jn
-/* Dateiname		    : Bessel.cpp
-/* Autoren		    	: T. Burr, J. Ahrensfeld
-/* Datum			      : 28.10.1999
-/* letzte Änderung	: 28.01.2000
-/* Version			    : 1.0
-/************************************************************************/
-
-#include "stdio.h"
-#include "math.h"
-#include "stdlib.h"
-
-
-#define MAX_SUM 25
-#define VERSION "1.0"
-
-/************************************************************************/
-/* Funktionsdeklarationen */
-/************************************************************************/
-// Fakultätsberechnung
-double fak (int N)
-{
-	int index;
-	double erg=1;
-
-	for (index = 1; index <= N; index++)
-		erg = erg * index;
-
-	return erg;
-}
-
-// Bessel()
-// Berechnung von Jn von mfm
-double bessel(int n, double mfm)
-{
-	int m;
-	double Jn=0;
-
-	for (m=0; m < MAX_SUM; m++)
-	{
-		Jn = Jn + (pow(-1.0,m)/(fak(m)*fak(m+n))*pow(mfm/2.0,(2*m+n)));
-	}
-	return Jn;
-}
-
-
-/************************************************************************/
-/* Das Hauptprogramm
-/************************************************************************/
-void main()
-{
-
-	int N, Nmax;
-	double erg;
-	float mfm;
-
-	printf("\n\t     Besselfunktion Version %s",VERSION);
-	printf("\n\t     ~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
-	printf("\n\tCopyright by J. Ahrensfeld & T. Burr\n\n");
-
-// ---------------------------------------------------------------------------------
-		// Benutzereingaben
-		printf("\nBerechnungen fuer J = 0...");
-		if(scanf("%d",&Nmax)==0)
-			exit (-1);
-
-		printf("Bitte Modulationsindex eingeben : ");
-		if(scanf("%f",&mfm)==0)
-			exit(-1);
-
-		printf("\n");
-
-// ---------------------------------------------------------------------------------
-		// Berechnung
-		for (N=0; N <= Nmax; N++)
-		{
-			erg = bessel(N,(double)mfm);
-			printf("J(%d) = %10.8f\n",N,erg);
-		}
-
-		printf("FERTIG.\n");
-
-	}
-
-/************************************************************************/
-
diff --git a/lib/CPUs/MIPS/bsp/examples/Makefile b/lib/CPUs/MIPS/bsp/examples/Makefile
deleted file mode 100644
index 71d95b0..0000000
--- a/lib/CPUs/MIPS/bsp/examples/Makefile
+++ /dev/null
@@ -1,333 +0,0 @@
-ENDIAN='big'
-
-ifeq ($(ENDIAN), 'big')
-  ENDIAN_FLAGS=-EB
-  CFLAGS=$(ENDIAN_FLAGS) -specs=specs/eb/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
-else
-  ENDIAN_FLAGS=-EL
-  CFLAGS=$(ENDIAN_FLAGS) -specs=specs/specs -msoft-float -O2 -march=r3000 -I. -Ilibsys -Wl,-M
-endif
-
-LIBS=-lm -lsys
-
-AS=mipsel-elf-as
-AR=mipsel-elf-ar
-CC=mipsel-elf-gcc
-LD=mipsel-elf-ld
-OBJDUMP=mipsel-elf-objdump
-OBJCOPY=mipsel-elf-objcopy
-FLASHGEN=flashgen
-
-PROG = hello.elf testbench.elf test_irq.elf dhry.elf queens.elf stanford.elf paranoia.elf rmd160_test.elf Bessel.elf whet.elf phrasen.elf dttl.elf richards_benchmark.elf test_exception.elf life.elf r3.elf gunzip.elf basic_math.elf jman_patches.elf jman_patchmeshes.elf jman_polys.elf test_hpi.elf test_vga.elf
-
-all: $(PROG)
-
-libsys.a:
-	$(MAKE) -C libsys
-
-hello.elf: hello.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -Os hello.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-testbench.elf: testbench.c  libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 -DNOSIGNAL -DBATCHMODE -DNOMAIN -Os -g testbench.c paranoia.c delay_mips.c bogomips.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_irq.elf: test_irq.c libsys.a
-	$(CC) $(CFLAGS) -o $@ test_irq.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-dhry.elf: dhry_1.c dhry_2.c dhry.h libsys.a
-	$(CC) $(CFLAGS) -o $@ -DHZ=1000 dhry_1.c dhry_2.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-queens.elf: queens.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -DUNIX_Old -DHZ=1000 queens.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-stanford.elf: stanford.c libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ -DHZ=1000 stanford.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-paranoia.elf: paranoia.c libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ -DNOSIGNAL -DBATCHMODE paranoia.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-rmd160_test.elf: rmd160_test.c rmd160.c rmd160.h libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ rmd160_test.c rmd160.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-hashtest.elf: hashtest.c rmd160.c rmd160.h libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ hashtest.c rmd160.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-Bessel.elf: Bessel.c libsys.a
-	$(CC) $(CFLAGS) -o $@ Bessel.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-whet.elf: whet.c libsys.a
-	$(CC) $(CFLAGS) -o $@ whet.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-phrasen.elf: phrasen.c libsys.a
-	$(CC) $(CFLAGS) -o $@ phrasen.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-dttl.elf: dttl.c random.c libsys.a
-	$(CC) $(CFLAGS) -o $@ dttl.c random.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-richards_benchmark.elf: richards_benchmark.c libsys.a
-	$(CC) $(CFLAGS) -o $@ richards_benchmark.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_exception.elf: test_exception.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -O1 test_exception.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-life.elf: life.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -g life.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-r3.elf: r3.c libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ -DJMIPS_VGA -O2 r3.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-gunzip.elf: gunzip.c inflate.c crc32.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -o $@ gunzip.c inflate.c crc32.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-basic_math.elf: basicmath_small.c   rad2deg.c  cubic.c   isqrt.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -o $@ basicmath_small.c rad2deg.c cubic.c isqrt.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-JMAN_SRC= \
-	jman/bintree.c \
-	jman/camset.c \
-	jman/engine.c \
-	jman/graph_state.c \
-	jman/grid.c \
-	jman/imageio.c \
-	jman/linklist.c \
-	jman/matrix.c \
-	jman/object.c \
-	jman/render.c \
-	jman/ri.c \
-	jman/ribgen.c \
-	jman/stack.c \
-	jman/vars.c
-
-jman_patches.elf:	$(JMAN_SRC) jman/main_patches.c libsys.a
-	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patches.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-jman_patchmeshes.elf:	$(JMAN_SRC) jman/main_patchmeshes.c jman/patches2.c libsys.a
-	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_patchmeshes.c jman/patches2.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-jman_polys.elf:	$(JMAN_SRC) jman/main_polypin.c jman/polys.c  libsys.a
-	$(CC) $(CFLAGS) -I../ -o $@ -o $@ jman/main_polypin.c jman/polys.c $(JMAN_SRC) $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-serdump.elf: serdump.c  libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ -O2 serdump.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-pppi.elf: pppissue/test1.c pppissue/utils.c pppissue/pppd.h libsys.a
-	$(CC) $(CFLAGS) -O2 -o $@ -O2 pppissue/test1.c pppissue/utils.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-lwl.elf: lwl.c  libsys.a
-	$(CC) $(CFLAGS) -O2 -o $@ lwl.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-ucb.elf: ucb.c  libsys.a
-	$(CC) $(CFLAGS) -O2 -o $@ ucb.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_hpi.elf: hpi.c test_hpi.c cfiflash.c libsys.a
-	$(CC) $(CFLAGS) -o $@ -g hpi.c test_hpi.c cfiflash.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin
-	cat $@.srec | packhex > $@.pack
-
-test_vga.elf: test_vga.c libsys.a
-	$(CC) $(CFLAGS) -o $@ test_vga.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-barcode.elf: barcode.c libsys.a
-	$(CC) $(CFLAGS) -o $@ barcode.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-lua.elf: lua_init.c libsys.a
-	$(CC) $(CFLAGS) -I./lua-5.1.4/etc -I./lua-5.1.4/src -o $@ lua_init.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-mandelbrot.elf: mandelbrot.c libsys.a
-	$(CC) $(CFLAGS) -o $@ mandelbrot.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-bogomips.elf: bogomips.c delay_mips.c libsys.a
-	$(CC) $(CFLAGS) -DHZ=1000 -o $@ bogomips.c delay_mips.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_asm.elf: test_asm.S libsys.a
-	$(CC) $(CFLAGS) -DHZ=1000 -o $@ test_asm.S $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_ac97.elf: test_ac97.c libsys.a
-	$(CC) $(CFLAGS) -o $@ test_ac97.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-test_dcache.elf: test_dcache.c libsys.a
-	$(CC) $(CFLAGS) -O0 -o $@ test_dcache.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-aes256_1.elf: aes256_1.c aes256.c aes256.h libsys.a
-	$(CC) $(CFLAGS) -O3 -o $@ aes256_1.c aes256.c $(LIBS) >$@.map
-	$(OBJDUMP) -d $@ > $@.dis
-	$(OBJCOPY) $@ -O binary $@.bin
-	$(OBJCOPY) -O srec $@ $@.srec
-	$(FLASHGEN) $@.bin $(ENDIAN_FLAGS)
-	cat $@.srec | packhex > $@.pack
-
-clean:
-	rm -rf *.a *.o *.bin *.map *.dis *.srec *.pack *.elf $(PROG) > /dev/null
diff --git a/lib/CPUs/MIPS/bsp/examples/aes256.c b/lib/CPUs/MIPS/bsp/examples/aes256.c
deleted file mode 100644
index 97a5136..0000000
--- a/lib/CPUs/MIPS/bsp/examples/aes256.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
-*   Byte-oriented AES-256 implementation.
-*   All lookup tables replaced with 'on the fly' calculations.
-*
-*   Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com
-*   Other contributors: Hal Finney
-*
-*   Permission to use, copy, modify, and distribute this software for any
-*   purpose with or without fee is hereby granted, provided that the above
-*   copyright notice and this permission notice appear in all copies.
-*
-*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-#include "aes256.h"
-
-#define F(x)   (((x)<<1) ^ ((((x)>>7) & 1) * 0x1b))
-#define FD(x)  (((x) >> 1) ^ (((x) & 1) ? 0x8d : 0))
-
-#define BACK_TO_TABLES
-#ifdef BACK_TO_TABLES
-
-const uint8_t sbox[256] = {
-    0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
-    0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
-    0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
-    0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
-    0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
-    0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
-    0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
-    0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
-    0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
-    0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
-    0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
-    0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
-    0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
-    0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
-    0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
-    0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
-    0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
-    0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
-    0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
-    0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
-    0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
-    0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
-    0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
-    0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
-    0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
-    0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
-    0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
-    0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
-    0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
-    0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
-    0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
-    0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
-};
-const uint8_t sboxinv[256] = {
-    0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
-    0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
-    0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87,
-    0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
-    0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d,
-    0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
-    0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2,
-    0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
-    0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16,
-    0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
-    0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda,
-    0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
-    0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,
-    0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
-    0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02,
-    0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
-    0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea,
-    0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
-    0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85,
-    0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
-    0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89,
-    0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
-    0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20,
-    0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
-    0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31,
-    0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
-    0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d,
-    0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
-    0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0,
-    0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
-    0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26,
-    0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
-};
-
-#define rj_sbox(x)     sbox[(x)]
-#define rj_sbox_inv(x) sboxinv[(x)]
-
-#else /* tableless subroutines */
-
-/* -------------------------------------------------------------------------- */
-uint8_t gf_alog(uint8_t x) // calculate anti-logarithm gen 3
-{
-    uint8_t atb = 1, z;
-
-    while (x--) {z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z;}
-
-    return atb;
-} /* gf_alog */
-
-/* -------------------------------------------------------------------------- */
-uint8_t gf_log(uint8_t x) // calculate logarithm gen 3
-{
-    uint8_t atb = 1, i = 0, z;
-
-    do {
-        if (atb == x) break;
-        z = atb; atb <<= 1; if (z & 0x80) atb^= 0x1b; atb ^= z;
-    } while (++i > 0);
-
-    return i;
-} /* gf_log */
-
-
-/* -------------------------------------------------------------------------- */
-uint8_t gf_mulinv(uint8_t x) // calculate multiplicative inverse
-{
-    return (x) ? gf_alog(255 - gf_log(x)) : 0;
-} /* gf_mulinv */
-
-/* -------------------------------------------------------------------------- */
-uint8_t rj_sbox(uint8_t x)
-{
-    uint8_t y, sb;
-
-    sb = y = gf_mulinv(x);
-    y = (y<<1)|(y>>7); sb ^= y;  y = (y<<1)|(y>>7); sb ^= y;
-    y = (y<<1)|(y>>7); sb ^= y;  y = (y<<1)|(y>>7); sb ^= y;
-
-    return (sb ^ 0x63);
-} /* rj_sbox */
-
-/* -------------------------------------------------------------------------- */
-uint8_t rj_sbox_inv(uint8_t x)
-{
-    uint8_t y, sb;
-
-    y = x ^ 0x63;
-    sb = y = (y<<1)|(y>>7);
-    y = (y<<2)|(y>>6); sb ^= y; y = (y<<3)|(y>>5); sb ^= y;
-
-    return gf_mulinv(sb);
-} /* rj_sbox_inv */
-
-#endif
-
-/* -------------------------------------------------------------------------- */
-uint8_t rj_xtime(uint8_t x)
-{
-    return (x & 0x80) ? ((x << 1) ^ 0x1b) : (x << 1);
-} /* rj_xtime */
-
-/* -------------------------------------------------------------------------- */
-void aes_subBytes(uint8_t *buf)
-{
-    register uint8_t i = 16;
-
-    while (i--) buf[i] = rj_sbox(buf[i]);
-} /* aes_subBytes */
-
-/* -------------------------------------------------------------------------- */
-void aes_subBytes_inv(uint8_t *buf)
-{
-    register uint8_t i = 16;
-
-    while (i--) buf[i] = rj_sbox_inv(buf[i]);
-} /* aes_subBytes_inv */
-
-/* -------------------------------------------------------------------------- */
-void aes_addRoundKey(uint8_t *buf, uint8_t *key)
-{
-    register uint8_t i = 16;
-
-    while (i--) buf[i] ^= key[i];
-} /* aes_addRoundKey */
-
-/* -------------------------------------------------------------------------- */
-void aes_addRoundKey_cpy(uint8_t *buf, uint8_t *key, uint8_t *cpk)
-{
-    register uint8_t i = 16;
-
-    while (i--)  buf[i] ^= (cpk[i] = key[i]), cpk[16+i] = key[16 + i];
-} /* aes_addRoundKey_cpy */
-
-
-/* -------------------------------------------------------------------------- */
-void aes_shiftRows(uint8_t *buf)
-{
-    register uint8_t i, j; /* to make it potentially parallelable :) */
-
-    i = buf[1]; buf[1] = buf[5]; buf[5] = buf[9]; buf[9] = buf[13]; buf[13] = i;
-    i = buf[10]; buf[10] = buf[2]; buf[2] = i;
-    j = buf[3]; buf[3] = buf[15]; buf[15] = buf[11]; buf[11] = buf[7]; buf[7] = j;
-    j = buf[14]; buf[14] = buf[6]; buf[6]  = j;
-
-} /* aes_shiftRows */
-
-/* -------------------------------------------------------------------------- */
-void aes_shiftRows_inv(uint8_t *buf)
-{
-    register uint8_t i, j; /* same as above :) */
-
-    i = buf[1]; buf[1] = buf[13]; buf[13] = buf[9]; buf[9] = buf[5]; buf[5] = i;
-    i = buf[2]; buf[2] = buf[10]; buf[10] = i;
-    j = buf[3]; buf[3] = buf[7]; buf[7] = buf[11]; buf[11] = buf[15]; buf[15] = j;
-    j = buf[6]; buf[6] = buf[14]; buf[14] = j;
-
-} /* aes_shiftRows_inv */
-
-/* -------------------------------------------------------------------------- */
-void aes_mixColumns(uint8_t *buf)
-{
-    register uint8_t i, a, b, c, d, e;
-
-    for (i = 0; i < 16; i += 4)
-    {
-        a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3];
-        e = a ^ b ^ c ^ d;
-        buf[i] ^= e ^ rj_xtime(a^b);   buf[i+1] ^= e ^ rj_xtime(b^c);
-        buf[i+2] ^= e ^ rj_xtime(c^d); buf[i+3] ^= e ^ rj_xtime(d^a);
-    }
-} /* aes_mixColumns */
-
-/* -------------------------------------------------------------------------- */
-void aes_mixColumns_inv(uint8_t *buf)
-{
-    register uint8_t i, a, b, c, d, e, x, y, z;
-
-    for (i = 0; i < 16; i += 4)
-    {
-        a = buf[i]; b = buf[i + 1]; c = buf[i + 2]; d = buf[i + 3];
-        e = a ^ b ^ c ^ d;
-        z = rj_xtime(e);
-        x = e ^ rj_xtime(rj_xtime(z^a^c));  y = e ^ rj_xtime(rj_xtime(z^b^d));
-        buf[i] ^= x ^ rj_xtime(a^b);   buf[i+1] ^= y ^ rj_xtime(b^c);
-        buf[i+2] ^= x ^ rj_xtime(c^d); buf[i+3] ^= y ^ rj_xtime(d^a);
-    }
-} /* aes_mixColumns_inv */
-
-/* -------------------------------------------------------------------------- */
-void aes_expandEncKey(uint8_t *k, uint8_t *rc)
-{
-    register uint8_t i;
-
-    k[0] ^= rj_sbox(k[29]) ^ (*rc);
-    k[1] ^= rj_sbox(k[30]);
-    k[2] ^= rj_sbox(k[31]);
-    k[3] ^= rj_sbox(k[28]);
-    *rc = F( *rc);
-
-    for(i = 4; i < 16; i += 4)  k[i] ^= k[i-4],   k[i+1] ^= k[i-3],
-        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
-    k[16] ^= rj_sbox(k[12]);
-    k[17] ^= rj_sbox(k[13]);
-    k[18] ^= rj_sbox(k[14]);
-    k[19] ^= rj_sbox(k[15]);
-
-    for(i = 20; i < 32; i += 4) k[i] ^= k[i-4],   k[i+1] ^= k[i-3],
-        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
-
-} /* aes_expandEncKey */
-
-/* -------------------------------------------------------------------------- */
-void aes_expandDecKey(uint8_t *k, uint8_t *rc)
-{
-    uint8_t i;
-
-    for(i = 28; i > 16; i -= 4) k[i+0] ^= k[i-4], k[i+1] ^= k[i-3],
-        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
-
-    k[16] ^= rj_sbox(k[12]);
-    k[17] ^= rj_sbox(k[13]);
-    k[18] ^= rj_sbox(k[14]);
-    k[19] ^= rj_sbox(k[15]);
-
-    for(i = 12; i > 0; i -= 4)  k[i+0] ^= k[i-4], k[i+1] ^= k[i-3],
-        k[i+2] ^= k[i-2], k[i+3] ^= k[i-1];
-
-    *rc = FD(*rc);
-    k[0] ^= rj_sbox(k[29]) ^ (*rc);
-    k[1] ^= rj_sbox(k[30]);
-    k[2] ^= rj_sbox(k[31]);
-    k[3] ^= rj_sbox(k[28]);
-} /* aes_expandDecKey */
-
-
-/* -------------------------------------------------------------------------- */
-void aes256_init(aes256_context *ctx, uint8_t *k)
-{
-    uint8_t rcon = 1;
-    register uint8_t i;
-
-    for (i = 0; i < sizeof(ctx->key); i++) ctx->enckey[i] = ctx->deckey[i] = k[i];
-    for (i = 8;--i;) aes_expandEncKey(ctx->deckey, &rcon);
-} /* aes256_init */
-
-/* -------------------------------------------------------------------------- */
-void aes256_done(aes256_context *ctx)
-{
-    register uint8_t i;
-
-    for (i = 0; i < sizeof(ctx->key); i++)
-        ctx->key[i] = ctx->enckey[i] = ctx->deckey[i] = 0;
-} /* aes256_done */
-
-/* -------------------------------------------------------------------------- */
-void aes256_encrypt_ecb(aes256_context *ctx, uint8_t *buf)
-{
-    uint8_t i, rcon;
-
-    aes_addRoundKey_cpy(buf, ctx->enckey, ctx->key);
-    for(i = 1, rcon = 1; i < 14; ++i)
-    {
-        aes_subBytes(buf);
-        aes_shiftRows(buf);
-        aes_mixColumns(buf);
-        if( i & 1 ) aes_addRoundKey( buf, &ctx->key[16]);
-        else aes_expandEncKey(ctx->key, &rcon), aes_addRoundKey(buf, ctx->key);
-    }
-    aes_subBytes(buf);
-    aes_shiftRows(buf);
-    aes_expandEncKey(ctx->key, &rcon);
-    aes_addRoundKey(buf, ctx->key);
-} /* aes256_encrypt */
-
-/* -------------------------------------------------------------------------- */
-void aes256_decrypt_ecb(aes256_context *ctx, uint8_t *buf)
-{
-    uint8_t i, rcon;
-
-    aes_addRoundKey_cpy(buf, ctx->deckey, ctx->key);
-    aes_shiftRows_inv(buf);
-    aes_subBytes_inv(buf);
-
-    for (i = 14, rcon = 0x80; --i;)
-    {
-        if( ( i & 1 ) )
-        {
-            aes_expandDecKey(ctx->key, &rcon);
-            aes_addRoundKey(buf, &ctx->key[16]);
-        }
-        else aes_addRoundKey(buf, ctx->key);
-        aes_mixColumns_inv(buf);
-        aes_shiftRows_inv(buf);
-        aes_subBytes_inv(buf);
-    }
-    aes_addRoundKey( buf, ctx->key);
-} /* aes256_decrypt */
diff --git a/lib/CPUs/MIPS/bsp/examples/aes256.h b/lib/CPUs/MIPS/bsp/examples/aes256.h
deleted file mode 100644
index c5a22ba..0000000
--- a/lib/CPUs/MIPS/bsp/examples/aes256.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*  
-*   Byte-oriented AES-256 implementation.
-*   All lookup tables replaced with 'on the fly' calculations. 
-*
-*   Copyright (c) 2007-2009 Ilya O. Levin, http://www.literatecode.com
-*   Other contributors: Hal Finney
-*
-*   Permission to use, copy, modify, and distribute this software for any
-*   purpose with or without fee is hereby granted, provided that the above
-*   copyright notice and this permission notice appear in all copies.
-*
-*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-#ifndef uint8_t
-#define uint8_t  unsigned char
-#endif
-
-#ifdef __cplusplus
-extern "C" { 
-#endif
-
-    typedef struct {
-        uint8_t key[32]; 
-        uint8_t enckey[32]; 
-        uint8_t deckey[32];
-    } aes256_context; 
-
-
-    void aes256_init(aes256_context *, uint8_t * /* key */);
-    void aes256_done(aes256_context *);
-    void aes256_encrypt_ecb(aes256_context *, uint8_t * /* plaintext */);
-    void aes256_decrypt_ecb(aes256_context *, uint8_t * /* cipertext */);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/lib/CPUs/MIPS/bsp/examples/aes256_1.c b/lib/CPUs/MIPS/bsp/examples/aes256_1.c
deleted file mode 100644
index 8a987b8..0000000
--- a/lib/CPUs/MIPS/bsp/examples/aes256_1.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
-*   Byte-oriented AES-256 implementation.
-*   All lookup tables replaced with 'on the fly' calculations.
-*
-*   Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com
-*
-*   Permission to use, copy, modify, and distribute this software for any
-*   purpose with or without fee is hereby granted, provided that the above
-*   copyright notice and this permission notice appear in all copies.
-*
-*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-#include <stdlib.h>
-#include <stdio.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-#include "aes256.h"
-
-#ifndef NUM_BLOCKS
-#define	NUM_BLOCKS	10000
-#endif
-
-#define DUMP(s, i, buf, sz)  {printf(s);                   \
-                              for (i = 0; i < (sz);i++)    \
-                                  printf("%02x ", buf[i]); \
-                              printf("\n");}
-
-
-int main (int argc, char *argv[])
-{
-    aes256_context ctx;
-    uint8_t key[32];
-    uint8_t buf[16], i;
-	long start, end, j;
-
-    /* put a test vector */
-    for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i;
-    for (i = 0; i < sizeof(key);i++) key[i] = i;
-
-    DUMP("txt: ", i, buf, sizeof(buf));
-    DUMP("key: ", i, key, sizeof(key));
-    printf("---\n");
-
-    aes256_init(&ctx, key);
-	start = clock();
-	for (j=0; j < NUM_BLOCKS; j++)
-	{
-	    aes256_encrypt_ecb(&ctx, buf);
-  	}
-	end = clock();
-    DUMP("enc: ", i, buf, sizeof(buf));
-
-	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
-
-    aes256_init(&ctx, key);
-	start = clock();
-	for (j=0; j < NUM_BLOCKS; j++)
-	{
-	    aes256_decrypt_ecb(&ctx, buf);
-  	}
-	end = clock();
-    DUMP("dec: ", i, buf, sizeof(buf));
-
-	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
-
-    aes256_done(&ctx);
-
-    return 0;
-} /* main */
diff --git a/lib/CPUs/MIPS/bsp/examples/barcode.c b/lib/CPUs/MIPS/bsp/examples/barcode.c
deleted file mode 100644
index e1dc1bc..0000000
--- a/lib/CPUs/MIPS/bsp/examples/barcode.c
+++ /dev/null
@@ -1,358 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-
-#define	CPU_FREQ_HZ	100000000
-#include "libsys.h"
-#include "irq.h"
-
-UINT32 buffer[16384];
-
-#define	T_SAMPLE		5000
-#define	TIMEOUT			1000
-
-typedef struct _bar_t
-{
-	UINT32 T;
-	UINT32 black;
-} bar_t;
-
-enum
-{
-	state_idle = 0,
-	state_sample,
-	state_finish
-};
-
-typedef struct _sbar_cand_t
-{
-	UINT32 T;
-	UINT32 is_primitive;
-} bar_cand_t;
-
-bar_t bars[1024];
-
-void bsort(float *pData, UINT32 len)
-{
-	float t;
-	int i, j;
-
-	for(i=len-1; i>=0; i--)
-	{
-		for(j=1; j<len; j++)
-		{
-			if (pData[j-1] > pData[j])
-			{
-				t = pData[j-1];
-				pData[j-1] = pData[j];
-				pData[j] = t;
-			}
-		}
-	}
-}
-
-typedef struct _smedian_t
-{
-	UINT32 N;
-	UINT32 is_dirty;
-	float *pBuf, *pSorted;
-	UINT32 w;
-	float median;
-} median_t;
-
-void Median_init(median_t *pObj, UINT32 N, float init_val)
-{
-	int i;
-	pObj->pBuf = (float*)malloc(N*sizeof(float));
-	pObj->pSorted = (float*)malloc(N*sizeof(float));
-	for (i=0; i < N; i++)
-		pObj->pBuf[0] = init_val;
-	pObj->median = init_val;
-	pObj->is_dirty = 0;
-	pObj->w = 0;
-	pObj->N = N;
-}
-
-void Median_free(median_t *pObj)
-{
-	if (pObj->pBuf)
-		free(pObj->pBuf);
-
-	if (pObj->pSorted)
-		free(pObj->pSorted);
-
-	pObj->pBuf = NULL;
-	pObj->pSorted = NULL;
-
-}
-
-void Median_value_add(median_t *pObj, float value)
-{
-	pObj->is_dirty = 1;
-	pObj->pBuf[pObj->w++] = value;
-
-	if (pObj->w == pObj->N)
-		pObj->w = 0;
-
-}
-
-float Median_get(median_t *pObj)
-{
-	if (!pObj->is_dirty)
-		return pObj->median;
-
-	memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float));
-
-	bsort(pObj->pSorted, pObj->N);
-
-	if (pObj->N&1)
-	{
-		pObj->median = pObj->pSorted[(pObj->N-1)/2];
-	}
-	else
-	{
-		pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]);
-	}
-
-	pObj->is_dirty = 0;
-
-	return pObj->median;
-}
-
-// -------------------------------------------------------------
-UINT32 detect_module(UINT32 T, UINT32 T0)
-{
-	UINT32 m, best_M;
-	float err, kc, best_err;
-
-	best_err = 4.f;
-	best_M = 0;
-
-	for (m=1; m < 5; m++)
-	{
-		kc = (float)T/(m*T0);
-		err = fabs(kc - 1);
-
-		if (err < best_err)
-		{
-			best_M = m;
-			best_err = err;
-		}
-	}
-
-	return best_M;
-}
-
-void handler7(void)
-{
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT;
-	UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT;
-	static UINT32 state, bar_count;
-	static UINT32 timeout_count, timeout_reload;
-	static UINT32 white, pin_last, skip, start;
-	static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0;
-	float ratio, error, kc;
-	UINT32 i;
-	static median_t med_b, med_w;
-	static bar_cand_t bc_b, bc_w;
-	static median_t speed_b, speed_w;
-
-	if (*pTim_stat & 1)
-	{
-		*pTim_stat = 1;
-		white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0);
-
-		switch (state)
-		{
-			case state_idle:
-			timeout_reload = TIMEOUT;
-			if (white != pin_last)
-			{
-				if (white)
-					break;
-
-				state = state_sample;
-				module_cnt_b = 0;
-				module_cnt_w = 0;
-				Tmod0_w	= 0xFFFFFFFF;
-				Tmod0_b	= 0xFFFFFFFF;
-				bar_count = 0;
-				Median_init(&med_b, 3, 0);
-				Median_init(&med_w, 3, 0);
-				Median_init(&speed_b, 3, 1);
-				Median_init(&speed_w, 3, 1);
-			}
-			break;
-
-			case state_sample:
-			if (!timeout_count)
-			{
-				state = state_finish;
-				break;
-			}
-
-			if (white)
-			{
-				module_cnt_w++;
-			}
-			else
-			{
-				module_cnt_b++;
-			}
-			if (white != pin_last)
-			{
-				if (pin_last)
-				{
-					if (bar_count < 10)
-					{
-						if (1.5*module_cnt_w < Tmod0_w)
-						{
-							Tmod0_w = module_cnt_w;
-						}
-					}
-					Median_value_add(&med_w, Tmod0_w);
-
-					timeout_reload = 10*Tmod0_w;
-					bars[bar_count].T = module_cnt_w;
-					bars[bar_count].black = 0;
-					module_cnt_w = 0;
-
-				}
-				else
-				{
-					if (bar_count < 10)
-					{
-						if (1.5*module_cnt_b < Tmod0_b)
-						{
-							Tmod0_b = module_cnt_b;
-						}
-					}
-					Median_value_add(&med_b, Tmod0_b);
-
-					timeout_reload = 10*Tmod0_b;
-					bars[bar_count].T = module_cnt_b;
-					bars[bar_count].black = 1;
-					module_cnt_b = 0;
-				}
-				bar_count++;
-
-			}
-			break;
-
-			case state_finish:
-			printf("------------------------------------------------\n");
-			printf("          Black                    White        \n");
-			skip = 0;
-			start = 1;
-			Tmod0_w = Median_get(&med_w);
-			Tmod0_b = Median_get(&med_b);
-			for (i=0; i < bar_count; i++)
-			{
-				if (bars[i].black)
-				{
-					T0 = Median_get(&med_b);
-					ratio = (float)bars[i].T/T0;
-					if (start)
-					{
-						if (ratio > 4)
-						{
-							skip = 1;
-							continue;
-						}
-					}
-					start = 0;
-					skip = 0;
-					M = detect_module(bars[i].T, T0);
-					kc = (float)bars[i].T/(M*T0);
-					error = kc - 1;
-
-//					printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0);
-//					if (M == 1)
-					Median_value_add(&med_b, (UINT32)(T0*kc));
-					Median_value_add(&speed_b, (float)bars[i].T/(M*Tmod0_b));
-
-					printf("%06d %2.6f ", bars[i].T, Median_get(&speed_b));
-
-				}
-				else
-				{
-					if (skip)
-						continue;
-
-					T0 = Median_get(&med_w);
-					ratio = (float)bars[i].T/T0;
-					if (ratio > 9)
-					{
-						start = 1;
-//						printf("\n");
-//						printf("------------------------------------------------\n");
-//						printf("          Black                    White        \n");
-						continue;
-					}
-
-
-					M = detect_module(bars[i].T, T0);
-					kc = (float)bars[i].T/(M*T0);
-					error = kc - 1;
-
-//					printf("          M=%d, R=%2.2f, E=%+2.2f [%04d]", M, ratio, error, T0);
-//					if (M == 1)
-					Median_value_add(&med_w, (UINT32)(T0*kc));
-					Median_value_add(&speed_w, (float)bars[i].T/(M*Tmod0_w));
-
-					printf("%06d %2.6f ", bars[i].T, Median_get(&speed_w));
-					printf("\n");
-				}
-			}
-			Median_free(&med_b);
-			Median_free(&med_w);
-			Median_free(&speed_b);
-			Median_free(&speed_w);
-			if (bar_count)
-				printf("\n");
-
-			state = state_idle;
-			break;
-
-		}
-		if (white != pin_last)
-			timeout_count = timeout_reload;
-
-		pin_last = white;
-		if (timeout_count)
-			timeout_count--;
-
-	}
-}
-
-int main(void)
-{
-
-	int i;
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
-	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
-
-	*pTim0_cnt = 0;
-	*pTim0_cmp = (UINT32)T_SAMPLE;
-	*pTim_stat = 1;
-	*pTim_ctrl = 3;
-
-	interrupt_register(7, (void*)handler7);
-
-	printf("Jenners BarCoder\n");
-
-	interrupt_enable(7);
-
-	while(1)
-	{
-	}
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/barcode.new.c b/lib/CPUs/MIPS/bsp/examples/barcode.new.c
deleted file mode 100644
index 06f1152..0000000
--- a/lib/CPUs/MIPS/bsp/examples/barcode.new.c
+++ /dev/null
@@ -1,322 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-
-#define	CPU_FREQ_HZ	100000000
-#include "libsys.h"
-#include "irq.h"
-
-UINT32 buffer[16384];
-
-#define	T_SAMPLE		5000
-#define	TIMEOUT			1000
-
-typedef struct _bar_t
-{
-	UINT32 T;
-	UINT32 black;
-} bar_t;
-
-enum
-{
-	state_idle = 0,
-	state_sample,
-	state_finish
-};
-
-bar_t bars[1024];
-
-void bsort(float *pData, UINT32 len)
-{
-	float t;
-	int i, j;
-
-	for(i=len-1; i>=0; i--)
-	{
-		for(j=1; j<len; j++)
-		{
-			if (pData[j-1] > pData[j])
-			{
-				t = pData[j-1];
-				pData[j-1] = pData[j];
-				pData[j] = t;
-			}
-		}
-	}
-}
-
-typedef struct _smedian_t
-{
-	UINT32 N;
-	UINT32 is_dirty;
-	float *pBuf, *pSorted;
-	UINT32 w;
-	float median;
-} median_t;
-
-void Median_init(median_t *pObj, UINT32 N, float init_val)
-{
-	int i;
-	pObj->pBuf = (float*)malloc(N*sizeof(float));
-	pObj->pSorted = (float*)malloc(N*sizeof(float));
-	for (i=0; i < N; i++)
-		pObj->pBuf[0] = init_val;
-	pObj->median = init_val;
-	pObj->is_dirty = 0;
-	pObj->w = 0;
-	pObj->N = N;
-}
-
-void Median_free(median_t *pObj)
-{
-	if (pObj->pBuf)
-		free(pObj->pBuf);
-
-	if (pObj->pSorted)
-		free(pObj->pSorted);
-
-	pObj->pBuf = NULL;
-	pObj->pSorted = NULL;
-
-}
-
-void Median_value_add(median_t *pObj, float value)
-{
-	pObj->is_dirty = 1;
-	pObj->pBuf[pObj->w++] = value;
-
-	if (pObj->w == pObj->N)
-		pObj->w = 0;
-
-}
-
-float Median_get(median_t *pObj)
-{
-	if (!pObj->is_dirty)
-		return pObj->median;
-
-	memcpy(pObj->pSorted, pObj->pBuf, pObj->N*sizeof(float));
-
-	bsort(pObj->pSorted, pObj->N);
-
-	if (pObj->N&1)
-	{
-		pObj->median = pObj->pSorted[(pObj->N-1)/2];
-	}
-	else
-	{
-		pObj->median = 0.5f*(pObj->pSorted[pObj->N/2] + pObj->pSorted[pObj->N/2+1]);
-	}
-
-	pObj->is_dirty = 0;
-
-	return pObj->median;
-}
-
-// -------------------------------------------------------------
-UINT32 detect_module(UINT32 T, UINT32 *pBC)
-{
-	UINT32 m, best_M;
-	float err, kc, best_err;
-
-	best_err = 4.f;
-	best_M = 0;
-
-	for (m=0; m < 4; m++)
-	{
-		kc = (float)T/pBC[m];
-		err = fabs(kc - 1);
-
-		if (err < best_err)
-		{
-			best_M = m+1;
-			best_err = err;
-		}
-	}
-
-	return best_M;
-}
-
-void handler7(void)
-{
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pPS20_stat = (UINT32*)SYS_PS2_0_STAT;
-	UINT32 volatile *pPS21_stat = (UINT32*)SYS_PS2_1_STAT;
-	static UINT32 state, bar_count;
-	static UINT32 timeout_count, timeout_reload;
-	static UINT32 white, pin_last, skip, start;
-	static UINT32 module_cnt_w, module_cnt_b, Tmod0_w, Tmod0_b, M, T0;
-	float ratio, error, kc;
-	UINT32 i, j;
-	static median_t med_b, med_w;
-	static UINT32 bc_b[4], bc_w[4];
-
-	if (*pTim_stat & 1)
-	{
-		*pTim_stat = 1;
-		white = ((*pPS20_stat & SYS_PS2_BIT_PIN_DATA) == 0);
-
-		switch (state)
-		{
-			case state_idle:
-			timeout_reload = TIMEOUT;
-			if (white != pin_last)
-			{
-				if (white)
-					break;
-
-				state = state_sample;
-				module_cnt_b = 0;
-				module_cnt_w = 0;
-				Tmod0_w	= 0xFFFFFFFF;
-				Tmod0_b	= 0xFFFFFFFF;
-				bar_count = 0;
-				Median_init(&med_b, 3, 1);
-				Median_init(&med_w, 3, 1);
-			}
-			break;
-
-			case state_sample:
-			if (!timeout_count)
-			{
-				state = state_finish;
-				break;
-			}
-
-			if (white)
-			{
-				module_cnt_w++;
-			}
-			else
-			{
-				module_cnt_b++;
-			}
-			if (white != pin_last)
-			{
-				if (pin_last)
-				{
-					if (bar_count < 10)
-					{
-						if (1.5*module_cnt_w < Tmod0_w)
-						{
-							Tmod0_w = module_cnt_w;
-						}
-					}
-					timeout_reload = 10*Tmod0_w;
-					bars[bar_count].T = module_cnt_w;
-					bars[bar_count].black = 0;
-					module_cnt_w = 0;
-
-				}
-				else
-				{
-					if (bar_count < 10)
-					{
-						if (1.5*module_cnt_b < Tmod0_b)
-						{
-							Tmod0_b = module_cnt_b;
-						}
-					}
-					timeout_reload = 10*Tmod0_b;
-					bars[bar_count].T = module_cnt_b;
-					bars[bar_count].black = 1;
-					module_cnt_b = 0;
-				}
-				bar_count++;
-
-			}
-			break;
-
-			case state_finish:
-			printf("------------------------------------------------\n");
-			printf("          Black                    White        \n");
-			skip = 0;
-			start = 1;
-			for (i=0; i < 4; i++)
-			{
-				bc_b[i] = (i+1)*Tmod0_b;
-				bc_w[i] = (i+1)*Tmod0_w;
-			}
-			for (i=0; i < bar_count; i++)
-			{
-				if (bars[i].black)
-				{
-					M = detect_module(bars[i].T, bc_b);
-					if (M)
-					{
-						kc = (float)bars[i].T/bc_b[M-1];
-						error = kc - 1;
-						Median_value_add(&med_b, kc);
-						printf("M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_b[M-1]);
-						kc = Median_get(&med_b);
-						bc_b[M-1] = (UINT32)(kc*bc_b[M-1]);
-					}
-//					printf("%d", M);
-
-				}
-				else
-				{
-					M = detect_module(bars[i].T, bc_w);
-					if (M)
-					{
-						kc = (float)bars[i].T/bc_w[M-1];
-						error = kc - 1;
-						Median_value_add(&med_w, kc);
-						printf("          M=%d, R=%2.2f, E=%+2.2f [%04d]", M, kc, error, bc_w[M-1]);
-						kc = Median_get(&med_w);
-						bc_w[M-1] = (UINT32)(kc*bc_w[M-1]);
-
-					}
-//					printf("%d", M);
-					printf("\n");
-				}
-			}
-			Median_free(&med_b);
-			Median_free(&med_w);
-			if (bar_count)
-				printf("\n");
-
-			state = state_idle;
-			break;
-
-		}
-		if (white != pin_last)
-			timeout_count = timeout_reload;
-
-		pin_last = white;
-		if (timeout_count)
-			timeout_count--;
-
-	}
-}
-
-int main(void)
-{
-
-	int i;
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
-	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
-
-	*pTim0_cnt = 0;
-	*pTim0_cmp = (UINT32)T_SAMPLE;
-	*pTim_stat = 1;
-	*pTim_ctrl = 3;
-
-	interrupt_register(7, (void*)handler7);
-
-	printf("Jenners BarCoder\n");
-
-	interrupt_enable(7);
-
-	while(1)
-	{
-	}
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/basicmath_small.c b/lib/CPUs/MIPS/bsp/examples/basicmath_small.c
deleted file mode 100644
index 049fea2..0000000
--- a/lib/CPUs/MIPS/bsp/examples/basicmath_small.c
+++ /dev/null
@@ -1,84 +0,0 @@
-#include "snipmath.h"
-#include <math.h>
-
-/* The printf's may be removed to isolate just the math calculations */
-
-int main(void)
-{
-  double  a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0;
-  double  a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0;
-  double  a3 = 1.0, b3 = -3.5, c3 = 22.0, d3 = -31.0;
-  double  a4 = 1.0, b4 = -13.7, c4 = 1.0, d4 = -35.0;
-  double  x[3];
-  double X;
-  int     solutions;
-  int i;
-  unsigned long l = 0x3fed0169L;
-  struct int_sqrt q;
-  long n = 0;
-
-  /* solve soem cubic functions */
-  printf("********* CUBIC FUNCTIONS ***********\n");
-  /* should get 3 solutions: 2, 6 & 2.5   */
-  SolveCubic(a1, b1, c1, d1, &solutions, x);  
-  printf("Solutions:");
-  for(i=0;i<solutions;i++)
-    printf(" %f",x[i]);
-  printf("\n");
-  /* should get 1 solution: 2.5           */
-  SolveCubic(a2, b2, c2, d2, &solutions, x);  
-  printf("Solutions:");
-  for(i=0;i<solutions;i++)
-    printf(" %f",x[i]);
-  printf("\n");
-  SolveCubic(a3, b3, c3, d3, &solutions, x);
-  printf("Solutions:");
-  for(i=0;i<solutions;i++)
-    printf(" %f",x[i]);
-  printf("\n");
-  SolveCubic(a4, b4, c4, d4, &solutions, x);
-  printf("Solutions:");
-  for(i=0;i<solutions;i++)
-    printf(" %f",x[i]);
-  printf("\n");
-  /* Now solve some random equations */
-  for(a1=1;a1<10;a1++) {
-    for(b1=10;b1>0;b1--) {
-      for(c1=5;c1<15;c1+=0.5) {
-	for(d1=-1;d1>-11;d1--) {
-	  SolveCubic(a1, b1, c1, d1, &solutions, x);  
-	  printf("Solutions:");
-	  for(i=0;i<solutions;i++)
-	    printf(" %f",x[i]);
-	  printf("\n");
-	}
-      }
-    }
-  }
-  
-  printf("********* INTEGER SQR ROOTS ***********\n");
-  /* perform some integer square roots */
-  for (i = 0; i < 1001; ++i)
-    {
-      usqrt(i, &q);
-			// remainder differs on some machines
-     // printf("sqrt(%3d) = %2d, remainder = %2d\n",
-     printf("sqrt(%3d) = %2d\n",
-	     i, q.sqrt);
-    }
-  usqrt(l, &q);
-  //printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac);
-  printf("\nsqrt(%lX) = %X\n", l, q.sqrt);
-
-
-  printf("********* ANGLE CONVERSION ***********\n");
-  /* convert some rads to degrees */
-  for (X = 0.0; X <= 360.0; X += 1.0)
-    printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X));
-  puts("");
-  for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 180))
-    printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X));
-  
-  
-  return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/bogomips.c b/lib/CPUs/MIPS/bsp/examples/bogomips.c
deleted file mode 100644
index e859d2f..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bogomips.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * bogomips.c -- Program to measure bogomips... this program will probably go
- * totally wacky with cpufreq enabled.
- *
- * Copyright (C) 2005 Darrick Wong.
- */
-#include <stdio.h>
-#include <time.h>
-
-/* this should be approx 2 Bo*oMips to start (note initial shift), and will
- *    still work even if initially too large, it will just take slightly longer */
-unsigned long loops_per_jiffy = (1<<12);
-
-/* This is the number of bits of precision for the loops_per_jiffy.  Each
- *    bit takes on average 1.5/HZ seconds.  This (like the original) is a little
- *       better than 1% */
-#define LPS_PREC 8
-
-extern void delay(unsigned int loops);
-
-//plagiarized straight from the 2.4 sources.
-#ifdef NOMAIN
-int calibrate_delay(void)
-#else
-int main(void)
-#endif
-{
-        unsigned long ticks, loopbit;
-        int lps_precision = LPS_PREC;
-
-        loops_per_jiffy = (1<<12);
-
-        printf("Calibrating delay loop... ");
-        while (loops_per_jiffy <<= 1) {
-                /* wait for "start of" clock tick */
-                ticks = clock();
-                while (ticks == clock())
-                        /* nothing */;
-                /* Go .. */
-                ticks = clock();
-                delay(loops_per_jiffy);
-                ticks = clock() - ticks;
-                if (ticks)
-                        break;
-        }
-
-/* Do a binary approximation to get loops_per_jiffy set to equal one clock
-   (up to lps_precision bits) */
-
-       loops_per_jiffy >>= 1;
-        loopbit = loops_per_jiffy;
-        while ( lps_precision-- && (loopbit >>= 1) ) {
-                loops_per_jiffy |= loopbit;
-                ticks = clock();
-                while (ticks == clock());
-                ticks = clock();
-                delay(loops_per_jiffy);
-                if (clock() != ticks)   /* longer than 1 tick */
-                        loops_per_jiffy &= ~loopbit;
-        }
-
-
-/* Round the value and print it */
-        printf("%lu.%02lu BogoMIPS\n",
-                loops_per_jiffy/(500000/HZ),
-                (loops_per_jiffy/(5000/HZ)) % 100);
-
-
-		return loops_per_jiffy;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile b/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile
deleted file mode 100644
index 513a332..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-ENDIAN='big'
-
-ifeq ($(ENDIAN), 'big')
-  ENDIAN_FLAGS=-EB
-  LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib/eb -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)/eb
-else
-  ENDIAN_FLAGS=-EL
-  LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)
-endif
-
-CFLAGS=$(ENDIAN_FLAGS) -Os -I. -I../ -I../libsys -msoft-float -march=r3000
-LFLAGS=$(ENDIAN_FLAGS) -M -T bootloader.ld
-
-LIBS=-lc -lgcc
-
-CC=mipsel-elf-gcc
-LD=mipsel-elf-ld
-OBJDUMP=mipsel-elf-objdump
-OBJCOPY=mipsel-elf-objcopy
-
-all: bootloader_flash
-
-libsys: startup_boot.S init_boot.S kernel_boot.S libsys_boot.c
-	$(CC) $(CFLAGS) -c startup_boot.S -o startup.o
-	$(CC) $(CFLAGS) -c init_boot.S -o init.o
-	$(CC) $(CFLAGS) -c kernel_boot.S -o kernel.o
-	$(CC) $(CFLAGS) -c libsys_boot.c -o libsys.o
-
-bootloader: libsys bootloader.c 
-	$(CC) $(CFLAGS) -g -c bootloader.c
-	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o bootloader.o -o bootloader.elf $(LIBS) >bootloader.map
-	$(OBJDUMP) -d bootloader.elf > bootloader.dis
-	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
-	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	romgen bootloader.ROM.bin 10 $(ENDIAN_FLAGS)
-
-bootloader_flash: libsys bootloader_with_flash.c 
-	$(CC) $(CFLAGS) -g -c bootloader_with_flash.c
-	$(CC) $(CFLAGS) -g -c ../cfiflash.c
-	$(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o cfiflash.o bootloader_with_flash.o -o bootloader.elf $(LIBS) >bootloader.map
-	$(OBJDUMP) -d bootloader.elf > bootloader.dis
-	$(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin
-	$(OBJCOPY) -O srec bootloader.elf bootloader.srec
-	romgen bootloader.ROM.bin 11 $(ENDIAN_FLAGS)
-
-clean:
-	rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c
deleted file mode 100644
index 7ade222..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c
+++ /dev/null
@@ -1,247 +0,0 @@
-#include "libsys_boot.h"
-
-typedef struct _ssrec_t
-{
-	UINT32 addr;
-	UINT32 size;
-	UINT32 type;
-	UINT8 *data;
-
-} srec_t;
-
-enum srec_type
-{
-	srec_err, srec_sob, srec_data, srec_rec, srec_eob
-};
-
-UINT8 h2i(UINT8 *c)
-{
-	int i;
-	UINT8 t, b = 0;
-
-	for (i=0; i < 2; i++)
-	{
-		t = c[i];
-		if (t >= 'A')
-			t = t - 'A' + 10;
-		else
-			t -= '0';
-
-		b = (b << 4) | t;
-	}
-	return b;
-}
-
-int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
-{
-	UINT8 chksum, byte;
-	int alen, i;
-
-	if (!buflen)
-		return srec_err;
-
-	pRec->type = srec_rec;
-	alen = 0;
-	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
-	{
-	  alen = pBuf[1] - '0' + 1;
-	  pRec->type = srec_data;
-	}
-	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
-	{
-	  alen = 11 - (pBuf[1] - '0');
-	  pRec->type = srec_eob;
-	}
-	else if (pBuf[1] == '0')
-	{
-	  alen = 2;
-	  pRec->type = srec_sob;
-	}
-
-	byte = h2i(&pBuf[2]);
-	pRec->size = byte;
-	chksum = byte;
-
-	pRec->addr = 0;
-	for (i=0; i < alen; i++)
-	{
-		byte = h2i(&pBuf[4+2*i]);
-        pRec->addr = pRec->addr << 8 | byte;
-		chksum += byte;
-	}
-	pRec->size -= (alen+1);
-
-	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
-	for (i=0; i < (int)pRec->size; i++)
-	{
-		byte = h2i(&pRec->data[2*i]);
-		pRec->data[i] = byte;
-		chksum += byte;
-	}
-	chksum = ~chksum;
-	byte = h2i(&pRec->data[2*i]);
-	if (chksum != byte)
-		return 0;
-
-	return pRec->type;
-}
-
-int srec_getline(UINT8 *pLine)
-{
-	char c;
-	int i = 0;
-
-	do
-	{
-		c = readchar();
-
-	} while ((c != 's') && (c != 'S'));
-
-	while(((c != 0x0D) && (c != 0x0A)))
-	{
-		pLine[i++] = c;
-		c = readchar();
-	};
-
-	return i;
-}
-
-void Jump_to(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-	__asm
-	(
-		"nop\n"
-	);
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"mfc0	$26, $12\n"			// change exception vector
-		"li		$27, 0xFFBFFFFF\n"
-		"and	$26, $27\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"lw		$v0, 16($sp)\n"
-		"nop\n"
-		"jr		$v0\n"				// jump entry
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-void PrintCPUinfo(void)
-{
-	int result, rev_id;
-
-	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
-
-	// Print Status register
-	result = CP0_SR_read();
-
-	sputs("Status  : ");
-	print_word(result);
-	sputs("\n");
-
-	// Print Revision
-	result = CP0_PRID_read();
-	rev_id = (result >> 8) & 0xFF;
-	sputs("CPU type: ");
-	if ((rev_id > 0) && (rev_id < 0x07))
-	{
-		sputs(cpu_type_str[rev_id]);
-		sputs(" Rev.");
-		rev_id = result & 0xFF;
-		print_byte((char)rev_id);
-	}
-	else
-		sputs("Unknown");
-
-	sputs("\n");
-
-}
-
-#define	MAX_IMG_SIZE		(1024*1024)	// bytes
-
-int main(int argc, char *argv[])
-{
-	UINT8 buf[256];
-	srec_t srec;
-	int result, srec_state, i;
-	UINT32 haddr;
-	volatile UINT8 *pMem;
-	haddr = 0;
-
-	// ----------------------------------------------------------
-	sputs("\n\n");
-	PrintCPUinfo();
-	sputs("Booting from UART..");
-
-	while(1)
-	{
-		sputs(".");
-		while(1)
-		{
-			result = srec_getline(buf);
-			srec_state = decode_srec(&srec, buf, result);
-			switch (srec_state)
-			{
-				case srec_data:
-					if ((srec.addr + srec.size) > haddr)
-						haddr = srec.addr + srec.size;
-
-					pMem = (UINT8*)srec.addr;
-					for (i=0; i < srec.size; i++)
-						*pMem++ = srec.data[i];
-
-					break;
-
-				case srec_eob:
-					sputs("done\n\n");
-					sputs("Execute program at ");
-					print_word(srec.addr);
-					sputs("\n\n");
-
-					Exec_at((void*)srec.addr);
-					break;
-
-				default:
-					result = -1;
-					break;
-			}
-			if (result < 0)
-			{
-				break;
-			}
-
-		};
-	}
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld
deleted file mode 100644
index c3cd35e..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld
+++ /dev/null
@@ -1,53 +0,0 @@
-MEMORY
-{
-  rom          : ORIGIN = 0xBFC00000, LENGTH = 0x00002000  /*   8K    */
-  ram          : ORIGIN = 0x40000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-OUTPUT_ARCH(mips)
-SEARCH_DIR(".");
-SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb");
-SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb");
-
-stack_ptr = 0x7FFFEFF0;
-baudrate = 0x0D;
-sys_led_port = 0xA0000000;
-sys_uart_data = 0xA0010000;
-sys_uart_stat = 0xA0010004;
-sys_uart_baud = 0xA0010008;
-sys_timer_usec = 0xA000008;
-sys_timer_sec = 0xA000000C;
-
-
-SECTIONS
-{
-   .init ORIGIN(rom) :
-   {
-      start = ALIGN(4);
-      entry = ALIGN(4);
-      _entry = ALIGN(4);
-      __entry = ALIGN(4);
-     *(.stext)
-   }  > rom
-   
-   .ktext ORIGIN(rom) + 0x180 :
-   {
-     *(.ktext)
-   }  > rom
-
-   .text . :
-   {
-     *(.text)
-   }  > rom
-
-   .rodata . :
-   {
-     *(.rodata*)
-   }  > rom
-
-   .data ORIGIN(ram) :
-   {
-     *(.*data) *(.*bss) *(.*common)
-   }  > ram
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c
deleted file mode 100644
index 197ab44..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c
+++ /dev/null
@@ -1,383 +0,0 @@
-#include "libsys_boot.h"
-#include "cfiflash.h"
-
-#define	MAGIC_EB	0x4A464931	// "JFI1" in big-endian;
-#define	MAGIC_EL	0x3149464A	// "JFI1" in little-endian;
-
-typedef struct _ssrec_t
-{
-	UINT32 addr;
-	UINT32 size;
-	UINT32 type;
-	UINT8 *data;
-
-} srec_t;
-typedef struct _sflash_alloc_tbl_t
-{
-	UINT32 images[16];
-
-} flash_alloc_tbl_t;
-
-typedef struct _sflash_img_hdr_t
-{
-	UINT32 magic;
-	UINT32 target_base;
-	UINT32 img_base;
-	UINT32 img_size;
-	UINT32 hdr_next;
-	UINT8 img_name[128];
-	UINT8 res[108];
-
-} flash_img_hdr_t;
-
-enum srec_type
-{
-	srec_err, srec_sob, srec_data, srec_rec, srec_eob
-};
-
-UINT8 h2i(UINT8 *c)
-{
-	int i;
-	UINT8 t, b = 0;
-
-	for (i=0; i < 2; i++)
-	{
-		t = c[i];
-		if (t >= 'A')
-			t = t - 'A' + 10;
-		else
-			t -= '0';
-
-		b = (b << 4) | t;
-	}
-	return b;
-}
-
-int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen)
-{
-	UINT8 chksum, byte;
-	int alen, i;
-
-	if (!buflen)
-		return srec_err;
-
-	pRec->type = srec_rec;
-	alen = 0;
-	if ((pBuf[1] > '0') && (pBuf[1] < '4'))
-	{
-	  alen = pBuf[1] - '0' + 1;
-	  pRec->type = srec_data;
-	}
-	else if ((pBuf[1] >= '7') && (pBuf[1] <= '9'))
-	{
-	  alen = 11 - (pBuf[1] - '0');
-	  pRec->type = srec_eob;
-	}
-	else if (pBuf[1] == '0')
-	{
-	  alen = 2;
-	  pRec->type = srec_sob;
-	}
-
-	byte = h2i(&pBuf[2]);
-	pRec->size = byte;
-	chksum = byte;
-
-	pRec->addr = 0;
-	for (i=0; i < alen; i++)
-	{
-		byte = h2i(&pBuf[4+2*i]);
-        pRec->addr = pRec->addr << 8 | byte;
-		chksum += byte;
-	}
-	pRec->size -= (alen+1);
-
-	pRec->data = (UINT8*) &pBuf[4 + 2*alen];
-	for (i=0; i < (int)pRec->size; i++)
-	{
-		byte = h2i(&pRec->data[2*i]);
-		pRec->data[i] = byte;
-		chksum += byte;
-	}
-	chksum = ~chksum;
-	byte = h2i(&pRec->data[2*i]);
-	if (chksum != byte)
-		return 0;
-
-	return pRec->type;
-}
-
-int srec_getline(UINT8 *pLine)
-{
-	char c;
-	int i = 0;
-
-	do
-	{
-		c = readchar();
-
-	} while ((c != 's') && (c != 'S'));
-
-	while(((c != 0x0D) && (c != 0x0A)))
-	{
-		pLine[i++] = c;
-		c = readchar();
-	};
-
-	return i;
-}
-
-void Jump_to(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-	__asm
-	(
-		"nop\n"
-	);
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"li		$26, 0x10000000\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-
-	__asm
-	(
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-void Exec_RE_at(void *pEntry)
-{
-	__asm
-	(
-		".set	noreorder\n"
-	);
-
-	__asm
-	(
-		"mfc0	$26, $12\n"			// change exception vector
-		"li		$27, 0xFFBFFFFF\n"
-		"and	$26, $27\n"
-		"li		$27, 0x02000000\n"	// Reverse Endianess
-		"or		$26, $27\n"
-		"mtc0	$26, $12\n"
-	);
-
-	__asm
-	(
-		"jr		%[pEntry]\n"				// jump entry
-		:
-		: [pEntry] "r" (pEntry)
-	);
-
-	__asm
-	(
-		"rfe\n"
-	);
-
-	__asm
-	(
-		".set	reorder\n"
-	);
-}
-
-#define	MAX_IMG_SIZE		(1024*1024)	// bytes
-#define SDRAM_BASE			0x40000000
-#define FLASH_USE_BLOCK		1
-
-int main(int argc, char *argv[])
-{
-	UINT8 buf[256];
-	srec_t srec;
-	int srec_state, i;
-	UINT32 haddr, result;
-	flash_t flash;
-	flash_img_hdr_t img_hdr = {0};
-	flash_img_hdr_t *pImg_hdr;
-	UINT32 img_size, block_sel;
-
-	volatile UINT32 *pLED = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pBtn = (UINT32*)SYS_GPIO0;
-	volatile UINT32 *pDip = (UINT32*)SYS_GPIO1;
-	volatile UINT8 *pMem;
-	volatile UINT32 *pFlashIO = (UINT32*)SYS_FLASH_IO;		// Flash in uncached area
-	volatile UINT32 *pFlashMem = (UINT32*)SYS_FLASH_MEM;	// Flash in cached area
-	volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE;
-	UINT32 flash_offset;
-
-	*pLED = 0;
-	haddr = 0;
-	block_sel = 0x7F & (UINT32)*pDip;
-
-	// ----------------------------------------------------------
-	if (IS_ERROR(flash_find(&flash, SYS_FLASH_IO)))
-	{
-		sputs("Cannot find flash device. Exit now!\n\n");
-		return 1;
-	}
-
-	// Get flash offset by value of DIP-switch
-	flash_offset = flash_get_offset_by_blocknum(&flash, block_sel);
-
-	ram32 = (UINT32*)(SDRAM_BASE);
-	pFlashIO = (UINT32*)(SYS_FLASH_IO + flash_offset);
-
-	if (!(*pBtn & 8))
-	{
-		sputs("\n\n");
-		pImg_hdr = (flash_img_hdr_t*)pFlashIO;
-		if ((pImg_hdr->magic != MAGIC_EL) && (pImg_hdr->magic != MAGIC_EB))
-		{
-			sputs("\n\n");
-			sputs("Invalid image found at ");print_word(flash_offset); sputs(". Abort.\n");
-			return 1;
-		}
-
-		sputs("Booting application from flash (");print_word(flash_offset);sputs(")...");
-
-		ram32 = (UINT32*)pImg_hdr->target_base;
-		img_size = pImg_hdr->img_size;
-
-		// It's safe to use cached Flash,
-		// because  D-Cache was invalidated during execution of start code
-		pFlashMem = (UINT32*)(SYS_FLASH_MEM + pImg_hdr->img_base);
-
-		for (i=0; i < img_size/4; i++)
-			ram32[i] = pFlashMem[i];
-
-		sputs("done\n");
-
-		sputs("Execute at ");print_word(pImg_hdr->target_base); sputs("\n\n");
-		Exec_at((void*)ram32);
-	}
-	else
-	{
-
-		sputs("\n\n");
-
-		sputs("Reading HEX-Record from UART..");
-
-		// Erase SDRAM
-		for (i=0; i < MAX_IMG_SIZE/4; i++)
-			ram32[i] = 0;
-
-
-		while(1)
-		{
-			sputs(".");
-			while(1)
-			{
-				result = srec_getline(buf);
-				srec_state = decode_srec(&srec, buf, result);
-				*pLED = 0;
-				switch (srec_state)
-				{
-					case srec_data:
-						if ((srec.addr + srec.size) > haddr)
-							haddr = srec.addr + srec.size;
-
-						pMem = (UINT8*)srec.addr;
-						for (i=0; i < srec.size; i++)
-							*pMem++ = srec.data[i];
-
-						break;
-
-					case srec_eob:
-						sputs("done\n\n");
-						img_hdr.magic = MAGIC_EB;
-						img_hdr.target_base = srec.addr;
-						img_hdr.img_size = haddr - srec.addr;
-						img_hdr.img_base = flash_offset + sizeof(flash_img_hdr_t);
-						img_hdr.hdr_next = flash_get_offset_blockaligned(&flash, img_hdr.img_base + img_hdr.img_size);
-						sputs("Size of application    : ");print_word(img_hdr.img_size); sputs("\n");
-						sputs("Programming flash at   : ");print_word(flash_offset); sputs("\n");
-						sputs("Next free flash offset : ");print_word(img_hdr.hdr_next); sputs("\n");
-
-						sputs("Flash erase...");
-						result = flash_erase(&flash, flash_offset, img_hdr.img_size + sizeof(flash_img_hdr_t));
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("done\n");
-
-						sputs("Flash write...");
-						result = flash_program(&flash, flash_offset, (UINT8*)&img_hdr, sizeof(flash_img_hdr_t));
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						result = flash_program(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size);
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("done\n");
-
-						sputs("Flash verify...");
-						result = flash_verify(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size);
-						if (IS_ERROR(result))
-						{
-							sputs("failed (");print_word(result);sputs(")\n");
-							break;
-						}
-						sputs("passed\n");
-
-						// Jump to reset vector
-						Jump_to((void*)0xBFC00000);
-
-						break;
-
-					default:
-						result = -1;
-						break;
-				}
-				if (IS_ERROR(result))
-				{
-					*pLED = 0x40000000;
-					break;
-				}
-
-			};
-		}
-	}
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S
deleted file mode 100644
index 84a8d9d..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S
+++ /dev/null
@@ -1,19 +0,0 @@
-		.file	"init.S"
-	
-		.text
-		.section .init,"ax"
-		.align	2
-		.globl _init
-		.extern end
-	
-_init:
-		.set	noreorder
-
-		# set uart
-		la	$26, sys_uart_baud
-		addiu	$27, $0, baudrate
-		sw	$27, 0($26)
-		
-		jr	$ra
-
-		.set	reorder
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat b/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat
deleted file mode 100644
index 33bc43a..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/jtag_upd.bat
+++ /dev/null
@@ -1,13 +0,0 @@
-@rem
-@rem   Setup Chipscope's TCL JTAG path
-@rem 
-@rem   Usage: cs_xtclsh.bat args...
-@rem
-@date /T > date.tmp
-@date 15.03.2009
-@set CS_PATH=%XILINX%\ChipScope\bin\nt
-@echo %CS_PATH%
-
-@call %CS_PATH%\cs_xtclsh bootloader.ROM.tcl
-@type date.tmp | date >nul
-@del date.tmp
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S
deleted file mode 100644
index b4a8694..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S
+++ /dev/null
@@ -1,46 +0,0 @@
-		.file	"kernel.S"
-
-		.section .ktext,"ax"
-		.align	2
-
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		.set	noreorder
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		li 		$27, 0xC0000000
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		la 		$27, sys_led_port
-		sw 		$26, 0($27)
-
-		# wait for all interrupts = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 0xFF
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		# Return
-		nop
-		jr	$26
-		rfe
-		.set	reorder
-	
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c
deleted file mode 100644
index 0f39d80..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c
+++ /dev/null
@@ -1,214 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <stdlib.h>
-#include "libsys_boot.h"
-
-// ---------------------------------------------------------------------------------
-// MIPS specific
-UINT32 CP0_SR_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $12\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_SR_write(UINT32 val)
-{
-	__asm
-	(
-		"mtc0   %[val], $12\n"
-		: /* no output */
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_CR_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $13\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_CR_write(UINT32 val)
-{
-	__asm
-	(
-		"mtc0   %[val], $13\n"
-		:
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_PRID_read(void)
-{
-	UINT32 result;
-
-	__asm
-	(
-		"mfc0   %[val], $15\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-// ---------------------------------------------------------------------------------
-char readchar(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA;
-
-	while(!(0x10 & *pUART_stat));
-
-	return (char)*pUART_data;
-}
-
-void writechar(char c)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = (UINT32)c;
-}
-
-void _putchar(char c)
-{
-	if (c == 0x0A)
-	{
-		writechar(0x0D);
-	}
-	writechar(c);
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		_putchar(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		_putchar(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
-// ---------------------------------------------------------------------------------
-// PrintBuffer8()
-// Prints byte buffer as hex and ascii interpretation
-// ---------------------------------------------------------------------------------
-// _Parameters :
-// pBuf:       : IN: Buffer to display
-// nbpr        : Number of bytes per row to display
-// len         : Length of input buffer
-// _Return:      none
-//
-// ---------------------------------------------------------------------------
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len)
-{
-	memdump(pBuf, 1, nbpr, len);
-}
-
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len)
-{
-    int i, j, cnt_hex, cnt_asc, base;
-    unsigned char c;
-
-    i = j = 0;
-    cnt_hex = len;
-    cnt_asc = len;
-    base = 0;
-	if (!print_offset_only)
-		base = (int)pBuf;
-
-    do
-    {
-        print_word(base + i);
-        sputs(": ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_hex)
-            {
-    		    print_byte(pBuf[i+j]);
-		        sputs(" ");
-                cnt_hex--;
-            }
-            else
-            {
-                sputs("   ");
-                break;
-            }
-
-        }
-
-        sputs("   ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_asc)
-            {
-                c = pBuf[i+j];
-                if((c < 0x20) || (c > 0x7F))
-                    c = '.';
-
-                _putchar(c);
-                cnt_asc--;
-            }
-            else
-            {
-                sputs(" ");
-                break;
-            }
-        }
-        sputs("\n");
-        i += num_bytes_per_row;
-
-    } while (cnt_hex);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h
deleted file mode 100644
index 3bf4ecc..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef LIBSYS_H
-#define LIBSYS_H
-
-// ---------------------------------------------------------
-// Types
-// ---------------------------------------------------------
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define	IS_ERROR(e)		((e & 0x80000000) == 0x80000000)
-
-#define	SYS_GPIO0		0xA0000000
-#define	SYS_GPIO1		0xA0000004
-#define	SYS_LED_PORT	SYS_GPIO0
-#define	SYS_USB_CTRL	SYS_GPIO1
-#define	SYS_TIMER_USEC	0xA0000008
-#define	SYS_TIMER_SEC	0xA000000C
-#define	SYS_UART_DATA	0xA0010000
-#define	SYS_UART_STAT	0xA0010004
-#define	SYS_UART_BAUD	0xA0010008
-#define	SYS_USB_DATA	0xA0020000
-#define	SYS_USB_MBX		0xA0020004
-#define	SYS_USB_ADDR	0xA0020008
-#define	SYS_USB_STATUS	0xA002000C
-#define	SYS_FLASH_IO	0xA4000000
-#define	SYS_FLASH_MEM	0x00000000
-
-// MIPS specific
-UINT32 CP0_SR_read(void);
-void CP0_SR_write(UINT32 val);
-UINT32 CP0_CR_read(void);
-void CP0_CR_write(UINT32 val);
-UINT32 CP0_PRID_read(void);
-
-// General
-char readchar(void);
-void writechar(char c);
-int write(int file, char *ptr, int len);
-int sputs(char *pStr);
-void print_byte(char byte);
-void print_word(int word);
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len);
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len);
-
-#endif // LIBSYS_H
-
diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S
deleted file mode 100644
index 8da9ee0..0000000
--- a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S
+++ /dev/null
@@ -1,43 +0,0 @@
-		.file	"startup.S"
-	
-		.text
-		.section .init,"ax"
-		.extern _init
-		.align	2
-	
-_start:
-		.set	noreorder
-
-		# set stack pointer 
-		la	$sp, stack_ptr
-
-		# Set Kernel mode
-		li		$26, 0x1040000C
-		mtc0	$26, $12
-		li		$26, 0x00000000
-		mtc0	$26, $13
-
-		mfc0	$26, $15
-		nop
-		mtc0	$26, $31
-
-		# Invalidate I-Cache
-		cop0	32
-		
-		# Invalidate D-Cache
-		cop0	34
-
-		# jump init
-		la $26, _init
-		jalr $26
-		nop
-
-		la $26, main
-		jalr $26
-		nop
-_terminate:
-		nop
-		j		_terminate
-		nop
-	
-		.set	reorder
diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.c b/lib/CPUs/MIPS/bsp/examples/cfiflash.c
deleted file mode 100644
index bbfbe43..0000000
--- a/lib/CPUs/MIPS/bsp/examples/cfiflash.c
+++ /dev/null
@@ -1,415 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include "libsys.h"
-#include "cfiflash.h"
-
-UINT32 cfi_get_status(flash_t *pObj)
-{
-	volatile UINT32 *pF;
-	UINT32 status;
-
-	pF = (UINT32*)pObj->pBase;
-
-	*pF = 0x00700070;
-
-	status = *pF;
-
-	*pF = 0x00FF00FF;
-
-	return status;
-
-}
-
-void cfi_init(flash_t *pObj, UINT32 base_addr)
-{
-	int i;
-	UINT8 *pInfo;
-	UINT32 endian;
-	UINT8 *pEndian;
-
-	pObj->pBase = (void*)base_addr;
-
-	pInfo = (UINT8*)&pObj->info;
-	for (i=0; i < sizeof(flash_info_t); i++)
-	{
-		pInfo[i] = 0;
-	}
-	pObj->eb = 0;
-	endian = 0x12345678;
-	pEndian = (UINT8*)&endian;
-	if (*pEndian == 0x12)
-	{
-		pObj->eb = 1;
-	}
-
-}
-
-UINT32 cfi_find(flash_t *pObj)
-{
-	int i;
-	volatile UINT32 *pF;
-	volatile UINT16 *pF16;
-//	UINT8 qry_ref[12] = {0x51, 0x00, 0x51, 0x00, 0x52, 0x00, 0x52, 0x00, 0x59, 0x00, 0x59, 0x00};
-	UINT32 size;
-
-	pF = (UINT32*)pObj->pBase;
-	pF16 = (UINT16*)pObj->pBase;
-
-	// Look for flash
-	*pF = 0x00980098;
-//	for (i=0; i < sizeof(qry_ref); i++)
-//		if (((UINT8*)(&pF[0x10]))[i] != qry_ref[i])
-//			return (UINT32)-1;
-
-	*pF = 0x00FF00FF;
-	*pF = 0x00900090;
-
-/*
-	printf("ManID             : %8.8X\n", (UINT32)pF[0]);
-	printf("Device code       : %8.8X\n", (UINT32)pF[1]);
-	printf("Block info        : %8.8X\n", (UINT32)pF[2]);
-
-	printf("VCC(min)          : %8.8X\n", (UINT32)pF[0x1B]);
-	printf("VCC(max)          : %8.8X\n", (UINT32)pF[0x1C]);
-	printf("VPP(min)          : %8.8X\n", (UINT32)pF[0x1D]);
-	printf("VPP(max)          : %8.8X\n", (UINT32)pF[0x1E]);
-	printf("Device Layout     : %8.8X\n", (UINT32)pF[0x27]);
-	printf("Interface type    : %8.8X %8.8X\n", (UINT32)pF[0x28], (UINT32)pF[0x29]);
-	printf("Write buffer size : %8.8X %8.8X\n", (UINT32)pF[0x2A], (UINT32)pF[0x2B]);
-	printf("Num. erase blocks : %8.8X\n", (UINT32)pF[0x2C]);
-	printf("Erase block info  : %8.8X %8.8X %8.8X %8.8X\n", (UINT32)pF[0x2D], (UINT32)pF[0x2E], (UINT32)pF[0x2F], (UINT32)pF[0x30]);
-*/
-	pObj->info.num_flash = 2;
-	pObj->info.if_width = 32;
-	size = (UINT32)pF16[2*0x27];
-	pObj->info.flashsize = pObj->info.num_flash;
-	for (i=0; i < size; i++)
-		pObj->info.flashsize *= 2;
-
-	size = (UINT32)(pF16[2*0x2B] << 8 | pF16[2*0x2A]);
-	pObj->info.wbuf_size = pObj->info.num_flash;
-	for (i=0; i < size; i++)
-		pObj->info.wbuf_size *= 2;
-
-	pObj->info.nblocks = (UINT32)(pF16[2*0x2E] << 8 | pF16[2*0x2D]) + 1;
-	pObj->info.blocksize = pObj->info.num_flash * ((UINT32)(pF16[2*0x30] << 8 | pF16[2*0x2F]) * 256);
-
-	*pF = 0x00FF00FF;
-
-	return 0;
-}
-
-UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index)
-{
-	volatile UINT32 *pF;
-	UINT32 status, block_index, block_mask;
-	UINT32 error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	block_mask = ((pObj->info.nblocks-1) << 16);
-	block_index = word_index & block_mask;
-
-	*pF = 0x00900090;
-
-	error = ((UINT32)pF[block_index+2] & 0x00010001) != 0;
-	*pF = 0x00FF00FF;
-
-	return error;
-}
-
-UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index)
-{
-	volatile UINT32 *pF;
-	UINT32 status, block_index, block_mask;
-	UINT32 error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	block_mask = ((pObj->info.nblocks-1) << 16);
-	block_index = word_index & block_mask;
-
-	pF[block_index] = 0x00200020;
-	pF[block_index] = 0x00D000D0;
-
-	error = 0;
-	do
-	{
-		status = pF[block_index];
-
-	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-
-	if (status & (SR_BIT_ECLBS | SR_BIT_VPENS | SR_BIT_DPS))
-	{
-		error = CFI_ERR_DEV_FAIL | status;
-	}
-
-	pF[block_index] = 0x00FF00FF;
-
-	return error;
-}
-
-UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index)
-{
-	volatile UINT32 *pF;
-	UINT32 status, block_index, block_mask;
-	UINT32 error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	block_mask = ((pObj->info.nblocks-1) << 16);
-	block_index = word_index & block_mask;
-
-	pF[block_index] = 0x00600060;
-	pF[block_index] = 0x00010001;
-
-	error = 0;
-	do
-	{
-		status = pF[block_index];
-
-	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-
-	if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS))
-	{
-		error = CFI_ERR_DEV_FAIL | status;
-	}
-
-	pF[block_index] = 0x00FF00FF;
-
-	return error;
-}
-
-UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index)
-{
-	volatile UINT32 *pF;
-	UINT32 status, block_index, block_mask;
-	UINT32 error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	block_mask = ((pObj->info.nblocks-1) << 16);
-	block_index = word_index & block_mask;
-
-	pF[block_index] = 0x00600060;
-	pF[block_index] = 0x00D000D0;
-
-	error = 0;
-	do
-	{
-		status = pF[block_index];
-
-	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-
-	if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS))
-	{
-		error = CFI_ERR_DEV_FAIL | status;
-	}
-
-	pF[block_index] = 0x00FF00FF;
-
-	return error;
-}
-
-UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word)
-{
-	volatile UINT32 *pF;
-	UINT32 status, error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	pF[word_index] = 0x00400040;
-	pF[word_index] = word;
-
-	error = 0;
-	do
-	{
-		status = pF[word_index];
-
-	} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-
-	if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS))
-	{
-		error = CFI_ERR_DEV_FAIL | status;
-	}
-
-	pF[word_index] = 0x00FF00FF;
-
-	return error;
-
-}
-
-UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words)
-{
-	int i, j, k;
-	volatile UINT32 *pF;
-	UINT32 status, bcurr, bnext, block_mask, nblock_write, nbuf_write;
-	UINT32 error;
-
-	pF = (UINT32*)pObj->pBase;
-
-	if (word_index >= (pObj->info.flashsize/4))
-		return CFI_ERR_INVPARAM;
-
-	block_mask = ((pObj->info.nblocks-1) << 16);
-
-	k = 0;
-	while(num_words)
-	{
-
-		bcurr = word_index & block_mask;
-		bnext = bcurr + (1 << 16);
-		nblock_write = bnext - word_index;
-		if (nblock_write > num_words)
-			nblock_write = num_words;
-
-		while(nblock_write)
-		{
-			error = 0;
-			pF[bcurr] = 0x00E800E8;
-			do
-			{
-				status = pF[bcurr];
-
-			} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-			if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS))
-			{
-				error = CFI_ERR_DEV_FAIL | status;
-				break;
-			}
-
-			nbuf_write = nblock_write;
-			if (nblock_write > pObj->info.wbuf_size/4)
-				nbuf_write = pObj->info.wbuf_size/4;
-
-			pF[bcurr] = (nbuf_write-1) << 16 | (nbuf_write-1);
-
-			for (j=0; j < nbuf_write; j++)
-				pF[word_index+j] = pWords[k++];
-
-			word_index += j;
-			nblock_write -= j;
-			num_words -= j;
-
-			error = 0;
-			pF[bcurr] = 0x00D000D0;
-			do
-			{
-				status = pF[bcurr];
-
-			} while((status & SR_BIT_ISMS) != SR_BIT_ISMS);
-			if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS))
-			{
-				error = CFI_ERR_DEV_FAIL | status;
-				break;
-			}
-
-			pF[bcurr] = 0x00FF00FF;
-		}
-
-		if (IS_ERROR(error))
-		{
-			pF[bcurr] = 0x00FF00FF;
-			break;
-		}
-		bcurr = bnext;
-	}
-
-	return error;
-
-}
-
-UINT32 flash_find(flash_t *pObj, UINT32 base_addr)
-{
-	cfi_init(pObj, base_addr);
-	return cfi_find(pObj);
-}
-
-UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size)
-{
-	int i;
-	UINT32 offset_end, error;
-
-	if (size % 4)
-		size = 4*(size/4 + 1);
-
-	offset_end = offset + size;
-
-	for (i=offset; i < offset_end; i += pObj->info.blocksize)
-	{
-		if (cfi_block_is_locked(pObj, i/4))
-		{
-			error = cfi_block_unlock(pObj, i/4);
-			if (IS_ERROR(error))
-				break;
-		}
-		error = cfi_block_erase(pObj, i/4);
-		if (IS_ERROR(error))
-			break;
-	}
-
-	return error;
-
-}
-
-UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size)
-{
-	if (size % 4)
-		size = 4*(size/4 + 1);
-
-	return cfi_program_multi(pObj, offset/4, (UINT32*)pData, size/4);
-}
-
-UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size)
-{
-	int i;
-	UINT8 *pF;
-
-	pF = (UINT8*)(pObj->pBase + offset);
-
-	for (i=0; i < size; i++)
-		if (pF[i] != pData[i])
-			return CFI_ERR_VFY_FAIL;
-
-	return 0;
-}
-
-UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset)
-{
-	UINT32 blocknum;
-
-	blocknum = offset/pObj->info.blocksize;
-	if (offset%pObj->info.blocksize)
-		blocknum++;
-
-	return blocknum;
-}
-
-UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum)
-{
-	if (blocknum >= pObj->info.nblocks)
-		blocknum = pObj->info.nblocks - 1;
-
-	return blocknum*pObj->info.blocksize;
-}
-
-UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset)
-{
-	return flash_get_blocknum_by_offset(pObj, offset) * pObj->info.blocksize;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.h b/lib/CPUs/MIPS/bsp/examples/cfiflash.h
deleted file mode 100644
index 1233642..0000000
--- a/lib/CPUs/MIPS/bsp/examples/cfiflash.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/************************************************************************/
-#ifndef CFIFLASH_H
-#define CFIFLASH_H
-
-#include "libsys.h"
-
-#define	SR_BIT_DPS			0x00020002
-#define	SR_BIT_PSS			0x00040004
-#define	SR_BIT_VPENS		0x00080008
-#define	SR_BIT_PSLBS		0x00100010
-#define	SR_BIT_ECLBS		0x00200020
-#define	SR_BIT_ESS			0x00400040
-#define	SR_BIT_ISMS			0x00800080
-
-#define	CFI_ERR_BASE		(LSYS_ERR_BASE + 0x00100000)
-#define	CFI_ERR_GENERAL		(CFI_ERR_BASE + 0)
-#define	CFI_ERR_NOTFOUND	(CFI_ERR_BASE + 1)
-#define	CFI_ERR_INVPARAM	(CFI_ERR_BASE + 2)
-#define	CFI_ERR_VFY_FAIL	(CFI_ERR_BASE + 3)
-#define	CFI_ERR_DEV_FAIL	(CFI_ERR_BASE + 0x10000000)
-
-typedef struct _sflash_info_t
-{
-	UINT32 flashsize;
-	UINT32 blocksize;
-	UINT32 nblocks;
-	UINT32 wbuf_size;
-	UINT32 if_width;
-	UINT32 num_flash;
-
-} flash_info_t;
-
-typedef struct _sflash_t
-{
-	void *pBase;
-	UINT32 eb;
-	flash_info_t info;
-
-} flash_t;
-
-void cfi_init(flash_t *pObj, UINT32 base_addr);
-UINT32 cfi_find(flash_t *pObj);
-UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index);
-UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index);
-UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index);
-UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index);
-UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word);
-UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words);
-
-UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum);
-UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset);
-UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset);
-UINT32 flash_find(flash_t *pObj, UINT32 base_addr);
-UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size);
-UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size);
-UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size);
-
-#endif // CFIFLASH_H
diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.c b/lib/CPUs/MIPS/bsp/examples/crc32.c
deleted file mode 100644
index 6f63429..0000000
--- a/lib/CPUs/MIPS/bsp/examples/crc32.c
+++ /dev/null
@@ -1,54 +0,0 @@
-#include <stdio.h>
-
-unsigned long MakeCRC32(char *data, unsigned int len, unsigned int CRC)
-{
-   /* ========================================================================
-    * Table of CRC-32's of all single-byte values (made by makecrc.c)
-    */
-   unsigned long crc_32_tab[] = {
-      0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, 0x706af48fL, 0xe963a535L, 0x9e6495a3L,
-	0x0edb8832L, 0x79dcb8a4L, 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, 0x90bf1d91L,
-	0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L,
-	0x136c9856L, 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, 0xfa0f3d63L, 0x8d080df5L,
-	0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,
-	0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L,
-	0x26d930acL, 0x51de003aL, 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, 0xb8bda50fL,
-	0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL,
-	0x76dc4190L, 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, 0x9fbfe4a5L, 0xe8b8d433L,
-	0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,
-	0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L,
-	0x65b0d9c6L, 0x12b7e950L, 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, 0xfbd44c65L,
-	0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL,
-	0x4369e96aL, 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, 0xaa0a4c5fL, 0xdd0d7cc9L,
-	0x5005713cL, 0x270241aaL, 0xbe0b1010L, 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,
-	0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL,
-	0xedb88320L, 0x9abfb3b6L, 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, 0x73dc1683L,
-	0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L,
-	0xf00f9344L, 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, 0x196c3671L, 0x6e6b06e7L,
-	0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,
-	0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL,
-	0xd80d2bdaL, 0xaf0a1b4cL, 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, 0x4669be79L,
-	0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL,
-	0xc5ba3bbeL, 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, 0x2cd99e8bL, 0x5bdeae1dL,
-	0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,
-	0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L,
-	0x86d3d2d4L, 0xf1d4e242L, 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, 0x18b74777L,
-	0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L,
-	0xa00ae278L, 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, 0x4969474dL, 0x3e6e77dbL,
-	0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,
-	0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, 0xcdd70693L, 0x54de5729L, 0x23d967bfL,
-	0xb3667a2eL, 0xc4614ab8L, 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, 0x2d02ef8dL
-   };
-
-   if (data == NULL)
-     return 0;
-   
-   CRC = ~CRC;
-   while (len --)
-     {
-	CRC = crc_32_tab[((unsigned char) CRC ^ *data) & 0xFF] ^ (CRC >> 8);
-	data ++;
-     }
-   
-   return ~CRC;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.h b/lib/CPUs/MIPS/bsp/examples/crc32.h
deleted file mode 100644
index 04687b0..0000000
--- a/lib/CPUs/MIPS/bsp/examples/crc32.h
+++ /dev/null
@@ -1,13 +0,0 @@
-//  CRC32 function
-//  To create a CRC from a new buffer, use this:
-//      crc = MakeCRC32(mydata, data_len, 0);
-//  If you need to continue the CRC (e.g. your data is in multiple buffers),
-//  continue like this:
-//      crc = MakeCRC32(moredata, more_len, crc);
-//      
-//  Your desired CRC should be the complement of the CRC generated by
-//  MakeCRC32:
-//      desired = crc
-//      desired - crc = 0
-
-unsigned long MakeCRC32(char *data, unsigned int len, unsigned long CRC);
diff --git a/lib/CPUs/MIPS/bsp/examples/cubic.c b/lib/CPUs/MIPS/bsp/examples/cubic.c
deleted file mode 100644
index 7740eb2..0000000
--- a/lib/CPUs/MIPS/bsp/examples/cubic.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-/*
-**  CUBIC.C - Solve a cubic polynomial
-**  public domain by Ross Cottrell
-*/
-
-#include <math.h>
-#include <stdlib.h>
-#include "snipmath.h"
-
-void SolveCubic(double  a,
-                double  b,
-                double  c,
-                double  d,
-                int    *solutions,
-                double *x)
-{
-      long double    a1 = b/a, a2 = c/a, a3 = d/a;
-      long double    Q = (a1*a1 - 3.0*a2)/9.0;
-      long double R = (2.0*a1*a1*a1 - 9.0*a1*a2 + 27.0*a3)/54.0;
-      double    R2_Q3 = R*R - Q*Q*Q;
-
-      double    theta;
-
-      if (R2_Q3 <= 0)
-      {
-            *solutions = 3;
-            theta = acos(R/sqrt(Q*Q*Q));
-            x[0] = -2.0*sqrt(Q)*cos(theta/3.0) - a1/3.0;
-            x[1] = -2.0*sqrt(Q)*cos((theta+2.0*PI)/3.0) - a1/3.0;
-            x[2] = -2.0*sqrt(Q)*cos((theta+4.0*PI)/3.0) - a1/3.0;
-      }
-      else
-      {
-            *solutions = 1;
-            x[0] = pow(sqrt(R2_Q3)+fabs(R), 1/3.0);
-            x[0] += Q/x[0];
-            x[0] *= (R < 0.0) ? 1 : -1;
-            x[0] -= a1/3.0;
-      }
-}
-
-#ifdef TEST
-
-int main(void)
-{
-      double  a1 = 1.0, b1 = -10.5, c1 = 32.0, d1 = -30.0;
-      double  a2 = 1.0, b2 = -4.5, c2 = 17.0, d2 = -30.0;
-      double  x[3];
-      int     solutions;
-
-      SolveCubic(a1, b1, c1, d1, &solutions, x);
-
-      /* should get 3 solutions: 2, 6 & 2.5   */
-
-      SolveCubic(a2, b2, c2, d2, &solutions, x);
-
-      /* should get 1 solution: 2.5           */
-
-      return 0;
-}
-
-#endif /* TEST */
diff --git a/lib/CPUs/MIPS/bsp/examples/dbg.c b/lib/CPUs/MIPS/bsp/examples/dbg.c
deleted file mode 100644
index fc5a429..0000000
--- a/lib/CPUs/MIPS/bsp/examples/dbg.c
+++ /dev/null
@@ -1,375 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "irq.h"
-#include "libsys.h"
-#include "mips_dis.h"
-
-#define	MAX_USER_BP				16
-#define	BP_MASK_ID				0x00FFF
-#define	BP_MASK_TYPE			0xFF000
-
-#define	BP_GET_ID(bp)			((bp >> 6) & 0xFFF)
-
-#define	BP_USER_BASE			0x10000
-#define	BP_USER(id)				(((BP_USER_BASE + id) << 6) | 0x0D)
-
-#define	BP_MGMT_BASE_SS			0x20000
-#define	BP_MGMT_SS(id)			(((BP_MGMT_BASE_SS + id) << 6) | 0x0D)
-
-#define	BP_MGMT_BASE_RU			0x30000
-#define	BP_MGMT_RU(id)			(((BP_MGMT_BASE_RU + id) << 6) | 0x0D)
-
-static char g_buf[80];
-
-typedef struct _sbp_t
-{
-	UINT32 *pAddr;
-	UINT32 instr;
-} bp_t;
-
-static EXCEPTION_CONTEXT xcp_last;
-static bp_t user_bp[MAX_USER_BP];
-static bp_t mgmt_bp_ss[2];
-static bp_t mgmt_bp_ru[2];
-static int g_is_ss;
-static int g_bp_index;
-
-int IsBreak(UINT32 instr)
-{
-	return ((instr & 0xFC00003F) == 0x0000000D);
-}
-
-UINT32 BreakGetType(UINT32 instr)
-{
-	return (instr >> 6) & BP_MASK_TYPE;
-}
-
-char* reg_changed(UINT32 reg1, UINT32 reg2)
-{
-	static char chg_str[2] = {0};
-
-	if (reg1 != reg2)
-		chg_str[0] = '*';
-	else
-		chg_str[0] = ' ';
-
-	return chg_str;
-}
-
-void dbg_handler(struct xcptcontext * xcp)
-{
-
- 	UINT32 bp_addr, bp_index = 0, branch_addr, reg, result, bp_type;
-    int junk, i, leave_isr, is_branch_shadow, is_user_bp;
-	UINT32 volatile *pBtn = (UINT32*)SYS_GPIO0;
-	UINT32 *pInstr, *pAddr_curr, *pAddr_prev, *pAddr_next;
-
-	sputs("\n");
-	PRINT_REG_CHG(" Status : ", xcp->sr, reg_changed(xcp->sr, xcp_last.sr));
-	PRINT_REG_CHG("  Cause : ", xcp->cr, reg_changed(xcp->cr, xcp_last.cr));
-	PRINT_REG_CHG("    EPC : ", xcp->epc, reg_changed(xcp->epc, xcp_last.epc));
-	PRINT_REG_CHG("BadAddr : ", xcp->baddr, reg_changed(xcp->baddr, xcp_last.baddr));
-	sputs("\n");
-	PRINT_REG_CHG("   MDLO : ", xcp->mdlo, reg_changed(xcp->mdlo, xcp_last.mdlo));
-	PRINT_REG_CHG("   MDHI : ", xcp->mdhi, reg_changed(xcp->mdhi, xcp_last.mdhi));
-
-	sputs("\n");
-
-	sputs("Registers:\n");
-	PRINT_REG_CHG(" 0 (ze) : ", xcp->regs[0], reg_changed(xcp->regs[0], xcp_last.regs[0]));
-	PRINT_REG_CHG(" 1 (at) : ", xcp->regs[1], reg_changed(xcp->regs[1], xcp_last.regs[1]));
-	PRINT_REG_CHG(" 2 (v0) : ", xcp->regs[2], reg_changed(xcp->regs[2], xcp_last.regs[2]));
-	PRINT_REG_CHG(" 3 (v1) : ", xcp->regs[3], reg_changed(xcp->regs[3], xcp_last.regs[3]));
-	sputs("\n");
-	PRINT_REG_CHG(" 4 (a0) : ", xcp->regs[4], reg_changed(xcp->regs[4], xcp_last.regs[4]));
-	PRINT_REG_CHG(" 5 (a1) : ", xcp->regs[5], reg_changed(xcp->regs[5], xcp_last.regs[5]));
-	PRINT_REG_CHG(" 6 (a2) : ", xcp->regs[6], reg_changed(xcp->regs[6], xcp_last.regs[6]));
-	PRINT_REG_CHG(" 7 (a3) : ", xcp->regs[7], reg_changed(xcp->regs[7], xcp_last.regs[7]));
-	sputs("\n");
-	PRINT_REG_CHG(" 8 (t0) : ", xcp->regs[8], reg_changed(xcp->regs[8], xcp_last.regs[8]));
-	PRINT_REG_CHG(" 9 (t1) : ", xcp->regs[9], reg_changed(xcp->regs[9], xcp_last.regs[9]));
-	PRINT_REG_CHG("10 (t2) : ", xcp->regs[10], reg_changed(xcp->regs[10], xcp_last.regs[10]));
-	PRINT_REG_CHG("11 (t3) : ", xcp->regs[11], reg_changed(xcp->regs[11], xcp_last.regs[11]));
-	sputs("\n");
-	PRINT_REG_CHG("12 (t4) : ", xcp->regs[12], reg_changed(xcp->regs[12], xcp_last.regs[12]));
-	PRINT_REG_CHG("13 (t5) : ", xcp->regs[13], reg_changed(xcp->regs[13], xcp_last.regs[13]));
-	PRINT_REG_CHG("14 (t6) : ", xcp->regs[14], reg_changed(xcp->regs[14], xcp_last.regs[14]));
-	PRINT_REG_CHG("15 (t7) : ", xcp->regs[15], reg_changed(xcp->regs[15], xcp_last.regs[15]));
-	sputs("\n");
-	PRINT_REG_CHG("16 (s0) : ", xcp->regs[16], reg_changed(xcp->regs[16], xcp_last.regs[16]));
-	PRINT_REG_CHG("17 (s1) : ", xcp->regs[17], reg_changed(xcp->regs[17], xcp_last.regs[17]));
-	PRINT_REG_CHG("18 (s2) : ", xcp->regs[18], reg_changed(xcp->regs[18], xcp_last.regs[18]));
-	PRINT_REG_CHG("19 (s3) : ", xcp->regs[19], reg_changed(xcp->regs[19], xcp_last.regs[19]));
-	sputs("\n");
-	PRINT_REG_CHG("20 (s4) : ", xcp->regs[20], reg_changed(xcp->regs[20], xcp_last.regs[20]));
-	PRINT_REG_CHG("21 (s5) : ", xcp->regs[21], reg_changed(xcp->regs[21], xcp_last.regs[21]));
-	PRINT_REG_CHG("22 (s6) : ", xcp->regs[22], reg_changed(xcp->regs[22], xcp_last.regs[22]));
-	PRINT_REG_CHG("23 (s7) : ", xcp->regs[23], reg_changed(xcp->regs[23], xcp_last.regs[23]));
-	sputs("\n");
-	PRINT_REG_CHG("24 (s8) : ", xcp->regs[24], reg_changed(xcp->regs[24], xcp_last.regs[24]));
-	PRINT_REG_CHG("25 (s9) : ", xcp->regs[25], reg_changed(xcp->regs[25], xcp_last.regs[25]));
-	PRINT_REG_CHG("26 (k0) : ", xcp->regs[26], reg_changed(xcp->regs[26], xcp_last.regs[26]));
-	PRINT_REG_CHG("27 (k1) : ", xcp->regs[27], reg_changed(xcp->regs[27], xcp_last.regs[27]));
-	sputs("\n");
-	PRINT_REG_CHG("28 (gp) : ", xcp->regs[28], reg_changed(xcp->regs[28], xcp_last.regs[28]));
-	PRINT_REG_CHG("29 (sp) : ", xcp->regs[29], reg_changed(xcp->regs[29], xcp_last.regs[29]));
-	PRINT_REG_CHG("30 (fp) : ", xcp->regs[30], reg_changed(xcp->regs[30], xcp_last.regs[30]));
-	PRINT_REG_CHG("31 (ra) : ", xcp->regs[31], reg_changed(xcp->regs[31], xcp_last.regs[31]));
-	sputs("\n");
-	sputs("\n");
-
-	memcpy(&xcp_last, xcp, sizeof(EXCEPTION_CONTEXT));
-
-	is_user_bp = 0;
-	pAddr_curr = (UINT32*)xcp->epc;
-	is_branch_shadow = ((xcp->cr & 0x80000000) == 0x80000000);
-	if (is_branch_shadow)
-		pAddr_curr++;
-
-	pAddr_prev = pAddr_curr - 1;
-	pAddr_next = pAddr_curr + 1;
-
-	if (IsBreak(*pAddr_curr))
-	{
-		bp_type = BreakGetType(*pAddr_curr);
-
-		switch (bp_type)
-		{
-			case BP_MGMT_BASE_SS:
-
-			// Restore original instructions after single-step
-//			sputs("1. Restore after single-step at ");print_word((long)mgmt_bp_ss[0].pAddr);sputs("\n");
-			*(mgmt_bp_ss[0].pAddr) = mgmt_bp_ss[0].instr;
-			ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr);
-			if (mgmt_bp_ss[1].pAddr)
-			{
-//				sputs("2. Restore after single-step at ");print_word((long)mgmt_bp_ss[1].pAddr);sputs("\n");
-				*(mgmt_bp_ss[1].pAddr) = mgmt_bp_ss[1].instr;
-				ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr);
-			}
-
-			break;
-
-			case BP_MGMT_BASE_RU:
-
-			bp_index = BP_GET_ID(*pAddr_curr);
-//			sputs("Restore user break at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
-
-			*(user_bp[bp_index].pAddr) = BP_USER(bp_index);
-			ICACHE_invalidate_at(user_bp[bp_index].pAddr);
-
-			*(mgmt_bp_ru[0].pAddr) = mgmt_bp_ru[0].instr;
-			ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr);
-//			sputs("1. Restore after RU at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
-			if (mgmt_bp_ru[1].pAddr)
-			{
-				*(mgmt_bp_ru[1].pAddr) = mgmt_bp_ru[1].instr;
-				ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr);
-//				sputs("2. Restore after RU at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
-			}
-			if (!g_is_ss)
-				return;
-
-			break;
-
-			case BP_USER_BASE:
-
-			is_user_bp = 1;
-			bp_index = BP_GET_ID(*pAddr_curr);
-//			sputs("Restore instruction at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n");
-			*(user_bp[bp_index].pAddr) = user_bp[bp_index].instr;
-			ICACHE_invalidate_at(user_bp[bp_index].pAddr);
-			break;
-
-			default:
-//			sputs("Found ordinary break at ");print_word((long)pAddr_curr);sputs("\n");
-			break;
-
-		}
-	}
-
-	pInstr = pAddr_prev;
-	// Disassemble instructions
-    for (i=0; i < 3; i++)
-    {
-		print_word((long)pInstr);
-		if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE))
-		{
-			tdisasm(g_buf, (long)user_bp[BP_GET_ID(*pInstr)].pAddr, user_bp[BP_GET_ID(*pInstr)].instr, 0, &junk, &junk, &junk);
-			sputs(": b   ");
-		}
-		else
-		{
-			tdisasm(g_buf, (long)pInstr, *pInstr, 0, &junk, &junk, &junk);
-			if (pInstr == pAddr_curr)
-				if (is_user_bp == 1)
-					sputs(": b-> ");
-				else
-					sputs(":  -> ");
-			else
-				sputs(":     ");
-		}
-		sputs(g_buf);
-		sputs("\n");
-		pInstr++;
-	}
-
-	if (is_user_bp)
-	{
-		// Save original instruction
-		mgmt_bp_ru[0].pAddr = pAddr_next;
-		mgmt_bp_ru[0].instr = *(mgmt_bp_ru[0].pAddr);
-		// Replace instruction with managment breakpoint
-		*(mgmt_bp_ru[0].pAddr) = BP_MGMT_RU(bp_index);
-		ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr);
-		mgmt_bp_ru[1].pAddr = NULL;
-		mgmt_bp_ru[1].pAddr = 0;
-//		sputs("1. Insert RU-break at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n");
-
-		// We have two possible management breaks, if previous instruction was branch or jump
-		if (is_branch_shadow)
-		{
-			result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, &reg);
-			// Is jump target stored in register
-			if (result == 3)
-			{
-				branch_addr = xcp->regs[reg&0x1F];
-			}
-			// Save original instruction
-			mgmt_bp_ru[1].pAddr = (UINT32*)branch_addr;
-			mgmt_bp_ru[1].instr = *(mgmt_bp_ru[1].pAddr);
-			// Replace instruction with managment breakpoint
-			*(mgmt_bp_ru[1].pAddr) = BP_MGMT_RU(bp_index);
-			ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr);
-//			sputs("2. Insert RU-break at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n");
-		}
-	}
-
-	do
-	{
-		leave_isr = 0;
-		switch(_getchar())
-		{
-			case 'g':
-			leave_isr = 1;
-			g_is_ss = 0;
-			if (IsBreak(*pAddr_curr))
-			{
-				if (BreakGetType(*pAddr_curr) != BP_USER_BASE)
-				{
-					xcp->epc += 4;		// Skip ordinary program breaks
-				}
-			}
-			break;
-
-			case 'b':
-			printf("Enter breakpoint: ");
-			scanf("%x", &bp_addr);
-			printf("Insert breakpoint at %.8X\n", bp_addr);
-			user_bp[g_bp_index].pAddr = (UINT32*)bp_addr;
-			user_bp[g_bp_index].instr = *(user_bp[g_bp_index].pAddr);
-			*(user_bp[g_bp_index].pAddr) = BP_USER(g_bp_index);
-
-		    tdisasm(g_buf, (long)user_bp[g_bp_index].pAddr, user_bp[g_bp_index].instr, 0, &junk, &junk, &junk);
-			print_word((long)user_bp[g_bp_index].pAddr);sputs(": b   ");sputs(g_buf);sputs("\n");
-			ICACHE_invalidate_at(user_bp[g_bp_index].pAddr);
-			g_bp_index++;
-			break;
-
-			case 's':
-			g_is_ss = 1;
-			leave_isr = 1;
-			// Don't overwrite RU breaks
-//			printf("is_user_bp = %d, IsBreak = %d, pAddr_curr = %08X, *pAddr_curr = %08X\n", is_user_bp, IsBreak(*pAddr_curr), pAddr_curr, *pAddr_curr);
-
-			if (is_user_bp)
-				break;
-
-			// Don't overwrite user breaks
-			if (IsBreak(*pAddr_curr))
-			{
-				if (BreakGetType(*pAddr_curr) == BP_USER_BASE)
-				{
-					break;
-				}
-				else
-				{
-					xcp->epc += 4;		// Skip ordinary program breaks
-				}
-			}
-			// Save original instruction
-			mgmt_bp_ss[0].pAddr = pAddr_next;
-			mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr);
-			// Replace instruction with managment breakpoint
-			*(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1);
-			ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr);
-			mgmt_bp_ss[1].pAddr = NULL;
-			mgmt_bp_ss[1].pAddr = 0;
-			// We have two possible management breaks, if previous instruction was branch or jump
-			if (is_branch_shadow)
-			{
-				result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, &reg);
-				// Is jump target stored in register
-				if (result == 3)
-				{
-					branch_addr = xcp->regs[reg&0x1F];
-				}
-				// Save original instruction
-				mgmt_bp_ss[1].pAddr = (UINT32*)branch_addr;
-				mgmt_bp_ss[1].instr = *(mgmt_bp_ss[1].pAddr);
-				// Replace instruction with managment breakpoint
-				*(mgmt_bp_ss[1].pAddr) = BP_MGMT_SS(2);
-				ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr);
-			}
-			break;
-
-			case 'P':
-			g_is_ss = 1;
-			leave_isr = 1;
-			// Don't overwrite RU breaks
-			if (is_user_bp)
-				break;
-			// Don't overwrite user breaks
-			if (IsBreak(*pAddr_curr) && (BreakGetType(*pAddr_curr) == BP_USER_BASE))
-				break;
-
-			// Save original instruction
-			mgmt_bp_ss[0].pAddr = (UINT32*)xcp->regs[0x1F];
-			mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr);
-			// Replace instruction with managment breakpoint
-			*(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1);
-			ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr);
-			mgmt_bp_ss[1].pAddr = NULL;
-			mgmt_bp_ss[1].pAddr = 0;
-			break;
-
-			default:
-			break;
-		}
-	} while (!leave_isr);
-
-}
-
-void debug_int(struct xcptcontext * xcp)
-{
-	dbg_handler(xcp);
-
-}
-
-int debug_break(struct xcptcontext * xcp)
-{
-	dbg_handler(xcp);
-	return 0;
-
-}
-
-void dbg_init(void)
-{
-	memset(&xcp_last, 0, sizeof(EXCEPTION_CONTEXT));
-	interrupt_register(2, debug_int);
-	interrupt_enable(2);
-
-	xcpt_register(Bp, debug_break);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/delay_mips.c b/lib/CPUs/MIPS/bsp/examples/delay_mips.c
deleted file mode 100644
index 133a176..0000000
--- a/lib/CPUs/MIPS/bsp/examples/delay_mips.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// MIPS delay.
-
-void __inline__ delay(int loops)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"1:bnez	%[loops], 1b\n"
-		"addiu	%[loops], -1\n"
-		".set	reorder\n"
-		:
-		: [loops] "r" (loops)
-	);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/demo.c b/lib/CPUs/MIPS/bsp/examples/demo.c
deleted file mode 100644
index e3fc38a..0000000
--- a/lib/CPUs/MIPS/bsp/examples/demo.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
-*   Byte-oriented AES-256 implementation.
-*   All lookup tables replaced with 'on the fly' calculations.
-*
-*   Copyright (c) 2007 Ilya O. Levin, http://www.literatecode.com
-*
-*   Permission to use, copy, modify, and distribute this software for any
-*   purpose with or without fee is hereby granted, provided that the above
-*   copyright notice and this permission notice appear in all copies.
-*
-*   THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-*   WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-*   MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-*   ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-*   WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-*   ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-*   OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-#include <stdlib.h>
-#include <stdio.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-#include "aes256.h"
-
-#define DUMP(s, i, buf, sz)  {printf(s);                   \
-                              for (i = 0; i < (sz);i++)    \
-                                  printf("%02x ", buf[i]); \
-                              printf("\n");}
-
-
-int main (int argc, char *argv[])
-{
-    aes256_context ctx;
-    uint8_t key[32];
-    uint8_t buf[16], i;
-	long start, end, j;
-
-    /* put a test vector */
-    for (i = 0; i < sizeof(buf);i++) buf[i] = i * 16 + i;
-    for (i = 0; i < sizeof(key);i++) key[i] = i;
-
-    DUMP("txt: ", i, buf, sizeof(buf));
-    DUMP("key: ", i, key, sizeof(key));
-    printf("---\n");
-
-    aes256_init(&ctx, key);
-	start = clock();
-	for (j=0; j < 1000; j++)
-	{
-	    aes256_encrypt_ecb(&ctx, buf);
-  	}
-	end = clock();
-
-	printf("Speed %f blocks/s\n", (float)j/((float)(end-start)/CLOCKS_PER_SEC));
-
-    DUMP("enc: ", i, buf, sizeof(buf));
-    printf("tst: 8e a2 b7 ca 51 67 45 bf ea fc 49 90 4b 49 60 89\n");
-
-    aes256_init(&ctx, key);
-    aes256_decrypt_ecb(&ctx, buf);
-    DUMP("dec: ", i, buf, sizeof(buf));
-
-    aes256_done(&ctx);
-
-    return 0;
-} /* main */
diff --git a/lib/CPUs/MIPS/bsp/examples/dhry.h b/lib/CPUs/MIPS/bsp/examples/dhry.h
deleted file mode 100644
index c8d8f0a..0000000
--- a/lib/CPUs/MIPS/bsp/examples/dhry.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- ****************************************************************************
- *
- *                   "DHRYSTONE" Benchmark Program
- *                   -----------------------------
- *                                                                            
- *  Version:    C, Version 2.1
- *                                                                            
- *  File:       dhry.h (part 1 of 3)
- *
- *  Date:       May 25, 1988
- *
- *  Author:     Reinhold P. Weicker
- *                      Siemens AG, E STE 35
- *                      Postfach 3240
- *                      8520 Erlangen
- *                      Germany (West)
- *                              Phone:  [xxx-49]-9131-7-20330
- *                                      (8-17 Central European Time)
- *                              Usenet: ..!mcvax!unido!estevax!weicker
- *
- *              Original Version (in Ada) published in
- *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
- *              pp. 1013 - 1030, together with the statistics
- *              on which the distribution of statements etc. is based.
- *
- *              In this C version, the following C library functions are used:
- *              - strcpy, strcmp (inside the measurement loop)
- *              - printf, scanf (outside the measurement loop)
- *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
- *              are used for execution time measurement. For measurements
- *              on other systems, these calls have to be changed.
- *
- *  Collection of Results:
- *              Reinhold Weicker (address see above) and
- *              
- *              Rick Richardson
- *              PC Research. Inc.
- *              94 Apple Orchard Drive
- *              Tinton Falls, NJ 07724
- *                      Phone:  (201) 389-8963 (9-17 EST)               
- *                      Usenet: ...!uunet!pcrat!rick
- *
- *      Please send results to Rick Richardson and/or Reinhold Weicker.
- *      Complete information should be given on hardware and software used.
- *      Hardware information includes: Machine type, CPU, type and size
- *      of caches; for microprocessors: clock frequency, memory speed
- *      (number of wait states).
- *      Software information includes: Compiler (and runtime library)
- *      manufacturer and version, compilation switches, OS version.
- *      The Operating System version may give an indication about the
- *      compiler; Dhrystone itself performs no OS calls in the measurement loop.
- *
- *      The complete output generated by the program should be mailed
- *      such that at least some checks for correctness can be made.
- *
- ***************************************************************************
- *
- *  History:    This version C/2.1 has been made for two reasons:
- *
- *              1) There is an obvious need for a common C version of
- *              Dhrystone, since C is at present the most popular system
- *              programming language for the class of processors
- *              (microcomputers, minicomputers) where Dhrystone is used most.
- *              There should be, as far as possible, only one C version of
- *              Dhrystone such that results can be compared without
- *              restrictions. In the past, the C versions distributed
- *              by Rick Richardson (Version 1.1) and by Reinhold Weicker
- *              had small (though not significant) differences.
- *
- *              2) As far as it is possible without changes to the Dhrystone
- *              statistics, optimizing compilers should be prevented from
- *              removing significant statements.
- *
- *              This C version has been developed in cooperation with
- *              Rick Richardson (Tinton Falls, NJ), it incorporates many
- *              ideas from the "Version 1.1" distributed previously by
- *              him over the UNIX network Usenet.
- *              I also thank Chaim Benedelac (National Semiconductor),
- *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
- *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
- *              for their help with comments on earlier versions of the
- *              benchmark.
- *
- *  Changes:    In the initialization part, this version follows mostly
- *              Rick Richardson's version distributed via Usenet, not the
- *              version distributed earlier via floppy disk by Reinhold Weicker.
- *              As a concession to older compilers, names have been made
- *              unique within the first 8 characters.
- *              Inside the measurement loop, this version follows the
- *              version previously distributed by Reinhold Weicker.
- *
- *              At several places in the benchmark, code has been added,
- *              but within the measurement loop only in branches that 
- *              are not executed. The intention is that optimizing compilers
- *              should be prevented from moving code out of the measurement
- *              loop, or from removing code altogether. Since the statements
- *              that are executed within the measurement loop have NOT been
- *              changed, the numbers defining the "Dhrystone distribution"
- *              (distribution of statements, operand types and locality)
- *              still hold. Except for sophisticated optimizing compilers,
- *              execution times for this version should be the same as
- *              for previous versions.
- *              
- *              Since it has proven difficult to subtract the time for the
- *              measurement loop overhead in a correct way, the loop check
- *              has been made a part of the benchmark. This does have
- *              an impact - though a very minor one - on the distribution
- *              statistics which have been updated for this version.
- *
- *              All changes within the measurement loop are described
- *              and discussed in the companion paper "Rationale for
- *              Dhrystone version 2".
- *
- *              Because of the self-imposed limitation that the order and
- *              distribution of the executed statements should not be
- *              changed, there are still cases where optimizing compilers
- *              may not generate code for some statements. To a certain
- *              degree, this is unavoidable for small synthetic benchmarks.
- *              Users of the benchmark are advised to check code listings
- *              whether code is generated for all statements of Dhrystone.
- *
- *              Version 2.1 is identical to version 2.0 distributed via
- *              the UNIX network Usenet in March 1988 except that it corrects
- *              some minor deficiencies that were found by users of version 2.0.
- *              The only change within the measurement loop is that a
- *              non-executed "else" part was added to the "if" statement in
- *              Func_3, and a non-executed "else" part removed from Proc_3.
- *
- ***************************************************************************
- *
- * Defines:     The following "Defines" are possible:
- *              -DREG=register          (default: Not defined)
- *                      As an approximation to what an average C programmer
- *                      might do, the "register" storage class is applied
- *                      (if enabled by -DREG=register)
- *                      - for local variables, if they are used (dynamically)
- *                        five or more times
- *                      - for parameters if they are used (dynamically)
- *                        six or more times
- *                      Note that an optimal "register" strategy is
- *                      compiler-dependent, and that "register" declarations
- *                      do not necessarily lead to faster execution.
- *              -DNOSTRUCTASSIGN        (default: Not defined)
- *                      Define if the C compiler does not support
- *                      assignment of structures.
- *              -DNOENUMS               (default: Not defined)
- *                      Define if the C compiler does not support
- *                      enumeration types.
- *              -DTIMES                 (default)
- *              -DTIME
- *                      The "times" function of UNIX (returning process times)
- *                      or the "time" function (returning wallclock time)
- *                      is used for measurement. 
- *                      For single user machines, "time ()" is adequate. For
- *                      multi-user machines where you cannot get single-user
- *                      access, use the "times ()" function. If you have
- *                      neither, use a stopwatch in the dead of night.
- *                      "printf"s are provided marking the points "Start Timer"
- *                      and "Stop Timer". DO NOT use the UNIX "time(1)"
- *                      command, as this will measure the total time to
- *                      run this program, which will (erroneously) include
- *                      the time to allocate storage (malloc) and to perform
- *                      the initialization.
- *              -DHZ=nnn
- *                      In Berkeley UNIX, the function "times" returns process
- *                      time in 1/HZ seconds, with HZ = 60 for most systems.
- *                      CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
- *                      A VALUE.
- *
- ***************************************************************************
- *
- *  Compilation model and measurement (IMPORTANT):
- *
- *  This C version of Dhrystone consists of three files:
- *  - dhry.h (this file, containing global definitions and comments)
- *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
- *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
- *
- *  The following "ground rules" apply for measurements:
- *  - Separate compilation
- *  - No procedure merging
- *  - Otherwise, compiler optimizations are allowed but should be indicated
- *  - Default results are those without register declarations
- *  See the companion paper "Rationale for Dhrystone Version 2" for a more
- *  detailed discussion of these ground rules.
- *
- *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
- *  models ("small", "medium", "large" etc.) should be given if possible,
- *  together with a definition of these models for the compiler system used.
- *
- **************************************************************************
- *
- *  Dhrystone (C version) statistics:
- *
- *  [Comment from the first distribution, updated for version 2.
- *   Note that because of language differences, the numbers are slightly
- *   different from the Ada version.]
- *
- *  The following program contains statements of a high level programming
- *  language (here: C) in a distribution considered representative:           
- *
- *    assignments                  52 (51.0 %)
- *    control statements           33 (32.4 %)
- *    procedure, function calls    17 (16.7 %)
- *
- *  103 statements are dynamically executed. The program is balanced with
- *  respect to the three aspects:                                             
- *
- *    - statement type
- *    - operand type
- *    - operand locality
- *         operand global, local, parameter, or constant.                     
- *
- *  The combination of these three aspects is balanced only approximately.    
- *
- *  1. Statement Type:                                                        
- *  -----------------             number
- *
- *     V1 = V2                     9
- *       (incl. V1 = F(..)
- *     V = Constant               12
- *     Assignment,                 7
- *       with array element
- *     Assignment,                 6
- *       with record component
- *                                --
- *                                34       34
- *
- *     X = Y +|-|"&&"|"|" Z        5
- *     X = Y +|-|"==" Constant     6
- *     X = X +|- 1                 3
- *     X = Y *|/ Z                 2
- *     X = Expression,             1
- *           two operators
- *     X = Expression,             1
- *           three operators
- *                                --
- *                                18       18
- *
- *     if ....                    14
- *       with "else"      7
- *       without "else"   7
- *           executed        3
- *           not executed    4
- *     for ...                     7  |  counted every time
- *     while ...                   4  |  the loop condition
- *     do ... while                1  |  is evaluated
- *     switch ...                  1
- *     break                       1
- *     declaration with            1
- *       initialization
- *                                --
- *                                34       34
- *
- *     P (...)  procedure call    11
- *       user procedure      10
- *       library procedure    1
- *     X = F (...)
- *             function  call      6
- *       user function        5                                         
- *       library function     1                                               
- *                                --                                          
- *                                17       17
- *                                        ---
- *                                        103
- *
- *    The average number of parameters in procedure or function calls
- *    is 1.82 (not counting the function values aX *
- *
- *  2. Operators
- *  ------------
- *                          number    approximate
- *                                    percentage
- *
- *    Arithmetic             32          50.8                                 
- *
- *       +                     21          33.3                              
- *       -                      7          11.1                              
- *       *                      3           4.8
- *       / (int div)            1           1.6
- *
- *    Comparison             27           42.8
- *
- *       ==                     9           14.3
- *       /=                     4            6.3
- *       >                      1            1.6
- *       <                      3            4.8
- *       >=                     1            1.6
- *       <=                     9           14.3
- *
- *    Logic                   4            6.3
- *
- *       && (AND-THEN)          1            1.6
- *       |  (OR)                1            1.6
- *       !  (NOT)               2            3.2
- * 
- *                           --          -----
- *                           63          100.1
- *
- *
- *  3. Operand Type (counted once per operand reference):
- *  ---------------
- *                          number    approximate
- *                                    percentage
- *
- *     Integer               175        72.3 %
- *     Character              45        18.6 %
- *     Pointer                12         5.0 %
- *     String30                6         2.5 %
- *     Array                   2         0.8 %
- *     Record                  2         0.8 %
- *                           ---       -------
- *                           242       100.0 %
- *
- *  When there is an access path leading to the final operand (e.g. a record
- *  component), only the final data type on the access path is counted.       
- *
- *
- *  4. Operand Locality:                                                      
- *  -------------------
- *                                number    approximate
- *                                          percentage
- *
- *     local variable              114        47.1 %
- *     global variable              22         9.1 %
- *     parameter                    45        18.6 %
- *        value                        23         9.5 %
- *        reference                    22         9.1 %
- *     function result               6         2.5 %
- *     constant                     55        22.7 %
- *                                 ---       -------
- *                                 242       100.0 %
- *
- *
- *  The program does not compute anything meaningful, but it is syntactically
- *  and semantically correct. All variables have a value assigned to them
- *  before they are used as a source operand.
- *
- *  There has been no explicit effort to account for the effects of a
- *  cache, or to balance the use of long or short displacements for code or
- *  data.
- *
- ***************************************************************************
- */
-
-/* Compiler and system dependent definitions: */
-
-#ifndef TIME
-#undef TIMES
-#define TIMES
-#endif
-                /* Use times(2) time function unless    */
-                /* explicitly defined otherwise         */
-#ifdef MSC_CLOCK
-#undef HZ
-#undef TIMES
-#include <time.h>
-#define HZ	CLK_TCK
-#endif
-		/* Use Microsoft C hi-res clock */
-
-#ifdef TIMES
-#include <sys/types.h>
-#include <sys/times.h>
-                /* for "times" */
-#endif
-
-#define Mic_secs_Per_Second     1000000.0
-                /* Berkeley UNIX C returns process times in seconds/HZ */
-
-#ifdef  NOSTRUCTASSIGN
-#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
-#else
-#define structassign(d, s)      d = s
-#endif
-
-#ifdef  NOENUM
-#define Ident_1 0
-#define Ident_2 1
-#define Ident_3 2
-#define Ident_4 3
-#define Ident_5 4
-  typedef int   Enumeration;
-#else
-  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
-                Enumeration;
-#endif
-        /* for boolean and enumeration types in Ada, Pascal */
-
-/* General definitions: */
-
-#include <stdio.h>
-                /* for strcpy, strcmp */
-
-#define Null 0 
-                /* Value of a Null pointer */
-#define true  1
-#define false 0
-
-typedef int     One_Thirty;
-typedef int     One_Fifty;
-typedef char    Capital_Letter;
-typedef int     Boolean;
-typedef char    Str_30 [31];
-typedef int     Arr_1_Dim [50];
-typedef int     Arr_2_Dim [50] [50];
-
-typedef struct record 
-    {
-    struct record *Ptr_Comp;
-    Enumeration    Discr;
-    union {
-          struct {
-                  Enumeration Enum_Comp;
-                  int         Int_Comp;
-                  char        Str_Comp [31];
-                  } var_1;
-          struct {
-                  Enumeration E_Comp_2;
-                  char        Str_2_Comp [31];
-                  } var_2;
-          struct {
-                  char        Ch_1_Comp;
-                  char        Ch_2_Comp;
-                  } var_3;
-          } variant;
-      } Rec_Type, *Rec_Pointer;
-
-
diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_1.c b/lib/CPUs/MIPS/bsp/examples/dhry_1.c
deleted file mode 100644
index f7b8373..0000000
--- a/lib/CPUs/MIPS/bsp/examples/dhry_1.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- ****************************************************************************
- *
- *                   "DHRYSTONE" Benchmark Program
- *                   -----------------------------
- *
- *  Version:    C, Version 2.1
- *
- *  File:       dhry_1.c (part 2 of 3)
- *
- *  Date:       May 25, 1988
- *
- *  Author:     Reinhold P. Weicker
- *
- ****************************************************************************
- */
-
-#include "dhry.h"
-
-/* Global Variables: */
-
-Rec_Pointer     Ptr_Glob,
-                Next_Ptr_Glob;
-int             Int_Glob;
-Boolean         Bool_Glob;
-char            Ch_1_Glob,
-                Ch_2_Glob;
-int             Arr_1_Glob [50];
-int             Arr_2_Glob [50] [50];
-
-extern char     *malloc ();
-Enumeration     Func_1 ();
-  /* forward declaration necessary since Enumeration may not simply be int */
-
-#ifndef REG
-        Boolean Reg = false;
-#define REG
-        /* REG becomes defined as empty */
-        /* i.e. no register variables   */
-#else
-        Boolean Reg = true;
-#endif
-
-/* variables for time measurement: */
-
-#ifdef TIMES
-struct tms      time_info;
-                /* see library function "times" */
-#define Too_Small_Time (2*HZ)
-                /* Measurements should last at least about 2 seconds */
-#endif
-#ifdef TIME
-extern long     time();
-                /* see library function "time"  */
-#define Too_Small_Time 2
-                /* Measurements should last at least 2 seconds */
-#endif
-#ifdef MSC_CLOCK
-extern clock_t	clock();
-#define Too_Small_Time (2*HZ)
-#endif
-
-long            Begin_Time,
-                End_Time,
-                User_Time;
-float           Microseconds,
-                Dhrystones_Per_Second;
-
-/* end of variables for time measurement */
-
-
-main ()
-/*****/
-
-  /* main program, corresponds to procedures        */
-  /* Main and Proc_0 in the Ada version             */
-{
-        One_Fifty       Int_1_Loc;
-  REG   One_Fifty       Int_2_Loc;
-        One_Fifty       Int_3_Loc;
-  REG   char            Ch_Index;
-        Enumeration     Enum_Loc;
-        Str_30          Str_1_Loc;
-        Str_30          Str_2_Loc;
-  REG   int             Run_Index;
-  REG   int             Number_Of_Runs;
-
-  /* Initializations */
-
-  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
-  Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
-
-  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
-  Ptr_Glob->Discr                       = Ident_1;
-  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
-  Ptr_Glob->variant.var_1.Int_Comp      = 40;
-  strcpy (Ptr_Glob->variant.var_1.Str_Comp,
-          "DHRYSTONE PROGRAM, SOME STRING");
-  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
-
-  Arr_2_Glob [8][7] = 10;
-        /* Was missing in published program. Without this statement,    */
-        /* Arr_2_Glob [8][7] would have an undefined value.             */
-        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
-        /* overflow may occur for this array element.                   */
-
-  /*
-  printf ("\n");
-  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
-  printf ("\n");
-  if (Reg)
-  {
-    printf ("Program compiled with 'register' attribute\n");
-    printf ("\n");
-  }
-  else
-  {
-    printf ("Program compiled without 'register' attribute\n");
-    printf ("\n");
-  }
-  printf ("Please give the number of runs through the benchmark: ");
-  {
-    int n;
-    scanf ("%d", &n);
-    Number_Of_Runs = n;
-  }
-  printf ("\n");
-  */
-#ifdef NRUNS
-    Number_Of_Runs = NRUNS;
-#else
-    Number_Of_Runs = 2000000;
-#endif
-  printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs);
-
-  /***************/
-  /* Start timer */
-  /***************/
-
-#ifdef TIMES
-  times (&time_info);
-  Begin_Time = (long) time_info.tms_utime;
-#endif
-#ifdef TIME
-  Begin_Time = time ( (long *) 0);
-#endif
-#ifdef MSC_CLOCK
-  Begin_Time = clock();
-#endif
-
-  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
-  {
-
-    Proc_5();
-    Proc_4();
-      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
-    Int_1_Loc = 2;
-    Int_2_Loc = 3;
-    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
-    Enum_Loc = Ident_2;
-    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
-      /* Bool_Glob == 1 */
-    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
-    {
-      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
-        /* Int_3_Loc == 7 */
-      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
-        /* Int_3_Loc == 7 */
-      Int_1_Loc += 1;
-    } /* while */
-      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
-    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
-      /* Int_Glob == 5 */
-    Proc_1 (Ptr_Glob);
-    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
-                             /* loop body executed twice */
-    {
-      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
-          /* then, not executed */
-        {
-        Proc_6 (Ident_1, &Enum_Loc);
-        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
-        Int_2_Loc = Run_Index;
-        Int_Glob = Run_Index;
-        }
-    }
-      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
-    Int_2_Loc = Int_2_Loc * Int_1_Loc;
-    Int_1_Loc = Int_2_Loc / Int_3_Loc;
-    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
-      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
-    Proc_2 (&Int_1_Loc);
-      /* Int_1_Loc == 5 */
-
-  } /* loop "for Run_Index" */
-
-  /**************/
-  /* Stop timer */
-  /**************/
-
-#ifdef TIMES
-  times (&time_info);
-  End_Time = (long) time_info.tms_utime;
-#endif
-#ifdef TIME
-  End_Time = time ( (long *) 0);
-#endif
-#ifdef MSC_CLOCK
-  End_Time = clock();
-#endif
-  /*
-  printf ("Execution ends\n");
-  printf ("\n");
-  printf ("Final values of the variables used in the benchmark:\n");
-  printf ("\n");
-  printf ("Int_Glob:            %d\n", Int_Glob);
-  printf ("        should be:   %d\n", 5);
-  printf ("Bool_Glob:           %d\n", Bool_Glob);
-  printf ("        should be:   %d\n", 1);
-  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
-  printf ("        should be:   %c\n", 'A');
-  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
-  printf ("        should be:   %c\n", 'B');
-  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
-  printf ("        should be:   %d\n", 7);
-  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
-  printf ("        should be:   Number_Of_Runs + 10\n");
-  printf ("Ptr_Glob->\n");
-  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
-  printf ("        should be:   (implementation-dependent)\n");
-  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
-  printf ("        should be:   %d\n", 0);
-  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
-  printf ("        should be:   %d\n", 2);
-  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
-  printf ("        should be:   %d\n", 17);
-  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
-  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
-  printf ("Next_Ptr_Glob->\n");
-  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
-  printf ("        should be:   (implementation-dependent), same as above\n");
-  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
-  printf ("        should be:   %d\n", 0);
-  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
-  printf ("        should be:   %d\n", 1);
-  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
-  printf ("        should be:   %d\n", 18);
-  printf ("  Str_Comp:          %s\n",
-                                Next_Ptr_Glob->variant.var_1.Str_Comp);
-  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
-  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
-  printf ("        should be:   %d\n", 5);
-  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
-  printf ("        should be:   %d\n", 13);
-  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
-  printf ("        should be:   %d\n", 7);
-  printf ("Enum_Loc:            %d\n", Enum_Loc);
-  printf ("        should be:   %d\n", 1);
-  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
-  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
-  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
-  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
-  printf ("\n");
-
-*/
-  User_Time = End_Time - Begin_Time;
-
-  if (User_Time < Too_Small_Time)
-  {
-    printf ("Measured time too small to obtain meaningful results\n");
-    printf ("Please increase number of runs\n");
-    printf ("\n");
-  }
-  else
-  {
-#ifdef TIME
-    Microseconds = (float) User_Time * Mic_secs_Per_Second
-                        / (float) Number_Of_Runs;
-    Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time;
-#else
-    Microseconds = (float) User_Time * Mic_secs_Per_Second
-                        / ((float) HZ * ((float) Number_Of_Runs));
-    Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs)
-                        / (float) User_Time;
-#endif
-    printf ("Microseconds for one run through Dhrystone: ");
-    printf ("%6.1f \n", Microseconds);
-    printf ("Dhrystones per Second:                      ");
-    printf ("%6.1f \n", Dhrystones_Per_Second);
-    printf ("\n");
-    printf ("This equals to %6.1f DMIPS\n", Dhrystones_Per_Second/1757);
-  }
-
-}
-
-
-Proc_1 (Ptr_Val_Par)
-/******************/
-
-REG Rec_Pointer Ptr_Val_Par;
-    /* executed once */
-{
-  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
-                                        /* == Ptr_Glob_Next */
-  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
-  /* corresponds to "rename" in Ada, "with" in Pascal           */
-
-  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
-  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
-  Next_Record->variant.var_1.Int_Comp
-        = Ptr_Val_Par->variant.var_1.Int_Comp;
-  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
-  Proc_3 (&Next_Record->Ptr_Comp);
-    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp
-                        == Ptr_Glob->Ptr_Comp */
-  if (Next_Record->Discr == Ident_1)
-    /* then, executed */
-  {
-    Next_Record->variant.var_1.Int_Comp = 6;
-    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp,
-           &Next_Record->variant.var_1.Enum_Comp);
-    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
-    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
-           &Next_Record->variant.var_1.Int_Comp);
-  }
-  else /* not executed */
-    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
-} /* Proc_1 */
-
-
-Proc_2 (Int_Par_Ref)
-/******************/
-    /* executed once */
-    /* *Int_Par_Ref == 1, becomes 4 */
-
-One_Fifty   *Int_Par_Ref;
-{
-  One_Fifty  Int_Loc;
-  Enumeration   Enum_Loc;
-
-  Int_Loc = *Int_Par_Ref + 10;
-  do /* executed once */
-    if (Ch_1_Glob == 'A')
-      /* then, executed */
-    {
-      Int_Loc -= 1;
-      *Int_Par_Ref = Int_Loc - Int_Glob;
-      Enum_Loc = Ident_1;
-    } /* if */
-  while (Enum_Loc != Ident_1); /* true */
-} /* Proc_2 */
-
-
-Proc_3 (Ptr_Ref_Par)
-/******************/
-    /* executed once */
-    /* Ptr_Ref_Par becomes Ptr_Glob */
-
-Rec_Pointer *Ptr_Ref_Par;
-
-{
-  if (Ptr_Glob != Null)
-    /* then, executed */
-    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
-  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
-} /* Proc_3 */
-
-
-Proc_4 () /* without parameters */
-/*******/
-    /* executed once */
-{
-  Boolean Bool_Loc;
-
-  Bool_Loc = Ch_1_Glob == 'A';
-  Bool_Glob = Bool_Loc | Bool_Glob;
-  Ch_2_Glob = 'B';
-} /* Proc_4 */
-
-
-Proc_5 () /* without parameters */
-/*******/
-    /* executed once */
-{
-  Ch_1_Glob = 'A';
-  Bool_Glob = false;
-} /* Proc_5 */
-
-
-        /* Procedure for the assignment of structures,          */
-        /* if the C compiler doesn't support this feature       */
-#ifdef  NOSTRUCTASSIGN
-memcpy (d, s, l)
-register char   *d;
-register char   *s;
-register int    l;
-{
-        while (l--) *d++ = *s++;
-}
-#endif
-
-
diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_2.c b/lib/CPUs/MIPS/bsp/examples/dhry_2.c
deleted file mode 100644
index 63a3d3e..0000000
--- a/lib/CPUs/MIPS/bsp/examples/dhry_2.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- ****************************************************************************
- *
- *                   "DHRYSTONE" Benchmark Program
- *                   -----------------------------
- *                                                                            
- *  Version:    C, Version 2.1
- *                                                                            
- *  File:       dhry_2.c (part 3 of 3)
- *
- *  Date:       May 25, 1988
- *
- *  Author:     Reinhold P. Weicker
- *
- ****************************************************************************
- */
-
-#include "dhry.h"
-
-#ifndef REG
-#define REG
-        /* REG becomes defined as empty */
-        /* i.e. no register variables   */
-#endif
-
-extern  int     Int_Glob;
-extern  char    Ch_1_Glob;
-
-
-Proc_6 (Enum_Val_Par, Enum_Ref_Par)
-/*********************************/
-    /* executed once */
-    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
-
-Enumeration  Enum_Val_Par;
-Enumeration *Enum_Ref_Par;
-{
-  *Enum_Ref_Par = Enum_Val_Par;
-  if (! Func_3 (Enum_Val_Par))
-    /* then, not executed */
-    *Enum_Ref_Par = Ident_4;
-  switch (Enum_Val_Par)
-  {
-    case Ident_1: 
-      *Enum_Ref_Par = Ident_1;
-      break;
-    case Ident_2: 
-      if (Int_Glob > 100)
-        /* then */
-      *Enum_Ref_Par = Ident_1;
-      else *Enum_Ref_Par = Ident_4;
-      break;
-    case Ident_3: /* executed */
-      *Enum_Ref_Par = Ident_2;
-      break;
-    case Ident_4: break;
-    case Ident_5: 
-      *Enum_Ref_Par = Ident_3;
-      break;
-  } /* switch */
-} /* Proc_6 */
-
-
-Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
-/**********************************************/
-    /* executed three times                                      */ 
-    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
-    /*                  Int_Par_Ref becomes 7                    */
-    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
-    /*                  Int_Par_Ref becomes 17                   */
-    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
-    /*                  Int_Par_Ref becomes 18                   */
-One_Fifty       Int_1_Par_Val;
-One_Fifty       Int_2_Par_Val;
-One_Fifty      *Int_Par_Ref;
-{
-  One_Fifty Int_Loc;
-
-  Int_Loc = Int_1_Par_Val + 2;
-  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
-} /* Proc_7 */
-
-
-Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
-/*********************************************************************/
-    /* executed once      */
-    /* Int_Par_Val_1 == 3 */
-    /* Int_Par_Val_2 == 7 */
-Arr_1_Dim       Arr_1_Par_Ref;
-Arr_2_Dim       Arr_2_Par_Ref;
-int             Int_1_Par_Val;
-int             Int_2_Par_Val;
-{
-  REG One_Fifty Int_Index;
-  REG One_Fifty Int_Loc;
-
-  Int_Loc = Int_1_Par_Val + 5;
-  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
-  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
-  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
-  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
-    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
-  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
-  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
-  Int_Glob = 5;
-} /* Proc_8 */
-
-
-Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
-/*************************************************/
-    /* executed three times                                         */
-    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
-    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
-    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
-
-Capital_Letter   Ch_1_Par_Val;
-Capital_Letter   Ch_2_Par_Val;
-{
-  Capital_Letter        Ch_1_Loc;
-  Capital_Letter        Ch_2_Loc;
-
-  Ch_1_Loc = Ch_1_Par_Val;
-  Ch_2_Loc = Ch_1_Loc;
-  if (Ch_2_Loc != Ch_2_Par_Val)
-    /* then, executed */
-    return (Ident_1);
-  else  /* not executed */
-  {
-    Ch_1_Glob = Ch_1_Loc;
-    return (Ident_2);
-   }
-} /* Func_1 */
-
-
-Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
-/*************************************************/
-    /* executed once */
-    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
-    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
-
-Str_30  Str_1_Par_Ref;
-Str_30  Str_2_Par_Ref;
-{
-  REG One_Thirty        Int_Loc;
-      Capital_Letter    Ch_Loc;
-
-  Int_Loc = 2;
-  while (Int_Loc <= 2) /* loop body executed once */
-    if (Func_1 (Str_1_Par_Ref[Int_Loc],
-                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
-      /* then, executed */
-    {
-      Ch_Loc = 'A';
-      Int_Loc += 1;
-    } /* if, while */
-  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
-    /* then, not executed */
-    Int_Loc = 7;
-  if (Ch_Loc == 'R')
-    /* then, not executed */
-    return (true);
-  else /* executed */
-  {
-    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
-      /* then, not executed */
-    {
-      Int_Loc += 7;
-      Int_Glob = Int_Loc;
-      return (true);
-    }
-    else /* executed */
-      return (false);
-  } /* if Ch_Loc */
-} /* Func_2 */
-
-
-Boolean Func_3 (Enum_Par_Val)
-/***************************/
-    /* executed once        */
-    /* Enum_Par_Val == Ident_3 */
-Enumeration Enum_Par_Val;
-{
-  Enumeration Enum_Loc;
-
-  Enum_Loc = Enum_Par_Val;
-  if (Enum_Loc == Ident_3)
-    /* then, executed */
-    return (true);
-  else /* not executed */
-    return (false);
-} /* Func_3 */
-
diff --git a/lib/CPUs/MIPS/bsp/examples/dttl.c b/lib/CPUs/MIPS/bsp/examples/dttl.c
deleted file mode 100644
index 8efffa2..0000000
--- a/lib/CPUs/MIPS/bsp/examples/dttl.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* dttl.c -- simulation of Cassini/Huygens symbol synchronizer loop
- *
- * Author:           Lorenzo Simone's (matlab script)
- * Modifications by: Jon Hamkins (conversion to C, support routines,
- *                   memory requirement reductions)
- * Last Revised:     Wed Jan 31 10:47:52 PST 2001
- */
-#define	M_PI	3.1415926535897932384626433832795
-
-#include <math.h>
-#include <stdio.h>
-#include "random.h"
-
-/* global variables */
-int delay,
-   L;  /* samples per symbol */
-double Pt, /* transition density */
-   sigma;  /* noise standard deviation */
-long seed=-123;
-
-/* This function simulates a large 1-dimensional array without requiring
- * storage for the whole array.  This is possible because the array is
- * accessed in roughly increasing indices.  Thus, we only need to
- * store a few symbols worth of samples in the array, and we can reuse
- * the array indices as time goes on. */
-int drint(double v)
-{
-	return (int)(v+0.5);
-}
-
-double
-rec(int idx)
-{
-   static int firsttime = 1,
-      max,                  /* maximum index containing data */
-      mod,                  /* length of ring buffer */
-      b;                    /* value of last transmitted bit */
-   static double r[2000];   /* need several symbols worth of samples */
-   int i,j,k;
-
-   /* First time, store samples for random delay and first few symbols */
-   if (firsttime==1) {
-      firsttime=0;
-      for (i=0; i<delay; i++) r[i] = 0;  /* random delay */
-      b = (ran1(&seed)>0.5) ? 1 : -1; /* first random symbol */
-      for (j=0; j<3; j++) { /* 3 binary symbols with transition Pt */
-         b = (ran1(&seed)>Pt) ? b : -b;  /* next symbol value */
-         for (k=0; k<L; k++) r[i++] = b + sigma*gaussian(&seed);
-      }
-      max = i-1;
-      mod = i;
-   }
-   if (idx>max)  /* check if we need to create another sample */
-   {
-      b = (ran1(&seed)>Pt) ? b : -b;  /* next symbol value */
-      /* generate samples for one symbol and store in ring buffer */
-      for (i=1; i<=L; i++) r[(int)(fmod(max+i,mod))] = b+sigma*gaussian(&seed);
-      max += L;  /* maximum index for which samples exist */
-   }
-   /* return appropriate sample from ring buffer */
-   return(r[(int)(fmod(idx,mod))]);
-}
-
-main()
-{
-   double
-      detout,            /* detector output */
-      I, old_I,          /* in-phase accumulations */
-      Q, old_Q,          /* quadrature accumulations */
-      T,                 /* transition detection */
-      theta,             /* baseband NCO output (radians) */
-      lambda,            /* normalized timing error (symbols) */
-      A, alfa, Ampl, Bl, Df,
-      DR, Es_No, Es_No_lin, Fc1, Fc2, Fvco, Fs, Kd, Kv,
-      lambda_ss_sim = 0., lambda_ss_th, No, P, P_No,
-      sigma_lambda_sim = 0., sigma_lambda_th, SNR_sim, SNR_th, tau, Tc1, Tc2,
-      time, Ts, x1, Y, bit_I, bit_Q, bit;
-   int i, j, k, N, offset, k1, k2, EOB;
-   FILE *p1, *p2, *p3, *p4, *p5;
-
-   /* Data settings */
-   Fc1 = 48000;        /* sample rate at DTTL input (F1/2 = 8.215MHz/2) */
-   Tc1 = 1./Fc1;
-
-   DR = 4800;           /* data rate (symb/sec)  */
-
-   Fc2 = DR;             /* sampling rate pre-detection */
-   Tc2 = 1./Fc2;
-
-   L = drint(Tc2/Tc1);    /* samples per symbol in the arm filters */
-   offset = drint(L/2.);
-
-   Es_No = 600.;                    /* dB */
-   P_No = Es_No+10.*log10(DR);     /* data power-over-noise spectral density */
-                                   /* ratio (dBHz) */
-
-   N = 2500;                       /* number of symbols to simulate */
-   Pt=.5;                          /* Transition density */
-
-   Bl=0.01*DR;                     /* loop bandwidth (Hz)  */
-   Df=0.001*DR;                      /* frequency offset */
-   Fvco=DR+Df;
-
-   tau=ran1(&seed)-.5;             /* set symbol timing offset, -.5 to .5 */
-   delay=drint(2.*L+tau*L+1);       /* channel delay */
-
-   P=1.;                           /* data power */
-   Ampl=sqrt(P);
-
-   No=10.*log10(P*Tc2)-Es_No;      /* noise spectral density (dBW/Hz)  */
-   sigma=sqrt(pow(10.,0.1*No)/(2.*Tc1));
-   printf("sigma=%f\n",sigma);
-
-   /* DPLL settings */
-   Fs=DR;                           /* loop sampling frequency (Hz) */
-   Ts=1./Fs;                        /* loop sampling time (s) */
-
-   /* Loop gain */
-   Kd=2.*Ampl*Pt;                   /* phase detector gain (quants/rad) */
-                                    /* @ high Es/No */
-   Kv=1.;                           /* VCO gain (rad/quants) */
-
-   /* Analog loop filter components */
-   alfa=4.*Bl/(Kd*Kv);
-
-   /* Digital loop filter components */
-   A=alfa*Ts;
-
-   /* Initial condition */
-   theta = 0;
-   old_I=1;
-   old_Q=1;
-   x1=0;
-   Y=0;
-
-   /* Plot data files */
-//   p1 = fopen("plot1.dat","w");  /* theta */
-//   p2 = fopen("plot2.dat","w");  /* lambda */
-//   p3 = fopen("plot3.dat","w");  /* detout */
-//   p4 = fopen("plot4.dat","w");  /* I-Data */
-//   p5 = fopen("plot5.dat","w");  /* Q-Data */
-
-   k1 = drint(0.5*N);
-   k2 = N;
-
-   printf("Data rate: %.0f symbols/sec\n",DR);
-   printf("Sample rate at DTTL input: %.0f samples/sec\n",Fc1);
-   printf("Samples per symbol: %d\n",L);
-   printf("Random delay set to: %f symbols (%d samples)\n",tau,delay);
-   printf("Transition density used in random bit generation: %f\n",Pt);
-   printf("Es/No: %f dB\n",Es_No);
-   printf("Loop bandwidth: %f Hz\n",Bl);
-   printf("Doppler: %f Hz\n",Df);
-   printf("Simulation length: %d symbols (%d samples)\n\n",N,N*L+delay);
-
-   /* Simulation Loop */
-   for (i=2; i<=N; i++)
-   {
-	  /* loop over symbols */
-      /* find start of in-phase integration */
-      for (j=1; j < L; j++)
-	  {
-         if (fmod(theta + 2*M_PI * Fvco*(j+1+(i-1)*(Fc1/DR))/Fc1, 2*M_PI)
-		   < fmod(theta + 2*M_PI * Fvco*(j  +(i-1)*(Fc1/DR))/Fc1, 2*M_PI))
-           break;
-		/* one could replace loop above with a direct calculation such as: */
-		/* j=ceil((1.-modulo(theta/(2*M_PI),1.))/(Fvco*Tc1))-1.; */
-		/* j+1 is the first index in the block */
-		EOB=j+(i-1)*L;  /* End of Block */
-	  }
-      /* In-phase integrator */
-      bit_I = 0.;
-	  printf("Symbol # %d\n", i);
-	  printf("I[%d:%d] :\n", EOB-L+1, EOB);
-      for (j=EOB-L+1; j<=EOB; j++)
-	  {
-		  bit = rec(j);
-		  if (bit > 0)
-			  printf("-");
-		  else
-			  printf("_");
-
-		  bit_I += bit;
-	  }
-	  printf("\n");
-  	  I = bit_I;
-
-      /* Mid-Phase integrator */
-      bit_Q = 0.;
-	  printf("Q[%d:%d] :\n", EOB-L+offset+1, EOB+offset);
-      for (j=EOB-L+offset+1; j<=EOB+offset; j++)
-	  {
-		  bit = rec(j);
-		  if (bit > 0)
-			  printf("-");
-		  else
-			  printf("_");
-
-		  bit_Q += bit;
-	  }
-	  printf("\n\n");
-	  Q = bit_Q;
-
-      Q *= 2.*M_PI/(Tc2/Tc1);
-
-      /* Transition Detector */
-      I = (I > 0) ? 1. : -1.;  /* hard limiter */
-      T = 0.5*(I - old_I);
-
-      /* Detector Output */
-      detout = fmod(old_Q*T,2*M_PI);
-
-      /* Save accumulations for next time through loop */
-      old_I = I;
-      old_Q = Q;
-      if (fabs(detout)>M_PI)
-         detout = -detout+2*M_PI*((detout>0) ? 1. : -1.);
-
-      /* NCO */
-      Y += detout*A; /* Loop filter */
-      theta=Kv*Y;  /* phase */
-//      lambda = theta/(2.*M_PI)+(i*Tc2*Df+tau);  /* normalized error */
-      lambda = theta/(2.*M_PI)+(i*(Fvco/DR -1) + tau);  /* normalized error */
-
-     /* error mean and variance calculation */
-      lambda_ss_sim += lambda;  /* partial sum */
-      sigma_lambda_sim += lambda*lambda; /* partial sum of squares */
-
-      /* store phase and normalized error to data files */
-//      fprintf(p1,"%f %f\n",(double)i,theta);
-//      fprintf(p2,"%f %f\n",(double)i,lambda);
-//      fprintf(p3,"%f %f\n",(double)i,detout);
-//      fprintf(p4,"%f %f\n",(double)i,I);
-//      fprintf(p5,"%f %f\n",(double)i,Q);
-   }
-//   fclose(p1);
-//   fclose(p2);
-//   fclose(p3);
-//   fclose(p4);
-//   fclose(p5);
-
-   /* Statistics Analysis */
-   /* ------------------- */
-   /* complete the mean and variance calculation */
-   lambda_ss_sim /= N;
-   sigma_lambda_sim = sigma_lambda_sim/N - lambda_ss_sim*lambda_ss_sim;
-   Es_No_lin = pow(10.,0.1*Es_No);
-//   sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*pow(erf(sqrt(Es_No_lin)),2.));
-   sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*Es_No_lin);
-   SNR_sim = -10*log10(sigma_lambda_sim);
-   SNR_th = -10*log10(sigma_lambda_th);
-   /* Steady-State error */
-   lambda_ss_th=Df/(4.*Bl);
-   printf("Simulation: var: %f rad^2  loop SNR: %f dB ss error: %f%%\n",
-         sigma_lambda_sim, SNR_sim, 100.*lambda_ss_sim);
-   printf("Theory:     var: %f rad^2  loop SNR: %f dB ss error: %f%%\n",
-         sigma_lambda_th, SNR_th, 100.*lambda_ss_th);
-//   system("gnuplot < plot1.gp");
-//   system("gnuplot < plot2.gp");
-      printf("Done.\n");
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/gunzip.c b/lib/CPUs/MIPS/bsp/examples/gunzip.c
deleted file mode 100644
index 066c88e..0000000
--- a/lib/CPUs/MIPS/bsp/examples/gunzip.c
+++ /dev/null
@@ -1,198 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <ctype.h>
-#include <time.h>
-
-#define	CPU_FREQ_HZ	100000000
-#include "libsys.h"
-
-#include "crc32.h"
-#include "inflate.h"
-
-char buffer[1024*1024];
-char * volatile pPtr_r;
-char * volatile pPtr_w;
-volatile int timeout_cnt;
-volatile int file_len;
-
-void handler3(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART0_DATA;
-
-	while(0x200 & *pUART_stat)
-	{
-//		sputs("w: "); print_word((int)pPtr_w); sputs("\n");
-		if (pPtr_w == &buffer[sizeof(buffer)-1])
-			pPtr_w = buffer;
-		*(pPtr_w++) = *pUART_data;
-		timeout_cnt = 100;
-		file_len++;
-	}
-
-}
-
-int READBYTE(z_stream *zs) {
-   if (zs->avail_in <= 0)
-     return -1;
-
-   zs->avail_in --;
-   return *(zs->next_in ++);
-}
-
-#define MAX_BUFOUT	16*1024*1024
-int main(int argc, char **argv)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART0_STAT;
-	unsigned char outData[MAX_BUFOUT];
-	FILE *infp;
-	int i, gpflags, tmp[4];
-	unsigned long size, crc;
-	unsigned char *fileData;
-	unsigned long bytes, InflatedSize, InflatedCRC, speed_count;
-	z_stream zs;
-	time_t start_time, work_time;
-
-	UART0_setbaud(460800);
-
-	printf("Reading gzipped stream..\n");
-
-	pPtr_r = buffer;
-	pPtr_w = buffer;
-	*pUART_stat = (1 << 6);
-	interrupt_register(3, handler3);
-	interrupt_enable(3);
-
-	file_len = 0;
-	timeout_cnt = 1000000;
-	while(timeout_cnt--)
-	{
-		sleep(1);
-	}
-
-	printf("file_len: %d\n", file_len);
-   bytes = file_len;
-   fileData = pPtr_r;
-
-   zs.next_in = fileData;
-   zs.avail_in = (unsigned int) bytes;
-   zs.next_out = outData;
-   zs.avail_out = MAX_BUFOUT;
-
-   tmp[0] = READBYTE(&zs);
-   if (tmp[0] == -1)
-     {
-	// error reading from file
-	printf("error reading data from file\n");
-	return 0;
-     }
-   tmp[1] = READBYTE(&zs);
-
-   if (tmp[0] != 0x1f || tmp[1] != 0x8b) {
-//      fprintf(stderr, "Magic number mismatch 0x%02x%02x\n",
-//	      tmp[0], tmp[1]);
-      return 20;
-   }
-
-   tmp[0] = READBYTE(&zs);
-   if(tmp[0] != 8) {
-//      fprintf(stderr, "Unknown compression method: 0x%02x\n", tmp[0]);
-      return 20;
-   }
-
-   gpflags = READBYTE(&zs);
-   if ((gpflags & ~0x1f)) {
-      printf("Unknown flags set!\n");
-   }
-
-   /* Skip file modification time (4 bytes) */
-   READBYTE(&zs);
-   READBYTE(&zs);
-   READBYTE(&zs);
-   READBYTE(&zs);
-   /* Skip extra flags and operating system fields (2 bytes) */
-   READBYTE(&zs);
-   READBYTE(&zs);
-
-   if ((gpflags & 4)) {
-      /* Skip extra field */
-      tmp[0] = READBYTE(&zs);
-      tmp[1] = READBYTE(&zs);
-      i = tmp[0] + 256*tmp[1];
-      while (i--)
-	{
-	   READBYTE(&zs);
-	}
-   }
-   if((gpflags & 8)) {
-      while((READBYTE(&zs))) {
-      }
-   }
-   if((gpflags & 16)) {
-      while((READBYTE(&zs))) {
-      }
-   }
-   if((gpflags & 2)) {
-      /* Skip CRC16 */
-      READBYTE(&zs);
-      READBYTE(&zs);
-   }
-
-	printf("Go\n");
-	// normal test
-	start_time = clock();
-	if (InflateData(&zs))
-	{
-		printf("Problem during decompression!\n");
-		return 0;
-	}
-	work_time = clock() - start_time;
-
-
-/*
-	// speed test
-	fprintf(stdout, "SPEED TEST!\n");
-	speed_count = 0;
-	while (time(NULL) - start_time < 20)
-	  {
-	     zs_speed.next_in = zs.next_in;
-	     zs_speed.next_out = zs.next_out;
-	     zs_speed.avail_in = zs.avail_in;
-	     zs_speed.avail_out = zs.avail_out;
-	     if (InflateData(&zs_speed))
-	       {
-		  fprintf(stdout, "Problem during decompression!\n");
-		  return 0;
-	       }
-	     speed_count ++;
-	  }
-	fprintf(stdout, "speed count %ld\n", speed_count);
-	zs.next_in = zs_speed.next_in;
-	zs.next_out = zs_speed.next_out;
-	zs.avail_in = zs_speed.avail_in;
-	zs.avail_out = zs_speed.avail_out;
-*/
-
-	crc = READBYTE(&zs);
-	crc |= (READBYTE(&zs)<<8);
-	crc |= (READBYTE(&zs)<<16);
-	crc |= (READBYTE(&zs)<<24);
-
-	size = READBYTE(&zs);
-	size |= (READBYTE(&zs)<<8);
-	size |= (READBYTE(&zs)<<16);
-	size |= (READBYTE(&zs)<<24);
-
-	InflatedSize = MAX_BUFOUT - zs.avail_out;
-	InflatedCRC = MakeCRC32(outData, InflatedSize, 0);
-
-//	write(1, outData, InflatedSize);
-	fprintf(stdout, "CRC:  %08lx %08lx %s\n", crc, InflatedCRC,	(crc != InflatedCRC)?"**error**":"");
-	fprintf(stdout, "Size: %08lx %08lx %s\n", size, InflatedSize, (size != InflatedSize)?"**error**":"");
-	fprintf(stdout, "Time for decompression was %.2f seconds\n", (float)work_time/1000);
-	fprintf(stdout, "Throughput is %d kByte/s\n", InflatedSize/work_time);
-
-   return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/hashtest.c b/lib/CPUs/MIPS/bsp/examples/hashtest.c
deleted file mode 100644
index b960966..0000000
--- a/lib/CPUs/MIPS/bsp/examples/hashtest.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/********************************************************************\
- *
- *      FILE:     hashtest.c
- *
- *      CONTENTS: test file for sample C-implementation of
- *                RIPEMD-160 and RIPEMD128
- *        * command line arguments:
- *           filename  -- compute hash code of file read binary
- *           -sstring  -- print string & hashcode
- *           -t        -- perform time trial
- *           -x        -- execute standard test suite, ASCII input
- *        * for linkage with rmd128.c: define RMDsize as 128
- *          for linkage with rmd160.c: define RMDsize as 160 (default)
- *      TARGET:   any computer with an ANSI C compiler
- *
- *      AUTHOR:   Antoon Bosselaers, ESAT-COSIC
- *      DATE:     18 April 1996
- *      VERSION:  1.1
- *      HISTORY:  bug in RMDonemillion() corrected
- *
- *      Copyright (c) Katholieke Universiteit Leuven
- *      1996, All Rights Reserved
- *
- *  Conditions for use of the RIPEMD-160 Software
- *
- *  The RIPEMD-160 software is freely available for use under the terms and
- *  conditions described hereunder, which shall be deemed to be accepted by
- *  any user of the software and applicable on any use of the software:
- *
- *  1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for
- *     all purposes be considered the owner of the RIPEMD-160 software and of
- *     all copyright, trade secret, patent or other intellectual property
- *     rights therein.
- *  2. The RIPEMD-160 software is provided on an "as is" basis without
- *     warranty of any sort, express or implied. K.U.Leuven makes no
- *     representation that the use of the software will not infringe any
- *     patent or proprietary right of third parties. User will indemnify
- *     K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities
- *     which may arise as a result of its use of the software. In no
- *     circumstances K.U.Leuven R&D will be held liable for any deficiency,
- *     fault or other mishappening with regard to the use or performance of
- *     the software.
- *  3. User agrees to give due credit to K.U.Leuven in scientific publications
- *     or communications in relation with the use of the RIPEMD-160 software
- *     as follows: RIPEMD-160 software written by Antoon Bosselaers,
- *     available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/.
- *
-\********************************************************************/
-#ifndef RMDsize
-#define RMDsize 160
-#endif
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <time.h>
-#include <string.h>
-#if RMDsize == 128
-#include "rmd128.h"
-#elif RMDsize == 160
-#include "rmd160.h"
-#endif
-
-#define TEST_BLOCK_SIZE 8000
-#define TEST_BLOCKS 1250
-#define TEST_BYTES ((long)TEST_BLOCK_SIZE * (long)TEST_BLOCKS)
-
-/********************************************************************/
-
-byte *RMD(byte *message)
-/*
- * returns RMD(message)
- * message should be a string terminated by '\0'
- */
-{
-   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E))   */
-   static byte   hashcode[RMDsize/8]; /* for final hash-value         */
-   dword         X[16];               /* current 16-word chunk        */
-   unsigned int  i;                   /* counter                      */
-   dword         length;              /* length in bytes of message   */
-   dword         nbytes;              /* # of bytes not yet processed */
-
-   /* initialize */
-   MDinit(MDbuf);
-   length = (dword)strlen((char *)message);
-
-   /* process message in 16-word chunks */
-   for (nbytes=length; nbytes > 63; nbytes-=64) {
-      for (i=0; i<16; i++) {
-         X[i] = BYTES_TO_DWORD(message);
-         message += 4;
-      }
-      compress(MDbuf, X);
-   }                                    /* length mod 64 bytes left */
-
-   /* finish: */
-   MDfinish(MDbuf, message, length, 0);
-
-   for (i=0; i<RMDsize/8; i+=4) {
-      hashcode[i]   =  MDbuf[i>>2];         /* implicit cast to byte  */
-      hashcode[i+1] = (MDbuf[i>>2] >>  8);  /*  extracts the 8 least  */
-      hashcode[i+2] = (MDbuf[i>>2] >> 16);  /*  significant bits.     */
-      hashcode[i+3] = (MDbuf[i>>2] >> 24);
-   }
-
-   return (byte *)hashcode;
-}
-
-/********************************************************************/
-
-byte *RMDbinary(char *fname)
-/*
- * returns RMD(message in file fname)
- * fname is read as binary data.
- */
-{
-   FILE         *mf;                  /* pointer to file <fname>      */
-   byte          data[1024];          /* contains current mess. block */
-   dword         nbytes;              /* length of this block         */
-   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E))   */
-   static byte   hashcode[RMDsize/8]; /* for final hash-value         */
-   dword         X[16];               /* current 16-word chunk        */
-   unsigned int  i, j;                /* counters                     */
-   dword         length[2];           /* length in bytes of message   */
-   dword         offset;              /* # of unprocessed bytes at    */
-                                      /*          call of MDfinish    */
-
-   /* initialize */
-   if ((mf = fopen(fname, "rb")) == NULL) {
-      fprintf(stderr, "\nRMDbinary: cannot open file \"%s\".\n",
-              fname);
-      exit(1);
-   }
-   MDinit(MDbuf);
-   length[0] = 0;
-   length[1] = 0;
-
-   while ((nbytes = fread(data, 1, 1024, mf)) != 0) {
-      /* process all complete blocks */
-      for (i=0; i<(nbytes>>6); i++) {
-         for (j=0; j<16; j++)
-            X[j] = BYTES_TO_DWORD(data+64*i+4*j);
-         compress(MDbuf, X);
-      }
-      /* update length[] */
-      if (length[0] + nbytes < length[0])
-         length[1]++;                  /* overflow to msb of length */
-      length[0] += nbytes;
-   }
-
-   /* finish: */
-   offset = length[0] & 0x3C0;   /* extract bytes 6 to 10 inclusive */
-   MDfinish(MDbuf, data+offset, length[0], length[1]);
-
-   for (i=0; i<RMDsize/8; i+=4) {
-      hashcode[i]   =  MDbuf[i>>2];
-      hashcode[i+1] = (MDbuf[i>>2] >>  8);
-      hashcode[i+2] = (MDbuf[i>>2] >> 16);
-      hashcode[i+3] = (MDbuf[i>>2] >> 24);
-   }
-
-   fclose(mf);
-
-   return (byte *)hashcode;
-}
-
-/********************************************************************/
-
-void speedtest(void)
-/*
- * A time trial routine, to measure the speed of ripemd.
- * Measures processor time required to process TEST_BLOCKS times
- *  a message of TEST_BLOCK_SIZE characters.
- */
-{
-   clock_t      t0, t1;
-   byte        *data;
-   byte         hashcode[RMDsize/8];
-   dword        X[16];
-   dword        MDbuf[RMDsize/32];
-   unsigned int i, j, k;
-
-   srand(time(NULL));
-
-   /* allocate and initialize test data */
-   if ((data = (byte*)malloc(TEST_BLOCK_SIZE)) == NULL) {
-      fprintf(stderr, "speedtest: allocation error\n");
-      exit(1);
-   }
-   for (i=0; i<TEST_BLOCK_SIZE; i++)
-      data[i] = (byte)(rand() >> 7);
-
-   /* start timer */
-   printf("\n\nRIPEMD-%u time trial. Processing %ld characters...\n",
-          RMDsize, TEST_BYTES);
-   t0 = clock();
-
-   /* process data */
-   MDinit(MDbuf);
-   for (i=0; i<TEST_BLOCKS; i++) {
-      for (j=0; j<TEST_BLOCK_SIZE; j+=64) {
-         for (k=0; k<16; k++)
-            X[k] = BYTES_TO_DWORD(data+j+4*k);
-         compress(MDbuf, X);
-      }
-   }
-   MDfinish(MDbuf, data, TEST_BYTES, 0);
-
-   /* stop timer, get time difference */
-   t1 = clock();
-   printf("\nTest input processed in %g seconds.\n",
-          (double)(t1-t0)/(double)CLOCKS_PER_SEC);
-   printf("Characters processed per second: %g\n",
-          (double)CLOCKS_PER_SEC*TEST_BYTES/((double)t1-t0));
-
-	printf("\n=> %3.2f Mbit/s\n\n", 8*(double)CLOCKS_PER_SEC*TEST_BYTES/((double)t1-t0)/(1024*1024));
-
-   for (i=0; i<RMDsize/8; i+=4) {
-      hashcode[i]   =  MDbuf[i>>2];
-      hashcode[i+1] = (MDbuf[i>>2] >>  8);
-      hashcode[i+2] = (MDbuf[i>>2] >> 16);
-      hashcode[i+3] = (MDbuf[i>>2] >> 24);
-   }
-   printf("\nhashcode: ");
-   for (i=0; i<RMDsize/8; i++)
-      printf("%02x", hashcode[i]);
-   printf("\n");
-
-   free(data);
-   return;
-}
-
-/********************************************************************/
-
-void RMDonemillion(void)
-/*
- * returns RMD() of message consisting of 1 million 'a' characters
- */
-{
-   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E)) */
-   static byte   hashcode[RMDsize/8]; /* for final hash-value       */
-   dword         X[16];               /* current 16-word chunk      */
-   unsigned int  i;                   /* counter                    */
-
-   MDinit(MDbuf);
-   memcpy(X, "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa", 32);
-   memcpy(X+8, X, 32);
-   for (i=15625; i>0; i--)
-      compress(MDbuf, X);
-   MDfinish(MDbuf, NULL, 1000000UL, 0);
-   for (i=0; i<RMDsize/8; i+=4) {
-      hashcode[i]   =  MDbuf[i>>2];
-      hashcode[i+1] = (MDbuf[i>>2] >>  8);
-      hashcode[i+2] = (MDbuf[i>>2] >> 16);
-      hashcode[i+3] = (MDbuf[i>>2] >> 24);
-   }
-   printf("\n* message: 1 million times \"a\"\n  hashcode: ");
-   for (i=0; i<RMDsize/8; i++)
-      printf("%02x", hashcode[i]);
-
-}
-
-/********************************************************************/
-
-void RMDstring(char *message, char *print)
-{
-   unsigned int  i;
-   byte         *hashcode;
-
-   hashcode = RMD((byte *)message);
-   printf("\n* message: %s\n  hashcode: ", print);
-   for (i=0; i<RMDsize/8; i++)
-      printf("%02x", hashcode[i]);
-}
-
-/********************************************************************/
-
-void testsuite (void)
-/*
- *   standard test suite
- */
-{
-   printf("\n\nRIPEMD-%u test suite results (ASCII):\n", RMDsize);
-
-   RMDstring("", "\"\" (empty string)");
-   RMDstring("a", "\"a\"");
-   RMDstring("abc", "\"abc\"");
-   RMDstring("message digest", "\"message digest\"");
-   RMDstring("abcdefghijklmnopqrstuvwxyz", "\"abcdefghijklmnopqrstuvwxyz\"");
-   RMDstring("abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq",
-             "\"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq\"");
-   RMDstring("ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789",
-             "\"A...Za...z0...9\"");
-   RMDstring("1234567890123456789012345678901234567890"
-             "1234567890123456789012345678901234567890",
-             "8 times \"1234567890\"");
-   RMDonemillion();
-   printf("\n");
-
-   return;
-}
-
-/********************************************************************/
-
-main (int argc, char *argv[])
-/*
- *  main program. calls one or more of the test routines depending
- *  on command line arguments. see the header of this file.
- *
- */
-{
-	while(1)
-	{
-//		testsuite ();
-//		printf("\n");
-		speedtest ();
-		printf("\n");
-	}
-
-	return 0;
-}
-
-/********************** end of file hashtest.c **********************/
-
diff --git a/lib/CPUs/MIPS/bsp/examples/hello.c b/lib/CPUs/MIPS/bsp/examples/hello.c
deleted file mode 100644
index e655913..0000000
--- a/lib/CPUs/MIPS/bsp/examples/hello.c
+++ /dev/null
@@ -1,19 +0,0 @@
-#include <stdio.h>
-#define	A	0.5
-#define	B	0.55
-
-_Sat long _Fract sat_add3 (_Sat long _Fract a, _Sat long _Fract b)
-{
-  return a + b;
-}
-
-long _Fract mul3 (long _Fract a, long _Fract b)
-{
-  return a * b;
-}
-
-int main()
-{
-  printf("hello %X + %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, sat_add3(A, B));
-  printf("hello %X * %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, mul3(A, B));
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/hpi.c b/lib/CPUs/MIPS/bsp/examples/hpi.c
deleted file mode 100644
index 3a21263..0000000
--- a/lib/CPUs/MIPS/bsp/examples/hpi.c
+++ /dev/null
@@ -1,949 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include "libsys.h"
-#include "hpi.h"
-
-static volatile UINT32 _g_int_active;
-static volatile UINT32 _g_mbx_return;
-static volatile UINT32 _g_mbx_in_flag;
-
-// ---------------------------------------------------------
-// Globals
-// ---------------------------------------------------------
-typedef struct _susb_t
-{
-	fp_t fptr_ept[USB_MAX_NUM_EPT];
-	void *aptr_ept[USB_MAX_NUM_EPT];
-
-	fp_t fptr_rst;
-	void *aptr_rst;
-
-	fp_t fptr_sof;
-	void *aptr_sof;
-
-	fp_t fptr_cfg;
-	void *aptr_cfg;
-
-	fp_t fptr_sus;
-	void *aptr_sus;
-
-	fp_t fptr_id;
-	void *aptr_id;
-
-	fp_t fptr_vbus;
-	void *aptr_vbus;
-
-} usb_t;
-
-static usb_t _g_usb[USB_MAX_NUM_PORTS];
-//static usb_irp_t *_g_usb_irp_ptr[USB_MAX_NUM_PORTS][USB_MAX_NUM_EPT];
-
-// ---------------------------------------------------------
-// HPI ISR
-// ---------------------------------------------------------
-void cy67k3_isr(void)
-{
-	INT32 i;
-	UINT16 sie_msg, hpi_status;
-	UINT32 port, siemsg_handled, int_handled;
-	_g_int_active = 1;
-//	sputs("--------------------------------------------------------\n");
-//	sputs("USB-Interrupt(4)\n");
-//	sputs("HPI Status   : ");
-	hpi_status = cy67k3_read_HPI_STATUS();
-//	print_word(hpi_status);
-//	sputs("\n");
-
-//	sputs("MAILBOX (REG): ");
-
-//	cy67k3_write(HPI_ADDRESS, HPI_REG_MAILBOX);
-//	print_word(cy67k3_read_HPI_DATA());
-//	sputs("\n");
-
-	int_handled = 0;
-	if (hpi_status & HPI_STATUS_MBX_IN)
-	{
-		int_handled = 1;
-//		sputs("MAILBOX (HPI): ");
-		_g_mbx_return = cy67k3_read_HPI_MAILBOX();
-		_g_mbx_in_flag = 1;
-//		print_word(_g_mbx_return);
-//		sputs("\n");
-	}
-
-	if (hpi_status & HPI_STATUS_RESET1)
-	{
-		int_handled = 1;
-		hpi_read_reg(SUSB1_REG_STATUS);
-		hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 1);
-//		sputs("RESET 1\n");
-	}
-
-	if (hpi_status & HPI_STATUS_RESET2)
-	{
-		int_handled = 1;
-		hpi_read_reg(SUSB2_REG_STATUS);
-		hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2);
-//		sputs("RESET 2\n");
-	}
-
-	if (hpi_status & HPI_STATUS_DONE1)
-	{
-		int_handled = 1;
-//		sputs("DONE 1\n");
-	}
-
-	if (hpi_status & HPI_STATUS_DONE2)
-	{
-		int_handled = 1;
-//		sputs("DONE 2\n");
-	}
-
-	if (hpi_status & HPI_STATUS_SOFEOP1)
-	{
-		int_handled = 1;
-		hpi_read_reg(SUSB1_REG_STATUS);
-//		sputs("SOF/EOP 1\n");
-	}
-
-	if (hpi_status & HPI_STATUS_SOFEOP2)
-	{
-		int_handled = 1;
-		hpi_read_reg(SUSB2_REG_STATUS);
-//		sputs("SOF/EOP 2\n");
-	}
-
-	port = 0;
-	siemsg_handled = 0;
-	if (hpi_status & HPI_STATUS_SIEMSG1)
-	{
-		int_handled = 1;
-		sie_msg = hpi_read_reg(HPI_REG_SIE1MSG);
-
-		// Reset message register
-		hpi_write_reg(HPI_REG_SIE1MSG, 0x0000);
-
-		if (sie_msg & SUSB_RST_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_rst)
-				(_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst);
-		}
-
-		if (sie_msg & SUSB_SOF_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_sof)
-				(_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof);
-		}
-
-		if (sie_msg & SUSB_CFG_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_cfg)
-				(_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg);
-		}
-
-		if (sie_msg & SUSB_SUS_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_sus)
-				(_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus);
-		}
-
-		if (sie_msg & SUSB_ID_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_id)
-				(_g_usb[port].fptr_id)(_g_usb[port].aptr_id);
-		}
-
-		if (sie_msg & SUSB_VBUS_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_vbus)
-				(_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus);
-		}
-
-		for (i=0; i < 8; i++)
-		{
-			if (sie_msg & (SUSB_EP0_MSG << i))
-			{
-				siemsg_handled = 1;
-				if (_g_usb[port].fptr_ept[i])
-					(_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]);
-			}
-		}
-		if (!siemsg_handled)
-		{
-			sputs("Unhandled SIE1 message ");
-			print_word(sie_msg);
-			sputs("!\n");
-		}
-
-	}
-	port = 1;
-	siemsg_handled = 0;
-	if (hpi_status & HPI_STATUS_SIEMSG2)
-	{
-		int_handled = 1;
-		sie_msg = hpi_read_reg(HPI_REG_SIE2MSG);
-
-		// Reset message register
-		hpi_write_reg(HPI_REG_SIE2MSG, 0x0000);
-
-		if (sie_msg & SUSB_RST_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_rst)
-				(_g_usb[port].fptr_rst)(_g_usb[port].aptr_rst);
-		}
-
-		if (sie_msg & SUSB_SOF_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_sof)
-				(_g_usb[port].fptr_sof)(_g_usb[port].aptr_sof);
-		}
-
-		if (sie_msg & SUSB_CFG_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_cfg)
-				(_g_usb[port].fptr_cfg)(_g_usb[port].aptr_cfg);
-		}
-
-		if (sie_msg & SUSB_SUS_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_sus)
-				(_g_usb[port].fptr_sus)(_g_usb[port].aptr_sus);
-		}
-
-		if (sie_msg & SUSB_ID_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_id)
-				(_g_usb[port].fptr_id)(_g_usb[port].aptr_id);
-		}
-
-		if (sie_msg & SUSB_VBUS_MSG)
-		{
-			siemsg_handled = 1;
-			if (_g_usb[port].fptr_vbus)
-				(_g_usb[port].fptr_vbus)(_g_usb[port].aptr_vbus);
-		}
-
-		for (i=0; i < 8; i++)
-		{
-			if (sie_msg & (SUSB_EP0_MSG << i))
-			{
-				siemsg_handled = 1;
-				if (_g_usb[port].fptr_ept[i])
-					(_g_usb[port].fptr_ept[i])(_g_usb[port].aptr_ept[i]);
-			}
-		}
-		if (!siemsg_handled)
-		{
-			sputs("Unhandled SIE2 message ");
-			print_word(sie_msg);
-			sputs("!\n");
-		}
-
-	}
-	if (!int_handled)
-	{
-		sputs("Unhandled interrupt (status = ");
-		print_word(hpi_status);
-		sputs(")!\n");
-	}
-
-//	sputs("--------------------------------------------------------\n");
-	_g_int_active = 0;
-}
-
-// ---------------------------------------------------------
-// CY7C67300 low-level routines
-// ---------------------------------------------------------
-void cy67k3_reset(void)
-{
-	int i;
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL;
-
-	*pHpi = 3;
-	for (i=0; i <160; i++)
-	{
-		__asm __volatile
-		(
-			".set	noreorder\n"
-			"nop\n"
-			"nop\n"
-			"nop\n"
-			"nop\n"
-			".set	reorder\n"
-		);
-	}
-
-	*pHpi = 2;
-
-}
-
-UINT16 cy67k3_read_HPI_DATA(void)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA;
-
-	return (UINT16)*pHpi;
-}
-
-UINT16 cy67k3_read_HPI_MAILBOX(void)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX;
-
-	return (UINT16)*pHpi;
-}
-
-UINT16 cy67k3_read_HPI_ADDRESS(void)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR;
-
-	return (UINT16)*pHpi;
-}
-
-UINT16 cy67k3_read_HPI_STATUS(void)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS;
-
-	return (UINT16)*pHpi;
-}
-
-void cy67k3_write_HPI_DATA(UINT16 data)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_DATA;
-
-	*pHpi = (UINT32)data;
-}
-
-void cy67k3_write_HPI_MAILBOX(UINT16 data)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_MBX;
-
-	*pHpi = (UINT32)data;
-}
-
-void cy67k3_write_HPI_ADDRESS(UINT16 data)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_ADDR;
-
-	*pHpi = (UINT32)data;
-}
-
-void cy67k3_write_HPI_STATUS(UINT16 data)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_STATUS;
-
-	*pHpi = (UINT32)data;
-}
-
-// ---------------------------------------------------------
-// HPI API
-// ---------------------------------------------------------
-UINT32 hpi_init(void)
-{
-	volatile UINT32 *pHpi = (UINT32*)SYS_USB_CTRL;
-	int i;
-	UINT16 reg;
-
-	// ToDo: Enable HPI interrupt
-	_g_int_active = 0;
-
-	hpi_write_reg(HPI_REG_SIE1MSG, 0x0000);
-	hpi_write_reg(HPI_REG_SIE2MSG, 0x0000);
-	hpi_write_reg(SUSB1_REG_STATUS, 0xFFFF);
-	hpi_write_reg(SUSB2_REG_STATUS, 0xFFFF);
-
-	// Init 1
-	for(i=0; i < USB_MAX_NUM_EPT; i++)
-	{
-		hpi_write_reg(SUSB1_REG_EP_ADDR0 + 16*i, 0);
-		hpi_write_reg(SUSB1_REG_EP_CNTRES0 + 16*i, 0);
-		hpi_write_reg(SUSB1_REG_EP_COUNT0 + 16*i, 0);
-		hpi_write_reg(SUSB1_REG_EP_CTRL0 + 16*i, 0);
-		hpi_write_reg(SUSB1_REG_EP_STATUS0 + 16*i, 0);
-	}
-	// Init 2
-	for(i=0; i < USB_MAX_NUM_EPT; i++)
-	{
-		hpi_write_reg(SUSB2_REG_EP_ADDR0 + 16*i, 0);
-		hpi_write_reg(SUSB2_REG_EP_CNTRES0 + 16*i, 0);
-		hpi_write_reg(SUSB2_REG_EP_COUNT0 + 16*i, 0);
-		hpi_write_reg(SUSB2_REG_EP_CTRL0 + 16*i, 0);
-		hpi_write_reg(SUSB2_REG_EP_STATUS0 + 16*i, 0);
-	}
-
-	hpi_write_reg(HPI_REG_INTROUTE, 0x0000);
-	reg = hpi_read_reg(HPI_REG_INTROUTE);
-//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x0202);	// Route reset {1,2} to HPI only
-//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x2800);	// Route SOF/EOP {1,2} to HPI only
-//	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x1400);	// Route SOF/EOP {1,2} to CY16 only
-	hpi_write_reg(HPI_REG_INTROUTE, reg | 0x3C00);	// Route SOF/EOP {1,2} to HPI and CY16
-
-
-	interrupt_register(4, cy67k3_isr);
-	interrupt_enable(4);
-	*pHpi = 0x02;
-
-	return HPI_NOERROR;
-}
-
-void hpi_mbx_write(UINT16 msgcode)
-{
-	_g_mbx_in_flag = 0;
-	cy67k3_write_HPI_MAILBOX(msgcode);
-}
-
-UINT32 hpi_mbx_read(void)
-{
-	UINT32 err;
-	UINT16 cy_return;
-
-	if (_g_int_active)
-	{
-		while (!(cy67k3_read_HPI_STATUS() & HPI_STATUS_MBX_IN));
-		cy_return = cy67k3_read_HPI_MAILBOX();
-	}
-	else
-	{
-		while(!_g_mbx_in_flag);
-		cy_return = _g_mbx_return;
-	}
-
-	switch (cy_return)
-	{
-		case COMM_ACK:
-			err = cy_return;
-		break;
-
-		case COMM_NAK:
-		case COMM_ASYNC:
-			err = HPI_ERR_PREFIX_MBX | cy_return;
-		break;
-
-		default:
-			err = HPI_ERR_PREFIX_MBX | cy_return;
-		break;
-	}
-	return err;
-}
-
-UINT32 hpi_check_addr(UINT16 addr)
-{
-	if ((addr >= 0x0000) && (addr < 0x4000))
-		return 0;
-
-	if ((addr >= 0xC080) && (addr < 0xC0BC))
-		return 0;
-
-	if (addr >= 0xE000)
-		return 0;
-
-	sputs("Invalid address for HPI direct access! Use LCP-command instead!\n");
-	return HPI_ERR_INVPARAM;
-}
-
-UINT32 hpi_read_reg(UINT16 addr)
-{
-	UINT32 result;
-
-	result = hpi_check_addr(addr);
-	if (IS_ERROR(result))
-		return result;
-
-	cy67k3_write_HPI_ADDRESS(addr);
-	return cy67k3_read_HPI_DATA();
-}
-
-UINT32 hpi_write_reg(UINT16 addr, UINT16 data)
-{
-	UINT32 result;
-
-	result = hpi_check_addr(addr);
-	if (IS_ERROR(result))
-		return result;
-
-	cy67k3_write_HPI_ADDRESS(addr);
-	cy67k3_write_HPI_DATA(data);
-}
-
-UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 len)
-{
-	int i, num_words;
-
-	if (addr > 0x3FFE)
-		return HPI_ERR_INVPARAM;
-
-	if (addr & 1)				// Not 16bit aligned?
-		return HPI_ERR_INVPARAM;
-
-	cy67k3_write_HPI_ADDRESS(addr);
-
-	num_words = len/2;
-	if (len % 2)
-		num_words++;
-
-	for (i=0; i < num_words; i++)
-		cy67k3_write_HPI_DATA(pData[i]);
-
-	return len;
-}
-
-UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 len)
-{
-	int i, num_words;
-
-	if (addr > 0x3FFE)
-		return HPI_ERR_INVPARAM;
-
-	if (addr & 1)				// Not 16bit aligned?
-		return HPI_ERR_INVPARAM;
-
-	cy67k3_write_HPI_ADDRESS(addr);
-
-	num_words = len/2;
-	if (len % 2)
-		num_words++;
-
-	for (i=0; i < num_words; i++)
-		pData[i] = cy67k3_read_HPI_DATA();
-
-	return len;
-}
-
-UINT32 hpi_comm_reset(void)
-{
-	hpi_mbx_write(COMM_RESET);
-
-	return hpi_mbx_read();
-}
-
-UINT32 hpi_comm_jump2code(UINT16 addr)
-{
-	cy67k3_write_HPI_ADDRESS(addr);
-	hpi_mbx_write(COMM_JUMP2CODE);
-
-	return hpi_mbx_read();
-}
-
-UINT32 hpi_comm_callcode(UINT16 addr)
-{
-	hpi_write_reg(COMM_CODE_ADDR, addr);
-
-	hpi_mbx_write(COMM_CALL_CODE);
-
-	return hpi_mbx_read();
-}
-
-UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic)
-{
-
-	hpi_write_reg(COMM_CTRL_REG_ADDR, addr);
-	hpi_write_reg(COMM_CTRL_REG_DATA, data);
-	hpi_write_reg(COMM_CTRL_REG_LOGIC, logic);
-
-	hpi_mbx_write(COMM_WRITE_CTRL_REG);
-
-	return hpi_mbx_read();
-}
-
-UINT32 hpi_comm_read_ctrl_reg(UINT16 addr)
-{
-	UINT32 result;
-
-	hpi_write_reg(COMM_CTRL_REG_ADDR, addr);
-
-	hpi_mbx_write(COMM_READ_CTRL_REG);
-
-	result = hpi_mbx_read();
-	if (IS_ERROR(result))
-		return result;
-
-	cy67k3_write_HPI_ADDRESS(COMM_CTRL_REG_DATA);
-	return (UINT32)cy67k3_read_HPI_DATA();
-
-}
-
-UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len)
-{
-	return HPI_ERR_NOTIMPL;
-
-}
-
-UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len)
-{
-	return HPI_ERR_NOTIMPL;
-
-}
-
-typedef struct _sreg_param_t
-{
-	UINT32 id;
-	UINT16 val;
-
-} reg_param_t;
-
-UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...)
-{
-	int i;
-	UINT32 result;
-	va_list args;
-	reg_param_t reg_param[MAX_NUM_REGS];
-
-	va_start(args, nargs);
-
-	if (nargs > MAX_NUM_REGS)
-	{
-		fprintf(stderr, "hpi_comm_exec_int(): Number (%d), of arguments exceeds %d!\n", nargs, MAX_NUM_REGS);
-		return HPI_ERR_INVPARAM;
-	}
-
-	for (i=0; i < nargs; i++)
-	{
-		reg_param[i].id = va_arg(args, UINT32);
-		if (reg_param[i].id > MAX_NUM_REGS)
-		{
-			fprintf(stderr, "hpi_comm_exec_int(): Invalid register R%d!\n", reg_param[i].id);
-			return HPI_ERR_INVPARAM;
-		}
-
-		reg_param[i].val = (UINT16)va_arg(args, UINT32);
-	}
-	va_end(args);
-
-	hpi_write_reg(COMM_INT_NUM, intnum);
-
-	for (i=0; i < nargs; i++)
-	{
-		hpi_write_reg(COMM_R0 + 2*reg_param[i].id, reg_param[i].val);
-	}
-
-	hpi_mbx_write(COMM_EXEC_INT);
-
-	result = hpi_mbx_read();
-	if (IS_ERROR(result))
-		return result;
-
-	return (UINT32)hpi_read_reg(COMM_R0);
-}
-
-UINT32 usb_init(void)
-{
-	INT32 i;
-
-	for (i=0; i < USB_MAX_NUM_PORTS; i++)
-	{
-		memset(&_g_usb[i], 0, sizeof(usb_t));
-	}
-	return 0;
-}
-
-UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg)
-{
-	UINT32 result;
-	if (port >= USB_MAX_NUM_PORTS)
-		return -1;
-
-	result = 0;
-	switch (type)
-	{
-		case SUSB_EP0_MSG:
-		_g_usb[port].fptr_ept[0] = pFunc;
-		_g_usb[port].aptr_ept[0] = pArg;
-		break;
-
-		case SUSB_EP1_MSG:
-		_g_usb[port].fptr_ept[1] = pFunc;
-		_g_usb[port].aptr_ept[1] = pArg;
-		break;
-
-		case SUSB_EP2_MSG:
-		_g_usb[port].fptr_ept[2] = pFunc;
-		_g_usb[port].aptr_ept[2] = pArg;
-		break;
-
-		case SUSB_EP3_MSG:
-		_g_usb[port].fptr_ept[3] = pFunc;
-		_g_usb[port].aptr_ept[3] = pArg;
-		break;
-
-		case SUSB_EP4_MSG:
-		_g_usb[port].fptr_ept[4] = pFunc;
-		_g_usb[port].aptr_ept[4] = pArg;
-		break;
-
-		case SUSB_EP5_MSG:
-		_g_usb[port].fptr_ept[5] = pFunc;
-		_g_usb[port].aptr_ept[5] = pArg;
-		break;
-
-		case SUSB_EP6_MSG:
-		_g_usb[port].fptr_ept[6] = pFunc;
-		_g_usb[port].aptr_ept[6] = pArg;
-		break;
-
-		case SUSB_EP7_MSG:
-		_g_usb[port].fptr_ept[7] = pFunc;
-		_g_usb[port].aptr_ept[7] = pArg;
-		break;
-
-		case SUSB_RST_MSG:
-		_g_usb[port].fptr_rst = pFunc;
-		_g_usb[port].aptr_rst = pArg;
-		break;
-
-		case SUSB_SOF_MSG:
-		_g_usb[port].fptr_sof = pFunc;
-		_g_usb[port].aptr_sof = pArg;
-		break;
-
-		case SUSB_CFG_MSG:
-		_g_usb[port].fptr_cfg = pFunc;
-		_g_usb[port].aptr_cfg = pArg;
-		break;
-
-		case SUSB_SUS_MSG:
-		_g_usb[port].fptr_sus = pFunc;
-		_g_usb[port].aptr_sus = pArg;
-		break;
-
-		case SUSB_ID_MSG:
-		_g_usb[port].fptr_id = pFunc;
-		_g_usb[port].aptr_id = pArg;
-		break;
-
-		case SUSB_VBUS_MSG:
-		_g_usb[port].fptr_vbus = pFunc;
-		_g_usb[port].aptr_vbus = pArg;
-		break;
-
-		default:
-		result = -1;
-		break;
-	}
-
-	return result;
-}
-
-UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out)
-{
-
-	if (!pIRP)
-		return -1;
-
-	if (port >= USB_MAX_NUM_PORTS)
-		return -1;
-
-	if (ept >= USB_MAX_NUM_EPT)
-		return -1;
-
-	if (size >= USB_MAX_IMG_SIZE)
-		return -1;
-
-	memset(pIRP, 0, sizeof(usb_irp_t));
-	pIRP->is_out = is_out;
-	pIRP->is_in = !is_out;
-	pIRP->tsize = size;
-	pIRP->port = port;
-	pIRP->ept = ept;
-	pIRP->cy_irp_addr = USB_IRP_BASE + port*USB_MAX_NUM_EPT*sizeof(cy_req_t) + ept*sizeof(cy_req_t);
-	pIRP->cy_req.next = 0;
-	pIRP->cy_req.addr = USB_IMG_BASE + port*USB_MAX_NUM_EPT*USB_MAX_IMG_SIZE + ept*USB_MAX_IMG_SIZE;
-	pIRP->cy_req.size = size;
-	pIRP->cy_req.callback = 0;
-	fifo_alloc(&pIRP->fifo, 8*USB_MAX_IMG_SIZE);
-
-	return 0;
-}
-
-UINT32 usb_irp_enqueue(usb_irp_t *pIRP)
-{
-	UINT32 result;
-
-	if (!pIRP)
-	{
-//		sputs ("usb_irp_enqueue(): Invalid IRP!\n");
-		return -1;
-	}
-
-//	printf("cy_addr: %4.4X, Next: %4.4X, Addr: %4.4X, Size: %4.4X, CB: %4.4X\n", pIRP->cy_irp_addr, pIRP->cy_req.next, pIRP->cy_req.addr, pIRP->cy_req.size, pIRP->cy_req.callback);
-
-	if (pIRP->is_out)
-	{
-		hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t));
-		if (pIRP->port == 0)
-			result = hpi_comm_exec_int(SUSB1_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
-
-		if (pIRP->port == 1)
-			result = hpi_comm_exec_int(SUSB2_RECEIVE_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
-	}
-	if (pIRP->is_in)
-	{
-		pIRP->tx_in_progress = 1;
-		hpi_write_ram(pIRP->cy_irp_addr, (UINT16*)&pIRP->cy_req, sizeof(cy_req_t));
-		if (pIRP->port == 0)
-			result = hpi_comm_exec_int(SUSB1_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
-
-		if (pIRP->port == 1)
-			result = hpi_comm_exec_int(SUSB2_SEND_INT, 2, R1, pIRP->ept, R8, pIRP->cy_irp_addr);
-	}
-
-//	if (result)
-//		printf ("usb_irp_enqueue(): Result = %8.8X\n", result);
-
-	return result;
-
-}
-
-UINT32 fifo_alloc(fifo_t *pObj, UINT32 size)
-{
-	pObj->pBuf = (UINT8*)malloc(size);
-	if (!pObj->pBuf)
-	{
-//		printf ("fifo_alloc(): Error allocating memory!\n");
-		return -1;
-	}
-//	printf ("fifo_alloc(): pBuf at %8.8X\n", (UINT32)pObj->pBuf);
-	pObj->size = size;
-	pObj->pPtr_wr = pObj->pBuf;
-	pObj->pPtr_rd = pObj->pBuf;
-
-	return 0;
-}
-
-UINT32 fifo_free(fifo_t *pObj)
-{
-	if (pObj->pBuf)
-		free(pObj->pBuf);
-
-	return 0;
-}
-
-UINT32 fifo_flush(fifo_t *pObj)
-{
-	pObj->pPtr_wr = pObj->pBuf;
-	pObj->pPtr_rd = pObj->pBuf;
-
-	return 0;
-}
-
-UINT32 fifo_is_empty(fifo_t *pObj)
-{
-	return (pObj->pPtr_wr == pObj->pPtr_rd);
-}
-
-UINT32 fifo_is_full(fifo_t *pObj)
-{
-	UINT8 *pNext, *pEnd;
-
-	pEnd = pObj->pBuf + pObj->size;
-	pNext = pObj->pPtr_wr + 1;
-	if (pNext == pEnd)
-		pNext = pObj->pBuf;
-
-	return (pNext == pObj->pPtr_rd);
-}
-
-UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block)
-{
-	UINT32 i;
-	UINT32 wait_4ever, timeout_cnt, cnt;
-	UINT8 *pEnd;
-
-	pEnd = pObj->pBuf + pObj->size;
-	wait_4ever = (timeout == 0);
-
-	cnt = 0;
-	while(size)
-	{
-		timeout_cnt = timeout;
-
-		while(fifo_is_empty(pObj))
-		{
-			if (!do_block)
-				return cnt;
-
-			if (!wait_4ever)
-			{
-				if (timeout_cnt)
-				{
-					timeout_cnt--;
-					sleep(1);
-				}
-				else
-				{
-					return cnt;
-				}
-			}
-		}
-
-		if (pData)
-			pData[cnt] = *(pObj->pPtr_rd);
-
-		cnt++;
-		pObj->pPtr_rd++;
-		if (pObj->pPtr_rd == pEnd)
-			pObj->pPtr_rd = pObj->pBuf;
-
-		size--;
-	}
-
-	return cnt;
-}
-
-UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block)
-{
-	UINT32 wait_4ever, timeout_cnt, cnt;
-	UINT8 *pEnd;
-
-	pEnd = pObj->pBuf + pObj->size;
-	wait_4ever = (timeout == 0);
-
-	cnt = 0;
-	while(size)
-	{
-		timeout_cnt = timeout;
-
-		while(fifo_is_full(pObj))
-		{
-			if (!do_block)
-				return cnt;
-
-			if (!wait_4ever)
-			{
-				if (timeout_cnt)
-				{
-					timeout_cnt--;
-					sleep(1);
-				}
-				else
-				{
-					return cnt;
-				}
-			}
-		}
-
-		if (pData)
-			*(pObj->pPtr_wr) = pData[cnt];
-
-		cnt++;
-		pObj->pPtr_wr++;
-		if (pObj->pPtr_wr == pEnd)
-			pObj->pPtr_wr = pObj->pBuf;
-
-		size--;
-	}
-
-	return cnt;
-}
-
-// ---------------------------------------------------------
diff --git a/lib/CPUs/MIPS/bsp/examples/hpi.h b/lib/CPUs/MIPS/bsp/examples/hpi.h
deleted file mode 100644
index 58edabe..0000000
--- a/lib/CPUs/MIPS/bsp/examples/hpi.h
+++ /dev/null
@@ -1,384 +0,0 @@
-#ifndef HPI_H
-#define HPI_H
-
-// ---------------------------------------------------------
-// API related
-// ---------------------------------------------------------
-//#define	IS_ERROR(e)			(0 != (e & HPI_ERROR))
-#define	HPI_NOERROR			0
-#define	HPI_ERROR			0x80000000
-#define	HPI_ERR_NOTIMPL		(HPI_ERROR + 1)
-#define	HPI_ERR_INVPARAM	(HPI_ERROR + 2)
-#define	HPI_ERR_TIMEOUT		(HPI_ERROR + 3)
-#define	HPI_ERR_PREFIX_MBX	(HPI_ERROR + 0x00010000)
-
-#define	MAX_NUM_REGS		14
-#define R0					0
-#define R1					1
-#define R2					2
-#define R3					3
-#define R4					4
-#define R5					5
-#define R6					6
-#define R7					7
-#define R8					8
-#define R9					9
-#define R10					10
-#define R11					11
-#define R12					12
-#define R13					13
-
-#define USB_MAX_NUM_PORTS	2
-#define USB_MAX_NUM_EPT		8
-#define USB_MAX_IMG_SIZE	512
-#define USB_IRP_BASE		0x0F80
-#define USB_IMG_BASE		0x1000
-
-typedef void (*fp_t)(void*);
-
-// Receive buffer on EP
-typedef struct _scy_req_t
-{
-	UINT16 next;
-	UINT16 addr;
-	UINT16 size;
-	UINT16 callback;
-} cy_req_t;
-
-typedef struct _sfifo_t
-{
-	UINT32 size;
-	UINT8 *pBuf;
-	UINT8 * volatile pPtr_wr, * volatile pPtr_rd;
-
-} fifo_t;
-
-typedef struct _susb_irp_t
-{
-	UINT16 tsize;
-	UINT32 is_in, is_out;
-	UINT32 port, ept;
-	UINT16 cy_irp_addr;
-	fifo_t fifo;
-	UINT32 tx_in_progress;
-	cy_req_t cy_req;
-} usb_irp_t;
-
-// ---------------------------------------------------------
-// CY7C67300 related
-// ---------------------------------------------------------
-#define	HPI_WAITACK			1
-#define	HPI_NOWAIT			0
-
-// ---------------------------------------------------------
-// HPI status flags
-#define	HPI_STATUS_MBX_IN	0x0001
-#define	HPI_STATUS_RESET1	0x0002
-#define	HPI_STATUS_DONE1	0x0004
-#define	HPI_STATUS_DONE2	0x0008
-#define	HPI_STATUS_SIEMSG1	0x0010
-#define	HPI_STATUS_SIEMSG2	0x0020
-#define	HPI_STATUS_RESUME1	0x0040
-#define	HPI_STATUS_RESUME2	0x0080
-#define	HPI_STATUS_MBX_OUT	0x0100
-#define	HPI_STATUS_RESET2	0x0200
-#define	HPI_STATUS_SOFEOP1	0x0400
-#define	HPI_STATUS_SOFEOP2	0x1000
-#define	HPI_STATUS_ID		0x4000
-#define	HPI_STATUS_VBUS		0x8000
-
-// ---------------------------------------------------------
-// LCP command codes
-#define COMM_RESET			0xFA50
-#define COMM_JUMP2CODE		0xCE00
-#define COMM_EXEC_INT		0xCE01
-#define COMM_READ_CTRL_REG	0xCE02
-#define COMM_WRITE_CTRL_REG	0xCE03
-#define COMM_CALL_CODE		0xCE04
-#define COMM_READ_XMEM		0xCE05
-#define COMM_WRITE_XMEM		0xCE06
-#define C0MM_CONFIG			0xCE07
-#define COMM_READ_MEM		0xCE08
-#define COMM_WRITE_MEM		0xCE09
-// LCP response codes
-#define COMM_ACK			0x0FED
-#define COMM_NAK			0xDEAD
-#define COMM_ASYNC			0xF00D
-
-// ---------------------------------------------------------
-// LCP memory addresses
-#define COMM_PORT_CMD		0x01BA	// For PORT Command
-#define COMM_MEM_ADDR		0x01BC	// Address for COMM_RD/WR_MEM
-#define COMM_MEM_LEN		0x01BE	// Address for COMM_RD/WR_MEM
-#define COMM_LAST_DATA		0x01C0	// memory pointer for xmem
-#define COMM_CTRL_REG_ADDR	0x01BC	// Address for COMM_RD/WR_CTRL_REG
-#define COMM_CTRL_REG_DATA	0x01BE	// Address for COMM_RD/WR_CTRL_REG
-#define COMM_CTRL_REG_LOGIC	0x01C0	// Address used for AND/OR
-#define REG_WRITE_FLG		0x0000	// Value for COMM_CTRL_REG_LOGIC
-#define REG_AND_FLG			0x0001	// Value for COMM_CTRL_REG_LOGIC
-#define REG_OR_FLG			0x0002	// Value for COMM_CTRL_REG_LOGIC
-#define COMM_TIMEOUT		0x01BE	// Address setting Timeout for sending response to host
-#define COMM_CODE_ADDR		0x01BC	// Address for COMM_CALL_CODE and COMM_JUMP2CODE
-#define COMM_INT_NUM		0x01C2	// Address used for COMM_EXEC_INT
-#define COMM_R0				0x01C4	// CY16-R0 register
-#define COMM_R1				0x01C6	// CY16-R1 register
-#define COMM_R2				0x01C8	// CY16-R2 register
-#define COMM_R3				0x01CA	// CY16-R3 register
-#define COMM_R4				0x01CC	// CY16-R4 register
-#define COMM_R5				0x01CE	// CY16-R5 register
-#define COMM_R6				0x01D0	// CY16-R6 register
-#define COMM_R7				0x01D2	// CY16-R7 register
-#define COMM_R8				0x01D4	// CY16-R8 register
-#define COMM_R9				0x01D6	// CY16-R9 register
-#define COMM_R10			0x01D8	// CY16-R10 register
-#define COMM_R11			0x01DA	// CY16-R11 register
-#define COMM_R12			0x01DC	// CY16-R12 register
-#define COMM_R13			0x01DE	// CY16-R13 register
-
-// for COMM_CTRL_REG_LOGIC
-#define	LOGIC_DIRECT		0
-#define	LOGIC_AND			1
-#define	LOGIC_OR			2
-
-// ---------------------------------------------------------
-// Software interrupts
-#define	SUSB_INIT_INT							113
-// USB 1
-#define	SUSB1_DEVICE_DESCRIPTOR_VEC				90
-#define	SUSB1_CONFIGURATION_DESCRIPTOR_VEC		91
-#define	SUSB1_STRING_DESCRIPTOR_VEC				92
-#define	SUSB1_FINISH_INT						89
-#define	SUSB1_STALL_INT							82
-#define	SUSB1_STANDARD_INT						83
-#define	SUSB1_SEND_INT							80
-#define	SUSB1_RECEIVE_INT						81
-#define	SUSB1_VENDOR_INT						85
-#define	SUSB1_CLASS_INT							87
-#define	SUSB1_LOADER_INT						94
-#define	SUSB1_DELTA_CONFIG_INT					95
-
-// USB 2
-#define	SUSB2_DEVICE_DESCRIPTOR_VEC				106
-#define	SUSB2_CONFIGURATION_DESCRIPTOR_VEC		107
-#define	SUSB2_STRING_DESCRIPTOR_VEC				108
-#define	SUSB2_FINISH_INT						105
-#define	SUSB2_STALL_INT							98
-#define	SUSB2_STANDARD_INT						99
-#define	SUSB2_SEND_INT							96
-#define	SUSB2_RECEIVE_INT						97
-#define	SUSB2_VENDOR_INT						101
-#define	SUSB2_CLASS_INT							103
-#define	SUSB2_LOADER_INT						110
-#define	SUSB2_DELTA_CONFIG_INT					111
-
-// ---------------------------------------------------------
-// General USB Registers
-#define	USB_REG_FLAGS							0xC000	// CPU Flags
-#define	USB_REG_BANK							0xC002	// Register Bank
-#define	USB_REG_REVISON							0xC004	// Hardware Revision
-#define	USB_REG_SPEED							0xC008	// CPU Speed
-#define	USB_REG_PWRCTRL							0xC00A	// Power Control
-#define	USB_REG_INTEN							0xC00E	// Interrupt Enable
-#define	USB_REG_BP								0xC014	// Breakpoint
-#define	USB_REG_USBDIAG							0xC03C	// USB Diagnostic
-#define	USB_REG_MEMDIAG							0xC03E	// Memory Diagnostic
-
-// HPI registers
-#define	HPI_REG_BP								0x0140	// HPI Breakpoint
-#define	HPI_REG_INTROUTE						0x0142	// Interrupt Routing
-#define	HPI_REG_SIE1MSG							0x0144	// SIE1msg
-#define	HPI_REG_SIE2MSG							0x0148	// SIE2msg
-#define	HPI_REG_MAILBOX							0xC0C6	// HPI Mailbox
-
-// ---------------------------------------------------------
-// General Device Registers
-// Device 1
-#define	SUSB1_REG_PORTSEL						0xC084	// Port select
-#define	SUSB1_REG_USBCTRL						0xC08A	// USB control
-#define	SUSB1_REG_INTEN							0xC08C	// Interrupt enable
-#define	SUSB1_REG_ADDR							0xC08E	// Address
-#define	SUSB1_REG_STATUS						0xC090	// Status
-#define	SUSB1_REG_FRAMENUM						0xC092	// Frame number
-#define	SUSB1_REG_SOFEOPCNT						0xC094	// SOF/EOP count
-
-// Device 2
-#define	SUSB2_REG_PORTSEL						0xC0A4	// Port select
-#define	SUSB2_REG_USBCTRL						0xC0AA	// USB control
-#define	SUSB2_REG_INTEN							0xC0AC	// Interrupt enable
-#define	SUSB2_REG_ADDR							0xC0AE	// Address
-#define	SUSB2_REG_STATUS						0xC0B0	// Status
-#define	SUSB2_REG_FRAMENUM						0xC0B2	// Frame number
-#define	SUSB2_REG_SOFEOPCNT						0xC0B4	// SOF/EOP count
-
-// ---------------------------------------------------------
-// Endpoint Registers
-// Device 1 Control
-#define	SUSB1_REG_EP_CTRL0						0x0200
-#define	SUSB1_REG_EP_CTRL1						0x0210
-#define	SUSB1_REG_EP_CTRL2						0x0220
-#define	SUSB1_REG_EP_CTRL3						0x0230
-#define	SUSB1_REG_EP_CTRL4						0x0240
-#define	SUSB1_REG_EP_CTRL5						0x0250
-#define	SUSB1_REG_EP_CTRL6						0x0260
-#define	SUSB1_REG_EP_CTRL7						0x0270
-// Device 1 Address
-#define	SUSB1_REG_EP_ADDR0						0x0202
-#define	SUSB1_REG_EP_ADDR1						0x0212
-#define	SUSB1_REG_EP_ADDR2						0x0222
-#define	SUSB1_REG_EP_ADDR3						0x0232
-#define	SUSB1_REG_EP_ADDR4						0x0242
-#define	SUSB1_REG_EP_ADDR5						0x0252
-#define	SUSB1_REG_EP_ADDR6						0x0262
-#define	SUSB1_REG_EP_ADDR7						0x0272
-// Device 1 Count
-#define	SUSB1_REG_EP_COUNT0						0x0204
-#define	SUSB1_REG_EP_COUNT1						0x0214
-#define	SUSB1_REG_EP_COUNT2						0x0224
-#define	SUSB1_REG_EP_COUNT3						0x0234
-#define	SUSB1_REG_EP_COUNT4						0x0244
-#define	SUSB1_REG_EP_COUNT5						0x0254
-#define	SUSB1_REG_EP_COUNT6						0x0264
-#define	SUSB1_REG_EP_COUNT7						0x0274
-// Device 1 Status
-#define	SUSB1_REG_EP_STATUS0					0x0206
-#define	SUSB1_REG_EP_STATUS1					0x0216
-#define	SUSB1_REG_EP_STATUS2					0x0226
-#define	SUSB1_REG_EP_STATUS3					0x0236
-#define	SUSB1_REG_EP_STATUS4					0x0246
-#define	SUSB1_REG_EP_STATUS5					0x0256
-#define	SUSB1_REG_EP_STATUS6					0x0266
-#define	SUSB1_REG_EP_STATUS7					0x0276
-// Device 1 Count result
-#define	SUSB1_REG_EP_CNTRES0					0x0208
-#define	SUSB1_REG_EP_CNTRES1					0x0218
-#define	SUSB1_REG_EP_CNTRES2					0x0228
-#define	SUSB1_REG_EP_CNTRES3					0x0238
-#define	SUSB1_REG_EP_CNTRES4					0x0248
-#define	SUSB1_REG_EP_CNTRES5					0x0258
-#define	SUSB1_REG_EP_CNTRES6					0x0268
-#define	SUSB1_REG_EP_CNTRES7					0x0278
-
-// Device 2 Control
-#define	SUSB2_REG_EP_CTRL0						0x0280
-#define	SUSB2_REG_EP_CTRL1						0x0290
-#define	SUSB2_REG_EP_CTRL2						0x02A0
-#define	SUSB2_REG_EP_CTRL3						0x02B0
-#define	SUSB2_REG_EP_CTRL4						0x02C0
-#define	SUSB2_REG_EP_CTRL5						0x02D0
-#define	SUSB2_REG_EP_CTRL6						0x02E0
-#define	SUSB2_REG_EP_CTRL7						0x02F0
-// Device 2 Address
-#define	SUSB2_REG_EP_ADDR0						0x0282
-#define	SUSB2_REG_EP_ADDR1						0x0292
-#define	SUSB2_REG_EP_ADDR2						0x02A2
-#define	SUSB2_REG_EP_ADDR3						0x02B2
-#define	SUSB2_REG_EP_ADDR4						0x02C2
-#define	SUSB2_REG_EP_ADDR5						0x02D2
-#define	SUSB2_REG_EP_ADDR6						0x02E2
-#define	SUSB2_REG_EP_ADDR7						0x02F2
-// Device 2 Count
-#define	SUSB2_REG_EP_COUNT0						0x0284
-#define	SUSB2_REG_EP_COUNT1						0x0294
-#define	SUSB2_REG_EP_COUNT2						0x02A4
-#define	SUSB2_REG_EP_COUNT3						0x02B4
-#define	SUSB2_REG_EP_COUNT4						0x02C4
-#define	SUSB2_REG_EP_COUNT5						0x02D4
-#define	SUSB2_REG_EP_COUNT6						0x02E4
-#define	SUSB2_REG_EP_COUNT7						0x02F4
-// Device 2 Status
-#define	SUSB2_REG_EP_STATUS0					0x0286
-#define	SUSB2_REG_EP_STATUS1					0x0296
-#define	SUSB2_REG_EP_STATUS2					0x02A6
-#define	SUSB2_REG_EP_STATUS3					0x02B6
-#define	SUSB2_REG_EP_STATUS4					0x02C6
-#define	SUSB2_REG_EP_STATUS5					0x02D6
-#define	SUSB2_REG_EP_STATUS6					0x02E6
-#define	SUSB2_REG_EP_STATUS7					0x02F6
-// Device 2 Count result
-#define	SUSB2_REG_EP_CNTRES0					0x0288
-#define	SUSB2_REG_EP_CNTRES1					0x0298
-#define	SUSB2_REG_EP_CNTRES2					0x02A8
-#define	SUSB2_REG_EP_CNTRES3					0x02B8
-#define	SUSB2_REG_EP_CNTRES4					0x02C8
-#define	SUSB2_REG_EP_CNTRES5					0x02D8
-#define	SUSB2_REG_EP_CNTRES6					0x02E8
-#define	SUSB2_REG_EP_CNTRES7					0x02F8
-
-// ---------------------------------------------------------
-// others
-#define HUSB_TDLISTDONE		0x1000
-#define HUSB_SOF			0x2000
-#define HUSB_ARMV			0x0001
-#define HUSB_AINS_FS		0x0002
-#define HUSB_AINS_LS		0x0004
-#define HUSB_AWAKEUP		0x0008
-#define HUSB_BRMV			0x0010
-#define HUSB_BINS_FS		0x0020
-#define HUSB_BINS_LS		0x0040
-#define HUSB_BWAKEUP		0x0080
-
-#define SUSB_EP0_MSG		0x0001
-#define SUSB_EP1_MSG		0x0002
-#define SUSB_EP2_MSG		0x0004
-#define SUSB_EP3_MSG		0x0008
-#define SUSB_EP4_MSG		0x0010
-#define SUSB_EP5_MSG		0x0020
-#define SUSB_EP6_MSG		0x0040
-#define SUSB_EP7_MSG		0x0080
-#define SUSB_RST_MSG		0x0100
-#define SUSB_SOF_MSG		0x0200
-#define SUSB_CFG_MSG		0x0400
-#define SUSB_SUS_MSG		0x0800
-#define SUSB_ID_MSG			0x4000
-#define SUSB_VBUS_MSG		0x8000
-
-// ---------------------------------------------------------
-// Functions
-// ---------------------------------------------------------
-
-// HPI low-level routines
-void cy67k3_isr(void);
-void cy67k3_reset(void);
-UINT16 cy67k3_read_HPI_DATA(void);
-UINT16 cy67k3_read_HPI_MAILBOX(void);
-UINT16 cy67k3_read_HPI_ADDRESS(void);
-UINT16 cy67k3_read_HPI_STATUS(void);
-void cy67k3_write_HPI_DATA(UINT16 data);
-void cy67k3_write_HPI_MAILBOX(UINT16 data);
-void cy67k3_write_HPI_ADDRESS(UINT16 data);
-void cy67k3_write_HPI_STATUS(UINT16 data);
-
-// HPI API
-UINT32 hpi_init(void);
-void hpi_mbx_write(UINT16 msgcode);
-UINT32 hpi_mbx_read(void);
-UINT32 hpi_read_reg(UINT16 addr);
-UINT32 hpi_write_reg(UINT16 addr, UINT16 data);
-UINT32 hpi_write_ram(UINT16 addr, UINT16 *pData, UINT32 num_words);
-UINT32 hpi_read_ram(UINT16 addr, UINT16 *pData, UINT32 num_words);
-UINT32 hpi_comm_reset(void);
-UINT32 hpi_comm_jump2code(UINT16 addr);
-UINT32 hpi_comm_callcode(UINT16 addr);
-UINT32 hpi_comm_write_ctrl_reg(UINT16 addr, UINT16 data, UINT16 logic);
-UINT32 hpi_comm_read_ctrl_reg(UINT16 addr);
-UINT32 hpi_comm_write_xmem(UINT16 addr, UINT8 *pData, UINT16 len);
-UINT32 hpi_comm_read_xmem(UINT16 addr, UINT8 *pData, UINT16 len);
-UINT32 hpi_comm_exec_int(UINT16 intnum, UINT32 nargs, ...);
-
-// USB API
-UINT32 usb_init(void);
-UINT32 usb_irp_register(usb_irp_t *pIRP, UINT32 port, UINT32 ept, UINT32 size, UINT32 is_out);
-UINT32 usb_irp_enqueue(usb_irp_t *pIRP);
-UINT32 usb_callback_register(UINT32 port, UINT32 type, fp_t pFunc, void *pArg);
-
-#define	FIFO_BLOCK		1
-#define	FIFO_NONBLOCK	0
-UINT32 fifo_alloc(fifo_t *pObj, UINT32 size);
-UINT32 fifo_free(fifo_t *pObj);
-UINT32 fifo_flush(fifo_t *pObj);
-UINT32 fifo_is_full(fifo_t *pObj);
-UINT32 fifo_is_empty(fifo_t *pObj);
-UINT32 fifo_read(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block);
-UINT32 fifo_write(fifo_t *pObj, UINT8 *pData, UINT32 size, UINT32 timeout, UINT32 do_block);
-
-#endif // HPI_H
diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.c b/lib/CPUs/MIPS/bsp/examples/inflate.c
deleted file mode 100644
index b50581d..0000000
--- a/lib/CPUs/MIPS/bsp/examples/inflate.c
+++ /dev/null
@@ -1,504 +0,0 @@
-/* inflate routines for Palm OS (to inflate a deflated stream)
- *
- * Based heavily upon gunzip.c by Pasi Ojala <albert@cs.tut.fi>
- *   http://www.cs.tut.fi/~albert/Dev/gunzip/
- * Many, many thanks for that code!
- *
- * Changes:
- *  2002-12-30 - Added #defines to use zlib's struct instead of mine, just
- *               in case you want to compile it that way.
- *  2002-12-29 - Found out that this is VERY slow.  ZLib is 3x faster.
- *               Worked on speeding it up.  Partially successful.  Profiled
- *               code and marked critical areas.  1932 bytes added to a
- *               Palm program by linking in the .o file.  Schweet!
- *  2002-12-21 - Finished surgery.  Only one function to inflate dynamic and
- *               fixed data.  Rewrote table generation to be iterative.
- *               Hacked and slashed my way through unnecessary code.
- *               The size is now down to 3512 bytes.
- *  2002-12-20 - Started major surgery
- *  2002-12-19 - Looked at the code a bit more
- *  2002-12-17 - Continued work.  Down to about 6k for the .o file
- *  2002-12-09 - Continued work, added z_stream_fid instead of globals
- *  2002-12-08 - Started work so that it decompresses up to 64k (one memory
- *               chunk on the Palm.
- *  2002-12-07 - Removed bit reverse table.  Removed unzip code.
- */
-#include "libsys.h"
-#include "inflate.h"
-#ifdef VERBOSE
-#include <stdio.h>    // Just in case you put a printf() function back in
-#endif
-
-void Status(char *, int);
-
-typedef struct HufNode_struct {
-   // b0 and b1 are either values in the tree array to jump to (branches)
-   // or are literal values.
-   // if (bX & 0x8000)
-   //     value = bX ^ 0x8000;
-   // else
-   //     link_to_array_element = bX;
-   unsigned int b0;  // Bigger than 1 byte (2 is ideal)
-   unsigned int b1;  // Bigger than 1 byte (2 is ideal)
-} HufNode;
-
-
-// Not that rhobust anymore -- If out of data, this will
-// return a whole lot of 1 bits.
-//
-// This function consumes a large percentage of time (#1)
-char READBIT(z_stream *zs)
-{
-   char carry;
-
-   if (zs->reserved == 1)
-     {
-	if (zs->avail_in == 0)
-	  return 1;
-	zs->reserved = *(zs->next_in ++) | 0x0100;
-	zs->avail_in --;
-     }
-
-   carry = zs->reserved & 1;
-   zs->reserved >>= 1;
-
-   return carry;
-}
-
-
-// Make sure that [a] is <= 16
-// If there are endian problems, force [a] to be <= 8
-// Might be faster if all (up to [a] bits) of zs->reserved was read into res
-// right away.
-//
-// This function consumes a large percentage of time (#4)
-int READBITS(z_stream *zs, int a)
-{
-   int res = 0, pos = 0;
-
-   while (a --)
-     {
-	if (zs->reserved == 1)
-	  {
-	     if (zs->avail_in == 0)
-	       return 1;
-	     zs->reserved = *(zs->next_in ++) | 0x0100;
-	     zs->avail_in --;
-	  }
-
-	res += (zs->reserved & 1) << pos;
-	zs->reserved >>= 1;
-	pos ++;
-     }
-
-   return res;
-}
-
-
-// Huffman tree structures, variables and related routines
-//
-// These routines are one-bit-at-a-time decode routines. They
-// are not as fast as multi-bit routines, but maybe a bit easier
-// to understand and use a lot less memory.
-//
-// The tree is created in an array
-//
-// currentTree = where to put the tree (in an array)
-// numval = Number of elements in the lengths array
-// lengths = array of lengths
-//
-//
-// This function consumes a large percentage of time (#5)
-int CreateTree(HufNode *currentTree, int numval, unsigned char *lengths) {
-   int i, j, len;  // basically scratch values
-   int BlankNode;  // Where is the next blank array index
-   int this_code, mask, *bitData;  // used in tree generation
-   int bl_count[16] = { 0, };  // Counter of code lengths
-   int next_code[16] = { 0, };  // Code for a specific length
-   // 16 = (15 is max length of a code when inflating) + (1 for zero)
-
-   // Step 1:  Count the code lengths
-   for (i = 0; i < numval; i ++)
-     {
-	j = lengths[i];
-	if (j > 15)
-	  return 1;
-	bl_count[j] ++;
-     }
-
-   // Step 2:  Find numerical value of the smallest code of each length
-   // Also note that I've inserted some weak validation code here.  I'm
-   // not 100% sure that it is up to RFC specs, but it seems to work fine
-   // in my tests
-   //
-   // The validation theory is that at the root node, you have 2 branches or
-   // values possible.  If you branch, you get 2 more potentials.  If you
-   // get a value, you lose one potential.  So, if the root node has one of
-   // each, the number of potentials at the next level is still two.  If that
-   // node just has branches, the number of potentials is four.  If both of
-   // the nodes on the following level just have values, the number of
-   // potentials is 0, leaving us with a complete tree.
-   //
-   // If I don't validate and if an invalid tree gets generated, an
-   // infinite loop is possible
-   bl_count[0] = 0;
-   j = 0;
-   len = 2;
-   for (i = 1; i < 16; i ++)
-     {
-	len -= bl_count[i];
-	len *= 2;
-	j = (j + bl_count[i - 1]) << 1;
-	next_code[i] = j;
-     }
-   if (len)
-     return 1;
-
-   // Step 3:  Assign numerical values to all codes
-   BlankNode = 1;
-   currentTree[0].b0 = 0x0000;
-   currentTree[0].b1 = 0x0000;
-   for (i = 0; i < numval; i ++)
-     {
-	len = lengths[i];
-	if (len != 0)
-	  {
-	     this_code = next_code[len];
-	     next_code[len] ++;
-	     mask = 1 << (len - 1);
-	     j = 0;
-	     while (mask > 1)
-	       {
-		  if (this_code & mask)
-		    bitData = &(currentTree[j].b1);
-		  else
-		    bitData = &(currentTree[j].b0);
-
-		  if (*bitData == 0x0000)
-		    {
-		       *bitData = BlankNode;
-		       j = BlankNode;
-		       BlankNode ++;
-		       currentTree[j].b0 = 0x0000;
-		       currentTree[j].b1 = 0x0000;
-		    }
-		  else
-		    j = *bitData;
-
-		  mask >>= 1;
-	       }
-	     if (this_code & 0x01)
-	       currentTree[j].b1 = 0x8000 | i;
-	     else
-	       currentTree[j].b0 = 0x8000 | i;
-	  }
-     }
-
-#ifdef VERBOSE
-   fprintf(stderr, "%d table entries used\n",
-	   BlankNode);
-   if (numval < 20) {
-      for (i = 0; i < BlankNode; i ++)
-	{
-	   fprintf(stderr, "0x%03x - ", i);
-	   if (currentTree[i].b0 & 0x8000)
-	     fprintf(stderr, "value: 0x%03x ", currentTree[i].b0 ^ 0x8000);
-	   else
-	     fprintf(stderr, " link: 0x%03x ", currentTree[i].b0);
-
-	 if (currentTree[i].b1 & 0x8000)
-	   fprintf(stderr, "value: 0x%03x\n", currentTree[i].b1 ^ 0x8000);
-	 else
-	   fprintf(stderr, " link: 0x%03x\n", currentTree[i].b1);
-      }
-   }
-#endif
-
-   return 0;
-}
-
-
-// Using the tree passed in, read bits from the data stream until we arrive
-// at the proper value
-//
-// This function consumes a large percentage of time (#2)
-int DecodeValue(z_stream *zs, HufNode *currentTree)
-{
-   unsigned int i = 0;
-
-   // decode one symbol of the data per iteration
-   // Infinite loop detection code could go here.  Maximum
-   // bits to read is 15.
-   while (i < 0x8000)
-     {
-	if (READBIT(zs))
-	  i = currentTree[i].b1;
-	else
-	  i = currentTree[i].b0;
-     }
-   return i & 0x7FFF;
-}
-
-
-int Decompress_Stored(z_stream *zs)
-{
-   int blockLen, cSum;
-
-#ifdef VERBOSE
-   fprintf(stderr, "Stored\n");
-#endif
-
-   zs->reserved = 1;;
-   if (zs->avail_in < 4)
-     return -1;
-
-   zs->avail_in -= 4;
-   blockLen = *(zs->next_in ++);
-   blockLen |= *(zs->next_in ++) << 8;
-
-   cSum = *(zs->next_in ++);
-   cSum |= (*(zs->next_in ++) << 8);
-
-   if ((blockLen + cSum) ^ 0xFFFF)
-     return 1;
-   if (zs->avail_in < blockLen || zs->avail_out < blockLen)
-     return -1;
-   zs->avail_in -= blockLen;
-   zs->avail_out -= blockLen;
-
-   while (blockLen --)
-     {
-	*(zs->next_out) = *(zs->next_in);
-	zs->next_out ++;
-	zs->next_in ++;
-     }
-
-   return 0;
-}
-
-
-int MakeTrees(z_stream *zs, char is_fixed, HufNode *literalTree,
-		     HufNode *distanceTree)
-{
-   // Order of the bit length code lengths
-   static const unsigned border[] = {
-      16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 };
-   unsigned char ll[288+32];
-   int i, j, n, l, literalCodes, distCodes;
-
-   if (is_fixed)
-     {
-	literalCodes = 288;
-
-	// Set a large range to 8
-	for (i = 0; i < 288; i ++)
-	  ll[i] = 8;
-	// In that range, set some to 9 and others to 7
-	// (smaller code, but slightly slower table generation)
-	for (i = 144; i < 256; i ++)
-	  ll[i] = 9;
-	for (; i < 280; i ++)
-	  ll[i] = 7;
-
-	distCodes = 32;
-
-	for (i = 288; i < 320; i ++)
-	  ll[i] = 5;
-     }
-   else
-     {
-	literalCodes = 257 + READBITS(zs, 5);
-	distCodes = 1 + READBITS(zs, 5);
-	l = 4 + READBITS(zs, 4);
-
-	for (j = 0; j < 19; j ++)
-	  ll[j] = 0;
-
-	// Get the decode tree code lengths
-	// The decode tree is Huffman encoded
-
-	for (j = 0; j < l; j++)
-	  {
-	     ll[border[j]] = READBITS(zs, 3);
-	  }
-	if (CreateTree(distanceTree, 19, ll))
-	   return 1;
-
-	// read in literal and distance code lengths
-	n = literalCodes + distCodes;
-	i = 0;
-	while (i < n)
-	  {
-	     j = DecodeValue(zs, distanceTree);
-	     if (j < 16)	// length of code in bits (0..15)
-	       ll[i++] = j;
-	     else if (j == 16)
-	       {	// repeat last length 3 to 6 times
-		  j = 3 + READBITS(zs, 2);
-
-		  if (i + j > n)
-		    return 1;
-
-		  l = i ? ll[i-1] : 0;
-		  while (j --)
-		    ll[i++] = l;
-	       }
-	     else
-	       {
-		  if (j == 17)		// 3 to 10 zero length codes
-		    j = 3 + READBITS(zs, 3);
-		  else		// j == 18: 11 to 138 zero length codes
-		    j = 11 + READBITS(zs, 7);
-
-		  if (i + j > n)
-		       return 1;
-
-		  while (j --)
-		    ll[i++] = 0;
-	       }
-	  }
-     }
-
-
-   // Can overwrite tree decode tree as it is not used anymore
-   if (CreateTree(literalTree, literalCodes, &ll[0]))
-     return 1;
-
-   if(CreateTree(distanceTree, distCodes, &ll[literalCodes]))
-     return 1;
-
-   return 0;
-}
-
-
-// This function consumes a large percentage of time (#3)
-// Most output produced by gzip/zlib/etc is dynamic.
-int Decompress_DynamicOrFixed(z_stream *zs, char is_fixed)
-{
-   // Copy lengths for literal codes 257..285
-   static const unsigned short cplens[] = {
-      3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31,
-	35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 };
-   // Extra bits for literal codes 257..285
-   static const unsigned short cplext[] = {
-      0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2,
-	3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99 }; // 99==invalid
-   // Copy offsets for distance codes 0..29
-   static const unsigned short cpdist[] = {
-      0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0007, 0x0009, 0x000d,
-	0x0011, 0x0019, 0x0021, 0x0031, 0x0041, 0x0061, 0x0081, 0x00c1,
-	0x0101, 0x0181, 0x0201, 0x0301, 0x0401, 0x0601, 0x0801, 0x0c01,
-	0x1001, 0x1801, 0x2001, 0x3001, 0x4001, 0x6001 };
-   // Extra bits for distance codes
-   static const unsigned short cpdext[] = {
-      0,  0,  0,  0,  1,  1,  2,  2,
-	3,  3,  4,  4,  5,  5,  6,  6,
-	7,  7,  8,  8,  9,  9, 10, 10,
-	11, 11, 12, 12, 13, 13 };
-   HufNode literalTree[288];
-   HufNode distanceTree[32];
-   int j, l, dist;
-
-#ifdef VERBOSE
-   if (is_fixed)
-     fprintf(stderr, "Fixed Huffman codes\n");
-   else
-     fprintf(stderr, "Dynamic Huffman codes\n");
-#endif
-
-   if (MakeTrees(zs, is_fixed, literalTree, distanceTree))
-     return 1;
-
-   while (1)
-     {
-	j = DecodeValue(zs, literalTree);
-	if (j >= 256)
-	  {
-	     if (j == 256)     // EOF
-	       break;
-
-	     //printf("%04x ", j);
-	     j -= 256 + 1;  // bytes + EOF
-
-	     l = READBITS(zs, cplext[j]) + cplens[j];
-	     //printf("%04x ", l);
-
-	     j = DecodeValue(zs, distanceTree);
-	     //printf("%02x ", j);
-
-	     dist = READBITS(zs, cpdext[j]) + cpdist[j];
-	     //printf("%04x ", dist);
-
-	     //printf("LZ77 len %d dist %d @%04x\n", l, dist, bIdx);
-	     while(l--)
-	       {
-		  //printf("%02x ", c);
-		  if (! zs->avail_out --)
-		    return -1;
-
-		  *(zs->next_out ++) = *(zs->next_out - dist);
-	       }
-	     //printf("\n");
-	  }
-	else
-	  {
-	     //printf("%02x\n", j);
-	     if (! zs->avail_out --)
-	       return -1;
-	     *(zs->next_out ++) = (unsigned char) j;
-	  }
-     }
-   return 0;
-}
-
-
-// Returns 0 if success
-int InflateData(z_stream *zs) {
-   int last, type;
-
-   zs->reserved = 1;;
-
-   do
-     {
-	last = READBIT(zs);
-#ifdef VERBOSE
-	if (last)
-	  fprintf(stderr, "Last Block: ");
-	else
-	  fprintf(stderr, "Not Last Block: ");
-#endif
-
-	type = READBITS(zs, 2);
-
-	if (type == 0)
-	  {
-#ifdef VERBOSE
-	  	fprintf(stderr, "Decompress_Stored..");
-#endif
-	     if (Decompress_Stored(zs))
-	       return 1;
-	  }
-	else if (type > 2)
-	  {
-#ifdef VERBOSE
-	     if (type == 3)
-	       fprintf(stderr, "Reserved block type!!\n");
-	     else  // the "else" should never happen
-	       fprintf(stderr, "Unexpected value %d!\n", type);
-#endif
-	     zs->reserved = 1;;
-	     return 1;
-	  }
-	else
-	  {
-#ifdef VERBOSE
-	  	fprintf(stderr, "Decompress_DynamicOrFixed..");
-#endif
-	     if (Decompress_DynamicOrFixed(zs, type & 0x01))
-	       return 1;
-	  }
-     } while(!last);
-
-   zs->reserved = 1;;
-   return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.h b/lib/CPUs/MIPS/bsp/examples/inflate.h
deleted file mode 100644
index 1f6fd38..0000000
--- a/lib/CPUs/MIPS/bsp/examples/inflate.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifdef USE_ZLIB_STRUCT
-#include "SysZLib.h"  // For PalmOS.  Change to your liking.
-#else
-typedef struct z_stream_s
-{
-   unsigned char *next_in;  // Next input byte (CHANGES)
-   unsigned int avail_in;  // number of bytes left at next_in
-   unsigned char *next_out;  // Next output byte goes here (CHANGES)
-   unsigned int avail_out;  // number of bytes left at next_out
-   unsigned int reserved;  // For the readbit() and readbits() functions
-                           // Bigger than 1 byte
-} z_stream;
-#endif
-
-int InflateData(z_stream *zs);
diff --git a/lib/CPUs/MIPS/bsp/examples/irq.c b/lib/CPUs/MIPS/bsp/examples/irq.c
deleted file mode 100644
index 85e1320..0000000
--- a/lib/CPUs/MIPS/bsp/examples/irq.c
+++ /dev/null
@@ -1,92 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <stdlib.h>
-#include "libsys.h"
-#include "regdef.h"
-#include "xcpt.h"
-#include "irq.h"
-
-static fp_irq_t g_irq_handler[MAX_NUM_IRQ] = {NULL};
-
-int _irq_dispatch(struct xcptcontext * xcp)
-{
-	int i, ip, cause;
-
-	cause = xcp->cr & xcp->sr;
-	ip =  (cause >> 8) & 0xFF;
-
-	for (i=0; i < MAX_NUM_IRQ; i++)
-	{
-		if (ip & 1)
-			if (g_irq_handler[i])
-				(g_irq_handler[i])(xcp);
-
-		ip >>= 1;
-	}
-
-	return 0;
-}
-
-void interrupt_register(int irq_num, fp_irq_t fp)
-{
-	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
-		g_irq_handler[irq_num] = fp;
-
-}
-
-void interrupt_enable(int irq_num)
-{
-	reg_t reg, im;
-
-	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
-	{
-		im = 1 << irq_num;
-		reg = CP0_SR_read();
-		reg |= (SR_MASK_IM & (im << 8));
-		CP0_SR_write(reg);
-	}
-
-}
-
-void interrupt_disable(int irq_num)
-{
-	reg_t reg, im;
-
-	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
-	{
-		im = 1 << irq_num;
-		reg = CP0_SR_read();
-		reg &= ~(SR_MASK_IM & (im << 8));
-		CP0_SR_write(reg);
-	}
-}
-
-void interrupt_set(int irq_num)
-{
-	reg_t reg, ip;
-
-	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
-	{
-		ip = 1 << irq_num;
-		reg = CP0_CR_read();
-		reg |= (CR_MASK_IP & (ip << 8));
-		CP0_CR_write(reg);
-	}
-}
-
-void interrupt_clr(int irq_num)
-{
-	reg_t reg, ip;
-
-	if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ))
-	{
-		ip = 1 << irq_num;
-		reg = CP0_CR_read();
-		reg &= ~(CR_MASK_IP & (ip << 8));
-		CP0_CR_write(reg);
-	}
-}
-
-
diff --git a/lib/CPUs/MIPS/bsp/examples/irq.h b/lib/CPUs/MIPS/bsp/examples/irq.h
deleted file mode 100644
index d6c343c..0000000
--- a/lib/CPUs/MIPS/bsp/examples/irq.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef IRQ_H
-#define IRQ_H
-
-#include "xcpt.h"
-
-#define MAX_NUM_IRQ				8
-
-typedef void (*fp_irq_t)(struct xcptcontext * xcp);
-
-int _irq_dispatch(struct xcptcontext * xcp);
-void interrupt_register(int irq_num, fp_irq_t fp);
-void interrupt_enable(int irq_num);
-void interrupt_disable(int irq_num);
-
-#endif // IRQ_H
diff --git a/lib/CPUs/MIPS/bsp/examples/isqrt.c b/lib/CPUs/MIPS/bsp/examples/isqrt.c
deleted file mode 100644
index 6022fc1..0000000
--- a/lib/CPUs/MIPS/bsp/examples/isqrt.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-#include <string.h>
-#include "snipmath.h"
-
-#define BITSPERLONG 32
-
-#define TOP2BITS(x) ((x & (3L << (BITSPERLONG-2))) >> (BITSPERLONG-2))
-
-
-/* usqrt:
-    ENTRY x: unsigned long
-    EXIT  returns floor(sqrt(x) * pow(2, BITSPERLONG/2))
-
-    Since the square root never uses more than half the bits
-    of the input, we use the other half of the bits to contain
-    extra bits of precision after the binary point.
-
-    EXAMPLE
-        suppose BITSPERLONG = 32
-        then    usqrt(144) = 786432 = 12 * 65536
-                usqrt(32) = 370727 = 5.66 * 65536
-
-    NOTES
-        (1) change BITSPERLONG to BITSPERLONG/2 if you do not want
-            the answer scaled.  Indeed, if you want n bits of
-            precision after the binary point, use BITSPERLONG/2+n.
-            The code assumes that BITSPERLONG is even.
-        (2) This is really better off being written in assembly.
-            The line marked below is really a "arithmetic shift left"
-            on the double-long value with r in the upper half
-            and x in the lower half.  This operation is typically
-            expressible in only one or two assembly instructions.
-        (3) Unrolling this loop is probably not a bad idea.
-
-    ALGORITHM
-        The calculations are the base-two analogue of the square
-        root algorithm we all learned in grammar school.  Since we're
-        in base 2, there is only one nontrivial trial multiplier.
-
-        Notice that absolutely no multiplications or divisions are performed.
-        This means it'll be fast on a wide range of processors.
-*/
-
-void usqrt(unsigned long x, struct int_sqrt *q)
-{
-      unsigned long a = 0L;                   /* accumulator      */
-      unsigned long r = 0L;                   /* remainder        */
-      unsigned long e = 0L;                   /* trial product    */
-
-      int i;
-
-      for (i = 0; i < BITSPERLONG; i++)   /* NOTE 1 */
-      {
-            r = (r << 2) + TOP2BITS(x); x <<= 2; /* NOTE 2 */
-            a <<= 1;
-            e = (a << 1) + 1;
-            if (r >= e)
-            {
-                  r -= e;
-                  a++;
-            }
-      }
-      memcpy(q, &a, sizeof(long));
-}
-
-#ifdef TEST
-
-#include <stdio.h>
-#include <stdlib.h>
-
-main(void)
-{
-      int i;
-      unsigned long l = 0x3fed0169L;
-      struct int_sqrt q;
-
-      for (i = 0; i < 101; ++i)
-      {
-            usqrt(i, &q);
-            printf("sqrt(%3d) = %2d, remainder = %2d\n",
-                  i, q.sqrt, q.frac);
-      }
-      usqrt(l, &q);
-      printf("\nsqrt(%lX) = %X, remainder = %X\n", l, q.sqrt, q.frac);
-      return 0;
-}
-
-#endif /* TEST */
diff --git a/lib/CPUs/MIPS/bsp/examples/kernel.S b/lib/CPUs/MIPS/bsp/examples/kernel.S
deleted file mode 100644
index aa0648b..0000000
--- a/lib/CPUs/MIPS/bsp/examples/kernel.S
+++ /dev/null
@@ -1,184 +0,0 @@
-#include <regdef.h>
-#include <xcpt_asm.h>
-
-		.section .exc_vect
-_xcpt_vector_tbl:
-		.fill	16, 4, 0		
-			
-		.text
-
-LEAF(_xcpt_handler)
-		.set noreorder
-		.set noat
-		/* Note: exceptions do not save and restore registers k0 and k1.
-		* on entry, k1 = exception class.
-		*/
-		
-		/* allocate exception stack frame (on 8-byte boundary) */
-		subu k1, sp, XCP_SIZE
-		srl k1, 3 	/* shift right/left -> alligned on boundary */
-		sll k1, 3
-
-		/* save enough registers to get by */
-		sw AT, XCP_AT(k1)
-		sw v0, XCP_V0(k1)
-		sw v1, XCP_V1(k1)
-		sw a0, XCP_A0(k1)
-		sw a1, XCP_A1(k1)
-		sw a2, XCP_A2(k1)
-		sw a3, XCP_A3(k1)
-		sw sp, XCP_SP(k1)
-		sw ra, XCP_RA(k1)
-		
-		/* get coprocessor 0 exception state */
-		mfc0 a0, CP0_CR
-		mfc0 a1, CP0_SR
-		mfc0 a2, CP0_BADDR
-		mfc0 a3, CP0_EPC
-
-		/* we can safely use AT now */
-		.set at
-
-		/* switch to using sp to point at exception frame */
-		move sp, k1
-		
-		/* nothing sensible to store for k0/k1, store zero */
-		sw zero, XCP_K0(sp)
-		sw zero, XCP_K1(sp)		
-
-		/* we are now interruptible: dump all remaining state
-		* into the exception stack frame.
-		*/
-		/* coprocessor exception state */
-		sw a0, XCP_CR(sp)
-		sw a1, XCP_SR(sp)
-		sw a2, XCP_BADDR(sp)
-		sw a3, XCP_EPC(sp)
-
-		/* mdhi and mdlo */
-		mfhi v0
-		mflo v1
-		sw v0, XCP_MDHI(sp)
-		sw v1, XCP_MDLO(sp)
-
-		/* Save all the other general registers.
-		* We save zero, s0-s7 and s8 as well, as instruction emulators (e.g. FP
-		* operations) and debuggers rely on all registers stored together in
-		* well-defined structure.
-		*/
-		sw zero, XCP_ZERO(sp)
-		sw t0, XCP_T0(sp)
-		sw t1, XCP_T1(sp)
-		sw t2, XCP_T2(sp)
-		sw t3, XCP_T3(sp)
-		sw t4, XCP_T4(sp)
-		sw t5, XCP_T5(sp)
-		sw t6, XCP_T6(sp)
-		sw t7, XCP_T7(sp)
-		sw s0, XCP_S0(sp)
-		sw s1, XCP_S1(sp)
-		sw s2, XCP_S2(sp)
-		sw s3, XCP_S3(sp)
-		sw s4, XCP_S4(sp)
-		sw s5, XCP_S5(sp)
-		sw s6, XCP_S6(sp)
-		sw s7, XCP_S7(sp)
-		sw t8, XCP_T8(sp)
-		sw t9, XCP_T9(sp)
-		sw gp, XCP_GP(sp)
-		sw s8, XCP_S8(sp)
-
-		/* I don't know what the following does. [rb] */
-		/* load our _gp pointer */
-#		la gp, _gp
-
-		/* and call the C exception handler */
-		move a0, sp	# arg1 = &xcp
-		subu sp, 16	# (arg save area)
-		j _xcpt_call
-		move ra, zero	# fake return address
-		
-		/* This strange call to _xcpt_call with zero return address is to
-		* help exception-aware debuggers to trace back over the exception event.
-		* We are basically interposing a bogus stackframe (with a zero return
-		* address) between the C exception handler and the actual machine
-		* exception.
-		*/
-$xcptrest:
-		.set noat
-		add AT, sp, 16
-		
-		/* at points to exception frame */
-$xcptrestother:
-		/* restore all state */
-		/* restore most general registers */
-		lw t0, XCP_T0(AT)
-		lw t1, XCP_T1(AT)
-		lw t2, XCP_T2(AT)
-		lw t3, XCP_T3(AT)
-		lw t4, XCP_T4(AT)
-		lw t5, XCP_T5(AT)
-		lw t6, XCP_T6(AT)
-		lw t7, XCP_T7(AT)
-		lw s0, XCP_S0(AT)
-		lw s1, XCP_S1(AT)
-		lw s2, XCP_S2(AT)
-		lw s3, XCP_S3(AT)
-		lw s4, XCP_S4(AT)
-		lw s5, XCP_S5(AT)
-		lw s6, XCP_S6(AT)
-		lw s7, XCP_S7(AT)
-		lw t8, XCP_T8(AT)
-		lw t9, XCP_T9(AT)
-		lw gp, XCP_GP(AT)
-		lw s8, XCP_S8(AT)
-
-		/* mdhi and mdlo */
-		lw v0, XCP_MDHI(AT)
-		lw v1, XCP_MDLO(AT)
-		mthi v0
-		mtlo v1
-
-		/* remaining general registers */
-		lw a0, XCP_A0(AT)
-		lw a1, XCP_A1(AT)
-		lw a2, XCP_A2(AT)
-		lw a3, XCP_A3(AT)
-		lw ra, XCP_RA(AT)
-
-		/* restore the exception-time status register */
-		.set noreorder
-		lw v0, XCP_SR(AT)
-		nop			
-		mtc0 v0, CP0_SR
-		lw v1, XCP_V1(AT)
-		lw v0, XCP_V0(AT)
-		lw sp, XCP_SP(AT)
-
-		/* we are not uninterruptible and can use k1 safely */
-		lw k1, XCP_EPC(AT)
-		lw AT, XCP_AT(AT)
-		mtc0 k1, CP0_EPC
-		j	k1
-		rfe
-
-		.set reorder
-		.set at
-END(_xcpt_handler)
-		
-		
-LEAF(_xcpt_call)
-		/* on entry: a0 == &xcp */
-		subu sp, 24
-		sw ra, 16(sp)
-		
-		/* punt out to _xcpt_deliver */
-		jal _xcpt_deliver
-		nop
-		lw ra, 16(sp)
-		addu sp, 24
-		beqz ra, $xcptrest
-		nop
-		j ra
-		nop
-END(_xcpt_call)	
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.c b/lib/CPUs/MIPS/bsp/examples/libsys.c
deleted file mode 100644
index 93721da..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys.c
+++ /dev/null
@@ -1,1101 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/resource.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include "libsys.h"
-
-
-// ---------------------------------------------------------------------------------
-// Forward declarations
-// ---------------------------------------------------------------------------------
-void flush(UINT32 port);
-UINT32 GetPort(int file);
-
-// ---------------------------------------------------------------------------------
-// Types
-// ---------------------------------------------------------------------------------
-void libsys_init(void)
-{
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	UINT32 volatile *pITIM_ctrl = (UINT32*)SYS_ITIM_CTRL;
-
-	Screen_clr();
-
-	// Disable timers
-	*pITIM_ctrl = 0;
-
-	// Disable all VGA stuff
-	*pVGA_ctrl = 0;
-
-	// Initialzie syscall support
-	syscalls_init();
-
-	// Initalize debugger
-	dbg_init();
-
-	// flush stdin
-	flush(GetPort(0));
-
-	// Do some initializations here
-
-}
-
-UINT32 GetPort(int file)
-{
-	if (file == 0)
-		return 0;
-
-	if (file == 1)
-		return 0;
-
-	if (file == 2)
-		return 2;
-}
-
-enum
-{
-	IF_TYPE_INVALID = 0,
-	IF_TYPE_UART,
-	IF_TYPE_PS2,
-	IF_TYPE_VGA
-};
-
-typedef struct _suart_if_t
-{
-	volatile UINT32 *pCTRL;
-	volatile UINT32 *pDATA;
-	volatile UINT32 *pBAUD;
-} uart_if_t;
-
-typedef struct _sps2_if_t
-{
-	volatile UINT32 *pCTRL;
-	volatile UINT32 *pDATA;
-} ps2_if_t;
-
-typedef struct _svga_if_t
-{
-	volatile UINT32 *pCTRL;
-	volatile UINT32 *pDATA;
-	volatile UINT32 *pCSRX;
-	volatile UINT32 *pCSRY;
-} vga_if_t;
-
-typedef struct _scon_if_in_t
-{
-	UINT32 type;
-	void *pIF;
-} con_if_in_t;
-
-typedef struct _scon_if_out_t
-{
-	UINT32 type;
-	void *pIF;
-} con_if_out_t;
-
-// ---------------------------------------------------------------------------------
-// Globals
-// ---------------------------------------------------------------------------------
-static uart_if_t uart_if[2] =
-{
-	{(UINT32*)SYS_UART0_STAT, (UINT32*)SYS_UART0_DATA, (UINT32*)SYS_UART0_BAUD},
-	{(UINT32*)SYS_UART1_STAT, (UINT32*)SYS_UART1_DATA, (UINT32*)SYS_UART1_BAUD}
-};
-
-extern ps2_if_t ps2_if[];
-
-static vga_if_t vga_if =
-{
-	(UINT32*)SYS_VGA_CTRL, (UINT32*)SYS_VGA_ASCII, (UINT32*)SYS_VGA_POSX, (UINT32*)SYS_VGA_POSY
-};
-
-static con_if_in_t con_if_in[4] =
-{
-	{IF_TYPE_UART, &uart_if[0]},
-	{IF_TYPE_UART, &uart_if[1]},
-	{IF_TYPE_PS2, &ps2_if[0]},
-	{IF_TYPE_PS2, &ps2_if[1]}
-};
-
-static con_if_out_t con_if_out[4] =
-{
-	{IF_TYPE_UART, &uart_if[0]},
-	{IF_TYPE_UART, &uart_if[1]},
-	{IF_TYPE_VGA, &vga_if},
-	{IF_TYPE_INVALID, NULL}
-};
-
-// ---------------------------------------------------------------------------------
-// MIPS specific
-// ---------------------------------------------------------------------------------
-UINT32 CP0_SR_read(void)
-{
-	UINT32 result;
-
-	__asm__
-	(
-		"mfc0   %[val], $12\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_SR_write(UINT32 val)
-{
-	__asm__
-	(
-		"mtc0   %[val], $12\n"
-		: /* no output */
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_CR_read(void)
-{
-	UINT32 result;
-
-	__asm__
-	(
-		"mfc0   %[val], $13\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_CR_write(UINT32 val)
-{
-	__asm__
-	(
-		"mtc0   %[val], $13\n"
-		:
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_TR_read(void)
-{
-	UINT32 result;
-
-	__asm__
-	(
-		"mfc0   %[val], $31\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_TR_write(UINT32 val)
-{
-	__asm__
-	(
-		"mtc0   %[val], $31\n"
-		:
-		: [val] "r" (val)
-	);
-}
-
-UINT32 CP0_PRID_read(void)
-{
-	UINT32 result;
-
-	__asm__
-	(
-		"mfc0   %[val], $15\n"
-		: [val] "=r" (result)
-	);
-
-	return result;
-}
-
-void CP0_TR_write_ptr(UINT32* pPtr)
-{
-	__asm__
-	(
-		"swc0   $31, 0(%[pPtr])\n"
-		:
-		: [pPtr] "r" (pPtr)
-	);
-}
-
-void CP0_TR_read_ptr(UINT32* pPtr)
-{
-	__asm__
-	(
-		"lwc0   $31, 0(%[pPtr])\n"
-		:
-		: [pPtr] "r" (pPtr)
-	);
-}
-
-void ICACHE_invalidate_all(void)
-{
-	__asm__
-	(
-		"cop0	32\n"
-	);
-}
-
-void ICACHE_invalidate_at(UINT32* pPtr)
-{
-	__asm__
-	(
-		"mtc0   %[pPtr], $31\n"
-		"cop0	33\n"
-		:
-		: [pPtr] "r" (pPtr)
-	);
-}
-
-void DCACHE_invalidate_all(void)
-{
-	__asm__
-	(
-		"cop0	34\n"
-	);
-}
-
-void DCACHE_invalidate_at(UINT32* pPtr)
-{
-	__asm__
-	(
-		"mtc0   %[pPtr], $31\n"
-		"cop0	35\n"
-		:
-		: [pPtr] "r" (pPtr)
-	);
-}
-
-// -------------------------------------------------------------
-// BEGIN QUICK AND DIRTY
-// -------------------------------------------------------------
-//keymap for the AT keyboard SG layout
-typedef struct
-{
-    UINT8 scancode;
-    UINT8 unshifted;
-    UINT8 shifted;
-    UINT8 altered;
-} libsys_key_entry_t;
-
-#define SHIFTED (1<<0)
-#define ALTERED (1<<1)
-#define CONTROLLED (1<<2)
-
-static const libsys_key_entry_t __keymap_german[] =
-{
-    {0x1c, 'a', 'A', 'a'},
-    {0x32, 'b', 'B', 'b'},
-    {0x21, 'c', 'C', 'c'},
-    {0x23, 'd', 'D', 'd'},
-    {0x24, 'e', 'E', '€'},
-    {0x2b, 'f', 'F', 'f'},
-    {0x34, 'g', 'G', 'g'},
-    {0x33, 'h', 'H', 'h'},
-    {0x43, 'i', 'I', 'i'},
-    {0x3b, 'j', 'J', 'j'},
-    {0x42, 'k', 'K', 'k'},
-    {0x4b, 'l', 'L', 'l'},
-    {0x3a, 'm', 'M', 'µ'},
-    {0x31, 'n', 'N', 'n'},
-    {0x44, 'o', 'O', 'o'},
-    {0x4d, 'p', 'P', 'p'},
-    {0x15, 'q', 'Q', '@'},
-    {0x2d, 'r', 'R', 'r'},
-    {0x1b, 's', 'S', 's'},
-    {0x2c, 't', 'T', 't'},
-    {0x3c, 'u', 'U', 'u'},
-    {0x2a, 'v', 'V', 'v'},
-    {0x1d, 'w', 'W', 'w'},
-    {0x22, 'x', 'X', 'x'},
-    {0x1a, 'y', 'Y', 'y'},
-    {0x35, 'z', 'Z', 'z'},
-    {0x16, '1', '!', '1'},
-    {0x1e, '2', '"', '2'},
-    {0x26, '3', '§', '3'},
-    {0x25, '4', '$', '4'},
-    {0x2e, '5', '%', '5'},
-    {0x36, '6', '&', '6'},
-    {0x3d, '7', '/', '{'},
-    {0x3e, '8', '(', '['},
-    {0x46, '9', ')', ']'},
-    {0x45, '0', '=', '}'},
-    {0x4e, 'ß', '?', '\\'},
-    {0x29, ' ', ' ', ' '},
-    {0x41, ',', ';', ','},
-    {0x49, '.', ':', '.'},
-    {0x4a, '-', '_', '-'},
-    {0x52, 'ä', 'Ä', 'ä'},
-    {0x4c, 'ö', 'Ö', 'ö'},
-    {0x54, 'ü', 'Ü', 'ü'},
-    {0x5a, '\n', '\n', '\n'},       //RETURN
-    {0x5b, '+', '*', '~'},
-    {0x5d, '#', '\'', '#'},
-    {0x0e, '^', '°', '^'},
-    {0x61, '<', '>', '|'},
-    {0x66, '\b', '\b', '\b'},
-    {0}       //sentinel
-};
-
-static char __findkey(char scancode, int mode)
-{
-    const libsys_key_entry_t *p = __keymap_german;
-    while (p->scancode)
-    {
-        if (p->scancode == scancode)
-        {
-            switch (mode)
-            {
-                case SHIFTED:
-                    return p->shifted;
-                case ALTERED:
-                    return p->altered;
-                case ALTERED|SHIFTED:
-                default:
-                    return p->unshifted;
-            }
-        }
-        p++;
-    }
-    return 0;
-}
-
-#define RELEASE         0x8000
-#define SPECIALKEY      0x4000
-#define EXTENDED        0x2000
-#define X_CONTROLLED    0x0400
-#define X_ALTERED       0x0200
-#define X_SHIFTED       0x0100
-#define CAPS    (SPECIALKEY|0x58)
-#define F1      (SPECIALKEY|0x05)
-#define F2      (SPECIALKEY|0x06)
-#define F3      (SPECIALKEY|0x04)
-#define F4      (SPECIALKEY|0x0c)
-#define F5      (SPECIALKEY|0x03)
-#define F6      (SPECIALKEY|0x0b)
-#define F7      (SPECIALKEY|0x83)
-#define F8      (SPECIALKEY|0x0a)
-#define F9      (SPECIALKEY|0x01)
-#define F10     (SPECIALKEY|0x09)
-#define F11     (SPECIALKEY|0x78)
-#define F12     (SPECIALKEY|0x07)
-#define ARROW_UP        (SPECIALKEY|EXTENDED|0x75)
-#define ARROW_DOWN      (SPECIALKEY|EXTENDED|0x72)
-#define ARROW_LEFT      (SPECIALKEY|EXTENDED|0x6b)
-#define ARROW_RIGHT     (SPECIALKEY|EXTENDED|0x74)
-
-UINT32 PS2_readchar(ps2_if_t *pIF)
-{
-	if (!pIF)
-		return -1;
-
-	while (!(SYS_PS2_BIT_RX_AVAIL & *pIF->pCTRL));
-
-	return (*pIF->pDATA & 0xFF);
-
-}
-
-UINT32 con_readchar(ps2_if_t *pIF)
-{
-	UINT8 c;
-	static char mode = 0;
-	static char nextrelease = 0;
-	static char extended = 0;
-	int flags = 0;
-	int char_valid = 0;
-	UINT8 key;
-
-	key = PS2_readchar(pIF);
-
-	switch (key)
-	{
-		case 0xf0: //release key
-			nextrelease = 1;
-			break;
-		case 0x14: //control key
-			if (nextrelease)
-			{
-				mode &= ~CONTROLLED;
-			} else
-			{
-				mode |= CONTROLLED;
-			}
-			nextrelease = 0;
-			break;
-		case 0x12: //left SHIFT
-		case 0x59: //right SHIFT
-			if (nextrelease)
-			{
-				mode &= ~SHIFTED;
-			} else
-			{
-				mode |= SHIFTED;
-			}
-			nextrelease = 0;
-			break;
-		case 0x11: //left and right ALT (right one also with E0)
-			if (nextrelease)
-			{
-				mode &= ~ALTERED;
-			} else
-			{
-				mode |= ALTERED;
-			}
-			nextrelease = 0;
-			break;
-		case 0xe0:  //extended key following
-			extended = 1;
-			break;
-		default:
-			if (nextrelease) flags |= RELEASE;
-			if (extended) flags |= EXTENDED;
-			flags |= mode << 8;
-			c = __findkey(key, mode);
-			char_valid = (c && ((flags & RELEASE) != RELEASE));
-			nextrelease = 0;
-			extended = 0;
-			break;
-	}
-
-	if (char_valid)
-	{
-		// fprintf(stderr, "c = %c (%d), flags = 0x%08X, mode = 0x%08X\n", c, c, flags, mode);
-		return c;
-	}
-
-	return -1;
-}
-// -------------------------------------------------------------
-// END QUICK AND DIRTY
-// -------------------------------------------------------------
-
-// ------------------------------------
-// Low-level I/O
-// ------------------------------------
-int UART_readchar(uart_if_t *pIF)
-{
-	if (!pIF)
-		return -1;
-
-	if (SYS_UART_BIT_RX_AVAIL & *pIF->pCTRL)
-		return (*pIF->pDATA & 0xFF);
-
-	return -1;
-}
-
-void UART_writechar(uart_if_t *pIF, char c)
-{
-	if (!pIF)
-		return;
-
-	while((SYS_UART_BIT_TX_HALFFULL & *pIF->pCTRL) != 0);
-
-	*pIF->pDATA = (UINT32)c;
-}
-
-void cg_writechar(vga_if_t *pIF, char c)
-{
-	UINT32 code;
-
-	if (!pIF)
-		return;
-
-	// Output translation
-	switch(c)
-	{
-		case 'Ä':
-		code = 196;
-		break;
-
-		case 'ä':
-		code = 228;
-		break;
-
-		case 'Ö':
-		code = 214;
-		break;
-
-		case 'ö':
-		code = 246;
-		break;
-
-		case 'Ü':
-		code = 220;
-		break;
-
-		case 'ü':
-		code = 252;
-		break;
-
-		case '&':
-		code = 230;
-		break;
-
-		case '§':
-		code = 167;
-		break;
-
-		case 'ß':
-		code = 223;
-		break;
-
-		case '°':
-		code = 176;
-		break;
-
-		case 'µ':
-		code = 181;
-		break;
-
-		default:
-		code = (UINT32)c;
-		break;
-	}
-
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pDATA = code;
-}
-
-void cg_set_csr_x(vga_if_t *pIF, UINT32 coord)
-{
-	if (!pIF)
-		return;
-
-	// Set cursor
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCSRX = coord;
-}
-
-void cg_set_csr_y(vga_if_t *pIF, UINT32 coord)
-{
-	if (!pIF)
-		return;
-
-	// Set cursor
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCSRY = coord;
-}
-
-void cg_clr_line(vga_if_t *pIF)
-{
-	if (!pIF)
-		return;
-
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCTRL |= SYS_VGA_BIT_CLRLINE;
-}
-
-void cg_clr_screen(vga_if_t *pIF)
-{
-
-	if (!pIF)
-		return;
-
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCTRL |= SYS_VGA_BIT_CLRSCR;
-
-	// Cursor home
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCSRX = 0;
-
-	while (!(*pIF->pCTRL & SYS_VGA_BIT_CGRDY));
-		*pIF->pCSRY = 0;
-
-}
-
-void Screen_clr(void)
-{
-	cg_clr_screen(&vga_if);
-}
-
-void Screen_line_clr(void)
-{
-	cg_clr_line(&vga_if);
-}
-
-void Screen_csr_set_x(UINT32 coord)
-{
-	cg_set_csr_x(&vga_if, coord);
-}
-
-void Screen_csr_set_y(UINT32 coord)
-{
-	cg_set_csr_y(&vga_if, coord);
-}
-
-UINT32 Screen_get_resx(void)
-{
-	UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES;
-
-	return (0xFFF & (*pVGA_res >> 0));
-}
-
-UINT32 Screen_get_resy(void)
-{
-	UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES;
-
-	return (0xFFF & (*pVGA_res >> 12));
-}
-
-UINT32 Screen_get_fps(void)
-{
-	UINT32 volatile *pVGA_res = (UINT32*)SYS_VGA_RES;
-
-	return (0xFF & (*pVGA_res >> 24));
-}
-
-// ---------------------------------------------------------------------------------
-void flush(UINT32 port)
-{
-	int c;
-	con_if_in_t *pIF;
-
-	pIF = &con_if_in[port];
-
-	do
-	{
-		switch(pIF->type)
-		{
-			case IF_TYPE_UART:
-			c = UART_readchar((uart_if_t*)pIF->pIF);
-			break;
-
-			case IF_TYPE_PS2:
-			c = con_readchar((ps2_if_t*)pIF->pIF);
-			break;
-
-			default:
-			break;
-		}
-
-	} while(c > 0);
-}
-
-char readchar(UINT32 port)
-{
-	int c;
-	con_if_in_t *pIF;
-
-	pIF = &con_if_in[port];
-
-	do
-	{
-		switch(pIF->type)
-		{
-			case IF_TYPE_UART:
-			c = UART_readchar((uart_if_t*)pIF->pIF);
-			break;
-
-			case IF_TYPE_PS2:
-			c = con_readchar((ps2_if_t*)pIF->pIF);
-			break;
-
-			default:
-			break;
-		}
-
-	} while(c < 0);
-
-	return (char)c;
-}
-
-void writechar(UINT32 port, char c)
-{
-	con_if_out_t *pIF;
-
-	pIF = &con_if_out[port];
-
-	switch(pIF->type)
-	{
-		case IF_TYPE_UART:
-		UART_writechar((uart_if_t*)pIF->pIF, c);
-		break;
-
-		case IF_TYPE_VGA:
-		cg_writechar((vga_if_t*)pIF->pIF, c);
-		break;
-
-		default:
-		break;
-	}
-}
-
-void _putchar(UINT32 port, char c)
-{
-
-	con_if_out_t *pIF;
-
-	pIF = &con_if_out[port];
-
-	switch(pIF->type)
-	{
-		case IF_TYPE_UART:
-		if (c == 0x0A)
-			UART_writechar((uart_if_t*)pIF->pIF, 0x0D);
-		UART_writechar((uart_if_t*)pIF->pIF, c);
-		break;
-
-		case IF_TYPE_VGA:
-		cg_writechar((vga_if_t*)pIF->pIF, c);
-		if (c == 0x0A)
-		{
-			cg_clr_line((vga_if_t*)pIF->pIF);
-			cg_writechar((vga_if_t*)pIF->pIF, 0x0D);
-		}
-		break;
-
-		default:
-		break;
-	}
-}
-
-char _getchar(void)
-{
-	return readchar(GetPort(0));
-}
-
-void _exit (int exitcode)
-{
-	fflush(stdout);
-	fflush(stderr);
-	while(1);
-}
-
-void sleep(unsigned ms)
-{
-	unsigned stop;
-	struct tms t;
-
-	times(&t);
-	stop = t.tms_utime + ms;
-
-	do
-	{
-		times(&t);
-	} while (t.tms_utime < stop);
-
-}
-
-
-int getrusage(int who, struct rusage *usage)
-{
-	volatile long *pReg_usec = (long*)SYS_TIMER_USEC;
-	volatile long *pReg_sec = (long*)SYS_TIMER_SEC;
-
-	// who: RUSAGE_SELF or RUSAGE_CHILDREN
-	usage->ru_utime.tv_usec = *pReg_usec;
-	usage->ru_utime.tv_sec = *pReg_sec;
-	usage->ru_stime.tv_usec = *pReg_usec;
-	usage->ru_stime.tv_sec = *pReg_sec;
-}
-
-clock_t times(struct tms *buffer)
-{
-	volatile long *pReg_usec = (long*)SYS_TIMER_USEC;
-	volatile long *pReg_sec = (long*)SYS_TIMER_SEC;
-	long sec;
-	long usec;
-
-	sec = *pReg_sec;
-	usec = *pReg_usec;
-
-	if (buffer)
-	{
-		buffer->tms_utime = sec*1000 + usec/1000;
-		buffer->tms_stime = 0;
-		buffer->tms_cutime = 0;
-		buffer->tms_cstime = 0;
-	}
-
-	return (clock_t)sec;
-}
-
-int gettimeofday(struct timeval *tp, void *tzp)
-{
-	volatile long *pReg_usec = (long*)SYS_TIMER_USEC;
-	volatile long *pReg_sec = (long*)SYS_TIMER_SEC;
-
-	if (tp)
-	{
-		tp->tv_sec = *pReg_sec;
-		tp->tv_usec = *pReg_usec;
-	}
-
-	return 0;
-}
-
-int settimeofday(const struct timeval *tp, const struct timezone *tzp)
-{
-	volatile long *pReg_usec = (long*)SYS_TIMER_USEC;
-	volatile long *pReg_sec = (long*)SYS_TIMER_SEC;
-	div_t res;
-
-	res = div(tp->tv_usec, 1E6);
-
-	if (tp)
-	{
-		*pReg_usec = res.rem;
-		*pReg_sec  = tp->tv_sec + res.quot;
-	}
-
-	return 0;
-}
-
-caddr_t sbrk(int incr)
-{
-	extern char end;
-	extern char stack_ptr;
-	static char *heap_end;
-	char *prev_heap_end;
-
-	if (heap_end == 0)
-	{
-		heap_end = &end;
-	}
-
-	prev_heap_end = heap_end;
-	if (heap_end + incr > &stack_ptr)
-	{
-//		sputs("Heap and stack collision\n");
-//		sputs("Stack Ptr = ");print_word(&stack_ptr);sputs("\n");
-//		sputs("Heap end  = ");print_word(heap_end);sputs("\n");
-//		sputs("Increment = ");print_word(incr);sputs("\n");
-		exit(1);
-	}
-	heap_end += incr;
-	return (caddr_t) prev_heap_end;
-}
-
-int fstat(int file, struct stat *st)
-{
-//	sputs("fstat ("); print_word(file); sputs(")\n");
-	st->st_mode = S_IFCHR;
-	st->st_blksize = 0;
-	return 0;
-}
-
-int lseek(int file, int ptr, int dir)
-{
-//	sputs("lseek ("); print_word(file); sputs(")\n");
-	errno = ESPIPE;
-	return -1;
-}
-
-int open(const char *name, int flags, int mode)
-{
-//	sputs("open (\""); sputs(name); sputs("\")\n");
-	errno = EIO;
-	return -1;
-}
-
-int close(int file)
-{
-//	sputs("close ("); print_word(file); sputs(")\n");
-	return 0;
-}
-
-int read(int file, char *ptr, int len)
-{
-	UINT32 port;
-	int i;
-	char c;
-
-//	sputs("read (file="); print_word(file); sputs(", len ="); print_word(len); sputs(")\n");
-	i = 0;
-	port = GetPort(file);
-
-	while (i < len)
-	{
-		c = readchar(port);
-
-		if (c == 0x04)
-			break;
-
-		if ((c == 0x0D) || (c == 0x0A))
-		{
-			writechar(port, 0x0D);
-			ptr[i++] = 0x0D;
-			writechar(port, 0x0A);
-			ptr[i++] = 0x0A;
-			break;
-		}
-
-		writechar(port, c);
-		ptr[i++] = c;
-
-	}
-	return i;
-}
-
-int write(int file, char *ptr, int len)
-{
-	UINT32 port;
-	int i = 0;
-
-//	sputs("write ("); print_word(file); sputs(")\n");
-
-	port = GetPort(file);
-	for (i=0; i < len; i++)
-		_putchar(port, *ptr++);
-
-	return i;
-}
-
-int isatty(int file)
-{
-//	sputs("isatty ("); print_word(file); sputs(")\n");
-	return 1;
-}
-
-int getpid(void)
-{
-	return 1;
-}
-
-#include <errno.h>
-#undef errno
-extern int errno;
-int kill(int pid, int sig)
-{
-	errno = EINVAL;
-	return -1;
-}
-
-#include <errno.h>
-#undef errno
-extern int errno;
-int link(char *old, char *new)
-{
-	errno = EMLINK;
-	return -1;
-}
-
-#include <errno.h>
-#undef errno
-extern int errno;
-int unlink(char *name)
-{
-	errno = ENOENT;
-	return -1;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		_putchar(GetPort(0), *(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		_putchar(GetPort(0), c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
-// ---------------------------------------------------------------------------------
-// PrintBuffer8()
-// Prints byte buffer as hex and ascii interpretation
-// ---------------------------------------------------------------------------------
-// _Parameters :
-// pBuf:       : IN: Buffer to display
-// nbpr        : Number of bytes per row to display
-// len         : Length of input buffer
-// _Return:      none
-//
-// ---------------------------------------------------------------------------
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len)
-{
-	memdump(pBuf, 1, nbpr, len);
-}
-
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len)
-{
-    int i, j, cnt_hex, cnt_asc, base;
-    unsigned char c;
-
-    i = j = 0;
-    cnt_hex = len;
-    cnt_asc = len;
-    base = 0;
-	if (!print_offset_only)
-		base = (int)pBuf;
-
-    do
-    {
-        print_word(base + i);
-        sputs(": ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_hex)
-            {
-    		    print_byte(pBuf[i+j]);
-		        sputs(" ");
-                cnt_hex--;
-            }
-            else
-            {
-                sputs("   ");
-                break;
-            }
-
-        }
-
-        sputs("   ");
-        for (j=0; j < num_bytes_per_row; j++)
-        {
-            if (cnt_asc)
-            {
-                c = pBuf[i+j];
-                if((c < 0x20) || (c > 0x7F))
-                    c = '.';
-
-                _putchar(GetPort(0), c);
-                cnt_asc--;
-            }
-            else
-            {
-                sputs(" ");
-                break;
-            }
-        }
-        sputs("\n");
-        i += num_bytes_per_row;
-
-    } while (cnt_hex);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.h b/lib/CPUs/MIPS/bsp/examples/libsys.h
deleted file mode 100644
index d14d2d9..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys.h
+++ /dev/null
@@ -1,187 +0,0 @@
-#ifndef LIBSYS_H
-#define LIBSYS_H
-
-// ---------------------------------------------------------
-// Types
-// ---------------------------------------------------------
-#define INT8							signed char
-#define INT16							signed short
-#define INT32							signed int
-#define INT64							signed long long
-#define UINT8							unsigned char
-#define UINT16							unsigned short
-#define UINT32							unsigned int
-#define UINT64							unsigned long long
-#define INT								INT32
-#define UINT							UINT32
-#define FLOAT32							float
-#define FLOAT64							double
-
-#define	NO_ERROR						LSYS_SUCCESS
-#define	ERROR							LSYS_ERR_BASE
-#define	LSYS_SUCCESS					0
-#define	LSYS_ERR_BASE					0x80000000
-
-#define	IS_ERROR(e)						((e & LSYS_ERR_BASE) == LSYS_ERR_BASE)
-
-// GPIO
-#define	SYS_GPIO0						0xA0000000
-#define	SYS_GPIO1						0xA0000004
-#define	SYS_LED_PORT					SYS_GPIO0
-#define	SYS_USB_CTRL					SYS_GPIO1
-#define	SYS_TIMER_USEC					0xA0000008
-#define	SYS_TIMER_SEC					0xA000000C
-
-// TIMERs
-#define	SYS_ITIM_CTRL					0xA0000018
-#define	SYS_ITIM_STAT					0xA000001C
-#define	SYS_ITIM0_CNT					0xA0000020
-#define	SYS_ITIM1_CNT					0xA0000024
-#define	SYS_ITIM2_CNT					0xA0000028
-#define	SYS_ITIM3_CNT					0xA000002C
-#define	SYS_ITIM0_CMP					0xA0000030
-#define	SYS_ITIM1_CMP					0xA0000034
-#define	SYS_ITIM2_CMP					0xA0000038
-#define	SYS_ITIM3_CMP					0xA000003C
-
-// UARTs
-#define SYS_UART_BIT_TX_HALFFULL		0x00000001
-#define SYS_UART_BIT_TX_FULL			0x00000002
-#define SYS_UART_BIT_RX_HALFFULL		0x00000004
-#define SYS_UART_BIT_RX_FULL			0x00000008
-#define SYS_UART_BIT_RX_AVAIL			0x00000010
-#define SYS_UART_BIT_TX_INTEN			0x00000020
-#define SYS_UART_BIT_RX_INTEN			0x00000040
-#define SYS_UART_BIT_TX_IRQ				0x00000100
-#define SYS_UART_BIT_RX_IRQ				0x00000200
-#define	SYS_UART_DATA					SYS_UART0_DATA
-#define	SYS_UART_STAT					SYS_UART0_STAT
-#define	SYS_UART_BAUD					SYS_UART0_BAUD
-#define	SYS_UART0_DATA					0xA0010000
-#define	SYS_UART0_STAT					0xA0010004
-#define	SYS_UART0_BAUD					0xA0010008
-#define	SYS_UART1_DATA					0xA0010100
-#define	SYS_UART1_STAT					0xA0010104
-#define	SYS_UART1_BAUD					0xA0010108
-
-// PS2s
-#define SYS_PS2_BIT_TX_EMPTY			0x00000001
-#define SYS_PS2_BIT_RX_AVAIL			0x00000004
-#define SYS_PS2_BIT_PIN_CLOCK			0x00000008
-#define SYS_PS2_BIT_PIN_DATA			0x00000010
-#define SYS_PS2_BIT_TX_INTEN			0x00000020
-#define SYS_PS2_BIT_RX_INTEN			0x00000040
-#define SYS_PS2_BIT_TX_IRQ				0x00000100
-#define SYS_PS2_BIT_RX_IRQ				0x00000200
-#define SYS_PS2_BIT_RX_ERR_PAR			0x00000800
-#define SYS_PS2_BIT_RX_ERR_FLAG			0x00008000
-#define	SYS_PS2_0_DATA					0xA0010200
-#define	SYS_PS2_0_STAT					0xA0010204
-#define	SYS_PS2_1_DATA					0xA0010300
-#define	SYS_PS2_1_STAT					0xA0010304
-
-// USB
-#define	SYS_USB_DATA					0xA0020000
-#define	SYS_USB_MBX						0xA0020004
-#define	SYS_USB_ADDR					0xA0020008
-#define	SYS_USB_STATUS					0xA002000C
-
-// VGA
-#define	SYS_VGA_CTRL					0xA0030000	// R/W
-#define	SYS_VGA_BIT_CGRDY				0x00000001	// RO
-#define	SYS_VGA_BIT_MSTEN				0x00000002	// R/W
-#define	SYS_VGA_BIT_BUFCHG_INTEN		0x00000004	// RO
-#define	SYS_VGA_BIT_BUFCHG_FLAG			0x00000008	// RO
-#define	SYS_VGA_BIT_CLRSCR				0x00000010	// WO
-#define	SYS_VGA_BIT_CLRLINE				0x00000020	// WO
-#define	SYS_VGA_BIT_BLIT_REQ			0x00000100	// R/W
-#define	SYS_VGA_BIT_BLIT_BSY			0x00000100	// R/W
-#define	SYS_VGA_BIT_BLIT_FIN			0x00000200	// R/W
-#define	SYS_VGA_BIT_BLIT_ACK			0x00000200	// R/W
-#define	SYS_VGA_BIT_BLIT_FIN_INTEN		0x00000400	// R/W
-#define	SYS_VGA_ASCII					0xA0030004	// R/W
-#define	SYS_VGA_POSX					0xA0030008	// R/W
-#define	SYS_VGA_POSY					0xA003000C	// R/W
-#define	SYS_VGA_CGCOL					0xA0030010	// R/W
-#define	SYS_VGA_RES						0xA0030014	// RO
-#define	SYS_VGA_FB_FRONT				0xA0030018	// R/W
-#define	SYS_VGA_FB_BACK					0xA003001C	// R/W
-#define	SYS_VGA_BLIT_SRC0				SYS_VGA_BLIT_SRC0_FIRST	// R/W
-#define	SYS_VGA_BLIT_SRC0_FIRST			0xA0030020	// R/W
-#define	SYS_VGA_BLIT_SRC0_LAST			0xA0030024	// R/W
-#define	SYS_VGA_BLIT_SRC0_DIMX			0xA0030028	// R/W
-#define	SYS_VGA_BLIT_DST				SYS_VGA_BLIT_DST_FIRST	// R/W
-#define	SYS_VGA_BLIT_DST_FIRST			0xA0030050	// R/W
-#define	SYS_VGA_BLIT_DST_LAST			0xA0030054	// R/W
-#define	SYS_VGA_BLIT_DST_DIMX			0xA0030058	// R/W
-#define	SYS_VGA_BLIT_NX					0xA0030060	// R/W
-#define	SYS_VGA_BLIT_NY					0xA0030064	// R/W
-
-// AC'97
-#define	SYS_AC97_STAT					0xA0040000
-#define	SYS_AC97_CTRL					0xA0040000
-#define	SYS_AC97_ACSTAT					0xA0040400
-#define	SYS_AC97_ACCTRL					0xA0040600
-#define	SYS_AC97_PCM					0xA0040800
-#define	SYS_AC97_WAVIN					SYS_AC97_PCM
-#define	SYS_AC97_WAVOUT					SYS_AC97_PCM
-
-// Flash
-#define	SYS_FLASH_IO					0xA4000000
-#define	SYS_FLASH_MEM					0x00000000
-
-// Sync. SRAM
-#define	SYS_SSRAM_IO					0xA8000000
-
-UINT32 CP0_SR_read(void);
-void CP0_SR_write(UINT32 val);
-UINT32 CP0_CR_read(void);
-void CP0_CR_write(UINT32 val);
-UINT32 CP0_PRID_read(void);
-UINT32 CP0_TR_read(void);
-void CP0_TR_write(UINT32 val);
-void CP0_TR_write_ptr(UINT32* pPtr);
-void CP0_TR_read_ptr(UINT32* pPtr);
-void ICACHE_invalidate_all(void);
-void ICACHE_invalidate_at(UINT32* pPtr);
-void DCACHE_invalidate_all(void);
-void DCACHE_invalidate_at(UINT32* pPtr);
-
-#define CALC_BAUD(b) \
-	((UINT32)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1);
-
-#define	UART0_setbaud(b) \
-	*((UINT32*)SYS_UART0_BAUD) = CALC_BAUD(b);
-
-#define	UART1_setbaud(b) \
-	*((UINT32*)SYS_UART1_BAUD) = CALC_BAUD(b);
-
-#define	UART2_setbaud(b) \
-	*((UINT32*)SYS_UART2_BAUD) = CALC_BAUD(b);
-
-char readchar(UINT32 port);
-void writechar(UINT32 port, char c);
-int write(int file, char *ptr, int len);
-int sputs(char *pStr);
-void print_byte(char byte);
-void print_word(int word);
-void _exit (int exitcode);
-void sleep(unsigned ms);
-
-char _getchar(void);
-
-void PrintBuffer8(UINT8 *pBuf, int nbpr, int len);
-void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len);
-
-void Screen_clr(void);
-void Screen_line_clr(void);
-void Screen_csr_set_x(UINT32 coord);
-void Screen_csr_set_y(UINT32 coord);
-UINT32 Screen_get_resx(void);
-UINT32 Screen_get_resy(void);
-UINT32 Screen_get_fps(void);
-
-
-
-#endif // LIBSYS_H
-
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history b/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history
deleted file mode 100644
index f347082..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys/.directory_history
+++ /dev/null
@@ -1,70 +0,0 @@
-VHDL/lib/CPUs/MIPS/bsp/examples/dbg.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/dbg.c
-VHDL/lib/CPUs/MIPS/bsp/examples/irq.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.c
-VHDL/lib/CPUs/MIPS/bsp/examples/irq.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.h
-VHDL/lib/CPUs/MIPS/bsp/examples/kernel.S
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/kernel.S
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/dbg.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/irq.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/kernel.S
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/libsys.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_xcpt.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/regdef.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/startup.S
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.c
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt_asm.h
-
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.c
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_gfx.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_gfx.h
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c
-VHDL/lib/CPUs/MIPS/bsp/examples/mips_ps2.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h
-VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.c
-VHDL/lib/CPUs/MIPS/bsp/examples/mipsdis.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/mips_dis.h
-VHDL/lib/CPUs/MIPS/bsp/examples/regdef.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/regdef.h
-VHDL/lib/CPUs/MIPS/bsp/examples/startup.S
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/startup.S
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.c
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.c
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt.h
-VHDL/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h
-VHDL/lib/CPUs/MIPS/bsp/examples/libsys/xcpt_asm.h
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/Makefile b/lib/CPUs/MIPS/bsp/examples/libsys/Makefile
deleted file mode 100644
index 376b961..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-ENDIAN_FLAGS=-EL
-CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M
-
-AS=mipsel-elf-as
-AR=mipsel-elf-ar
-CC=mipsel-elf-gcc
-LD=mipsel-elf-ld
-OBJDUMP=mipsel-elf-objdump
-OBJCOPY=mipsel-elf-objcopy
-FLASHGEN=flashgen
-
-SRCS=libsys.c xcpt.c syscalls.c irq.c dbg.c mips_dis.c mips_gfx.c mips_ps2.c
-OBJS=libsys.o xcpt.o syscalls.o irq.o dbg.o mips_dis.o mips_gfx.o mips_ps2.o
-
-all: libsys.a
-	$(MAKE) -C eb
-	
-%.o : %.c %.h
-	$(CC) $(CFLAGS) -G 0 -c $(SRCS)
-
-libsys.a: $(OBJS)
-	$(AR) -r libsys.a $(OBJS)
-	$(CC) $(CFLAGS) -G 0 -c startup.S
-	$(CC) $(CFLAGS) -G 0 -c kernel.S
-	
-clean:
-	rm -rf *.a *.o *.map *.dis *.elf > /dev/null
-	$(MAKE) -C eb clean
-	
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c b/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c
deleted file mode 100644
index 960c240..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.c
+++ /dev/null
@@ -1,268 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "libsys.h"
-#include "mips_ps2.h"
-
-ps2_if_t ps2_if[2] =
-{
-	{ps2_type_unknown, (UINT32*)SYS_PS2_0_STAT, (UINT32*)SYS_PS2_0_DATA},
-	{ps2_type_unknown, (UINT32*)SYS_PS2_1_STAT, (UINT32*)SYS_PS2_1_DATA}
-};
-
-UINT32 PS2_get_num_if(void)
-{
-	return (sizeof(ps2_if)/sizeof(ps2_if_t));
-}
-
-ps2_if_t *PS2_get_if(UINT32 port)
-{
-	if (port < PS2_get_num_if())
-		return &ps2_if[port];
-
-	return NULL;
-}
-
-void PS2_byte_write(UINT32 port, UINT8 byte)
-{
-	ps2_if_t *pIF;
-
-	pIF = &ps2_if[port];
-
-	while(!(*pIF->pCTRL & SYS_PS2_BIT_TX_EMPTY));
-
-	*pIF->pDATA = (UINT32)byte;
-}
-
-UINT32 PS2_byte_read(UINT32 port, UINT32 timeout_ms)
-{
-	ps2_if_t *pIF;
-
-	pIF = &ps2_if[port];
-
-	while(!(*pIF->pCTRL & SYS_PS2_BIT_RX_AVAIL))
-	{
-		timeout_ms--;
-		if (!timeout_ms)
-			return PS2_ERR_TIMEOUT;
-
-		sleep(1);
-	}
-	return (UINT32)*pIF->pDATA;
-}
-
-UINT32 PS2_cmd(UINT32 port, UINT8 cmd, UINT32 ack_timeout_ms)
-{
-	UINT32 result;
-
-	PS2_byte_write(port, cmd);
-	result = PS2_byte_read(port, ack_timeout_ms);
-	if (0xFA != result)
-	{
-		printf ("PS2_cmd(%d): no ACK received. Result = %08X\n", port, result);
-		return PS2_ERR_PS2_PREFIX | result;
-	}
-	return 0;
-}
-
-void PS2_flush(UINT32 port)
-{
-	while (!IS_ERROR(PS2_byte_read(port, 10)));
-}
-
-UINT32 PS2_init(UINT32 port)
-{
-	int i;
-	ps2_if_t *pIF;
-	UINT8 id[2];
-
-	pIF = &ps2_if[port];
-	pIF->type = ps2_type_unknown;
-
-	UINT32 result;
-
-	// Disable RX-interrupt
-	*pIF->pCTRL &= ~SYS_PS2_BIT_RX_INTEN;
-
-	printf ("PS2_init(%d) - Initialize... ", port);
-
-	// Flush buffer
-	PS2_flush(port);
-
-	// send RESET
-	result = PS2_cmd(port, 0xFF, 1000);
-	if (IS_ERROR(result))
-	{
-		printf ("Reset error %08X\n", result);
-		return result;
-	}
-
-	// Read BAT
-	result = PS2_byte_read(port, 1000);
-	if (0xAA != result)
-	{
-		printf ("BAT error %08X\n", result);
-		return result;
-	}
-
-	printf ("Success\n");
-
-	while(1)
-	{
-		// Read ID
-		result = PS2_byte_read(port, 10);
-		if (IS_ERROR(result))
-		{
-			// No ID => keyboard
-			printf ("PS2_init(%d) - Keyboard detected\n", port);
-
-			// send Get Device-ID
-			result = PS2_cmd(port, 0xF2, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("Get Device-ID error %08X\n", result);
-				break;
-			}
-			id[0] = PS2_byte_read(port, 1000);
-			id[1] = PS2_byte_read(port, 1000);
-			printf ("PS2_init(%d) - Device-ID: %02X%02X\n", port, id[0], id[1]);
-
-			// Get Scan code set (phase 1)
-			result = PS2_cmd(port, 0xF0, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("1. Get Scan code error %08X\n", result);
-				break;
-			}
-			// Get Scan code set (phase 2)
-			result = PS2_cmd(port, 0x00, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("2. Get Scan code error %08X\n", result);
-				break;
-			}
-			result = PS2_byte_read(port, 1000);
-			printf ("PS2_init(%d) - Current scan code set = %d\n", port, result);
-
-			// if Scan code SET != 2
-			if (result != 2)
-			{
-				printf ("PS2_init(%d) - Set scan code set = 2\n", port);
-				// Set Scan code set (phase 1)
-				result = PS2_cmd(port, 0xF0, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("1. Set Scan code error %08X\n", result);
-					break;
-				}
-				// Set Scan code set (phase 2)
-				result = PS2_cmd(port, 0x02, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("2. Set Scan code error %08X\n", result);
-					break;
-				}
-			}
-
-			// Test LEDs
-			for (i=0; i < 4; i++)
-			{
-				result = PS2_cmd(port, 0xED, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("1. LED error %08X\n", result);
-					break;
-				}
-				result = PS2_cmd(port, 0x02, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("2. LED error %08X\n", result);
-					break;
-				}
-				sleep(100);
-				result = PS2_cmd(port, 0xED, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("1. LED error %08X\n", result);
-					break;
-				}
-				result = PS2_cmd(port, 0x04, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("2. LED error %08X\n", result);
-					break;
-				}
-				sleep(100);
-				result = PS2_cmd(port, 0xED, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("1. LED error %08X\n", result);
-					break;
-				}
-				result = PS2_cmd(port, 0x01, 1000);
-				if (IS_ERROR(result))
-				{
-					printf ("2. LED error %08X\n", result);
-					break;
-				}
-				sleep(100);
-			}
-			result = PS2_cmd(port, 0xED, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("1. LED error %08X\n", result);
-				break;
-			}
-			result = PS2_cmd(port, 0x00, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("2. LED error %08X\n", result);
-				break;
-			}
-
-			pIF->type = ps2_type_keyb;
-			result = pIF->type;
-			break;
-		}
-
-		// We got a byte => maybe mouse
-		if (result == 0)
-		{
-			// We got zero => yes, it's a mouse
-			printf ("PS2_init(%d) - Mouse device detected\n", port);
-
-			// send Get Device-ID
-			result = PS2_cmd(port, 0xF2, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("Get Device-ID error %08X\n", result);
-				break;
-			}
-			id[0] = PS2_byte_read(port, 1000);
-			printf ("PS2_init(%d) - Device-ID: %02X\n", port, id[0]);
-			printf ("PS2_init(%d) - Enable stream mode...", port);
-			result = PS2_cmd(port, 0xF4, 1000);
-			if (IS_ERROR(result))
-			{
-				printf ("error %08X\n", result);
-				break;
-			}
-			printf ("Success\n");
-			pIF->type = ps2_type_mouse;
-			result = pIF->type;
-			break;
-		}
-	}
-
-	// Flush buffer
-	PS2_flush(port);
-
-	if (IS_ERROR(result))
-		return result;
-
-	// Enable RX-interrupt
-	*pIF->pCTRL |= SYS_PS2_BIT_RX_INTEN;
-
-	return result;
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h b/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h
deleted file mode 100644
index 9bfee72..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys/mips_ps2.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef PS2_H
-#define PS2_H
-
-#include "libsys.h"
-
-// --------------------------------------------------
-// Types
-// --------------------------------------------------
-enum
-{
-	ps2_type_unknown = 0,
-	ps2_type_keyb,
-	ps2_type_mouse
-};
-
-typedef struct _sps2_if_t
-{
-	UINT32 type;
-	volatile UINT32 *pCTRL;
-	volatile UINT32 *pDATA;
-} ps2_if_t;
-
-// --------------------------------------------------
-// Constants
-// --------------------------------------------------
-#define	PS2_MODULE_PREFIX	0x1000000
-#define	PS2_SUCCESS			LSYS_SUCCESS
-#define	PS2_ERROR			(LSYS_ERR_BASE | PS2_MODULE_PREFIX)
-#define	PS2_ERR_TIMEOUT		(PS2_ERROR | 0x0000001)
-#define	PS2_ERR_PS2_PREFIX	(PS2_ERROR | 0x0010000)
-
-// --------------------------------------------------
-// Functions
-// --------------------------------------------------
-UINT32 PS2_get_num_if(void);
-ps2_if_t *PS2_get_if(UINT32 port);
-UINT32 PS2_init(UINT32 port);
-void PS2_byte_write(UINT32 port, UINT8 byte);
-UINT32 PS2_byte_read(UINT32 port, UINT32 timeout_ms);
-UINT32 PS2_cmd(UINT32 port, UINT8 cmd, UINT32 ack_timeout_ms);
-void PS2_flush(UINT32 port);
-
-#endif // PS2_H
diff --git a/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c b/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c
deleted file mode 100644
index 040372b..0000000
--- a/lib/CPUs/MIPS/bsp/examples/libsys/syscalls.c
+++ /dev/null
@@ -1,86 +0,0 @@
-#include <stdio.h>
-#include "libsys.h"
-#include "xcpt.h"
-
-/* 10 digits + 1 sign + 1 trailing nul */
-static char itoa_buf[12];
-
-char *itoa(int i)
-{
-	char *pos = itoa_buf + sizeof(itoa_buf) - 1;
-	unsigned int u;
-	int negative = 0;
-
-	if (i < 0)
-	{
-		negative = 1;
-		u = ((unsigned int)(-(1+i))) + 1;
-	}
-	else
-	{
-		u = i;
-	}
-
-	*pos = 0;
-
-	do
-	{
-		*--pos = '0' + (u % 10);
-		u /= 10;
-	} while (u);
-
-	if (negative)
-	{
-		*--pos = '-';
-	}
-
-	return pos;
-}
-
-int syscalls_handler(struct xcptcontext * xcp)
-{
-	int syscall_code;
-	char *pStr, buf[33];
-
-	syscall_code = xcp->regs[2];
-
-	switch(syscall_code)
-	{
-		case 1:		// print integer
-		sputs(itoa(xcp->regs[4]));
-		break;
-
-		case 4:		// print string
-		pStr = (char*)xcp->regs[4];
-		sputs(pStr);
-		break;
-
-		case 5:		// read integer
-		pStr = fgets(buf, sizeof(buf), stdin);
-		xcp->regs[2] = atoi(pStr);
-		break;
-
-		case 8:		// read string
-		pStr = (char*)xcp->regs[4];
-		fgets(pStr, xcp->regs[5], stdin);
-		break;
-
-		case 10:		// exit
-		_exit(0);
-		break;
-
-		default:
-		sputs("\nUnknown syscall (");print_word(syscall_code);sputs(") at ");print_word(xcp->epc);sputs("\n");
-		break;
-	}
-
-	xcp->epc += 4;	// set return address to instruction after syscall
-
-	return 0;
-}
-
-void syscalls_init(void)
-{
-	xcpt_register(Syscall, syscalls_handler);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/life.c b/lib/CPUs/MIPS/bsp/examples/life.c
deleted file mode 100644
index bba5a0e..0000000
--- a/lib/CPUs/MIPS/bsp/examples/life.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* life.c - demonstrator for later Mips+LCD game of life
- *
- * 23.03.06 - MACRO-based version
- * 22.02.06 - new file
- */
-
-//#include "ks0108.h"
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "libsys.h"
-
-
-#define NX  200 // 70 // 128  // 48 // 128
-#define NY  150 // 31 // 64   // 27 // 64
-
-#define	SCREEN_X	800
-#define	SCREEN_Y	600
-
-#define	SCALE_X		(4)
-#define	SCALE_Y		(4)
-#define	OFFSET_X	((SCREEN_X-(SCALE_X*NX))/2)
-#define	OFFSET_Y	((SCREEN_Y-(SCALE_Y*NY))/2)
-
-// OCCUPIED must be uneven, EMPTY even.
-#define OCCUPIED 0x77771111
-#define EMPTY    0xeeee0000
-
-#define MATRIX( row, col )  (*(matrix + (NX*col) + row ))
-#define FUTURE( row, col )  (*(future + (NX*col) + row ))
-
-UINT32 *g_gx_buff;
-
-int clock_lfsr32()
-{
-  return rand();
-}
-
-
-/* return a pseudo-random integer in the range 0..1023 */
-int random1023() {
-  int tmp;
-
-  tmp = clock_lfsr32();
-  return tmp & 0x000003ff;
-}
-
-typedef struct _scolor_t
-{
-	UINT8 r, g, b, a;
-} __attribute__ ((__packed__)) color_t;
-
-
-void DrawPixel(UINT32 x, UINT32 y, color_t *pColor)
-{
-	int i, j;
-	for (i=0; i < SCALE_Y; i++)
-		for (j=0; j < SCALE_X; j++)
-			g_gx_buff[(OFFSET_X+SCALE_X*x+j) + SCREEN_X*(OFFSET_Y+SCALE_Y*y+i)] = *((UINT32*)pColor);
-}
-
-
-/* MSB/LSB in y-Richtung vertauscht */
-void displayBoard1( int* matrix )
-{
-	int x, y;
-	int mask, accu;
-	UINT32 color;
-
-	for( x=0; x < NX; x++ )
-	{
-		mask = 0x80;
-		accu = 0x00;
-		for( y=0; y < NY; y++ )
-		{
-			color = (UINT32)-(MATRIX(x,y) & 0x1);
-			DrawPixel(x, y, (color_t*)&color);
-//			if (MATRIX( x, y ) != OCCUPIED)
-//			{
-//				accu |= mask;
-//			}
-//			mask = mask >> 1;
-
-//			color = 0;
-//			DrawPixel(x, (y>>3), (color_t*)&color);
-//			if (mask == 0)
-//			{
-//				color = accu;
-//				DrawPixel(x, (y>>3), (color_t*)&color);
-//				mask = 0x80;
-//				accu = 0x00;
-//			}
-		}
-//		color = accu;
-//		DrawPixel(x, (y>>3), (color_t*)&color);
-
-	}
-//	*(matrix-15) = 0xdead0000;
-//	*(matrix-16) = *(matrix-16) + 1;
-}
-
-void initializeBoard( int* matrix ) {
-  int x, y;
-  for( x=0; x < NX; x++ ) {
-    for( y=0; y < NY; y++ ) {
-        int d = random1023();
-        if (d > 920)  MATRIX( x, y ) = OCCUPIED;
-        else          MATRIX( x, y ) = EMPTY;
-    }
-  }
-}
-
-
-int countNeighbors( int* matrix, int i, int j ) {
-    int im = i-1;
-    int ip = i+1;
-
-    int jm = j-1;
-    int jp = j+1;
-
-    int n = 0;
-    // wrap-around
-    if (ip >= NX) ip = 0;
-    if (jp >= NY) jp = 0;
-
-    if (im < 0) im = NX-1;
-    if (jm < 0) jm = NY-1;
-
-    // check eight neighbors
-    n += MATRIX(im, jm ) & 0x1;  // nw
-    n += MATRIX(im, j  ) & 0x1;  // west
-    n += MATRIX(im, jp ) & 0x1;  // sw
-
-    n += MATRIX(i,  jm ) & 0x1;  // north
- // n += MATRIX(i,   j ) & 0x1;  // center
-    n += MATRIX(i,  jp ) & 0x1;  // south
-
-    n += MATRIX(ip, jm ) & 0x1;  // ne
-    n += MATRIX(ip, j  ) & 0x1;  // east
-    n += MATRIX(ip, jp ) & 0x1;  // se
-
-    return n;
-}
-
-
-/**
- * the actual game of life algorithm: cell is born when three neighbors,
- * survives when exactly two live neighbors, dies otherwise.
- */
-void nextGeneration( int* matrix, int* future ) {
-  int i, j;
-  int lifes = 0;
-
-  for( i=0; i < NX; i++ ) {
-    for( j=0; j < NY; j++ ) {
-      // count neighbors
-      int n = countNeighbors( matrix, i, j );
-
-      //if ((n != 0) && (random1023() > 990)) { // some slight random offset
-      // if (random1023() > 500) FUTURE(i,j) = OCCUPIED;
-      //  else                    FUTURE(i,j) = EMPTY;
-      //}
-      // else if (n == 3)                                FUTURE(i,j) = OCCUPIED;
-
-      if (n == 3)                                     FUTURE(i,j) = OCCUPIED;
-      else if ((n == 2) && (MATRIX(i,j) == OCCUPIED)) FUTURE(i,j) = OCCUPIED;
-      else                                            FUTURE(i,j) = EMPTY;
-
-      if (FUTURE(i,j) == OCCUPIED) lifes++;
-    }
-  }
-  // generation ++;
-
-  // avoid extinction :-)
-  if (lifes < 10) {
-    // printf( "CREATING A NEW POPULATION\n\n\n" );
-    initializeBoard( matrix );
-  }
-  else { // swap buffers: C PROHIBITS ASSIGNING TO ARRAY TYPES
-    for( i=0; i < NX; i++ ) {
-      for( j=0; j < NY; j++ ) {
-        MATRIX(i,j) = FUTURE(i,j);
-      }
-    }
-  }
-}
-
-void gx_init(void)
-{
-	volatile UINT32 *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	volatile UINT32 *pVGA_front = (UINT32*)SYS_VGA_FB_FRONT;
-	volatile UINT32 *pVGA_back = (UINT32*)SYS_VGA_FB_BACK;
-
-	sleep(500);
-
-	g_gx_buff = (UINT32*)malloc(SCREEN_X*SCREEN_Y*sizeof(UINT32));
-	memset(g_gx_buff, 0, SCREEN_X*SCREEN_Y*sizeof(UINT32));
-	printf("g_gx_buff  : %8.8X\n", (UINT32)g_gx_buff);
-
-	*pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-	*pVGA_front = (UINT32)g_gx_buff;
-	*pVGA_back = (UINT32)g_gx_buff;
-
-}
-
-int main( int argc, char* argv[] ) {
-
-	int* ptr, cnt = 0;
-
-	int* matrix;
-	int* future;
-	volatile UINT32 *pBtn = (UINT32*)SYS_GPIO0;
-
-	//  lcdEnableDisplay( 1 );
-	//  lcdSetColor( 1 );
-	//  lcdSetPixel( 0, 0 );
-	//  lcdSetPixel( 3, 5 );
-
-	// if we have stdlib:
-	matrix = (void*) malloc( NX*NY*sizeof(int) );
-	future = (void*) malloc( NX*NY*sizeof(int) );
-
-
-	gx_init();
-
-//  matrix = (void *) 0x00004000;
-//  future = (void *) 0x00014000;
-
-  // init_lfsr32( 0xcafebabe );
-  // init_lfsr32( 0x13 );
-
-	srand(clock());
-	initializeBoard( matrix );
-
-	while( 1 )
-	{
-
-		if (*pBtn)
-		{
-			srand(clock());
-			initializeBoard( matrix );
-			cnt = 0;
-		}
-		sputs("Generation #"); print_word(cnt++); sputs("\n");
-		displayBoard1( matrix );
-		nextGeneration( matrix, future );
-	}
-
-  // return 0
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/link/link.ld b/lib/CPUs/MIPS/bsp/examples/link/link.ld
deleted file mode 100644
index bf3b367..0000000
--- a/lib/CPUs/MIPS/bsp/examples/link/link.ld
+++ /dev/null
@@ -1,225 +0,0 @@
-/* Script for -z combreloc: combine and sort reloc sections */
-OUTPUT_FORMAT("elf32-littlemips", "elf32-bigmips",
-	      "elf32-littlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SEARCH_DIR("./libsys");
-SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb");
-SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb");
-
-stack_ptr = 0x7FFFEFF0;
-baudrate = 0x0D;
-sys_led_port = 0xA0000000;
-sys_uart_data = 0xA0010000;
-sys_uart_stat = 0xA0010004;
-sys_uart_baud = 0xA0010008;
-sys_timer_usec = 0xA000008;
-sys_timer_sec = 0xA000000C;
-
-STARTUP(startup.o)
-INPUT(kernel.o)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  PROVIDE (__executable_start = 0x40000000); . = 0x40000000;
-   .start __executable_start : 
-   {
-      start = ALIGN(2);
-      entry = ALIGN(2);
-      _entry = ALIGN(2);
-      __entry = ALIGN(2);
-     *(.start)
-   }
-   /* Kernel text with low-level exception handler */
-   .exc_vector __executable_start + 0x080 :
-   {
-      _exc_vect_start = .;
-     *(.exc_vect)
-      _exc_vect_end = .;
-   }
-  .init           :
-  {
-    KEEP (*(.init))
-  } =0
-  .plt            : { *(.plt) }
-  .text           :
-  {
-    _ftext = . ;
-    *(.text .stub .text.* .gnu.linkonce.t.*)
-    /* .gnu.warning sections are handled specially by elf32.em.  */
-    *(.gnu.warning)
-    *(.mips16.fn.*) *(.mips16.call.*)
-  } =0
-  .fini           :
-  {
-    KEEP (*(.fini))
-  } =0
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
-  .rodata1        : { *(.rodata1) }
-  .sdata2         :
-  {
-    *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
-  }
-  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
-  .eh_frame_hdr : { *(.eh_frame_hdr) }
-  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
-  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }
-  /* Adjust the address for the data segment.  We want to adjust up to
-     the same address within the page on the next page up.  */
-  . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
-  /* Exception handling  */
-  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
-  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
-  /* Thread Local Storage sections  */
-  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
-  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  }
-  .init_array     :
-  {
-     PROVIDE_HIDDEN (__init_array_start = .);
-     KEEP (*(SORT(.init_array.*)))
-     KEEP (*(.init_array))
-     PROVIDE_HIDDEN (__init_array_end = .);
-  }
-  .fini_array     :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(.fini_array))
-    KEEP (*(SORT(.fini_array.*)))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  }
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-       the constructors, so we make sure it is
-       first.  Because this is a wildcard, it
-       doesn't matter if the user does not
-       actually link against crtbegin.o; the
-       linker won't look for a file to match a
-       wildcard.  The wildcard also means that it
-       doesn't matter which directory crtbegin.o
-       is in.  */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-       the crtend.o file until after the sorted ctors.
-       The .ctor section from the crtend file contains the
-       end of ctors marker and it must be last */
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  }
-  .dtors          :
-  {
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  }
-  .jcr            : { KEEP (*(.jcr)) }
-  .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) }
-  . = DATA_SEGMENT_RELRO_END (0, .);
-  .data           :
-  {
-    _fdata = . ;
-    *(.data .data.* .gnu.linkonce.d.*)
-    SORT(CONSTRUCTORS)
-  }
-  .data1          : { *(.data1) }
-  .got.plt        : { *(.got.plt) }
-  . = .;
-  _gp = ALIGN(16) + 0x7ff0;
-  .got            : { *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata          :
-  {
-    *(.sdata .sdata.* .gnu.linkonce.s.*)
-  }
-  .lit8           : { *(.lit8) }
-  .lit4           : { *(.lit4) }
-  _edata = .; PROVIDE (edata = .);
-  __bss_start = .;
-  _fbss = .;
-  .sbss           :
-  {
-    *(.dynsbss)
-    *(.sbss .sbss.* .gnu.linkonce.sb.*)
-    *(.scommon)
-  }
-  .bss            :
-  {
-   *(.dynbss)
-   *(.bss .bss.* .gnu.linkonce.b.*)
-   *(COMMON)
-   /* Align here to ensure that the .bss section occupies space up to
-      _end.  Align after .bss to ensure correct alignment even if the
-      .bss section disappears because there are no input sections.
-      FIXME: Why do we need it? When there is no .bss section, we don't
-      pad the .data section.  */
-   . = ALIGN(. != 0 ? 32 / 8 : 1);
-  }
-  . = ALIGN(32 / 8);
-  . = ALIGN(32 / 8);
-  _end = .; PROVIDE (end = .);
-  . = DATA_SEGMENT_END (.);
-  /* Stabs debugging sections.  */
-  .stab          0 : { *(.stab) }
-  .stabstr       0 : { *(.stabstr) }
-  .stab.excl     0 : { *(.stab.excl) }
-  .stab.exclstr  0 : { *(.stab.exclstr) }
-  .stab.index    0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  .comment       0 : { *(.comment) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* DWARF 3 */
-  .debug_pubtypes 0 : { *(.debug_pubtypes) }
-  .debug_ranges   0 : { *(.debug_ranges) }
-  .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
-  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
-  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
-  .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) }
-  .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) }
-  .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) }
-  .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) }
-  .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) }
-  .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) }
-  .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) }
-  .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) }
-  /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) }
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/lua_init.c b/lib/CPUs/MIPS/bsp/examples/lua_init.c
deleted file mode 100644
index 0edd3d5..0000000
--- a/lib/CPUs/MIPS/bsp/examples/lua_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "all.c"
diff --git a/lib/CPUs/MIPS/bsp/examples/lwl.c b/lib/CPUs/MIPS/bsp/examples/lwl.c
deleted file mode 100644
index 3905cf0..0000000
--- a/lib/CPUs/MIPS/bsp/examples/lwl.c
+++ /dev/null
@@ -1,46 +0,0 @@
-#include "libsys.h"
-
-int non_aligned_load(UINT32* pMem)
-{
-	UINT32 result;
-	__asm__
-	(
-		"li     $t0, 0x01234567\n"
-		"li     $t1, 0x89ABCDEF\n"
-		"sw     $t0, 0(%[pMem])\n"
-		"sw     $t1, 64(%[pMem])\n"
-		"lw     %[val], 0(%[pMem])\n"
-		"lw     %[val], 64(%[pMem])\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"li     %[val], 0x55555555\n"
-		"lw     %[val], 0(%[pMem])\n"
-		"lwl    %[val], 65(%[pMem])\n"
-		: [val] "=r" (result)
-		: [pMem] "r" (pMem)
-	);
-	return result;
-}
-
-int main()
-{
-	int buf[256], res, i;
-
-	res = non_aligned_load(buf);
-
-	return res;
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/mandelbrot.c b/lib/CPUs/MIPS/bsp/examples/mandelbrot.c
deleted file mode 100644
index ce7aa9d..0000000
--- a/lib/CPUs/MIPS/bsp/examples/mandelbrot.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// by Erik Wrenholt
-#include <stdio.h>
-#include <sys/time.h>
-
-#define BAILOUT 16
-#define MAX_ITERATIONS 1000
-
-int mandelbrot(double x, double y)
-{
-	double cr = y - 0.5;
-	double ci = x;
-	double zi = 0.0;
-	double zr = 0.0;
-	int i = 0;
-
-	while(1) {
-		i ++;
-		double temp = zr * zi;
-		double zr2 = zr * zr;
-		double zi2 = zi * zi;
-		zr = zr2 - zi2 + cr;
-		zi = temp + temp + ci;
-		if (zi2 + zr2 > BAILOUT)
-			return i;
-		if (i > MAX_ITERATIONS)
-			return 0;
-	}
-	
-}
-
-int main (int argc, const char * argv[]) {
-	struct timeval aTv;
-	gettimeofday(&aTv, NULL);
-	long init_time = aTv.tv_sec;
-	long init_usec = aTv.tv_usec;
-
-	int x,y;
-	for (y = -39; y < 39; y++) {
-		printf("\n");
-		for (x = -39; x < 39; x++) {
-			int i = mandelbrot(x/40.0, y/40.0);
-			if (i==0)
-				printf("*");
-			else
-				printf(" ");
-		}	
-	}
-	printf ("\n");
-	
-	gettimeofday(&aTv,NULL);
-	double query_time = (aTv.tv_sec - init_time) + (double)(aTv.tv_usec - init_usec)/1000000.0;	
-	printf ("C Elapsed %0.2f\n", query_time);
-    return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/mips_gfx.c b/lib/CPUs/MIPS/bsp/examples/mips_gfx.c
deleted file mode 100644
index ee06438..0000000
--- a/lib/CPUs/MIPS/bsp/examples/mips_gfx.c
+++ /dev/null
@@ -1,566 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "libsys.h"
-#include "mips_gfx.h"
-
-#define USE_HW_BLITTER
-
-// -------------------------------------------------------------
-// Functions
-// -------------------------------------------------------------
-void __gfx_block_set_8(UINT32* pDst, UINT32 value)
-{
-	__asm__ volatile
-	(
-		"sw   %[value], 0(%[pDst])\n"
-		"sw   %[value], 4(%[pDst])\n"
-		"sw   %[value], 8(%[pDst])\n"
-		"sw   %[value], 12(%[pDst])\n"
-		"sw   %[value], 16(%[pDst])\n"
-		"sw   %[value], 20(%[pDst])\n"
-		"sw   %[value], 24(%[pDst])\n"
-		"sw   %[value], 28(%[pDst])\n"
-		:
-		: [pDst] "r" (pDst), [value] "r" (value)
-	);
-}
-
-void __gfx_block_copy_8(UINT32* pDst, UINT32* pSrc)
-{
-	 __asm__ volatile
-	(
-		".set noreorder\n"
-		".set nomacro\n"
-		"lw   $s0, 0(%[pSrc])\n"
-		"lw   $s1, 4(%[pSrc])\n"
-		"sw   $s0, 0(%[pDst])\n"
-		"lw   $s0, 8(%[pSrc])\n"
-		"sw   $s1, 4(%[pDst])\n"
-		"lw   $s1, 12(%[pSrc])\n"
-		"sw   $s0, 8(%[pDst])\n"
-		"lw   $s0, 16(%[pSrc])\n"
-		"sw   $s1, 12(%[pDst])\n"
-		"lw   $s1, 20(%[pSrc])\n"
-		"sw   $s0, 16(%[pDst])\n"
-		"lw   $s0, 24(%[pSrc])\n"
-		"sw   $s1, 20(%[pDst])\n"
-		"lw   $s1, 28(%[pSrc])\n"
-		"sw   $s0, 24(%[pDst])\n"
-		"sw   $s1, 28(%[pDst])\n"
-		".set macro\n"
-		".set reorder\n"
-		:
-		: [pDst] "r" (pDst), [pSrc] "r" (pSrc)
-		: "s0", "s1"
-	);
-}
-
-void __gfx_copy_32(UINT32* pDst, UINT32* pSrc, UINT32 nblocks)
-{
-	while (nblocks)
-	{
-		__gfx_block_copy_8(pDst, pSrc);
-		pDst += 8;
-		pSrc += 8;
-		nblocks--;
-	}
-
-}
-
-void GFX_DirtyRectSetClean(buf_t *pBuf)
-{
-	pBuf->rect.xmin = pBuf->w;
-	pBuf->rect.xmax = 0;
-	pBuf->rect.ymin = pBuf->h;
-	pBuf->rect.ymax = 0;
-	pBuf->is_dirty = 0;
-}
-
-void GFX_DirtyRectInit(buf_t *pBuf, UINT32 w, UINT32 h)
-{
-	pBuf->w = w;
-	pBuf->h = h;
-	pBuf->regs = (vga_hw_t*)SYS_VGA_CTRL;
-	GFX_DirtyRectSetClean(pBuf);
-}
-
-void GFX_DirtyRectUpdate(buf_t *pBuf, UINT32 xmin, UINT32 xmax, UINT32 ymin, UINT32 ymax)
-{
-
-	if (xmin < pBuf->rect.xmin)
-	{
-		pBuf->is_dirty = 1;
-		pBuf->rect.xmin = xmin;
-	}
-
-	if (xmax > pBuf->rect.xmax)
-	{
-		pBuf->is_dirty = 1;
-		pBuf->rect.xmax = xmax;
-	}
-
-	if (ymin < pBuf->rect.ymin)
-	{
-		pBuf->is_dirty = 1;
-		pBuf->rect.ymin = ymin;
-	}
-
-	if (ymax > pBuf->rect.ymax)
-	{
-		pBuf->is_dirty = 1;
-		pBuf->rect.ymax = ymax;
-	}
-
-	if (pBuf->is_dirty && ((pBuf->rect.xmax-pBuf->rect.xmin)%8))
-		pBuf->rect.xmax = pBuf->rect.xmin + ((pBuf->rect.xmax-pBuf->rect.xmin)/8 + 1) * 8; // Make len_x multiple of 8
-
-}
-
-void GFX_DirtyRectCopy(buf_t *pBuf)
-{
-	UINT32 xmin, xmax, ymin, ymax, x, y;
-	UINT32 *pDst, *pDst_end;
-	UINT32 *pSrc, *pSrc_end;
-
-	xmin = pBuf->rect.xmin;
-	xmax = pBuf->rect.xmax;
-
-	ymin = pBuf->rect.ymin;
-	ymax = pBuf->rect.ymax;
-
-	ymin *= pBuf->w;
-	ymax *= pBuf->w;
-
-#ifdef USE_HW_BLITTER
-	pSrc = (UINT32*)&pBuf->pLast->pFB[xmin + ymin];
-	pDst = (UINT32*)&pBuf->pFB[xmin + ymin];
-
-	while (pBuf->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-	pBuf->regs->pVGA_src0 = (UINT32)pSrc;
-	pBuf->regs->pVGA_dst = (UINT32)pDst;
-	pBuf->regs->pVGA_src0_dimx = (UINT32)4*pBuf->w;
-	pBuf->regs->pVGA_dst_dimx = (UINT32)4*pBuf->w;
-	pBuf->regs->pVGA_nx = (UINT32)(pBuf->rect.xmax-pBuf->rect.xmin);
-	pBuf->regs->pVGA_ny = (UINT32)(pBuf->rect.ymax-pBuf->rect.ymin);
-	pBuf->regs->pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-
-#else
-
-	if (!((xmax-xmin)%8))
-	{
-		for (y=ymin; y < ymax; y += pBuf->w)
-		{
-			pSrc = &pBuf->pLast->pFB[xmin + y];
-			pSrc_end = &pBuf->pLast->pFB[xmax + y];
-			pDst = &pBuf->pFB[xmin + y];
-			pDst_end = &pBuf->pFB[xmax + y];
-			while(pDst < pDst_end)
-			{
-				__gfx_block_copy_8(pDst, pSrc);
-				pDst += 8;
-				pSrc += 8;
-			}
-		}
-		return;
-	}
-
-//	fprintf(stderr, "GFX_DirtyRectCopy(): Slow copy!\n");
-	for (y=ymin; y < ymax; y += pBuf->w)
-	{
-		for (x=xmin; x < xmax; x++)
-		{
-			pBuf->pFB[x + y] = pBuf->pLast->pFB[x + y];
-		}
-	}
-#endif
-
-}
-
-void GFX_init(gfx_t *pObj)
-{
-	int i;
-	buf_t *pBuf;
-	UINT32 w, h, fps;
-
-	pObj->regs = (vga_hw_t*)SYS_VGA_CTRL;
-
-	pObj->regs->pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN;
-
-	w = Screen_get_resx();
-	h = Screen_get_resy();
-	fps = Screen_get_fps();
-
-	printf("VGA screen = %d x %d @ %d fps\n", w, h, fps);
-
-	pObj->w = w;
-	pObj->h = h;
-
-	// Init background buffer
-	pObj->pBG = (UINT32*)calloc(w * h, sizeof(buf_t));
-
-	// Init framebuffers
-	pObj->pBuf = (buf_t*)calloc(1, sizeof(buf_t));
-	pBuf = pObj->pBuf;
-	pBuf->pFB = (UINT32*)calloc((w+8) * h, sizeof(UINT32));		// w+8 because of dirty rectangle 8 byte min. x-size
-	for (i=1; i < GFX_NUM_FRAME_BUFFERS; i++)
-	{
-
-		pBuf->pNext = (buf_t*)calloc(1, sizeof(buf_t));
-		pBuf->pNext->pLast = pBuf;
-		pBuf = pBuf->pNext;
-		pBuf->pFB = (UINT32*)calloc((w+8) * h, sizeof(UINT32));	// w+8 because of dirty rectangle 8 byte min. x-size
-	}
-	pObj->pBuf->pLast = pBuf;
-	pBuf->pNext = pObj->pBuf;
-
-	pBuf = pObj->pBuf;
-	for (i=0; i < GFX_NUM_FRAME_BUFFERS; i++)
-	{
-		GFX_DirtyRectInit(pBuf, w, h);
-
-//		fprintf(stderr, "pBuf = %08X, pLast = %08X, pNext = %08X\n", pBuf, pBuf->pLast, pBuf->pNext);
-		pBuf = pBuf->pNext;
-	}
-
-	pObj->regs->pVGA_front = (UINT32)pObj->pBuf->pLast->pFB;
-	pObj->regs->pVGA_back = (UINT32)pObj->pBuf->pLast->pFB;
-	pObj->regs->pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-
-
-}
-
-void GFX_set_background(gfx_t *pObj, UINT32 *pImage, UINT32 image_nx, UINT32 image_ny, UINT32 image_scale_x, UINT32 image_scale_y)
-{
-
-	UINT32 off_x, off_y;
-	UINT32 i, j;
-	UINT32 *pDst, *pSrc;
-	buf_t *pBuf;
-
-	if (!pImage)
-		return;
-
-	off_x = (pObj->w-(image_scale_x*image_nx))/2;
-	off_y = (pObj->h-(image_scale_y*image_ny))/2;
-
-	pDst = ((UINT32*)pObj->pBG) + pObj->w*off_y + off_x;
-	pSrc = pImage;
-
-	for (i=0; i < image_ny*image_nx; i += 8)
-	{
-		__gfx_block_copy_8(pDst, pSrc);
-		pDst += 8;
-		pSrc += 8;
-	}
-
-	pBuf = pObj->pBuf;
-
-	pDst = pBuf->pFB;
-	pSrc = pObj->pBG;
-
-	for (i=0; i < image_ny*image_nx; i += 8)
-	{
-		__gfx_block_copy_8(pDst, pSrc);
-		pDst += 8;
-		pSrc += 8;
-	}
-
-	do
-	{
-		GFX_DirtyRectUpdate(pBuf, 0, pObj->w, 0, pObj->h);
-		pBuf = pBuf->pNext;
-
-	} while(pBuf != pObj->pBuf);
-
-
-}
-
-void GFX_frame(gfx_t *pObj, UINT32 sync_mode)
-{
-
-	// Wait until back buffer becomes front
-	if (sync_mode == GFX_FRAME_SYNC)
-	{
-		while(pObj->regs->pVGA_front == (UINT32)pObj->pBuf->pFB);
-	}
-
-	GFX_copy_front2back(pObj);
-
-	// Invalidate D-Cache after blitting has finished
-	while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-	DCACHE_invalidate_all();
-
-}
-
-void GFX_show(gfx_t *pObj)
-{
-
-	pObj->regs->pVGA_back = (UINT32)pObj->pBuf->pFB;
-	pObj->pBuf = pObj->pBuf->pNext;
-
-}
-
-void GFX_copy_front2back(gfx_t *pObj)
-{
-	buf_t *pBuf;
-
-	pBuf = pObj->pBuf;
-
-	// Lopp over all frame buffers, except front buffer
-	while(pBuf != pObj->pBuf->pLast)
-	{
-		if (pBuf->is_dirty)
-		{
-//			fprintf(stderr, "Dirty rect [%08X]: w=%d, h=%d\n", (int)pBuf, pBuf->rect.xmax - pBuf->rect.xmin, pBuf->rect.ymax - pBuf->rect.ymin);
-			GFX_DirtyRectCopy(pBuf);
-			GFX_DirtyRectSetClean(pBuf);
-		}
-		pBuf = pBuf->pNext;
-	}
-}
-
-void GFX_get_FB_front(gfx_t *pObj, UINT32 **ppFB)
-{
-	*ppFB = pObj->pBuf->pLast->pFB;
-}
-
-void box_create(box_t *pObj, UINT32 w, UINT32 h)
-{
-	pObj->w = w;
-	pObj->h = h;
-}
-
-void GFX_restore(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy)
-{
-	UINT32 xmin, xmax, ymin, ymax, x, y;
-	UINT32 *pDst, *pDst_end;
-	UINT32 *pSrc, *pSrc_end;
-	buf_t *pBuf;
-
-	xmin = posx;
-	xmax = pBox->w + posx;
-	if (xmax > pObj->w)
-		xmax = pObj->w;
-
-	ymin = posy;
-	ymax = pBox->h + posy;
-	if (ymax > pObj->h)
-		ymax = pObj->h;
-
-	pBuf = pObj->pBuf->pNext;
-
-	// Lopp over all frame buffers, except current back buffer
-	while(pBuf != pObj->pBuf)
-	{
-		GFX_DirtyRectUpdate(pBuf, xmin, xmax, ymin, ymax);
-		pBuf = pBuf->pNext;
-
-	}
-	pBuf = pObj->pBuf;
-
-	x = xmax - xmin + 1;
-	if (x%2)
-		x++;
-	y = ymax - ymin + 1;
-	if (y%2)
-		y++;
-
-	ymin *= pObj->w;
-	ymax *= pObj->w;
-
-#ifdef USE_HW_BLITTER
-	pSrc = (UINT32*)&pObj->pBG[xmin + ymin];
-	pDst = (UINT32*)&pBuf->pFB[xmin + ymin];
-
-	while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-	pObj->regs->pVGA_src0 = (UINT32)pSrc;
-	pObj->regs->pVGA_dst = (UINT32)pDst;
-	pObj->regs->pVGA_src0_dimx = (UINT32)4*pObj->w;
-	pObj->regs->pVGA_dst_dimx = (UINT32)4*pObj->w;
-	pObj->regs->pVGA_nx = (UINT32)x - 1;
-	pObj->regs->pVGA_ny = (UINT32)y - 1;
-	pObj->regs->pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-
-#else
-
-	if (!((xmax-xmin)%8))
-	{
-		for (y=ymin; y < ymax; y += pBuf->w)
-		{
-			pSrc = &pObj->pBG[xmin + y];
-			pSrc_end = &pObj->pBG[xmax + y];
-			pDst = &pBuf->pFB[xmin + y];
-			pDst_end = &pBuf->pFB[xmax + y];
-			while(pDst < pDst_end)
-			{
-				__gfx_block_copy_8(pDst, pSrc);
-				pDst += 8;
-				pSrc += 8;
-			}
-		}
-		return;
-	}
-
-//	fprintf(stderr, "GFX_DirtyRectCopy(): Slow copy!\n");
-	for (y=ymin; y < ymax; y += pBuf->w)
-	{
-		for (x=xmin; x < xmax; x++)
-		{
-			pBuf->pFB[x + y] = pObj->pBG[x + y];
-		}
-	}
-#endif
-
-}
-
-void GFX_box_draw(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color)
-{
-	UINT32 xmin, xmax, ymin, ymax, x, y;
-	UINT32 *pFB, *pFB_end;
-	buf_t *pBuf;
-
-	xmin = posx;
-	xmax = pBox->w + posx;
-	if (xmax > pObj->w)
-		xmax = pObj->w;
-
-	ymin = posy;
-	ymax = pBox->h + posy;
-	if (ymax > pObj->h)
-		ymax = pObj->h;
-
-	pBuf = pObj->pBuf->pNext;
-
-	// Lopp over all frame buffers, except current back buffer
-	while(pBuf != pObj->pBuf)
-	{
-		GFX_DirtyRectUpdate(pBuf, xmin, xmax, ymin, ymax);
-		pBuf = pBuf->pNext;
-
-	}
-	pBuf = pObj->pBuf;
-
-	ymin *= pObj->w;
-	ymax *= pObj->w;
-
-	while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-	if (!((xmax-xmin)%8))
-	{
-		for (y=ymin; y < ymax; y += pObj->w)
-		{
-			pFB = &pBuf->pFB[xmin + y];
-			pFB_end = &pBuf->pFB[xmax + y];
-			while(pFB < pFB_end)
-			{
-				__gfx_block_set_8(pFB, color);
-				pFB += 8;
-			}
-		}
-		return;
-	}
-
-//	fprintf(stderr, "GFX_box_draw(): Slow copy!\n");
-	for (y=ymin; y < ymax; y += pObj->w)
-	{
-		for (x=xmin; x < xmax; x++)
-		{
-			pBuf->pFB[x + y] = color;
-		}
-	}
-}
-
-void GFX_box_draw_bg(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color)
-{
-	UINT32 xmin, xmax, ymin, ymax, x, y;
-	UINT32 *pFB, *pFB_end;
-
-	xmin = posx;
-	xmax = pBox->w + posx;
-	if (xmax > pObj->w)
-		xmax = pObj->w;
-
-	ymin = posy;
-	ymax = pBox->h + posy;
-	if (ymax > pObj->h)
-		ymax = pObj->h;
-
-	ymin *= pObj->w;
-	ymax *= pObj->w;
-
-	while (pObj->regs->pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-	if (!((xmax-xmin)%8))
-	{
-		for (y=ymin; y < ymax; y += pObj->w)
-		{
-			pFB = &pObj->pBG[xmin + y];
-			pFB_end = &pObj->pBG[xmax + y];
-			while(pFB < pFB_end)
-			{
-				__gfx_block_set_8(pFB, color);
-				pFB += 8;
-			}
-		}
-		return;
-	}
-
-//	fprintf(stderr, "GFX_box_draw_bg(): Slow copy!\n");
-	for (y=ymin; y < ymax; y += pObj->w)
-	{
-		for (x=xmin; x < xmax; x++)
-		{
-			pObj->pBG[x + y] = color;
-		}
-	}
-}
-
-void GFX_box_draw_direct(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color)
-{
-	UINT32 xmin, xmax, ymin, ymax, x, y;
-	UINT32 *pFB, *pFB_end;
-	buf_t *pBuf;
-
-	pBuf = pObj->pBuf->pLast;
-
-	xmin = posx;
-	xmax = pBox->w + posx;
-	if (xmax > pObj->w)
-		xmax = pObj->w;
-
-	ymin = posy;
-	ymax = pBox->h + posy;
-	if (ymax > pObj->h)
-		ymax = pObj->h;
-
-	ymin *= pObj->w;
-	ymax *= pObj->w;
-
-	if (!((xmax-xmin)%8))
-	{
-		for (y=ymin; y < ymax; y += pObj->w)
-		{
-			pFB = &pBuf->pFB[xmin + y];
-			pFB_end = &pBuf->pFB[xmax + y];
-			while(pFB < pFB_end)
-			{
-				__gfx_block_set_8(pFB, color);
-				pFB += 8;
-			}
-		}
-		return;
-	}
-
-//	fprintf(stderr, "GFX_box_draw_direct(): Slow copy!\n");
-	for (y=ymin; y < ymax; y += pObj->w)
-	{
-		for (x=xmin; x < xmax; x++)
-		{
-			pBuf->pFB[x + y] = color;
-		}
-	}
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/mips_gfx.h b/lib/CPUs/MIPS/bsp/examples/mips_gfx.h
deleted file mode 100644
index 1363e07..0000000
--- a/lib/CPUs/MIPS/bsp/examples/mips_gfx.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef GFX_H
-#define GFX_H
-
-#include "libsys.h"
-
-#define	GFX_NUM_FRAME_BUFFERS	2
-#define	GFX_FRAME_NOSYNC		0
-#define	GFX_FRAME_SYNC			1
-
-// -------------------------------------------------------------
-// Types
-// -------------------------------------------------------------
-typedef struct _sbox_t
-{
-	UINT32 w, h;
-} box_t;
-
-typedef struct _srect_t
-{
-	UINT32 xmin, xmax;
-	UINT32 ymin, ymax;
-} rect_t;
-
-typedef struct _svga_hw_t
-{
-	UINT32 volatile pVGA_ctrl;			// 0xA0030000	// R/W
-	UINT32 volatile pVGA_ascii;			// 0xA0030004	// R/W
-	UINT32 volatile pVGA_posx;			// 0xA0030008	// R/W
-	UINT32 volatile pVGA_posy;			// 0xA003000C	// R/W
-	UINT32 volatile pVGA_cgcol;			// 0xA0030010	// R/W
-	UINT32 volatile pVGA_res;			// 0xA0030014	// RO
-	UINT32 volatile pVGA_front;			// 0xA0030018	// R/W
-	UINT32 volatile pVGA_back;			// 0xA003001C	// R/W
-	UINT32 volatile pVGA_src0;			// 0xA0030020	// R/W
-	UINT32 volatile pVGA_src0_last;		// 0xA0030024	// R/W
-	UINT32 volatile pVGA_src0_dimx;		// 0xA0030028	// R/W
-	UINT32 volatile pVGA_src0_res;		// 0xA003002C	// R/W
-	UINT32 volatile pVGA_src1;			// 0xA0030030	// R/W
-	UINT32 volatile pVGA_src1_last;		// 0xA0030034	// R/W
-	UINT32 volatile pVGA_src1_dimx;		// 0xA0030038	// R/W
-	UINT32 volatile pVGA_src1_res;		// 0xA003003C	// R/W
-	UINT32 volatile pVGA_src2;			// 0xA0030040	// R/W
-	UINT32 volatile pVGA_src2_last;		// 0xA0030044	// R/W
-	UINT32 volatile pVGA_src2_dimx;		// 0xA0030048	// R/W
-	UINT32 volatile pVGA_src2_res;		// 0xA003004C	// R/W
-	UINT32 volatile pVGA_dst;			// 0xA0030050	// R/W
-	UINT32 volatile pVGA_dst_last;		// 0xA0030054	// R/W
-	UINT32 volatile pVGA_dst_dimx;		// 0xA0030058	// R/W
-	UINT32 volatile pVGA_dst_res;		// 0xA003005C	// R/W
-	UINT32 volatile pVGA_nx;			// 0xA0030060	// R/W
-	UINT32 volatile pVGA_ny;			// 0xA0030064	// R/W
-
-} vga_hw_t;
-
-typedef struct _sbuf_t
-{
-	UINT32 *pFB;
-	struct _sbuf_t *pNext;
-	struct _sbuf_t *pLast;
-	UINT32 is_dirty;
-	rect_t rect;
-	UINT32 w, h;
-	vga_hw_t *regs;
-} buf_t;
-
-typedef struct _sgfx_t
-{
-	UINT32 w, h;
-	buf_t *pBuf;
-	UINT32 *pBG;
-	vga_hw_t *regs;
-
-} gfx_t;
-
-// -------------------------------------------------------------
-// Functions
-// -------------------------------------------------------------
-void __gfx_block_set_8(UINT32* pDst, UINT32 value);
-void __gfx_block_copy_8(UINT32* pDst, UINT32* pSrc);
-void __gfx_copy_32(UINT32* pDst, UINT32* pSrc, UINT32 nblocks);
-void GFX_init(gfx_t *pObj);
-void GFX_frame(gfx_t *pObj, UINT32 sync_mode);
-void GFX_show(gfx_t *pObj);
-void GFX_copy_front2back(gfx_t *pObj);
-void GFX_get_FB_front(gfx_t *pObj, UINT32 **ppFB);
-void box_create(box_t *pObj, UINT32 w, UINT32 h);
-void GFX_restore(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy);
-void GFX_box_draw(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color);
-void GFX_box_draw_bg(gfx_t *pObj, box_t *pBox, UINT32 posx, UINT32 posy, UINT32 color);
-
-#endif // GFX_H
diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.c b/lib/CPUs/MIPS/bsp/examples/mipsdis.c
deleted file mode 100644
index d05e965..0000000
--- a/lib/CPUs/MIPS/bsp/examples/mipsdis.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/* +----------------------------------------------------------------+ */
-/* |            Copyright (c) 1994 Stanford University.             | */
-/* |                      All Rights Reserved.                      | */
-/* |                                                                | */
-/* |   This software is distributed with *ABSOLUTELY NO SUPPORT*    | */
-/* |   and *NO WARRANTY*.   Use or reproduction of this code for    | */
-/* |   commerical gains is strictly prohibited.   Otherwise, you    | */
-/* |   are given permission to use or modify this code as long      | */
-/* |   as you do not remove this notice.                            | */
-/* +----------------------------------------------------------------+ */
-/* --------------------------------------------------- */
-/* | Copyright (c) 1986 MIPS Computer Systems, Inc.  | */
-/* | All Rights Reserved.                            | */
-/* --------------------------------------------------- */
-
-/*
- * Copyright 1985 by MIPS Computer Systems, Inc.
- */
-
-/* TORCH disassembler */
-/* derived from MIPS instruction dissassembler by PGL October 91 */
-
-#include <stdio.h>
-#include <string.h>
-#include "mips_dis.h"
-
-#define false 0
-#define true 1
-typedef int boolean;
-char *strcat();
-
-#define ZERO 0
-
-#define COMPILER_NAMES tdis_reg_names[0]
-#define HARDWARE_NAMES tdis_reg_names[1]
-#define ASSEMBLER_NAMES tdis_reg_names[2]
-#define DIS_REG_NAMES(x)	tdis_reg_names[x]
-
-union extension_byte {
-    unsigned char byte;
-    struct {	/* extension byte bits in little-endian order */
-#if (defined __MIPSEB || defined _MIPSEB || defined MIPSEB)
-	unsigned reserved:1;
-	unsigned dyn_nop:1;
-	unsigned rs_boost:2;
-	unsigned rt_boost:2;
-	unsigned rd_boost:2;
-#elif (defined __MIPSEL || defined _MIPSEL || defined MIPSEL)
-	unsigned rd_boost:2;
-	unsigned rt_boost:2;
-	unsigned rs_boost:2;
-	unsigned dyn_nop:1;
-	unsigned reserved:1;
-#endif /*MIPSEB*/
-    } e;
-};
-
-#define blez_op_T	blez_op
-#define blez_op_N	(blez_op | 0x10)
-#define bgtz_op_T	bgtz_op
-#define bgtz_op_N	(bgtz_op | 0x10)
-#define beq_op_T	beq_op
-#define beq_op_N	(beq_op | 0x10)
-#define bne_op_T	bne_op
-#define bne_op_N	(bne_op | 0x10)
-#define bc_op_T		bc_op
-#define bc_op_N		(bc_op | 0x02)
-
-static char *op_name[64] = {
-/* 0 */	"special",	"regimm","j",	"jal",	"beq",  "bne",  "blez", "bgtz",
-/* 8 */	"addi",	"addiu","slti",	"sltiu","andi",	"ori",	"xori",	"lui",
-/*16 */	"cop0",	"cop1",	"cop2",	"cop3",	"beql","bnel","blezl","bgtzl",
-/*24 */	"op60",	"op64",	"op68",	"op6c",	"op70",	"op74",	"op78",	"op7c",
-/*32 */	"lb",	"lh",	"lwl",	"lw",	"lbu",	"lhu",	"lwr",	"ld",
-/*40 */	"sb",	"sh",	"swl",	"sw",	"opb0",	"opb4",	"swr",	"sd",
-/*48 */	"lwc0",	"lwc1",	"lwc2",	"lwc3",	"ldc0",	"ldc1",	"ldc2",	"ldc3",
-/*56 */	"swc0",	"swc1",	"swc2",	"swc3",	"sdc0",	"sdc1",	"sdc2",	"sdc3"
-};
-
-static char *spec_name[64] = {
-/* 0*/ "sll",	"spec01","srl",	"sra",	"sllv",	"spec05","srlv","srav",
-/* 8*/ "jr",	"jalr",	"spec12","spec13","syscall","break","vcall","spec17",
-/*16*/ "mfhi",	"mthi",	"mflo",	"mtlo",	"spec24","spec25","spec26","spec27",
-/*24*/ "mult",	"multu","div",	"divu",	"spec34","spec35","spec36","spec37",
-/*32*/ "add",	"addu",	"sub",	"subu",	"and",	"or",	"xor",	"nor",
-/*40*/ "spec50","spec51","slt","sltu",	"spec54","spec55","spec56","spec57",
-/*48*/ "spec60","spec61","spec62","spec63","spec64","spec65","spec66","spec67",
-/*56*/ "spec70","spec71","spec72","spec73","spec74","spec75","spec76","spec77"
-};
-
-static char *bcond_name[32] = {
-	"bltz",
-	"bgez",
-	"bltzl",
-	"bgezl",
-	"bcond04",
-	"bcond05",
-	"bcond06",
-	"bcond07",
-	"tgei",
-	"tgeiu",
-	"tlti",
-	"tltiu",
-	"teqi",
-	"bcond0d",
-	"tnei",
-	"bcond0f",
-	"bltzal",
-	"bgezal",
-	"bltzall",
-	"bgezall",
-	"bcond14",
-	"bcond15",
-	"bcond16",
-	"bcond17",
-	"bcond18",
-	"bcond19",
-	"bcond1a",
-	"bcond1b",
-	"bcond1c",
-	"bcond1d",
-	"bcond1e",
-	"bcond1f"
-};
-
-static char *cop1_name[64] = {
-/* 0 */	"add",	"sub",	"mul",	"div",	"sqrt", "abs",	"mov",	"neg",
-/* 8 */	"fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f",
-/*16 */	"fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17",
-/*24 */	"fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f",
-/*32 */	"cvt.s","cvt.d","cvt.e","fop23","cvt.w","fop25","fop26","fop27",
-/*40 */	"fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f",
-/*48 */	"c.f", "c.un","c.eq","c.ueq","c.olt","c.ult","c.ole","c.ule",
-/*56 */	"c.sf","c.ngle","c.seq","c.ngl","c.lt","c.nge","c.le","c.ngt"
-};
-
-static char *fmt_name[16] = {
-	"s",	"d",	"e",	"q",
-	"w",	"fmt5",	"fmt6",	"fmt7",
-	"fmt8",	"fmt9",	"fmta",	"fmtb",
-	"fmtc",	"fmtd",	"fmte",	"fmtf"
-};
-
-/* public */
-/* Three sets of commonly used register names */
-const char *tdis_reg_names[3][64] = {
-    {   /* compiler names */
-	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3",
-	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7",
-	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7",
-	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra",
-	"zero.B","at.B","v0.B",	"v1.B",	"a0.B",	"a1.B",	"a2.B",	"a3.B",
-	"t0.B",	"t1.B",	"t2.B",	"t3.B",	"t4.B",	"t5.B",	"t6.B",	"t7.B",
-	"s0.B",	"s1.B",	"s2.B",	"s3.B",	"s4.B",	"s5.B",	"s6.B",	"s7.B",
-	"t8.B",	"t9.B",	"k0.B",	"k1.B",	"gp.B",	"sp.B",	"s8.B",	"ra.B"
-    },
-    {	/* hardware names */
-	"r0",	"r1",	"r2",	"r3",	"r4",	"r5",	"r6",	"r7",
-	"r8",	"r9",	"r10",	"r11",	"r12",	"r13",	"r14",	"r15",
-	"r16",	"r17",	"r18",	"r19",	"r20",	"r21",	"r22",	"r23",
-	"r24",	"r25",	"r26",	"r27",	"gp",	"sp",	"r30",	"r31",
-	"r0.B",	"r1.B",	"r2.B",	"r3.B",	"r4.B",	"r5.B",	"r6.B",	"r7.B",
-	"r8.B",	"r9.B",	"r10.B","r11.B","r12.B","r13.B","r14.B","r15.B",
-	"r16.B","r17.B","r18.B","r19.B","r20.B","r21.B","r22.B","r23.B",
-	"r24.B","r25.B","r26.B","r27.B","gp.B",	"sp.B",	"r30.B","r31.B"
-    },
-    {	/* assembler names */
-	"$0",	"$at",	"$2",	"$3",	"$4",	"$5",	"$6",	"$7",
-	"$8",	"$9",	"$10",	"$11",	"$12",	"$13",	"$14",	"$15",
-	"$16",	"$17",	"$18",	"$19",	"$20",	"$21",	"$22",	"$23",
-	"$24",	"$25",	"$26",	"$27",	"$gp",	"$sp",	"$30",	"$31",
-	"$0.B",	"$at.B","$2.B",	"$3.B",	"$4.B",	"$5.B",	"$6.B",	"$7.B",
-	"$8.B",	"$9.B",	"$10.B","$11.B","$12.B","$13.B","$14.B","$15.B",
-	"$16.B","$17.B","$18.B","$19.B","$20.B","$21.B","$22.B","$23.B",
-	"$24.B","$25.B","$26.B","$27.B","$gp.B","$sp.B","$30.B","$31.B"
-    }
-};
-
-static char *c0_opname[64] = {
-    "c0op0","tlbr","tlbwi","c0op3","c0op4","c0op5","tlbwr","c0op7",
-    "tlbp","c0op9","c0op10","c0op11","c0op12","c0op13","c0op14","c0op15",
-    "rfe","c0op17","c0op18","c0op19","c0op20","c0op21","c0op22","c0op23",
-    "c0op24","c0op25","c0op26","c0op27","c0op28","c0op29","c0op30","c0op31",
-    "c0op32","c0op33","c0op34","c0op35","c0op36","c0op37","c0op38","c0op39",
-    "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47",
-    "c0op48","c0op49","c0op50","c0op51","c0op52","c0op53","c0op54","c0op55",
-    "c0op56","c0op57","c0op58","c0op59","c0op60","c0op61","c0op62","c0op63"
-};
-
-static char *c0_reg[32] = {
-    "index","random","tlblo","c0r3","context","c0r5","c0r6","c0r7",
-    "badvaddr","c0r9","tlbhi","epcn","sr",	"cause","epc",	"c0r15",
-    "c0r16","c0r17","c0r18","c0r19","c0r20","c0r21","c0r22","c0r23",
-    "c0r24","c0r25","c0r26","c0r27","c0r28","c0r29","c0r30","c0r31"
-};
-
-/* Remember the options set by dis_init */
-//#define ADDR_DEFAULT "%#010x:\t"
-#define ADDR_DEFAULT 0
-//#define VALUE_DEFAULT "%#010x\t"
-#define VALUE_DEFAULT 0
-#define NAME_DEFAULT COMPILER_NAMES
-static struct {
-    char *addr_format;
-    char *value_format;
-    const char **reg_names;
-    int print_jal_targets;
-} save = {
-    ADDR_DEFAULT,
-    VALUE_DEFAULT,
-    NAME_DEFAULT,
-    true
-};
-
-/* Update regmask to reflect the use of this general-purpose (not fp)
-  register, and return its name */
-static const char *
-register_name(ireg, boosted, regmask)
-unsigned ireg, *regmask;
-int boosted;
-{
-    if (!boosted)
-	*regmask |= (1 << ireg);
-    return save.reg_names[boosted ? ireg + 32 : ireg];
-}
-
-/* public -- see dissassembler.h */
-int
-tdisasm(buffer, address, iword, ext, regmask, symbol_value, ls_register)
-char *buffer;
-unsigned char ext;	/* extension byte */
-unsigned address, iword, *regmask, *symbol_value, *ls_register;
-{
-    int return_value = 0;
-    char *bufptr = buffer;
-    boolean do_b_displacement = false;
-    boolean do_loadstore = false;
-    union mips_instruction i;
-    union extension_byte e;
-
-	*bufptr = 0;
-    i.word = iword;
-    e.byte = ext;
-    *regmask = *symbol_value = *ls_register = 0;
-
-    /* Put out the address and hex value of the instruction,
-       leaving bufptr set at the end */
-    if (save.addr_format) {
-	sprintf(bufptr, save.addr_format, address);
-	bufptr += strlen(bufptr);
-    }
-    if (save.value_format) {
-	sprintf(bufptr, save.value_format, iword);
-	bufptr += strlen(bufptr);
-    }
-
-    /* check for dynamic NOP */
-    if (e.e.dyn_nop) {
-	strcat(bufptr, "D.");
-	bufptr += 2;
-    }
-
-    /* decode the instruction */
-    switch (i.j_format.opcode) {
-
-    case spec_op:
-
-	if (i.word == 0x20) {
-	    strcat(bufptr, "nop");
-	    if (e.e.rd_boost)
-		strcat(bufptr, ".B");
-	    bufptr += strlen(bufptr);
-	    break;
-	} else if (i.r_format.func == addu_op && i.r_format.rt == ZERO) {
-	    sprintf(bufptr, "move%s\t%s,%s",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    bufptr += strlen(bufptr);
-	    break;
-	}
-	strcat(bufptr, spec_name[i.r_format.func]);
-	if (e.e.rd_boost)
-	    strcat(bufptr, ".B");
-	bufptr += strlen(bufptr);
-
-	switch (i.r_format.func) {
-	case sll_op:
-	case srl_op:
-	case sra_op:
-	    sprintf(bufptr, "\t%s,%s,%d",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask),
-		    i.r_format.re);
-	    break;
-	case sllv_op:
-	case srlv_op:
-	case srav_op:
-	    sprintf(bufptr, "\t%s,%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    break;
-	case mfhi_op:
-	case mflo_op:
-	    sprintf(bufptr, "\t%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask));
-	    break;
-	case jalr_op:
-	    return_value = 3;
-	    sprintf(bufptr, "\t%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    *ls_register = i.r_format.rs;
-	    break;
-	case jr_op:
-	    return_value = 3;
-	    *ls_register = i.r_format.rs;
-	    /* fall through */
-	case mtlo_op:
-	case mthi_op:
-	    sprintf(bufptr, "\t%s",
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    break;
-	case mult_op:
-	case multu_op:
-	case div_op:
-	case divu_op:
-	    sprintf(bufptr, "\t%s,%s",
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask));
-	    break;
-	case syscall_op:
-	    break;
-	case break_op:
-	case vcall_op:
-	    {
-		char *format = "\t%d";
-		unsigned op2 = i.r_format.rd * 32 + i.r_format.re;
-
-		if (op2)
-		    format = "\t%d,%d";
-		sprintf(bufptr, format, i.r_format.rs*32+i.r_format.rt,
-			op2);
-	    }
-	    break;
-	default:
-	    sprintf(bufptr, "\t%s,%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask));
-	    break;
-	};
-	break;
-
-    case bcond_op:
-	sprintf(bufptr, "%s%s\t%s,",
-		bcond_name[i.i_format.rt],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	do_b_displacement = true;
-	break;
-
-    case blez_op_T:
-    case bgtz_op_T:
-    case blez_op_N:
-    case bgtz_op_N:
-	sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	do_b_displacement = true;
-	break;
-    case beq_op_T:
-    case beq_op_N:
-	if (i.i_format.rs == ZERO && i.i_format.rt == ZERO) {
-	    strcat(bufptr, "b");
-	    if (i.j_format.opcode == beq_op_T)
-		strcat(bufptr, ".T");
-	    else
-		strcat(bufptr, ".N");
-	    if (e.e.rd_boost)
-		strcat(bufptr, ".B\t");
-	    else
-		strcat(bufptr, "\t");
-	    do_b_displacement = true;
-	    break;
-	}
-	/* fall through */
-    case bne_op_T:
-    case bne_op_N:
-	sprintf(bufptr, "%s%s\t%s,%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask),
-		register_name(i.i_format.rt, e.e.rt_boost, regmask));
-	do_b_displacement = true;
-	break;
-
-    case cop0_op:
-    case cop1_op:
-    case cop2_op:
-    case cop3_op:
-	{
-	    unsigned which_cop = i.j_format.opcode - cop0_op;
-	    char *f_or_r = "rf";
-
-	    switch (i.r_format.rs) {
-	    case bc_op_T:
-		sprintf(bufptr, "bc%d%c.T%s\t", which_cop,
-			"ft"[i.r_format.rt],
-			e.e.rd_boost ? ".B" : "");
-		do_b_displacement = true;
-		break;
-	    case bc_op_N:
-		sprintf(bufptr, "bc%d%c.N%s\t", which_cop,
-			"ft"[i.r_format.rt],
-			e.e.rd_boost ? ".B" : "");
-		do_b_displacement = true;
-		break;
-	    case mtc_op:
-		if (which_cop == 0)
-		    sprintf(bufptr, "mtc%d%s\t%s,%s", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    c0_reg[i.f_format.rd]);
-		else
-		    sprintf(bufptr, "mtc%d%s\t%s,%c%d", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    f_or_r[(which_cop == 1)],
-			    i.f_format.rd);
-		break;
-	    case mfc_op:
-		if (which_cop == 0)
-		    sprintf(bufptr, "mfc%d%s\t%s,%s", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    c0_reg[i.f_format.rd]);
-		else
-		    sprintf(bufptr, "mfc%d%s\t%s,%c%d", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    f_or_r[(which_cop == 1)],
-			    i.f_format.rd);
-		break;
-	    case cfc_op:
-		sprintf(bufptr, "cfc%d%s\t%s,%c%d", which_cop,
-			e.e.rd_boost ? ".B" : "",
-			register_name(i.r_format.rt, e.e.rt_boost, regmask),
-			f_or_r[(which_cop == 1)],
-			i.f_format.rd);
-		break;
-	    case ctc_op:
-		sprintf(bufptr, "ctc%d%s\t%s,%c%d", which_cop,
-			e.e.rd_boost ? ".B" : "",
-			register_name(i.r_format.rt, e.e.rt_boost, regmask),
-			f_or_r[(which_cop == 1)],
-			i.f_format.rd);
-		break;
-	    default:
-		if (which_cop != 1)
-		    sprintf(bufptr, "c0%s\t%s", e.e.rd_boost ? ".B" : "",
-			    c0_opname[i.f_format.func]);
-		else
-		    {
-			sprintf(bufptr, "%s.%s%s\t",
-				cop1_name[i.f_format.func],
-				fmt_name[i.f_format.fmt],
-				e.e.rd_boost ? ".B" : "");
-			bufptr += strlen(bufptr);
-			switch (i.f_format.func) {
-			case fsqrt_op:
-			case fabs_op:
-			case fmov_op:
-			case fcvts_op:
-			case fcvtd_op:
-			case fcvte_op:
-			case fcvtw_op:
-			    sprintf(bufptr, "f%d,f%d",
-				    i.f_format.re,
-				    i.f_format.rd);
-			    break;
-			case fcmp_op+0x0:
-			case fcmp_op+0x1:
-			case fcmp_op+0x2:
-			case fcmp_op+0x3:
-			case fcmp_op+0x4:
-			case fcmp_op+0x5:
-			case fcmp_op+0x6:
-			case fcmp_op+0x7:
-			case fcmp_op+0x8:
-			case fcmp_op+0x9:
-			case fcmp_op+0xa:
-			case fcmp_op+0xb:
-			case fcmp_op+0xc:
-			case fcmp_op+0xd:
-			case fcmp_op+0xe:
-			case fcmp_op+0xf:
-			    sprintf(bufptr, "f%d,f%d",
-				    i.f_format.rd,
-				    i.f_format.rt);
-			    break;
-			default:
-			    sprintf(bufptr, "f%d,f%d,f%d",
-				    i.f_format.re,
-				    i.f_format.rd,
-				    i.f_format.rt);
-			    break;
-			}	/* switch on func */
-		    }
-		break;		/* End of default */
-	    }			/* switch on rs */
-	}
-	break;			/* End of cop0, cop1, cop2, cop3 */
-
-    case jal_op:
-    case j_op:
-	sprintf(bufptr, "%s%s\t", op_name[i.j_format.opcode],
-		e.e.rd_boost ? ".B" : "");
-	*symbol_value = (address & 0xF0000000) | i.j_format.target << 2;
-	if (save.print_jal_targets)
-	    {
-		bufptr += strlen(bufptr);
-		sprintf(bufptr, "%#x", *symbol_value);
-	    }
-	return_value = 1;
-	break;
-
-    case swc1_op:
-    case sdc1_op:
-    case lwc1_op:
-    case ldc1_op:
-	sprintf(bufptr, "%s%s\tf%d,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		i.i_format.rt);
-	do_loadstore = true;
-	break;
-
-    case lb_op:
-    case lh_op:
-    case lw_op:
-    case ld_op:
-    case lbu_op:
-    case lhu_op:
-    case sb_op:
-    case sh_op:
-    case sw_op:
-    case sd_op:
-    case lwl_op:
-    case lwr_op:
-	sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rt, e.e.rt_boost, regmask));
-	do_loadstore = true;
-	break;
-
-    case ori_op:
-    case xori_op:
-	if (i.u_format.rs == ZERO) {
-	    sprintf(bufptr, "li%s\t%s,%d",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		    i.u_format.uimmediate);
-	    break;
-	}
-	/* fall through */
-    case andi_op:
-	sprintf(bufptr, "%s%s\t%s,%s,%#x", op_name[i.u_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		register_name(i.u_format.rs, e.e.rs_boost, regmask),
-		i.u_format.uimmediate);
-	break;
-    case lui_op:
-	sprintf(bufptr, "%s%s\t%s,%#x", op_name[i.u_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		i.u_format.uimmediate);
-	break;
-    case addi_op:
-    case addiu_op:
-	if (i.i_format.rs == ZERO) {
-	    short sign_extender = i.i_format.simmediate;
-	    sprintf(bufptr, "li%s\t%s,%d",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.i_format.rt, e.e.rt_boost, regmask),
-		    sign_extender);
-	    break;
-	}
-	/* fall through */
-    default:
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    sprintf(bufptr, "%s%s\t%s,%s,%d", op_name[i.i_format.opcode],
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.i_format.rt, e.e.rt_boost, regmask),
-		    register_name(i.i_format.rs, e.e.rs_boost, regmask),
-		    sign_extender);
-	}
-	break;
-    }
-
-    /* Some instructions require more than just registers */
-
-    if (do_loadstore)
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    *symbol_value = sign_extender;
-	    *ls_register = i.i_format.rs;
-	    bufptr += strlen(bufptr);
-	    sprintf(bufptr, "%d(%s)", sign_extender,
-		    register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	    return_value = -1;
-	}
-    else if (do_b_displacement)
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    bufptr += strlen(bufptr);
-	    *symbol_value = 4 + address + ((((long)sign_extender & 0xFFFD0000) | (0x3FFFF & (sign_extender << 2))));
-	    sprintf(bufptr, "%#x", *symbol_value);
-	    return_value = 2;
-	}
-
-    return return_value;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.h b/lib/CPUs/MIPS/bsp/examples/mipsdis.h
deleted file mode 100644
index 2e9aca4..0000000
--- a/lib/CPUs/MIPS/bsp/examples/mipsdis.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/* ------------------------------------------------------------------ */
-/* | Copyright Unpublished, MIPS Computer Systems, Inc.  All Rights | */
-/* | Reserved.  This software contains proprietary and confidential | */
-/* | information of MIPS and its suppliers.  Use, disclosure or     | */
-/* | reproduction is prohibited without the prior express written   | */
-/* | consent of MIPS.                                               | */
-/* ------------------------------------------------------------------ */
-/*  inst.h 4.2 */
-/*
- * inst.h -- instruction format defines
- */
-
-/**
- ** UPDATE - 19 Sept 89 by Michael Smith
- **
- ** Removed signed type to remove obnoxious C++ warning message.
- **/
-
-#ifdef LANGUAGE_C
-#ifdef MIPSEB
-union mips_instruction {
-	unsigned word;
-	unsigned char byte[4];
-	struct {
-		unsigned opcode : 6;
-		unsigned target : 26;
-	} j_format;
-	struct {
-		unsigned opcode : 6;
-		unsigned rs : 5;
-		unsigned rt : 5;
-		unsigned simmediate : 16;
-	} i_format;
-	struct {
-		unsigned opcode : 6;
-		unsigned rs : 5;
-		unsigned rt : 5;
-		unsigned uimmediate : 16;
-	} u_format;
-	struct {
-		unsigned opcode : 6;
-		unsigned rs : 5;
-		unsigned rt : 5;
-		unsigned rd : 5;
-		unsigned re : 5;
-		unsigned func : 6;
-	} r_format;
-	struct {
-		unsigned opcode : 6;
-		unsigned : 1;
-		unsigned fmt : 4;
-		unsigned rt : 5;
-		unsigned rd : 5;
-		unsigned re : 5;
-		unsigned func : 6;
-	} f_format;
-};
-#endif
-
-#ifdef MIPSEL
-union mips_instruction {
-	unsigned word;
-	unsigned char byte[4];
-	struct {
-		unsigned target : 26;
-		unsigned opcode : 6;
-	} j_format;
-	struct {
-		unsigned simmediate : 16;
-		unsigned rt : 5;
-		unsigned rs : 5;
-		unsigned opcode : 6;
-	} i_format;
-	struct {
-		unsigned uimmediate : 16;
-		unsigned rt : 5;
-		unsigned rs : 5;
-		unsigned opcode : 6;
-	} u_format;
-	struct {
-		unsigned func : 6;
-		unsigned re : 5;
-		unsigned rd : 5;
-		unsigned rt : 5;
-		unsigned rs : 5;
-		unsigned opcode : 6;
-	} r_format;
-	struct {
-		unsigned func : 6;
-		unsigned re : 5;
-		unsigned rd : 5;
-		unsigned rt : 5;
-		unsigned fmt : 4;
-		unsigned : 1;
-		unsigned opcode : 6;
-	} f_format;
-};
-#endif
-
-#define	spec_op		0x00
-#define	bcond_op	0x01
-#define	j_op		0x02
-#define	jal_op		0x03
-
-#define	beq_op		0x04
-#define	bne_op		0x05
-#define	blez_op		0x06
-#define	bgtz_op		0x07
-
-#define	addi_op		0x08
-#define	addiu_op	0x09
-#define	slti_op		0x0A
-#define	sltiu_op	0x0B
-
-#define	andi_op		0x0C
-#define	ori_op		0x0D
-#define	xori_op		0x0E
-#define	lui_op		0x0F
-
-#define	lb_op		0x20
-#define	lh_op		0x21
-#define	lw_op		0x23
-#define	lbu_op		0x24
-#define	lhu_op		0x25
-#define	ld_op		0x27
-#define	sb_op		0x28
-#define	sh_op		0x29
-#define	sw_op		0x2B
-#define	sd_op		0x2F
-#define	lwl_op		0x22
-#define	lwr_op		0x26
-#define	swl_op		0x2a
-#define	swr_op		0x2e
-
-/* Co-processor sub-opcodes */
-#define	bc_op		0x08
-#define	mfc_op		0x00
-#define cfc_op		0x02
-#define	mtc_op		0x04
-#define ctc_op		0x06
-
-/* Co-processor 0 opcodes */
-#define	cop0_op		0x10
-#define	lwc0_op		0x30
-#define	ldc0_op		0x34
-#define	swc0_op		0x38
-#define	sdc0_op		0x3c
-
-/* Co-processor 0 sub-opcodes */
-#define	tlbr_op		0x1
-#define	tlbwi_op	0x2
-#define	tlbwr_op	0x6
-#define	tlbp_op		0x8
-#define	rfe_op		0x10
-
-/* Co-processor 1 opcodes */
-#define	cop1_op		0x11
-#define	lwc1_op		0x31
-#define	ldc1_op		0x35
-#define	swc1_op		0x39
-#define	sdc1_op		0x3D
-
-/* Co-processor 1 sub-opcodes */
-#define	fadd_op		0x00
-#define	fsub_op		0x01
-#define	fmpy_op		0x02
-#define	fdiv_op		0x03
-#define	fsqrt_op	0x04
-#define	fabs_op		0x05
-#define	fmov_op		0x06
-#define fneg_op		0x07
-#define	fcvts_op	0x20
-#define	fcvtd_op	0x21
-#define	fcvte_op	0x22
-#define	fcvtw_op	0x24
-#define	fcmp_op		0x30
-#define	s_fmt		0
-#define	d_fmt		1
-#define	e_fmt		2
-#define	w_fmt		4
-
-/* Other coprocessor opcodes */
-#define	cop2_op		0x12
-#define	lwc2_op		0x32
-#define	ldc2_op		0x36
-#define	swc2_op		0x3a
-#define	sdc2_op		0x3e
-
-#define	cop3_op		0x13
-#define	lwc3_op		0x33
-#define	ldc3_op		0x37
-#define	swc3_op		0x3b
-#define	sdc3_op		0x3f
-
-
-/* bcond subopcodes */
-#define	bltz_op		0x00
-#define	bgez_op		0x01
-#define	bltzal_op	0x10
-#define	bgezal_op	0x11
-
-/* special subopcodes */
-#define	sll_op		0x00
-#define	srl_op		0x02
-#define	sra_op		0x03
-#define	sllv_op		0x04
-#define	srlv_op		0x06
-#define	srav_op		0x07
-#define	jr_op		0x08
-#define	jalr_op		0x09
-#define	syscall_op	0x0C
-#define	break_op	0x0D
-#define	vcall_op	0x0E
-
-#define	mfhi_op		0x10
-#define	mthi_op		0x11
-#define	mflo_op		0x12
-#define	mtlo_op		0x13
-#define	mult_op		0x18
-#define	multu_op	0x19
-#define	div_op		0x1A
-#define	divu_op		0x1B
-
-#define	add_op		0x20
-#define	addu_op		0x21
-#define	and_op		0x24
-#define	or_op		0x25
-#define	xor_op		0x26
-#define	nor_op		0x27
-#define	sub_op		0x22
-#define	subu_op		0x23
-#define	slt_op		0x2A
-#define	sltu_op		0x2B
-
-#endif /* LANGUAGE_C */
-
-#ifdef LANGUAGE_PASCAL
-
-#ifdef MIPSEB
-type
-    mips_instruction =
-      packed record
-        case cardinal of
-	  0: (
-	    word: cardinal;
-	    );
-	  1: (
-	    byte: packed array[0..3] of 0..255;
-	    );
-	  2: (
-	    opcode: 0..63;
-	    target: 0..67108863;
-	    );
-	  3: (
-	    opcode3: 0..63;
-	    rs: 0..31;
-	    rt: 0..31;
-	    simmediate: -32768..32767;
-	    );
-	  4: (
-	    opcode4: 0..63;
-	    rs4: 0..63;
-	    rt4: 0..63;
-	    uimmediate: 0..65535;
-	    );
-	  5: (
-	    opcode5: 0..63;
-	    rs5: 0..63;
-	    rt5: 0..63;
-	    rd5: 0..63;
-	    re5: 0..63;
-	    func: 0..63;
-	    );
-      end {record};
-#endif
-
-#ifdef MIPSEL
-type
-    mips_instruction =
-      packed record
-        case cardinal of
-	  0: (
-	    word: cardinal;
-	    );
-	  1: (
-	    byte: packed array[0..3] of 0..255;
-	    );
-	  2: (
-	    target: 0..67108863;
-	    opcode: 0..63;
-	    );
-	  3: (
-	    simmediate: -32768..32767;
-	    rt: 0..31;
-	    rs: 0..31;
-	    opcode3: 0..63;
-	    );
-	  4: (
-	    uimmediate: 0..65535;
-	    rt4: 0..63;
-	    rs4: 0..63;
-	    opcode4: 0..63;
-	    );
-	  5: (
-	    func: 0..63;
-	    re5: 0..63;
-	    rd5: 0..63;
-	    rt5: 0..63;
-	    rs5: 0..63;
-	    opcode5: 0..63;
-	    );
-      end {record};
-#endif
-
-#define	spec_op		16#00
-#define	bcond_op	16#01
-#define	j_op		16#02
-#define	jal_op		16#03
-
-#define	beq_op		16#04
-#define	bne_op		16#05
-#define	blez_op		16#06
-#define	bgtz_op		16#07
-
-#define	addi_op		16#08
-#define	addiu_op	16#09
-#define	slti_op		16#0A
-#define	sltiu_op	16#0B
-
-#define	andi_op		16#0C
-#define	ori_op		16#0D
-#define	xori_op		16#0E
-#define	lui_op		16#0F
-
-#define	lb_op		16#20
-#define	lh_op		16#21
-#define	lw_op		16#23
-#define	lbu_op		16#24
-#define	lhu_op		16#25
-#define	ld_op		16#27
-#define	sb_op		16#28
-#define	sh_op		16#29
-#define	sw_op		16#2B
-#define	sd_op		16#2F
-#define	lwl_op		16#22
-#define	lwr_op		16#26
-#define	swl_op		16#2a
-#define	swr_op		16#2e
-
-/* Co-processor sub-opcodes */
-#define	bc_op		16#08
-#define	mfc_op		16#00
-#define cfc_op		16#02
-#define	mtc_op		16#04
-#define ctc_op		16#06
-
-/* Co-processor 0 opcodes */
-#define	cop0_op		16#10
-#define	lwc0_op		16#30
-#define	ldc0_op		16#34
-#define	swc0_op		16#38
-#define	sdc0_op		16#3c
-
-/* Co-processor 0 sub-opcodes */
-#define	tlbr_op		16#1
-#define	tlbwi_op	16#2
-#define	tlbwr_op	16#6
-#define	tlbp_op		16#8
-#define	rfe_op		16#10
-
-/* Co-processor 1 opcodes */
-#define	cop1_op		16#11
-#define	lwc1_op		16#31
-#define	ldc1_op		16#35
-#define	swc1_op		16#39
-#define	sdc1_op		16#3D
-
-/* Co-processor 1 sub-opcodes */
-#define	fadd_op		16#00
-#define	fsub_op		16#01
-#define	fmpy_op		16#02
-#define	fdiv_op		16#03
-#define	fsqrt_op	16#04
-#define	fabs_op		16#05
-#define	fmov_op		16#06
-#define fneg_op		16#07
-#define	fcvts_op	16#20
-#define	fcvtd_op	16#21
-#define	fcvte_op	16#22
-#define	fcvtw_op	16#24
-#define	fcmp_op		16#30
-#define	s_fmt		0
-#define	d_fmt		1
-#define	e_fmt		2
-#define	w_fmt		4
-
-/* Other coprocessor opcodes */
-#define	cop2_op		16#12
-#define	lwc2_op		16#32
-#define	ldc2_op		16#36
-#define	swc2_op		16#3a
-#define	sdc2_op		16#3e
-
-#define	cop3_op		16#13
-#define	lwc3_op		16#33
-#define	ldc3_op		16#37
-#define	swc3_op		16#3b
-#define	sdc3_op		16#3f
-
-
-/* bcond subopcodes */
-#define	bltz_op		16#00
-#define	bgez_op		16#01
-#define	bltzal_op	16#10
-#define	bgezal_op	16#11
-
-/* special subopcodes */
-#define	sll_op		16#00
-#define	srl_op		16#02
-#define	sra_op		16#03
-#define	sllv_op		16#04
-#define	srlv_op		16#06
-#define	srav_op		16#07
-#define	jr_op		16#08
-#define	jalr_op		16#09
-#define	syscall_op	16#0C
-#define	break_op	16#0D
-#define	vcall_op	16#0E
-
-#define	mfhi_op		16#10
-#define	mthi_op		16#11
-#define	mflo_op		16#12
-#define	mtlo_op		16#13
-#define	mult_op		16#18
-#define	multu_op	16#19
-#define	div_op		16#1A
-#define	divu_op		16#1B
-
-#define	add_op		16#20
-#define	addu_op		16#21
-#define	and_op		16#24
-#define	or_op		16#25
-#define	xor_op		16#26
-#define	nor_op		16#27
-#define	sub_op		16#22
-#define	subu_op		16#23
-#define	slt_op		16#2A
-#define	sltu_op		16#2B
-
-#endif /* LANGUAGE_PASCAL */
diff --git a/lib/CPUs/MIPS/bsp/examples/paranoia.c b/lib/CPUs/MIPS/bsp/examples/paranoia.c
deleted file mode 100644
index 38f08e1..0000000
--- a/lib/CPUs/MIPS/bsp/examples/paranoia.c
+++ /dev/null
@@ -1,2302 +0,0 @@
-/*
- *  paranoia.c,v 1.4 1995/08/23 19:26:32 joel Exp
- *
- *      A C version of Kahan's Floating Point Test "Paranoia"
- *
- *                      Thos Sumner, UCSF, Feb. 1985
- *                      David Gay, BTL, Jan. 1986
- *
- *      This is a rewrite from the Pascal version by
- *
- *                      B. A. Wichmann, 18 Jan. 1985
- *
- *      (and does NOT exhibit good C programming style).
- *
- *      Sun May 16 18:21:51 MDT 1993 Jeffrey Wheat (cassidy@cygnus.com)
- *      Removed KR_headers defines, removed ANSI prototyping
- *      Cleaned up and reformated code. Added special CYGNUS
- *      "verbose" mode type messages (-DCYGNUS).
- *      Note: This code is VERY NASTY.
- *
- *      Adjusted to use Standard C headers 19 Jan. 1992 (dmg);
- *      compile with -DKR_headers or insert
- * #define KR_headers
- *      at the beginning if you have an old-style C compiler.
- *
- * (C) Apr 19 1983 in BASIC version by:
- *      Professor W. M. Kahan,
- *      567 Evans Hall
- *      Electrical Engineering & Computer Science Dept.
- *      University of California
- *      Berkeley, California 94720
- *      USA
- *
- * converted to Pascal by:
- *      B. A. Wichmann
- *      National Physical Laboratory
- *      Teddington Middx
- *      TW11 OLW
- *      UK
- *
- * converted to C by:
- *
- *      David M. Gay            and     Thos Sumner
- *      AT&T Bell Labs                  Computer Center, Rm. U-76
- *      600 Mountain Avenue             University of California
- *      Murray Hill, NJ 07974           San Francisco, CA 94143
- *      USA                             USA
- *
- * with simultaneous corrections to the Pascal source (reflected
- * in the Pascal source available over netlib).
- * [A couple of bug fixes from dgh = sun!dhough incorporated 31 July 1986.]
- *
- * Reports of results on various systems from all the versions
- * of Paranoia are being collected by Richard Karpinski at the
- * same address as Thos Sumner.  This includes sample outputs,
- * bug reports, and criticisms.
- *
- * You may copy this program freely if you acknowledge its source.
- * Comments on the Pascal version to NPL, please.
- *
- *
- * The C version catches signals from floating-point exceptions.
- * If signal(SIGFPE,...) is unavailable in your environment, you may
- * #define NOSIGNAL to comment out the invocations of signal.
- *
- * This source file is too big for some C compilers, but may be split
- * into pieces.  Comments containing "SPLIT" suggest convenient places
- * for this splitting.  At the end of these comments is an "ed script"
- * (for the UNIX(tm) editor ed) that will do this splitting.
- *
- * By #defining SINGLE_PRECISION when you compile this source, you may
- * obtain a single-precision C version of Paranoia.
- *
- * The following is from the introductory commentary from Wichmann's work:
- *
- * The BASIC program of Kahan is written in Microsoft BASIC using many
- * facilities which have no exact analogy in Pascal.  The Pascal
- * version below cannot therefore be exactly the same.  Rather than be
- * a minimal transcription of the BASIC program, the Pascal coding
- * follows the conventional style of block-structured languages.  Hence
- * the Pascal version could be useful in producing versions in other
- * structured languages.
- *
- * Rather than use identifiers of minimal length (which therefore have
- * little mnemonic significance), the Pascal version uses meaningful
- * identifiers as follows [Note: A few changes have been made for C]:
- *
- *
- * BASIC   C               BASIC   C               BASIC   C
- *
- *   A                       J                       S    StickyBit
- *   A1   AInverse           J0   NoErrors           T
- *   B    Radix                    [Failure]         T0   Underflow
- *   B1   BInverse           J1   NoErrors           T2   ThirtyTwo
- *   B2   RadixD2                  [SeriousDefect]   T5   OneAndHalf
- *   B9   BMinusU2           J2   NoErrors           T7   TwentySeven
- *   C                             [Defect]          T8   TwoForty
- *   C1   CInverse           J3   NoErrors           U    OneUlp
- *   D                             [Flaw]            U0   UnderflowThreshold
- *   D4   FourD              K    PageNo             U1
- *   E0                      L    Milestone          U2
- *   E1                      M                       V
- *   E2   Exp2               N                       V0
- *   E3                      N1                      V8
- *   E5   MinSqEr            O    Zero               V9
- *   E6   SqEr               O1   One                W
- *   E7   MaxSqEr            O2   Two                X
- *   E8                      O3   Three              X1
- *   E9                      O4   Four               X8
- *   F1   MinusOne           O5   Five               X9   Random1
- *   F2   Half               O8   Eight              Y
- *   F3   Third              O9   Nine               Y1
- *   F6                      P    Precision          Y2
- *   F9                      Q                       Y9   Random2
- *   G1   GMult              Q8                      Z
- *   G2   GDiv               Q9                      Z0   PseudoZero
- *   G3   GAddSub            R                       Z1
- *   H                       R1   RMult              Z2
- *   H1   HInverse           R2   RDiv               Z9
- *   I                       R3   RAddSub
- *   IO   NoTrials           R4   RSqrt
- *   I3   IEEE               R9   Random9
- *
- * SqRWrng
- *
- * All the variables in BASIC are true variables and in consequence,
- * the program is more difficult to follow since the "constants" must
- * be determined (the glossary is very helpful).  The Pascal version
- * uses Real constants, but checks are added to ensure that the values
- * are correctly converted by the compiler.
- *
- * The major textual change to the Pascal version apart from the
- * identifiersis that named procedures are used, inserting parameters
- * wherehelpful.  New procedures are also introduced.  The
- * correspondence is as follows:
- *
- *
- * BASIC       Pascal
- * lines
- *
- *   90- 140   Pause
- *  170- 250   Instructions
- *  380- 460   Heading
- *  480- 670   Characteristics
- *  690- 870   History
- * 2940-2950   Random
- * 3710-3740   NewD
- * 4040-4080   DoesYequalX
- * 4090-4110   PrintIfNPositive
- * 4640-4850   TestPartialUnderflow
- *
-*/
-
-#include <stdio.h>
-#include <string.h>
-
-/*
- * To compile this on host using only libm from newlib (and using host libc)
- * do:
- *       gcc -g -DNEED_REENT -DCYGNUS paranoia.c .../newlib-1.6/newlib/libm.a
- */
-
-#ifdef NEED_REENT
-#include <reent.h>
-struct _reent libm_reent = _REENT_INIT(libm_reent);
-struct _reent *_impure_ptr = &libm_reent;
-#endif
-
-#ifndef NOSIGNAL
-#include <signal.h>
-#include <setjmp.h>
-#else   /* NOSIGNAL */
-#define longjmp(e,v)
-#define setjmp(e)       0
-#define jmp_buf  int
-#endif /* NOSIGNAL */
-
-#ifdef SINGLE_PRECISION
-#define FLOAT float
-#define FABS(x) (float)fabs((double)(x))
-#define FLOOR(x) (float)floor((double)(x))
-#define LOG(x) (float)log((double)(x))
-#define POW(x,y) (float)pow((double)(x),(double)(y))
-#define SQRT(x) (float)sqrt((double)(x))
-#else /* !SINGLE_PRECISION */
-#define FLOAT double
-#define FABS(x) fabs(x)
-#define FLOOR(x) floor(x)
-#define LOG(x) log(x)
-#define POW(x,y) pow(x,y)
-#define SQRT(x) sqrt(x)
-#endif /* SINGLE_PRECISION */
-
-jmp_buf ovfl_buf;
-extern double fabs (), floor (), log (), pow (), sqrt ();
-extern void exit ();
-typedef void (*Sig_type) ();
-FLOAT   Sign (), Random ();
-extern void BadCond ();
-extern void SqXMinX ();
-extern void TstCond ();
-extern void notify ();
-extern int read ();
-extern void Characteristics ();
-extern void Heading ();
-extern void History ();
-extern void Instructions ();
-extern void IsYeqX ();
-extern void NewD ();
-extern void Pause ();
-extern void PrintIfNPositive ();
-extern void SR3750 ();
-extern void SR3980 ();
-extern void TstPtUf ();
-
-Sig_type sigsave;
-
-#define KEYBOARD 0
-
-FLOAT   Radix, BInvrse, RadixD2, BMinusU2;
-
-/*Small floating point constants.*/
-FLOAT   Zero = 0.0;
-FLOAT   Half = 0.5;
-FLOAT   One = 1.0;
-FLOAT   Two = 2.0;
-FLOAT   Three = 3.0;
-FLOAT   Four = 4.0;
-FLOAT   Five = 5.0;
-FLOAT   Eight = 8.0;
-FLOAT   Nine = 9.0;
-FLOAT   TwentySeven = 27.0;
-FLOAT   ThirtyTwo = 32.0;
-FLOAT   TwoForty = 240.0;
-FLOAT   MinusOne = -1.0;
-FLOAT   OneAndHalf = 1.5;
-
-/*Integer constants*/
-int     NoTrials = 20;          /*Number of tests for commutativity. */
-#define False 0
-#define True 1
-
-/*
- * Definitions for declared types
- *      Guard == (Yes, No);
- *      Rounding == (Chopped, Rounded, Other);
- *      Message == packed array [1..40] of char;
- *      Class == (Flaw, Defect, Serious, Failure);
- */
-#define Yes 1
-#define No  0
-#define Chopped 2
-#define Rounded 1
-#define Other   0
-#define Flaw    3
-#define Defect  2
-#define Serious 1
-#define Failure 0
-typedef int Guard, Rounding, Class;
-typedef char Message;
-
-/* Declarations of Variables */
-int     Indx;
-char    ch[8];
-FLOAT   AInvrse, A1;
-FLOAT   C, CInvrse;
-FLOAT   D, FourD;
-FLOAT   E0, E1, Exp2, E3, MinSqEr;
-FLOAT   SqEr, MaxSqEr, E9;
-FLOAT   Third;
-FLOAT   F6, F9;
-FLOAT   H, HInvrse;
-int     I;
-FLOAT   StickyBit, J;
-FLOAT   MyZero;
-FLOAT   Precision;
-FLOAT   Q, Q9;
-FLOAT   R, Random9;
-FLOAT   T, Underflow, S;
-FLOAT   OneUlp, UfThold, U1, U2;
-FLOAT   V, V0, V9;
-FLOAT   W;
-FLOAT   X, X1, X2, X8, Random1;
-FLOAT   Y, Y1, Y2, Random2;
-FLOAT   Z, PseudoZero, Z1, Z2, Z9;
-int     ErrCnt[4];
-int     fpecount;
-int     Milestone;
-int     PageNo;
-int     M, N, N1;
-Guard   GMult, GDiv, GAddSub;
-Rounding RMult, RDiv, RAddSub, RSqrt;
-int     Break, Done, NotMonot, Monot, Anomaly, IEEE, SqRWrng, UfNGrad;
-
-/* Computed constants.
- *   U1 gap below 1.0, i.e, 1.0 - U1 is next number below 1.0
- *   U2 gap above 1.0, i.e, 1.0 + U2 is next number above 1.0
- */
-
-int     batchmode;              /* global batchmode test */
-
-/* program name and version variables and macro */
-char   *temp;
-char   *program_name;
-char   *program_vers;
-
-#ifndef VERSION
-#define VERSION "1.1 [cygnus]"
-#endif /* VERSION */
-
-#define basename(cp)    ((temp=(char *)strrchr((cp), '/')) ? temp+1 : (cp))
-
-#ifndef BATCHMODE
-# ifdef CYGNUS
-#  define BATCHMODE
-# endif
-#endif
-
-/* floating point exception receiver */
-void
-_sigfpe (x)
-int x;
-{
-    fpecount++;
-    printf ("\n* * * FLOATING-POINT ERROR %d * * *\n", x);
-    fflush (stdout);
-    if (sigsave) {
-#ifndef NOSIGNAL
-        signal (SIGFPE, sigsave);
-#endif /* NOSIGNAL */
-        sigsave = 0;
-        longjmp (ovfl_buf, 1);
-    }
-    exit (1);
-}
-
-#ifdef NOMAIN
-#define main paranoia
-#endif
-
-int
-main (argc, argv)
-int argc;
-char **argv;
-{
-    /* First two assignments use integer right-hand sides. */
-    Zero = 0;
-    One = 1;
-    Two = One + One;
-    Three = Two + One;
-    Four = Three + One;
-    Five = Four + One;
-    Eight = Four + Four;
-    Nine = Three * Three;
-    TwentySeven = Nine * Three;
-    ThirtyTwo = Four * Eight;
-    TwoForty = Four * Five * Three * Four;
-    MinusOne = -One;
-    Half = One / Two;
-    OneAndHalf = One + Half;
-    ErrCnt[Failure] = 0;
-    ErrCnt[Serious] = 0;
-    ErrCnt[Defect] = 0;
-    ErrCnt[Flaw] = 0;
-    PageNo = 1;
-
-#ifdef BATCHMODE
-    batchmode = 1;              /* run test in batchmode? */
-#else /* !BATCHMODE */
-    batchmode = 0;              /* run test interactively */
-#endif /* BATCHMODE */
-
-/*
-    program_name = basename (argv[0]);
-*/
-    program_vers = VERSION;
-
-    printf ("%s version %s\n", "Paranoia", program_vers);
-
-    /*=============================================*/
-    Milestone = 0;
-    /*=============================================*/
-#ifndef NOSIGNAL
-    signal (SIGFPE, _sigfpe);
-#endif
-
-    if (!batchmode) {
-        Instructions ();
-        Pause ();
-        Heading ();
-        Instructions ();
-        Pause ();
-        Heading ();
-        Pause ();
-        Characteristics ();
-        Pause ();
-        History ();
-        Pause ();
-    }
-
-    /*=============================================*/
-    Milestone = 7;
-    /*=============================================*/
-    printf ("Program is now RUNNING tests on small integers:\n");
-    TstCond (Failure, (Zero + Zero == Zero) && (One - One == Zero)
-        && (One > Zero) && (One + One == Two),
-        "0+0 != 0, 1-1 != 0, 1 <= 0, or 1+1 != 2");
-    Z = -Zero;
-    if (Z != 0.0) {
-        ErrCnt[Failure] = ErrCnt[Failure] + 1;
-        printf ("Comparison alleges that -0.0 is Non-zero!\n");
-        U1 = 0.001;
-        Radix = 1;
-        TstPtUf ();
-    }
-    TstCond (Failure, (Three == Two + One) && (Four == Three + One)
-        && (Four + Two * (-Two) == Zero)
-        && (Four - Three - One == Zero),
-        "3 != 2+1, 4 != 3+1, 4+2*(-2) != 0, or 4-3-1 != 0");
-    TstCond (Failure, (MinusOne == (0 - One))
-        && (MinusOne + One == Zero) && (One + MinusOne == Zero)
-        && (MinusOne + FABS (One) == Zero)
-        && (MinusOne + MinusOne * MinusOne == Zero),
-        "-1+1 != 0, (-1)+abs(1) != 0, or -1+(-1)*(-1) != 0");
-    TstCond (Failure, Half + MinusOne + Half == Zero,
-        "1/2 + (-1) + 1/2 != 0");
-    /*=============================================*/
-    Milestone = 10;
-    /*=============================================*/
-    TstCond (Failure, (Nine == Three * Three)
-        && (TwentySeven == Nine * Three) && (Eight == Four + Four)
-        && (ThirtyTwo == Eight * Four)
-        && (ThirtyTwo - TwentySeven - Four - One == Zero),
-        "9 != 3*3, 27 != 9*3, 32 != 8*4, or 32-27-4-1 != 0");
-    TstCond (Failure, (Five == Four + One) &&
-        (TwoForty == Four * Five * Three * Four)
-        && (TwoForty / Three - Four * Four * Five == Zero)
-        && (TwoForty / Four - Five * Three * Four == Zero)
-        && (TwoForty / Five - Four * Three * Four == Zero),
-        "5 != 4+1, 240/3 != 80, 240/4 != 60, or 240/5 != 48");
-    if (ErrCnt[Failure] == 0) {
-        printf ("-1, 0, 1/2, 1, 2, 3, 4, 5, 9, 27, 32 & 240 are O.K.\n");
-        printf ("\n");
-    }
-    printf ("Searching for Radix and Precision.\n");
-    W = One;
-    do {
-        W = W + W;
-        Y = W + One;
-        Z = Y - W;
-        Y = Z - One;
-    }
-    while (MinusOne + FABS (Y) < Zero);
-    /*.. now W is just big enough that |((W+1)-W)-1| >= 1 ...*/
-    Precision = Zero;
-    Y = One;
-    do {
-        Radix = W + Y;
-        Y = Y + Y;
-        Radix = Radix - W;
-    }
-    while (Radix == Zero);
-    if (Radix < Two)
-        Radix = One;
-    printf ("Radix = %f .\n", Radix);
-    if (Radix != 1) {
-        W = One;
-        do {
-            Precision = Precision + One;
-            W = W * Radix;
-            Y = W + One;
-        }
-        while ((Y - W) == One);
-    }
-    /*... now W == Radix^Precision is barely too big to satisfy (W+1)-W == 1
-                                                      ...*/
-    U1 = One / W;
-    U2 = Radix * U1;
-    printf ("Closest relative separation found is U1 = %.7e .\n\n", U1);
-    printf ("Recalculating radix and precision\n ");
-
-    /*save old values*/
-    E0 = Radix;
-    E1 = U1;
-    E9 = U2;
-    E3 = Precision;
-
-    X = Four / Three;
-    Third = X - One;
-    F6 = Half - Third;
-    X = F6 + F6;
-    X = FABS (X - Third);
-    if (X < U2)
-        X = U2;
-
-    /*... now X = (unknown no.) ulps of 1+...*/
-    do {
-        U2 = X;
-        Y = Half * U2 + ThirtyTwo * U2 * U2;
-        Y = One + Y;
-        X = Y - One;
-    }
-    while (!((U2 <= X) || (X <= Zero)));
-
-    /*... now U2 == 1 ulp of 1 + ... */
-    X = Two / Three;
-    F6 = X - Half;
-    Third = F6 + F6;
-    X = Third - Half;
-    X = FABS (X + F6);
-    if (X < U1)
-        X = U1;
-
-    /*... now  X == (unknown no.) ulps of 1 -... */
-    do {
-        U1 = X;
-        Y = Half * U1 + ThirtyTwo * U1 * U1;
-        Y = Half - Y;
-        X = Half + Y;
-        Y = Half - X;
-        X = Half + Y;
-    }
-    while (!((U1 <= X) || (X <= Zero)));
-    /*... now U1 == 1 ulp of 1 - ... */
-    if (U1 == E1)
-        printf ("confirms closest relative separation U1 .\n");
-    else
-        printf ("gets better closest relative separation U1 = %.7e .\n", U1);
-    W = One / U1;
-    F9 = (Half - U1) + Half;
-    Radix = FLOOR (0.01 + U2 / U1);
-    if (Radix == E0)
-        printf ("Radix confirmed.\n");
-    else
-        printf ("MYSTERY: recalculated Radix = %.7e .\n", Radix);
-    TstCond (Defect, Radix <= Eight + Eight,
-        "Radix is too big: roundoff problems");
-    TstCond (Flaw, (Radix == Two) || (Radix == 10)
-        || (Radix == One), "Radix is not as good as 2 or 10");
-    /*=============================================*/
-    Milestone = 20;
-    /*=============================================*/
-    TstCond (Failure, F9 - Half < Half,
-        "(1-U1)-1/2 < 1/2 is FALSE, prog. fails?");
-    X = F9;
-    I = 1;
-    Y = X - Half;
-    Z = Y - Half;
-    TstCond (Failure, (X != One)
-        || (Z == Zero), "Comparison is fuzzy,X=1 but X-1/2-1/2 != 0");
-    X = One + U2;
-    I = 0;
-    /*=============================================*/
-    Milestone = 25;
-    /*=============================================*/
-    /*... BMinusU2 = nextafter(Radix, 0) */
-    BMinusU2 = Radix - One;
-    BMinusU2 = (BMinusU2 - U2) + One;
-    /* Purify Integers */
-    if (Radix != One) {
-        X = -TwoForty * LOG (U1) / LOG (Radix);
-        Y = FLOOR (Half + X);
-        if (FABS (X - Y) * Four < One)
-            X = Y;
-        Precision = X / TwoForty;
-        Y = FLOOR (Half + Precision);
-        if (FABS (Precision - Y) * TwoForty < Half)
-            Precision = Y;
-    }
-    if ((Precision != FLOOR (Precision)) || (Radix == One)) {
-        printf ("Precision cannot be characterized by an Integer number\n");
-        printf ("of significant digits but, by itself, this is a minor flaw.\n");
-    }
-    if (Radix == One)
-        printf ("logarithmic encoding has precision characterized solely by U1.\n");
-    else
-        printf ("The number of significant digits of the Radix is %f .\n",
-            Precision);
-    TstCond (Serious, U2 * Nine * Nine * TwoForty < One,
-        "Precision worse than 5 decimal figures  ");
-    /*=============================================*/
-    Milestone = 30;
-    /*=============================================*/
-    /* Test for extra-precise subepressions */
-    X = FABS (((Four / Three - One) - One / Four) * Three - One / Four);
-    do {
-        Z2 = X;
-        X = (One + (Half * Z2 + ThirtyTwo * Z2 * Z2)) - One;
-    }
-    while (!((Z2 <= X) || (X <= Zero)));
-    X = Y = Z = FABS ((Three / Four - Two / Three) * Three - One / Four);
-    do {
-        Z1 = Z;
-        Z = (One / Two - ((One / Two - (Half * Z1 + ThirtyTwo * Z1 * Z1))
-                + One / Two)) + One / Two;
-    }
-    while (!((Z1 <= Z) || (Z <= Zero)));
-    do {
-        do {
-            Y1 = Y;
-            Y = (Half - ((Half - (Half * Y1 + ThirtyTwo * Y1 * Y1)) + Half
-                )) + Half;
-        }
-        while (!((Y1 <= Y) || (Y <= Zero)));
-        X1 = X;
-        X = ((Half * X1 + ThirtyTwo * X1 * X1) - F9) + F9;
-    }
-    while (!((X1 <= X) || (X <= Zero)));
-    if ((X1 != Y1) || (X1 != Z1)) {
-        BadCond (Serious, "Disagreements among the values X1, Y1, Z1,\n");
-        printf ("respectively  %.7e,  %.7e,  %.7e,\n", X1, Y1, Z1);
-        printf ("are symptoms of inconsistencies introduced\n");
-        printf ("by extra-precise evaluation of arithmetic subexpressions.\n");
-        notify ("Possibly some part of this");
-        if ((X1 == U1) || (Y1 == U1) || (Z1 == U1))
-            printf (
-                "That feature is not tested further by this program.\n");
-    } else {
-        if ((Z1 != U1) || (Z2 != U2)) {
-            if ((Z1 >= U1) || (Z2 >= U2)) {
-                BadCond (Failure, "");
-                notify ("Precision");
-                printf ("\tU1 = %.7e, Z1 - U1 = %.7e\n", U1, Z1 - U1);
-                printf ("\tU2 = %.7e, Z2 - U2 = %.7e\n", U2, Z2 - U2);
-            } else {
-                if ((Z1 <= Zero) || (Z2 <= Zero)) {
-                    printf ("Because of unusual Radix = %f", Radix);
-                    printf (", or exact rational arithmetic a result\n");
-                    printf ("Z1 = %.7e, or Z2 = %.7e ", Z1, Z2);
-                    notify ("of an\nextra-precision");
-                }
-                if (Z1 != Z2 || Z1 > Zero) {
-                    X = Z1 / U1;
-                    Y = Z2 / U2;
-                    if (Y > X)
-                        X = Y;
-                    Q = -LOG (X);
-                    printf ("Some subexpressions appear to be calculated extra\n");
-                    printf ("precisely with about %g extra B-digits, i.e.\n",
-                        (Q / LOG (Radix)));
-                    printf ("roughly %g extra significant decimals.\n",
-                        Q / LOG (10.));
-                }
-                printf ("That feature is not tested further by this program.\n");
-            }
-        }
-    }
-    Pause ();
-    /*=============================================*/
-    Milestone = 35;
-    /*=============================================*/
-    if (Radix >= Two) {
-        X = W / (Radix * Radix);
-        Y = X + One;
-        Z = Y - X;
-        T = Z + U2;
-        X = T - Z;
-        TstCond (Failure, X == U2,
-            "Subtraction is not normalized X=Y,X+Z != Y+Z!");
-        if (X == U2)
-            printf (
-                "Subtraction appears to be normalized, as it should be.");
-    }
-    printf ("\nChecking for guard digit in *, /, and -.\n");
-    Y = F9 * One;
-    Z = One * F9;
-    X = F9 - Half;
-    Y = (Y - Half) - X;
-    Z = (Z - Half) - X;
-    X = One + U2;
-    T = X * Radix;
-    R = Radix * X;
-    X = T - Radix;
-    X = X - Radix * U2;
-    T = R - Radix;
-    T = T - Radix * U2;
-    X = X * (Radix - One);
-    T = T * (Radix - One);
-    if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero))
-        GMult = Yes;
-    else {
-        GMult = No;
-        TstCond (Serious, False,
-            "* lacks a Guard Digit, so 1*X != X");
-    }
-    Z = Radix * U2;
-    X = One + Z;
-    Y = FABS ((X + Z) - X * X) - U2;
-    X = One - U2;
-    Z = FABS ((X - U2) - X * X) - U1;
-    TstCond (Failure, (Y <= Zero)
-        && (Z <= Zero), "* gets too many final digits wrong.\n");
-    Y = One - U2;
-    X = One + U2;
-    Z = One / Y;
-    Y = Z - X;
-    X = One / Three;
-    Z = Three / Nine;
-    X = X - Z;
-    T = Nine / TwentySeven;
-    Z = Z - T;
-    TstCond (Defect, X == Zero && Y == Zero && Z == Zero,
-        "Division lacks a Guard Digit, so error can exceed 1 ulp\n\
-or  1/3  and  3/9  and  9/27 may disagree");
-    Y = F9 / One;
-    X = F9 - Half;
-    Y = (Y - Half) - X;
-    X = One + U2;
-    T = X / One;
-    X = T - X;
-    if ((X == Zero) && (Y == Zero) && (Z == Zero))
-        GDiv = Yes;
-    else {
-        GDiv = No;
-        TstCond (Serious, False,
-            "Division lacks a Guard Digit, so X/1 != X");
-    }
-    X = One / (One + U2);
-    Y = X - Half - Half;
-    TstCond (Serious, Y < Zero,
-        "Computed value of 1/1.000..1 >= 1");
-    X = One - U2;
-    Y = One + Radix * U2;
-    Z = X * Radix;
-    T = Y * Radix;
-    R = Z / Radix;
-    StickyBit = T / Radix;
-    X = R - X;
-    Y = StickyBit - Y;
-    TstCond (Failure, X == Zero && Y == Zero,
-        "* and/or / gets too many last digits wrong");
-    Y = One - U1;
-    X = One - F9;
-    Y = One - Y;
-    T = Radix - U2;
-    Z = Radix - BMinusU2;
-    T = Radix - T;
-    if ((X == U1) && (Y == U1) && (Z == U2) && (T == U2))
-        GAddSub = Yes;
-    else {
-        GAddSub = No;
-        TstCond (Serious, False,
-            "- lacks Guard Digit, so cancellation is obscured");
-    }
-    if (F9 != One && F9 - One >= Zero) {
-        BadCond (Serious, "comparison alleges  (1-U1) < 1  although\n");
-        printf ("  subtraction yields  (1-U1) - 1 = 0 , thereby vitiating\n");
-        printf ("  such precautions against division by zero as\n");
-        printf ("  ...  if (X == 1.0) {.....} else {.../(X-1.0)...}\n");
-    }
-    if (GMult == Yes && GDiv == Yes && GAddSub == Yes)
-        printf (
-            "     *, /, and - appear to have guard digits, as they should.\n");
-    /*=============================================*/
-    Milestone = 40;
-    /*=============================================*/
-    Pause ();
-    printf ("Checking rounding on multiply, divide and add/subtract.\n");
-    RMult = Other;
-    RDiv = Other;
-    RAddSub = Other;
-    RadixD2 = Radix / Two;
-    A1 = Two;
-    Done = False;
-    do {
-        AInvrse = Radix;
-        do {
-            X = AInvrse;
-            AInvrse = AInvrse / A1;
-        }
-        while (!(FLOOR (AInvrse) != AInvrse));
-        Done = (X == One) || (A1 > Three);
-        if (!Done)
-            A1 = Nine + One;
-    }
-    while (!(Done));
-    if (X == One)
-        A1 = Radix;
-    AInvrse = One / A1;
-    X = A1;
-    Y = AInvrse;
-    Done = False;
-    do {
-        Z = X * Y - Half;
-        TstCond (Failure, Z == Half,
-            "X * (1/X) differs from 1");
-        Done = X == Radix;
-        X = Radix;
-        Y = One / X;
-    }
-    while (!(Done));
-    Y2 = One + U2;
-    Y1 = One - U2;
-    X = OneAndHalf - U2;
-    Y = OneAndHalf + U2;
-    Z = (X - U2) * Y2;
-    T = Y * Y1;
-    Z = Z - X;
-    T = T - X;
-    X = X * Y2;
-    Y = (Y + U2) * Y1;
-    X = X - OneAndHalf;
-    Y = Y - OneAndHalf;
-    if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T <= Zero)) {
-        X = (OneAndHalf + U2) * Y2;
-        Y = OneAndHalf - U2 - U2;
-        Z = OneAndHalf + U2 + U2;
-        T = (OneAndHalf - U2) * Y1;
-        X = X - (Z + U2);
-        StickyBit = Y * Y1;
-        S = Z * Y2;
-        T = T - Y;
-        Y = (U2 - Y) + StickyBit;
-        Z = S - (Z + U2 + U2);
-        StickyBit = (Y2 + U2) * Y1;
-        Y1 = Y2 * Y1;
-        StickyBit = StickyBit - Y2;
-        Y1 = Y1 - Half;
-        if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero)
-            && (StickyBit == Zero) && (Y1 == Half)) {
-            RMult = Rounded;
-            printf ("Multiplication appears to round correctly.\n");
-        } else if ((X + U2 == Zero) && (Y < Zero) && (Z + U2 == Zero)
-                && (T < Zero) && (StickyBit + U2 == Zero)
-            && (Y1 < Half)) {
-            RMult = Chopped;
-            printf ("Multiplication appears to chop.\n");
-        } else
-            printf ("* is neither chopped nor correctly rounded.\n");
-        if ((RMult == Rounded) && (GMult == No))
-            notify ("Multiplication");
-    } else
-        printf ("* is neither chopped nor correctly rounded.\n");
-    /*=============================================*/
-    Milestone = 45;
-    /*=============================================*/
-    Y2 = One + U2;
-    Y1 = One - U2;
-    Z = OneAndHalf + U2 + U2;
-    X = Z / Y2;
-    T = OneAndHalf - U2 - U2;
-    Y = (T - U2) / Y1;
-    Z = (Z + U2) / Y2;
-    X = X - OneAndHalf;
-    Y = Y - T;
-    T = T / Y1;
-    Z = Z - (OneAndHalf + U2);
-    T = (U2 - OneAndHalf) + T;
-    if (!((X > Zero) || (Y > Zero) || (Z > Zero) || (T > Zero))) {
-        X = OneAndHalf / Y2;
-        Y = OneAndHalf - U2;
-        Z = OneAndHalf + U2;
-        X = X - Y;
-        T = OneAndHalf / Y1;
-        Y = Y / Y1;
-        T = T - (Z + U2);
-        Y = Y - Z;
-        Z = Z / Y2;
-        Y1 = (Y2 + U2) / Y2;
-        Z = Z - OneAndHalf;
-        Y2 = Y1 - Y2;
-        Y1 = (F9 - U1) / F9;
-        if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero)
-            && (Y2 == Zero) && (Y2 == Zero)
-            && (Y1 - Half == F9 - Half)) {
-            RDiv = Rounded;
-            printf ("Division appears to round correctly.\n");
-            if (GDiv == No)
-                notify ("Division");
-        } else if ((X < Zero) && (Y < Zero) && (Z < Zero) && (T < Zero)
-            && (Y2 < Zero) && (Y1 - Half < F9 - Half)) {
-            RDiv = Chopped;
-            printf ("Division appears to chop.\n");
-        }
-    }
-    if (RDiv == Other)
-        printf ("/ is neither chopped nor correctly rounded.\n");
-    BInvrse = One / Radix;
-    TstCond (Failure, (BInvrse * Radix - Half == Half),
-        "Radix * ( 1 / Radix ) differs from 1");
-    /*=============================================*/
-    Milestone = 50;
-    /*=============================================*/
-    TstCond (Failure, ((F9 + U1) - Half == Half)
-        && ((BMinusU2 + U2) - One == Radix - One),
-        "Incomplete carry-propagation in Addition");
-    X = One - U1 * U1;
-    Y = One + U2 * (One - U2);
-    Z = F9 - Half;
-    X = (X - Half) - Z;
-    Y = Y - One;
-    if ((X == Zero) && (Y == Zero)) {
-        RAddSub = Chopped;
-        printf ("Add/Subtract appears to be chopped.\n");
-    }
-    if (GAddSub == Yes) {
-        X = (Half + U2) * U2;
-        Y = (Half - U2) * U2;
-        X = One + X;
-        Y = One + Y;
-        X = (One + U2) - X;
-        Y = One - Y;
-        if ((X == Zero) && (Y == Zero)) {
-            X = (Half + U2) * U1;
-            Y = (Half - U2) * U1;
-            X = One - X;
-            Y = One - Y;
-            X = F9 - X;
-            Y = One - Y;
-            if ((X == Zero) && (Y == Zero)) {
-                RAddSub = Rounded;
-                printf ("Addition/Subtraction appears to round correctly.\n");
-                if (GAddSub == No)
-                    notify ("Add/Subtract");
-            } else
-                printf ("Addition/Subtraction neither rounds nor chops.\n");
-        } else
-            printf ("Addition/Subtraction neither rounds nor chops.\n");
-    } else
-        printf ("Addition/Subtraction neither rounds nor chops.\n");
-    S = One;
-    X = One + Half * (One + Half);
-    Y = (One + U2) * Half;
-    Z = X - Y;
-    T = Y - X;
-    StickyBit = Z + T;
-    if (StickyBit != Zero) {
-        S = Zero;
-        BadCond (Flaw, "(X - Y) + (Y - X) is non zero!\n");
-    }
-    StickyBit = Zero;
-    if ((GMult == Yes) && (GDiv == Yes) && (GAddSub == Yes)
-        && (RMult == Rounded) && (RDiv == Rounded)
-        && (RAddSub == Rounded) && (FLOOR (RadixD2) == RadixD2)) {
-        printf ("Checking for sticky bit.\n");
-        X = (Half + U1) * U2;
-        Y = Half * U2;
-        Z = One + Y;
-        T = One + X;
-        if ((Z - One <= Zero) && (T - One >= U2)) {
-            Z = T + Y;
-            Y = Z - X;
-            if ((Z - T >= U2) && (Y - T == Zero)) {
-                X = (Half + U1) * U1;
-                Y = Half * U1;
-                Z = One - Y;
-                T = One - X;
-                if ((Z - One == Zero) && (T - F9 == Zero)) {
-                    Z = (Half - U1) * U1;
-                    T = F9 - Z;
-                    Q = F9 - Y;
-                    if ((T - F9 == Zero) && (F9 - U1 - Q == Zero)) {
-                        Z = (One + U2) * OneAndHalf;
-                        T = (OneAndHalf + U2) - Z + U2;
-                        X = One + Half / Radix;
-                        Y = One + Radix * U2;
-                        Z = X * Y;
-                        if (T == Zero && X + Radix * U2 - Z == Zero) {
-                            if (Radix != Two) {
-                                X = Two + U2;
-                                Y = X / Two;
-                                if ((Y - One == Zero))
-                                    StickyBit = S;
-                            } else
-                                StickyBit = S;
-                        }
-                    }
-                }
-            }
-        }
-    }
-    if (StickyBit == One)
-        printf ("Sticky bit apparently used correctly.\n");
-    else
-        printf ("Sticky bit used incorrectly or not at all.\n");
-    TstCond (Flaw, !(GMult == No || GDiv == No || GAddSub == No ||
-            RMult == Other || RDiv == Other || RAddSub == Other),
-        "lack(s) of guard digits or failure(s) to correctly round or chop\n\
-(noted above) count as one flaw in the final tally below");
-    /*=============================================*/
-    Milestone = 60;
-    /*=============================================*/
-    printf ("\n");
-    printf ("Does Multiplication commute?  ");
-    printf ("Testing on %d random pairs.\n", NoTrials);
-    Random9 = SQRT (3.0);
-    Random1 = Third;
-    I = 1;
-    do {
-        X = Random ();
-        Y = Random ();
-        Z9 = Y * X;
-        Z = X * Y;
-        Z9 = Z - Z9;
-        I = I + 1;
-    }
-    while (!((I > NoTrials) || (Z9 != Zero)));
-    if (I == NoTrials) {
-        Random1 = One + Half / Three;
-        Random2 = (U2 + U1) + One;
-        Z = Random1 * Random2;
-        Y = Random2 * Random1;
-        Z9 = (One + Half / Three) * ((U2 + U1) + One) - (One + Half /
-            Three) * ((U2 + U1) + One);
-    }
-    if (!((I == NoTrials) || (Z9 == Zero)))
-        BadCond (Defect, "X * Y == Y * X trial fails.\n");
-    else
-        printf ("     No failures found in %d integer pairs.\n", NoTrials);
-    /*=============================================*/
-    Milestone = 70;
-    /*=============================================*/
-    printf ("\nRunning test of square root(x).\n");
-    TstCond (Failure, (Zero == SQRT (Zero))
-        && (-Zero == SQRT (-Zero))
-        && (One == SQRT (One)), "Square root of 0.0, -0.0 or 1.0 wrong");
-    MinSqEr = Zero;
-    MaxSqEr = Zero;
-    J = Zero;
-    X = Radix;
-    OneUlp = U2;
-    SqXMinX (Serious);
-    X = BInvrse;
-    OneUlp = BInvrse * U1;
-    SqXMinX (Serious);
-    X = U1;
-    OneUlp = U1 * U1;
-    SqXMinX (Serious);
-    if (J != Zero)
-        Pause ();
-    printf ("Testing if sqrt(X * X) == X for %d Integers X.\n", NoTrials);
-    J = Zero;
-    X = Two;
-    Y = Radix;
-    if ((Radix != One))
-        do {
-            X = Y;
-            Y = Radix * Y;
-        }
-        while (!((Y - X >= NoTrials)));
-    OneUlp = X * U2;
-    I = 1;
-    while (I <= NoTrials) {
-        X = X + One;
-        SqXMinX (Defect);
-        if (J > Zero)
-            break;
-        I = I + 1;
-    }
-    printf ("Test for sqrt monotonicity.\n");
-    I = -1;
-    X = BMinusU2;
-    Y = Radix;
-    Z = Radix + Radix * U2;
-    NotMonot = False;
-    Monot = False;
-    while (!(NotMonot || Monot)) {
-        I = I + 1;
-        X = SQRT (X);
-        Q = SQRT (Y);
-        Z = SQRT (Z);
-        if ((X > Q) || (Q > Z))
-            NotMonot = True;
-        else {
-            Q = FLOOR (Q + Half);
-            if ((I > 0) || (Radix == Q * Q))
-                Monot = True;
-            else if (I > 0) {
-                if (I > 1)
-                    Monot = True;
-                else {
-                    Y = Y * BInvrse;
-                    X = Y - U1;
-                    Z = Y + U1;
-                }
-            } else {
-                Y = Q;
-                X = Y - U2;
-                Z = Y + U2;
-            }
-        }
-    }
-    if (Monot)
-        printf ("sqrt has passed a test for Monotonicity.\n");
-    else {
-        BadCond (Defect, "");
-        printf ("sqrt(X) is non-monotonic for X near %.7e .\n", Y);
-    }
-    /*=============================================*/
-    Milestone = 80;
-    /*=============================================*/
-    MinSqEr = MinSqEr + Half;
-    MaxSqEr = MaxSqEr - Half;
-    Y = (SQRT (One + U2) - One) / U2;
-    SqEr = (Y - One) + U2 / Eight;
-    if (SqEr > MaxSqEr)
-        MaxSqEr = SqEr;
-    SqEr = Y + U2 / Eight;
-    if (SqEr < MinSqEr)
-        MinSqEr = SqEr;
-    Y = ((SQRT (F9) - U2) - (One - U2)) / U1;
-    SqEr = Y + U1 / Eight;
-    if (SqEr > MaxSqEr)
-        MaxSqEr = SqEr;
-    SqEr = (Y + One) + U1 / Eight;
-    if (SqEr < MinSqEr)
-        MinSqEr = SqEr;
-    OneUlp = U2;
-    X = OneUlp;
-    for (Indx = 1; Indx <= 3; ++Indx) {
-        Y = SQRT ((X + U1 + X) + F9);
-        Y = ((Y - U2) - ((One - U2) + X)) / OneUlp;
-        Z = ((U1 - X) + F9) * Half * X * X / OneUlp;
-        SqEr = (Y + Half) + Z;
-        if (SqEr < MinSqEr)
-            MinSqEr = SqEr;
-        SqEr = (Y - Half) + Z;
-        if (SqEr > MaxSqEr)
-            MaxSqEr = SqEr;
-        if (((Indx == 1) || (Indx == 3)))
-            X = OneUlp * Sign (X) * FLOOR (Eight / (Nine * SQRT (OneUlp)));
-        else {
-            OneUlp = U1;
-            X = -OneUlp;
-        }
-    }
-    /*=============================================*/
-    Milestone = 85;
-    /*=============================================*/
-    SqRWrng = False;
-    Anomaly = False;
-    RSqrt = Other;              /* ~dgh */
-    if (Radix != One) {
-        printf ("Testing whether sqrt is rounded or chopped.\n");
-        D = FLOOR (Half + POW (Radix, One + Precision - FLOOR (Precision)));
-        /* ... == Radix^(1 + fract) if (Precision == Integer + fract. */
-        X = D / Radix;
-        Y = D / A1;
-        if ((X != FLOOR (X)) || (Y != FLOOR (Y))) {
-            Anomaly = True;
-        } else {
-            X = Zero;
-            Z2 = X;
-            Y = One;
-            Y2 = Y;
-            Z1 = Radix - One;
-            FourD = Four * D;
-            do {
-                if (Y2 > Z2) {
-                    Q = Radix;
-                    Y1 = Y;
-                    do {
-                        X1 = FABS (Q + FLOOR (Half - Q / Y1) * Y1);
-                        Q = Y1;
-                        Y1 = X1;
-                    }
-                    while (!(X1 <= Zero));
-                    if (Q <= One) {
-                        Z2 = Y2;
-                        Z = Y;
-                    }
-                }
-                Y = Y + Two;
-                X = X + Eight;
-                Y2 = Y2 + X;
-                if (Y2 >= FourD)
-                    Y2 = Y2 - FourD;
-            }
-            while (!(Y >= D));
-            X8 = FourD - Z2;
-            Q = (X8 + Z * Z) / FourD;
-            X8 = X8 / Eight;
-            if (Q != FLOOR (Q))
-                Anomaly = True;
-            else {
-                Break = False;
-                do {
-                    X = Z1 * Z;
-                    X = X - FLOOR (X / Radix) * Radix;
-                    if (X == One)
-                        Break = True;
-                    else
-                        Z1 = Z1 - One;
-                }
-                while (!(Break || (Z1 <= Zero)));
-                if ((Z1 <= Zero) && (!Break))
-                    Anomaly = True;
-                else {
-                    if (Z1 > RadixD2)
-                        Z1 = Z1 - Radix;
-                    do {
-                        NewD ();
-                    }
-                    while (!(U2 * D >= F9));
-                    if (D * Radix - D != W - D)
-                        Anomaly = True;
-                    else {
-                        Z2 = D;
-                        I = 0;
-                        Y = D + (One + Z) * Half;
-                        X = D + Z + Q;
-                        SR3750 ();
-                        Y = D + (One - Z) * Half + D;
-                        X = D - Z + D;
-                        X = X + Q + X;
-                        SR3750 ();
-                        NewD ();
-                        if (D - Z2 != W - Z2)
-                            Anomaly = True;
-                        else {
-                            Y = (D - Z2) + (Z2 + (One - Z) * Half);
-                            X = (D - Z2) + (Z2 - Z + Q);
-                            SR3750 ();
-                            Y = (One + Z) * Half;
-                            X = Q;
-                            SR3750 ();
-                            if (I == 0)
-                                Anomaly = True;
-                        }
-                    }
-                }
-            }
-        }
-        if ((I == 0) || Anomaly) {
-            BadCond (Failure, "Anomalous arithmetic with Integer < ");
-            printf ("Radix^Precision = %.7e\n", W);
-            printf (" fails test whether sqrt rounds or chops.\n");
-            SqRWrng = True;
-        }
-    }
-    if (!Anomaly) {
-        if (!((MinSqEr < Zero) || (MaxSqEr > Zero))) {
-            RSqrt = Rounded;
-            printf ("Square root appears to be correctly rounded.\n");
-        } else {
-            if ((MaxSqEr + U2 > U2 - Half) || (MinSqEr > Half)
-                || (MinSqEr + Radix < Half))
-                SqRWrng = True;
-            else {
-                RSqrt = Chopped;
-                printf ("Square root appears to be chopped.\n");
-            }
-        }
-    }
-    if (SqRWrng) {
-        printf ("Square root is neither chopped nor correctly rounded.\n");
-        printf ("Observed errors run from %.7e ", MinSqEr - Half);
-        printf ("to %.7e ulps.\n", Half + MaxSqEr);
-        TstCond (Serious, MaxSqEr - MinSqEr < Radix * Radix,
-            "sqrt gets too many last digits wrong");
-    }
-    /*=============================================*/
-    Milestone = 90;
-    /*=============================================*/
-    Pause ();
-    printf ("Testing powers Z^i for small Integers Z and i.\n");
-    N = 0;
-    /* ... test powers of zero. */
-    I = 0;
-    Z = -Zero;
-    M = 3;
-    Break = False;
-    do {
-        X = One;
-        SR3980 ();
-        if (I <= 10) {
-            I = 1023;
-            SR3980 ();
-        }
-        if (Z == MinusOne)
-            Break = True;
-        else {
-            Z = MinusOne;
-            /* .. if(-1)^N is invalid, replace MinusOne by One. */
-            I = -4;
-        }
-    }
-    while (!Break);
-    PrintIfNPositive ();
-    N1 = N;
-    N = 0;
-    Z = A1;
-    M = (int) FLOOR (Two * LOG (W) / LOG (A1));
-    Break = False;
-    do {
-        X = Z;
-        I = 1;
-        SR3980 ();
-        if (Z == AInvrse)
-            Break = True;
-        else
-            Z = AInvrse;
-    }
-    while (!(Break));
-    /*=============================================*/
-    Milestone = 100;
-    /*=============================================*/
-    /*  Powers of Radix have been tested, */
-    /*         next try a few primes     */
-    M = NoTrials;
-    Z = Three;
-    do {
-        X = Z;
-        I = 1;
-        SR3980 ();
-        do {
-            Z = Z + Two;
-        }
-        while (Three * FLOOR (Z / Three) == Z);
-    }
-    while (Z < Eight * Three);
-    if (N > 0) {
-        printf ("Errors like this may invalidate financial calculations\n");
-        printf ("\tinvolving interest rates.\n");
-    }
-    PrintIfNPositive ();
-    N += N1;
-    if (N == 0)
-        printf ("... no discrepancies found.\n");
-    if (N > 0)
-        Pause ();
-    else
-        printf ("\n");
-    /*=============================================*/
-    Milestone = 110;
-    /*=============================================*/
-    printf ("Seeking Underflow thresholds UfThold and E0.\n");
-    D = U1;
-    if (Precision != FLOOR (Precision)) {
-        D = BInvrse;
-        X = Precision;
-        do {
-            D = D * BInvrse;
-            X = X - One;
-        }
-        while (X > Zero);
-    }
-    Y = One;
-    Z = D;
-    /* ... D is power of 1/Radix < 1. */
-    do {
-        C = Y;
-        Y = Z;
-        Z = Y * Y;
-    }
-    while ((Y > Z) && (Z + Z > Z));
-    Y = C;
-    Z = Y * D;
-    do {
-        C = Y;
-        Y = Z;
-        Z = Y * D;
-    }
-    while ((Y > Z) && (Z + Z > Z));
-    if (Radix < Two)
-        HInvrse = Two;
-    else
-        HInvrse = Radix;
-    H = One / HInvrse;
-    /* ... 1/HInvrse == H == Min(1/Radix, 1/2) */
-    CInvrse = One / C;
-    E0 = C;
-    Z = E0 * H;
-    /* ...1/Radix^(BIG Integer) << 1 << CInvrse == 1/C */
-    do {
-        Y = E0;
-        E0 = Z;
-        Z = E0 * H;
-    }
-    while ((E0 > Z) && (Z + Z > Z));
-    UfThold = E0;
-    E1 = Zero;
-    Q = Zero;
-    E9 = U2;
-    S = One + E9;
-    D = C * S;
-    if (D <= C) {
-        E9 = Radix * U2;
-        S = One + E9;
-        D = C * S;
-        if (D <= C) {
-            BadCond (Failure, "multiplication gets too many last digits wrong.\n");
-            Underflow = E0;
-            Y1 = Zero;
-            PseudoZero = Z;
-            Pause ();
-        }
-    } else {
-        Underflow = D;
-        PseudoZero = Underflow * H;
-        UfThold = Zero;
-        do {
-            Y1 = Underflow;
-            Underflow = PseudoZero;
-            if (E1 + E1 <= E1) {
-                Y2 = Underflow * HInvrse;
-                E1 = FABS (Y1 - Y2);
-                Q = Y1;
-                if ((UfThold == Zero) && (Y1 != Y2))
-                    UfThold = Y1;
-            }
-            PseudoZero = PseudoZero * H;
-        }
-        while ((Underflow > PseudoZero)
-            && (PseudoZero + PseudoZero > PseudoZero));
-    }
-    /* Comment line 4530 .. 4560 */
-    if (PseudoZero != Zero) {
-        printf ("\n");
-        Z = PseudoZero;
-        /* ... Test PseudoZero for "phoney- zero" violates */
-        /* ... PseudoZero < Underflow or PseudoZero < PseudoZero + PseudoZero
-                   ... */
-        if (PseudoZero <= Zero) {
-            BadCond (Failure, "Positive expressions can underflow to an\n");
-            printf ("allegedly negative value\n");
-            printf ("PseudoZero that prints out as: %g .\n", PseudoZero);
-            X = -PseudoZero;
-            if (X <= Zero) {
-                printf ("But -PseudoZero, which should be\n");
-                printf ("positive, isn't; it prints out as  %g .\n", X);
-            }
-        } else {
-            BadCond (Flaw, "Underflow can stick at an allegedly positive\n");
-            printf ("value PseudoZero that prints out as %g .\n", PseudoZero);
-        }
-        TstPtUf ();
-    }
-    /*=============================================*/
-    Milestone = 120;
-    /*=============================================*/
-    if (CInvrse * Y > CInvrse * Y1) {
-        S = H * S;
-        E0 = Underflow;
-    }
-    if (!((E1 == Zero) || (E1 == E0))) {
-        BadCond (Defect, "");
-        if (E1 < E0) {
-            printf ("Products underflow at a higher");
-            printf (" threshold than differences.\n");
-            if (PseudoZero == Zero)
-                E0 = E1;
-        } else {
-            printf ("Difference underflows at a higher");
-            printf (" threshold than products.\n");
-        }
-    }
-    printf ("Smallest strictly positive number found is E0 = %g .\n", E0);
-    Z = E0;
-    TstPtUf ();
-    Underflow = E0;
-    if (N == 1)
-        Underflow = Y;
-    I = 4;
-    if (E1 == Zero)
-        I = 3;
-    if (UfThold == Zero)
-        I = I - 2;
-    UfNGrad = True;
-    switch (I) {
-    case 1:
-        UfThold = Underflow;
-        if ((CInvrse * Q) != ((CInvrse * Y) * S)) {
-            UfThold = Y;
-            BadCond (Failure, "Either accuracy deteriorates as numbers\n");
-            printf ("approach a threshold = %.17e\n", UfThold);;
-            printf (" coming down from %.17e\n", C);
-            printf (" or else multiplication gets too many last digits wrong.\n");
-        }
-        Pause ();
-        break;
-
-    case 2:
-        BadCond (Failure, "Underflow confuses Comparison, which alleges that\n");
-        printf ("Q == Y while denying that |Q - Y| == 0; these values\n");
-        printf ("print out as Q = %.17e, Y = %.17e .\n", Q, Y2);
-        printf ("|Q - Y| = %.17e .\n", FABS (Q - Y2));
-        UfThold = Q;
-        break;
-
-    case 3:
-        X = X;
-        break;
-
-    case 4:
-        if ((Q == UfThold) && (E1 == E0)
-            && (FABS (UfThold - E1 / E9) <= E1)) {
-            UfNGrad = False;
-            printf ("Underflow is gradual; it incurs Absolute Error =\n");
-            printf ("(roundoff in UfThold) < E0.\n");
-            Y = E0 * CInvrse;
-            Y = Y * (OneAndHalf + U2);
-            X = CInvrse * (One + U2);
-            Y = Y / X;
-            IEEE = (Y == E0);
-        }
-    }
-    if (UfNGrad) {
-        printf ("\n");
-        sigsave = _sigfpe;
-        if (setjmp (ovfl_buf)) {
-            printf ("Underflow / UfThold failed!\n");
-            R = H + H;
-        } else
-            R = SQRT (Underflow / UfThold);
-        sigsave = 0;
-        if (R <= H) {
-            Z = R * UfThold;
-            X = Z * (One + R * H * (One + H));
-        } else {
-            Z = UfThold;
-            X = Z * (One + H * H * (One + H));
-        }
-        if (!((X == Z) || (X - Z != Zero))) {
-            BadCond (Flaw, "");
-            printf ("X = %.17e\n\tis not equal to Z = %.17e .\n", X, Z);
-            Z9 = X - Z;
-            printf ("yet X - Z yields %.17e .\n", Z9);
-            printf ("    Should this NOT signal Underflow, ");
-            printf ("this is a SERIOUS DEFECT\nthat causes ");
-            printf ("confusion when innocent statements like\n");;
-            printf ("    if (X == Z)  ...  else");
-            printf ("  ... (f(X) - f(Z)) / (X - Z) ...\n");
-            printf ("encounter Division by Zero although actually\n");
-            sigsave = _sigfpe;
-            if (setjmp (ovfl_buf))
-                printf ("X / Z fails!\n");
-            else
-                printf ("X / Z = 1 + %g .\n", (X / Z - Half) - Half);
-            sigsave = 0;
-        }
-    }
-    printf ("The Underflow threshold is %.17e, %s\n", UfThold,
-        " below which");
-    printf ("calculation may suffer larger Relative error than ");
-    printf ("merely roundoff.\n");
-    Y2 = U1 * U1;
-    Y = Y2 * Y2;
-    Y2 = Y * U1;
-    if (Y2 <= UfThold) {
-        if (Y > E0) {
-            BadCond (Defect, "");
-            I = 5;
-        } else {
-            BadCond (Serious, "");
-            I = 4;
-        }
-        printf ("Range is too narrow; U1^%d Underflows.\n", I);
-    }
-    /*=============================================*/
-    Milestone = 130;
-    /*=============================================*/
-    Y = -FLOOR (Half - TwoForty * LOG (UfThold) / LOG (HInvrse)) / TwoForty;
-    Y2 = Y + Y;
-    printf ("Since underflow occurs below the threshold\n");
-    printf ("UfThold = (%.17e) ^ (%.17e)\nonly underflow ", HInvrse, Y);
-    printf ("should afflict the expression\n\t(%.17e) ^ (%.17e);\n",
-        HInvrse, Y2);
-    printf ("actually calculating yields:");
-    if (setjmp (ovfl_buf)) {
-        sigsave = 0;
-        BadCond (Serious, "trap on underflow.\n");
-    } else {
-        sigsave = _sigfpe;
-        V9 = POW (HInvrse, Y2);
-        sigsave = 0;
-        printf (" %.17e .\n", V9);
-        if (!((V9 >= Zero) && (V9 <= (Radix + Radix + E9) * UfThold))) {
-            BadCond (Serious, "this is not between 0 and underflow\n");
-            printf ("   threshold = %.17e .\n", UfThold);
-        } else if (!(V9 > UfThold * (One + E9)))
-            printf ("This computed value is O.K.\n");
-        else {
-            BadCond (Defect, "this is not between 0 and underflow\n");
-            printf ("   threshold = %.17e .\n", UfThold);
-        }
-    }
-    /*=============================================*/
-    Milestone = 140;
-    /*=============================================*/
-    printf ("\n");
-    /* ...calculate Exp2 == exp(2) == 7.389056099... */
-    X = Zero;
-    I = 2;
-    Y = Two * Three;
-    Q = Zero;
-    N = 0;
-    do {
-        Z = X;
-        I = I + 1;
-        Y = Y / (I + I);
-        R = Y + Q;
-        X = Z + R;
-        Q = (Z - X) + R;
-    }
-    while (X > Z);
-    Z = (OneAndHalf + One / Eight) + X / (OneAndHalf * ThirtyTwo);
-    X = Z * Z;
-    Exp2 = X * X;
-    X = F9;
-    Y = X - U1;
-    printf ("Testing X^((X + 1) / (X - 1)) vs. exp(2) = %.17e as X -> 1.\n",
-        Exp2);
-    for (I = 1;;) {
-        Z = X - BInvrse;
-        Z = (X + One) / (Z - (One - BInvrse));
-        Q = POW (X, Z) - Exp2;
-        if (FABS (Q) > TwoForty * U2) {
-            N = 1;
-            V9 = (X - BInvrse) - (One - BInvrse);
-            BadCond (Defect, "Calculated");
-            printf (" %.17e for\n", POW (X, Z));
-            printf ("\t(1 + (%.17e) ^ (%.17e);\n", V9, Z);
-            printf ("\tdiffers from correct value by %.17e .\n", Q);
-            printf ("\tThis much error may spoil financial\n");
-            printf ("\tcalculations involving tiny interest rates.\n");
-            break;
-        } else {
-            Z = (Y - X) * Two + Y;
-            X = Y;
-            Y = Z;
-            Z = One + (X - F9) * (X - F9);
-            if (Z > One && I < NoTrials)
-                I++;
-            else {
-                if (X > One) {
-                    if (N == 0)
-                        printf ("Accuracy seems adequate.\n");
-                    break;
-                } else {
-                    X = One + U2;
-                    Y = U2 + U2;
-                    Y += X;
-                    I = 1;
-                }
-            }
-        }
-    }
-    /*=============================================*/
-    Milestone = 150;
-    /*=============================================*/
-    printf ("Testing powers Z^Q at four nearly extreme values.\n");
-    N = 0;
-    Z = A1;
-    Q = FLOOR (Half - LOG (C) / LOG (A1));
-    Break = False;
-    do {
-        X = CInvrse;
-        Y = POW (Z, Q);
-        IsYeqX ();
-        Q = -Q;
-        X = C;
-        Y = POW (Z, Q);
-        IsYeqX ();
-        if (Z < One)
-            Break = True;
-        else
-            Z = AInvrse;
-    }
-    while (!(Break));
-    PrintIfNPositive ();
-    if (N == 0)
-        printf (" ... no discrepancies found.\n");
-    printf ("\n");
-
-    /*=============================================*/
-    Milestone = 160;
-    /*=============================================*/
-    Pause ();
-    printf ("Searching for Overflow threshold:\n");
-    printf ("This may generate an error.\n");
-    Y = -CInvrse;
-    V9 = HInvrse * Y;
-    sigsave = _sigfpe;
-    if (setjmp (ovfl_buf)) {
-        I = 0;
-        V9 = Y;
-        goto overflow;
-    }
-    do {
-        V = Y;
-        Y = V9;
-        V9 = HInvrse * Y;
-    }
-    while (V9 < Y);
-    I = 1;
-  overflow:
-    sigsave = 0;
-    Z = V9;
-    printf ("Can `Z = -Y' overflow?\n");
-    printf ("Trying it on Y = %.17e .\n", Y);
-    V9 = -Y;
-    V0 = V9;
-    if (V - Y == V + V0)
-        printf ("Seems O.K.\n");
-    else {
-        printf ("finds a ");
-        BadCond (Flaw, "-(-Y) differs from Y.\n");
-    }
-    if (Z != Y) {
-        BadCond (Serious, "");
-        printf ("overflow past %.17e\n\tshrinks to %.17e .\n", Y, Z);
-    }
-    if (I) {
-        Y = V * (HInvrse * U2 - HInvrse);
-        Z = Y + ((One - HInvrse) * U2) * V;
-        if (Z < V0)
-            Y = Z;
-        if (Y < V0)
-            V = Y;
-        if (V0 - V < V0)
-            V = V0;
-    } else {
-        V = Y * (HInvrse * U2 - HInvrse);
-        V = V + ((One - HInvrse) * U2) * Y;
-    }
-    printf ("Overflow threshold is V  = %.17e .\n", V);
-    if (I)
-        printf ("Overflow saturates at V0 = %.17e .\n", V0);
-    else
-        printf ("There is no saturation value because \
-the system traps on overflow.\n");
-    V9 = V * One;
-    printf ("No Overflow should be signaled for V * 1 = %.17e\n", V9);
-    V9 = V / One;
-    printf ("                           nor for V / 1 = %.17e .\n", V9);
-    printf ("Any overflow signal separating this * from the one\n");
-    printf ("above is a DEFECT.\n");
-    /*=============================================*/
-    Milestone = 170;
-    /*=============================================*/
-    if (!(-V < V && -V0 < V0 && -UfThold < V && UfThold < V)) {
-        BadCond (Failure, "Comparisons involving ");
-        printf ("+-%g, +-%g\nand +-%g are confused by Overflow.",
-            V, V0, UfThold);
-    }
-    /*=============================================*/
-    Milestone = 175;
-    /*=============================================*/
-    printf ("\n");
-    for (Indx = 1; Indx <= 3; ++Indx) {
-        switch (Indx) {
-        case 1:
-            Z = UfThold;
-            break;
-        case 2:
-            Z = E0;
-            break;
-        case 3:
-            Z = PseudoZero;
-            break;
-        }
-        if (Z != Zero) {
-            V9 = SQRT (Z);
-            Y = V9 * V9;
-            if (Y / (One - Radix * E9) < Z
-                || Y > (One + Radix * E9) * Z) {        /* dgh: + E9 --> * E9 */
-                if (V9 > U1)
-                    BadCond (Serious, "");
-                else
-                    BadCond (Defect, "");
-                printf ("Comparison alleges that what prints as Z = %.17e\n", Z);
-                printf (" is too far from sqrt(Z) ^ 2 = %.17e .\n", Y);
-            }
-        }
-    }
-    /*=============================================*/
-    Milestone = 180;
-    /*=============================================*/
-    for (Indx = 1; Indx <= 2; ++Indx) {
-        if (Indx == 1)
-            Z = V;
-        else
-            Z = V0;
-        V9 = SQRT (Z);
-        X = (One - Radix * E9) * V9;
-        V9 = V9 * X;
-        if (((V9 < (One - Two * Radix * E9) * Z) || (V9 > Z))) {
-            Y = V9;
-            if (X < W)
-                BadCond (Serious, "");
-            else
-                BadCond (Defect, "");
-            printf ("Comparison alleges that Z = %17e\n", Z);
-            printf (" is too far from sqrt(Z) ^ 2 (%.17e) .\n", Y);
-        }
-    }
-    /*=============================================*/
-    Milestone = 190;
-    /*=============================================*/
-    Pause ();
-    X = UfThold * V;
-    Y = Radix * Radix;
-    if (X * Y < One || X > Y) {
-        if (X * Y < U1 || X > Y / U1)
-            BadCond (Defect, "Badly");
-        else
-            BadCond (Flaw, "");
-
-        printf (" unbalanced range; UfThold * V = %.17e\n\t%s\n",
-            X, "is too far from 1.\n");
-    }
-    /*=============================================*/
-    Milestone = 200;
-    /*=============================================*/
-    for (Indx = 1; Indx <= 5; ++Indx) {
-        X = F9;
-        switch (Indx) {
-        case 2:
-            X = One + U2;
-            break;
-        case 3:
-            X = V;
-            break;
-        case 4:
-            X = UfThold;
-            break;
-        case 5:
-            X = Radix;
-        }
-        Y = X;
-        sigsave = _sigfpe;
-        if (setjmp (ovfl_buf))
-            printf ("  X / X  traps when X = %g\n", X);
-        else {
-            V9 = (Y / X - Half) - Half;
-            if (V9 == Zero)
-                continue;
-            if (V9 == -U1 && Indx < 5)
-                BadCond (Flaw, "");
-            else
-                BadCond (Serious, "");
-            printf ("  X / X differs from 1 when X = %.17e\n", X);
-            printf ("  instead, X / X - 1/2 - 1/2 = %.17e .\n", V9);
-        }
-        sigsave = 0;
-    }
-    /*=============================================*/
-    Milestone = 210;
-    /*=============================================*/
-    MyZero = Zero;
-    printf ("\n");
-    printf ("What message and/or values does Division by Zero produce?\n");
-#ifndef BATCHMODE
-    printf ("This can interupt your program.  You can ");
-    printf ("skip this part if you wish.\n");
-    printf ("Do you wish to compute 1 / 0? ");
-    fflush (stdout);
-    read (KEYBOARD, ch, 8);
-    if ((ch[0] == 'Y') || (ch[0] == 'y')) {
-#endif /* !BATCHMODE */
-        sigsave = _sigfpe;
-        printf ("    Trying to compute 1 / 0 produces ...");
-        if (!setjmp (ovfl_buf))
-            printf ("  %.7e .\n", One / MyZero);
-        sigsave = 0;
-#ifndef BATCHMODE
-    } else
-        printf ("O.K.\n");
-    printf ("\nDo you wish to compute 0 / 0? ");
-    fflush (stdout);
-    read (KEYBOARD, ch, 80);
-    if ((ch[0] == 'Y') || (ch[0] == 'y')) {
-#endif /* !BATCHMODE */
-        sigsave = _sigfpe;
-        printf ("\n    Trying to compute 0 / 0 produces ...");
-        if (!setjmp (ovfl_buf))
-            printf ("  %.7e .\n", Zero / MyZero);
-        sigsave = 0;
-#ifndef BATCHMODE
-    } else
-        printf ("O.K.\n");
-#endif /* !BATCHMODE */
-    /*=============================================*/
-    Milestone = 220;
-    /*=============================================*/
-
-    Pause ();
-    printf ("\n");
-    {
-        static char *msg[] =
-        {
-            "FAILUREs  encountered =",
-            "SERIOUS DEFECTs  discovered =",
-            "DEFECTs  discovered =",
-            "FLAWs  discovered ="};
-        int     i;
-        for (i = 0; i < 4; i++)
-            if (ErrCnt[i])
-                printf ("The number of  %-29s %d.\n",
-                    msg[i], ErrCnt[i]);
-    }
-
-    printf ("\n");
-    if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[Defect]
-            + ErrCnt[Flaw]) > 0) {
-        if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[
-                    Defect] == 0) && (ErrCnt[Flaw] > 0)) {
-            printf ("The arithmetic diagnosed seems ");
-            printf ("Satisfactory though flawed.\n");
-        }
-        if ((ErrCnt[Failure] + ErrCnt[Serious] == 0)
-            && (ErrCnt[Defect] > 0)) {
-            printf ("The arithmetic diagnosed may be Acceptable\n");
-            printf ("despite inconvenient Defects.\n");
-        }
-        if ((ErrCnt[Failure] + ErrCnt[Serious]) > 0) {
-            printf ("The arithmetic diagnosed has ");
-            printf ("unacceptable Serious Defects.\n");
-        }
-        if (ErrCnt[Failure] > 0) {
-            printf ("Potentially fatal FAILURE may have spoiled this");
-            printf (" program's subsequent diagnoses.\n");
-        }
-    } else {
-
-        printf ("No failures, defects nor flaws have been discovered.\n");
-        if (!((RMult == Rounded) && (RDiv == Rounded)
-                && (RAddSub == Rounded) && (RSqrt == Rounded)))
-            printf ("The arithmetic diagnosed seems Satisfactory.\n");
-        else {
-            if (StickyBit >= One &&
-                (Radix - Two) * (Radix - Nine - One) == Zero) {
-                printf ("Rounding appears to conform to ");
-                printf ("the proposed IEEE standard P");
-                if ((Radix == Two) &&
-                    ((Precision - Four * Three * Two) *
-                        (Precision - TwentySeven -
-                            TwentySeven + One) == Zero))
-                    printf ("754");
-                else
-                    printf ("854");
-                if (IEEE)
-                    printf (".\n");
-                else {
-                    printf (",\nexcept for possibly Double Rounding");
-                    printf (" during Gradual Underflow.\n");
-                }
-            }
-            printf ("The arithmetic diagnosed appears to be Excellent!\n");
-        }
-    }
-
-    if (fpecount)
-        printf ("\nA total of %d floating point exceptions were registered.\n",
-            fpecount);
-    printf ("END OF TEST.\n");
-    return 0;
-}
-
-FLOAT
-Sign (X)
-     FLOAT   X;
-{
-    return X >= 0. ? 1.0 : -1.0;
-}
-
-void
-Pause ()
-{
-#ifndef BATCHMODE
-    char    ch[8];
-
-    printf ("\nTo continue, press RETURN");
-    fflush (stdout);
-    read (KEYBOARD, ch, 8);
-#endif /* !BATCHMODE */
-#ifndef CYGNUS
-    printf ("\nDiagnosis resumes after milestone Number %d", Milestone);
-    printf ("          Page: %d\n\n", PageNo);
-    ++Milestone;
-    ++PageNo;
-#endif /* !CYGNUS */
-}
-
-void
-TstCond (K, Valid, T)
-     int     K, Valid;
-     char   *T;
-{
-#ifdef CYGNUS
-    printf ("TEST: %s\n", T);
-#endif /* CYGNUS */
-    if (!Valid) {
-        BadCond (K, T);
-        printf (".\n");
-    }
-#ifdef CYGNUS
-    printf ("PASS: %s\n", T);
-#endif /* CYGNUS */
-}
-
-void
-BadCond (K, T)
-     int     K;
-     char   *T;
-{
-    static char *msg[] =
-    {"FAILURE", "SERIOUS DEFECT", "DEFECT", "FLAW"};
-
-    ErrCnt[K] = ErrCnt[K] + 1;
-#ifndef CYGNUS
-    printf ("%s:  %s", msg[K], T);
-#else
-    printf ("ERROR: Severity: %s:  %s", msg[K], T);
-#endif /* CYGNUS */
-}
-
-/*
- * Random computes
- *     X = (Random1 + Random9)^5
- *     Random1 = X - FLOOR(X) + 0.000005 * X;
- *   and returns the new value of Random1
-*/
-FLOAT
-Random ()
-{
-    FLOAT   X, Y;
-
-    X = Random1 + Random9;
-    Y = X * X;
-    Y = Y * Y;
-    X = X * Y;
-    Y = X - FLOOR (X);
-    Random1 = Y + X * 0.000005;
-    return (Random1);
-}
-
-void
-SqXMinX (ErrKind)
-     int     ErrKind;
-{
-    FLOAT   XA, XB;
-
-    XB = X * BInvrse;
-    XA = X - XB;
-    SqEr = ((SQRT (X * X) - XB) - XA) / OneUlp;
-    if (SqEr != Zero) {
-        if (SqEr < MinSqEr)
-            MinSqEr = SqEr;
-        if (SqEr > MaxSqEr)
-            MaxSqEr = SqEr;
-        J = J + 1.0;
-        BadCond (ErrKind, "\n");
-        printf ("sqrt( %.17e) - %.17e  = %.17e\n", X * X, X, OneUlp * SqEr);
-        printf ("\tinstead of correct value 0 .\n");
-    }
-}
-
-void
-NewD ()
-{
-    X = Z1 * Q;
-    X = FLOOR (Half - X / Radix) * Radix + X;
-    Q = (Q - X * Z) / Radix + X * X * (D / Radix);
-    Z = Z - Two * X * D;
-    if (Z <= Zero) {
-        Z = -Z;
-        Z1 = -Z1;
-    }
-    D = Radix * D;
-}
-
-void
-SR3750 ()
-{
-    if (!((X - Radix < Z2 - Radix) || (X - Z2 > W - Z2))) {
-        I = I + 1;
-        X2 = SQRT (X * D);
-        Y2 = (X2 - Z2) - (Y - Z2);
-        X2 = X8 / (Y - Half);
-        X2 = X2 - Half * X2 * X2;
-        SqEr = (Y2 + Half) + (Half - X2);
-        if (SqEr < MinSqEr)
-            MinSqEr = SqEr;
-        SqEr = Y2 - X2;
-        if (SqEr > MaxSqEr)
-            MaxSqEr = SqEr;
-    }
-}
-
-void
-IsYeqX ()
-{
-    if (Y != X) {
-        if (N <= 0) {
-            if (Z == Zero && Q <= Zero)
-                printf ("WARNING:  computing\n");
-            else
-                BadCond (Defect, "computing\n");
-            printf ("\t(%.17e) ^ (%.17e)\n", Z, Q);
-            printf ("\tyielded %.17e;\n", Y);
-            printf ("\twhich compared unequal to correct %.17e ;\n",
-                X);
-            printf ("\t\tthey differ by %.17e .\n", Y - X);
-        }
-        N = N + 1;              /* ... count discrepancies. */
-    }
-}
-
-void
-SR3980 ()
-{
-    do {
-        Q = (FLOAT) I;
-        Y = POW (Z, Q);
-        IsYeqX ();
-        if (++I > M)
-            break;
-        X = Z * X;
-    }
-    while (X < W);
-}
-
-void
-PrintIfNPositive ()
-{
-    if (N > 0)
-        printf ("Similar discrepancies have occurred %d times.\n", N);
-}
-
-void
-TstPtUf ()
-{
-    N = 0;
-    if (Z != Zero) {
-        printf ("Since comparison denies Z = 0, evaluating ");
-        printf ("(Z + Z) / Z should be safe.\n");
-        sigsave = _sigfpe;
-        if (setjmp (ovfl_buf))
-            goto very_serious;
-        Q9 = (Z + Z) / Z;
-        printf ("What the machine gets for (Z + Z) / Z is  %.17e .\n",
-            Q9);
-        if (FABS (Q9 - Two) < Radix * U2) {
-            printf ("This is O.K., provided Over/Underflow");
-            printf (" has NOT just been signaled.\n");
-        } else {
-            if ((Q9 < One) || (Q9 > Two)) {
-              very_serious:
-                N = 1;
-                ErrCnt[Serious] = ErrCnt[Serious] + 1;
-                printf ("This is a VERY SERIOUS DEFECT!\n");
-            } else {
-                N = 1;
-                ErrCnt[Defect] = ErrCnt[Defect] + 1;
-                printf ("This is a DEFECT!\n");
-            }
-        }
-        sigsave = 0;
-        V9 = Z * One;
-        Random1 = V9;
-        V9 = One * Z;
-        Random2 = V9;
-        V9 = Z / One;
-        if ((Z == Random1) && (Z == Random2) && (Z == V9)) {
-            if (N > 0)
-                Pause ();
-        } else {
-            N = 1;
-            BadCond (Defect, "What prints as Z = ");
-            printf ("%.17e\n\tcompares different from  ", Z);
-            if (Z != Random1)
-                printf ("Z * 1 = %.17e ", Random1);
-            if (!((Z == Random2)
-                    || (Random2 == Random1)))
-                printf ("1 * Z == %g\n", Random2);
-            if (!(Z == V9))
-                printf ("Z / 1 = %.17e\n", V9);
-            if (Random2 != Random1) {
-                ErrCnt[Defect] = ErrCnt[Defect] + 1;
-                BadCond (Defect, "Multiplication does not commute!\n");
-                printf ("\tComparison alleges that 1 * Z = %.17e\n",
-                    Random2);
-                printf ("\tdiffers from Z * 1 = %.17e\n", Random1);
-            }
-            Pause ();
-        }
-    }
-}
-
-void
-notify (s)
-     char   *s;
-{
-    printf ("%s test appears to be inconsistent...\n", s);
-    printf ("   PLEASE NOTIFY KARPINKSI!\n");
-}
-
-void
-msglist (s)
-     char  **s;
-{
-    while (*s)
-        printf ("%s\n", *s++);
-}
-
-void
-Instructions ()
-{
-    static char *instr[] =
-    {
-        "Lest this program stop prematurely, i.e. before displaying\n",
-        "    `END OF TEST',\n",
-        "try to persuade the computer NOT to terminate execution when an",
-        "error like Over/Underflow or Division by Zero occurs, but rather",
-        "to persevere with a surrogate value after, perhaps, displaying some",
-        "warning.  If persuasion avails naught, don't despair but run this",
-        "program anyway to see how many milestones it passes, and then",
-        "amend it to make further progress.\n",
-        "Answer questions with Y, y, N or n (unless otherwise indicated).\n",
-        0};
-
-    msglist (instr);
-}
-
-void
-Heading ()
-{
-    static char *head[] =
-    {
-        "Users are invited to help debug and augment this program so it will",
-        "cope with unanticipated and newly uncovered arithmetic pathologies.\n",
-        "Please send suggestions and interesting results to",
-        "\tRichard Karpinski",
-        "\tComputer Center U-76",
-        "\tUniversity of California",
-        "\tSan Francisco, CA 94143-0704, USA\n",
-        "In doing so, please include the following information:",
-#ifdef SINGLE_PRECISION
-        "\tPrecision:\tsingle;",
-#else /* !SINGLE_PRECISION */
-        "\tPrecision:\tdouble;",
-#endif /* SINGLE_PRECISION */
-        "\tVersion:\t10 February 1989;",
-        "\tComputer:\n",
-        "\tCompiler:\n",
-        "\tOptimization level:\n",
-        "\tOther relevant compiler options:",
-        0};
-
-    msglist (head);
-}
-
-void
-Characteristics ()
-{
-    static char *chars[] =
-    {
-        "Running this program should reveal these characteristics:",
-        "     Radix = 1, 2, 4, 8, 10, 16, 100, 256 ...",
-        "     Precision = number of significant digits carried.",
-        "     U2 = Radix/Radix^Precision = One Ulp",
-        "\t(OneUlpnit in the Last Place) of 1.000xxx .",
-        "     U1 = 1/Radix^Precision = One Ulp of numbers a little less than 1.0 .",
-        "     Adequacy of guard digits for Mult., Div. and Subt.",
-        "     Whether arithmetic is chopped, correctly rounded, or something else",
-        "\tfor Mult., Div., Add/Subt. and Sqrt.",
-        "     Whether a Sticky Bit used correctly for rounding.",
-        "     UnderflowThreshold = an underflow threshold.",
-        "     E0 and PseudoZero tell whether underflow is abrupt, gradual, or fuzzy.",
-        "     V = an overflow threshold, roughly.",
-        "     V0  tells, roughly, whether  Infinity  is represented.",
-        "     Comparisions are checked for consistency with subtraction",
-        "\tand for contamination with pseudo-zeros.",
-        "     Sqrt is tested.  Y^X is not tested.",
-        "     Extra-precise subexpressions are revealed but NOT YET tested.",
-        "     Decimal-Binary conversion is NOT YET tested for accuracy.",
-        0};
-
-    msglist (chars);
-}
-
-void
-History ()
-{                               /* History */
-    /* Converted from Brian Wichmann's Pascal version to C by Thos Sumner,
-        with further massaging by David M. Gay. */
-
-    static char *hist[] =
-    {
-        "The program attempts to discriminate among",
-        "   FLAWs, like lack of a sticky bit,",
-        "   Serious DEFECTs, like lack of a guard digit, and",
-        "   FAILUREs, like 2+2 == 5 .",
-        "Failures may confound subsequent diagnoses.\n",
-        "The diagnostic capabilities of this program go beyond an earlier",
-        "program called `MACHAR', which can be found at the end of the",
-        "book  `Software Manual for the Elementary Functions' (1980) by",
-        "W. J. Cody and W. Waite. Although both programs try to discover",
-        "the Radix, Precision and range (over/underflow thresholds)",
-        "of the arithmetic, this program tries to cope with a wider variety",
-        "of pathologies, and to say how well the arithmetic is implemented.",
-        "\nThe program is based upon a conventional radix representation for",
-        "floating-point numbers, but also allows logarithmic encoding",
-        "as used by certain early WANG machines.\n",
-        "BASIC version of this program (C) 1983 by Prof. W. M. Kahan;",
-        "see source comments for more history.",
-        0};
-
-    msglist (hist);
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/phrasen.c b/lib/CPUs/MIPS/bsp/examples/phrasen.c
deleted file mode 100644
index 08abf97..0000000
--- a/lib/CPUs/MIPS/bsp/examples/phrasen.c
+++ /dev/null
@@ -1,298 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include "libsys.h"
-
-struct substantive
-{
-	char *subst;
-	int sex;
-};
-
-struct verben
-{
-	char *verb_k;
-	char *verb_gr;
-	int art;
-};
-
-struct adjektive
-{
-	char *adj;
-};
-
-	char *art[4]={"er","ie","as","en"};
-
-char getch(void)
-{
-	return _getchar();
-}
-
-void randomize(void)
-{
-	srand(clock());
-}
-
-struct substantive namen[]=
-{
-	{"Gerhard Schröder",1},{"Helmut Kohl",1},{"Rudolf Scharping",1},
-	{"Claudia Nolte",2},	{"Johannes Rau",1},{"Wolfgang Schäuble",1},
-	{"Joschka Fischer",1},{"Toni Blair",1},{"Kleopatra",2},
-	{"Claudia Schiffer",2},{"Hannelore Kohl",2},{"Konrad Adenauer",1},
-	{"Michael Jackson",1},{"Karl Marx",1},	{"Helmut Kohl",1},{"Heino",1},
-	{"Gerhard Schröder",1},{"Donald Duck",1},{"Madonna",2},{"Jesus",1},
-	{"Gott",1},{"Sheryl Crow",2},{"Verona Feldbusch",2},{"Pipi Langstrumpf",2},
-	{"Bill Gates",1},{"Bill Clinton",1},{"Cleopatra",2},{"Winnetou",1},
-	{"Käpt'n Blaubär",1},{"Rita Süssmuth",2},{"Boris Becker",1},
-	{"Lilo Wanders",2},{"Queen Elizabeth",2},{"Lady Di",2},{"Steffi Graf",2},
-	{"Frank Zappa",1},{"Dolly Buster",2},{"Mao Tse Tung",1},{"Ghandi",1},
-	{"Dalai Lama",1},{"Teufel",1},{"Lenin",1},{"Edmund Stoiber",1},
-	{"Ludwig van Beethoven",1},{"Wolfgang Amadeus Mozart",1},
-	{"Richard Wagner",1},{"Erich Honecker",1},{"Adam Riese",1},
-	{"Bill Clinton",1},{"Josef Stalin",1},{"Willy Brandt",1},
-	{"John F. Kennedy",1},{"E.T.",1},{"Donald Duck",1},{"Lothar Matthäus",1},
-	{"Hans Dietrich Genscher",1},{"Franz Josef Strauss",1},{"Sting",1},
-	{"Hermann Hesse",1},{"Albert Einstein",1},{"Max Planck",1},
-	{"Tom Jones",1},{"Heidi Kabel",2},{"Homer Simpson",1},{"Zeus",1},
-	{"Helmut Schmidt",1},{"Antje Vollmer",2},{"Politiker",1},{"Papst",1},
-	{"Bundeskanzler",1},{"Arzt",1},{"Friseuse",2},{"Teufel",1},
-	{"Sandmännchen",3},{"Mutter",2},{"Vater",1},{"Säufer",1},{"Student",1},
-	{"Bauer",1},{"Leiche",2},{"Polizist",1},{"Patientin",2},{"Bäcker",1},
-	{"Wirt",1},	{"Schlachter",1},{"Baby",3},{"Reporter",1},{"Politiker",1},
-	{"Beamtin",2},{"Oma",2},{"Putzfrau",2},{"Blinde",2},{"Wahnsinnige",2},
-	{"Mörder",1},{"Psychiater",1},{"Prinz Charles",1},{"Onkel",1},{"Tante",2}
-};
-
-struct substantive sachen[]=
-{
-	{"Haus",3},{"Buch",3},{"Fahrrad",3},{"Schule",2},{"Auto",3},{"Nase",2},
-	{"Mund",1},{"Kopf",1},{"Kaffee",1},{"Telephon",3},{"Tasse",2},{"Katze",2},
-	{"Hund",1},{"Maus",2},{"Stuhl",1},{"Mann",1},{"Frau",2},{"Kind",3},
-	{"Idiotin",2},{"Lampe",2},{"Panzer",1},{"Klavier",3},{"Gitarre",2},
-	{"Straße",2},{"Wasser",3},{"Luft",2},{"Feuer",3},{"Erde",2},{"Mond",1},
-	{"Sonne",2},{"Bild",3},{"Stadt",2},{"Land",3},{"Fluss",1},
-	{"Bundeskanzler",1},{"Ball",1},{"Hut",1},{"Hose",2},{"Hemd",3},{"Tod",1},
-	{"Geld",3},{"Tisch",1},{"Hand",2},{"Baum",1},{"Bier",3},{"Ratte",2},
-	{"Esel",1},{"Musik",2},{"Blech",3},{"Dose",2},{"Zahn",1},{"Humor",1},
-	{"Unterhose",2},{"Gift",3},{"Gesicht",3},{"Fuß",1},{"Auge",3},{"Warze",2},
-	{"Ohr",3},{"Kanone",2},{"Milch",2},{"Messer",3},{"Papier",3},{"Haar",3},
-	{"Welt",2},{"Motor",1},{"Langeweile",2},{"Grab",3},{"Schnaps",1},
-	{"Vogel",1},{"Fisch",1},{"Meer",3},{"Banane",2},{"Brot",3},
-	{"Sitzung",2},{"Labor",3},{"Kurzschluß",1},{"Lüge",2},{"Axt",2},
-	{"Abstimmung",2},{"Toilette",2},{"Zigarette",2},{"Winter",1},
-	{"Torte",2},{"Bahnhof",1},{"Sarg",1},{"Imbiss",1},{"Mund",1},{"Seife",2},
-	{"Fernseher",1},{"Flasche",2},{"Eimer",1},{"Uhr",2},{"Irrenhaus",3},
-	{"Wüste",2},{"Klumpen",1},{"Glück",3},{"Schiff",3},{"Käse",1},{"Quark",1},
-	{"Sommer",1},{"Witz",1},{"Idee",2},{"Nacht",2},{"Dreck",1},{"Meer",3},
-	{"Blut",3},{"Herz",3},{"Apfel",1},{"Banane",2},{"Mist",1},{"Atom",3},
-	{"Note",2},{"Gehirn",3},{"Gefühl",3},{"Bombe",2},{"Vakuum",3},
-	{"Zahl",2},{"Wort",3},{"Programm",3},{"Computer",1},{"Orient",1},
-	{"Gabelstapler",1}
-};
-
-struct adjektive ad[]=
-{
-	{"schön"},{"doof"},{"gut"},{"schlecht"},{"gelb"},{"grün"},{"rot"},
-	{"blau"},{"schnell"},{"lang"},{"kurz"},{"hell"},{"düster"},{"sanft"},
-	{"hart"},{"langsam"},{"bitter"},{"süß"},{"kaputt"},{"nett"},{"groß"},
-	{"klein"},{"leicht"},{"schwer"},{"dick"},{"dünn"},{"rund"},{"eckig"},
-	{"heiß"},{"kalt"},{"schlau"},{"elektrisch"},{"nass"},{"trocken"},{"ratlos"},
-	{"abartig"},{"genial"},{"bestechlich"},{"irr"},{"steif"},{"angespannt"},
-	{"laut"},{"leis"},{"warm"},{"wütend"},{"sauber"},{"schmutzig"},{"arm"},
-	{"ätzend"},{"langweilig"},{"interessant"},{"erfahren"},{"abgewählt"},
-	{"durchgeknallt"},{"angenehm"},{"widerwärtig"},{"willig"},{"mutig"},
-	{"schwach"},{"stark"},{"nervend"},{"spießig"},{"alt"},{"neu"},{"spitz"},
-	{"stumpf"},{"teuflisch"},{"scharf"},{"lecker"},{"übelriechend"},{"halb"},
-	{"ganz"},{"bleich"},{"peinlich"},{"taktlos"},{"gewieft"},{"windig"},
-	{"größenwahnsinnig"},{"verrückt"},{"uralt"},{"aalglatt"},{"korrekt"},
-	{"kompetent"},{"einfühlsam"},{"tot"},{"schleimig"},{"gestört"},{"hohl"},
-	{"beknackt"},{"nackt"},{"barfüßig"},{"schwitzend"},{"laufend"},{"knackig"},
-	{"unverschämt"},{"schläfrig"},{"wohlgeformt"},{"kugelförmig"},{"rauh"},
-	{"degeneriert"},{"ekelhaft"},{"brutal"},{"gemein"},{"aggressiv"},
-	{"aufdringlich"},{"betroffen"},{"geliebt"},{"gehasst"},{"beharrlich"},
-	{"unmenschlich"},{"verblödet"},{"wichtig"},{"gigantisch"},{"winzig"},
-	{"witzig"},{"komisch"},{"pervers"},{"fett"},{"stinkend"},{"lausig"},
-	{"wendig"},{"breit"},{"locker"},{"einzigartig"},{"sterbend"},{"munter"},
-	{"ungepflegt"},{"eisern"},{"echt"},{"besser"},{"wild"},{"ächzend"},
-	{"frohlockend"},{"unscheinbar"},{"nebulös"},{"skandalös"},{"obzön"},
-	{"beschränkt"},{"genervt"},{"hilflos"},{"unwürdig"},{"geleckt"},
-	{"betrunken"},{"unwürdig"},{"bissig"},{"verkalkt"},{"senil"},
-	{"jungfräulich"},{"ausgeleiert"},{"beleibt"},{"nachtragend"},{"errötend"},
-	{"kahl"},{"würgend"},{"abwesend"},{"ruhig"},{"albern"},{"trostlos"},
-	{"salzig"},{"lachend"},{"merkwürdig"},{"behaart"},{"leblos"},{"aufgeblasen"},
-	{"frech"},{"kopflos"},{"schmierig"}
-};
-
-struct verben verb[]=
-{
-	{"geht","gehen",6},{"steht","stehen",2},{"sitzt","sitzen",2},
-	{"spielt","spielen",7},{"singt","singen",2},{"trinkt","trinken",3},
-	{"redet","reden",2},	{"liebt","lieben",7},{"schläft","schlafen",2},
-	{"ißt","essen",3},{"lacht","lachen",2},{"tötet","töten",7},
-	{"lügt","lügen",2},{"fliegt","fliegen",2},{"überfährt","überfahren",7},
-	{"sieht","sehen",3},{"hört","hören",3},{"spricht","sprechen",2},
-	{"berechnet","rechnen",3},{"schwimmt","schwimmen",2},
-	{"zerschneidet","zerschnitten werden",3},{"raucht","rauchen",3},
-	{"spaltet","spalten",3},{"verbrennt","verbrennen",2},{"ist","sein",2},
-	{"hat","haben",1},{"zerbricht","zerbrechen",3},{"muss","müssen",4},
-	{"kann","können",4},{"darf","dürfen",4},{"will","wollen",5},
-	{"klaut","klauen",1},{"soll","sollen",4},{"studiert","studieren",3},
-	{"reibt","reiben",3},{"liest","lesen",2},{"irrt","irren",2},
-	{"spendiert","spendieren",1},{"schlägt","schlagen",3},{"fragt","fragen",7},
-	{"zerstört","zerstören",1},{"erschießt","sich erschießen",1},
-	{"überlegt","überlegen",2},{"trifft","treffen",7},{"leckt","lecken",1},
-	{"wirft","werfen",1},{"vergiftet","vergiftet werden",1},
-	{"öffnet","öffnen",1},{"schreit","schreien",2},{"sprengt","explodieren",3},
-	{"erwürgt","würgen",7},{"arbeitet","arbeiten",2},{"erlegt","erlegen",1},
-	{"putzt","putzen",1},{"stirbt","sterben",2},	{"kauft","kaufen",1},
-	{"brüllt","brüllen",2},{"versteht","es verstehen",7},
-	{"zertritt","zertreten werden",1},{"verendet","verenden",2},
-	{"labert","labern",2},{"kratzt","kratzen",1},{"wird","nichts werden",2},
-	{"entkleidet","sich entkleiden",7},{"verbiegt","sich verbiegen",1},
-	{"verschenkt","es verschenken",7},{"vergisst","es vergessen",1},
-	{"ergreift","greifen",1},{"baut","bauen",1},{"betet","beten",},
-	{"rollt","rollen",3},{"bleibt","bleiben",2},{"wäscht","sich waschen",1},
-	{"heiratet","heiraten",7},{"hebt","heben",1},{"denkt","nachdenken",2}
-};
-
-void end_sach_aus(void);
-void nam_aus(void);
-void end_nam_aus(void);
-void adj_aus(void);
-int verb_aus_k(void);
-int verb_aus_gr(void);
-int zufall(int);
-
-int main()
-{
-	int vindx;
-	int rem=0;
-	char end;
-
-	setbuf(stdout, NULL);
-	randomize();
-	printf("\n\t\t************************");
-	printf("\n\t\t* DER ELEKTRISCHE POET *");
-	printf("\n\t\t************************\n");
-	printf("\n\tCopyright by J. Ahrensfeld & T. Burr");
-	printf("\n\n\tFür die Texte ist Ihr Computer verantwortlich :-)\n");
-	printf("\n\tZum beenden des Programmes 'x' eingeben!\n");
-	printf("\n\tWeiter mit beliebiger Taste!\n");
-	end = getch();
-
-	while(end != 'x')
-	{
-		if(rem >= 10)
-			{
-				printf("\n\n\tZum beenden des Programmes 'x' eingeben!\n");
-				rem = 0;
-				if(getch() == 'x')
-					break;
-			}
-		printf("\n\n");
-		nam_aus();
-
-		vindx=verb_aus_k();
-
-		switch (vindx)
-			{
-				case 1: end_sach_aus(); break;
-
-				case 2: adj_aus(); break;
-
-				case 3: end_sach_aus(); break;
-
-				case 4: verb_aus_gr(); break;
-
-				case 5: verb_aus_gr(); break;
-
-				case 6: adj_aus(); break;
-
-				case 7: end_nam_aus(); break;
-			}
-
-		printf(".");
-		end = getch();
-      rem++;
-
-	}
-	printf("\n\n\tDas ist das Ende!");
-	return 0;
-}
-
-int zufall(int max)
-{
-
-	return (rand()%max);
-}
-
-void adj_aus(void)
-{
-	printf("%s", ad[zufall((sizeof(ad)/sizeof(*ad)))].adj);
-	return;
-}
-
-void end_sach_aus(void)
-{
-		int index;
-
-		index = zufall(sizeof(sachen)/sizeof(*sachen));
-		if (sachen[index].sex==1)
-			printf("d%s", art[3]);
-		else
-			printf("d%s", art[(sachen[index].sex)-1]);
-		printf(" ");
-		adj_aus();
-		if (sachen[index].sex==1)
-			printf("en %s", sachen[index].subst);
-		else
-			printf("e %s", sachen[index].subst);
-		return;
-}
-
-void nam_aus(void)
-{
-		int index;
-
-		index = zufall(sizeof(namen)/sizeof(*namen));
-		printf("D%s", art[(namen[index].sex)-1]);
-		printf(" ");
-		adj_aus();
-		printf("e %s " ,namen[index].subst);
-		return;
-}
-
-void end_nam_aus(void)
-{
-		int index;
-
-		index = zufall(sizeof(namen)/sizeof(*namen));
-		if (namen[index].sex==1)
-			printf("d%s", art[3]);
-		else
-			printf("d%s", art[(namen[index].sex)-1]);
-		printf(" ");
-		adj_aus();
-		if (namen[index].sex==1)
-			printf("en %s", namen[index].subst);
-		else
-			printf("e %s", namen[index].subst);
-		return;
-}
-
-int verb_aus_k(void)
-{
-		int index;
-
-		index = zufall(sizeof(verb)/sizeof(*verb));
-		printf("%s ", verb[index].verb_k);
-		return (verb[index].art);
-}
-
-int verb_aus_gr(void)
-{
-		int index;
-
-		index = zufall(sizeof(verb)/sizeof(*verb));
-		printf("%s", verb[index].verb_gr);
-		return index;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/pi.h b/lib/CPUs/MIPS/bsp/examples/pi.h
deleted file mode 100644
index 5cfed9b..0000000
--- a/lib/CPUs/MIPS/bsp/examples/pi.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-#ifndef PI__H
-#define PI__H
-
-#ifndef PI
- #define PI         (4*atan(1))
-#endif
-
-#define deg2rad(d) ((d)*PI/180)
-#define rad2deg(r) ((r)*180/PI)
-
-#endif /* PI__H */
diff --git a/lib/CPUs/MIPS/bsp/examples/queens.c b/lib/CPUs/MIPS/bsp/examples/queens.c
deleted file mode 100644
index f9735e6..0000000
--- a/lib/CPUs/MIPS/bsp/examples/queens.c
+++ /dev/null
@@ -1,856 +0,0 @@
-/*
-**  Queens.c    --  Find solutions to the Eight-Queens chess problem.
-**                  Roberto Sierra  7/25/93  Version 1.1
-**                                  3/19/84  Version 1.0
-**
-**  Description:
-**      This program finds all the possible ways that N queens can
-**      be placed on an NxN chessboard so that the queens cannot
-**      capture one another -- that is, so that no rank, file or
-**      diagonal is occupied by more than one queen.  By default,
-**      the program prints the first solution it finds.  You can
-**      use the -a option to print all solutions, or the -c option
-**      just to count them.  The program allows the chess board
-**      to be from 1x1 (trivial case) to 100x100.  Warning: the
-**      larger the chess board, the longer it typically takes to
-**      find each solution, even though there may be more of them.
-**
-**      This is a terrific example of the utility of recursion. The
-**      algorithm uses recursion to drastically limit the number
-**      of board positions that are tested.  The program is able
-**      to find all 8x8 queen solutions in a fraction of a second
-**      (not counting print time).  The code makes no attempt to
-**      eliminate symmetrical solutions, so the number of solutions
-**      reported will always be higher than the actual number of
-**      distinct solutions.
-**
-**
-**  Usage:
-**      Queens [-ac] n
-**
-**      n       number of queens (rows and columns).
-**              An integer from 1 to 100.
-**      -a      Find (and print) all solutions.
-**      -c      Count all solutions, but do not print them.
-**
-**      The output is sent to stdout.  All errors messages are
-**      sent to stderr.  If a problem arises, the return code is -1.
-**
-**
-**  Examples:
-**
-**      Queens 8        ## Show an 8x8 solution
-**      8 queens on a 8x8 board...
-**       Q - - - - - - -
-**       - - - - Q - - -
-**       - - - - - - - Q
-**       - - - - - Q - -
-**       - - Q - - - - -
-**       - - - - - - Q -
-**       - Q - - - - - -
-**       - - - Q - - - -
-**
-**      Queens -c 8     ## Count all 8x8 solutions
-**      8 queens on a 8x8 board...
-**      ...there are 92 solutions.
-**
-**      Queens -a 4     ## Show all 4x4 solutions
-**      4 queens on a 4x4 board...
-**
-**      Solution #1:
-**       - Q - -
-**       - - - Q
-**       Q - - -
-**       - - Q -
-**
-**      Solution #2:
-**       - - Q -
-**       Q - - -
-**       - - - Q
-**       - Q - -
-**
-**      ...there are 2 solutions.
-**
-**
-**  Build Instructions:
-**      You'll need an ANSI C compiler (or the willingness to edit
-**      the program a bit).  If you've got Gnu C, then you can
-**      compile and load the program as follows:
-**
-**              gcc Queens.c -ansi -o Queens
-**
-**      [If you're using MPW on the Mac, define '-d MPW' on the
-**      compile line so that background processing will occur.]
-**
-**
-**  Algorithm:
-**      In a 1984 Byte article, I ran across an interesting letter
-**      from a high school student who was attempting to solve the
-**      Eight Queens problem using a BASIC interpreter.  He had
-**      developed a program which placed eight queens successively
-**      on all sixty-four squares, testing for conflicts at each
-**      iteration.  Of course, such a program would require 64^8
-**      iterations (about 2.8x10^14 iterations).  Even in C on a,
-**      fast CPU, this could take months or years.  Byte's answer was
-**      to alter the loops so that the queens resided on separate
-**      ranks, thereby reducing the number of iterations required
-**      to find all solutions to 8^8 iterations (about 16 million).
-**      More reasonable, but still requiring a chunk of CPU time.
-**
-**      I puzzled about this problem a bit, and came to realize that
-**      this was still wasting a lot of CPU cycles.  Though I'm sure
-**      others have come up with good algorithms, I decided to come
-**      up with my own, with a particular eye on efficiency.  The
-**      resulting algorithm finds all 8x8 solutions in a fraction
-**      of a second (there are 92 solutions, including rotations).
-**      On a Sun 4, it'll find all 365,596 solutions on a 14x14 board
-**      in a bit over 2 minutes (printing them out requires extra
-**      time, of course).  Even Byte's solution would require 14^14
-**      iterations (about 10^16) which would take aeons.
-**
-**      My algorithm works as follows:
-**      (1)  Place a queen in the top left corner.
-**      (2)  Place another queen immediately below.
-**      (3)  Test for conflicts.  If the second queen conflicts (it
-**           does at first), then move it one square to the right.
-**      (4)  Loop step 3 until there are no conflicts.  Place
-**           the next queen on the board and recurse.
-**      (5)  If any queen reaches the right edge of the board,
-**           remove it and 'pop' to the previous recursion level.
-**      (6)  Now repeat these steps recursively until all eight
-**           queens (or however many) have been placed without
-**           conflict -- the result is a solution to the problem,
-**           which is counted and optionally printed.
-**
-**      Because conflicts are tested as the recursion proceeds,
-**      this has the effect of 'pruning' the recursion so that
-**      a large number of board positions are not even attempted.
-**      The result is that the algorithm runs in reasonable time.
-**
-**      I used a few tricks to make the test-for-conflict code
-**      extremely efficient -- there is no 'inner' loop to search
-**      along ranks, files, or diagonals.  A series of arrays are
-**      maintained instead which indicate which queen currently
-**      'owns' each rank, file or diagonal.  This makes the
-**      algorithm really fly, though the code is a little hard to
-**      read.  Lastly, pointer arithmetic is used to reduce the
-**      number of implicit multiplications used in array addressing.
-**
-**
-**  Contact:
-**      For queries regarding this program, contact Roberto Sierra
-**      at any of the following addresses:
-**
-**              Roberto Sierra
-**              bert@netcom.com   (preferred address)
-**              73557.2101@compuserve.com
-**
-**              Tempered MicroDesigns
-**              P.O. Box 170638
-**              San Francisco, CA  94117
-**
-**
-**  Fine Print:
-**      This program is in the public domain and can be used for
-**      any purpose whatsoever, including commercial application.
-**      [I'd like to hear what you do with it, though.]
-**      Absolutely no warranty or liability is implied or extended
-**      by the author.
-**
-**
-**  Modification History:
-**      PRS  3/19/84  v1.0 -- Original version.
-**      PRS  7/25/93  v1.1 -- ANSIfied the code.  More efficient pointers.
-**
-*/
-
-/***************************************************************/
-/* Timer options. You MUST uncomment one of the options below  */
-/* or compile, for example, with the '-DUNIX' option.          */
-/***************************************************************/
-/* #define Amiga       */
-/* #define UNIX        */
-/* #define UNIX_Old    */
-/* #define VMS         */
-/* #define BORLAND_C   */
-/* #define MSC         */
-/* #define MAC         */
-/* #define IPSC        */
-/* #define FORTRAN_SEC */
-/* #define GTODay      */
-/* #define CTimer      */
-/* #define UXPM        */
-/* #define MAC_TMgr    */
-/* #define PARIX       */
-/* #define POSIX       */
-/* #define WIN32       */
-/* #define POSIX1      */
-/***********************/
-
-#include <stdio.h>                              /* Need standard I/O functions */
-#include <stdlib.h>                             /* Need exit() routine interface */
-#include <string.h>                             /* Need strcmp() interface */
-#ifdef  MPW                                     /* Macintosh MPW ONLY */
-#include <CursorCtl.h>                          /* Need cursor control interfaces */
-#endif
-
-#define MAXQUEENS   100                         /* Maximum number of queens */
-#define MAXRANKS    MAXQUEENS                   /* Maximum number of ranks (rows) */
-#define MAXFILES    MAXQUEENS                   /* Maximum number of files (columns) */
-#define MAXDIAGS    (MAXRANKS+MAXFILES-1)       /* Maximum number of diagonals */
-#define EMPTY       (MAXQUEENS+1)               /* Marks unoccupied file or diagonal */
-
-/* GLOBAL VARIABLES */
-
-int             queens;                         /* Number of queens to place */
-int             ranks;                          /* Number of ranks (rows) */
-int             files;                          /* Number of files (columns) */
-int             printing = 1;                   /* TRUE if printing positions */
-int             findall = 0;                    /* TRUE if finding all solutions */
-
-unsigned long   solutions = 0;                  /* Number of solutions found */
-int             queen[MAXRANKS];                /* File on which each queen is located */
-int             file[MAXFILES];                 /* Which queen 'owns' each file */
-int             fordiag[MAXDIAGS];              /* Which queen 'owns' forward diagonals */
-int             bakdiag[MAXDIAGS];              /* Which queen 'owns' reverse diagonals */
-char            *progname = 0;                  /* The name of this program */
-
-
-
-
-
-/***********************/
-/****   ROUTINES    ****/
-/***********************/
-
-/* Internal prototypes */
-//void    main(int argc,char **argv);             /* Main program */
-void    find(int level);                        /* Algorithm to find solutions */
-void    pboard(void);                           /* Print a solution */
-void run_queens(int argc,char **argv);
-
-
-
-
-/*---------------------- main() ---------------------------
-**  MAIN program.  The main purpose of this routine is
-**  to deal with decoding the command line arguments,
-**  initializing the various arrays, and starting the
-**  recursive search routine.
-*/
-int main(void)
-{
-	char *args[] = {"queens", "-c", "12"};
-	run_queens(3, args);
-}
-
-void run_queens(int argc,char **argv)
-{
-    register int    i;                          /* Loop variable */
-    register char   *p;                         /* Pointer to argument */
-    double starttime, benchtime, dtime();
-
-#ifdef  MPW                                     /* Macintosh MPW ONLY */
-    InitCursorCtl(0);                           /* Enable cursor control */
-#endif
-
-    progname = argv[0];                         /* The name of the program */
-
-    /****   DECODE COMMAND LINE ARGUMENTS   ****/
-
-    for (i=1; i<argc; ++i) {                    /* Scan through arguments */
-	p = argv[i];                            /* Pointer to base of argument */
-	if (*p == '-') {                        /* Command line option? */
-	    while (*++p) {                      /* Loop through characters */
-		switch (*p) {                   /* What is the character */
-		case 'a':                       /* '-a' option */
-		    findall = 1;                /* Set flag to find all solutions */
-		    break;
-		case 'c':                       /* '-c' option */
-		    printing = 0;               /* Counting, not printing */
-		    findall = 1;                /* Also forces findall option */
-		    break;
-		default:                        /* Illegal option */
-		    fprintf(stderr,"%s: Illegal option '%s'\n",progname,argv[i]);
-		    fprintf(stderr,"usage: %s [-ac] queens\n",progname);
-		    exit(-1);
-		}                               /* End of switch */
-	    }                                   /* End of loop */
-	} else {                                /* End of option test */
-	    if (sscanf(p,"%d",&queens) != 1) {  /* Read integer argument */
-		fprintf(stderr,"%s: non-integer argument '%s'\n",progname,p);
-		exit(-1);
-	    }
-	    if (queens <= 0) {                  /* N must be positive */
-		fprintf(stderr,"%s: queens must be positive integer\n",progname);
-		exit(-1);
-	    }
-	    if (queens > MAXQUEENS) {           /* N can't be too large */
-		fprintf(stderr,"%s: can't have more than %d queens\n",
-			progname, MAXQUEENS);
-		exit(-1);
-	    }
-	}                                       /* End of argument test */
-    }                                           /* End of argument scan loop */
-    if (queens == 0) {
-	fprintf(stderr,"%s: missing queens argument\n",progname);
-	fprintf(stderr,"usage: %s [-ac] queens\n",progname);
-	exit(-1);
-    }
-
-
-    ranks = files = queens;                     /* NxN board for N queens */
-    printf("%d queen%s on a %dx%d board...\n",
-	    queens, queens>1? "s" : "", ranks, files);
-    fflush(stdout);
-
-    starttime = dtime();
-
-    /*  Initialization  */
-    solutions = 0;                              /* No solutions yet */
-    for (i=0; i<MAXFILES; ++i) file[i] = EMPTY;
-    for (i=0; i<MAXDIAGS; ++i) fordiag[i] = bakdiag[i] = EMPTY;
-
-    /* Find all solutions (begin recursion) */
-    find(0);
-    if (printing && solutions) putchar('\n');
-
-    /* Report results */
-    if (solutions == 1) {
-	printf("...there is 1 solution\n");
-    } else {
-	printf("...there are %ld solutions\n", solutions);
-    }
-
-    benchtime = dtime() - starttime;
-    printf("Run Time (sec) = %9.3lf\n\n",benchtime);
-
-
-    exit(0);                                    /* No errors */
-}                                               /* End of main() */
-
-
-
-/*-------------------------- find() ----------------------------
-**  FIND is the recursive heart of the program, and finds all
-**  solutions given a set of level-1 fixed queen positions.
-**  The routine moves a single queen through all files (columns)
-**  at the current rank (recursion level).  As the queen is moved,
-**  conflict tests are made.  If the queen can be placed without
-**  conflict, then the routine recurses to the next level.  When
-**  all queens have been placed without conflict, a solution is
-**  counted and reported.
-*/
-
-void find(register int level)
-{
-    register int    f;                          /* Indexes through files */
-    register int    *fp,*fdp,*bdp;              /* Ptrs to file/diagonal entries */
-
-#ifdef  MPW                                     /* Macintosh MPW ONLY */
-    if (level & 7 == 0) {                       /* Periodically break for... */
-	SpinCursor(1);                          /* background processing */
-    }
-#endif
-
-    if (level == queens) {                      /* Placed all queens?  Stop. */
-	++solutions;                            /* Congrats, this is a solution! */
-	if (printing) pboard();                 /* Print board if printing */
-	if (!findall) exit(0);                  /* May stop after first solution */
-#ifdef  MPW                                     /* Macintosh MPW ONLY */
-	SpinCursor(1);                          /* Allow background processing */
-#endif
-    } else {                                    /* Not at final level yet */
-
-	for (                                   /* MOVE QUEEN THROUGH ALL FILES */
-	    f = 0,                              /* Queen starts at left (file 0) */
-	    fp = file,                          /* Ptr to base of file array */
-	    fdp = &fordiag[level],              /* Ptr to first fwd diag entry */
-	    bdp = &bakdiag[level+files-1]       /* Ptr to first bak diag entry */
-	;
-	    f < files                           /* Loop through all files */
-	;
-	    ++f,                                /* Advance index */
-	    ++fp, ++fdp, --bdp                  /* Advance pointers */
-	) {
-	    if (*fp >= level &&                 /* No queen on the file? */
-		*fdp >= level && *bdp >= level  /* No queens on diagonals? */
-	    ) {
-		queen[level] = f;               /* Note new position of queen */
-		*fp = *fdp = *bdp = level;      /* Place queen on file & diags */
-		find(level+1);                  /* This level OK, recurse to next */
-		*fp = *fdp = *bdp = EMPTY;      /* Remove queen from file & diags */
-	    }                                   /* End of conflict test */
-	}                                       /* End of file loop */
-    }                                           /* End if (level == queens) */
-}                                               /* End of find() */
-
-
-
-
-/*------------------------- pboard() -----------------------
-**  This routines prints the board for a particular solution.
-**  The output is sent to stdout.
-*/
-
-void pboard(void)
-{
-    register int    i,j;                        /* Rank/File indices */
-
-    if (findall) {                              /* Only if searching for all */
-	printf("\nSolution #%lu:\n",solutions); /* Print solution number */
-    }
-    for (i=0; i<ranks; ++i) {                   /* Loop through all ranks */
-	for (j=0; j<files; ++j) {               /* Loop through all files */
-	    putchar(' ');                       /* Output a space */
-	    if (j==queen[i]) putchar('Q');      /* Output Q for queen... */
-	    else putchar('-');                  /* or '-' if empty */
-	}
-	putchar('\n');                          /* Break line */
-    }
-    fflush(stdout);                             /* Flush solution to output */
-}                                               /* End of pboard() */
-
-/*****************************************************/
-/* Various timer routines.                           */
-/* Al Aburto, aburto@nosc.mil, 18 Feb 1997           */
-/*                                                   */
-/* t = dtime() outputs the current time in seconds.  */
-/* Use CAUTION as some of these routines will mess   */
-/* up when timing across the hour mark!!!            */
-/*                                                   */
-/* For timing I use the 'user' time whenever         */
-/* possible. Using 'user+sys' time is a separate     */
-/* issue.                                            */
-/*                                                   */
-/* Example Usage:                                    */
-/* [timer options added here]                        */
-/* main()                                            */
-/* {                                                 */
-/* double starttime,benchtime,dtime();               */
-/*                                                   */
-/* starttime = dtime();                              */
-/* [routine to time]                                 */
-/* benchtime = dtime() - starttime;                  */
-/* }                                                 */
-/*                                                   */
-/* [timer code below added here]                     */
-/*****************************************************/
-
-/*********************************/
-/* Timer code.                   */
-/*********************************/
-/*******************/
-/*  Amiga dtime()  */
-/*******************/
-#ifdef Amiga
-#include <ctype.h>
-#define HZ 50
-
-double dtime()
-{
- double q;
-
- struct tt
-       {
-	long  days;
-	long  minutes;
-	long  ticks;
-       } tt;
-
- DateStamp(&tt);
-
- q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ;
-
- return q;
-}
-#endif
-
-/*****************************************************/
-/*  UNIX dtime(). This is the preferred UNIX timer.  */
-/*  Provided by: Markku Kolkka, mk59200@cc.tut.fi    */
-/*  HP-UX Addition by: Bo Thide', bt@irfu.se         */
-/*****************************************************/
-#ifdef UNIX
-#include <sys/time.h>
-#include <sys/resource.h>
-
-#ifdef hpux
-#include <sys/syscall.h>
-#define getrusage(a,b) syscall(SYS_getrusage,a,b)
-#endif
-
-struct rusage rusage;
-
-double dtime()
-{
- double q;
-
- getrusage(RUSAGE_SELF,&rusage);
-
- q = (double)(rusage.ru_utime.tv_sec);
- q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06;
-
- return q;
-}
-#endif
-
-/***************************************************/
-/*  UNIX_Old dtime(). This is the old UNIX timer.  */
-/*  Make sure HZ is properly defined in param.h !! */
-/***************************************************/
-#ifdef UNIX_Old
-#include <sys/types.h>
-#include <sys/times.h>
-#include <sys/param.h>
-
-#ifndef HZ
-#define HZ 60
-#endif
-
-struct tms tms;
-
-double dtime()
-{
- double q;
-
- times(&tms);
-
- q = (double)(tms.tms_utime) / (double)HZ;
-
- return q;
-}
-#endif
-
-/*********************************************************/
-/*  VMS dtime() for VMS systems.                         */
-/*  Provided by: RAMO@uvphys.phys.UVic.CA                */
-/*  Some people have run into problems with this timer.  */
-/*********************************************************/
-#ifdef VMS
-#include time
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-struct tbuffer_t
-      {
-       int proc_user_time;
-       int proc_system_time;
-       int child_user_time;
-       int child_system_time;
-      };
-
-struct tbuffer_t tms;
-
-double dtime()
-{
- double q;
-
- times(&tms);
-
- q = (double)(tms.proc_user_time) / (double)HZ;
-
- return q;
-}
-#endif
-
-/******************************/
-/*  BORLAND C dtime() for DOS */
-/******************************/
-#ifdef BORLAND_C
-#include <ctype.h>
-#include <dos.h>
-#include <time.h>
-
-#define HZ 100
-struct time tnow;
-
-double dtime()
-{
- double q;
-
- gettime(&tnow);
-
- q = 60.0 * (double)(tnow.ti_min);
- q = q + (double)(tnow.ti_sec);
- q = q + (double)(tnow.ti_hund)/(double)HZ;
-
- return q;
-}
-#endif
-
-/**************************************/
-/*  Microsoft C (MSC) dtime() for DOS */
-/**************************************/
-#ifdef MSC
-#include <time.h>
-#include <ctype.h>
-
-#define HZ CLOCKS_PER_SEC
-clock_t tnow;
-
-double dtime()
-{
- double q;
-
- tnow = clock();
-
- q = (double)tnow / (double)HZ;
-
- return q;
-}
-#endif
-
-/*************************************/
-/*  Macintosh (MAC) Think C dtime()  */
-/*************************************/
-#ifdef MAC
-#include <time.h>
-
-#define HZ 60
-
-double dtime()
-{
- double q;
-
- q = (double)clock() / (double)HZ;
-
- return q;
-}
-#endif
-
-/************************************************************/
-/*  iPSC/860 (IPSC) dtime() for i860.                       */
-/*  Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU  */
-/************************************************************/
-#ifdef IPSC
-extern double dclock();
-
-double dtime()
-{
- double q;
-
- q = dclock();
-
- return q;
-}
-#endif
-
-/**************************************************/
-/*  FORTRAN dtime() for Cray type systems.        */
-/*  This is the preferred timer for Cray systems. */
-/**************************************************/
-#ifdef FORTRAN_SEC
-
-fortran double second();
-
-double dtime()
-{
- double q;
-
- second(&q);
-
- return q;
-}
-#endif
-
-/***********************************************************/
-/*  UNICOS C dtime() for Cray UNICOS systems.  Don't use   */
-/*  unless absolutely necessary as returned time includes  */
-/*  'user+system' time.  Provided by: R. Mike Dority,      */
-/*  dority@craysea.cray.com                                */
-/***********************************************************/
-#ifdef CTimer
-#include <time.h>
-
-double dtime()
-{
- double    q;
- clock_t   clock(void);
-
- q = (double)clock() / (double)CLOCKS_PER_SEC;
-
- return q;
-}
-#endif
-
-/********************************************/
-/* Another UNIX timer using gettimeofday(). */
-/* However, getrusage() is preferred.       */
-/********************************************/
-#ifdef GTODay
-#include <sys/time.h>
-
-struct timeval tnow;
-
-double dtime()
-{
- double q;
-
- gettimeofday(&tnow,NULL);
- q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6;
-
- return q;
-}
-#endif
-
-/*****************************************************/
-/*  Fujitsu UXP/M timer.                             */
-/*  Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */
-/*****************************************************/
-#ifdef UXPM
-#include <sys/types.h>
-#include <sys/timesu.h>
-struct tmsu rusage;
-
-double dtime()
-{
- double q;
-
- timesu(&rusage);
-
- q = (double)(rusage.tms_utime) * 1.0e-06;
-
- return q;
-}
-#endif
-
-/**********************************************/
-/*    Macintosh (MAC_TMgr) Think C dtime()    */
-/*   requires Think C Language Extensions or  */
-/*    #include <MacHeaders> in the prefix     */
-/*  provided by Francis H Schiffer 3rd (fhs)  */
-/*         skipschiffer@genie.geis.com        */
-/**********************************************/
-#ifdef MAC_TMgr
-#include <Timer.h>
-#include <stdlib.h>
-
-static TMTask   mgrTimer;
-static Boolean  mgrInited = false;
-static double   mgrClock;
-
-#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer )
-#define MAX_TIME  1800000000L
-/* MAX_TIME limits time between calls to */
-/* dtime( ) to no more than 30 minutes   */
-/* this limitation could be removed by   */
-/* creating a completion routine to sum  */
-/* 30 minute segments (fhs 1994 feb 9)   */
-
-static void Remove_timer( )
-{
- RMV_TIMER;
- mgrInited = false;
-}
-
-double  dtime( )
-{
- if( mgrInited ) {
-   RMV_TIMER;
-   mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6;
- } else {
-   if( _atexit( &Remove_timer ) == 0 ) mgrInited = true;
-   mgrClock = 0.0;
- }
-
- if ( mgrInited )
-   {
-    mgrTimer.tmAddr = NULL;
-    mgrTimer.tmCount = 0;
-    mgrTimer.tmWakeUp = 0;
-    mgrTimer.tmReserved = 0;
-    InsTime( (QElemPtr)&mgrTimer );
-    PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME );
-   }
- return( mgrClock );
-}
-#endif
-
-/***********************************************************/
-/*  Parsytec GCel timer.                                   */
-/*  Provided by: Georg Wambach, gw@informatik.uni-koeln.de */
-/***********************************************************/
-#ifdef PARIX
-#include <sys/time.h>
-
-double dtime()
-{
- double q;
-
- q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH;
-
- return q;
-}
-#endif
-
-/************************************************/
-/*  Sun Solaris POSIX dtime() routine           */
-/*  Provided by: Case Larsen, CTLarsen.lbl.gov  */
-/************************************************/
-#ifdef POSIX
-#include <sys/time.h>
-#include <sys/resource.h>
-#include <sys/rusage.h>
-
-#ifdef __hpux
-#include <sys/syscall.h>
-#endif
-
-struct rusage rusage;
-
-double dtime()
-{
- double q;
-
- getrusage(RUSAGE_SELF,&rusage);
-
- q = (double)(rusage.ru_utime.tv_sec);
- q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09;
-
- return q;
-}
-#endif
-
-
-/****************************************************/
-/*  Windows NT (32 bit) dtime() routine             */
-/*  Provided by: Piers Haken, piersh@microsoft.com  */
-/****************************************************/
-#ifdef WIN32
-#include <windows.h>
-
-double dtime(void)
-{
- double q;
-
- q = (double)GetTickCount() * 1.0e-03;
-
- return q;
-}
-#endif
-
-/*****************************************************/
-/* Time according to POSIX.1  -  <J.Pelan@qub.ac.uk> */
-/* Ref: "POSIX Programmer's Guide"  O'Reilly & Assoc.*/
-/*****************************************************/
-#ifdef POSIX1
-#define _POSIX_SOURCE 1
-#include <unistd.h>
-#include <limits.h>
-#include <sys/times.h>
-
-struct tms tms;
-
-double dtime()
-{
- double q;
- times(&tms);
- q = (double)tms.tms_utime / (double)CLK_TCK;
- return q;
-}
-#endif
-
-/*-------- End of queens.c, Say goodnight Linda! --------*/
diff --git a/lib/CPUs/MIPS/bsp/examples/r3.c b/lib/CPUs/MIPS/bsp/examples/r3.c
deleted file mode 100644
index adba0bc..0000000
--- a/lib/CPUs/MIPS/bsp/examples/r3.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/*
- *  IOCCC Raytracer by Anders Gavare.
- *
- *  The raytracer was one of the winners of the 17th IOCCC.
- *
- *  NOTE:  This is the UNOBFUSCATED version of the raytracer I used
- *         during development, not the actual entry sent to the contest.
- *
- *
- *  How to build:
- *	cc r3.c -o r3       (plus optimization flags)
- *
- *  How to run:
- *	./r3 > ray.ppm
- *  or
- *	./r3 | xv -
- */
-#include "libsys.h"
-UINT32 *pP;
-
-xsize = 800;
-ysize = 600;
-An = 1;
-
-camera_X = 0;
-camera_Y = -10;
-camera_Z = -7;
-
-scale = 1296;
-RootOfScale = 36;
-maxcolor = 255;
-
-MaxDepth=9;
-_=1<<15;
-
-/*
-double sphere_x[44] = {
-	-15,-15,-15,-15,	//  I
-	-8,-8,-10,-6,-10,-6,	//  O
-	-1,-1, 1,1,		//  C
-	 6, 6, 8,8,		//  C
-	13,13,15,15,		//  C
-	-11,-11,-11,-11,-9,-9,-7,-7,	//  r
-	0,0,-2,-2,-2,2,2,2,		//  a
-	7,7,9,9,11,11,			//  y
-	};
-double sphere_z[44] = {
-	 3,0,-3,-6,		//  I
-	 -6, 3,0,0,-3,-3,	//  O
-	  0,-3,-6, 3,		//  C
-	  0,-3,-6, 3,		//  C
-	  0,-3,-6, 3,		//  C
-	-11,-13,-15,-17,-11,-15,-13,-17,	//  r
-	-11,-15,-13,-15,-17,-13,-15,-17,	//  a
-	-11,-13,-15,-17,-11,-13,		//  y
-	};
-*/
-
-/*  Common return variable:  */
-return_var;
-return_var2;
-return_var3;
-return_var4;
-
-
-get_sphere_coordinates(b)
-{
-        return_var = "1111886:6:??AAFFHHMMOO55557799@@>>>BBBGGIIKK"[b]-64;
-        return_var3 = "C@=::C@@==@=:C@=:C@=:C531/513/5131/31/531/53"[b]-64;
-
-/*	return_var = sphere_x[b];  */
-	return_var2 = b<22? 9 : 0;
-/*	return_var3 = sphere_z[b];  */
-	return_var4 = 2;
-}
-
-
-/*  sqroot(x) returns the square root of x in return_var  */
-sqroot_sub(x, mask, guess)
-{
-	mask?
-		(
-		  guess ^= mask,
-		  guess*guess > x ?
-			( guess ^= mask )
-		      :
-			0,
-		  sqroot_sub(x, mask/2, guess)
-		)
-	    :
-		( return_var = guess );
-}
-
-
-sqroot(x)
-{
-	sqroot_sub(x, _, 0);
-}
-
-
-/*
- *  hit_sphere():
- *
- *  returns where on a sphere we hit
- *  Returns distance in hit_sphere_q. (Negative return
- *  value if we didn't hit anything.)
- */
-hit_sphere_q;
-hit_sphere(objnr, x, y, z,
-	dx, dy, dz,
-	a, b)
-{
-	get_sphere_coordinates(objnr);
-	x -= return_var*scale;
-	y -= return_var2*scale;
-	z -= return_var3*scale;
-
-	/*
-	 *  Solve the following equation:
-	 *
-	 *    q^2 (dx^2+dy^2+dz^2) + q * 2(x*dx+y*dy+z*dz)
-	 *	+ x^2+y^2+z^2 - r^2 = 0
-	 *
-	 *  We assume that |dx,dy,dz| is 1.
-	 *
-	 *    q^2 + a q + b = 0
-	 *
-	 *  The solution is (of course)
-	 *
-	 *    q = -a/2 +- sqrt(a^2/4 - b)
-	 */
-
-	b = x*x/scale+y*y/scale+z*z/scale-return_var4*return_var4*scale;
-
-	/*  a = 2*(...), and then divide by -2  */
-	a = -x*dx/scale-y*dy/scale-z*dz/scale;
-
-	hit_sphere_q =
-	    (
-		(b = a*a/scale - b) >= 0 ?
-		      (
-/*			b = scale*sqrt((double)b/(double)scale), */
-/*			sqroot(b*scale), */
-
-/*			sqroot_sub(b, _, 0),
-			b = return_var * RootOfScale,
-*/
-			sqroot_sub(b*scale, _, 0),
-			b = return_var,
-
-			/*
-			 *  Return the lowest q (a+b or a-b) which is more
-			 *  than 0.  Return negative if neither
-			 *  a+b or a-b is more than 0.
-			 */
-
-			a + (a>b? -b : b)
-		      )
-		    :
-			-1.0
-	    );
-}
-
-
-/*
- *  find_closest():
- *
- *  find_closest() scans objects and returns an index
- *  to the object which was closest (has the lowest 'q').
- *  x,y,z,dx,dy,dz are scaled.
- *  find_closest_i is the index number of the found object,
- *  -1 if none was found. find_closest_q is the distance
- *  (scaled).
- */
-find_closest_i;				/*  index  ("sphere number")  */
-find_closest_q;		/*  distance (scaled)  */
-find_closest(objnr, x, y, z,
-	dx, dy, dz, notindex)
-{
-	/*  Initialize find_closest_i on first call:  */
-	find_closest_i =
-		!objnr ? -1 : find_closest_i;
-
-	objnr < 44 ?
-		(
-		  hit_sphere(objnr, x,y,z, dx,dy,dz, 0,0),
-		  (hit_sphere_q > 0 && objnr!=notindex &&
-		      (hit_sphere_q<find_closest_q || find_closest_i<0)) ?
-			  (
-			    find_closest_q = hit_sphere_q,
-			    find_closest_i = objnr
-			  ) : 0,
-		  find_closest(objnr+1, x,y,z,dx,dy,dz, notindex)
-		)
-	    : 0;
-}
-
-
-/*
- *  trace_ray():
- *
- *  Traces one ray.  orig_xyz and dir_xyz are scaled.
- *  Return value in trace_ray_R, G, and B.
- */
-trace_ray_R;
-trace_ray_G;
-trace_ray_B;
-nX;
-nY;
-nZ;		/*  tmp normal, and tmp
-			    sphere_light calculation  */
-trace_ray(orig_x, orig_y, orig_z,
-	dir_x, dir_y, dir_z,
-	depth, notindex,
-	tmpcol, closest_i_saved)
-{
-	/*
-	 *  "Scan" through the list of all objects
-	 *  to see which one is closest:
-	 */
-
-	find_closest(0, orig_x, orig_y, orig_z,
-	    dir_x, dir_y, dir_z, notindex);
-
-	depth>0 && find_closest_i >= 0?
-	      (
-		  /*  find_closest_i and _q are the object
-		      number and distance of the object we
-		      hit.  */
-
-		  orig_x += dir_x*find_closest_q/scale,
-		  orig_y += dir_y*find_closest_q/scale,
-		  orig_z += dir_z*find_closest_q/scale,
-
-		  /*
-		   *  Calculate color  (diffuse light):
-		   *  (Note:  use nZ as a temp variable while
-		   *  calculating nY)
-		   */
-		  get_sphere_coordinates(find_closest_i),
-		  nX = orig_x - return_var*scale,
-		  nY = orig_y - return_var2*scale,
-		  nZ = orig_z - return_var3*scale,
-
-		  tmpcol = (-2*nX -2*nY + nZ) / 3,	/* sqrt(9),  */
-		  /*  Set return_var to the length of the normal
-		      vector (in this case the sphere radius)  */
-/*		  return_var = sqrt(nX*nX + nY*nY +nZ*nZ), */
-		  sqroot(nX*nX + nY*nY +nZ*nZ),
-//		  return_var = return_var4*scale,
-		  /*  divide by return_var to get the color  */
-//		  tmpcol = return_var!=0? tmpcol*scale/return_var : 0,
-		  tmpcol /= return_var4,
-
-		  /*  color is now -1..1  */
-		  tmpcol *= tmpcol,	/*  square the color 1..-1 => 1..1 */
-		  tmpcol *= 200,
-		  tmpcol /= (scale*scale),
-/*		  tmpcol += 5, */
-
-		  closest_i_saved = find_closest_i,
-
-		  /*  Mirror:  out = in - 2*(-normal)*cos v
-			where v is the angle between in and
-			-normal  */
-
-		  /*  -normal:  (normalized to len=1.0)  */
-/*		  return_var = sqrt(nX*nX + nY*nY + nZ*nZ), */
-		  return_var!=0?
-		    (
-			nX = -nX * scale / return_var,
-			nY = -nY * scale / return_var,
-			nZ = -nZ * scale / return_var
-		    ) : 0,
-
-		  /*  use return_var as a temp variable,
-		      calculate cosinus between the vectors  */
-		  return_var = (dir_x*nX + dir_y*nY + dir_z*nZ)/scale,
-/*
-		  dir_x -= 2 * nX * return_var / scale,
-		  dir_y -= 2 * nY * return_var / scale,
-		  dir_z -= 2 * nZ * return_var / scale,
-*/
-		  dir_x -= nX * return_var / (scale/2),
-		  dir_y -= nY * return_var / (scale/2),
-		  dir_z -= nZ * return_var / (scale/2),
-
-		  trace_ray(orig_x, orig_y, orig_z,
-		      dir_x, dir_y, dir_z,
-		      depth-1, find_closest_i,  0,0),
-
-		  trace_ray_R /= 2,
-		  trace_ray_G /= 2,
-		  trace_ray_B /= 2,
-/*
-		  closest_i_saved &= 7,
-		  !closest_i_saved? (closest_i_saved++) : 0,
-*/
-/*
-		  closest_i_saved = closest_i_saved<4? closest_i_saved+1 : 7,
-*/
-/*
-  tvinga gråskalor:  closest_i_saved = 7,
-*/
-closest_i_saved = closest_i_saved<22? 7 :
-	(
-		closest_i_saved<30 ? 1 :
-			(
-				closest_i_saved<38 ? 2 :
-					(
-						closest_i_saved<44 ? 4 :
-							(
-								closest_i_saved == 44 ? 6 :
-									3
-							)
-					)
-			)
-	),
-
-		  trace_ray_R += closest_i_saved & 1 ? tmpcol : 0,
-		  trace_ray_G += closest_i_saved & 2 ? tmpcol : 0,
-		  trace_ray_B += closest_i_saved & 4 ? tmpcol : 0
-	      )
-	    :
-	      (
-		/*  If we didn't hit anything, set the color anyway:  */
-
-		depth==MaxDepth?	/*  True if this is a ray originating
-					    from the camera  */
-		      (
-			orig_z += 2,
-			dir_z = orig_z > 0? orig_z / 8 : orig_z / 20
-		      )
-		    : 0,
-
-		/*
-		 *  Colors according to Horizon_1 in gimp:
-		 *  At top of sky:    13,92,146  (light blue)
-		 *  At bottom sky:    255,255,255  (white)
-		 *  Top of ground:    213,168,111 (light brown)
-		 *  Bottom of ground: 103, 55, 26 (brown)
-		 */
-
-		dir_z > 0?
-		      (
-			trace_ray_B = dir_z * dir_z / scale,
-			trace_ray_R = 255 - 250 * trace_ray_B / scale,
-			trace_ray_G = 255 - 150 * trace_ray_B / scale,
-			trace_ray_B = 255 - 100 * trace_ray_B / scale
-		      )
-		    :
-		      (
-			trace_ray_B = dir_z * dir_z / scale,
-			trace_ray_B < scale/5?
-			      (
-				trace_ray_R = 255 - 210  * trace_ray_B / scale,
-				trace_ray_G = 255 - 435 * trace_ray_B / scale,
-				trace_ray_B = 255 - 720 * trace_ray_B / scale
-			      )
-			    :
-			      (
-				trace_ray_B -= scale/5,
-				trace_ray_R = 213 - 110 * trace_ray_B / scale,
-				trace_ray_G = 168 - 113 * trace_ray_B / scale,
-				trace_ray_B = 111 - 85 * trace_ray_B / scale
-			      )
-		      ),
-
-		depth!=MaxDepth?
-		      (
-			trace_ray_R /= 2,
-			trace_ray_G /= 2,
-			trace_ray_B /= 2
-		      )
-		    : 0
-	      );
-
-	trace_ray_R = trace_ray_R<0? 0 : trace_ray_R>maxcolor? maxcolor: trace_ray_R;
-	trace_ray_G = trace_ray_G<0? 0 : trace_ray_G>maxcolor? maxcolor : trace_ray_G;
-	trace_ray_B = trace_ray_B<0? 0 : trace_ray_B>maxcolor? maxcolor : trace_ray_B;
-}
-
-
-/*
- *  do_pixels_in_line():
- *
- *  the horizontal "for loop"
- */
-R; G; B;
-dpil_helper(x,y, a,b)
-{
-	trace_ray(
-		scale*camera_X + scale*40*(An*x+a)/xsize/An - scale*20,
-		scale*camera_Y,
-		scale*camera_Z - scale*30*(An*y+b)/ysize/An + scale*15,
-		0, scale, 0, MaxDepth, -1, 0,0);
-
-	R += trace_ray_R;
-	G += trace_ray_G;
-	B += trace_ray_B;
-
-	++a<An?
-		dpil_helper(x,y,a,b)
-	    : (
-		++b<An?
-			dpil_helper(x,y,0,b)
-		    : 0
-	      );
-}
-do_pixels_in_line(x, y)
-{
-	R = G = B = 0;
-	dpil_helper(x,y,0,0);
-
-	x < xsize ?
-	    (
-		/*  output the pixel to stdout,  */
-
-#ifndef JMIPS_VGA
-		printf("%c%c%c", R/An/An, G/An/An, B/An/An),
-#else
-		pP[x+xsize*y] = (R/An/An & 0xFF) | ((G/An/An & 0xFF) << 8) | ((B/An/An & 0xFF) << 16),
-#endif
-		/*  and then do the next pixel in this line:  */
-		do_pixels_in_line(x+1, y)
-	    ) : 0;
-}
-
-
-/*
- *  do_line():
- *
- *  the vertical "for loop"
- */
-do_line(y)
-{
-	/*  Do all lines:  */
-	do_pixels_in_line(0, --y? do_line(y),y:y);
-}
-
-main()
-{
-#ifdef JMIPS_VGA
-	volatile UINT32 *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	volatile UINT32 *pVGA_front = (UINT32*)SYS_VGA_FB_FRONT;
-	volatile UINT32 *pVGA_back = (UINT32*)SYS_VGA_FB_BACK;
-	UINT64 *pPixelBuf;
-
-	xsize = Screen_get_resx();
-	ysize = Screen_get_resy();
-
-	pPixelBuf = (UINT64*)malloc(xsize*ysize*sizeof(UINT32));
-	pP = (UINT32*)pPixelBuf;
-	printf("pPixelBuf  : %8.8X\n", (UINT32)pPixelBuf);
-
-	*pVGA_front = (UINT32)pPixelBuf;
-	*pVGA_back = (UINT32)pPixelBuf;
-	*pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-
-	memset(pPixelBuf, 0, xsize*ysize*sizeof(UINT32));
-#else
-
-	/*  Output PPM file header ...  */
-	printf("P6\n%i %i\n255\n", xsize, ysize);
-
-#endif
-
-	/*  and do all lines:  */
-	do_line(ysize);
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/rad2deg.c b/lib/CPUs/MIPS/bsp/examples/rad2deg.c
deleted file mode 100644
index 74c321f..0000000
--- a/lib/CPUs/MIPS/bsp/examples/rad2deg.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-/*
-**  RAD2DEG.C - Functions to convert between radians and degrees
-*/
-
-#include <math.h>
-#include "snipmath.h"
-
-#undef rad2deg                /* These are macros defined in PI.H */
-#undef deg2rad
-
-double rad2deg(double rad)
-{
-      return (180.0 * rad / (PI));
-}
-
-double deg2rad(double deg)
-{
-      return (PI * deg / 180.0);
-}
-
-#ifdef TEST
-
-#include <stdio.h>
-
-main()
-{
-      double X;
-
-      for (X = 0.0; X <= 360.0; X += 45.0)
-            printf("%3.0f degrees = %.12f radians\n", X, deg2rad(X));
-      puts("");
-      for (X = 0.0; X <= (2 * PI + 1e-6); X += (PI / 6))
-            printf("%.12f radians = %3.0f degrees\n", X, rad2deg(X));
-      return 0;
-}
-
-#endif /* TEST */
diff --git a/lib/CPUs/MIPS/bsp/examples/random.c b/lib/CPUs/MIPS/bsp/examples/random.c
deleted file mode 100644
index c5f6615..0000000
--- a/lib/CPUs/MIPS/bsp/examples/random.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* random.c
-
-   Author: Numerical recipes (ran1, gaussian), Jon Hamkins (others)
-   Revised by: Jon Hamkins
-   Date: 4-16-98
-*/
-
-#include <math.h>
-
-#define IA 16807
-#define IM 2147483647
-#define AM (1.0/IM)
-#define IQ 127773
-#define IR 2836
-#define NTAB 32
-#define NDIV (1+(IM-1)/NTAB)
-#define EPS 1.2e-14
-#define RNMX (1.0-EPS)
-/* From Numerical Recipes, p. 280, modified from float to double */
-/* returns a uniform deviate in (0,1) */
-double ran1(long *idum)
-{
-   int j;
-   long k;
-   static long iy=0;
-   static long iv[NTAB];
-   double temp;
-
-   if (*idum <=0 || !iy) {
-      if (-(*idum) < 1) *idum=1;
-      else *idum = -(*idum);
-      for (j=NTAB+7; j>=0; j--) {
-         k=(*idum)/IQ;
-         *idum=IA*(*idum-k*IQ)-IR*k;
-         if (*idum < 0) *idum += IM;
-         if (j < NTAB) iv[j] = *idum;
-      }
-      iy = iv[0];
-   }
-   k=(*idum)/IQ;
-   *idum=IA*(*idum-k*IQ)-IR*k;
-   if (*idum < 0) *idum += IM;
-   j=iy/NDIV;
-   iy=iv[j];
-   iv[j] = *idum;
-   if ((temp=AM*iy) > RNMX) return RNMX;
-   else return temp;
-}
-#undef IA
-#undef IM
-#undef AM
-#undef IQ
-#undef IR
-#undef NTAB
-#undef NDIV
-#undef EPS
-#undef RNMX
-
-/* Generate a N(0,1) r.v. */
-double gaussian(long *idum)
-{
-    static int iset=0;
-    static double gset;
-    double fac,r,v1,v2;
-    double ran1();
-    if  (iset == 0) {
-        do {
-            v1=2.0*ran1(idum)-1.0;
-            v2=2.0*ran1(idum)-1.0;
-            r=v1*v1+v2*v2;
-        } while (r >= 1.0 || r == 0.0);
-        fac=sqrt(-2.0*log(r)/r);
-        gset=v1*fac;
-        iset=1;
-        return v2*fac;
-    } else {
-        iset=0;
-        return gset;
-    }
-}
-
-/* generate a random bit */
-int random_bit(long *idum)
-{
-  return((ran1(idum)<0.5) ? 0 : 1);
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/random.h b/lib/CPUs/MIPS/bsp/examples/random.h
deleted file mode 100644
index 673d6af..0000000
--- a/lib/CPUs/MIPS/bsp/examples/random.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* random.h */
-
-/* functions provided by random.c */
-extern double ran1(long *idum);
-extern double gaussian(long *idum);
-extern int random_bit(long *idum);
diff --git a/lib/CPUs/MIPS/bsp/examples/regdef.h b/lib/CPUs/MIPS/bsp/examples/regdef.h
deleted file mode 100644
index 60c6c2a..0000000
--- a/lib/CPUs/MIPS/bsp/examples/regdef.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1985 MIPS Computer Systems, Inc.
- * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
- * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_REGDEF_H
-#define _ASM_REGDEF_H
-
-/*
- * Symbolic register names for 32 bit ABI
- */
-#define zero			$0      /* wired zero */
-#define AT				$1      /* assembler temp  - uppercase because of ".set at" */
-#define v0				$2      /* return value */
-#define v1				$3
-#define a0				$4      /* argument registers */
-#define a1				$5
-#define a2				$6
-#define a3				$7
-#define t0				$8      /* caller saved */
-#define t1				$9
-#define t2				$10
-#define t3				$11
-#define t4				$12
-#define t5				$13
-#define t6				$14
-#define t7				$15
-#define s0				$16     /* callee saved */
-#define s1				$17
-#define s2				$18
-#define s3				$19
-#define s4				$20
-#define s5				$21
-#define s6				$22
-#define s7				$23
-#define t8				$24     /* caller saved */
-#define t9				$25
-#define jp				$25     /* PIC jump register */
-#define k0				$26     /* kernel scratch */
-#define k1				$27
-#define gp				$28     /* global pointer */
-#define sp				$29     /* stack pointer */
-#define fp				$30     /* frame pointer */
-#define s8				$30		/* same like fp! */
-#define ra				$31     /* return address */
-
-/* CP0 registers */
-#define	CP0_INDEX		$0		/* R3000 available */
-#define	CP0_RANDOM		$1		/* R3000 available */
-#define	CP0_ENTRYLO		$2		/* R3000 available */
-#define	CP0_CONTEXT		$4		/* R3000 available */
-#define	CP0_BADDR		$8		/* R3000 available */
-#define	CP0_ENTRYHI		$10		/* R3000 available */
-#define	CP0_SR			$12		/* R3000 available */
-#define	CP0_CR			$13		/* R3000 available */
-#define	CP0_EPC			$14		/* R3000 available */
-#define	CP0_PRID		$15		/* R3000 available */
-
-/* Status register masks */
-#define	SR_MASK_IEC		0x00000001
-#define	SR_MASK_KUC		0x00000002
-#define	SR_MASK_IEP		0x00000004
-#define	SR_MASK_KUP		0x00000008
-#define	SR_MASK_IEO		0x00000010
-#define	SR_MASK_KUO		0x00000020
-#define	SR_MASK_IM		0x0000FF00
-#define	SR_MASK_DS		0x00FF0000
-#define	SR_MASK_RE		0x01000000
-#define	SR_MASK_CU		0xF0000000
-
-/* Cause register masks */
-#define	CR_MASK_EXC		0x0000007C
-#define	CR_MASK_IP		0x0000FF00
-#define	CR_MASK_CE		0x40000000
-#define	CR_MASK_BD		0x80000000
-
-#endif /* _ASM_REGDEF_H */
diff --git a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c b/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c
deleted file mode 100644
index f1fdfd0..0000000
--- a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c
+++ /dev/null
@@ -1,408 +0,0 @@
-
-/*  C version of the systems programming language benchmark
-**  Author:  M. J. Jordan  Cambridge Computer Laboratory.
-**
-**  Modified by:  M. Richards, Nov 1996
-**    to be ANSI C and runnable on 64 bit machines + other minor changes
-**  Modified by:  M. Richards, 20 Oct 1998
-**    made minor corrections to improve ANSI compliance (suggested
-**    by David Levine)
-**
-**  Compile with, say
-**
-**  gcc -o bench bench.c
-**
-**  or
-**
-**  gcc -o bench100 -Dbench100 bench.c  (for a version that obeys
-**                                       the main loop 100x more often)
-*/
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#ifdef SMALL_PROBLEM_SIZE
-#define                Count           1000*1000
-#define                Qpktcountval    2326389
-#define                Holdcountval     930555
-#else
-#define                Count           10000*1000
-#define                Qpktcountval    23263894
-#define                Holdcountval     9305557
-#endif
-
-
-#define                TRUE            1
-#define                FALSE           0
-#define                MAXINT          32767
-
-#define                BUFSIZE         3
-#define                I_IDLE          1
-#define                I_WORK          2
-#define                I_HANDLERA      3
-#define                I_HANDLERB      4
-#define                I_DEVA          5
-#define                I_DEVB          6
-#define                PKTBIT          1
-#define                WAITBIT         2
-#define                HOLDBIT         4
-#define                NOTPKTBIT       !1
-#define                NOTWAITBIT      !2
-#define                NOTHOLDBIT      0XFFFB
-
-#define                S_RUN           0
-#define                S_RUNPKT        1
-#define                S_WAIT          2
-#define                S_WAITPKT       3
-#define                S_HOLD          4
-#define                S_HOLDPKT       5
-#define                S_HOLDWAIT      6
-#define                S_HOLDWAITPKT   7
-
-#define                K_DEV           1000
-#define                K_WORK          1001
-
-struct packet
-{
-    struct packet  *p_link;
-    int             p_id;
-    int             p_kind;
-    int             p_a1;
-    char            p_a2[4];
-};
-
-struct task
-{
-    struct task    *t_link;
-    int             t_id;
-    int             t_pri;
-    struct packet  *t_wkq;
-    int             t_state;
-    struct task    *(*t_fn)(struct packet *);
-    long            t_v1;
-    long            t_v2;
-};
-
-char  alphabet[28] = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ";
-struct task *tasktab[11]  =  {0,0,0,0,0,0,0,0,0,0,0};
-struct task *tasklist    =  0;
-struct task *tcb;
-long    taskid;
-long    v1;
-long    v2;
-int     qpktcount    =  0;
-int     holdcount    =  0;
-int     tracing      =  1;
-int     layout       =  0;
-
-void append(struct packet *pkt, struct packet *ptr);
-
-void createtask(int id,
-                int pri,
-                struct packet *wkq,
-                int state,
-                struct task *(*fn)(struct packet *),
-                long v1,
-                long v2)
-{
-    struct task *t = (struct task *)malloc(sizeof(struct task));
-
-    tasktab[id] = t;
-    t->t_link   = tasklist;
-    t->t_id     = id;
-    t->t_pri    = pri;
-    t->t_wkq    = wkq;
-    t->t_state  = state;
-    t->t_fn     = fn;
-    t->t_v1     = v1;
-    t->t_v2     = v2;
-    tasklist    = t;
-}
-
-struct packet *pkt(struct packet *link, int id, int kind)
-{
-    int i;
-    struct packet *p = (struct packet *)malloc(sizeof(struct packet));
-
-    for (i=0; i<=BUFSIZE; i++)
-        p->p_a2[i] = 0;
-
-    p->p_link = link;
-    p->p_id = id;
-    p->p_kind = kind;
-    p->p_a1 = 0;
-
-    return (p);
-}
-
-void trace(char a)
-{
-   if ( --layout <= 0 )
-   {
-        printf("\n");
-        layout = 50;
-    }
-
-    printf("%c", a);
-}
-
-void schedule()
-{
-    while ( tcb != 0 )
-    {
-        struct packet *pkt;
-        struct task *newtcb;
-
-        pkt=0;
-
-        switch ( tcb->t_state )
-        {
-            case S_WAITPKT:
-                pkt = tcb->t_wkq;
-                tcb->t_wkq = pkt->p_link;
-                tcb->t_state = tcb->t_wkq == 0 ? S_RUN : S_RUNPKT;
-
-            case S_RUN:
-            case S_RUNPKT:
-                taskid = tcb->t_id;
-                v1 = tcb->t_v1;
-                v2 = tcb->t_v2;
-                if (tracing==TRUE) trace(taskid+'0');
-
-                newtcb = (*(tcb->t_fn))(pkt);
-                tcb->t_v1 = v1;
-                tcb->t_v2 = v2;
-                tcb = newtcb;
-                break;
-
-            case S_WAIT:
-            case S_HOLD:
-            case S_HOLDPKT:
-            case S_HOLDWAIT:
-            case S_HOLDWAITPKT:
-                tcb = tcb->t_link;
-                break;
-
-            default:
-                return;
-        }
-    }
-}
-
-struct task *Wait(void)
-{
-    tcb->t_state |= WAITBIT;
-    return (tcb);
-}
-
-struct task *holdself(void)
-{
-    ++holdcount;
-    tcb->t_state |= HOLDBIT;
-    return (tcb->t_link) ;
-}
-
-struct task *findtcb(int id)
-{
-    struct task *t = 0;
-
-    if (1<=id && id<=(long)10)
-    t = tasktab[id];
-    if (t==0) printf("\nBad task id %d\n", id);
-    return(t);
-}
-
-struct task *release(int id)
-{
-    struct task *t;
-
-    t = findtcb(id);
-    if ( t==0 ) return (0);
-
-    t->t_state &= NOTHOLDBIT;
-    if ( t->t_pri > tcb->t_pri ) return (t);
-
-    return (tcb) ;
-}
-
-
-struct task *qpkt(struct packet *pkt)
-{
-    struct task *t;
-
-    t = findtcb(pkt->p_id);
-    if (t==0) return (t);
-
-    qpktcount++;
-
-    pkt->p_link = 0;
-    pkt->p_id = taskid;
-
-   if (t->t_wkq==0)
-    {
-        t->t_wkq = pkt;
-        t->t_state |= PKTBIT;
-        if (t->t_pri > tcb->t_pri) return (t);
-    }
-    else
-    {
-        append(pkt, (struct packet *)&(t->t_wkq));
-    }
-
-    return (tcb);
-}
-
-struct task *idlefn(struct packet *pkt)
-{
-    --v2;
-    if ( v2==0 ) return ( holdself() );
-
-    if ( (v1&1) == 0 )
-    {
-        v1 = ( v1>>1) & MAXINT;
-        return ( release(I_DEVA) );
-    }
-    else
-    {
-        v1 = ( (v1>>1) & MAXINT) ^ 0XD008;
-        return ( release(I_DEVB) );
-    }
-}
-
-struct task *workfn(struct packet *pkt)
-{
-    if ( pkt==0 ) return ( Wait() );
-    else
-    {
-        int i;
-
-        v1 = I_HANDLERA + I_HANDLERB - v1;
-        pkt->p_id = v1;
-
-        pkt->p_a1 = 0;
-        for (i=0; i<=BUFSIZE; i++)
-        {
-            v2++;
-            if ( v2 > 26 ) v2 = 1;
-            (pkt->p_a2)[i] = alphabet[v2];
-        }
-        return ( qpkt(pkt) );
-    }
-}
-
-struct task *handlerfn(struct packet *pkt)
-{
-   if ( pkt!=0) append(pkt,
-                      (struct packet *)(pkt->p_kind==K_WORK ? &v1 : &v2));
-
-   if ( v1!=0 )
-    {
-        int count;
-        struct packet *workpkt = (struct packet *)v1;
-        count = workpkt->p_a1;
-
-        if ( count > BUFSIZE )
-        {
-           v1 = (long)(((struct packet *)v1)->p_link);
-           return ( qpkt(workpkt) );
-        }
-
-        if ( v2!=0 )
-        {
-            struct packet *devpkt;
-
-            devpkt = (struct packet *)v2;
-            v2 = (long)(((struct packet *)v2)->p_link);
-            devpkt->p_a1 = workpkt->p_a2[count];
-            workpkt->p_a1 = count+1;
-            return( qpkt(devpkt) );
-        }
-    }
-    return ( Wait() );
-}
-
-struct task *devfn(struct packet *pkt)
-{
-    if ( pkt==0 )
-    {
-        if ( v1==0 ) return ( Wait() );
-        pkt = (struct packet *)v1;
-        v1 = 0;
-        return ( qpkt(pkt) );
-    }
-    else
-    {
-        v1 = (long)pkt;
-        if (tracing==TRUE) trace(pkt->p_a1);
-        return ( holdself() );
-    }
-}
-
-void append(struct packet *pkt, struct packet *ptr)
-{
-    pkt->p_link = 0;
-
-    while ( ptr->p_link ) ptr = ptr->p_link;
-
-    ptr->p_link = pkt;
-}
-
-int main()
-{
-    struct packet *wkq = 0;
-    int retval;
-
-    printf("Bench mark starting\n");
-
-    createtask(I_IDLE, 0, wkq, S_RUN, idlefn, 1, Count);
-
-    wkq = pkt(0, 0, K_WORK);
-    wkq = pkt(wkq, 0, K_WORK);
-
-    createtask(I_WORK, 1000, wkq, S_WAITPKT, workfn, I_HANDLERA, 0);
-
-    wkq = pkt(0, I_DEVA, K_DEV);
-    wkq = pkt(wkq, I_DEVA, K_DEV);
-    wkq = pkt(wkq, I_DEVA, K_DEV);
-
-    createtask(I_HANDLERA, 2000, wkq, S_WAITPKT, handlerfn, 0, 0);
-
-    wkq = pkt(0, I_DEVB, K_DEV);
-    wkq = pkt(wkq, I_DEVB, K_DEV);
-    wkq = pkt(wkq, I_DEVB, K_DEV);
-
-    createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0);
-
-    wkq = 0;
-    createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0);
-    createtask(I_DEVB, 5000, wkq, S_WAIT, devfn, 0, 0);
-
-    tcb = tasklist;
-
-    qpktcount = holdcount = 0;
-
-    printf("Starting\n");
-
-    tracing = FALSE;
-    layout = 0;
-
-    schedule();
-
-    printf("finished\n");
-
-    printf("qpkt count = %d  holdcount = %d\n",
-           qpktcount, holdcount);
-
-    printf("These results are ");
-    if (qpktcount == Qpktcountval && holdcount == Holdcountval) {
-      printf("correct");
-      retval = 0;
-    } else {
-      printf("incorrect");
-      retval = 1;
-    }
-
-    printf("\nend of run\n");
-    return retval;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.c b/lib/CPUs/MIPS/bsp/examples/rmd160.c
deleted file mode 100644
index 8b0f2c7..0000000
--- a/lib/CPUs/MIPS/bsp/examples/rmd160.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/********************************************************************\
- *
- *      FILE:     rmd160.c
- *
- *      CONTENTS: A sample C-implementation of the RIPEMD-160
- *                hash-function.
- *      TARGET:   any computer with an ANSI C compiler
- *
- *      AUTHOR:   Antoon Bosselaers, ESAT-COSIC
- *      DATE:     1 March 1996
- *      VERSION:  1.0
- *
- *      Copyright (c) Katholieke Universiteit Leuven
- *      1996, All Rights Reserved
- *
- *  Conditions for use of the RIPEMD-160 Software
- *
- *  The RIPEMD-160 software is freely available for use under the terms and
- *  conditions described hereunder, which shall be deemed to be accepted by
- *  any user of the software and applicable on any use of the software:
- *
- *  1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for
- *     all purposes be considered the owner of the RIPEMD-160 software and of
- *     all copyright, trade secret, patent or other intellectual property
- *     rights therein.
- *  2. The RIPEMD-160 software is provided on an "as is" basis without
- *     warranty of any sort, express or implied. K.U.Leuven makes no
- *     representation that the use of the software will not infringe any
- *     patent or proprietary right of third parties. User will indemnify
- *     K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities
- *     which may arise as a result of its use of the software. In no
- *     circumstances K.U.Leuven R&D will be held liable for any deficiency,
- *     fault or other mishappening with regard to the use or performance of
- *     the software.
- *  3. User agrees to give due credit to K.U.Leuven in scientific publications
- *     or communications in relation with the use of the RIPEMD-160 software
- *     as follows: RIPEMD-160 software written by Antoon Bosselaers,
- *     available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/.
- *
-\********************************************************************/
-
-/*  header files */
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "rmd160.h"
-
-/********************************************************************/
-
-void MDinit(dword *MDbuf)
-{
-   MDbuf[0] = 0x67452301UL;
-   MDbuf[1] = 0xefcdab89UL;
-   MDbuf[2] = 0x98badcfeUL;
-   MDbuf[3] = 0x10325476UL;
-   MDbuf[4] = 0xc3d2e1f0UL;
-
-   return;
-}
-
-/********************************************************************/
-
-void compress(dword *MDbuf, dword *X)
-{
-   dword aa = MDbuf[0],  bb = MDbuf[1],  cc = MDbuf[2],
-         dd = MDbuf[3],  ee = MDbuf[4];
-   dword aaa = MDbuf[0], bbb = MDbuf[1], ccc = MDbuf[2],
-         ddd = MDbuf[3], eee = MDbuf[4];
-
-   /* round 1 */
-   FF(aa, bb, cc, dd, ee, X[ 0], 11);
-   FF(ee, aa, bb, cc, dd, X[ 1], 14);
-   FF(dd, ee, aa, bb, cc, X[ 2], 15);
-   FF(cc, dd, ee, aa, bb, X[ 3], 12);
-   FF(bb, cc, dd, ee, aa, X[ 4],  5);
-   FF(aa, bb, cc, dd, ee, X[ 5],  8);
-   FF(ee, aa, bb, cc, dd, X[ 6],  7);
-   FF(dd, ee, aa, bb, cc, X[ 7],  9);
-   FF(cc, dd, ee, aa, bb, X[ 8], 11);
-   FF(bb, cc, dd, ee, aa, X[ 9], 13);
-   FF(aa, bb, cc, dd, ee, X[10], 14);
-   FF(ee, aa, bb, cc, dd, X[11], 15);
-   FF(dd, ee, aa, bb, cc, X[12],  6);
-   FF(cc, dd, ee, aa, bb, X[13],  7);
-   FF(bb, cc, dd, ee, aa, X[14],  9);
-   FF(aa, bb, cc, dd, ee, X[15],  8);
-
-   /* round 2 */
-   GG(ee, aa, bb, cc, dd, X[ 7],  7);
-   GG(dd, ee, aa, bb, cc, X[ 4],  6);
-   GG(cc, dd, ee, aa, bb, X[13],  8);
-   GG(bb, cc, dd, ee, aa, X[ 1], 13);
-   GG(aa, bb, cc, dd, ee, X[10], 11);
-   GG(ee, aa, bb, cc, dd, X[ 6],  9);
-   GG(dd, ee, aa, bb, cc, X[15],  7);
-   GG(cc, dd, ee, aa, bb, X[ 3], 15);
-   GG(bb, cc, dd, ee, aa, X[12],  7);
-   GG(aa, bb, cc, dd, ee, X[ 0], 12);
-   GG(ee, aa, bb, cc, dd, X[ 9], 15);
-   GG(dd, ee, aa, bb, cc, X[ 5],  9);
-   GG(cc, dd, ee, aa, bb, X[ 2], 11);
-   GG(bb, cc, dd, ee, aa, X[14],  7);
-   GG(aa, bb, cc, dd, ee, X[11], 13);
-   GG(ee, aa, bb, cc, dd, X[ 8], 12);
-
-   /* round 3 */
-   HH(dd, ee, aa, bb, cc, X[ 3], 11);
-   HH(cc, dd, ee, aa, bb, X[10], 13);
-   HH(bb, cc, dd, ee, aa, X[14],  6);
-   HH(aa, bb, cc, dd, ee, X[ 4],  7);
-   HH(ee, aa, bb, cc, dd, X[ 9], 14);
-   HH(dd, ee, aa, bb, cc, X[15],  9);
-   HH(cc, dd, ee, aa, bb, X[ 8], 13);
-   HH(bb, cc, dd, ee, aa, X[ 1], 15);
-   HH(aa, bb, cc, dd, ee, X[ 2], 14);
-   HH(ee, aa, bb, cc, dd, X[ 7],  8);
-   HH(dd, ee, aa, bb, cc, X[ 0], 13);
-   HH(cc, dd, ee, aa, bb, X[ 6],  6);
-   HH(bb, cc, dd, ee, aa, X[13],  5);
-   HH(aa, bb, cc, dd, ee, X[11], 12);
-   HH(ee, aa, bb, cc, dd, X[ 5],  7);
-   HH(dd, ee, aa, bb, cc, X[12],  5);
-
-   /* round 4 */
-   II(cc, dd, ee, aa, bb, X[ 1], 11);
-   II(bb, cc, dd, ee, aa, X[ 9], 12);
-   II(aa, bb, cc, dd, ee, X[11], 14);
-   II(ee, aa, bb, cc, dd, X[10], 15);
-   II(dd, ee, aa, bb, cc, X[ 0], 14);
-   II(cc, dd, ee, aa, bb, X[ 8], 15);
-   II(bb, cc, dd, ee, aa, X[12],  9);
-   II(aa, bb, cc, dd, ee, X[ 4],  8);
-   II(ee, aa, bb, cc, dd, X[13],  9);
-   II(dd, ee, aa, bb, cc, X[ 3], 14);
-   II(cc, dd, ee, aa, bb, X[ 7],  5);
-   II(bb, cc, dd, ee, aa, X[15],  6);
-   II(aa, bb, cc, dd, ee, X[14],  8);
-   II(ee, aa, bb, cc, dd, X[ 5],  6);
-   II(dd, ee, aa, bb, cc, X[ 6],  5);
-   II(cc, dd, ee, aa, bb, X[ 2], 12);
-
-   /* round 5 */
-   JJ(bb, cc, dd, ee, aa, X[ 4],  9);
-   JJ(aa, bb, cc, dd, ee, X[ 0], 15);
-   JJ(ee, aa, bb, cc, dd, X[ 5],  5);
-   JJ(dd, ee, aa, bb, cc, X[ 9], 11);
-   JJ(cc, dd, ee, aa, bb, X[ 7],  6);
-   JJ(bb, cc, dd, ee, aa, X[12],  8);
-   JJ(aa, bb, cc, dd, ee, X[ 2], 13);
-   JJ(ee, aa, bb, cc, dd, X[10], 12);
-   JJ(dd, ee, aa, bb, cc, X[14],  5);
-   JJ(cc, dd, ee, aa, bb, X[ 1], 12);
-   JJ(bb, cc, dd, ee, aa, X[ 3], 13);
-   JJ(aa, bb, cc, dd, ee, X[ 8], 14);
-   JJ(ee, aa, bb, cc, dd, X[11], 11);
-   JJ(dd, ee, aa, bb, cc, X[ 6],  8);
-   JJ(cc, dd, ee, aa, bb, X[15],  5);
-   JJ(bb, cc, dd, ee, aa, X[13],  6);
-
-   /* parallel round 1 */
-   JJJ(aaa, bbb, ccc, ddd, eee, X[ 5],  8);
-   JJJ(eee, aaa, bbb, ccc, ddd, X[14],  9);
-   JJJ(ddd, eee, aaa, bbb, ccc, X[ 7],  9);
-   JJJ(ccc, ddd, eee, aaa, bbb, X[ 0], 11);
-   JJJ(bbb, ccc, ddd, eee, aaa, X[ 9], 13);
-   JJJ(aaa, bbb, ccc, ddd, eee, X[ 2], 15);
-   JJJ(eee, aaa, bbb, ccc, ddd, X[11], 15);
-   JJJ(ddd, eee, aaa, bbb, ccc, X[ 4],  5);
-   JJJ(ccc, ddd, eee, aaa, bbb, X[13],  7);
-   JJJ(bbb, ccc, ddd, eee, aaa, X[ 6],  7);
-   JJJ(aaa, bbb, ccc, ddd, eee, X[15],  8);
-   JJJ(eee, aaa, bbb, ccc, ddd, X[ 8], 11);
-   JJJ(ddd, eee, aaa, bbb, ccc, X[ 1], 14);
-   JJJ(ccc, ddd, eee, aaa, bbb, X[10], 14);
-   JJJ(bbb, ccc, ddd, eee, aaa, X[ 3], 12);
-   JJJ(aaa, bbb, ccc, ddd, eee, X[12],  6);
-
-   /* parallel round 2 */
-   III(eee, aaa, bbb, ccc, ddd, X[ 6],  9);
-   III(ddd, eee, aaa, bbb, ccc, X[11], 13);
-   III(ccc, ddd, eee, aaa, bbb, X[ 3], 15);
-   III(bbb, ccc, ddd, eee, aaa, X[ 7],  7);
-   III(aaa, bbb, ccc, ddd, eee, X[ 0], 12);
-   III(eee, aaa, bbb, ccc, ddd, X[13],  8);
-   III(ddd, eee, aaa, bbb, ccc, X[ 5],  9);
-   III(ccc, ddd, eee, aaa, bbb, X[10], 11);
-   III(bbb, ccc, ddd, eee, aaa, X[14],  7);
-   III(aaa, bbb, ccc, ddd, eee, X[15],  7);
-   III(eee, aaa, bbb, ccc, ddd, X[ 8], 12);
-   III(ddd, eee, aaa, bbb, ccc, X[12],  7);
-   III(ccc, ddd, eee, aaa, bbb, X[ 4],  6);
-   III(bbb, ccc, ddd, eee, aaa, X[ 9], 15);
-   III(aaa, bbb, ccc, ddd, eee, X[ 1], 13);
-   III(eee, aaa, bbb, ccc, ddd, X[ 2], 11);
-
-   /* parallel round 3 */
-   HHH(ddd, eee, aaa, bbb, ccc, X[15],  9);
-   HHH(ccc, ddd, eee, aaa, bbb, X[ 5],  7);
-   HHH(bbb, ccc, ddd, eee, aaa, X[ 1], 15);
-   HHH(aaa, bbb, ccc, ddd, eee, X[ 3], 11);
-   HHH(eee, aaa, bbb, ccc, ddd, X[ 7],  8);
-   HHH(ddd, eee, aaa, bbb, ccc, X[14],  6);
-   HHH(ccc, ddd, eee, aaa, bbb, X[ 6],  6);
-   HHH(bbb, ccc, ddd, eee, aaa, X[ 9], 14);
-   HHH(aaa, bbb, ccc, ddd, eee, X[11], 12);
-   HHH(eee, aaa, bbb, ccc, ddd, X[ 8], 13);
-   HHH(ddd, eee, aaa, bbb, ccc, X[12],  5);
-   HHH(ccc, ddd, eee, aaa, bbb, X[ 2], 14);
-   HHH(bbb, ccc, ddd, eee, aaa, X[10], 13);
-   HHH(aaa, bbb, ccc, ddd, eee, X[ 0], 13);
-   HHH(eee, aaa, bbb, ccc, ddd, X[ 4],  7);
-   HHH(ddd, eee, aaa, bbb, ccc, X[13],  5);
-
-   /* parallel round 4 */
-   GGG(ccc, ddd, eee, aaa, bbb, X[ 8], 15);
-   GGG(bbb, ccc, ddd, eee, aaa, X[ 6],  5);
-   GGG(aaa, bbb, ccc, ddd, eee, X[ 4],  8);
-   GGG(eee, aaa, bbb, ccc, ddd, X[ 1], 11);
-   GGG(ddd, eee, aaa, bbb, ccc, X[ 3], 14);
-   GGG(ccc, ddd, eee, aaa, bbb, X[11], 14);
-   GGG(bbb, ccc, ddd, eee, aaa, X[15],  6);
-   GGG(aaa, bbb, ccc, ddd, eee, X[ 0], 14);
-   GGG(eee, aaa, bbb, ccc, ddd, X[ 5],  6);
-   GGG(ddd, eee, aaa, bbb, ccc, X[12],  9);
-   GGG(ccc, ddd, eee, aaa, bbb, X[ 2], 12);
-   GGG(bbb, ccc, ddd, eee, aaa, X[13],  9);
-   GGG(aaa, bbb, ccc, ddd, eee, X[ 9], 12);
-   GGG(eee, aaa, bbb, ccc, ddd, X[ 7],  5);
-   GGG(ddd, eee, aaa, bbb, ccc, X[10], 15);
-   GGG(ccc, ddd, eee, aaa, bbb, X[14],  8);
-
-   /* parallel round 5 */
-   FFF(bbb, ccc, ddd, eee, aaa, X[12] ,  8);
-   FFF(aaa, bbb, ccc, ddd, eee, X[15] ,  5);
-   FFF(eee, aaa, bbb, ccc, ddd, X[10] , 12);
-   FFF(ddd, eee, aaa, bbb, ccc, X[ 4] ,  9);
-   FFF(ccc, ddd, eee, aaa, bbb, X[ 1] , 12);
-   FFF(bbb, ccc, ddd, eee, aaa, X[ 5] ,  5);
-   FFF(aaa, bbb, ccc, ddd, eee, X[ 8] , 14);
-   FFF(eee, aaa, bbb, ccc, ddd, X[ 7] ,  6);
-   FFF(ddd, eee, aaa, bbb, ccc, X[ 6] ,  8);
-   FFF(ccc, ddd, eee, aaa, bbb, X[ 2] , 13);
-   FFF(bbb, ccc, ddd, eee, aaa, X[13] ,  6);
-   FFF(aaa, bbb, ccc, ddd, eee, X[14] ,  5);
-   FFF(eee, aaa, bbb, ccc, ddd, X[ 0] , 15);
-   FFF(ddd, eee, aaa, bbb, ccc, X[ 3] , 13);
-   FFF(ccc, ddd, eee, aaa, bbb, X[ 9] , 11);
-   FFF(bbb, ccc, ddd, eee, aaa, X[11] , 11);
-
-   /* combine results */
-   ddd += cc + MDbuf[1];               /* final result for MDbuf[0] */
-   MDbuf[1] = MDbuf[2] + dd + eee;
-   MDbuf[2] = MDbuf[3] + ee + aaa;
-   MDbuf[3] = MDbuf[4] + aa + bbb;
-   MDbuf[4] = MDbuf[0] + bb + ccc;
-   MDbuf[0] = ddd;
-
-   return;
-}
-
-/********************************************************************/
-
-void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen)
-{
-   unsigned int i;                                 /* counter       */
-   dword        X[16];                             /* message words */
-
-   memset(X, 0, 16*sizeof(dword));
-
-   /* put bytes from strptr into X */
-   for (i=0; i<(lswlen&63); i++) {
-      /* byte i goes into word X[i div 4] at pos.  8*(i mod 4)  */
-      X[i>>2] ^= (dword) *strptr++ << (8 * (i&3));
-   }
-
-   /* append the bit m_n == 1 */
-   X[(lswlen>>2)&15] ^= (dword)1 << (8*(lswlen&3) + 7);
-
-   if ((lswlen & 63) > 55) {
-      /* length goes to next block */
-      compress(MDbuf, X);
-      memset(X, 0, 16*sizeof(dword));
-   }
-
-   /* append length in bits*/
-   X[14] = lswlen << 3;
-   X[15] = (lswlen >> 29) | (mswlen << 3);
-   compress(MDbuf, X);
-
-   return;
-}
-
-/************************ end of file rmd160.c **********************/
-
diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.h b/lib/CPUs/MIPS/bsp/examples/rmd160.h
deleted file mode 100644
index 70a33a6..0000000
--- a/lib/CPUs/MIPS/bsp/examples/rmd160.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/********************************************************************\
- *
- *      FILE:     rmd160.h
- *
- *      CONTENTS: Header file for a sample C-implementation of the
- *                RIPEMD-160 hash-function. 
- *      TARGET:   any computer with an ANSI C compiler
- *
- *      AUTHOR:   Antoon Bosselaers, ESAT-COSIC
- *      DATE:     1 March 1996
- *      VERSION:  1.0
- *
- *      Copyright (c) Katholieke Universiteit Leuven
- *      1996, All Rights Reserved
- *
- *  Conditions for use of the RIPEMD-160 Software
- *
- *  The RIPEMD-160 software is freely available for use under the terms and
- *  conditions described hereunder, which shall be deemed to be accepted by
- *  any user of the software and applicable on any use of the software:
- * 
- *  1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for
- *     all purposes be considered the owner of the RIPEMD-160 software and of
- *     all copyright, trade secret, patent or other intellectual property
- *     rights therein.
- *  2. The RIPEMD-160 software is provided on an "as is" basis without
- *     warranty of any sort, express or implied. K.U.Leuven makes no
- *     representation that the use of the software will not infringe any
- *     patent or proprietary right of third parties. User will indemnify
- *     K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities
- *     which may arise as a result of its use of the software. In no
- *     circumstances K.U.Leuven R&D will be held liable for any deficiency,
- *     fault or other mishappening with regard to the use or performance of
- *     the software.
- *  3. User agrees to give due credit to K.U.Leuven in scientific publications 
- *     or communications in relation with the use of the RIPEMD-160 software 
- *     as follows: RIPEMD-160 software written by Antoon Bosselaers, 
- *     available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/.
- *
-\********************************************************************/
-
-#ifndef  RMD160H           /* make sure this file is read only once */
-#define  RMD160H
-
-/********************************************************************/
-
-/* typedef 8 and 32 bit types, resp.  */
-/* adapt these, if necessary, 
-   for your operating system and compiler */
-typedef    unsigned char        byte;
-typedef    unsigned long        dword;
-
-
-/********************************************************************/
-
-/* macro definitions */
-
-/* collect four bytes into one word: */
-#define BYTES_TO_DWORD(strptr)                    \
-            (((dword) *((strptr)+3) << 24) | \
-             ((dword) *((strptr)+2) << 16) | \
-             ((dword) *((strptr)+1) <<  8) | \
-             ((dword) *(strptr)))
-
-/* ROL(x, n) cyclically rotates x over n bits to the left */
-/* x must be of an unsigned 32 bits type and 0 <= n < 32. */
-#define ROL(x, n)        (((x) << (n)) | ((x) >> (32-(n))))
-
-/* the five basic functions F(), G() and H() */
-#define F(x, y, z)        ((x) ^ (y) ^ (z)) 
-#define G(x, y, z)        (((x) & (y)) | (~(x) & (z))) 
-#define H(x, y, z)        (((x) | ~(y)) ^ (z))
-#define I(x, y, z)        (((x) & (z)) | ((y) & ~(z))) 
-#define J(x, y, z)        ((x) ^ ((y) | ~(z)))
-  
-/* the ten basic operations FF() through III() */
-#define FF(a, b, c, d, e, x, s)        {\
-      (a) += F((b), (c), (d)) + (x);\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define GG(a, b, c, d, e, x, s)        {\
-      (a) += G((b), (c), (d)) + (x) + 0x5a827999UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define HH(a, b, c, d, e, x, s)        {\
-      (a) += H((b), (c), (d)) + (x) + 0x6ed9eba1UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define II(a, b, c, d, e, x, s)        {\
-      (a) += I((b), (c), (d)) + (x) + 0x8f1bbcdcUL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define JJ(a, b, c, d, e, x, s)        {\
-      (a) += J((b), (c), (d)) + (x) + 0xa953fd4eUL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define FFF(a, b, c, d, e, x, s)        {\
-      (a) += F((b), (c), (d)) + (x);\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define GGG(a, b, c, d, e, x, s)        {\
-      (a) += G((b), (c), (d)) + (x) + 0x7a6d76e9UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define HHH(a, b, c, d, e, x, s)        {\
-      (a) += H((b), (c), (d)) + (x) + 0x6d703ef3UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define III(a, b, c, d, e, x, s)        {\
-      (a) += I((b), (c), (d)) + (x) + 0x5c4dd124UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-#define JJJ(a, b, c, d, e, x, s)        {\
-      (a) += J((b), (c), (d)) + (x) + 0x50a28be6UL;\
-      (a) = ROL((a), (s)) + (e);\
-      (c) = ROL((c), 10);\
-   }
-
-/********************************************************************/
-
-/* function prototypes */
-
-void MDinit(dword *MDbuf);
-/*
- *  initializes MDbuffer to "magic constants"
- */
-
-void compress(dword *MDbuf, dword *X);
-/*
- *  the compression function.
- *  transforms MDbuf using message bytes X[0] through X[15]
- */
-
-void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen);
-/*
- *  puts bytes from strptr into X and pad out; appends length 
- *  and finally, compresses the last block(s)
- *  note: length in bits == 8 * (lswlen + 2^32 mswlen).
- *  note: there are (lswlen mod 64) bytes left in strptr.
- */
-
-#endif  /* RMD160H */
-
-/*********************** end of file rmd160.h ***********************/
-
diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c b/lib/CPUs/MIPS/bsp/examples/rmd160_test.c
deleted file mode 100644
index d46b86e..0000000
--- a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c
+++ /dev/null
@@ -1,113 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "libsys.h"
-
-#include "rmd160.h"
-
-#ifndef RMDsize
-#define RMDsize 160
-#endif
-
-byte *RMD(byte *message)
-/*
- * returns RMD(message)
- * message should be a string terminated by '\0'
- */
-{
-   dword         MDbuf[RMDsize/32];   /* contains (A, B, C, D(, E))   */
-   static byte   hashcode[RMDsize/8]; /* for final hash-value         */
-   dword         X[16];               /* current 16-word chunk        */
-   unsigned int  i;                   /* counter                      */
-   dword         length;              /* length in bytes of message   */
-   dword         nbytes;              /* # of bytes not yet processed */
-
-   /* initialize */
-   MDinit(MDbuf);
-   length = (dword)strlen((char *)message);
-
-   /* process message in 16-word chunks */
-   for (nbytes=length; nbytes > 63; nbytes-=64) {
-      for (i=0; i<16; i++) {
-         X[i] = BYTES_TO_DWORD(message);
-         message += 4;
-      }
-      compress(MDbuf, X);
-   }                                    /* length mod 64 bytes left */
-
-   /* finish: */
-   MDfinish(MDbuf, message, length, 0);
-
-   for (i=0; i<RMDsize/8; i+=4) {
-      hashcode[i]   =  MDbuf[i>>2];         /* implicit cast to byte  */
-      hashcode[i+1] = (MDbuf[i>>2] >>  8);  /*  extracts the 8 least  */
-      hashcode[i+2] = (MDbuf[i>>2] >> 16);  /*  significant bits.     */
-      hashcode[i+3] = (MDbuf[i>>2] >> 24);
-   }
-
-   return (byte *)hashcode;
-}
-
-#define	MSG_SIZE	(1*1024*1024)		// Bit
-#define	TIME_STEP	2
-
-char msg[MSG_SIZE/8+1];
-byte hashref[] = {0xFC,0x20,0x7B,0x84,0x40,0x1C,0x49,0x0B,0x8D,0x69,0x88,0xD2,0x49,0x20,0x01,0x90,0x41,0x77,0x72,0x59};
-
-int main (void)
-{
-	int result, i, j, cnt;
-	byte *hashcode;
-	UINT32 start, stop;
-
-	for (i=0; i < MSG_SIZE/8; i++)
-		msg[i] = 0x55;
-
-	msg[i] = 0;
-
-	setbuf(stdout, NULL);
-
-	cnt = 0;
-	while(1)
-	{
-		while (start == time(NULL));
-
-		start = time(NULL);
-		stop = start + TIME_STEP;
-
-
-		while(1)
-		{
-			hashcode = RMD((byte *)msg);
-			cnt++;
-
-			if (memcmp(hashcode, hashref, sizeof(hashref)))
-			{
-				printf("Error RipeMD-160!\n");
-				printf("Hash expected: ");
-				for (i=0; i<sizeof(hashref); i++)
-					printf("%2.2X", hashref[i]);
-
-				printf("\n");
-				printf("Hash computed: ");
-				for (i=0; i<sizeof(hashref); i++)
-					printf("%2.2X", hashcode[i]);
-
-				printf("\n");
-				return 1;
-			}
-
-			if (time(NULL) == stop)
-			{
-				for (i=0; i<sizeof(hashref); i++)
-					printf("%2.2X", hashcode[i]);
-				printf("\n%d Hashes/s of %d Mbit message in %2d s => %d Mbit/s\n\n", cnt, MSG_SIZE/(1024*1024), TIME_STEP, cnt*MSG_SIZE/(1024*1024)/TIME_STEP);
-				cnt = 0;
-				break;
-			}
-		}
-	}
-
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/round.h b/lib/CPUs/MIPS/bsp/examples/round.h
deleted file mode 100644
index 4dcbb58..0000000
--- a/lib/CPUs/MIPS/bsp/examples/round.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-/*
-** rounding macros by Dave Knapp, Thad Smith, Jon Strayer, & Bob Stout
-*/
-
-#ifndef ROUND__H
-#define ROUND__H
-
-#include <math.h>
-
-#if defined(__cplusplus) && __cplusplus
-
-/*
-** Safe C++ inline versions
-*/
-
-/* round to integer */
-
-inline int iround(double x)
-{
-      return (int)floor(x + 0.5);
-}
-
-/* round number n to d decimal points */
-
-inline double fround(double n, unsigned d)
-{
-      return floor(n * pow(10., d) + .5) / pow(10., d);
-}
-
-#else
-
-/*
-** NOTE: These C macro versions are unsafe since arguments are referenced
-**       more than once.
-**
-**       Avoid using these with expression arguments to be safe.
-*/
-
-/*
-** round to integer
-*/
-
-#define iround(x) floor((x) + 0.5)
-
-/*
-** round number n to d decimal points
-*/
-
-#define fround(n,d) (floor((n)*pow(10.,(d))+.5)/pow(10.,(d)))
-
-#endif
-
-#endif /* ROUND__H */
diff --git a/lib/CPUs/MIPS/bsp/examples/serdump.c b/lib/CPUs/MIPS/bsp/examples/serdump.c
deleted file mode 100644
index 066d0ea..0000000
--- a/lib/CPUs/MIPS/bsp/examples/serdump.c
+++ /dev/null
@@ -1,83 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <ctype.h>
-#include <time.h>
-#include "libsys.h"
-
-#define BUF_SIZE	1024
-char buffer[BUF_SIZE];
-char rxbuf[BUF_SIZE];
-char * volatile pPtr_r;
-char * volatile pPtr_w;
-UINT32 volatile timeout_cnt;
-
-void handler3(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA;
-
-	while((0x10 & *pUART_stat))
-	{
-///		sputs("w: "); print_word((int)pPtr_w); sputs("\n");
-		if (pPtr_w == &buffer[BUF_SIZE-1])
-			pPtr_w = buffer;
-		*(pPtr_w++) = *pUART_data;
-		timeout_cnt = 200;
-
-	}
-
-}
-
-int main(int argc, char **argv)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	unsigned char *fileData;
-	unsigned long file_len, state;
-
-	pPtr_r = buffer;
-	pPtr_w = buffer;
-	interrupt_register(3, handler3);
-	interrupt_enable(3);
-	*pUART_stat |= (1 << 6);
-	setbuf(stderr, NULL);
-
-	state = 0;
-	while(1)
-	{
-		fprintf(stdout,"Reading serial stream..\n");
-		file_len = 0;
-		timeout_cnt = 20000000;
-		while(timeout_cnt--)
-		{
-			sleep(1);
-		}
-		while(pPtr_w != pPtr_r)
-		{
-//			sputs("r: "); print_word((int)pPtr_r); sputs("\n");
-			if (pPtr_r == &buffer[BUF_SIZE-1])
-				pPtr_r = buffer;
-			rxbuf[file_len++] = *(pPtr_r++);
-		}
-		if (file_len)
-		{
-			PrintBuffer8(rxbuf, 16, file_len);
-		}
-		switch(state)
-		{
-			case 0:
-			if (!memcmp(rxbuf, "CLIENT", file_len))
-			{
-				fprintf(stdout,"Send response\n");
-				fprintf(stderr,"SERVER");
-				state = 1;
-			}
-			break;
-			default:
-			break;
-		}
-	}
-
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/snipmath.h b/lib/CPUs/MIPS/bsp/examples/snipmath.h
deleted file mode 100644
index 9ef5841..0000000
--- a/lib/CPUs/MIPS/bsp/examples/snipmath.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-/*
-**  SNIPMATH.H - Header file for SNIPPETS math functions and macros
-*/
-
-#ifndef SNIPMATH__H
-#define SNIPMATH__H
-
-#include <math.h>
-#include "sniptype.h"
-#include "round.h"
-
-/*
-**  Callable library functions begin here
-*/
-
-void    SetBCDLen(int n);                             /* Bcdl.C         */
-long    BCDtoLong(char *BCDNum);                      /* Bcdl.C         */
-void    LongtoBCD(long num, char BCDNum[]);           /* Bcdl.C         */
-double  bcd_to_double(void *buf, size_t len,          /* Bcdd.C         */
-                      int digits);
-int     double_to_bcd(double arg, char *buf,          /* Bcdd.C         */
-                      size_t length, size_t digits );
-DWORD   ncomb1 (int n, int m);                        /* Combin.C       */
-DWORD   ncomb2 (int n, int m);                        /* Combin.C       */
-void    SolveCubic(double a, double b, double c,      /* Cubic.C        */
-                  double d, int *solutions,
-                  double *x);
-DWORD   dbl2ulong(double t);                          /* Dbl2Long.C     */
-long    dbl2long(double t);                           /* Dbl2Long.C     */
-double  dround(double x);                             /* Dblround.C     */
-
-/* Use #defines for Permutations and Combinations     -- Factoryl.C     */
-
-#define log10P(n,r) (log10factorial(n)-log10factorial((n)-(r)))
-#define log10C(n,r) (log10P((n),(r))-log10factorial(r))
-
-double  log10factorial(double N);                     /* Factoryl.C     */
-
-double  fibo(unsigned short term);                    /* Fibo.C         */
-double  frandom(int n);                               /* Frand.C        */
-double  ipow(double x, int n);                        /* Ipow.C         */
-int     ispow2(int x);                                /* Ispow2.C       */
-long    double ldfloor(long double a);                /* Ldfloor.C      */
-int     initlogscale(long dmax, long rmax);           /* Logscale.C     */
-long    logscale(long d);                             /* Logscale.C     */
-
-float   MSBINToIEEE(float f);                         /* Msb2Ieee.C     */
-float   IEEEToMSBIN(float f);                         /* Msb2Ieee.C     */
-int     perm_index (char pit[], int size);            /* Perm_Idx.C     */
-int     round_div(int n, int d);                      /* Rnd_Div.C      */
-long    round_ldiv(long n, long d);                   /* Rnd_Div.C      */
-double  rad2deg(double rad);                          /* Rad2Deg.C      */
-double  deg2rad(double deg);                          /* Rad2Deg.C      */
-
-#include "pi.h"
-#ifndef PHI
- #define PHI      ((1.0+sqrt(5.0))/2.0)         /* the golden number    */
- #define INV_PHI  (1.0/PHI)                     /* the golden ratio     */
-#endif
-
-/*
-**  File: ISQRT.C
-*/
-
-struct int_sqrt {
-      unsigned sqrt,
-               frac;
-};
-
-void usqrt(unsigned long x, struct int_sqrt *q);
-
-
-#endif /* SNIPMATH__H */
diff --git a/lib/CPUs/MIPS/bsp/examples/sniptype.h b/lib/CPUs/MIPS/bsp/examples/sniptype.h
deleted file mode 100644
index 399935d..0000000
--- a/lib/CPUs/MIPS/bsp/examples/sniptype.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* +++Date last modified: 05-Jul-1997 */
-
-/*
-**  SNIPTYPE.H - Include file for SNIPPETS data types and commonly used macros
-*/
-
-#ifndef SNIPTYPE__H
-#define SNIPTYPE__H
-
-#include <stdlib.h>                             /* For free()           */
-#include <string.h>                             /* For NULL & strlen()  */
-
-typedef enum {Error_ = -1, Success_, False_ = 0, True_} Boolean_T;
-
-/*#if !defined(WIN32) && !defined(_WIN32) && !defined(__NT__) \
-      && !defined(_WINDOWS)
-      #if !defined(OS2)*/
-  typedef unsigned char  BYTE;
-  typedef unsigned long  DWORD;
-/* #endif*/
- typedef unsigned short WORD;
-/*#else
- #define WIN32_LEAN_AND_MEAN
- #define NOGDI
- #define NOSERVICE
- #undef INC_OLE1
- #undef INC_OLE2
- #include <windows.h>
- #define HUGE
- #endif*/
-
-#define NUL '\0'
-#define LAST_CHAR(s) (((char *)s)[strlen(s) - 1])
-#define TOBOOL(x) (!(!(x)))
-#define FREE(p) (free(p),(p)=NULL)
-
-#endif /* SNIPTYPE__H */
diff --git a/lib/CPUs/MIPS/bsp/examples/specs/specs b/lib/CPUs/MIPS/bsp/examples/specs/specs
deleted file mode 100644
index 3871b63..0000000
--- a/lib/CPUs/MIPS/bsp/examples/specs/specs
+++ /dev/null
@@ -1,147 +0,0 @@
-*asm:
-%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} %{mips16} %{mno-mips16:-no-mips16} %{mips3d} %{mno-mips3d:-no-mips3d} %{mdmx} %{mno-mdmx:-no-mdmx} %{mdsp} %{mno-dsp} %{mdspr2} %{mno-dspr2} %{msmartmips} %{mno-smartmips} %{mmt} %{mno-mt} %{mfix-vr4120} %{mfix-vr4130} %(subtarget_asm_optimizing_spec) %(subtarget_asm_debugging_spec) %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} %{mfp32} %{mfp64} %{mshared} %{mno-shared} %{msym32} %{mno-sym32} %{mtune=*} %{v} %(subtarget_asm_spec)
-
-*asm_debug:
-%{gstabs*:--gstabs}%{!gstabs*:%{g*:--gdwarf2}} %{fdebug-prefix-map=*:--debug-prefix-map %*}
-
-*asm_final:
-
-
-*asm_options:
-%{--target-help:%:print-asm-header()} %a %Y %{c:%W{o*}%{!o*:-o %w%b%O}}%{!c:-o %d%w%u%O}
-
-*invoke_as:
-%{!S:-o %|.s |
- as %(asm_options) %m.s %A }
-
-*cpp:
-%(subtarget_cpp_spec)
-
-*cpp_options:
-%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w} %{f*} %{g*:%{!g0:%{!fno-working-directory:-fworking-directory}}} %{O*} %{undef} %{save-temps:-fpch-preprocess}
-
-*cpp_debug_options:
-%{d*}
-
-*cpp_unique_options:
-%{C|CC:%{!E:%eGCC does not support -C or -CC without -E}} %{!Q:-quiet} %{nostdinc*} %{C} %{CC} %{v} %{I*&F*} %{P} %I %{MD:-MD %{!o:%b.d}%{o*:%.d%*}} %{MMD:-MMD %{!o:%b.d}%{o*:%.d%*}} %{M} %{MM} %{MF*} %{MG} %{MP} %{MQ*} %{MT*} %{!E:%{!M:%{!MM:%{!MT:%{!MQ:%{MD|MMD:%{o*:-MQ %*}}}}}}} %{remap} %{g3|ggdb3|gstabs3|gcoff3|gxcoff3|gvms3:-dD} %{H} %C %{D*&U*&A*} %{i*} %Z %i %{fmudflap:-D_MUDFLAP -include mf-runtime.h} %{fmudflapth:-D_MUDFLAP -D_MUDFLAPTH -include mf-runtime.h} %{E|M|MM:%W{o*}}
-
-*trad_capable_cpp:
-cc1 -E %{traditional|ftraditional|traditional-cpp:-traditional-cpp}
-
-*cc1:
-%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} %{save-temps: } %(subtarget_cc1_spec)
-
-*cc1_options:
-%{pg:%{fomit-frame-pointer:%e-pg and -fomit-frame-pointer are incompatible}} %1 %{!Q:-quiet} -dumpbase %B %{d*} %{m*} %{a*} %{c|S:%{o*:-auxbase-strip %*}%{!o*:-auxbase %b}}%{!c:%{!S:-auxbase %b}} %{g*} %{O*} %{W*&pedantic*} %{w} %{std*&ansi&trigraphs} %{v:-version} %{pg:-p} %{p} %{f*} %{undef} %{Qn:-fno-ident} %{--help:--help} %{--target-help:--target-help} %{--help=*:--help=%(VALUE)} %{!fsyntax-only:%{S:%W{o*}%{!o*:-o %b.s}}} %{fsyntax-only:-o %j} %{-param*} %{fmudflap|fmudflapth:-fno-builtin -fno-merge-constants} %{coverage:-fprofile-arcs -ftest-coverage}
-
-*cc1plus:
-
-
-*link_gcc_c_sequence:
-%G %L %G
-
-*link_ssp:
-%{fstack-protector|fstack-protector-all:-lssp_nonshared -lssp}
-
-*endfile:
-crtend%O%s crtn%O%s
-
-*link:
-%(endian_spec) %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} %{bestGnum} %{shared} %{non_shared}
-
-*lib:
---start-group %o -lc --end-group
-
-*mfwrap:
- %{static: %{fmudflap|fmudflapth:  --wrap=malloc --wrap=free --wrap=calloc --wrap=realloc --wrap=mmap --wrap=munmap --wrap=alloca} %{fmudflapth: --wrap=pthread_create}} %{fmudflap|fmudflapth: --wrap=main}
-
-*mflib:
-%{fmudflap|fmudflapth: -export-dynamic}
-
-*link_gomp:
-
-
-*libgcc:
--lgcc
-
-*startfile:
-crti%O%s crtbegin%O%s
-
-*switches_need_spaces:
-
-
-*cross_compile:
-1
-
-*version:
-4.3.3
-
-*multilib:
-. !msoft-float !EL !EB;soft-float msoft-float !EL !EB;el !msoft-float EL !EB;eb !msoft-float !EL EB;soft-float/el msoft-float EL !EB;soft-float/eb msoft-float !EL EB;
-
-*multilib_defaults:
-EL mips1 mabi=32
-
-*multilib_extra:
-
-
-*multilib_matches:
-mel EL;meb EB;m4650 msingle-float;msoft-float msoft-float;EL EL;EB EB;
-
-*multilib_exclusions:
-
-
-*multilib_options:
-msoft-float EL/EB
-
-*linker:
-collect2
-
-*link_libgcc:
-%D
-
-*md_exec_prefix:
-
-
-*md_startfile_prefix:
-
-
-*md_startfile_prefix_1:
-
-
-*startfile_prefix_spec:
-
-*sysroot_spec:
---sysroot=%R
-
-*sysroot_suffix_spec:
-
-
-*sysroot_hdrs_suffix_spec:
-
-
-*subtarget_cc1_spec:
-
-
-*subtarget_cpp_spec:
-
-
-*subtarget_asm_optimizing_spec:
-%{noasmopt:-O0} %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}
-
-*subtarget_asm_debugging_spec:
-%{g} %{g0} %{g1} %{g2} %{g3} %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}
-
-*subtarget_asm_spec:
-
-
-*asm_abi_default_spec:
--mabi=32
-
-*endian_spec:
-%{!EB:%{!meb:-EL}} %{EB|meb:-EB}
-
-*link_command:
-%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:    %(linker) -T link/link.ld %l %{pie:-pie} %X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}   %{s} %{t} %{u*}  %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}    %{static:} %{L*} %(mfwrap) %(link_libgcc) %{lib}   %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)    %{fprofile-arcs|fprofile-generate|coverage:-lgcov}    %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}    %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/stanford.c b/lib/CPUs/MIPS/bsp/examples/stanford.c
deleted file mode 100644
index 907477b..0000000
--- a/lib/CPUs/MIPS/bsp/examples/stanford.c
+++ /dev/null
@@ -1,1117 +0,0 @@
-/* stanford baby benchmark suite from john hennessy --
-
-There are copies all around; the MIPS performance brief has up-to-date
-numbers for a bunch of machines. BUT, these wouldn't be my first
-choice. SPEC, the industry benchmark collection group, will probably
-specify a new set of benchmarks shortly and release then right after
-that. I imagine they will include espresso, gcc, and other large, but
-public domain programs, for real things.
-
-here's bench.c
-	John Hennessy
-*/
-
-
-/*  This is a suite of benchmarks that are relatively short, both in program
-    size and execution time.  It requires no input, and prints the execution
-    time for each program, using the system- dependent routine Getclock,
-    below, to find out the current CPU time.  It does a rudimentary check to
-    make sure each program gets the right output.  These programs were
-    gathered by John Hennessy and modified by Peter Nye.
-
-4.2 VERSION   */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/times.h>
-
-#ifndef	HZ
-#define HZ	60
-#endif
-#define  nil		 0
-#define	 false		 0
-#define  true		 1
-#define  bubblebase 	 1.61
-#define  dnfbase 	 3.5
-#define  permbase 	 1.75
-#define  queensbase 	 1.83
-#define  towersbase 	 2.39
-#define  quickbase 	 1.92
-#define  intmmbase 	 1.46
-#define  treebase 	  2.5
-#define  mmbase 	 0.0
-#define  fpmmbase 	 2.92
-#define  puzzlebase 	 0.5
-#define  fftbase 	 0.0
-#define  fpfftbase 	 4.44
-    /* Towers */
-#define maxcells 	 18
-
-    /* Intmm, Mm */
-#define rowsize 	 40
-
-    /* Puzzle */
-#define size	 	 511
-#define classmax 	 3
-#define typemax 	 12
-#define d 		 8
-
-    /* Bubble, Quick */
-#define sortelements 	 5000
-#define srtelements 	 500
-
-    /* fft */
-#define fftsize 	 256
-#define fftsize2 	 129
-/*
-type */
-    /* Perm */
-#define    permrange 10
-
-   /* tree */
-struct node
-{
-    struct node *left, *right;
-    int val;
-};
-
-/* Towers *//*
-   discsizrange = 1..maxcells; */
-#define    stackrange	3
-/*    cellcursor = 0..maxcells; */
-struct element
-{
-    int discsize;
-    int next;
-};
-/*    emsgtype = packed array[1..15] of char;
-*/
-/* Intmm, Mm *//*
-   index = 1 .. rowsize;
-   intmatrix = array [index,index] of integer;
-   realmatrix = array [index,index] of real;
- */
-/* Puzzle *//*
-   piececlass = 0..classmax;
-   piecetype = 0..typemax;
-   position = 0..size;
- */
-/* Bubble, Quick *//*
-   listsize = 0..sortelements;
-   sortarray = array [listsize] of integer;
- */
-    /* FFT */
-struct complex
-{
-    float rp, ip;
-};
-/*
-    carray = array [1..fftsize] of complex ;
-    c2array = array [1..fftsize2] of complex ;
-*/
-
-float value;
-float fixed, floated;
-
-    /* global */
-int timer;
-int xtimes[11];
-int seed;
-
-    /* Perm */
-int permarray[permrange + 1];
-int pctr;
-
-    /* tree */
-struct node *tree;
-
-    /* Towers */
-int stack[stackrange + 1];
-struct element cellspace[maxcells + 1];
-int freelist, movesdone;
-
-    /* Intmm, Mm */
-int ima[rowsize + 1][rowsize + 1], imb[rowsize + 1][rowsize + 1],
-    imr[rowsize + 1][rowsize + 1];
-float rma[rowsize + 1][rowsize + 1], rmb[rowsize + 1][rowsize + 1],
-    rmr[rowsize + 1][rowsize + 1];
-
-    /* Puzzle */
-int piececount[classmax + 1],
-    class[typemax + 1],
-    piecemax[typemax + 1],
-    puzzl[size + 1], p[typemax + 1][size + 1], n, kount;
-
-    /* Bubble, Quick */
-int sortlist[sortelements + 1], biggest, littlest, top;
-
-    /* FFT */
-struct complex z[fftsize + 1], w[fftsize + 1], e[fftsize2 + 1];
-float zr, zi;
-
-/* global procedures */
-
-int
-Getclock ()
-{
-    struct tms rusage;
-    times (&rusage);
-    return ((60*rusage.tms_utime/HZ) * 50 / 3);
-};
-
-Initrand ()
-{
-    seed = 74755;
-};
-
-int
-Rand ()
-{
-    seed = (seed * 1309 + 13849) & 65535;
-    return (seed);
-};
-
-
-
-    /* Permutation program, heavily recursive, written by Denny Brown. */
-
-Swap (a, b)
-     int *a, *b;
-{
-    int t;
-    t = *a;
-    *a = *b;
-    *b = t;
-};
-
-Initialize ()
-{
-    int i;
-    for (i = 1; i <= 7; i++)
-      {
-	  permarray[i] = i - 1;
-      };
-};
-
-Permute (n)
-     int n;
-{				/* permute */
-    int k;
-    pctr = pctr + 1;
-    if (n != 1)
-      {
-	  Permute (n - 1);
-	  for (k = n - 1; k >= 1; k--)
-	    {
-		Swap (&permarray[n], &permarray[k]);
-		Permute (n - 1);
-		Swap (&permarray[n], &permarray[k]);
-	    };
-      };
-} /* permute */ ;
-
-Perm ()
-{				/* Perm */
-    int i;
-    pctr = 0;
-    for (i = 1; i <= 5; i++)
-      {
-	  Initialize ();
-	  Permute (7);
-      };
-    if (pctr != 43300)
-	printf (" Error in Perm.\n");
-} /* Perm */ ;
-
-
-
-    /*  Program to Solve the Towers of Hanoi */
-
-Error (emsg)
-     char *emsg;
-{
-    printf (" Error in Towers: %s\n", emsg);
-};
-
-Makenull (s)
-{
-    stack[s] = 0;
-};
-
-int
-Getelement ()
-{
-    int temp;
-    if (freelist > 0)
-      {
-	  temp = freelist;
-	  freelist = cellspace[freelist].next;
-      }
-    else
-	Error ("out of space   ");
-    return (temp);
-};
-
-Push (i, s)
-     int i, s;
-{
-    int errorfound, localel;
-    errorfound = false;
-    if (stack[s] > 0)
-	if (cellspace[stack[s]].discsize <= i)
-	  {
-	      errorfound = true;
-	      Error ("disc size error");
-	  };
-    if (!errorfound)
-      {
-	  localel = Getelement ();
-	  cellspace[localel].next = stack[s];
-	  stack[s] = localel;
-	  cellspace[localel].discsize = i;
-      }
-};
-
-Init (s, n)
-     int s, n;
-{
-    int discctr;
-    Makenull (s);
-    for (discctr = n; discctr >= 1; discctr--)
-	Push (discctr, s);
-};
-
-int
-Pop (s)
-     int s;
-{
-    int temp, temp1;
-    if (stack[s] > 0)
-      {
-	  temp1 = cellspace[stack[s]].discsize;
-	  temp = cellspace[stack[s]].next;
-	  cellspace[stack[s]].next = freelist;
-	  freelist = stack[s];
-	  stack[s] = temp;
-	  return (temp1);
-      }
-    else
-	Error ("nothing to pop ");
-};
-
-Move (s1, s2)
-     int s1, s2;
-{
-    Push (Pop (s1), s2);
-    movesdone = movesdone + 1;
-};
-
-tower (i, j, k)
-     int i, j, k;
-{
-    int other;
-    if (k == 1)
-	Move (i, j);
-    else
-      {
-	  other = 6 - i - j;
-	  tower (i, other, k - 1);
-	  Move (i, j);
-	  tower (other, j, k - 1);
-      }
-};
-
-
-Towers ()
-{				/* Towers */
-    int i;
-    for (i = 1; i <= maxcells; i++)
-	cellspace[i].next = i - 1;
-    freelist = maxcells;
-    Init (1, 14);
-    Makenull (2);
-    Makenull (3);
-    movesdone = 0;
-    tower (1, 2, 14);
-    if (movesdone != 16383)
-	printf (" Error in Towers.\n");
-};				/* Towers */
-
-
-    /* The eight queens problem, solved 50 times. */
-/*
-	type
-	    doubleboard =   2..16;
-	    doublenorm  =   -7..7;
-	    boardrange  =   1..8;
-	    aarray      =   array [boardrange] of boolean;
-	    barray      =   array [doubleboard] of boolean;
-	    carray      =   array [doublenorm] of boolean;
-	    xarray      =   array [boardrange] of boardrange;
-*/
-
-Try (i, q, a, b, c, x)
-     int i, *q, a[], b[], c[], x[];
-{
-    int j;
-    j = 0;
-    *q = false;
-    while ((!*q) && (j != 8))
-      {
-	  j = j + 1;
-	  *q = false;
-	  if (b[j] && a[i + j] && c[i - j + 7])
-	    {
-		x[i] = j;
-		b[j] = false;
-		a[i + j] = false;
-		c[i - j + 7] = false;
-		if (i < 8)
-		  {
-		      Try (i + 1, q, a, b, c, x);
-		      if (!*q)
-			{
-			    b[j] = true;
-			    a[i + j] = true;
-			    c[i - j + 7] = true;
-			}
-		  }
-		else
-		    *q = true;
-	    }
-      }
-};
-
-Doit ()
-{
-    int i, q;
-    int a[9], b[17], c[15], x[9];
-    i = 0 - 7;
-    while (i <= 16)
-      {
-	  if ((i >= 1) && (i <= 8))
-	      a[i] = true;
-	  if (i >= 2)
-	      b[i] = true;
-	  if (i <= 7)
-	      c[i + 7] = true;
-	  i = i + 1;
-      };
-
-    Try (1, &q, b, a, c, x);
-    if (!q)
-	printf (" Error in Queens.\n");
-};
-
-Queens ()
-{
-    int i;
-    for (i = 1; i <= 50; i++)
-	Doit ();
-};
-
-    /* Multiplies two integer matrices. */
-
-Initmatrix (m)
-     int m[rowsize + 1][rowsize + 1];
-{
-    int temp, i, j;
-    for (i = 1; i <= rowsize; i++)
-	for (j = 1; j <= rowsize; j++)
-	  {
-	      temp = Rand ();
-	      m[i][j] = temp - (temp / 120) * 120 - 60;
-	  }
-};
-
-Innerproduct (result, a, b, row, column)
-     int *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1],
-	 row, column;
-	/* computes the inner product of A[row,*] and B[*,column] */
-{
-    int i;
-    *result = 0;
-    for (i = 1; i <= rowsize; i++)
-	*result = *result + a[row][i] * b[i][column];
-};
-
-Intmm ()
-{
-    int i, j;
-    Initrand ();
-    Initmatrix (ima);
-    Initmatrix (imb);
-    for (i = 1; i <= rowsize; i++)
-	for (j = 1; j <= rowsize; j++)
-	    Innerproduct (&imr[i][j], ima, imb, i, j);
-};
-
-
-    /* Multiplies two real matrices. */
-
-rInitmatrix (m)
-     float m[rowsize + 1][rowsize + 1];
-{
-    int temp, i, j;
-    for (i = 1; i <= rowsize; i++)
-	for (j = 1; j <= rowsize; j++)
-	  {
-	      temp = Rand ();
-	      m[i][j] = (temp - (temp / 120) * 120 - 60) / 3;
-	  }
-};
-
-rInnerproduct (result, a, b, row, column)
-     float *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1];
-     int row, column;
-	/* computes the inner product of A[row,*] and B[*,column] */
-{
-    int i;
-    *result = 0.0;
-    for (i = 1; i <= rowsize; i++)
-	*result = *result + a[row][i] * b[i][column];
-};
-
-Mm ()
-{
-    int i, j;
-    Initrand ();
-    rInitmatrix (rma);
-    rInitmatrix (rmb);
-    for (i = 1; i <= rowsize; i++)
-	for (j = 1; j <= rowsize; j++)
-	    rInnerproduct (&rmr[i][j], rma, rmb, i, j);
-};
-
-
-
-
-    /* A compute-bound program from Forest Baskett. */
-
-int
-Fit (i, j)
-     int i, j;
-{
-    int k;
-    for (k = 0; k <= piecemax[i]; k++)
-	if (p[i][k])
-	    if (puzzl[j + k])
-		return (false);
-    return (true);
-};
-
-int
-Place (i, j)
-     int i, j;
-{
-    int k;
-    for (k = 0; k <= piecemax[i]; k++)
-	if (p[i][k])
-	    puzzl[j + k] = true;
-    piececount[class[i]] = piececount[class[i]] - 1;
-    for (k = j; k <= size; k++)
-	if (!puzzl[k])
-	  {
-	      return (k);
-	  };
-    return (0);
-};
-
-Remove (i, j)
-     int i, j;
-{
-    int k;
-    for (k = 0; k <= piecemax[i]; k++)
-	if (p[i][k])
-	    puzzl[j + k] = false;
-    piececount[class[i]] = piececount[class[i]] + 1;
-};
-
-int
-Trial (j)
-     int j;
-{
-    int i, k;
-    kount = kount + 1;
-    for (i = 0; i <= typemax; i++)
-	if (piececount[class[i]] != 0)
-	    if (Fit (i, j))
-	      {
-		  k = Place (i, j);
-		  if (Trial (k) || (k == 0))
-		    {
-			return (true);
-		    }
-		  else
-		      Remove (i, j);
-	      };
-    return (false);
-};
-
-Puzzle ()
-{
-    int i, j, k, m;
-    for (m = 0; m <= size; m++)
-	puzzl[m] = true;
-    for (i = 1; i <= 5; i++)
-	for (j = 1; j <= 5; j++)
-	    for (k = 1; k <= 5; k++)
-		puzzl[i + d * (j + d * k)] = false;
-    for (i = 0; i <= typemax; i++)
-	for (m = 0; m <= size; m++)
-	    p[i][m] = false;
-    for (i = 0; i <= 3; i++)
-	for (j = 0; j <= 1; j++)
-	    for (k = 0; k <= 0; k++)
-		p[0][i + d * (j + d * k)] = true;
-    class[0] = 0;
-    piecemax[0] = 3 + d * 1 + d * d * 0;
-    for (i = 0; i <= 1; i++)
-	for (j = 0; j <= 0; j++)
-	    for (k = 0; k <= 3; k++)
-		p[1][i + d * (j + d * k)] = true;
-    class[1] = 0;
-    piecemax[1] = 1 + d * 0 + d * d * 3;
-    for (i = 0; i <= 0; i++)
-	for (j = 0; j <= 3; j++)
-	    for (k = 0; k <= 1; k++)
-		p[2][i + d * (j + d * k)] = true;
-    class[2] = 0;
-    piecemax[2] = 0 + d * 3 + d * d * 1;
-    for (i = 0; i <= 1; i++)
-	for (j = 0; j <= 3; j++)
-	    for (k = 0; k <= 0; k++)
-		p[3][i + d * (j + d * k)] = true;
-    class[3] = 0;
-    piecemax[3] = 1 + d * 3 + d * d * 0;
-    for (i = 0; i <= 3; i++)
-	for (j = 0; j <= 0; j++)
-	    for (k = 0; k <= 1; k++)
-		p[4][i + d * (j + d * k)] = true;
-    class[4] = 0;
-    piecemax[4] = 3 + d * 0 + d * d * 1;
-    for (i = 0; i <= 0; i++)
-	for (j = 0; j <= 1; j++)
-	    for (k = 0; k <= 3; k++)
-		p[5][i + d * (j + d * k)] = true;
-    class[5] = 0;
-    piecemax[5] = 0 + d * 1 + d * d * 3;
-    for (i = 0; i <= 2; i++)
-	for (j = 0; j <= 0; j++)
-	    for (k = 0; k <= 0; k++)
-		p[6][i + d * (j + d * k)] = true;
-    class[6] = 1;
-    piecemax[6] = 2 + d * 0 + d * d * 0;
-    for (i = 0; i <= 0; i++)
-	for (j = 0; j <= 2; j++)
-	    for (k = 0; k <= 0; k++)
-		p[7][i + d * (j + d * k)] = true;
-    class[7] = 1;
-    piecemax[7] = 0 + d * 2 + d * d * 0;
-    for (i = 0; i <= 0; i++)
-	for (j = 0; j <= 0; j++)
-	    for (k = 0; k <= 2; k++)
-		p[8][i + d * (j + d * k)] = true;
-    class[8] = 1;
-    piecemax[8] = 0 + d * 0 + d * d * 2;
-    for (i = 0; i <= 1; i++)
-	for (j = 0; j <= 1; j++)
-	    for (k = 0; k <= 0; k++)
-		p[9][i + d * (j + d * k)] = true;
-    class[9] = 2;
-    piecemax[9] = 1 + d * 1 + d * d * 0;
-    for (i = 0; i <= 1; i++)
-	for (j = 0; j <= 0; j++)
-	    for (k = 0; k <= 1; k++)
-		p[10][i + d * (j + d * k)] = true;
-    class[10] = 2;
-    piecemax[10] = 1 + d * 0 + d * d * 1;
-    for (i = 0; i <= 0; i++)
-	for (j = 0; j <= 1; j++)
-	    for (k = 0; k <= 1; k++)
-		p[11][i + d * (j + d * k)] = true;
-    class[11] = 2;
-    piecemax[11] = 0 + d * 1 + d * d * 1;
-    for (i = 0; i <= 1; i++)
-	for (j = 0; j <= 1; j++)
-	    for (k = 0; k <= 1; k++)
-		p[12][i + d * (j + d * k)] = true;
-    class[12] = 3;
-    piecemax[12] = 1 + d * 1 + d * d * 1;
-    piececount[0] = 13;
-    piececount[1] = 3;
-    piececount[2] = 1;
-    piececount[3] = 1;
-    m = 1 + d * (1 + d * 1);
-    kount = 0;
-    if (Fit (0, m))
-	n = Place (0, m);
-    else
-	printf ("Error1 in Puzzle\n");
-    if (!Trial (n))
-	printf ("Error2 in Puzzle.\n");
-    else if (kount != 2005)
-	printf ("Error3 in Puzzle.\n");
-};
-
-
-
-    /* Sorts an array using quicksort */
-
-Initarr ()
-{
-    int i, temp;
-    Initrand ();
-    biggest = 0;
-    littlest = 0;
-    for (i = 1; i <= sortelements; i++)
-      {
-	  temp = Rand ();
-	  sortlist[i] = temp - (temp / 100000) * 100000 - 50000;
-
-	  if (sortlist[i] > biggest)
-	      biggest = sortlist[i];
-	  else if (sortlist[i] < littlest)
-	      littlest = sortlist[i];
-      };
-};
-
-Quicksort (a, l, r)
-     int a[], l, r;
-	/* quicksort the array A from start to finish */
-{
-    int i, j, x, w;
-
-    i = l;
-    j = r;
-    x = a[(l + r) / 2];
-    do
-      {
-	  while (a[i] < x)
-	      i = i + 1;
-	  while (x < a[j])
-	      j = j - 1;
-	  if (i <= j)
-	    {
-		w = a[i];
-		a[i] = a[j];
-		a[j] = w;
-		i = i + 1;
-		j = j - 1;
-	    }
-      }
-    while (i <= j);
-    if (l < j)
-	Quicksort (a, l, j);
-    if (i < r)
-	Quicksort (a, i, r);
-};
-
-
-Quick ()
-{
-    Initarr ();
-    Quicksort (sortlist, 1, sortelements);
-    if ((sortlist[1] != littlest) || (sortlist[sortelements] != biggest))
-    {
-		printf (" Error in Quick.\n");
-	}
-
-};
-
-
-    /* Sorts an array using treesort */
-
-tInitarr ()
-{
-    int i, temp;
-    Initrand ();
-    biggest = 0;
-    littlest = 0;
-    for (i = 1; i <= sortelements; i++)
-      {
-	  temp = Rand ();
-	  sortlist[i] = temp - (temp / 100000) * 100000 - 50000;
-	  if (sortlist[i] > biggest)
-	      biggest = sortlist[i];
-	  else if (sortlist[i] < littlest)
-	      littlest = sortlist[i];
-      };
-
-};
-
-CreateNode (t, n)
-     struct node **t;
-     int n;
-{
-    *t = (struct node *) malloc (sizeof (struct node));
-    (*t)->left = nil;
-    (*t)->right = nil;
-    (*t)->val = n;
-};
-
-Insert (n, t)
-     int n;
-     struct node *t;
-	/* insert n into tree */
-{
-    if (n > t->val)
-	if (t->left == nil)
-	    CreateNode (&t->left, n);
-	else
-	    Insert (n, t->left);
-    else if (n < t->val)
-	if (t->right == nil)
-	    CreateNode (&t->right, n);
-	else
-	    Insert (n, t->right);
-};
-
-int
-Checktree (p)
-     struct node *p;
-    /* check by inorder traversal */
-{
-    int result;
-    result = true;
-    if (p->left != nil)
-	if (p->left->val <= p->val)
-	    result = false;
-	else
-	    result = Checktree (p->left) && result;
-    if (p->right != nil)
-	if (p->right->val >= p->val)
-	    result = false;
-	else
-	    result = Checktree (p->right) && result;
-    return (result);
-};				/* checktree */
-
-Trees ()
-{
-    int i;
-    tInitarr ();
-    tree = (struct node *) malloc (sizeof (struct node));
-    tree->left = nil;
-    tree->right = nil;
-    tree->val = sortlist[1];
-    for (i = 2; i <= sortelements; i++)
-	Insert (sortlist[i], tree);
-    if (!Checktree (tree))
-	printf (" Error in Tree.\n");
-};
-
-
-    /* Sorts an array using bubblesort */
-
-bInitarr ()
-{
-    int i, temp;
-    Initrand ();
-    biggest = 0;
-    littlest = 0;
-    for (i = 1; i <= srtelements; i++)
-      {
-	  temp = Rand ();
-	  sortlist[i] = temp - (temp / 100000) * 100000 - 50000;
-	  if (sortlist[i] > biggest)
-	      biggest = sortlist[i];
-	  else if (sortlist[i] < littlest)
-	      littlest = sortlist[i];
-      };
-};
-
-Bubble ()
-{
-    int i, j;
-    bInitarr ();
-    top = srtelements;
-
-    while (top > 1)
-      {
-
-	  i = 1;
-	  while (i < top)
-	    {
-
-		if (sortlist[i] > sortlist[i + 1])
-		  {
-		      j = sortlist[i];
-		      sortlist[i] = sortlist[i + 1];
-		      sortlist[i + 1] = j;
-		  };
-		i = i + 1;
-	    };
-
-	  top = top - 1;
-      };
-    if ((sortlist[1] != littlest) || (sortlist[srtelements] != biggest))
-	printf ("Error3 in Bubble.\n");
-};
-
-
-float
-Cos (x)
-     float x;
-/* computes cos of x (x in radians) by an expansion */
-{
-    int i, factor;
-    float result, power;
-
-    result = 1.0;
-    factor = 1;
-    power = x;
-    for (i = 2; i <= 10; i++)
-      {
-	  factor = factor * i;
-	  power = power * x;
-	  if ((i & 1) == 0)
-	    {
-		if ((i & 3) == 0)
-		    result = result + power / factor;
-		else
-		    result = result - power / factor;
-	    };
-      };
-    return (result);
-};
-
-int
-Min0 (arg1, arg2)
-     int arg1, arg2;
-{
-    if (arg1 < arg2)
-	return (arg1);
-    else
-	return (arg2);
-};
-
-Printcomplex (arg1, arg2, zarray, start, finish, increment)
-     int arg1, arg2, start, finish, increment;
-     struct complex zarray[];
-{
-    int i;
-    printf ("\n");
-
-    i = start;
-    do
-      {
-	  printf ("  %15.3e%15.3e", zarray[i].rp, zarray[i].ip);
-	  i = i + increment;
-	  printf ("  %15.3e%15.3e", zarray[i].rp, zarray[i].ip);
-	  printf ("\n");
-	  i = i + increment;
-      }
-    while (i <= finish);
-
-};
-
-Uniform11 (iy, yfl)
-     int iy;
-     float yfl;
-{
-    iy = (4855 * iy + 1731) & 8191;
-    yfl = iy / 8192.0;
-} /* uniform */ ;
-
-Exptab (n, e)
-     int n;
-     struct complex e[];
-
-{				/* exptab */
-    float theta, divisor, h[26];
-    int i, j, k, l, m;
-
-    theta = 3.1415926536;
-    divisor = 4.0;
-    for (i = 1; i <= 25; i++)
-      {
-	  h[i] = 1 / (2 * Cos (theta / divisor));
-	  divisor = divisor + divisor;
-      };
-
-    m = n / 2;
-    l = m / 2;
-    j = 1;
-    e[1].rp = 1.0;
-    e[1].ip = 0.0;
-    e[l + 1].rp = 0.0;
-    e[l + 1].ip = 1.0;
-    e[m + 1].rp = -1.0;
-    e[m + 1].ip = 0.0;
-
-    do
-      {
-	  i = l / 2;
-	  k = i;
-
-	  do
-	    {
-		e[k + 1].rp = h[j] * (e[k + i + 1].rp + e[k - i + 1].rp);
-		e[k + 1].ip = h[j] * (e[k + i + 1].ip + e[k - i + 1].ip);
-		k = k + l;
-	    }
-	  while (k <= m);
-
-	  j = Min0 (j + 1, 25);
-	  l = i;
-      }
-    while (l > 1);
-
-} /* exptab */ ;
-
-Fft (n, z, w, e, sqrinv)
-     int n;
-     struct complex z[], w[];
-     struct complex e[];
-     float sqrinv;
-{
-    int i, j, k, l, m, index;
-    m = n / 2;
-    l = 1;
-
-    do
-      {
-	  k = 0;
-	  j = l;
-	  i = 1;
-
-	  do
-	    {
-
-		do
-		  {
-		      w[i + k].rp = z[i].rp + z[m + i].rp;
-		      w[i + k].ip = z[i].ip + z[m + i].ip;
-		      w[i + j].rp = e[k + 1].rp * (z[i].rp - z[i + m].rp)
-			  - e[k + 1].ip * (z[i].ip - z[i + m].ip);
-		      w[i + j].ip = e[k + 1].rp * (z[i].ip - z[i + m].ip)
-			  + e[k + 1].ip * (z[i].rp - z[i + m].rp);
-		      i = i + 1;
-		  }
-		while (i <= j);
-
-		k = j;
-		j = k + l;
-	    }
-	  while (j <= m);
-
-	  /*z = w ; */ index = 1;
-	  do
-	    {
-		z[index] = w[index];
-		index = index + 1;
-	    }
-	  while (index <= n);
-	  l = l + l;
-      }
-    while (l <= m);
-
-    for (i = 1; i <= n; i++)
-      {
-	  z[i].rp = sqrinv * z[i].rp;
-	  z[i].ip = -sqrinv * z[i].ip;
-      };
-
-};
-
-Oscar ()
-{				/* oscar */
-    int i;
-    Exptab (fftsize, e);
-    seed = 5767;
-    for (i = 1; i <= fftsize; i++)
-      {
-	  Uniform11 (seed, zr);
-	  Uniform11 (seed, zi);
-	  z[i].rp = 20.0 * zr - 10.0;
-	  z[i].ip = 20.0 * zi - 10.0;
-      };
-
-
-    for (i = 1; i <= 20; i++)
-      {
-	  Fft (fftsize, z, w, e, 0.0625);
-//	  Printcomplex( 6, 99, z, 1, 256, 17 );
-      };
-} /* oscar */ ;
-
-main ()
-{
-    int i;
-    fixed = 0.0;
-    floated = 0.0;
-    printf ("Starting \n");
-/* rewrite (output); */
-	setbuf(stdout, nil);
-    printf ("    Perm");
-    timer = Getclock ();
-    Perm ();
-    xtimes[1] = Getclock () - timer;
-    fixed = fixed + permbase * xtimes[1];
-    floated = floated + permbase * xtimes[1];
-    printf ("  Towers");
-    timer = Getclock ();
-    Towers ();
-    xtimes[2] = Getclock () - timer;
-    fixed = fixed + towersbase * xtimes[2];
-    floated = floated + towersbase * xtimes[2];
-    printf ("  Queens");
-    timer = Getclock ();
-    Queens ();
-    xtimes[3] = Getclock () - timer;
-    fixed = fixed + queensbase * xtimes[3];
-    floated = floated + queensbase * xtimes[3];
-    printf ("   Intmm");
-    timer = Getclock ();
-    Intmm ();
-    xtimes[4] = Getclock () - timer;
-    fixed = fixed + intmmbase * xtimes[4];
-    floated = floated + intmmbase * xtimes[4];
-    printf ("      Mm");
-    timer = Getclock ();
-    Mm ();
-    xtimes[5] = Getclock () - timer;
-    fixed = fixed + mmbase * xtimes[5];
-    floated = floated + fpmmbase * xtimes[5];
-    printf ("  Puzzle");
-    timer = Getclock ();
-    Puzzle ();
-    xtimes[6] = Getclock () - timer;
-    fixed = fixed + puzzlebase * xtimes[6];
-    floated = floated + puzzlebase * xtimes[6];
-    printf ("   Quick");
-    timer = Getclock ();
-    Quick ();
-    xtimes[7] = Getclock () - timer;
-    fixed = fixed + quickbase * xtimes[7];
-    floated = floated + quickbase * xtimes[7];
-    printf ("  Bubble");
-    timer = Getclock ();
-    Bubble ();
-    xtimes[8] = Getclock () - timer;
-    fixed = fixed + bubblebase * xtimes[8];
-    floated = floated + bubblebase * xtimes[8];
-    printf ("    Tree");
-    timer = Getclock ();
-    Trees ();
-    xtimes[9] = Getclock () - timer;
-    fixed = fixed + treebase * xtimes[9];
-    floated = floated + treebase * xtimes[9];
-    printf ("     FFT");
-    timer = Getclock ();
-    Oscar ();
-    xtimes[10] = Getclock () - timer;
-    fixed = fixed + fftbase * xtimes[10];
-    floated = floated + fpfftbase * xtimes[10];
-    printf ("\n");
-    for (i = 1; i <= 10; i++)
-	printf ("%8d", xtimes[i]);
-    printf ("\n");
-    /* compute composites */
-    printf ("\n");
-    printf ("Nonfloating point composite is %10.0f\n", fixed / 10.0);
-    printf ("\n");
-    printf ("Floating point composite is %10.0f\n", floated / 10.0);
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/startup.S b/lib/CPUs/MIPS/bsp/examples/startup.S
deleted file mode 100644
index b3eb382..0000000
--- a/lib/CPUs/MIPS/bsp/examples/startup.S
+++ /dev/null
@@ -1,87 +0,0 @@
-		.file	"startup.S"
-	
-		.section .rodata
-		.data
-argv0:		.asciz		"\"This-MIPS-program\""
-argv:		.word		argv0	
-
-		.text
-		.section .start, "ax"
-		.extern _init
-		.extern libsys_init
-		.extern _exc_vect_start
-		.extern _xcpt_handler
-		.align	2
-		.globl _start
-_start:
-		.set	noreorder
-		j	init
-		nop		
-		.set	reorder
-
-		.text
-		.set	noreorder
-init:
-		# Set stack pointer 
-		la $sp, stack_ptr
-		# Set global pointer 
-		la $gp, _gp
-
-		# zero bss
-		la $8, __bss_start
-		la $9, _end
-$zeroise:		
-		sw $0, 0($8)
-		bne $8, $9, $zeroise
-		addiu	$8, 4
-
-		# Install exception vector jump code
-		la $t1, _exc_vect_copy_start
-		la $t2, _exc_vect_copy_end
-		la $t0, _exc_vect_start
-
-$install:	lw	$v0, 0($t1)
-		addiu	$t1, 4
-		sw	$v0, 0($t0)
-		bne	$t1, $t2, $install
-		addiu	$t0, 4
-		
-		# Call _init
-		la $k0, _init
-		jalr $k0
-		nop
-		
-		# Call libsys_init
-		la $k0, libsys_init
-		jalr $k0
-		nop
-
-		# Set user-mode
-		mfc0	$a0, $12
-		li	$a1, 3
-		or	$a0, $a1
-		mtc0	$a0, $12
-		
-		# Set environment
-		li	$a0, 1
-		la	$a1, argv
-
-		# Call main
-		la $k0, main
-		jalr $k0
-		nop
-
-		# Terminate after main returns
-_terminate:	
-		nop
-		la $t0, exit
-		jalr $t0
-		move $a0, $v0
-
-_exc_vect_copy_start:
-		la $k0, _xcpt_handler
-		jr $k0
-		nop
-_exc_vect_copy_end:
-		
-		.set	reorder
diff --git a/lib/CPUs/MIPS/bsp/examples/test_ac97.c b/lib/CPUs/MIPS/bsp/examples/test_ac97.c
deleted file mode 100644
index 12dce79..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_ac97.c
+++ /dev/null
@@ -1,310 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <time.h>
-#include "libsys.h"
-
-#define	PI				3.1415926535897932384626433832795
-#define	SAMPLE_RATE		48000
-#define	BUF_SIZE		(2*4800)
-#define	REC_BUF_SIZE	(5*60*2*SAMPLE_RATE)
-
-INT32 *buffer;
-INT32 *rec_buffer;
-UINT32 buf_size;
-
-INT32 * volatile pPtr_r;
-INT32 * volatile pPtr_w;
-UINT32 gcnt, led_cnt;
-volatile INT32 sample_left, sample_right;
-
-#define	AC97_REG_RESET		0x00
-#define	AC97_REG_VOLO_MST	0x02
-#define	AC97_REG_VOLO_HP	0x04
-#define	AC97_REG_VOLO_MONO	0x06
-#define	AC97_REG_VOLI_BEEP	0x0A
-#define	AC97_REG_VOLI_PHONE	0x0C
-#define	AC97_REG_VOLI_MIC	0x0E
-#define	AC97_REG_VOLI_LINE	0x10
-#define	AC97_REG_VOLI_CD	0x12
-#define	AC97_REG_VOLI_VIDEO	0x14
-#define	AC97_REG_VOLI_AUX	0x16
-#define	AC97_REG_VOLI_PCM	0x18
-#define	AC97_REG_REC_SRC	0x1A
-#define	AC97_REG_REC_GAIN	0x1C
-#define	AC97_REG_EXTCTRL	0x2A
-#define	AC97_REG_RATE_DAC	0x2C
-#define	AC97_REG_RATE_ADC	0x32
-
-UINT32 ac97_status(UINT32 reg)
-{
-	UINT32 offset;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile UINT32 *pAC_stat_ac = (UINT32*)SYS_AC97_ACSTAT;
-
-	offset = (reg & 0x7E);
-
-	// Wait if previous command is still pending
-	while(*pAC_stat & 1);
-
-	*(pAC_stat_ac + offset) = 0;
-
-	// Wait for data valid
-	while(!(*pAC_stat & 2));
-
-	return *pAC_stat_ac;
-}
-
-void ac97_ctrl(UINT32 reg, UINT16 value)
-{
-	UINT32 offset;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile UINT32 *pAC_ctrl_ac = (UINT32*)SYS_AC97_ACCTRL;
-
-	offset = (reg & 0x7E);
-
-	// Wait if previous command is still pending
-	while(*pAC_stat & 1);
-
-	*(pAC_ctrl_ac + offset) = value;
-
-}
-
-void ac97_isr_rec(void)
-{
-	int i, size;
-	volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM;
-
-	if (!gcnt)
-	{
-		gcnt = SAMPLE_RATE;
-		*pReg = led_cnt++;
-	}
-	gcnt--;
-
-	*pPtr_w++ = pAC_pcm[3];
-	if (pPtr_w == &buffer[buf_size])
-		pPtr_w = buffer;
-
-	*pPtr_w++ = pAC_pcm[4];
-	if (pPtr_w == &buffer[buf_size])
-		pPtr_w = buffer;
-
-	CP0_TR_write(pAC_pcm[3]);
-	CP0_TR_write(pAC_pcm[4]);
-
-}
-
-void ac97_isr_play(void)
-{
-	int i, size;
-	volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM;
-
-	if (!gcnt)
-	{
-		gcnt = SAMPLE_RATE;
-		*pReg = led_cnt++;
-	}
-	gcnt--;
-
-	*pAC_pcm = *pPtr_r++;
-	if (pPtr_r == &buffer[buf_size])
-		pPtr_r = buffer;
-}
-
-void ac97_isr_pass(void)
-{
-	int i, size;
-	volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile INT32 *pAC_pcm = (INT32*)SYS_AC97_PCM;
-
-	if (!gcnt)
-	{
-		gcnt = SAMPLE_RATE;
-		*pReg = led_cnt++;
-	}
-	gcnt--;
-
-	if (*pAC_stat & 0x08)
-	{
-
-//		CP0_TR_write(pAC_pcm[3]);
-//		CP0_TR_write(pAC_pcm[4]);
-
-		*pPtr_w++ = pAC_pcm[3];
-		if (pPtr_w == &buffer[buf_size])
-			pPtr_w = buffer;
-
-		*pPtr_w++ = pAC_pcm[4];
-		if (pPtr_w == &buffer[buf_size])
-			pPtr_w = buffer;
-	}
-
-	if (pPtr_r != pPtr_w)
-	{
-		*pAC_pcm = *pPtr_r++;
-		if (pPtr_r == &buffer[buf_size])
-			pPtr_r = buffer;
-	}
-
-}
-
-int main (void)
-{
-	int result, i, j;
-	volatile UINT32 *pReg = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pGPIO1 = (UINT32*)SYS_GPIO1;
-	volatile UINT32 *pAC_ctrl = (UINT32*)SYS_AC97_CTRL;
-	volatile UINT32 *pAC_stat = (UINT32*)SYS_AC97_STAT;
-	volatile UINT32 *pAC_ctrl_ac = (UINT32*)SYS_AC97_ACCTRL;
-	volatile UINT32 *pAC_stat_ac = (UINT32*)SYS_AC97_ACSTAT;
-	volatile UINT32 *pAC_pcm = (UINT32*)SYS_AC97_PCM;
-	double phi, dphi, y, mean;
-	char sel, cmd;
-	char buf[1024];
-	FILE *pFile = stdout;
-
-//	setbuf(stderr, NULL);
-//
-	fprintf(pFile, "AC-97 Test\n");
-	fprintf(pFile, "Status         : %8.8X\n", *pAC_ctrl);
-
-	ac97_ctrl(AC97_REG_VOLO_MST, 0);
-	ac97_ctrl(AC97_REG_VOLO_HP, 0);
-	ac97_ctrl(AC97_REG_VOLI_LINE, 0x8808);
-	ac97_ctrl(AC97_REG_VOLI_PCM, 0x0808);
-	ac97_ctrl(AC97_REG_REC_SRC, 0x0404);
-	ac97_ctrl(AC97_REG_REC_GAIN, 0);
-	ac97_ctrl(AC97_REG_EXTCTRL, 1);
-
-	ac97_ctrl(AC97_REG_RATE_DAC, SAMPLE_RATE);
-	ac97_ctrl(AC97_REG_RATE_ADC, SAMPLE_RATE);
-
-	led_cnt = 0;
-	gcnt = SAMPLE_RATE;
-
-	fprintf(pFile, "DAC-Rate       : %d\n", ac97_status(AC97_REG_RATE_DAC));
-	fprintf(pFile, "ADC-Rate       : %d\n", ac97_status(AC97_REG_RATE_ADC));
-
-	*pGPIO1	= 0x04;
-
-	while(1)
-	{
-		fprintf(pFile, "Aufnehmen und Abspielen (1)\n");
-		fprintf(pFile, "Sinus Ton               (2)\n");
-		fprintf(pFile, "Pass through            (3)\n");
-		fprintf(pFile, "Eingabe: ");
-
-		scanf("%c", &sel);
-//		sel = 0x31;
-
-		if (sel == 0x31)
-		{
-			buf_size = REC_BUF_SIZE;
-			buffer = (INT32*)malloc(REC_BUF_SIZE*sizeof(INT32));
-//			memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32)));
-			pPtr_r = buffer;
-			pPtr_w = buffer;
-
-			ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808);
-
-			cmd = 0;
-			while(1)
-			{
-				switch (cmd)
-				{
-					case 'r':
-					ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808);
-					pPtr_w = buffer;
-					fprintf(pFile, "Aufnahme\n");
-					interrupt_register(5, ac97_isr_rec);
-					interrupt_enable(5);
-					*pAC_ctrl = 0x24;
-					break;
-
-					case 'p':
-					ac97_ctrl(AC97_REG_VOLI_LINE, 0x8808);
-					pPtr_r = buffer;
-					fprintf(pFile, "Wiedergabe\n");
-					interrupt_register(5, ac97_isr_play);
-					interrupt_enable(5);
-					*pAC_ctrl = 0x12;
-					break;
-
-					case ' ':
-					ac97_ctrl(AC97_REG_VOLI_LINE, 0x0808);
-					fprintf(pFile, "Stop\n");
-					memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32)));
-					*pAC_ctrl = 0x00;
-					pPtr_r = buffer;
-					pPtr_w = buffer;
-					break;
-
-					default:
-						fprintf(pFile, "Aufnahme   (R)\n");
-						fprintf(pFile, "Wiedergabe (P)\n");
-						fprintf(pFile, "Stop       (Space)\n");
-					break;
-				}
-				cmd = readchar(0);
-			}
-		}
-		if (sel == 0x32)
-		{
-			buf_size = BUF_SIZE;
-			buffer = (INT32*)malloc(REC_BUF_SIZE*sizeof(INT32));
-			memset(buffer, 0, sizeof(REC_BUF_SIZE*sizeof(INT32)));
-			pPtr_r = buffer;
-			pPtr_w = buffer;
-
-			dphi = 120*2*PI/BUF_SIZE;
-			phi = 0;
-			for (i=0; i < BUF_SIZE/2; i++)
-			{
-				y = cos(phi);
-				buffer[2*i+0] = (INT32)(32000*y);
-				buffer[2*i+1] = (INT32)(32000*y);
-				phi = fmod((phi + dphi), 2.0*PI);
-			}
-
-			fprintf(stderr, "Status         : %8.8X\n", *pAC_ctrl);
-
-			interrupt_register(5, ac97_isr_play);
-			interrupt_enable(5);
-			*pAC_ctrl = 0x12;
-
-			fprintf(stderr, "Status         : %8.8X\n", *pAC_ctrl);
-
-			while(1)
-			{
-				fprintf(stderr, "Status         : %8.8X\n", *pAC_ctrl);
-			}
-		}
-		if (sel == 0x33)
-		{
-
-			buf_size = BUF_SIZE;
-			buffer = (INT32*)malloc(BUF_SIZE*sizeof(INT32));
-			memset(buffer, 0, sizeof(BUF_SIZE*sizeof(INT32)));
-			pPtr_r = buffer;
-			pPtr_w = buffer;
-			*pAC_ctrl = 0x32;
-			interrupt_register(5, ac97_isr_pass);
-			interrupt_enable(5);
-
-			fprintf(stdout, "Status         : %8.8X\n", *pAC_ctrl);
-
-			while(1);
-		}
-	}
-
-	return 0;
-
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/test_dcache.c b/lib/CPUs/MIPS/bsp/examples/test_dcache.c
deleted file mode 100644
index 74327d1..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_dcache.c
+++ /dev/null
@@ -1,61 +0,0 @@
-#include <stdlib.h>
-#include <stdio.h>
-#include "libsys.h"
-#include "libsys.h"
-
-UINT32 tset(UINT32 *pMem)
-{
-
-	__asm__
-	(
-		".set	noreorder\n"
-		".set	nomacro\n"
-		"addiu  $t1, $0, 0x5555\n"
-		"lw     $t0, 0(%[pMem])\n"
-		"sw     $t1, 24(%[pMem])\n"
-		"addiu	$t0, 8\n"
-		"sw     $t0, 0(%[pMem])\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"lw     $v0, 24(%[pMem])\n"
-		".set	macro\n"
-		".set	reorder\n"
-		:
-		: [pMem] "r" (pMem)
-		: "t0", "t1"
-	);
-}
-
-int main(void)
-{
-	int i;
-	volatile int *pLED = (int*)SYS_LED_PORT;
-	UINT64 *pBuf64;
-	UINT32 *pPtr;
-
-	pBuf64 = (UINT64*)0x4000FC80; //malloc(1024*sizeof(UINT32));
-
-	pPtr = (UINT32*)pBuf64;
-
-	for(i=0; i < 1024; i++)
-		*pPtr++ = i;
-
-	pPtr = (UINT32*)pBuf64;
-	sputs("Ptr: "); print_word((int)pPtr); sputs("\n");
-	DCACHE_invalidate_all();
-
-
-	*pLED = tset(pPtr);
-
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/test_endianess.c b/lib/CPUs/MIPS/bsp/examples/test_endianess.c
deleted file mode 100644
index 8f0d737..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_endianess.c
+++ /dev/null
@@ -1,64 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "libsys.h"
-
-#define TEST_SIZE	32768
-int main (void)
-{
-	int i;
-	UINT16 *ram16;
-	UINT32 sr;
-	UINT32 volatile *pReg = (UINT32*)SYS_LED_PORT;
-
-	*pReg = 0;
-
-	sr = CP0_SR_read();
-
-	ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16));
-
-	CP0_SR_write(sr | (1 << 25));
-
-	for (i=0; i < TEST_SIZE/2; i++)
-		ram16[i] = (UINT16)i;
-
-	for (i=TEST_SIZE/2-1; i >= 0; i--)
-		if (ram16[i] != (UINT16)i)
-			break;
-
-	i++;
-	if (i)
-		*pReg = 0xFFFFFFFF;
-	else
-		*pReg = 1;
-
-
-	free(ram16);
-
-	ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16));
-
-	*pReg = 0;
-	CP0_SR_write(sr & ~(1 << 25));
-
-	for (i=0; i < TEST_SIZE/2; i++)
-		ram16[i] = (UINT16)i;
-
-	for (i=TEST_SIZE/2-1; i >= 0; i--)
-		if (ram16[i] != (UINT16)i)
-			break;
-
-	i++;
-	if (i)
-		*pReg = 0xFFFFFFFF;
-	else
-		*pReg = 1;
-
-
-	free(ram16);
-
-
-//	sputs("Status : ");print_word(sr);sputs("\n");
-
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/test_exception.c b/lib/CPUs/MIPS/bsp/examples/test_exception.c
deleted file mode 100644
index 34a0bca..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_exception.c
+++ /dev/null
@@ -1,282 +0,0 @@
-#include <stdlib.h>
-#include <stdio.h>
-#include "libsys.h"
-
-void _exc_break(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"break 0x9\n"
-		".set	reorder\n"
-
-	);
-}
-
-void _exc_syscall(UINT32 code, UINT32 arg)
-{
-	__asm
-	(
-		"move   $v0, %[code]\n"
-		"move   $a0, %[arg]\n"
-		"syscall\n"
-		:
-		: [code] "r" (code), [arg] "r" (arg)
-		: "v0", "a0"
-
-	);
-}
-
-void _exc_arith(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x7FFFFFFF\n"
-		" addi  $t1, $t0, 2\n"
-		".set	reorder\n"
-
-	);
-}
-
-void _exc_store_err(void)
-{
-	volatile int *pSrc = (int*)SYS_TIMER_SEC;
-	volatile int *pDst = (int*)0x40000001;
-
-	*pDst = *pSrc;
-
-}
-
-void _exc_load_err(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x40000000\n"
-		" li	$t1, 0x40000000\n"
-		" lw 	$t1, 0($t1)\n"
-		" lw 	$t0, 2($t0)\n"
-		" lw 	$t1, 4($t0)\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_kaddr_err(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x80000000\n"
-		" jr    $t0\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_iaddr_daddr_err(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x40000003\n"
-		" li	$t1, 0x40000002\n"
-		" jr    $t0\n"
-		" lw 	$t1, 0($t1)\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_daddr_iaddr_err(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x40000003\n"
-		" li	$t1, 0x40000002\n"
-		" lw 	$t1, 0($t1)\n"
-		" jr    $t0\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_iaddr_err(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x40000003\n"
-		" jr    $t0\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_ri(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t0, 0x40010000\n"
-		" li	$t1, 0x9c563442\n"
-		" sw	$t1, 0($t0)\n"
-		" jr    $t0\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_ibe(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t1, 0x10000000\n"
-		" jr    $t1\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void _exc_dbe(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		" li	$t1, 0x10000000\n"
-		" lw	$t0, 0($t1)\n"
-		"nop\n"
-		" jr    $t0\n"
-		"nop\n"
-		".set	reorder\n"
-
-	);
-
-}
-
-void handler0(void)
-{
-	printf("Interrupt 0\n");
-	interrupt_clr(0);
-}
-
-void handler1(void)
-{
-	printf("Interrupt 1\n");
-	interrupt_clr(1);
-}
-
-int main(void)
-{
-	int buf[256];
-	int i, sel;
-
-	interrupt_register(0, handler0);
-	interrupt_enable(0);
-	interrupt_register(1, handler1);
-	interrupt_enable(1);
-
-	while(1)
-	{
-		printf("Welche exception möchten Sie testen?\n");
-		printf(" 1 : Reserved instruction\n");
-		printf(" 2 : Privileged address (BadVAddr = 0x80000000)\n");
-		printf(" 3 : Arithmetic overflow\n");
-		printf(" 4 : Syscall\n");
-		printf(" 5 : Breakpoint\n");
-		printf(" 6 : Load error on instruction (BadVAddr = 0x40000003)\n");
-		printf(" 7 : Load error on data (BadVAddr = 0x40000002)\n");
-		printf(" 8 : Store error on data (BadVAddr = 0x40000001)\n");
-		printf(" 9 : Bus error on instruction\n");
-		printf("10 : Bus error on data\n");
-		printf("11 : SW-interrupt 0\n");
-		printf("12 : SW-interrupt 1\n");
-		printf("13 : Load error on instruction and Load error on data (BadVAddr = 0x40000003)\n");
-		printf("14 : Load error on data and Load error on instruction (BadVAddr = 0x40000002)\n");
-
-		scanf("%d", &sel);
-		printf("Jetzt kommt die exception (%d)!\n", sel);
-
-		switch(sel)
-		{
-			case 1:
-			_exc_ri();
-			break;
-
-			case 2:
-			_exc_kaddr_err();
-			break;
-
-			case 3:
-			_exc_arith();
-			break;
-
-			case 4:
-			_exc_syscall(4, (UINT32)((char*)"Hallo Syscall ("));
-			_exc_syscall(1, 12345678);
-			_exc_syscall(4, (UINT32)((char*)")\n"));
-			break;
-
-			case 5:
-			_exc_break();
-			break;
-
-			case 6:
-			_exc_iaddr_err();
-			break;
-
-			case 7:
-			_exc_load_err();
-			break;
-
-			case 8:
-			_exc_store_err();
-			break;
-
-			case 9:
-			printf("IBE: Exception not implemented in current CPU!\nPush reset to restart!\n");
-			_exc_ibe();
-			break;
-
-			case 10:
-			printf("DBE: Exception not implemented in current CPU!\nPush reset to restart!\n");
-			_exc_dbe();
-			break;
-
-			case 11:
-			case 12:
-			interrupt_set(sel-11);
-			break;
-
-			case 13:
-			_exc_iaddr_daddr_err();
-			break;
-
-			case 14:
-			_exc_daddr_iaddr_err();
-			break;
-
-			default:
-			break;
-		}
-		sel = 0;
-	}
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/test_flash.c b/lib/CPUs/MIPS/bsp/examples/test_flash.c
deleted file mode 100644
index 7d40961..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_flash.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/************************************************************************/
-/*                                                                      */
-/*  AMD CFI Enabled Flash Memory Drivers                                */
-/*  File name: CFIDRIVE.C                                               */
-/*  Revision:  1.0  5/07/98                                             */
-/*                                                                      */
-/* Copyright (c) 1998 ADVANCED MICRO DEVICES, INC. All Rights Reserved. */
-/* This software is unpublished and contains the trade secrets and      */
-/* confidential proprietary information of AMD. Unless otherwise        */
-/* provided in the Software Agreement associated herewith, it is        */
-/* licensed in confidence "AS IS" and is not to be reproduced in whole  */
-/* or part by any means except for backup. Use, duplication, or         */
-/* disclosure by the Government is subject to the restrictions in       */
-/* paragraph (b) (3) (B) of the Rights in Technical Data and Computer   */
-/* Software clause in DFAR 52.227-7013 (a) (Oct 1988).                  */
-/* Software owned by                                                    */
-/* Advanced Micro Devices, Inc.,                                        */
-/* One AMD Place,                                                       */
-/* P.O. Box 3453                                                        */
-/* Sunnyvale, CA 94088-3453.                                            */
-/************************************************************************/
-/*  This software constitutes a basic shell of source code for          */
-/*  programming all AMD Flash components. AMD                           */
-/*  will not be responsible for misuse or illegal use of this           */
-/*  software for devices not supported herein. AMD is providing         */
-/*  this source code "AS IS" and will not be responsible for            */
-/*  issues arising from incorrect user implementation of the            */
-/*  source code herein. It is the user's responsibility to              */
-/*  properly design-in this source code.                                */
-/*                                                                      */
-/************************************************************************/
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "cfiflash.h"
-#include "libsys.h"
-
-#define TEST_SIZE		(1024*1024)
-#define	FLASH_OFFSET	0x700000
-int main(void)
-{
-	int i;
-	flash_t flash;
-	UINT8 *pFlash = (UINT8*)0xA4000000;
-	UINT32 result;
-	UINT8 *pBuf;
-
-	setbuf(stdout, NULL);
-	result = flash_find(&flash, 0xA4000000);
-
-	if (result < 0)
-	{
-		printf("flash_find() error!\n");
-		return 1;
-	}
-
-	printf("Found Flash at %8.8X\n", (UINT32)flash.pBase);
-
-	pBuf = (UINT8*)malloc(TEST_SIZE);
-
-	for (i=0; i < TEST_SIZE; i++)
-		pBuf[i] = i;
-
-	printf("Flash erase from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE);
-	result = flash_erase(&flash, FLASH_OFFSET, TEST_SIZE);
-	if (result < 0)
-	{
-		printf("error!\n");
-		return 1;
-	}
-	printf("OK\n");
-
-	printf("Flash program from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE);
-	result = flash_program(&flash, FLASH_OFFSET, pBuf, TEST_SIZE);
-	if (result < 0)
-	{
-		printf("error!\n");
-		return 1;
-	}
-	printf("OK\n");
-
-	printf("Flash verify from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE);
-	result = flash_verify(&flash, FLASH_OFFSET, pBuf, TEST_SIZE);
-	if (result < 0)
-	{
-		printf("error!\n");
-		return 1;
-	}
-	printf("OK\n");
-
-//	PrintBuffer8((UINT8*)pFlash, 16, TEST_SIZE);
-
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/test_hpi.c b/lib/CPUs/MIPS/bsp/examples/test_hpi.c
deleted file mode 100644
index 407d070..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_hpi.c
+++ /dev/null
@@ -1,848 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include "libsys.h"
-#include "cfiflash.h"
-#include "hpi.h"
-
-static volatile UINT32 _g_uart_msg;
-static volatile UINT32 _g_rst;
-static volatile UINT32 _g_sus;
-static volatile UINT32 _g_cfg;
-
-void uart_handler(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA;
-
-	while((SYS_PS2_BIT_RX_AVAIL & *pUART_stat))
-	{
-		_g_uart_msg = *pUART_data;
-	}
-
-}
-
-void PrintDevRegs(UINT devid)
-{
-	int i;
-	UINT32 reg_base1, reg_base2, reg_addr;
-
-	if ((devid < 1) || (devid > 2))
-		return;
-
-	printf("********************************************************\n");
-	printf("Device %d status\n", devid);
-	printf("********************************************************\n");
-	reg_base1 = 0x0200 + (devid-1)*0x80;
-	reg_base2 = 0xC080 + (devid-1)*0x20;
-	reg_addr = reg_base2 + 4;
-	printf("Port select (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 10;
-	printf("USB control (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 12;
-	printf("Int. enable (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 14;
-	printf("Address     (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 16;
-	printf("Status      (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 18;
-	printf("Frame # reg (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	reg_addr = reg_base2 + 20;
-	printf("SOF/EOP cnt (%4.4X)   : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	for (i=0; i < 8; i++)
-	{
-		printf("EP# %d\n", i);
-		reg_addr = reg_base1 + 16*i + 0;
-		printf("Control (%4.4X)       : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-		reg_addr = reg_base1 + 16*i + 2;
-		printf("Address (%4.4X)       : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-		reg_addr = reg_base1 + 16*i + 4;
-		printf("Count (%4.4X)         : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-		reg_addr = reg_base1 + 16*i + 6;
-		printf("Status (%4.4X)        : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-		reg_addr = reg_base1 + 16*i + 8;
-		printf("Count result (%4.4X)  : %4.4X\n", reg_addr, hpi_read_reg(reg_addr));
-
-	}
-}
-
-typedef struct _sdev_descr_t
-{
-	UINT8 size;					// length
-	UINT8 type;					// desc type
-	UINT16 usb_spec;			// USB spec
-	UINT8 devclass;				// device class
-	UINT8 subclass;				// sub class
-	UINT8 protocol;				// protocol
-	UINT8 max_packet_size;		// max packet size for endpoint 0
-	UINT16 vendor_id;			// Vendor ID
-	UINT16 product_id;			// Product ID
-	UINT16 device_id;			// device release number
-	UINT8 man_str_index;		// index of manufacture string
-	UINT8 prod_str_index;		// index of product string
-	UINT8 sn_str_index;			// index of serial number string
-	UINT8 nconfs;				// number of configurations
-} __attribute__ ((__packed__)) dev_descr_t;
-
-typedef struct _sconf_descr_t
-{
-	UINT8 size;					// length of this config
-	UINT8 type;					// desc type
-	UINT16 total_size;			// Total configuration desc length including this config and following descriptions
-	UINT8 nifaces;				// Number of interface descriptions following this
-	UINT8 conf_id;				// config number
-	UINT8 conf_str_index;		// index of string describing config
-	UINT8 attr;					// attributes (e.g. bus powered)
-	UINT8 current;				// 2mA x <current> (max. 250 => 500mA)
-} __attribute__ ((__packed__)) conf_descr_t;
-
-typedef struct _siface_descr_t
-{
-	UINT8 size;					// length of this config
-	UINT8 type;					// desc type
-	UINT8 base;					// base number
-	UINT8 alt;					// alt
-	UINT8 neps;					// number of endpoint description following this
-	UINT8 iface_class;			// interface class (vendor)
-	UINT8 subclass;				// subclass
-	UINT8 iface_proto;			// interface proto (vendor)
-	UINT8 iface_str_index;
-} __attribute__ ((__packed__)) iface_descr_t;
-
-typedef struct _sep_descr_t
-{
-	UINT8 size;					// length of this config
-	UINT8 type;					// type (endpoint)
-	UINT8 type_num;				// type/number (Host use WriteFile)
-	UINT8 bulk;					// Bulk
-	UINT16 pkt_size;			// packet size
-	UINT8 interval;				// interval
-} __attribute__ ((__packed__)) ep_descr_t;
-
-typedef struct _sotg_descr_t
-{
-	UINT8 size;					// length of this config
-	UINT8 type;					// type (OTG)
-	UINT8 hnp_srp;				// HNP|SRP support
-} __attribute__ ((__packed__)) otg_descr_t;
-
-typedef struct _sstr_descr_hdr_t
-{
-	UINT8 size;					// length of this config
-	UINT8 type;					// type
-} __attribute__ ((__packed__)) str_descr_hdr_t;
-
-typedef struct _scfg_inst_t
-{
-	usb_irp_t *pIRP_rx;
-	usb_irp_t *pIRP_tx;
-} cfg_inst_t;
-
-UINT32 conf_write(UINT8 *pConfDescr, UINT32 neps, ep_descr_t *pEP)
-{
-	UINT32 pos, size;
-	conf_descr_t cfg;
-	iface_descr_t iface;
-	otg_descr_t otg_descr;
-
-	// Fill config description
-	cfg.size = sizeof(conf_descr_t);
-	cfg.type = 2;
-	cfg.total_size = sizeof(conf_descr_t) + sizeof(iface_descr_t) + neps*sizeof(ep_descr_t) + sizeof(otg_descr_t);
-	cfg.nifaces = 1;	// can handle only one interface per config
-	cfg.conf_id = 1;
-	cfg.conf_str_index = 0;
-	cfg.attr = 0x80;
-	cfg.current = 50;
-
-	// Copy config description
-	pos = 0;
-	size = sizeof(conf_descr_t);
-	memcpy(&pConfDescr[pos], &cfg, size);
-
-	// Fill interface description
-	iface.size = sizeof(iface_descr_t);
-	iface.type = 4;
-	iface.base = 0;
-	iface.alt = 0;
-	iface.neps = neps;
-	iface.iface_class = 0;
-	iface.subclass = 0;
-	iface.iface_proto = 0;
-	iface.iface_str_index = 0;
-
-	// Copy interface description
-	pos += size;
-	size = sizeof(iface_descr_t);
-	memcpy(&pConfDescr[pos], &iface, size);
-
-	// Copy N end point descriptions
-	pos += size;
-	size = neps*sizeof(ep_descr_t);
-	memcpy(&pConfDescr[pos], pEP, size);
-
-	// Fill OTG description
-	otg_descr.size = sizeof(otg_descr_t);
-	otg_descr.type = 9;		// OTG
-	otg_descr.hnp_srp = 3;	// HNP|SRP supported
-
-	// Copy OTG description
-	pos += size;
-	size = sizeof(ep_descr_t);
-	memcpy(&pConfDescr[pos], &otg_descr, size);
-
-	pos += size;
-
-	return pos;
-}
-
-UINT32 str_write(UINT8 *pStrDescr, UINT8 *pStr0, UINT8 *pStr1, UINT8 *pStr2)
-{
-	int i;
-	UINT32 pos, size, strsize;
-	str_descr_hdr_t *pStrHdr;
-	UINT16 *pStr;
-
-	pos = 0;
-	size = sizeof(str_descr_hdr_t);
-	strsize = 2;
-	pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos];
-	pStrHdr->size = size + strsize;
-	pStrHdr->type = 3;
-
-	pos += size;
-	pStr = (UINT16*)&pStrDescr[pos];
-
-	*pStr = 0x0409;
-
-	// String 0
-	pos += size;
-	size = sizeof(str_descr_hdr_t);
-	strsize = strlen(pStr0);
-
-	pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos];
-	pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize;
-	pStrHdr->type = 3;
-
-	pos += size;
-	size = 2*strsize;
-	pStr = (UINT16*)&pStrDescr[pos];
-
-	for (i=0; i < strsize; i++)
-		pStr[i] = (UINT16)pStr0[i];
-
-	// String 1
-	pos += size;
-	size = sizeof(str_descr_hdr_t);
-	strsize = strlen(pStr1);
-
-	pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos];
-	pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize;
-	pStrHdr->type = 3;
-
-	pos += size;
-	size = 2*strsize;
-	pStr = (UINT16*)&pStrDescr[pos];
-
-	for (i=0; i < strsize; i++)
-		pStr[i] = (UINT16)pStr1[i];
-
-	// String 2
-	pos += size;
-	size = sizeof(str_descr_hdr_t);
-	strsize = strlen(pStr2);
-
-	pStrHdr = (str_descr_hdr_t*)&pStrDescr[pos];
-	pStrHdr->size = sizeof(str_descr_hdr_t) + 2*strsize;
-	pStrHdr->type = 3;
-
-	pos += size;
-	size = 2*strsize;
-	pStr = (UINT16*)&pStrDescr[pos];
-
-	for (i=0; i < strsize; i++)
-		pStr[i] = (UINT16)pStr2[i];
-
-	pos += size;
-
-	return pos;
-}
-
-void ep0_func(void *pArg)
-{
-	UINT32 result;
-	UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize;
-	usb_irp_t *pIRP = (usb_irp_t*)pArg;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS0);
-	ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES0);
-	ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT0);
-
-	if (ep_status & 0x10)
-	{
-		printf("Setup-flag detected. Status = %4.4X\n", ep_status);
-	}
-}
-
-void ep1_func(void *pArg)
-{
-	UINT32 result;
-	UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize;
-	usb_irp_t *pIRP = (usb_irp_t*)pArg;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS1);
-	ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES1);
-	ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT1);
-
-	tsize = pIRP->tsize;
-	if (ep_status & 0x0020)
-	{
-		printf("Length exception result %4.4X with count = %d\n", ep_status, (INT16)ep_cntres);
-		if (ep_status & 0x0400)
-			tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres);
-		if (ep_status & 0x0800)
-			tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres);
-
-	}
-	result = hpi_read_ram(pIRP->cy_req.addr, buf, tsize);
-	usb_irp_enqueue(pIRP);
-	fifo_write(&pIRP->fifo, (UINT8*)buf, result, 0, FIFO_BLOCK);
-
-//	printf("Read %d bytes\n", result);
-
-}
-
-void ep2_func(void *pArg)
-{
-	UINT32 result;
-	UINT16 buf[USB_MAX_IMG_SIZE/2], ep_cntres, ep_status, ep_count, tsize;
-	usb_irp_t *pIRP = (usb_irp_t*)pArg;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	ep_status = hpi_read_reg (SUSB2_REG_EP_STATUS2);
-	ep_cntres = hpi_read_reg (SUSB2_REG_EP_CNTRES2);
-	ep_count = hpi_read_reg (SUSB2_REG_EP_COUNT2);
-
-	tsize = pIRP->tsize;
-	if (ep_status & 0x0020)
-	{
-		printf("Length exception result %4.4X with count = %d\n", ep_status, (INT16)ep_cntres);
-		if (ep_status & 0x0400)
-			tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres);
-		if (ep_status & 0x0800)
-			tsize = (UINT16)((INT16)tsize - (INT16)ep_cntres);
-	}
-
-	pIRP->tx_in_progress = 0;
-	result = fifo_read(&pIRP->fifo, (UINT8*)buf, pIRP->tsize, 0, FIFO_NONBLOCK);
-	if (!result)
-		return;
-
-	pIRP->cy_req.size = result;
-	hpi_write_ram(pIRP->cy_req.addr, (UINT16*)buf, result);
-
-	usb_irp_enqueue(pIRP);
-
-//	printf("Wrote %d bytes\n", result);
-
-}
-
-void rst_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_RST_MSG\n");
-///	hpi_comm_reset();
-
-	_g_rst = 1;
-
-	*pLED = 0x40000000 + 1;
-
-}
-
-void sof_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_SOF_MSG\n");
-
-	*pLED = 0x40000000 + 2;
-
-}
-
-void cfg_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-	cfg_inst_t *pCFG = (cfg_inst_t*)pArg;
-	usb_irp_t *pIRP_rx = (usb_irp_t*)pCFG->pIRP_rx;
-	usb_irp_t *pIRP_tx = (usb_irp_t*)pCFG->pIRP_tx;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_CFG_MSG\n");
-	_g_cfg = 1;
-	usb_irp_enqueue(pIRP_rx);
-	fifo_flush(&pIRP_rx->fifo);
-	fifo_flush(&pIRP_tx->fifo);
-	pIRP_tx->tx_in_progress = 0;
-	*pLED = 0;
-
-}
-
-void sus_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_SUS_MSG\n");
-
-	*pLED = 0x40000000 + 3;
-
-	_g_sus = 1;
-
-}
-
-void id_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_ID_MSG\n");
-
-	*pLED = 0x40000000 + 4;
-
-}
-
-void vbus_func(void *pArg)
-{
-	volatile int *pLED = (int*)SYS_LED_PORT;
-
-//	printf("Callback with pArg = %8.8X\n", (UINT32)pArg);
-	sputs("SUSB_VBUS_MSG\n");
-
-	*pLED = 0x40000000 + 5;
-
-}
-
-UINT32 usb_init_descr(void)
-{
-	UINT32 result;
-
-	UINT16 buffer16[0x100];
-	UINT16 addr;
-	dev_descr_t dev_descr = {sizeof(dev_descr_t), 1, 0x0200, 0xFF, 0, 0, 8, 0x04B4, 0x7200, 0x0099, 1, 2, 3, 1};
-	ep_descr_t ep_descr[2] = {{sizeof(ep_descr_t), 5, 1, 2, 64, 0}, {sizeof(ep_descr_t), 5, 0x82, 2, 64, 0}};
-
-	// Set device descriptor
-	addr = 0xf516;	// default
-	addr = 0xA00;
-	hpi_write_ram(addr, (UINT16*)&dev_descr, sizeof(dev_descr_t));
-	hpi_write_reg(2*SUSB2_DEVICE_DESCRIPTOR_VEC, addr);
-
-	// Set new configuration descriptor
-
-	// Write config and interface descriptor
-	result = conf_write((UINT8*)buffer16, sizeof(ep_descr)/sizeof(ep_descr_t), ep_descr);
-
-	addr = 0xf528;	// default
-	addr = 0xB00;
-	hpi_write_ram(addr, (UINT16*)buffer16, result);
-	hpi_write_reg(2*SUSB2_CONFIGURATION_DESCRIPTOR_VEC, addr);
-
-	// Set string description
-	result = str_write((UINT8*)buffer16, "JDI Inc.", "JDI-USB (MIPS)", "311070");
-	addr = 0xf528;	// default
-	addr = 0xC00;
-	hpi_write_ram(addr, (UINT16*)buffer16, result);
-	hpi_write_reg(2*SUSB2_STRING_DESCRIPTOR_VEC, addr);
-
-	return 0;
-}
-
-UINT32 usb_force_reconnect(UINT32 port)
-{
-	UINT32 result;
-	UINT16 addr;
-
-	if (port >= USB_MAX_NUM_PORTS)
-		return -1;
-
-	if (port == 0)
-	{
-		// R1 = 0 : Full speed
-		// R2 = 1 : SIE1
-		addr = hpi_read_reg(SUSB1_REG_USBCTRL);
-		hpi_write_reg(SUSB1_REG_USBCTRL, addr | 0x0010);
-		result = hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 1);
-		hpi_write_reg(SUSB1_REG_USBCTRL, addr);
-	}
-	else
-	{
-		// R1 = 0 : Full speed
-		// R2 = 2 : SIE2
-		addr = hpi_read_reg(SUSB2_REG_USBCTRL);
-		hpi_write_reg(SUSB2_REG_USBCTRL, addr | 0x0010);
-		result = hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2);
-		hpi_write_reg(SUSB2_REG_USBCTRL, addr);
-	}
-	return result;
-}
-
-UINT32 usb_recv(usb_irp_t *pObj, UINT8 *pData, UINT32 len, UINT32 timeout)
-{
-	UINT32 result;
-
-	result = fifo_read(&pObj->fifo, pData, len, timeout, FIFO_BLOCK);
-
-	return result;
-}
-
-UINT32 usb_send(usb_irp_t *pObj, UINT8 *pData, UINT32 len, UINT32 timeout)
-{
-	UINT32 result;
-	UINT8 buf[USB_MAX_IMG_SIZE];
-
-	// Fill-up FIFO
-	result = fifo_write(&pObj->fifo, pData, len, 0, FIFO_NONBLOCK);
-	if (!result)
-		return 0;
-
-	// Trigger TX
-	if (!pObj->tx_in_progress)
-	{
-		pObj->cy_req.size = fifo_read(&pObj->fifo, (UINT8*)buf, pObj->tsize, 0, FIFO_NONBLOCK);
-		hpi_write_ram(pObj->cy_req.addr, (UINT16*)buf, pObj->cy_req.size);
-		usb_irp_enqueue(pObj);
-	}
-
-	// If necessary, write rest to FIFO
-	result += fifo_write(&pObj->fifo, &pData[result], len - result, timeout, FIFO_BLOCK);
-
-	return result;
-
-}
-
-#define TEST_SIZE				(2*1024*1024)
-#define TRANSFER_SIZE			64
-#define FLASH_IMAGE_SIZE		(2*1024*1024)
-
-int main(void)
-{
-	int i;
-	UINT32 result, sync, cmd, len, buf_count, led_count, remain, tx_cnt, flash_offset;
-	UINT8 buffer8[2048];
-	UINT16 buffer16[0x2000];
-	UINT16 addr;
-	volatile UINT32 *pLED = (UINT32*)SYS_LED_PORT;
-	volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT;
-	UINT32 start, end;
-	UINT32 *pFlash32;
-	UINT8 *pFlash8;
-	UINT32 buffer32[16], *pBuf;
-	UINT64 *pBuf64;
-	usb_irp_t irp_rx, irp_tx;
-	fifo_t fifo_rx, fifo_tx;
-	cfg_inst_t cfg_inst;
-	flash_t flash;
-	volatile UINT32 *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	volatile UINT32 *pVGA_front = (UINT32*)SYS_VGA_FB_FRONT;
-	volatile UINT32 *pVGA_back = (UINT32*)SYS_VGA_FB_BACK;
-
-	_g_rst = 0;
-	_g_sus = 0;
-	_g_cfg = 0;
-
-	usb_init();
-
-	// enable EP#0 callback
-	usb_callback_register(1, SUSB_EP0_MSG, ep0_func, NULL);
-
-	// enable EP#1 callback
-	usb_irp_register(&irp_rx, 1, 1, TRANSFER_SIZE, 1);
-	usb_callback_register(1, SUSB_EP1_MSG, ep1_func, &irp_rx);
-
-	// enable EP#2 callback
-	usb_irp_register(&irp_tx, 1, 2, TRANSFER_SIZE, 0);
-	usb_callback_register(1, SUSB_EP2_MSG, ep2_func, &irp_tx);
-
-	usb_callback_register(1, SUSB_RST_MSG, rst_func, NULL);
-	usb_callback_register(1, SUSB_SOF_MSG, sof_func, NULL);
-	cfg_inst.pIRP_rx = &irp_rx;
-	cfg_inst.pIRP_tx = &irp_tx;
-	usb_callback_register(1, SUSB_CFG_MSG, cfg_func, &cfg_inst);
-	usb_callback_register(1, SUSB_SUS_MSG, sus_func, NULL);
-	usb_callback_register(1, SUSB_ID_MSG, id_func, NULL);
-	usb_callback_register(1, SUSB_VBUS_MSG, vbus_func, NULL);
-
-	printf("HPI-Test\n\n");
-
-	if (IS_ERROR(hpi_init()))
-	{
-		sputs("hpi_init(): error\n");
-		return 1;
-	}
-
-	printf("cy67k3_reset\n");
-	cy67k3_reset();
-
-	while(!_g_rst);
-
-	printf("hpi_comm_reset\n");
-	hpi_comm_reset();
-
-	while(!_g_sus);
-
-	printf("usb_init_descr\n");
-	usb_init_descr();
-	printf("hpi_comm_exec_int\n");
-	hpi_comm_exec_int(SUSB_INIT_INT, 2, R1, 0, R2, 2);
-	printf("usb_force_reconnect\n");
-	usb_force_reconnect(1);
-
-	while(!_g_cfg);
-
-	printf("USB-Ready\n");
-
-	printf("CY-Read..");
-	start = clock();
-	for (i=0; i < TEST_SIZE; i+=0x2000)
-		hpi_read_ram(0x2000, buffer16, 0x2000);
-
-	end = clock();
-	printf("done (%.2f Mbyte/s)\n", (double)TEST_SIZE/(1000*(end-start)));
-
-	printf("CY-Write..");
-	start = clock();
-	for (i=0; i < TEST_SIZE; i+=0x2000)
-		hpi_write_ram(0x2000, buffer16, 0x2000);
-
-	end = clock();
-	printf("done (%.2f Mbyte/s)\n", (double)TEST_SIZE/(1000*(end-start)));
-
-	sputs("HPI-Status   : ");
-	print_word(cy67k3_read_HPI_STATUS());
-	sputs("\n");
-
-	sputs("HPI BP       : ");
-	print_word(hpi_read_reg(HPI_REG_BP));
-	sputs("\n");
-
-	sputs("HPI IRR      : ");
-	print_word(hpi_read_reg(HPI_REG_INTROUTE));
-	sputs("\n");
-
-	sputs("CPU Revision : ");
-	print_word(hpi_comm_read_ctrl_reg(USB_REG_REVISON));
-	sputs("\n");
-
-	hpi_comm_write_ctrl_reg(USB_REG_SPEED, 0x0000, LOGIC_DIRECT);
-	sputs("CPU Speed    : ");
-	print_word(hpi_comm_read_ctrl_reg(USB_REG_SPEED));
-	sputs("\n");
-
-//	usb_init_descr();
-//	usb_force_reconnect(1);
-
-	// enable RX interrupt
-	*pUART0_stat |= (1 << 6);
-	interrupt_register(3, uart_handler);
-	interrupt_enable(3);
-
-	// Enable EP#1
-	hpi_write_reg(SUSB2_REG_EP_COUNT1, TRANSFER_SIZE);
-	hpi_write_reg(SUSB2_REG_EP_CTRL1, 2);
-	hpi_write_reg(SUSB2_REG_EP_CNTRES1, 0);
-	hpi_write_reg(SUSB2_REG_EP_STATUS1, 0);
-
-	// Enable EP#2
-	hpi_write_reg(SUSB2_REG_EP_COUNT2, TRANSFER_SIZE);
-	hpi_write_reg(SUSB2_REG_EP_CTRL2, 2);
-	hpi_write_reg(SUSB2_REG_EP_CNTRES2, 0);
-	hpi_write_reg(SUSB2_REG_EP_STATUS2, 0);
-
-	led_count = 0;
-	buf_count = 0;
-
-	pBuf64 = (UINT64*)malloc(FLASH_IMAGE_SIZE);
-	pBuf = (UINT32*)pBuf64;
-
-	*pVGA_front = (UINT32)pBuf64;
-	*pVGA_back = (UINT32)pBuf64;
-	*pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-
-	if (IS_ERROR(flash_find(&flash, SYS_FLASH_IO)))
-	{
-		printf("Cannot find flash device. Exit now!\n");
-		return 1;
-	}
-
-	// Get flash offset by value of DIP-switch
-	flash_offset = flash_get_offset_by_blocknum(&flash, flash.info.nblocks-FLASH_IMAGE_SIZE/flash.info.blocksize);
-	printf("flash_offset: %08X\n", flash_offset);
-	pFlash32 = (UINT32*)(SYS_FLASH_IO + flash_offset);
-	pFlash8 = (UINT8*)pFlash32;
-
-	while(1)
-	{
-		switch (_g_uart_msg)
-		{
-			case '1':
-			_g_uart_msg = 0;
-			PrintDevRegs(1);
-			printf("\nSIEmsg1: %4.4X\n", hpi_read_reg(HPI_REG_SIE1MSG));
-			break;
-
-			case '2':
-			_g_uart_msg = 0;
-			PrintDevRegs(2);
-			printf("\nSIEmsg2: %4.4X\n", hpi_read_reg(HPI_REG_SIE2MSG));
-			break;
-
-			default:
-			break;
-		}
-		result = usb_recv(&irp_rx, (UINT8*)&sync, 4, 100);
-		if (!result)
-			continue;
-
-		*pLED = led_count++;
-
-		if (sync == 0xC24755AA)
-		{
-			printf("Sync found\n");
-			result = usb_recv(&irp_rx, (UINT8*)&cmd, 4, 1000);
-			if (!result)
-				continue;
-
-			result = usb_recv(&irp_rx, (UINT8*)&len, 4, 1000);
-			if (!result)
-				continue;
-
-			printf("Command %d with len %d found\n",cmd, len);
-			switch(cmd)
-			{
-				case 0x00000001:
-				result = usb_recv(&irp_rx, NULL, len, 1000);
-				if (result)
-				{
-					printf("Read %d bytes\n", result);
-				}
-				break;
-
-				case 0x00000002:
-				remain = len;
-				tx_cnt = 0;
-				while(remain)
-				{
-					len = sizeof(buffer8);
-					if (remain < len)
-						len = remain;
-
-					for (i=0; i < len; i++)
-						buffer8[i] = buf_count+i;
-
-					result = usb_send(&irp_tx, buffer8, len, 1000);
-					if (!result)
-						break;
-					tx_cnt += result;
-					remain -= result;
-					buf_count++;
-				}
-				printf("Wrote %d bytes\n", tx_cnt);
-				break;
-
-				case 0x00000003:
-				remain = len;
-				tx_cnt = 0;
-				while(remain)
-				{
-					len = 256;
-					if (remain < len)
-						len = remain;
-
-					result = usb_send(&irp_tx, (UINT8*)&pFlash8[tx_cnt], len, 1000);
-					if (!result)
-						break;
-					tx_cnt += result;
-					remain -= result;
-					buf_count++;
-				}
-				printf("Wrote %d bytes\n", tx_cnt);
-				break;
-
-				case 0x00000004:
-				*pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN;
-				result = usb_recv(&irp_rx, (UINT8*)pBuf, len, 1000);
-				if (result)
-				{
-					printf("Read %d bytes\n", result);
-				}
-
-				len = result;
-				if (len > FLASH_IMAGE_SIZE)
-				{
-					printf("Cannot write flash: image to large!\n");
-					break;
-				}
-
-				printf("Flash erase...");
-				result = flash_erase(&flash, flash_offset, len);
-				if (IS_ERROR(result))
-				{
-					printf("failed (%08X)\n", result);
-					break;
-				}
-				printf("done\n");
-
-				printf("Flash write...");
-				result = flash_program(&flash, flash_offset, (UINT8*)pBuf, len);
-				if (IS_ERROR(result))
-				{
-					printf("failed (%08X)\n", result);
-					break;
-				}
-				printf("done\n");
-
-				printf("Flash verify...");
-				result = flash_verify(&flash, flash_offset, (UINT8*)pBuf, len);
-				if (IS_ERROR(result))
-				{
-					printf("failed (%08X)\n", result);
-					break;
-				}
-				printf("passed\n");
-				*pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-				break;
-
-				case 0x000000FF:
-				usb_force_reconnect(1);
-				break;
-
-				default:
-				break;
-			}
-		}
-	}
-
-	return 0;
-}
-
-//			pMem = (UINT8*)0x40000000;
-//			result = fifo_write(&fifo_tx, pMem, 640, 0, FIFO_NONBLOCK);
-//			pMem += result;
-//			usb_irp_enqueue(&irp_tx);
diff --git a/lib/CPUs/MIPS/bsp/examples/test_irq.c b/lib/CPUs/MIPS/bsp/examples/test_irq.c
deleted file mode 100644
index b1a9213..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_irq.c
+++ /dev/null
@@ -1,335 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-
-#define	CPU_FREQ_HZ	100000000
-#include "libsys.h"
-#include "irq.h"
-#include "mips_gfx.h"
-#include "mips_ps2.h"
-
-char buffer[16384];
-char * volatile pPtr_r;
-char * volatile pPtr_w;
-static volatile INT32 mouse_x;
-static volatile INT32 mouse_y;
-static box_t box;
-static gfx_t gfx;
-static volatile int _g_posx, _g_posy;
-static volatile g_btn_l, g_btn_r;
-static volatile UINT32 g_color;
-
-// -------------------------------------------------------------
-void handler0(void)
-{
-	printf("Interrupt 0\n");
-	interrupt_clr(0);
-}
-
-void handler1(void)
-{
-	printf("Interrupt 1\n");
-	interrupt_clr(1);
-}
-
-void handler2(void)
-{
-	printf("Interrupt 2\n");
-}
-
-void handler3(void)
-{
-	volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT;
-	volatile UINT32 *pUART0_data = (UINT32*)SYS_UART0_DATA;
-	volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT;
-	volatile UINT32 *pUART1_data = (UINT32*)SYS_UART1_DATA;
-
-	while(0x200 & *pUART0_stat)
-	{
-//		sputs("w: "); print_word((int)pPtr_w); sputs("\n");
-		if (pPtr_w == &buffer[16383])
-			pPtr_w = buffer;
-		*(pPtr_w++) = *pUART0_data;
-	}
-
-	while(0x200 & *pUART1_stat)
-	{
-//		sputs("w: "); print_word((int)pPtr_w); sputs("\n");
-		if (pPtr_w == &buffer[16383])
-			pPtr_w = buffer;
-		*(pPtr_w++) = *pUART1_data;
-	}
-
-}
-
-void handler4(void)
-{
-	printf("Interrupt 4\n");
-}
-
-void handler5(void)
-{
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-
-	// Ack
-	*pVGA_ctrl |= SYS_VGA_BIT_BUFCHG_FLAG;
-
-}
-
-void handler6(void)
-{
-	int p, i;
-	ps2_if_t *pIF;
-	UINT8 mouse_rsp[3];
-	UINT32 timeout_count, key;
-
-	INT32 dx, dy;
-
-	for (p=0; p < PS2_get_num_if(); p++)
-	{
-		pIF = PS2_get_if(p);
-		if (SYS_PS2_BIT_RX_ERR_FLAG & *pIF->pCTRL)
-			fprintf(stderr, "PS2[%d]: Status = 0x%08X\n", p, *pIF->pCTRL);
-
-		if (pIF->type == ps2_type_keyb)
-		{
-			while(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)
-			{
-				key = *pIF->pDATA;
-				printf("Keyboard scan code = 0x%02X\n", key);
-			}
-		}
-		if (pIF->type == ps2_type_mouse)
-		{
-			if(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL))
-				continue;
-
-			for (i=0; i < 3; i++)
-			{
-				timeout_count = 100;
-				while(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL))
-				{
-					timeout_count--;
-					if (!timeout_count)
-					{
-						break;
-					}
-					sleep(1);
-				}
-				if (!timeout_count)
-				{
-					break;
-				}
-				mouse_rsp[i] = (UINT8)*pIF->pDATA;
-			}
-			if (!timeout_count)
-			{
-				continue;
-			}
-			dx = mouse_rsp[1];
-			if (mouse_rsp[0] &  0x10)
-				dx |= 0xFFFFFF00;
-			dy = mouse_rsp[2];
-			if (mouse_rsp[0] &  0x20)
-				dy |= 0xFFFFFF00;
-
-//			printf("dx = %5d, dy = %5d\n", dx, dy);
-
-			mouse_x += dx;
-			mouse_y -= dy;
-			g_btn_l = 0;
-			if (mouse_rsp[0] & 0x01)
-				g_btn_l = 1;
-
-			if (mouse_rsp[0] & 0x02)
-			{
-				if (g_btn_r == 0)
-				{
-					g_color  = (UINT32)rand();
-				}
-				g_btn_r = 1;
-			}
-			else
-				g_btn_r = 0;
-
-
-			if (mouse_x < 0)
-				mouse_x = 0;
-			if (mouse_y < 0)
-				mouse_y = 0;
-			if (mouse_x > (gfx.w-1))
-				mouse_x = gfx.w-1;
-			if (mouse_y >= (gfx.h-1))
-				mouse_y = gfx.h-1;
-
-//			Screen_csr_set_x(mouse_x);
-//			Screen_csr_set_y(mouse_y);
-
-//			printf("x = %5d, y = %5d\n", mouse_x, mouse_y);
-
-		}
-	}
-}
-
-void handler7(void)
-{
-	printf("Interrupt 7\n");
-}
-
-int main(void)
-{
-
-	int i;
-	volatile UINT32 *pUART0_stat = (UINT32*)SYS_UART0_STAT;
-	volatile UINT32 *pUART1_stat = (UINT32*)SYS_UART1_STAT;
-	volatile UINT32 *pUART0_baud = (UINT32*)SYS_UART0_BAUD;
-	volatile UINT32 *pUART1_baud = (UINT32*)SYS_UART1_BAUD;
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT;
-	UINT32 volatile *pVGA_moffs_1 = (UINT32*)SYS_VGA_FB_BACK;
-	UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL;
-	UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000);
-	UINT32 framecount;
-	UINT32 start, end;
-	char string[65];
-
-	interrupt_register(0, (void*)handler0);
-	interrupt_register(1, (void*)handler1);
-//	interrupt_register(2, (void*)handler2);
-	interrupt_register(3, (void*)handler3);
-//	interrupt_register(4, (void*)handler4);
-//	interrupt_register(5, (void*)handler5);
-	interrupt_register(6, (void*)handler6);
-	interrupt_register(7, (void*)handler7);
-
-	srand(clock());
-	UART1_setbaud(460800);
-	printf("Hello\n");
-	memset(buffer, 0, sizeof(buffer));
-
-	*pVGA_cgcol = 0x00FFFFFF;
-	_g_posx = _g_posy = 0;
-	g_color = 0xFFFFFFFF;
-	GFX_init(&gfx);
-
-	GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1);
-	box_create(&box, 256, 256);
-	GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color);
-	GFX_show(&gfx);
-	printf("VGA status = %08X\n", *pVGA_ctrl);
-
-	pPtr_r = buffer;
-	pPtr_w = buffer;
-
-	printf("UART0 Status = 0x%8.8X\n", *pUART0_stat);
-	printf("UART0 Baud   = 0x%8.8X\n", *pUART0_baud);
-	printf("UART1 Status = 0x%8.8X\n", *pUART1_stat);
-	printf("UART1 Baud   = 0x%8.8X\n", *pUART1_baud);
-
-	// UART: enable RX interrupt
-	*pUART0_stat |= (1 << 6);
-	*pUART1_stat |= (1 << 6);
-	printf("UART0 Status = 0x%8.8X\n", *pUART0_stat);
-	printf("UART1 Status = 0x%8.8X\n", *pUART1_stat);
-
-	PS2_init(0);
-	PS2_init(1);
-
-	sputs("r: "); print_word((int)pPtr_r); sputs("\n");
-	sputs("w: "); print_word((int)pPtr_w); sputs("\n");
-
-	// Print Status register
-	sputs("Status  : ");
-	print_word(CP0_SR_read());
-	sputs("\n");
-	sputs("\n");
-
-	interrupt_disable(6);
-	printf("Bitte gebe ein: ");
-	scanf("%s", string);
-	printf("Du schriebst: %s\n", string);
-
-	// Flush buffer
-	PS2_flush(0);
-	PS2_flush(1);
-
-	printf("Start:\n");
-
-	interrupt_enable(0);
-	interrupt_enable(1);
-//	interrupt_enable(2);
-	interrupt_enable(3);
-//	interrupt_enable(4);
-//	interrupt_enable(5);
-	interrupt_enable(6);
-	interrupt_enable(7);
-
-	interrupt_set(0);
-	interrupt_set(1);
-	interrupt_set(2);
-	interrupt_set(3);
-	interrupt_set(4);
-	interrupt_set(5);
-	interrupt_set(6);
-	interrupt_set(7);
-
-//	while(1)
-//	{
-//		printf("PS2-Status : 0x%08X\n", *(ps2_if[0].pCTRL));
-//		printf("PS2-Data   : 0x%08X\n", *(ps2_if[0].pDATA));
-//		sleep(1000);
-//	}
-
-	interrupt_enable(6);
-	framecount = Screen_get_fps();
-	start = clock();
-
-	while(1)
-	{
-		if (!framecount)
-		{
-			end = clock();
-			framecount = Screen_get_fps();
-			printf("%f FPS\n", (float)framecount/((float)(end-start)/CLOCKS_PER_SEC));
-			start = clock();
-		}
-
-		GFX_frame(&gfx, GFX_FRAME_SYNC);
-		framecount--;
-
-		while ((_g_posx != (UINT32)mouse_x) || (_g_posy != (UINT32)mouse_y) || g_btn_r || g_btn_l)
-		{
-
-			GFX_restore(&gfx, &box, _g_posx, _g_posy);
-
-			_g_posx = (UINT32)mouse_x;
-			_g_posy = (UINT32)mouse_y;
-
-			if (g_btn_l && !g_btn_r)
-			{
-				GFX_box_draw_bg(&gfx, &box, _g_posx, _g_posy, g_color);
-			}
-
-			if (g_btn_l && g_btn_r)
-			{
-				GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1);
-			}
-
-			GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color);
-			break;
-		}
-		GFX_show(&gfx);
-
-		if(pPtr_w != pPtr_r)
-		{
-//			sputs("r: "); print_word((int)pPtr_r); sputs("\n");
-			if (pPtr_r == &buffer[16383])
-				pPtr_r = buffer;
-			writechar(0, *(pPtr_r++));
-		}
-	}
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c b/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c
deleted file mode 100644
index eb3a61b..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_mipsdis.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/* +----------------------------------------------------------------+ */
-/* |            Copyright (c) 1994 Stanford University.             | */
-/* |                      All Rights Reserved.                      | */
-/* |                                                                | */
-/* |   This software is distributed with *ABSOLUTELY NO SUPPORT*    | */
-/* |   and *NO WARRANTY*.   Use or reproduction of this code for    | */
-/* |   commerical gains is strictly prohibited.   Otherwise, you    | */
-/* |   are given permission to use or modify this code as long      | */
-/* |   as you do not remove this notice.                            | */
-/* +----------------------------------------------------------------+ */
-/* --------------------------------------------------- */
-/* | Copyright (c) 1986 MIPS Computer Systems, Inc.  | */
-/* | All Rights Reserved.                            | */
-/* --------------------------------------------------- */
-
-/*
- * Copyright 1985 by MIPS Computer Systems, Inc.
- */
-
-/* TORCH disassembler */
-/* derived from MIPS instruction dissassembler by PGL October 91 */
-
-#include <stdio.h>
-#include <string.h>
-#include "mipsdis.h"
-
-#define false 0
-#define true 1
-typedef int boolean;
-char *strcat();
-
-#define ZERO 0
-
-#define COMPILER_NAMES tdis_reg_names[0]
-#define HARDWARE_NAMES tdis_reg_names[1]
-#define ASSEMBLER_NAMES tdis_reg_names[2]
-#define DIS_REG_NAMES(x)	tdis_reg_names[x]
-
-union extension_byte {
-    unsigned char byte;
-    struct {	/* extension byte bits in little-endian order */
-#if (defined __MIPSEB || defined _MIPSEB || defined MIPSEB)
-	unsigned reserved:1;
-	unsigned dyn_nop:1;
-	unsigned rs_boost:2;
-	unsigned rt_boost:2;
-	unsigned rd_boost:2;
-#elif (defined __MIPSEL || defined _MIPSEL || defined MIPSEL)
-	unsigned rd_boost:2;
-	unsigned rt_boost:2;
-	unsigned rs_boost:2;
-	unsigned dyn_nop:1;
-	unsigned reserved:1;
-#endif /*MIPSEB*/
-    } e;
-};
-
-#define blez_op_T	blez_op
-#define blez_op_N	(blez_op | 0x10)
-#define bgtz_op_T	bgtz_op
-#define bgtz_op_N	(bgtz_op | 0x10)
-#define beq_op_T	beq_op
-#define beq_op_N	(beq_op | 0x10)
-#define bne_op_T	bne_op
-#define bne_op_N	(bne_op | 0x10)
-#define bc_op_T		bc_op
-#define bc_op_N		(bc_op | 0x02)
-
-static char *op_name[64] = {
-/* 0 */	"special",	"regimm","j",	"jal",	"beq",  "bne",  "blez", "bgtz",
-/* 8 */	"addi",	"addiu","slti",	"sltiu","andi",	"ori",	"xori",	"lui",
-/*16 */	"cop0",	"cop1",	"cop2",	"cop3",	"beql","bnel","blezl","bgtzl",
-/*24 */	"op60",	"op64",	"op68",	"op6c",	"op70",	"op74",	"op78",	"op7c",
-/*32 */	"lb",	"lh",	"lwl",	"lw",	"lbu",	"lhu",	"lwr",	"ld",
-/*40 */	"sb",	"sh",	"swl",	"sw",	"opb0",	"opb4",	"swr",	"sd",
-/*48 */	"lwc0",	"lwc1",	"lwc2",	"lwc3",	"ldc0",	"ldc1",	"ldc2",	"ldc3",
-/*56 */	"swc0",	"swc1",	"swc2",	"swc3",	"sdc0",	"sdc1",	"sdc2",	"sdc3"
-};
-
-static char *spec_name[64] = {
-/* 0*/ "sll",	"spec01","srl",	"sra",	"sllv",	"spec05","srlv","srav",
-/* 8*/ "jr",	"jalr",	"spec12","spec13","syscall","break","vcall","spec17",
-/*16*/ "mfhi",	"mthi",	"mflo",	"mtlo",	"spec24","spec25","spec26","spec27",
-/*24*/ "mult",	"multu","div",	"divu",	"spec34","spec35","spec36","spec37",
-/*32*/ "add",	"addu",	"sub",	"subu",	"and",	"or",	"xor",	"nor",
-/*40*/ "spec50","spec51","slt","sltu",	"spec54","spec55","spec56","spec57",
-/*48*/ "spec60","spec61","spec62","spec63","spec64","spec65","spec66","spec67",
-/*56*/ "spec70","spec71","spec72","spec73","spec74","spec75","spec76","spec77"
-};
-
-static char *bcond_name[32] = {
-	"bltz",
-	"bgez",
-	"bltzl",
-	"bgezl",
-	"bcond04",
-	"bcond05",
-	"bcond06",
-	"bcond07",
-	"tgei",
-	"tgeiu",
-	"tlti",
-	"tltiu",
-	"teqi",
-	"bcond0d",
-	"tnei",
-	"bcond0f",
-	"bltzal",
-	"bgezal",
-	"bltzall",
-	"bgezall",
-	"bcond14",
-	"bcond15",
-	"bcond16",
-	"bcond17",
-	"bcond18",
-	"bcond19",
-	"bcond1a",
-	"bcond1b",
-	"bcond1c",
-	"bcond1d",
-	"bcond1e",
-	"bcond1f"
-};
-
-static char *cop1_name[64] = {
-/* 0 */	"add",	"sub",	"mul",	"div",	"sqrt", "abs",	"mov",	"neg",
-/* 8 */	"fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f",
-/*16 */	"fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17",
-/*24 */	"fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f",
-/*32 */	"cvt.s","cvt.d","cvt.e","fop23","cvt.w","fop25","fop26","fop27",
-/*40 */	"fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f",
-/*48 */	"c.f", "c.un","c.eq","c.ueq","c.olt","c.ult","c.ole","c.ule",
-/*56 */	"c.sf","c.ngle","c.seq","c.ngl","c.lt","c.nge","c.le","c.ngt"
-};
-
-static char *fmt_name[16] = {
-	"s",	"d",	"e",	"q",
-	"w",	"fmt5",	"fmt6",	"fmt7",
-	"fmt8",	"fmt9",	"fmta",	"fmtb",
-	"fmtc",	"fmtd",	"fmte",	"fmtf"
-};
-
-/* public */
-/* Three sets of commonly used register names */
-const char *tdis_reg_names[3][64] = {
-    {   /* compiler names */
-	"zero",	"at",	"v0",	"v1",	"a0",	"a1",	"a2",	"a3",
-	"t0",	"t1",	"t2",	"t3",	"t4",	"t5",	"t6",	"t7",
-	"s0",	"s1",	"s2",	"s3",	"s4",	"s5",	"s6",	"s7",
-	"t8",	"t9",	"k0",	"k1",	"gp",	"sp",	"s8",	"ra",
-	"zero.B","at.B","v0.B",	"v1.B",	"a0.B",	"a1.B",	"a2.B",	"a3.B",
-	"t0.B",	"t1.B",	"t2.B",	"t3.B",	"t4.B",	"t5.B",	"t6.B",	"t7.B",
-	"s0.B",	"s1.B",	"s2.B",	"s3.B",	"s4.B",	"s5.B",	"s6.B",	"s7.B",
-	"t8.B",	"t9.B",	"k0.B",	"k1.B",	"gp.B",	"sp.B",	"s8.B",	"ra.B"
-    },
-    {	/* hardware names */
-	"r0",	"r1",	"r2",	"r3",	"r4",	"r5",	"r6",	"r7",
-	"r8",	"r9",	"r10",	"r11",	"r12",	"r13",	"r14",	"r15",
-	"r16",	"r17",	"r18",	"r19",	"r20",	"r21",	"r22",	"r23",
-	"r24",	"r25",	"r26",	"r27",	"gp",	"sp",	"r30",	"r31",
-	"r0.B",	"r1.B",	"r2.B",	"r3.B",	"r4.B",	"r5.B",	"r6.B",	"r7.B",
-	"r8.B",	"r9.B",	"r10.B","r11.B","r12.B","r13.B","r14.B","r15.B",
-	"r16.B","r17.B","r18.B","r19.B","r20.B","r21.B","r22.B","r23.B",
-	"r24.B","r25.B","r26.B","r27.B","gp.B",	"sp.B",	"r30.B","r31.B"
-    },
-    {	/* assembler names */
-	"$0",	"$at",	"$2",	"$3",	"$4",	"$5",	"$6",	"$7",
-	"$8",	"$9",	"$10",	"$11",	"$12",	"$13",	"$14",	"$15",
-	"$16",	"$17",	"$18",	"$19",	"$20",	"$21",	"$22",	"$23",
-	"$24",	"$25",	"$26",	"$27",	"$gp",	"$sp",	"$30",	"$31",
-	"$0.B",	"$at.B","$2.B",	"$3.B",	"$4.B",	"$5.B",	"$6.B",	"$7.B",
-	"$8.B",	"$9.B",	"$10.B","$11.B","$12.B","$13.B","$14.B","$15.B",
-	"$16.B","$17.B","$18.B","$19.B","$20.B","$21.B","$22.B","$23.B",
-	"$24.B","$25.B","$26.B","$27.B","$gp.B","$sp.B","$30.B","$31.B"
-    }
-};
-
-static char *c0_opname[64] = {
-    "c0op0","tlbr","tlbwi","c0op3","c0op4","c0op5","tlbwr","c0op7",
-    "tlbp","c0op9","c0op10","c0op11","c0op12","c0op13","c0op14","c0op15",
-    "rfe","c0op17","c0op18","c0op19","c0op20","c0op21","c0op22","c0op23",
-    "c0op24","c0op25","c0op26","c0op27","c0op28","c0op29","c0op30","c0op31",
-    "c0op32","c0op33","c0op34","c0op35","c0op36","c0op37","c0op38","c0op39",
-    "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47",
-    "c0op48","c0op49","c0op50","c0op51","c0op52","c0op53","c0op54","c0op55",
-    "c0op56","c0op57","c0op58","c0op59","c0op60","c0op61","c0op62","c0op63"
-};
-
-static char *c0_reg[32] = {
-    "index","random","tlblo","c0r3","context","c0r5","c0r6","c0r7",
-    "badvaddr","c0r9","tlbhi","epcn","sr",	"cause","epc",	"c0r15",
-    "c0r16","c0r17","c0r18","c0r19","c0r20","c0r21","c0r22","c0r23",
-    "c0r24","c0r25","c0r26","c0r27","c0r28","c0r29","c0r30","c0r31"
-};
-
-/* Remember the options set by dis_init */
-#define ADDR_DEFAULT 0
-//#define ADDR_DEFAULT "%#010x:\t"
-//#define VALUE_DEFAULT "%#010x\t"
-#define VALUE_DEFAULT 0
-#define NAME_DEFAULT COMPILER_NAMES
-static struct {
-    char *addr_format;
-    char *value_format;
-    const char **reg_names;
-    int print_jal_targets;
-} save = {
-    ADDR_DEFAULT,
-    VALUE_DEFAULT,
-    NAME_DEFAULT,
-    true
-};
-
-/* Update regmask to reflect the use of this general-purpose (not fp)
-  register, and return its name */
-static const char *
-register_name(ireg, boosted, regmask)
-unsigned ireg, *regmask;
-int boosted;
-{
-    if (!boosted)
-	*regmask |= (1 << ireg);
-    return save.reg_names[boosted ? ireg + 32 : ireg];
-}
-
-/* public -- see dissassembler.h */
-int
-tdisasm(buffer, address, iword, ext, regmask, symbol_value, ls_register)
-char *buffer;
-unsigned char ext;	/* extension byte */
-unsigned address, iword, *regmask, *symbol_value, *ls_register;
-{
-    int return_value = 0;
-    char *bufptr = buffer;
-    boolean do_b_displacement = false;
-    boolean do_loadstore = false;
-    union mips_instruction i;
-    union extension_byte e;
-
-	*bufptr = 0;
-    i.word = iword;
-    e.byte = ext;
-    *regmask = *symbol_value = *ls_register = 0;
-
-    /* Put out the address and hex value of the instruction,
-       leaving bufptr set at the end */
-    if (save.addr_format) {
-	sprintf(bufptr, save.addr_format, address);
-	bufptr += strlen(bufptr);
-    }
-    if (save.value_format) {
-	sprintf(bufptr, save.value_format, iword);
-	bufptr += strlen(bufptr);
-    }
-
-    /* check for dynamic NOP */
-    if (e.e.dyn_nop) {
-	strcat(bufptr, "D.");
-	bufptr += 2;
-    }
-
-    /* decode the instruction */
-    switch (i.j_format.opcode) {
-
-    case spec_op:
-
-	if (i.word == 0x20) {
-	    strcat(bufptr, "nop");
-	    if (e.e.rd_boost)
-		strcat(bufptr, ".B");
-	    bufptr += strlen(bufptr);
-	    break;
-	} else if (i.r_format.func == addu_op && i.r_format.rt == ZERO) {
-	    sprintf(bufptr, "move%s\t%s,%s",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    bufptr += strlen(bufptr);
-	    break;
-	}
-	strcat(bufptr, spec_name[i.r_format.func]);
-	if (e.e.rd_boost)
-	    strcat(bufptr, ".B");
-	bufptr += strlen(bufptr);
-
-	switch (i.r_format.func) {
-	case sll_op:
-	case srl_op:
-	case sra_op:
-	    sprintf(bufptr, "\t%s,%s,%d",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask),
-		    i.r_format.re);
-	    break;
-	case sllv_op:
-	case srlv_op:
-	case srav_op:
-	    sprintf(bufptr, "\t%s,%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    break;
-	case mfhi_op:
-	case mflo_op:
-	    sprintf(bufptr, "\t%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask));
-	    break;
-	case jalr_op:
-	    return_value = 2;
-	    sprintf(bufptr, "\t%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    break;
-	case jr_op:
-	    return_value = 2;
-	    /* fall through */
-	case mtlo_op:
-	case mthi_op:
-	    sprintf(bufptr, "\t%s",
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask));
-	    break;
-	case mult_op:
-	case multu_op:
-	case div_op:
-	case divu_op:
-	    sprintf(bufptr, "\t%s,%s",
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask));
-	    break;
-	case syscall_op:
-	    break;
-	case break_op:
-	case vcall_op:
-	    {
-		char *format = "\t%d";
-		unsigned op2 = i.r_format.rd * 32 + i.r_format.re;
-
-		if (op2)
-		    format = "\t%d,%d";
-		sprintf(bufptr, format, i.r_format.rs*32+i.r_format.rt,
-			op2);
-	    }
-	    break;
-	default:
-	    sprintf(bufptr, "\t%s,%s,%s",
-		    register_name(i.r_format.rd, e.e.rd_boost, regmask),
-		    register_name(i.r_format.rs, e.e.rs_boost, regmask),
-		    register_name(i.r_format.rt, e.e.rt_boost, regmask));
-	    break;
-	};
-	break;
-
-    case bcond_op:
-	sprintf(bufptr, "%s%s\t%s,",
-		bcond_name[i.i_format.rt],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	do_b_displacement = true;
-	break;
-
-    case blez_op_T:
-    case bgtz_op_T:
-    case blez_op_N:
-    case bgtz_op_N:
-	sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	do_b_displacement = true;
-	break;
-    case beq_op_T:
-    case beq_op_N:
-	if (i.i_format.rs == ZERO && i.i_format.rt == ZERO) {
-	    strcat(bufptr, "b");
-	    if (i.j_format.opcode == beq_op_T)
-		strcat(bufptr, ".T");
-	    else
-		strcat(bufptr, ".N");
-	    if (e.e.rd_boost)
-		strcat(bufptr, ".B\t");
-	    else
-		strcat(bufptr, "\t");
-	    do_b_displacement = true;
-	    break;
-	}
-	/* fall through */
-    case bne_op_T:
-    case bne_op_N:
-	sprintf(bufptr, "%s%s\t%s,%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rs, e.e.rs_boost, regmask),
-		register_name(i.i_format.rt, e.e.rt_boost, regmask));
-	do_b_displacement = true;
-	break;
-
-    case cop0_op:
-    case cop1_op:
-    case cop2_op:
-    case cop3_op:
-	{
-	    unsigned which_cop = i.j_format.opcode - cop0_op;
-	    char *f_or_r = "rf";
-
-	    switch (i.r_format.rs) {
-	    case bc_op_T:
-		sprintf(bufptr, "bc%d%c.T%s\t", which_cop,
-			"ft"[i.r_format.rt],
-			e.e.rd_boost ? ".B" : "");
-		do_b_displacement = true;
-		break;
-	    case bc_op_N:
-		sprintf(bufptr, "bc%d%c.N%s\t", which_cop,
-			"ft"[i.r_format.rt],
-			e.e.rd_boost ? ".B" : "");
-		do_b_displacement = true;
-		break;
-	    case mtc_op:
-		if (which_cop == 0)
-		    sprintf(bufptr, "mtc%d%s\t%s,%s", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    c0_reg[i.f_format.rd]);
-		else
-		    sprintf(bufptr, "mtc%d%s\t%s,%c%d", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    f_or_r[(which_cop == 1)],
-			    i.f_format.rd);
-		break;
-	    case mfc_op:
-		if (which_cop == 0)
-		    sprintf(bufptr, "mfc%d%s\t%s,%s", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    c0_reg[i.f_format.rd]);
-		else
-		    sprintf(bufptr, "mfc%d%s\t%s,%c%d", which_cop,
-			    e.e.rd_boost ? ".B" : "",
-			    register_name(i.r_format.rt, e.e.rt_boost,regmask),
-			    f_or_r[(which_cop == 1)],
-			    i.f_format.rd);
-		break;
-	    case cfc_op:
-		sprintf(bufptr, "cfc%d%s\t%s,%c%d", which_cop,
-			e.e.rd_boost ? ".B" : "",
-			register_name(i.r_format.rt, e.e.rt_boost, regmask),
-			f_or_r[(which_cop == 1)],
-			i.f_format.rd);
-		break;
-	    case ctc_op:
-		sprintf(bufptr, "ctc%d%s\t%s,%c%d", which_cop,
-			e.e.rd_boost ? ".B" : "",
-			register_name(i.r_format.rt, e.e.rt_boost, regmask),
-			f_or_r[(which_cop == 1)],
-			i.f_format.rd);
-		break;
-	    default:
-		if (which_cop != 1)
-		    sprintf(bufptr, "c0%s\t%s", e.e.rd_boost ? ".B" : "",
-			    c0_opname[i.f_format.func]);
-		else
-		    {
-			sprintf(bufptr, "%s.%s%s\t",
-				cop1_name[i.f_format.func],
-				fmt_name[i.f_format.fmt],
-				e.e.rd_boost ? ".B" : "");
-			bufptr += strlen(bufptr);
-			switch (i.f_format.func) {
-			case fsqrt_op:
-			case fabs_op:
-			case fmov_op:
-			case fcvts_op:
-			case fcvtd_op:
-			case fcvte_op:
-			case fcvtw_op:
-			    sprintf(bufptr, "f%d,f%d",
-				    i.f_format.re,
-				    i.f_format.rd);
-			    break;
-			case fcmp_op+0x0:
-			case fcmp_op+0x1:
-			case fcmp_op+0x2:
-			case fcmp_op+0x3:
-			case fcmp_op+0x4:
-			case fcmp_op+0x5:
-			case fcmp_op+0x6:
-			case fcmp_op+0x7:
-			case fcmp_op+0x8:
-			case fcmp_op+0x9:
-			case fcmp_op+0xa:
-			case fcmp_op+0xb:
-			case fcmp_op+0xc:
-			case fcmp_op+0xd:
-			case fcmp_op+0xe:
-			case fcmp_op+0xf:
-			    sprintf(bufptr, "f%d,f%d",
-				    i.f_format.rd,
-				    i.f_format.rt);
-			    break;
-			default:
-			    sprintf(bufptr, "f%d,f%d,f%d",
-				    i.f_format.re,
-				    i.f_format.rd,
-				    i.f_format.rt);
-			    break;
-			}	/* switch on func */
-		    }
-		break;		/* End of default */
-	    }			/* switch on rs */
-	}
-	break;			/* End of cop0, cop1, cop2, cop3 */
-
-    case jal_op:
-    case j_op:
-	sprintf(bufptr, "%s%s\t", op_name[i.j_format.opcode],
-		e.e.rd_boost ? ".B" : "");
-	*symbol_value = (address & 0xF0000000) | i.j_format.target << 2;
-	if (save.print_jal_targets)
-	    {
-		bufptr += strlen(bufptr);
-		sprintf(bufptr, "%#x", *symbol_value);
-	    }
-	return_value = 1;
-	break;
-
-    case swc1_op:
-    case sdc1_op:
-    case lwc1_op:
-    case ldc1_op:
-	sprintf(bufptr, "%s%s\tf%d,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		i.i_format.rt);
-	do_loadstore = true;
-	break;
-
-    case lb_op:
-    case lh_op:
-    case lw_op:
-    case ld_op:
-    case lbu_op:
-    case lhu_op:
-    case sb_op:
-    case sh_op:
-    case sw_op:
-    case sd_op:
-    case lwl_op:
-    case lwr_op:
-	sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.i_format.rt, e.e.rt_boost, regmask));
-	do_loadstore = true;
-	break;
-
-    case ori_op:
-    case xori_op:
-	if (i.u_format.rs == ZERO) {
-	    sprintf(bufptr, "li%s\t%s,%d",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		    i.u_format.uimmediate);
-	    break;
-	}
-	/* fall through */
-    case andi_op:
-	sprintf(bufptr, "%s%s\t%s,%s,%#x", op_name[i.u_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		register_name(i.u_format.rs, e.e.rs_boost, regmask),
-		i.u_format.uimmediate);
-	break;
-    case lui_op:
-	sprintf(bufptr, "%s%s\t%s,%#x", op_name[i.u_format.opcode],
-		e.e.rd_boost ? ".B" : "",
-		register_name(i.u_format.rt, e.e.rt_boost, regmask),
-		i.u_format.uimmediate);
-	break;
-    case addi_op:
-    case addiu_op:
-	if (i.i_format.rs == ZERO) {
-	    short sign_extender = i.i_format.simmediate;
-	    sprintf(bufptr, "li%s\t%s,%d",
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.i_format.rt, e.e.rt_boost, regmask),
-		    sign_extender);
-	    break;
-	}
-	/* fall through */
-    default:
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    sprintf(bufptr, "%s%s\t%s,%s,%d", op_name[i.i_format.opcode],
-		    e.e.rd_boost ? ".B" : "",
-		    register_name(i.i_format.rt, e.e.rt_boost, regmask),
-		    register_name(i.i_format.rs, e.e.rs_boost, regmask),
-		    sign_extender);
-	}
-	break;
-    }
-
-    /* Some instructions require more than just registers */
-
-    if (do_loadstore)
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    *symbol_value = sign_extender;
-	    *ls_register = i.i_format.rs;
-	    bufptr += strlen(bufptr);
-	    sprintf(bufptr, "%d(%s)", sign_extender,
-		    register_name(i.i_format.rs, e.e.rs_boost, regmask));
-	    return_value = -1;
-	}
-    else if (do_b_displacement)
-	{
-	    short sign_extender = i.i_format.simmediate;
-	    bufptr += strlen(bufptr);
-	    sprintf(bufptr, "%#x", 4 + address + ((((long)sign_extender & 0xFFFD0000) | (0x3FFFF & (sign_extender << 2)))));
-//	    sprintf(bufptr, "%#x", (long)sign_extender);
-	    return_value = 2;
-	}
-
-    return return_value;
-}
-
-static long instrs[10]={
-    0x0411000a,
-    0x03e0f021,
-    0x02feb023,
-    0x24010050,
-    0x10360044,
-    0x24010090,
-    0x10360046,
-    0x240100b8,
-    0x10360048,
-    0x240100d0
-    };
-
-int main(void)
-{
-	int i;
-    int junk;
-    char buf[80];
-    long *pInstr = (long*)instrs;
-
-    for (i=0; i < 10; i++)
-    {
-	    tdisasm(buf, (long)&pInstr[i], pInstr[i], 0, &junk, &junk, &junk);
-	    printf("%s\n", buf);
-	}
-    return 0;
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/test_timer.c b/lib/CPUs/MIPS/bsp/examples/test_timer.c
deleted file mode 100644
index 91b5a78..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_timer.c
+++ /dev/null
@@ -1,40 +0,0 @@
-#include "libsys.h"
-
-
-int g_cnt;
-void handler7(void)
-{
-	UINT32 *pGPIO0 = (UINT32*)SYS_GPIO0;
-	UINT32 *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	if (*pTim_stat & 1)
-	{
-		*pTim_stat = 1;
-		*pGPIO0 = g_cnt++;
-	}
-
-}
-
-int main (void)
-{
-	UINT32 *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 *pTim_cnt = (UINT32*)SYS_ITIM_CNT;
-	UINT32 *pTim_cmp = (UINT32*)SYS_ITIM_CMP;
-	UINT32 *pGPIO0 = (UINT32*)SYS_GPIO0;
-
-	g_cnt = 1;
-	*pGPIO0 = 0;
-
-	interrupt_register(7, handler7);
-	interrupt_enable(7);
-
-	*pTim_cnt = 0;
-	*pTim_cmp = 2000;
-	*pTim_stat = 1;
-	*pTim_ctrl = 3;
-
-	while(1);
-
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/test_vga.c b/lib/CPUs/MIPS/bsp/examples/test_vga.c
deleted file mode 100644
index 7919abd..0000000
--- a/lib/CPUs/MIPS/bsp/examples/test_vga.c
+++ /dev/null
@@ -1,206 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-
-#define	CPU_FREQ_HZ	100000000
-#include "libsys.h"
-#include "irq.h"
-#include "mips_gfx.h"
-#include "mips_ps2.h"
-
-static volatile INT32 mouse_x;
-static volatile INT32 mouse_y;
-static box_t box;
-static gfx_t gfx;
-static volatile int _g_posx, _g_posy;
-static volatile g_btn_l, g_btn_r;
-static volatile UINT32 g_color;
-
-// -------------------------------------------------------------
-void handler5(void)
-{
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-
-	// Ack
-	*pVGA_ctrl |= SYS_VGA_BIT_BUFCHG_FLAG;
-
-}
-
-void handler6(void)
-{
-	int p, i;
-	ps2_if_t *pIF;
-	UINT8 mouse_rsp[3];
-	UINT32 timeout_count, key;
-
-	INT32 dx, dy;
-
-	for (p=0; p < PS2_get_num_if(); p++)
-	{
-		pIF = PS2_get_if(p);
-		if (SYS_PS2_BIT_RX_ERR_FLAG & *pIF->pCTRL)
-			fprintf(stderr, "PS2[%d]: Status = 0x%08X\n", p, *pIF->pCTRL);
-
-		if (pIF->type == ps2_type_keyb)
-		{
-			while(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL)
-			{
-				key = *pIF->pDATA;
-				printf("Keyboard scan code = 0x%02X\n", key);
-			}
-		}
-		if (pIF->type == ps2_type_mouse)
-		{
-			if(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL))
-				continue;
-
-			for (i=0; i < 3; i++)
-			{
-				timeout_count = 100;
-				while(!(SYS_PS2_BIT_RX_IRQ & *pIF->pCTRL))
-				{
-					timeout_count--;
-					if (!timeout_count)
-					{
-						break;
-					}
-					sleep(1);
-				}
-				if (!timeout_count)
-				{
-					break;
-				}
-				mouse_rsp[i] = (UINT8)*pIF->pDATA;
-			}
-			if (!timeout_count)
-			{
-				continue;
-			}
-			dx = mouse_rsp[1];
-			if (mouse_rsp[0] &  0x10)
-				dx |= 0xFFFFFF00;
-			dy = mouse_rsp[2];
-			if (mouse_rsp[0] &  0x20)
-				dy |= 0xFFFFFF00;
-
-//			printf("dx = %5d, dy = %5d\n", dx, dy);
-
-			mouse_x += dx;
-			mouse_y -= dy;
-			g_btn_l = 0;
-			if (mouse_rsp[0] & 0x01)
-				g_btn_l = 1;
-
-			if (mouse_rsp[0] & 0x02)
-			{
-				if (g_btn_r == 0)
-				{
-					g_color  = (UINT32)rand();
-				}
-				g_btn_r = 1;
-			}
-			else
-				g_btn_r = 0;
-
-
-			if (mouse_x < 0)
-				mouse_x = 0;
-			if (mouse_y < 0)
-				mouse_y = 0;
-			if (mouse_x > (gfx.w-1))
-				mouse_x = gfx.w-1;
-			if (mouse_y >= (gfx.h-1))
-				mouse_y = gfx.h-1;
-
-//			Screen_csr_set_x(mouse_x);
-//			Screen_csr_set_y(mouse_y);
-
-//			printf("x = %5d, y = %5d\n", mouse_x, mouse_y);
-
-		}
-	}
-}
-
-int main(void)
-{
-
-	int i;
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT;
-	UINT32 volatile *pVGA_moffs_1 = (UINT32*)SYS_VGA_FB_BACK;
-	UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL;
-	UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000);
-	UINT32 framecount;
-	UINT32 start, end;
-
-	interrupt_register(5, (void*)handler5);
-	interrupt_register(6, (void*)handler6);
-
-	srand(clock());
-	UART1_setbaud(460800);
-
-	*pVGA_cgcol = 0x00FFFFFF;
-	_g_posx = _g_posy = 0;
-	g_color = 0xFFFFFFFF;
-	GFX_init(&gfx);
-
-	GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1);
-	box_create(&box, 256, 256);
-	GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color);
-	GFX_show(&gfx);
-	printf("VGA status = %08X\n", *pVGA_ctrl);
-
-	PS2_init(0);
-	PS2_init(1);
-
-	// Flush buffer
-	PS2_flush(0);
-	PS2_flush(1);
-
-//	interrupt_enable(5);
-	interrupt_enable(6);
-
-	framecount = Screen_get_fps();
-	start = clock();
-
-	while(1)
-	{
-		if (!framecount)
-		{
-			end = clock();
-			framecount = Screen_get_fps();
-			printf("%f FPS\n", (float)framecount/((float)(end-start)/CLOCKS_PER_SEC));
-			start = clock();
-		}
-
-		GFX_frame(&gfx, GFX_FRAME_SYNC);
-		framecount--;
-
-		while ((_g_posx != (UINT32)mouse_x) || (_g_posy != (UINT32)mouse_y) || g_btn_r || g_btn_l)
-		{
-
-			GFX_restore(&gfx, &box, _g_posx, _g_posy);
-
-			_g_posx = (UINT32)mouse_x;
-			_g_posy = (UINT32)mouse_y;
-
-			if (g_btn_l && !g_btn_r)
-			{
-				GFX_box_draw_bg(&gfx, &box, _g_posx, _g_posy, g_color);
-			}
-
-			if (g_btn_l && g_btn_r)
-			{
-				GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1);
-			}
-
-			GFX_box_draw(&gfx, &box, _g_posx, _g_posy, g_color);
-			break;
-		}
-		GFX_show(&gfx);
-	}
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/testbench.c b/lib/CPUs/MIPS/bsp/examples/testbench.c
deleted file mode 100644
index 15d921d..0000000
--- a/lib/CPUs/MIPS/bsp/examples/testbench.c
+++ /dev/null
@@ -1,1229 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-#include <time.h>
-#include <sys/times.h>
-#include <sys/time.h>
-#include "libsys.h"
-#include "mips_gfx.h"
-
-#define	TEST10_ERROR	(ERROR | 0x1000)
-#define	TEST11_ERROR	(ERROR | 0x1100)
-#define	TEST12_ERROR	(ERROR | 0x1200)
-#define	TEST13_ERROR	(ERROR | 0x1300)
-#define	TEST14_ERROR	(ERROR | 0x1400)
-#define	TEST15_ERROR	(ERROR | 0x1500)
-#define	TEST16_ERROR	(ERROR | 0x1600)
-
-#define PIC_NX			800
-#define PIC_NY			600
-
-extern int paranoia(int argc, char **argv);
-
-UINT32* pf(void)
-{
-	static UINT32 p;
-
-	return &p;
-}
-
-volatile UINT32 _g_blitter_rdy;
-void ISR_blitter_rdy(void)
-{
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-
-	if (*pVGA_ctrl & SYS_VGA_BIT_BLIT_FIN)
-	{
-		putchar('.');
-		// Ack
-		*pVGA_ctrl |= SYS_VGA_BIT_BLIT_ACK;
-		_g_blitter_rdy = 1;
-	}
-}
-
-// -------------------------------------------------------------
-void LoadPic(UINT64 *pScreen, UINT32 screen_nx, UINT32 screen_ny, UINT32 *pImage, UINT32 image_nx, UINT32 image_ny, UINT32 image_scale_x, UINT32 image_scale_y)
-{
-
-	UINT32 off_x, off_y;
-	UINT32 i, j, black;
-	UINT32 *pScr, *pImg;
-
-	off_x = (screen_nx-(image_scale_x*image_nx))/2;
-	off_y = (screen_ny-(image_scale_y*image_ny))/2;
-
-	black = 0;
-	pScr = (UINT32*)pScreen;
-	for (i=0; i < screen_nx*screen_ny; i += 8)
-	{
-		__gfx_block_set_8(pScr, 0);
-		pScr += 8;
-	}
-
-	if (!pImage)
-		return;
-
-	pScr = ((UINT32*)pScreen) + screen_nx*off_y + off_x;
-	pImg = pImage;
-
-	for (i=0; i < image_ny*image_nx; i += 8)
-	{
-		__gfx_block_copy_8(pScr, pImg);
-		pScr += 8;
-		pImg += 8;
-	}
-
-/*
-	UINT32 off_x, off_y;
-	UINT32 i;
-	UINT32 *pScr;
-
-	off_x = (screen_nx-(image_scale_x*image_nx))/2;
-	off_y = (screen_ny-(image_scale_y*image_ny))/2;
-
-	memset(pScreen, 0, screen_nx*screen_ny*sizeof(UINT32));
-	pScr = ((UINT32*)pScreen) + screen_nx*off_y + off_x;
-
-	for (i=0; i < image_ny; i++)
-	{
-		memcpy(pScr, &pImage[i*image_nx], image_nx*sizeof(UINT32));
-		pScr += screen_nx;
-	}
-*/
-}
-
-int IsEndianBig(void)
-{
-	UINT8 *pBuf;
-	UINT32 word;
-	word = 0x12345678;
-	pBuf = (UINT8*)&word;
-	if (((*pBuf+0) == 0x12) && (*(pBuf+1) == 0x34) && (*(pBuf+2) == 0x56) && (*(pBuf+3) == 0x78))
-	{
-		return 1;
-	}
-	if (((*pBuf+0) == 0x78) && (*(pBuf+1) == 0x56) && (*(pBuf+2) == 0x34) && (*(pBuf+3) == 0x12))
-	{
-		return 0;
-	}
-	return -1;
-}
-
-void handler3(void)
-{
-	volatile UINT32 *pUART_stat = (UINT32*)SYS_UART_STAT;
-	volatile UINT32 *pUART_data = (UINT32*)SYS_UART_DATA;
-
-	if((0x10 & *pUART_stat))
-	{
-		_putchar(0, (char)*pUART_data);
-	}
-
-}
-
-int g_cnt;
-box_t box;
-gfx_t gfx;
-int posx, posy;
-
-void handler7(void)
-{
-	UINT32 volatile *pGPIO0 = (UINT32*)SYS_GPIO0;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
-	time_t curr_date;
-	struct tm *pDate;
-
-	if (*pTim0_cmp < 0x200)
-	{
-		*pTim0_cmp = 0x200;
-	}
-	if (*pTim_stat & 1)
-	{
-		*pTim_stat = 1;
-		*pGPIO0 = g_cnt++;
-		GFX_frame(&gfx, GFX_FRAME_NOSYNC);
-		GFX_restore(&gfx, &box, posx, posy);
-		GFX_show(&gfx);
-
-		posx = (UINT32)rand()%800;
-		posy = (UINT32)rand()%600;
-		GFX_frame(&gfx, GFX_FRAME_NOSYNC);
-		GFX_box_draw(&gfx, &box, posx, posy, (UINT32)rand());
-		GFX_show(&gfx);
-	}
-
-	if (*pTim_stat & 4)
-	{
-		*pTim_stat = 4;
-		curr_date = time(NULL);
-		pDate = gmtime(&curr_date);
-		fprintf(stderr, "%s", asctime(pDate));
-	}
-
-}
-
-int fibonacci(int f0, int f1, int *pDst, int len)
-{
-	int i;
-
-	i = 0;
-
-	pDst[i++] = f0;
-	pDst[i++] = f1;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-2] + pDst[i-1];
-	}
-
-	return i;
-}
-
-void PrintCPUinfo(void)
-{
-	int result, rev_id;
-	int cache_size, cache_line;
-	int eb;
-
-	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
-
-	// Print Status register
-	result = CP0_SR_read();
-
-	printf("--------------------------------------------------\n");
-	printf("Status   : %8.8X\n", result);
-
-	// Print Revision
-	result = CP0_PRID_read();
-	rev_id = (result >> 8) & 0xFF;
-	printf("CPU type : MIPS ");
-	if ((rev_id > 0) && (rev_id < 0x07))
-	{
-		printf(cpu_type_str[rev_id]);
-		printf(" Rev. ");
-		rev_id = result & 0xFF;
-		printf("%d", rev_id);
-	}
-	else
-		printf("Unknown");
-
-	eb = IsEndianBig();
-	if (eb)
-		printf(" [Big-endian]\n");
-	if (!eb)
-		printf(" [Little-endian]\n");
-	if (eb < 0)
-		printf(" [Unknown endian]\n");
-
-	cache_size = (result >> 16) & 7;
-	cache_line = (result >> 19) & 7;
-	printf("I-Cache  : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line)));
-	cache_size = (result >> 24) & 7;
-	cache_line = (result >> 27) & 7;
-	printf("D-Cache  : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line)));
-	printf("--------------------------------------------------\n");
-
-}
-
-UINT32 uncached_cachemiss_bug(void)
-{
-	UINT32 result;
-	UINT32 pMem[2];
-
-	pMem[0] = 0x12345678;
-	pMem[1] = 0xFFFFFFFF;
-
-	__asm__
-	(
-		"cop0	34\n"
-		"lui    $s0, 0xA000\n"
-		"lw     $a0, 48($s0)\n"
-		"or		$s1, $a0, $0\n"
-		"or		$a2, $0, $0\n"
-		"addiu	$a2, 0x7F00\n"
-		"sw     $a2, 48($s0)\n"
-//		"lw     $a1, 0(%[pMem])\n"
-		"lw     $a0, 48($s0)\n"
-		"lw     $a2, 4(%[pMem])\n"
-		"lw     $a1, 0(%[pMem])\n"
-		"nop\n"
-		"sw     $s1, 48($s0)\n"
-		"or		%[val], $a0, $0\n"
-		: [val] "=r" (result)
-		: [pMem] "r" (pMem)
-		: "a0", "a1", "a2", "s0", "s1"
-	);
-	return result;
-}
-
-UINT32 non_aligned_load()
-{
-	UINT32 result;
-	UINT32 pMem[3];
-
-	__asm__
-	(
-		"li     $t0, 0x01234567\n"
-		"li     $t1, 0x89ABCDEF\n"
-		"sw     $t0, 0(%[pMem])\n"
-		"sw     $t1, 4(%[pMem])\n"
-		"li     %[val], 0x55555555\n"
-		"lw     %[val], 0(%[pMem])\n"
-		"lwl    %[val], 5(%[pMem])\n"
-		: [val] "=r" (result)
-		: [pMem] "r" (pMem)
-		: "t0", "t1"
-	);
-
-	if (0 == IsEndianBig())
-	{
-		if (0xCDEF4567 != result)
-			return ERROR;
-	}
-	else
-	{
-		if (0xABCDEF67 != result)
-			return ERROR;
-	}
-	return 0;
-
-}
-
-int Test10_LoadStore()
-{
-	int *buf, i, result, data, err;
-	volatile int *pPtr;
-
-	buf = (int*)malloc(32*sizeof(int));
-//	sputs("buf = ");
-//	print_word((int)buf);
-//	sputs("\n");
-
-	while(1)
-	{
-		err = TEST10_ERROR;
-		// Basic Load/Store
-		pPtr = buf;
-		*pPtr++ = 0x00000000;
-		*pPtr++ = 0x55555555;
-		*pPtr++ = 0xAAAAAAAA;
-		*pPtr++ = 0xFFFFFFFF;
-		pPtr = buf;
-		if (*pPtr++ != 0x00000000)
-			break;
-		if (*pPtr++ != 0x55555555)
-			break;
-		if (*pPtr++ != 0xAAAAAAAA)
-			break;
-		if (*pPtr++ != 0xFFFFFFFF)
-			break;
-
-		// Filling from left
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data >> 1 | 0x80000000;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data >> 1 | 0x80000000;
-		}
-		if (i != 32)
-			break;
-
-		// Filling from right
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking ones
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking zeros
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-
-		}
-		if (i != 32)
-			break;
-
-		err = NO_ERROR;
-		break;
-	}
-	free(buf);
-
-	if (IS_ERROR(err))
-		return err;
-
-	if (IS_ERROR(non_aligned_load()))
-		return TEST10_ERROR | 1;
-
-	if (IS_ERROR(uncached_cachemiss_bug()))
-		return TEST10_ERROR | 2;
-
-	return NO_ERROR;
-
-}
-
-
-#define	NUM_ELEMENTS	10000
-#define	NUM_RUNS		3
-int Test11_AddSub()
-{
-	int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs;
-
-	fill = 0xAAAAAAAA;
-
-	num_right_runs = 0;
-
-	for (i=0; i < NUM_RUNS; i++)
-	{
-		for (j=0;  j < NUM_ELEMENTS; j++)
-		{
-			buf[j] = fill;
-			fill = ((fill ^ j) - 1) << 1;
-		}
-		num_right_elements = 2;
-		result = fibonacci(i, i+1, buf, NUM_ELEMENTS);
-		for (j=2;  j < NUM_ELEMENTS; j++)
-		{
-			diff = buf[j] - buf[j-1];
-			if (diff == buf[j-2])
-				num_right_elements++;
-		}
-		if (num_right_elements == NUM_ELEMENTS)
-			num_right_runs++;
-
-	}
-
-	if (num_right_runs != NUM_RUNS)
-		return TEST11_ERROR;
-
-	return NO_ERROR;
-}
-
-int Test12_MulDiv()
-{
-	int mix, i, j;
-	int s1, s2, sp, st;
-	div_t div_res;
-	long cl;
-
-	cl = (long)clock();
-	srand(cl);
-	for (i=0; i < 100; i++)
-	{
-		for (j=1; j < 100; j++)
-		{
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s1 = (int)rand() ^ mix;
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s2 = (int)rand() ^ mix;
-			if (!s2)
-			{
-				fprintf(stderr, "Test12_MulDiv(): Division by zero!\n");
-				fprintf(stderr, "Clock() was 0x%8.8X\n", cl);
-				continue;
-			}
-
-			div_res = div(s1, s2);
-
-			sp = s2*div_res.quot;
-			st = div_res.rem + sp;
-			if (st != s1)
-				return TEST12_ERROR;
-		}
-	}
-	return NO_ERROR;
-}
-
-int Test13_COP0_Load_Store(void)
-{
-    int i,size;
-	UINT32 *pSrc32, *pDst32;
-
-	size = 0x2000;
-	pSrc32 = (UINT32*)0xBFC00000;
-	pDst32 = (UINT32*)calloc(size,sizeof(UINT32));
-	for (i=0; i < size/4; i++)
-	{
-		CP0_TR_read_ptr(&pSrc32[i]);
-		CP0_TR_write_ptr(&pDst32[i]);
-	}
-	for (i=size/4-1; i >= 0; i--)
-		if (pDst32[i] != pSrc32[i])
-			break;
-
-	free(pDst32);
-	i++;
-	if (i)
-		return TEST13_ERROR;
-
-	return NO_ERROR;
-}
-
-int Test14_DCACHE_invalidate(void)
-{
-    int i,size;
-	UINT32 *pSrc32, *pDst32;
-
-	size = 0x2000;
-	pSrc32 = (UINT32*)0xBFC00000;
-	pDst32 = (UINT32*)calloc(size,sizeof(UINT32));
-	for (i=0; i < size/4; i++)
-	{
-		pDst32[i] = pSrc32[i];
-		DCACHE_invalidate_at(&pDst32[i]);
-	}
-	for (i=size/4-1; i >= 0; i--)
-	{
-		DCACHE_invalidate_at(&pDst32[i]);
-		if (pDst32[i] != pSrc32[i])
-			break;
-	}
-
-	free(pDst32);
-	i++;
-	if (i)
-		return TEST14_ERROR;
-
-	pDst32 = (UINT32*)calloc(size,sizeof(UINT32));
-	for (i=0; i < size/4; i++)
-	{
-		pDst32[i] = pSrc32[i];
-	}
-	DCACHE_invalidate_all();
-	for (i=size/4-1; i >= 0; i--)
-		if (pDst32[i] != pSrc32[i])
-			break;
-
-	free(pDst32);
-	i++;
-	if (i)
-		return TEST14_ERROR;
-
-	return NO_ERROR;
-}
-
-#define PI_SCALE 10000
-#define PI_MAXARR 2800
-#define PI_ARRINIT 2000
-
-int Test15_pi_calc()
-{
-	int i, j, k;
-	int carry = 0;
-	int arr[PI_MAXARR+1];
-	UINT32 int_part, result;
-	UINT16 pi_res[200] = {0};
-	UINT16 pi_ref[200] =
-	{
-		3141,5926,5358,9793,2384,6264,3383,2795, 288,4197,1693,9937,5105,8209,7494,4592,3078,1640,6286,2089,9862,8034,8253,4211,
-		7067,9821,4808,6513,2823, 664,7093,8446, 955, 582,2317,2535,9408,1284,8111,7450,2841, 270,1938,5211, 555,9644,6229,4895,
-		4930,3819,6442,8810,9756,6593,3446,1284,7564,8233,7867,8316,5271,2019, 914,5648,5669,2346, 348,6104,5432,6648,2133,9360,
-		7260,2491,4127,3724,5870, 660,6315,5881,7488,1520,9209,6282,9254, 917,1536,4367,8925,9036,  11,3305,3054,8820,4665,2138,
-		4146,9519,4151,1609,4330,5727, 365,7595,9195,3092,1861,1738,1932,6117,9310,5118,5480,7446,2379,9627,4956,7351,8857,5272,
-		4891,2279,3818,3011,9491,2983,3673,3624,4065,6643, 860,2139,4946,3952,2473,7190,7021,7986, 943,7027,7053,9217,1762,9317,
-		6752,3846,7481,8467,6694, 513,2000,5681,2714,5263,5608,2778,5771,3427,5778,9609,1736,3717,8721,4684,4090,1224,9534,3014,
-		6549,5853,7105, 792,2796,8925,8923,5420,1995,6112,1290,2196, 864, 344,1815,9813,6297,7477,1309,9605,1870,7211,3499,9999,
-		8372,9780,4995,1059,7317,3281,6096,3185
-	};
-
-	//	setbuf(stdout, NULL);
-	k = 0;
-	for (i = 0; i <= PI_MAXARR; ++i)
-		arr[i] = PI_ARRINIT;
-
-	for (i = PI_MAXARR; i; i -= 14)
-	{
-		int sum = 0;
-		for (j = i; j > 0; --j)
-		{
-			sum = sum*j + PI_SCALE*arr[j];
-			arr[j] = sum % (j*2-1);
-			sum /= (j*2-1);
-		}
-		result = carry + sum/PI_SCALE;
-		int_part = PI_SCALE * (result / PI_SCALE);
-		pi_res[k] = (UINT16)(result - int_part);
-		carry = sum % PI_SCALE;
-		k++;
-	}
-
-	for (k=0; k < sizeof(pi_ref)/sizeof(UINT16); k++)
-	{
-		printf("%d", pi_res[k]);
-	}
-	printf("\n");
-
-	if(memcmp(pi_res, pi_ref, sizeof(pi_ref)))
-		return TEST15_ERROR;
-
-	return NO_ERROR;
-}
-
-#define	TEST_SIZE			(16*1024*1024)	// Bytes
-#define	SMALL_TEST_SIZE		(8192)			// Bytes
-#define	FLASH_SIZE			(8*1024*1024)	// Bytes
-
-int Test16_MemTest(void)
-{
-	int result, i, j, cnt, size;
-	UINT8 *ram8 = NULL;
-	UINT16 *ram16 = NULL;
-	UINT32 *ram32 = NULL;
-	UINT32 volatile *pFlashIO = (UINT32*)SYS_FLASH_IO;
-	UINT32 volatile *pFlashMem = (UINT32*)SYS_FLASH_MEM;
-	UINT32 volatile *pROM = (UINT32*)0xBFC00000;
-	UINT32 volatile *pVGA_src0 = (UINT32*)SYS_VGA_BLIT_SRC0;
-	UINT32 volatile *pVGA_dst = (UINT32*)SYS_VGA_BLIT_DST;
-	UINT32 volatile *pVGA_dimx_src0 = (UINT32*)SYS_VGA_BLIT_SRC0_DIMX;
-	UINT32 volatile *pVGA_dimx_dst = (UINT32*)SYS_VGA_BLIT_DST_DIMX;
-	UINT32 volatile *pVGA_nx = (UINT32*)SYS_VGA_BLIT_NX;
-	UINT32 volatile *pVGA_ny = (UINT32*)SYS_VGA_BLIT_NY;
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT;
-
-
-	UINT32 *pSrc32, *pDst32;
-	UINT32 start, end;
-
-	// ----------------------------------------------------------
-	// Memtest BEGIN
-/*	printf("SSRAM Memory Test\r\n");
-	printf("Small data test\r\n");
-	printf("Write (32-Bit access)...");
-	start = clock();
-	for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++)
-		for (i=0; i < SMALL_TEST_SIZE/4; i++)
-			pSSRAM[i] = (UINT32)i;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start)));
-
-	PrintBuffer8((UINT8*)pSSRAM, 16, 256);
-
-	printf("Verify (32-Bit access)...");
-	start = clock();
-	for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++)
-		for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--)
-			if (pSSRAM[i] != (UINT32)i)
-				break;
-
-	end = clock();
-	i++;
-	if (i)
-		printf("failed\r\n");
-	else
-		printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start)));
-*/
-	// ----------------------------------------------------------
-	pSrc32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32));
-	pDst32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32));
-
-	// Memtest BEGIN
-	printf("Dump first 16 bytes of flash blocks\n");
-	for (i=0; i < FLASH_SIZE; i += 0x40000)
-		memdump((UINT8*)(pFlashIO+i/4), 0, 16, 16);
-
-	printf("\n");
-
-	printf("SDRAM Memory Test\n");
-	printf("Test size %d kByte\n\n", TEST_SIZE/1024);
-
-	ram8 = (UINT8*)pDst32;
-	printf("Zeroize SDRAM (memset)...");
-	start = clock();
-	memset(ram8, 0, TEST_SIZE);
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	printf("Zeroize SDRAM (8-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE; i++)
-		ram8[i] = (UINT8)0;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	ram16 = (UINT16*)pDst32;
-	printf("Zeroize SDRAM (16-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE/2; i++)
-		ram16[i] = (UINT16)0;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	ram32 = (UINT32*)pDst32;
-	printf("Zeroize SDRAM (32-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE/4; i++)
-		ram32[i] = (UINT32)0;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	ram8 = (UINT8*)pDst32;
-	printf("Write SDRAM (8-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE; i++)
-		ram8[i] = (UINT8)i;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	printf("Verify SDRAM (8-Bit access)...");
-	start = clock();
-	for (i=TEST_SIZE-1; i >= 0; i--)
-		if (ram8[i] != (UINT8)i)
-			break;
-
-	end = clock();
-	i++;
-	if (i)
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-	else
-		printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	ram16 = (UINT16*)pDst32;
-	printf("Write SDRAM (16-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE/2; i++)
-		ram16[i] = (UINT16)i;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	printf("Verify SDRAM (16-Bit access)...");
-	start = clock();
-	for (i=TEST_SIZE/2-1; i >= 0; i--)
-		if (ram16[i] != (UINT16)i)
-			break;
-
-	end = clock();
-	i++;
-	if (i)
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-	else
-		printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-
-	ram32 = (UINT32*)pDst32;
-	printf("Write SDRAM (32-Bit access)...");
-	start = clock();
-	for (i=0; i < TEST_SIZE/4; i++)
-	{
-		ram32[i] = (UINT32)i;
-	}
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	printf("Verify SDRAM (32-Bit access)...");
-	start = clock();
-	for (i=TEST_SIZE/4-1; i >= 0; i--)
-	{
-		if (ram32[i] != (UINT32)i)
-			break;
-	}
-
-	end = clock();
-	i++;
-	if (i)
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-	else
-		printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	printf("\n");
-	printf("Small data test (size = %d kByte)\n", SMALL_TEST_SIZE/1024);
-	printf("Write SDRAM (32-Bit access)...");
-	ram32 = (UINT32*)pDst32;
-	start = clock();
-	for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++)
-		for (i=0; i < SMALL_TEST_SIZE/4; i++)
-			ram32[i] = (UINT32)i;
-
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	// -------------------------------------------------------------------
-	// Verify
-	printf("Verify SDRAM (32-Bit access)...");
-	start = clock();
-	for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++)
-		for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--)
-			if (ram32[i] != (UINT32)i)
-				break;
-
-	end = clock();
-	i++;
-	if (i)
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-	else
-		printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-
-	for (i=1024; i < 4*65536; i *= 2)
-	{
-		printf("Memcpy() (%d kByte)...", i/1024);
-		start = clock();
-		for (j=0; j < TEST_SIZE/i; j++)
-			memcpy(pDst32, pSrc32, i);
-
-		end = clock();
-		printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	}
-	for (i=1024; i < 4*65536; i *= 2)
-	{
-		printf("__gfx_copy_32() (%d kByte)...", i/1024);
-		start = clock();
-		for (j=0; j < TEST_SIZE/i; j++)
-			__gfx_copy_32(pDst32, pSrc32, i/32);
-
-		end = clock();
-		printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	}
-	// -------------------------------------------------------------------
-	printf("\n");
-
-	printf("Memcpy() Flash(IO) => SDRAM \n");
-	printf("Copying %d kBytes...", FLASH_SIZE/(1024));
-	start = clock();
-	memcpy(pDst32, (UINT32*)pFlashIO, FLASH_SIZE);
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	printf("\n");
-
-	printf("Memcpy() Flash(MEM) => SDRAM \n");
-	printf("Copying %d kBytes...", FLASH_SIZE/(1024));
-	start = clock();
-	memcpy(pDst32, (UINT32*)pFlashMem, FLASH_SIZE);
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	printf("\n");
-
-	interrupt_register(5, (void*)ISR_blitter_rdy);
-	interrupt_enable(5);
-	*pVGA_ctrl |= SYS_VGA_BIT_BLIT_FIN_INTEN;
-	printf("Blitter speed test (scan disabled)...");
-	*pVGA_src0 = (UINT32)pSrc32;
-	*pVGA_dst = (UINT32)pDst32;
-	*pVGA_dimx_src0 = (UINT32)0;
-	*pVGA_dimx_dst = (UINT32)0;
-	*pVGA_nx = (UINT32)TEST_SIZE/4 - 1;
-	*pVGA_ny = (UINT32)0;
-
-	start = clock();
-	for (i=0; i < 10; i++)
-	{
-		_g_blitter_rdy = 0;
-		*pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-		while (!_g_blitter_rdy);
-	}
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)(10*TEST_SIZE)/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	printf("\n");
-
-	printf("Blitter speed test (scan enabled)...");
-	*pVGA_ctrl |= SYS_VGA_BIT_MSTEN;
-	sleep(500);
-	*pVGA_src0 = (UINT32)pSrc32;
-	*pVGA_dst = (UINT32)pDst32;
-	*pVGA_dimx_src0 = (UINT32)0;
-	*pVGA_dimx_dst = (UINT32)0;
-	*pVGA_nx = (UINT32)TEST_SIZE/4 - 1;
-	*pVGA_ny = (UINT32)0;
-
-	start = clock();
-	for (i=0; i < 10; i++)
-	{
-		_g_blitter_rdy = 0;
-		*pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-		while (!_g_blitter_rdy);
-	}
-	end = clock();
-	printf("done (%.2f MByte/s)\n", (double)(10*TEST_SIZE)/(1024*1024*(double)(end-start)/CLOCKS_PER_SEC));
-	printf("\n");
-	*pVGA_ctrl &= ~SYS_VGA_BIT_MSTEN;
-	*pVGA_ctrl &= ~SYS_VGA_BIT_BLIT_FIN_INTEN;
-	interrupt_disable(5);
-
-	size = 0x2000;
-	memcpy(pDst32, (UINT32*)pROM, size);
-	printf("Verify boot ROM...");
-	for (i=size/4-1; i >= 0; i--)
-		if (pDst32[i] != pROM[i])
-			break;
-	i++;
-	if (i)
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-	else
-		printf("passed\r\n");
-
-	printf("Verify FLASH(IO) <=> FLASH(MEM)...");
-	if (!memcmp((UINT32*)pFlashIO, (UINT32*)pFlashMem, FLASH_SIZE))
-		printf("passed\r\n");
-	else
-	{
-		printf("failed\r\n");
-		return TEST16_ERROR;
-	}
-
-//	memdump((UINT8*)pSrc32, 0, 16, size);
-//	memdump((UINT8*)0x40000000, 0, 16, 1024);
-
-	// Memtest END
-	// ----------------------------------------------------------
-	free(pSrc32);
-	free(pDst32);
-
-	sputs("\r\n");
-	return 0;
-}
-
-int main (void)
-{
-	int result, i, j, cnt, size;
-	UINT32 volatile *pUART_baud = (UINT32*)SYS_UART_BAUD;
-	UINT32 volatile *pUART_stat = (UINT32*)SYS_UART_STAT;
-	UINT32 volatile *pReg = (UINT32*)SYS_LED_PORT;
-	UINT32 volatile *pReg_usec = (UINT32*)SYS_TIMER_USEC;
-	UINT32 volatile *pReg_sec = (UINT32*)SYS_TIMER_SEC;
-	UINT32 volatile *pSSRAM = (UINT32*)SYS_SSRAM_IO;
-	UINT32 volatile *pTim_ctrl = (UINT32*)SYS_ITIM_CTRL;
-	UINT32 volatile *pTim_stat = (UINT32*)SYS_ITIM_STAT;
-	UINT32 volatile *pTim0_cnt = (UINT32*)SYS_ITIM0_CNT;
-	UINT32 volatile *pTim0_cmp = (UINT32*)SYS_ITIM0_CMP;
-	UINT32 volatile *pTim1_cnt = (UINT32*)SYS_ITIM1_CNT;
-	UINT32 volatile *pTim1_cmp = (UINT32*)SYS_ITIM1_CMP;
-	UINT32 volatile *pVGA_cgcol = (UINT32*)SYS_VGA_CGCOL;
-	UINT32 volatile *pFlashPicture = (UINT32*)(SYS_FLASH_MEM + 0x00600000);
-
-	UINT32 volatile *pVGA_src0 = (UINT32*)SYS_VGA_BLIT_SRC0;
-	UINT32 volatile *pVGA_dst = (UINT32*)SYS_VGA_BLIT_DST;
-	UINT32 volatile *pVGA_dimx_src0 = (UINT32*)SYS_VGA_BLIT_SRC0_DIMX;
-	UINT32 volatile *pVGA_dimx_dst = (UINT32*)SYS_VGA_BLIT_DST_DIMX;
-	UINT32 volatile *pVGA_nx = (UINT32*)SYS_VGA_BLIT_NX;
-	UINT32 volatile *pVGA_ny = (UINT32*)SYS_VGA_BLIT_NY;
-	UINT32 volatile *pVGA_ctrl = (UINT32*)SYS_VGA_CTRL;
-	UINT32 volatile *pVGA_moffs_0 = (UINT32*)SYS_VGA_FB_FRONT;
-
-	UINT32 screen_res_x, screen_res_y, screen_fps;
-	UINT64 *pBuf64_0, *pBuf64_1;
-	time_t curr_date;
-	struct tm *pDate, date;
-	UINT32 start, end;
-	char sel[80];
-	struct timeval time_sec;
-
-
-	g_cnt = 1;
-	Screen_clr();
-
-	*pVGA_cgcol = 0x00FFFFFF;
-
-	*pTim0_cnt = 0;
-	*pTim1_cnt = 0;
-	*pTim0_cmp = 0x4000;
-	*pTim1_cmp = 100000000;
-	*pTim_stat = (1 << 2) | (1 << 0);
-	*pTim_ctrl = (3 << 2);
-
-//	*pUART_baud = 1;
-
-	setbuf(stdout, NULL);
-	PrintCPUinfo();
-
-	interrupt_register(3, handler3);
-	fprintf(stderr, "UART interrupt registered.\n");
-
-	interrupt_register(7, handler7);
-	fprintf(stderr, "Timer interrupt registered.\n");
-
-	calibrate_delay();
-
-	printf("\n");
-
-	printf("Aktuelles Datum\n");
-	curr_date = time(NULL);
-	pDate = gmtime(&curr_date);
-	puts(asctime(pDate));
-
-	if (curr_date < 2)
-	{
-		printf("Datum und Uhrzeit setzen? [j/N]: ");
-		scanf("%s", sel);
-		if (toupper(sel[0]) == 'J')
-		{
-			do
-			{
-				printf("Datum\n");
-			printf("Jahr  : ");
-			scanf("%d", &date.tm_year);
-			printf("Monat : ");
-			scanf("%d", &date.tm_mon);
-			printf("Tag   : ");
-			scanf("%d", &date.tm_mday);
-
-				printf("Uhrzeit\n");
-				printf("Stunde  : ");
-				scanf("%d", &date.tm_hour);
-				printf("Minute  : ");
-				scanf("%d", &date.tm_min);
-				printf("Sekunde : ");
-				scanf("%d", &date.tm_sec);
-
-				date.tm_year  -= 1900;
-				date.tm_mon  -= 1;
-				time_sec.tv_sec = mktime(&date);
-				time_sec.tv_usec = 0;
-				settimeofday(&time_sec, NULL);
-
-				printf("Datum\n");
-				curr_date = time(NULL);
-				pDate = gmtime(&curr_date);
-				puts(asctime(pDate));
-				printf("\nOK? [J/n]: ");
-				scanf("%s", sel);
-				printf("sel=%d\n", (int)sel[0]);
-
-
-			} while(toupper(sel[0]) == 'N');
-		}
-	}
-	srand(clock());
-	*pReg = uncached_cachemiss_bug();
-	Test16_MemTest();
-
-	printf("pf  = %08X\n", (UINT32)pf());
-	*pf() = 0x1234;
-	printf("*pf = %08X\n", (UINT32)*pf());
-
-	box_create(&box, 32, 32);
-	GFX_init(&gfx);
-
-	start = clock();
-	for (i=0; i < 100000; i++)
-	{
-		GFX_box_draw_direct(&gfx, &box, (UINT32)rand()%800, (UINT32)rand()%600, (UINT32)rand());
-	}
-
-	end = clock();
-	printf("Fillrate %f rect/s\n", (float)i/((float)(end-start)/CLOCKS_PER_SEC));
-	sleep(2000);
-
-	GFX_frame(&gfx, GFX_FRAME_SYNC);
-	GFX_set_background(&gfx, pFlashPicture, 800, 600, 1, 1);
-	posx = posy = 0;
-	GFX_show(&gfx);
-
-//	while(1)
-	{
-		// Blitter test
-		fprintf(stderr, "Blit start\n");
-		*pVGA_src0 = (UINT32)*pFlashPicture;
-		*pVGA_dst = (UINT32)*pVGA_moffs_0;
-		*pVGA_dimx_src0 = (UINT32)4*800;
-		*pVGA_dimx_dst = (UINT32)4*800;
-		*pVGA_nx = (UINT32)800 - 1;
-		*pVGA_ny = (UINT32)600 - 1;
-		*pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-		while (*pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-		fprintf(stderr, "Blit end\n");
-		sleep(250);
-
-		// Blitter test
-		fprintf(stderr, "Blit start\n");
-		*pVGA_src0 = (UINT32)gfx.pBG;
-		*pVGA_dst = (UINT32)*pVGA_moffs_0;
-		*pVGA_dimx_src0 = (UINT32)4*800;
-		*pVGA_dimx_dst = (UINT32)4*800;
-		*pVGA_nx = (UINT32)800 - 1;
-		*pVGA_ny = (UINT32)600 - 1;
-		*pVGA_ctrl |= SYS_VGA_BIT_BLIT_REQ;
-		while (*pVGA_ctrl & SYS_VGA_BIT_BLIT_BSY);
-
-		fprintf(stderr, "Blit end\n");
-		sleep(1000);
-	}
-
-
-	interrupt_enable(7);
-	interrupt_enable(3);
-	*pTim_ctrl |= 3;
-	*pUART_stat |= (1 << 6);
-
-	cnt = 0;
-	while (1)
-	{
-		for (i=0; i < 100000; i++)
-		{
-			interrupt_disable(7);
-		}
-		for (i=0; i < 100000; i++)
-		{
-			interrupt_enable(7);
-		}
-
-		*pReg = cnt & 0x3FFFFFFF;
-
-		printf("-------------------------------------------\n");
-		printf("-- LoadStore ------------------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test10_LoadStore();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- AddSub ---------------------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test11_AddSub();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- MulDiv ---------------------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test12_MulDiv();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- Cop0 LWZ0 and SWC0 ---------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test13_COP0_Load_Store();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- D-Cache invalidate ---------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test14_DCACHE_invalidate();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- PI calc --------------------------------\n");
-		printf("-------------------------------------------\n");
-		result = Test15_pi_calc();
-		if (IS_ERROR(result))
-			break;
-		printf("passed\n\n");
-
-		printf("-------------------------------------------\n");
-		printf("-- Paranoia -------------------------------\n");
-		printf("-------------------------------------------\n");
-		paranoia(1, NULL);
-		printf("passed\n\n");
-
-//		printf("-------------------------------------------\n");
-//		printf("-- Mem Test -------------------------------\n");
-//		printf("-------------------------------------------\n");
-//		result = Test16_MemTest();
-//		if (IS_ERROR(result))
-//			break;
-//		printf("passed\n\n");
-
-		printf("Iteration %d: Passed\n", cnt);
-		curr_date = time(NULL);
-		pDate = gmtime(&curr_date);
-		puts(asctime(pDate));
-		cnt++;
-		*pTim0_cmp = 0x4000 + (UINT32)(rand() & 0x00FFFFFF);
-		*pTim_ctrl |= 1;
-
-//		printf("V=%.17e\n", pow((double)cnt-1, (double)cnt));
-	}
-	*pReg = 0x40000000 | cnt;
-	fprintf(stderr, "Failed with error %8.8X\n", result);
-
-	return 1;
-
-}
-
diff --git a/lib/CPUs/MIPS/bsp/examples/testlibusb.c b/lib/CPUs/MIPS/bsp/examples/testlibusb.c
deleted file mode 100644
index 5b48601..0000000
--- a/lib/CPUs/MIPS/bsp/examples/testlibusb.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* testlibusb.c */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/times.h>
-#include <sys/time.h>
-#include <usb.h>
-#include "tiffio.h"
-
-
-#define BUFLEN		(256*1024)
-#define FLASHSIZE	(2*1024*1024)
-int main(int argc, char *argv[])
-{
-	char *pBuf;
-	int ret, i, xfer_cnt, filesize, size;
-	char string[256];
-	double start, end;
-	struct timeval t;
-	FILE *pFile;
-	TIFF *pTif;
-	ttag_t config, photometric;
-	uint16 nSamples, nBits;
-	uint32 width, height;
-	uint32* raster;
-
-	typedef struct _scmd_t
-	{
-		unsigned sync;
-		unsigned code;
-		unsigned len;
-	} cmd_t;
-
-	cmd_t cmd_read = {0xC24755AA, 2, BUFLEN};
-	cmd_t cmd_write = {0xC24755AA, 1, BUFLEN};
-	cmd_t cmd_flash_read = {0xC24755AA, 3, FLASHSIZE};
-	cmd_t cmd_flash_write = {0xC24755AA, 4, FLASHSIZE};
-
-	libusb_context *pCtx;
-   	libusb_device_handle *handle;
-	size_t cnt;
-
-	ret = libusb_init(&pCtx);
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-
-	libusb_set_debug(pCtx, 3);
-
-	handle = libusb_open_device_with_vid_pid (pCtx, 0x04B4, 0x7200);
-	if (!handle)
-	{
-		printf("Error on opening device\n");
-		return 1;
-	}
-
-	pBuf = (char*)malloc(BUFLEN);
-	memset(pBuf, 0, BUFLEN);
-
-	// ------------------------------------------------------
-	printf("Send command\n");
-	// ------------------------------------------------------
-	ret = libusb_bulk_transfer (handle, 0x01, (char*)&cmd_write, sizeof(cmd_t), &xfer_cnt, 5000);
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-	gettimeofday(&t, NULL);
-	start = t.tv_sec + 1E-6*t.tv_usec;
-	ret = libusb_bulk_transfer(handle, 0x01, (char*)pBuf, cmd_write.len, &xfer_cnt, 5000);
-	size = xfer_cnt;
-	gettimeofday(&t, NULL);
-	end = t.tv_sec + 1E-6*t.tv_usec;
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-	printf("Sent %d bytes\n", size);
-	printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start)));
-
-	// ------------------------------------------------------
-	printf("Read command\n");
-	// ------------------------------------------------------
-	ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_read, sizeof(cmd_t), &xfer_cnt, 5000);
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-	gettimeofday(&t, NULL);
-	start = t.tv_sec + 1E-6*t.tv_usec;
-	ret = libusb_bulk_transfer(handle, 0x82, (char*)pBuf, cmd_read.len, &xfer_cnt, 5000);
-	size = xfer_cnt;
-	gettimeofday(&t, NULL);
-	end = t.tv_sec + 1E-6*t.tv_usec;
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-	printf("Received %d bytes\n", size);
-	printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start)));
-	free(pBuf);
-
-	// ------------------------------------------------------
-	printf("Read Flash\n");
-	// ------------------------------------------------------
-	pBuf = (char*)malloc(FLASHSIZE);
-	memset(pBuf, 0, FLASHSIZE);
-	ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_flash_read, sizeof(cmd_t), &xfer_cnt, 5000);
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-
-	gettimeofday(&t, NULL);
-	start = t.tv_sec + 1E-6*t.tv_usec;
-	ret = libusb_bulk_transfer(handle, 0x82, (char*)pBuf, cmd_flash_read.len, &xfer_cnt, 500000);
-	size = xfer_cnt;
-	gettimeofday(&t, NULL);
-	end = t.tv_sec + 1E-6*t.tv_usec;
-	if (ret != LIBUSB_SUCCESS)
-	{
-		printf("Error %08X\n", ret);
-		return 1;
-	}
-	printf("Received %d bytes\n", size);
-	printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start)));
-
-	pFile = fopen("./flash.bin", "wb");
-	fwrite(pBuf, 1, size, pFile);
-	fclose(pFile);
-	free(pBuf);
-
-	if (argc > 1)
-	{
-		// ------------------------------------------------------
-		printf("Write Flash (File = %s)\n", argv[1]);
-		// ------------------------------------------------------
-		pTif = TIFFOpen(argv[1],"r");
-		if (!pTif)
-		{
-			printf("Unable to open TIFF-file!\n");
-			return 1;
-		}
-		ret = TIFFGetField(pTif, TIFFTAG_IMAGEWIDTH, &width);
-		ret = TIFFGetField(pTif, TIFFTAG_IMAGELENGTH, &height);
-
-		printf("TIFFTAG_IMAGEWIDTH      = %d\n", width);
-		printf("TIFFTAG_IMAGELENGTH     = %d\n", height);
-
-		filesize = width * height * sizeof (uint32);
-
-		raster = (uint32*) _TIFFmalloc(filesize);
-		if (raster != NULL)
-		{
-			ret = TIFFReadRGBAImageOriented(pTif, width, height, raster, ORIENTATION_TOPLEFT, 0);
-			if (!ret)
-			{
-				printf("Unable to reading TIFF-file!\n");
-				return 1;
-			}
-		}
-		TIFFClose(pTif);
-
-		printf ("File size = %d\n", filesize);
-		if (filesize > FLASHSIZE)
-		{
-			printf("Cannot write flash: image to large!\n");
-			return 1;
-		}
-
-		cmd_flash_write.len = filesize;
-		ret = libusb_bulk_transfer(handle, 0x01, (char*)&cmd_flash_write, sizeof(cmd_t), &xfer_cnt, 5000);
-		if (ret != LIBUSB_SUCCESS)
-		{
-			printf("Error %08X\n", ret);
-			return 1;
-		}
-
-		gettimeofday(&t, NULL);
-		start = t.tv_sec + 1E-6*t.tv_usec;
-		size = 0;
-		ret = libusb_bulk_transfer(handle, 0x01, (char*)raster, filesize, &xfer_cnt, 500000);
-		if (ret != LIBUSB_SUCCESS)
-		{
-			printf("Error %08X\n", ret);
-			return 1;
-		}
-		size += xfer_cnt;
-		gettimeofday(&t, NULL);
-		end = t.tv_sec + 1E-6*t.tv_usec;
-		printf("Sent %d bytes\n", size);
-		printf("Data rate: %.2f kbyte/s\n", (double)size/(1024*(end-start)));
-
-		_TIFFfree(raster);
-
-	}
-
-	libusb_close(handle);
-	libusb_exit(pCtx);
-	return 0;
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/ucb.c b/lib/CPUs/MIPS/bsp/examples/ucb.c
deleted file mode 100644
index d3b9a82..0000000
--- a/lib/CPUs/MIPS/bsp/examples/ucb.c
+++ /dev/null
@@ -1,44 +0,0 @@
-#include "libsys.h"
-
-int uncached_cachemiss_bug(UINT32* pMem)
-{
-	UINT32 result;
-
-	pMem[0] = 0x12345678;
-	pMem[1] = 0xFFFFFFFF;
-
-	DCACHE_invalidate_all();
-
-	__asm__
-	(
-		"lui    $s0, 0xA000\n"
-		"lw     $a0, 32($s0)\n"
-		"or		$s1, $a0, $0\n"
-		"or		$a2, $0, $0\n"
-		"addiu	$a2, 1\n"
-		"sw     $a2, 32($s0)\n"
-//		"lw     $a1, 0(%[pMem])\n"
-		"lw     $a0, 32($s0)\n"
-		"lw     $a2, 4(%[pMem])\n"
-		"lw     $a1, 0(%[pMem])\n"
-		"nop\n"
-		"sw     $s1, 8($s0)\n"
-		"or		%[val], $a0, $0\n"
-		: [val] "=r" (result)
-		: [pMem] "r" (pMem)
-		: "a0", "a1", "a2", "s0", "s1"
-	);
-	return result;
-}
-
-int main()
-{
-	UINT32 volatile *pLed = (UINT32*)SYS_LED_PORT;
-	int buf[256], res;
-
-	res = uncached_cachemiss_bug(buf);
-	*pLed = res;
-
-	return res;
-
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/whet.c b/lib/CPUs/MIPS/bsp/examples/whet.c
deleted file mode 100644
index d939910..0000000
--- a/lib/CPUs/MIPS/bsp/examples/whet.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * @(#)whet.c	1.1
- */
-
-/*
- *      Whetstone benchmark in C.  This program is a translation of the
- *	original Algol version in "A Synthetic Benchmark" by H.J. Curnow
- *      and B.A. Wichman in Computer Journal, Vol  19 #1, February 1976.
- *
- *	Used to test compiler optimization and floating point performance.
- */
-
-/*
- * Compile with -DMEASURE_TIME for time measurement.
- *
- * Compile with -DPOUT to print intermediate results.
- *	Running this benchmark without printing the intermediate results is
- *	contrary to the authors' intentions! But using serial I/O can draw back
- *	the performance extremely when low baud rate communication is used.
- */
-#define MEASURE_TIME 1
-//#define POUT 1
-
-#define ITERATIONS	10 /* 10 Million Whetstone instructions */
-
-#include <math.h>
-#include <stdio.h>
-
-#ifdef MEASURE_TIME
-#include <time.h>
-unsigned long Begin_Time,End_Time,Total_Time;
-double whetstones;
-#endif
-
-#define Pout(n, j, k, x1, x2, x3, x4) pout(n, j, k, x1, x2, x3, x4);
-
-double		xx1, xx2, xx3, xx4, x, y, z, t, t1, t2;
-double 		e1[4];
-unsigned int	i, j, k, l, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11;
-
-main()
-{
-	printf("\nWhetstone Benchmark\n\n");
-
-	printf( "%d iterations\n", ITERATIONS );
-
-#ifdef MEASURE_TIME
-	Begin_Time = clock();
-#endif
-
-	/* initialize constants */
-
-	t   =   0.499975;
-	t1  =   0.50025;
-	t2  =   2.0;
-
-	/* set values of module weights */
-
-	n1  =   0 * ITERATIONS;
-	n2  =  12 * ITERATIONS;
-	n3  =  14 * ITERATIONS;
-	n4  = 345 * ITERATIONS;
-	n6  = 210 * ITERATIONS;
-	n7  =  32 * ITERATIONS;
-	n8  = 899 * ITERATIONS;
-	n9  = 616 * ITERATIONS;
-	n10 =   0 * ITERATIONS;
-	n11 =  93 * ITERATIONS;
-
-/* MODULE 1:  simple identifiers */
-
-	xx1 =  1.0;
-	xx2 = xx3 = xx4 = -1.0;
-
-	for(i = 1; i <= n1; i += 1) {
-		xx1 = ( xx1 + xx2 + xx3 - xx4 ) * t;
-		xx2 = ( xx1 + xx2 - xx3 + xx4 ) * t;
-		xx3 = ( xx1 - xx2 + xx3 + xx4 ) * t;
-		xx4 = (-xx1 + xx2 + xx3 + xx4 ) * t;
-	}
-#ifdef POUT
-	Pout(n1, n1, n1, xx1, xx2, xx3, xx4);
-#endif
-
-
-/* MODULE 2:  array elements */
-
-	e1[0] =  1.0;
-	e1[1] = e1[2] = e1[3] = -1.0;
-
-	for (i = 1; i <= n2; i +=1) {
-		e1[0] = ( e1[0] + e1[1] + e1[2] - e1[3] ) * t;
-		e1[1] = ( e1[0] + e1[1] - e1[2] + e1[3] ) * t;
-		e1[2] = ( e1[0] - e1[1] + e1[2] + e1[3] ) * t;
-		e1[3] = (-e1[0] + e1[1] + e1[2] + e1[3] ) * t;
-	}
-#ifdef POUT
-	Pout(n2, n3, n2, e1[0], e1[1], e1[2], e1[3]);
-#endif
-
-/* MODULE 3:  array as parameter */
-
-	for (i = 1; i <= n3; i += 1)
-		pa(e1);
-#ifdef POUT
-	Pout(n3, n2, n2, e1[0], e1[1], e1[2], e1[3]);
-#endif
-
-/* MODULE 4:  conditional jumps */
-
-	j = 1;
-	for (i = 1; i <= n4; i += 1) {
-		if (j == 1)
-			j = 2;
-		else
-			j = 3;
-
-		if (j > 2)
-			j = 0;
-		else
-			j = 1;
-
-		if (j < 1 )
-			j = 1;
-		else
-			j = 0;
-	}
-#ifdef POUT
-	Pout(n4, j, j, xx1, xx2, xx3, xx4);
-#endif
-
-/* MODULE 5:  omitted */
-
-/* MODULE 6:  integer arithmetic */
-
-	j = 1;
-	k = 2;
-	l = 3;
-
-	for (i = 1; i <= n6; i += 1) {
-		j = j * (k - j) * (l -k);
-		k = l * k - (l - j) * k;
-		l = (l - k) * (k + j);
-
-		e1[l - 2] = j + k + l;		/* C arrays are zero based */
-		e1[k - 2] = j * k * l;
-	}
-#ifdef POUT
-	Pout(n6, j, k, e1[0], e1[1], e1[2], e1[3]);
-#endif
-
-/* MODULE 7:  trig. functions */
-
-	x = y = 0.5;
-
-	for(i = 1; i <= n7; i +=1) {
-		x = t * atan(t2*sin(x)*cos(x)/(cos(x+y)+cos(x-y)-1.0));
-		y = t * atan(t2*sin(y)*cos(y)/(cos(x+y)+cos(x-y)-1.0));
-	}
-#ifdef POUT
-	Pout(n7, j, k, x, x, y, y);
-#endif
-
-/* MODULE 8:  procedure calls */
-
-	x = y = z = 1.0;
-
-	for (i = 1; i <= n8; i +=1)
-		p3(x, y, &z);
-#ifdef POUT
-	Pout(n8, j, k, x, y, z, z);
-#endif
-
-/* MODULE9:  array references */
-
-	j = 1;
-	k = 2;
-	l = 3;
-
-	e1[0] = 1.0;
-	e1[1] = 2.0;
-	e1[2] = 3.0;
-
-	for(i = 1; i <= n9; i += 1)
-		p0();
-#ifdef POUT
-	Pout(n9, j, k, e1[0], e1[1], e1[2], e1[3]);
-#endif
-
-/* MODULE10:  integer arithmetic */
-
-	j = 2;
-	k = 3;
-
-	for(i = 1; i <= n10; i +=1) {
-		j = j + k;
-		k = j + k;
-		j = k - j;
-		k = k - j - j;
-	}
-#ifdef POUT
-	Pout(n10, j, k, xx1, xx2, xx3, xx4);
-#endif
-
-/* MODULE11:  standard functions */
-
-	x = 0.75;
-	for(i = 1; i <= n11; i +=1)
-		x = sqrt( exp( log(x) / t1));
-
-#ifdef POUT
-	Pout(n11, j, k, x, x, x, x);
-#endif
-
-#ifdef MEASURE_TIME
-	End_Time = clock();
-
-	Total_Time = End_Time - Begin_Time; /* in 1/ seconds */
-
-	whetstones = (1e5 * ITERATIONS * CLOCKS_PER_SEC) / Total_Time;
-  	printf("\nWhetstone runs in %ld clock ticks (%d). %ld Kwhets/second\n",
- 		Total_Time, CLOCKS_PER_SEC, (long) whetstones / 1000 );
-#endif
-}
-
-pa(e)
-double e[4];
-{
-	register int j;
-
-	j = 0;
-     lab:
-	e[0] = (  e[0] + e[1] + e[2] - e[3] ) * t;
-	e[1] = (  e[0] + e[1] - e[2] + e[3] ) * t;
-	e[2] = (  e[0] - e[1] + e[2] + e[3] ) * t;
-	e[3] = ( -e[0] + e[1] + e[2] + e[3] ) / t2;
-	j += 1;
-	if (j < 6)
-		goto lab;
-}
-
-p3(x, y, z)
-double x, y, *z;
-{
-	x  = t * (x + y);
-	y  = t * (x + y);
-	*z = (x + y) /t2;
-}
-
-p0()
-{
-	e1[j] = e1[k];
-	e1[k] = e1[l];
-	e1[l] = e1[j];
-}
-
-#ifdef POUT
-pout(n, j, k, x1, x2, x3, x4)
-unsigned int n, j, k;
-double x1, x2, x3, x4;
-{
-	printf("%5u %5u %5u   %11.3e %11.3e %11.3e %11.3e\n",
-		n, j, k, x1, x2, x3, x4);
-}
-#endif
diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.c b/lib/CPUs/MIPS/bsp/examples/xcpt.c
deleted file mode 100644
index a6eca43..0000000
--- a/lib/CPUs/MIPS/bsp/examples/xcpt.c
+++ /dev/null
@@ -1,139 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/stat.h>
-#include <errno.h>
-#include <stdlib.h>
-#include "libsys.h"
-#include "xcpt.h"
-#include "irq.h"
-
-static fp_xcpt_t g_xcpt_handler[MAX_NUM_XCPT] = {NULL};
-
-char *_xcpt_code_str[MAX_NUM_XCPT] =
-{
-	"Int", "Mod", "TLBL", "TLBS", "AdEL", "AdES", "IBE", "DBE",
-	"Sys", "Bp", "RI", "CpU", "Ov", "Tr", "NCD/VCEI", "MC/FPE",
-	"Res(16)", "Res(17)", "Res(18)", "Res(19)", "Res(20)", "Res(21)", "Res(22)", "WATCH",
-	"Res(24)", "Res(25)", "Res(26)", "Res(27)", "Res(28)", "Res(29)", "Res(30)", "VCED"
- };
-
-void xcpt_register(int xcpt_num, fp_xcpt_t fp)
-{
-	if ((xcpt_num >= Mod) && (xcpt_num <= VCED))
-		g_xcpt_handler[xcpt_num] = fp;
-
-}
-
-int _xcpt_dispatch(struct xcptcontext * xcp)
-{
-	int xcpt_code, result, i;
-
-	xcpt_code =  ((0xFF & xcp->cr) >> 2);
-
-	result = XCPT_ERR_NOTHANDLED;
-	switch(xcpt_code)
-	{
-		case Int:
-		result = _irq_dispatch(xcp);
-		break;
-
-		default:
-		if (g_xcpt_handler[xcpt_code])
-		{
-			result = (g_xcpt_handler[xcpt_code])(xcp);
-		}
-		break;
-	}
-	return result;
-}
-
-int _xcpt_deliver(struct xcptcontext * _xcp)
-{
-
-	int exc_code;
-	volatile int *pInstr;
-
-	/* This function gets called by the low-level exception handler. */
-	if (_xcpt_dispatch(_xcp) == XCPT_ERR_NOTHANDLED)
-	{
-		sputs("\n");
-		PRINT_REG(" Status : ", _xcp->sr);
-		PRINT_REG("  Cause : ", _xcp->cr);
-		PRINT_REG("    EPC : ", _xcp->epc);
-		PRINT_REG("BadAddr : ", _xcp->baddr);
-		sputs("\n");
-		PRINT_REG("   MDLO : ", _xcp->mdlo);
-		PRINT_REG("   MDHI : ", _xcp->mdhi);
-
-		sputs("\n");
-
-		sputs("Registers:\n");
-		PRINT_REG(" 0 (ze) : ", _xcp->regs[0]);
-		PRINT_REG(" 1 (at) : ", _xcp->regs[1]);
-		PRINT_REG(" 2 (v0) : ", _xcp->regs[2]);
-		PRINT_REG(" 3 (v1) : ", _xcp->regs[3]);
-		sputs("\n");
-		PRINT_REG(" 4 (a0) : ", _xcp->regs[4]);
-		PRINT_REG(" 5 (a1) : ", _xcp->regs[5]);
-		PRINT_REG(" 6 (a2) : ", _xcp->regs[6]);
-		PRINT_REG(" 7 (a3) : ", _xcp->regs[7]);
-		sputs("\n");
-		PRINT_REG(" 8 (t0) : ", _xcp->regs[8]);
-		PRINT_REG(" 9 (t1) : ", _xcp->regs[9]);
-		PRINT_REG("10 (t2) : ", _xcp->regs[10]);
-		PRINT_REG("11 (t3) : ", _xcp->regs[11]);
-		sputs("\n");
-		PRINT_REG("12 (t4) : ", _xcp->regs[12]);
-		PRINT_REG("13 (t5) : ", _xcp->regs[13]);
-		PRINT_REG("14 (t6) : ", _xcp->regs[14]);
-		PRINT_REG("15 (t7) : ", _xcp->regs[15]);
-		sputs("\n");
-		PRINT_REG("16 (s0) : ", _xcp->regs[16]);
-		PRINT_REG("17 (s1) : ", _xcp->regs[17]);
-		PRINT_REG("18 (s2) : ", _xcp->regs[18]);
-		PRINT_REG("19 (s3) : ", _xcp->regs[19]);
-		sputs("\n");
-		PRINT_REG("20 (s4) : ", _xcp->regs[20]);
-		PRINT_REG("21 (s5) : ", _xcp->regs[21]);
-		PRINT_REG("22 (s6) : ", _xcp->regs[22]);
-		PRINT_REG("23 (s7) : ", _xcp->regs[23]);
-		sputs("\n");
-		PRINT_REG("24 (t8) : ", _xcp->regs[24]);
-		PRINT_REG("25 (t9) : ", _xcp->regs[25]);
-		PRINT_REG("26 (k0) : ", _xcp->regs[26]);
-		PRINT_REG("27 (k1) : ", _xcp->regs[27]);
-		sputs("\n");
-		PRINT_REG("28 (gp) : ", _xcp->regs[28]);
-		PRINT_REG("29 (sp) : ", _xcp->regs[29]);
-		PRINT_REG("30 (fp) : ", _xcp->regs[30]);
-		PRINT_REG("31 (ra) : ", _xcp->regs[31]);
-		sputs("\n");
-		sputs("\n");
-
-		exc_code = (_xcp->cr >> 2) & 0x1F;
-
-		sputs("Unhandled exception <");
-		sputs(_xcpt_code_str[exc_code]);
-		sputs("> at PC : ");
-
-		if (_xcp->cr & 0x80000000)
-		{
-			pInstr = (int*)(_xcp->epc + 4);
-		}
-		else
-		{
-			pInstr = (int*)(_xcp->epc);
-		}
-		print_word((int)pInstr);
-		sputs("\n");
-
-		sputs("Instruction at exception address : ");
-		print_word(*pInstr);
-		sputs("\n");
-
-		sputs("Terminate.\n");
-		_exit(exc_code);
-	}
-
-	return 0;
-}
diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.h b/lib/CPUs/MIPS/bsp/examples/xcpt.h
deleted file mode 100644
index 7958912..0000000
--- a/lib/CPUs/MIPS/bsp/examples/xcpt.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef XCPT_H
-#define XCPT_H
-
-#define MAX_NUM_XCPT			32
-#define	XCPT_ERR_NOTHANDLED		0x80000000
-
-typedef enum
-{
-	Int = 0, Mod = 1, TLBL = 2, TLBS = 3, AdEL = 4, AdES = 5,
-	IBE = 6, DBE = 7, Syscall = 8, Bp = 9, RI = 10, CpU = 11,
-	Ov = 12, TRAP = 13, VCEI = 14, FPE = 15, C2E = 16, Watch = 23, VCED = 31
-
-} EXCEPTION_CODE;
-
-typedef unsigned int reg_t;
-
-typedef struct xcptcontext
-{
-	/* This is the exception context frame that is passed to the exception
-	handlers. It gets filled in by the low-level exception handler in
-	"machine.S". An assembler version of this structure can be found at the
-	bottom of "machine.H".*/
-	reg_t sr;					/* Status Register */
-	reg_t cr;					/* Cause Register */
-	reg_t epc;					/* PC at time of exception. */
-	reg_t baddr;
-	reg_t regs[32];				/* Copy of all general purpose registers */
-	reg_t mdlo;					/* HI/LO registers (used for memory management) */
-	reg_t mdhi;
-	reg_t count;				/* Timer registers */
-	reg_t compare;
-	struct xcptcontext * prev;	/* To link exceptions. (unused for now) */
-	unsigned xclass;			/* Priority class of this exception. (unused for now). */
-
-} EXCEPTION_CONTEXT;
-
-typedef int (*fp_xcpt_t)(struct xcptcontext * xcp);
-
-#define PRINT_REG(tag_str, reg)			\
-			sputs(tag_str);				\
-			print_word(reg);			\
-			sputs("   ");
-
-
-#define PRINT_REG_CHG(tag_str, reg, chg_tag)			\
-			sputs(tag_str);				\
-			print_word(reg);			\
-			sputs(chg_tag);				\
-			sputs("  ");
-
-
-// Public functions
-void xcpt_register(int xcpt_num, fp_xcpt_t fp);
-
-#endif // XCPT_H
diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h b/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h
deleted file mode 100644
index 5735422..0000000
--- a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef XCPT_ASM_H
-#define XCPT_ASM_H
-
-/* LEAF - declare leaf routine */
-#define	LEAF(symbol)						\
-			.globl	symbol;					\
-			.align	2;						\
-			.type	symbol, @function;		\
-			.ent	symbol, 0;				\
-symbol:		.frame	sp, 0, ra
-
-/* END - mark end of function */
-#define	END(function)						\
-			.end	function;				\
-			.size	function, .-function
-
-/* Exception stack size */
-#define	XCP_SIZE		32768
-
-/* save location for registers */
-#define	XCP_SR			0
-#define	XCP_CR			4
-#define	XCP_EPC			8
-#define	XCP_BADDR		12
-#define	XCP_ZERO		16
-#define	XCP_AT			20
-#define	XCP_V0			24
-#define	XCP_V1			28
-#define	XCP_A0			32
-#define	XCP_A1			36
-#define	XCP_A2			40
-#define	XCP_A3			44
-#define	XCP_T0			48
-#define	XCP_T1			52
-#define	XCP_T2			56
-#define	XCP_T3			60
-#define	XCP_T4			64
-#define	XCP_T5			68
-#define	XCP_T6			72
-#define	XCP_T7			76
-#define	XCP_S0			80
-#define	XCP_S1			84
-#define	XCP_S2			88
-#define	XCP_S3			92
-#define	XCP_S4			96
-#define	XCP_S5			100
-#define	XCP_S6			104
-#define	XCP_S7			108
-#define	XCP_T8			112
-#define	XCP_T9			116
-#define	XCP_JP			116
-#define	XCP_K0			120
-#define	XCP_K1			124
-#define	XCP_GP			128
-#define	XCP_SP			132
-#define	XCP_S8			136
-#define	XCP_FP			136
-#define	XCP_RA			140
-#define	XCP_MDLO		144
-#define	XCP_MDHI		148
-#define	XCP_COUNT		152
-#define	XCP_COMPARE		156
-#define	XCP_PREV		160
-#define	XCP_CLASS		164
-
-
-#endif /* XCPT_ASM_H */
diff --git a/lib/CPUs/MIPS/dist/gpl-3.0.txt b/lib/CPUs/MIPS/dist/gpl-3.0.txt
deleted file mode 100644
index 94a9ed0..0000000
--- a/lib/CPUs/MIPS/dist/gpl-3.0.txt
+++ /dev/null
@@ -1,674 +0,0 @@
-                    GNU GENERAL PUBLIC LICENSE
-                       Version 3, 29 June 2007
-
- Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-                            Preamble
-
-  The GNU General Public License is a free, copyleft license for
-software and other kinds of works.
-
-  The licenses for most software and other practical works are designed
-to take away your freedom to share and change the works.  By contrast,
-the GNU General Public License is intended to guarantee your freedom to
-share and change all versions of a program--to make sure it remains free
-software for all its users.  We, the Free Software Foundation, use the
-GNU General Public License for most of our software; it applies also to
-any other work released this way by its authors.  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-them if you wish), that you receive source code or can get it if you
-want it, that you can change the software or use pieces of it in new
-free programs, and that you know you can do these things.
-
-  To protect your rights, we need to prevent others from denying you
-these rights or asking you to surrender the rights.  Therefore, you have
-certain responsibilities if you distribute copies of the software, or if
-you modify it: responsibilities to respect the freedom of others.
-
-  For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must pass on to the recipients the same
-freedoms that you received.  You must make sure that they, too, receive
-or can get the source code.  And you must show them these terms so they
-know their rights.
-
-  Developers that use the GNU GPL protect your rights with two steps:
-(1) assert copyright on the software, and (2) offer you this License
-giving you legal permission to copy, distribute and/or modify it.
-
-  For the developers' and authors' protection, the GPL clearly explains
-that there is no warranty for this free software.  For both users' and
-authors' sake, the GPL requires that modified versions be marked as
-changed, so that their problems will not be attributed erroneously to
-authors of previous versions.
-
-  Some devices are designed to deny users access to install or run
-modified versions of the software inside them, although the manufacturer
-can do so.  This is fundamentally incompatible with the aim of
-protecting users' freedom to change the software.  The systematic
-pattern of such abuse occurs in the area of products for individuals to
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-
-    <program>  Copyright (C) <year>  <name of author>
-    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, your program's commands
-might be different; for a GUI interface, you would use an "about box".
-
-  You should also get your employer (if you work as a programmer) or school,
-if any, to sign a "copyright disclaimer" for the program, if necessary.
-For more information on this, and how to apply and follow the GNU GPL, see
-<http://www.gnu.org/licenses/>.
-
-  The GNU General Public License does not permit incorporating your program
-into proprietary programs.  If your program is a subroutine library, you
-may consider it more useful to permit linking proprietary applications with
-the library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.  But first, please read
-<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/lib/CPUs/MIPS/dist/makedist.R12 b/lib/CPUs/MIPS/dist/makedist.R12
deleted file mode 100644
index 0d74ee1..0000000
--- a/lib/CPUs/MIPS/dist/makedist.R12
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/sh
-
-USE_TAG=MIPS_R12
-PROJECT="mips_sys"
-DIST_DIR="./release/mips.r12"
-
-echo Log for $USE_TAG >$USE_TAG.log
-
-# ---------------------------------------------------------------
-# Export files tagged for this release
-# To avoid CVS-problems with renamed files: Don't tag on per file basis. 
-# => Tag upper directory then delete tag from unwanted files!!!
-
-# Release notes
-cvs export -l -d $DIST_DIR/ -r $USE_TAG VHDL/lib/CPUs/MIPS/dist >>$USE_TAG.log
-
-# VHDL files
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/misc >>$USE_TAG.log
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/uart >>$USE_TAG.log
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/FIFO/src >>$USE_TAG.log
-cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src >>$USE_TAG.log
-cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src/core >>$USE_TAG.log
-
-# Simulation files
-cvs export -l -d $DIST_DIR/sim/ -r $USE_TAG VHDL/lib/CPUs/MIPS/sim >>$USE_TAG.log
-
-# Documentation files
-cvs export -d $DIST_DIR/doc/ -r $USE_TAG VHDL/lib/CPUs/MIPS/doc >>$USE_TAG.log
-rm -f $DIST_DIR/doc/*.vsd 
-
-# Tools
-cvs export -d $DIST_DIR/tools/ -r $USE_TAG VHDL/lib/CPUs/MIPS/tools >>$USE_TAG.log
diff --git a/lib/CPUs/MIPS/dist/makedist.R13 b/lib/CPUs/MIPS/dist/makedist.R13
deleted file mode 100644
index be6da72..0000000
--- a/lib/CPUs/MIPS/dist/makedist.R13
+++ /dev/null
@@ -1,32 +0,0 @@
-#!/bin/sh
-
-USE_TAG=MIPS_R13
-PROJECT="mips_sys"
-DIST_DIR="./release/mips.r13"
-
-echo Log for $USE_TAG >$USE_TAG.log
-
-# ---------------------------------------------------------------
-# Export files tagged for this release
-# To avoid CVS-problems with renamed files: Don't tag on per file basis. 
-# => Tag upper directory then delete tag from unwanted files!!!
-
-# Release notes
-cvs export -l -d $DIST_DIR/ -r $USE_TAG VHDL/lib/CPUs/MIPS/dist >>$USE_TAG.log
-
-# VHDL files
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/misc >>$USE_TAG.log
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/uart >>$USE_TAG.log
-cvs export -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/FIFO/src >>$USE_TAG.log
-cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src >>$USE_TAG.log
-cvs export -l -d $DIST_DIR/src/ -r $USE_TAG VHDL/lib/CPUs/MIPS/src/core >>$USE_TAG.log
-
-# Simulation files
-cvs export -l -d $DIST_DIR/sim/ -r $USE_TAG VHDL/lib/CPUs/MIPS/sim >>$USE_TAG.log
-
-# Documentation files
-cvs export -d $DIST_DIR/doc/ -r $USE_TAG VHDL/lib/CPUs/MIPS/doc >>$USE_TAG.log
-rm -f $DIST_DIR/doc/*.vsd 
-
-# Tools
-cvs export -d $DIST_DIR/tools/ -r $USE_TAG VHDL/lib/CPUs/MIPS/tools >>$USE_TAG.log
diff --git a/lib/CPUs/MIPS/dist/notes.txt b/lib/CPUs/MIPS/dist/notes.txt
deleted file mode 100644
index 78f7c0f..0000000
--- a/lib/CPUs/MIPS/dist/notes.txt
+++ /dev/null
@@ -1,100 +0,0 @@
------------------------------------------------------------------
-Changes in release 13
------------------------------------------------------------------
-- mips_biu.vhd: added asynchronous BUS-FIFOs to support different clocks for CPU and BUS
-- mips_dcache.vhd: improved instant-RAW stall behavior (faster execution)
-- uart_WB.vhd: added simulate_TX generic for plain TX output in simulation log
-
------------------------------------------------------------------
-Changes in release 12
------------------------------------------------------------------
-- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked
-  using a single mips*-elf-gcc command.
-  To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/,
-  and see bsp/examples/Makefile gcc usage
-  GCC-provided crt*-functions are now called without problems.
-  In summary: The toolchain is now more compliant to the intentional use of GCC.
-- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O,
-  which is now compliant to literature. 
-- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset.
-- new bsp-example source: gunzip
-- updated drawing 'mips_jbus_timing.pdf'
-- added drawing 'memory_map.pdf' 
-- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection.
-- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register.
-  Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo()
-- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis.
-  Removed idecode_rom.vhd from project as consequence.
-- added cop0 instructions to invalidate I-cache and D-Cache
-- added copz instructions lwcz and swcz
-- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload
-- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h
-- exception handlers can now be registered to any exception type 
-- bugfix mips_pipeline/mips_cop: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
-- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
-- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
-- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU.
-- uart_wb.vhd: added interrupt enable
-- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. 
-  Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. 
-- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception. 
-  Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable.
-  Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W.
-  Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already.
-- Bootloader: Startup.S now invalidates I/D-Caches at boot.
-- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge.
-- Bugfix in mips_pipeline: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
-  Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug.  
-  Symptom: Consecutive load instructions without nops using same target register (which is legal) like
-   lw $1, 0(mem)
-   lwl $1, 1(mem)
-  or
-   lwl $1, 0(mem)
-   lwr $1, 1(mem)
-  or similar, lead to incorrect result. Now it's fixed.
-- Bugfix mips_biu: instructions uncached LW => cached LW (with cache-miss) was buggy.
-  Symptom:
-  ...
-  1.: lw     $a0, 32($s0)  # Uncached load from memory mapped I/O
-  2.: lw     $a2, 4($v0)   # Cached load and cache-miss.
-                           # $a0 receives same value as $a2.
-                           # CPU skips writing $a0 due to busy flag of D-Cache,
-                           # which is already active in the previous cycle
-  ...
-
------------------------------------------------------------------
-Changes in release 11
------------------------------------------------------------------
-- bugfix in mips_pipeline: pc_is_branch is now initialized at reset
-  (fixes CPU unrecoverable state after reset)
-- reverted "optimization" in mips_dcache, which behaved buggy during exceptions
-- new example source: test_exception
-- minor changes in libsys
-- added async_port_timing in doc
-- examples/testbench: date set now really works
-
------------------------------------------------------------------
-Changes in release 10b
------------------------------------------------------------------
-- bugfix: fixed compiler bug (missing nop after lw) in bootloader,
-  which caused exception during boot
-
------------------------------------------------------------------
-Changes in release 10a
------------------------------------------------------------------
-async_port_wb:
-- added byte enable for async_port
-
-bootloader.c
-- bugfix: fixed compiler bug (missing nop after lw)
-
-mips-core
-- bugfix: SEL_O lines are also asserted correctly during reads
-
-tools/romgen
-- TCL-Jtag now compatible with Chipscope 10.1
-
-mips_sys.c
-- use byte enable for sram and flash
-
-
diff --git a/lib/CPUs/MIPS/doc/J-MIPS.txt b/lib/CPUs/MIPS/doc/J-MIPS.txt
deleted file mode 100644
index 43448cb..0000000
--- a/lib/CPUs/MIPS/doc/J-MIPS.txt
+++ /dev/null
@@ -1,109 +0,0 @@
------------------------------------------------------------------
-J-MIPS Features
------------------------------------------------------------------
-
-- Synchrones Design
-- Portable Beschreibung in VHDL 
-- Kompatible zur GNU Toolchain (Binutils, GCC, Newlib)
-- Befehle kompatibel mit MIPS-1 ISA (z.B. MIPS R3000)
-- 5-Stufige Pipeline und Hazardvermeidung durch Forwarding
-- 64Bit Multiplier (32Bit Operanden), 12 Cycles Latenz
-- 64Bit Divider (32Bit Operanden), 36 Cycles Latenz
-- Coprocessor 0 (COP0) für Exceptionhandling
-- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line
-- Direct-mapped Data Cache mit variabler Größe, 8-words per Line
-- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen)
-- 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3)
-- Endianness umschaltbar zur Hard-reset Zeit
-- Unterschiedliche Frequenzen für CPU und BUS möglich
-
------------------------------------------------------------------
-Known Limitations
------------------------------------------------------------------
-- keine MMU
-- keine Unterstützung für Bus exceptions IBE und DBE
-- kein externes Coprocessor interface (COP1..3) für z.B. FPU
-- Befehle für Cop1..3 nicht implementiert: 
-  CFCz, CTCz, COPz, MFCz, MTCz, LWCz, SWCz
-  Benutzung dieser Befehle führt zur Exception 'RI' (Reserved Instruction)
-- nicht alle COP0 Register/Bits vorhanden.
-
------------------------------------------------------------------
-Known Bugs
------------------------------------------------------------------
-- es gibt bestimmt noch nicht entdeckte Bugs
-
------------------------------------------------------------------
-Known Optimizations
------------------------------------------------------------------
-- Area: Multiplier als technologieabhängiges Primitive instanzieren
-- Area: Auf Divider verzichten
-- Area: Auf Multiplier verzichten
-- Area vs. Speed: Bei Hazards Pipeline-stall statt Forwarding. 
-  Durch Stalling geringerer Befehlsdurchsatz dafür weniger Logik. 
-  Weniger Logik bedeutet vielleicht wieder auch größere Taktfrequenz.
- 
------------------------------------------------------------------
-Known ToDos
------------------------------------------------------------------
-- Unterstützung für Bus exceptions IBE und DBE
-- Externes COP1..3 interface, fehlende COP-Befehle implementieren
-- Optimierungen evaluieren und ggf. durchführen
-
------------------------------------------------------------------
-Synthesis results
------------------------------------------------------------------
-Virtex-4 XC4VSX35-10 
-
-Config: 16Kbyte I/D-Cache
-
-Number of Slices		2387 	15360 	15%
-Number of Slice Flip Flops 	1784 	30720 	 5%
-Number of 4 input LUTs		3962 	30720 	12%
-Number of FIFO16/RAMB16s 	18	192 	 9%
-
-Speed: 110MHz nach Synthesis
-
------------------------------------------------------------------
-Virtex-1 XCV1000-4
-
-Config: 4Kbyte I/D-Cache
-
-Number of Slices		2045 	13824 	16%
-Number of Slice Flip Flops 	1783 	27648 	 7%
-Number of 4 input LUTs		3923 	27648 	15%
-Number of FIFO16/RAMB16s 	20	32	62%
-
-Speed: 30MHz nach Synthesis
-
------------------------------------------------------------------
-Performance bei 100MHz	
-- GCC ohne Small-data section
-- MIPS Rev. 9
------------------------------------------------------------------
-I/D-Cache	Dhrystone-2.1	RipeMD-160	Whetstone	Stanford	Queens(12x12)
-1k		 32 DMIPS	 5 Mbit/s	 345 kwhets/s	47/767		2,135s
-2k		 51 DMIPS	 5 Mbit/s	 534 kwhets/s	38/561		2,134s
-4k		 72 DMIPS	 5 Mbit/s	 623 kwhets/s	36/259		2,121s
-8k		 98 DMIPS	10 Mbit/s	1149 kwhets/s	31/228		1,938s
-16k		115 DMIPS	17 Mbit/s	1234 kwhets/s	23/225		1,938s
-32k		115 DMIPS	17 Mbit/s	1285 kwhets/s	24/218		1,938s
-64k		115 DMIPS	17 Mbit/s	1285 kwhets/s	20/221		1,938s
-
------------------------------------------------------------------
-Performance bei 100MHz	
-- GCC mit Small-data section
-- MIPS Rev. 9
------------------------------------------------------------------
-I/D-Cache	Dhrystone-2.1	RipeMD-160	Whetstone	Stanford	Queens(12x12)
-16k		117 DMIPS	17 Mbit/s	1236 kwhets/s	24/230		1,811s
-
------------------------------------------------------------------
-Performance bei 100MHz	
-- GCC mit Small-data section
-- MIPS Rev. 10
------------------------------------------------------------------
-I/D-Cache	Dhrystone-2.1	RipeMD-160	Whetstone	Stanford	Queens(12x12)
-16k		120 DMIPS	17 Mbit/s	1242 kwhets/s	25/219		1,803s
-
-
diff --git a/lib/CPUs/MIPS/doc/async_port_timing.pdf b/lib/CPUs/MIPS/doc/async_port_timing.pdf
deleted file mode 100644
index 8e2a4d2..0000000
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diff --git a/lib/CPUs/MIPS/doc/memory_map.pdf b/lib/CPUs/MIPS/doc/memory_map.pdf
deleted file mode 100644
index a5f3a40..0000000
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diff --git a/lib/CPUs/MIPS/doc/memory_map.vsd b/lib/CPUs/MIPS/doc/memory_map.vsd
deleted file mode 100644
index 720cf6a..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_biu.pdf b/lib/CPUs/MIPS/doc/mips_biu.pdf
deleted file mode 100644
index 74f2564..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_drawings.vsd b/lib/CPUs/MIPS/doc/mips_drawings.vsd
deleted file mode 100644
index 4da74c8..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_jbus_timing.pdf b/lib/CPUs/MIPS/doc/mips_jbus_timing.pdf
deleted file mode 100644
index ce0b05d..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_pipeline.pdf b/lib/CPUs/MIPS/doc/mips_pipeline.pdf
deleted file mode 100644
index 71c529e..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf b/lib/CPUs/MIPS/doc/mips_pipeline_stages.pdf
deleted file mode 100644
index b05de04..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_sys.vsd b/lib/CPUs/MIPS/doc/mips_sys.vsd
deleted file mode 100644
index 6c62de1..0000000
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diff --git a/lib/CPUs/MIPS/doc/mips_sys_ml402.pdf b/lib/CPUs/MIPS/doc/mips_sys_ml402.pdf
deleted file mode 100644
index 566ddaf..0000000
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diff --git a/lib/CPUs/MIPS/doc/toolchain/howto_build.txt b/lib/CPUs/MIPS/doc/toolchain/howto_build.txt
deleted file mode 100644
index 270be3b..0000000
--- a/lib/CPUs/MIPS/doc/toolchain/howto_build.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-# ---------------------------------------------------------------
-# 1. Binutils bauen und installieren
-# ---------------------------------------------------------------
-> tar -xzf binutils-2.19.tar.gz
-> mkdir binutils-2.19_build
-> cd binutils-2.19_build
-
-> ../binutils-2.19/configure --target=mipsel-elf --prefix=/usr/local
-> make
-> make install
- 
-# ---------------------------------------------------------------
-# 2. GCC bootstrapping 
-# ---------------------------------------------------------------
-> tar -xzf gcc-4.3.2.tar.gz
-> mkdir gcc-4.3.2_build
-> cd gcc-4.3.2_build
-> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --without-headers --with-newlib --with-float=soft --disable-multilib
-> CFLAGS_FOR_TARGET="-mno-gpopt" make all-gcc
-> make info-gcc
-> make install-gcc
- 
-# ---------------------------------------------------------------
-# 3. Newlib bauen und installieren
-# ---------------------------------------------------------------
-> tar -xzf newlib-1.16.0.tar.gz
-! Bug in newlib-1.16.0/newlib/libc/machine/mips/strlen.c.
-  Newlib von Hand patchen (32-bit MIPS targets):
-    "lbu $3,0($4)\n"
-    "nop\n"           <= nop einfügen
-    "bnez $3,1b\n"
-
-> mkdir newlib-1.16.0_build
-> cd newlib-1.16.0_build
-> ../newlib-1.16.0/configure --target=mipsel-elf --prefix=/usr/local --with-float=soft --disable-multilib
-> TARGET_CFLAGS="-mno-gpopt" make all
-> make install
-
-# ---------------------------------------------------------------
-# 4. GCC bauen und installieren
-# ---------------------------------------------------------------
-> cd gcc-4.3.2_build
-> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --disable-shared --with-newlib --with-float=soft --disable-multilib
-> CFLAGS_FOR_TARGET="-mno-gpopt" make all
-> make info
-> make install
diff --git a/lib/CPUs/MIPS/doc/toolchain/make.sh b/lib/CPUs/MIPS/doc/toolchain/make.sh
deleted file mode 100644
index 1568da9..0000000
--- a/lib/CPUs/MIPS/doc/toolchain/make.sh
+++ /dev/null
@@ -1,151 +0,0 @@
-#!/bin/sh
-TARGET=mipsel-elf
-PREFIX=/usr/local
-
-SRC_BINUTILS=binutils-2.19
-SRC_GCC=gcc-4.3.3
-SRC_NEWLIB=newlib-1.16.0
-SRC_GMP=gmp-4.2.4
-SRC_MPFR=mpfr-2.4.0
-
-# ---------------------------------------------------------------
-# 1. Binutils bauen und installieren
-# ---------------------------------------------------------------
-if [ ! -e $SRC_BINUTILS.tar.bz2 ]; then
-  echo Downloading $SRC_BINUTILS
-  wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/binutils/$SRC_BINUTILS.tar.bz2 || exit 1
-else
-  echo Skipped downloading $SRC_BINUTILS
-fi  
-
-if [ ! -e ./$SRC_BINUTILS ]; then
-  echo Unpacking $SRC_BINUTILS
-  tar -xjf $SRC_BINUTILS.tar.bz2 || exit 1
-else
-  echo Skipped unpacking $SRC_BINUTILS
-fi
-
-if [ ! -e ./$SRC_BINUTILS-build ]; then
-  echo Building $SRC_BINUTILS
-  mkdir -p $SRC_BINUTILS-build
-  cd $SRC_BINUTILS-build
-  ../$SRC_BINUTILS/configure --target=$TARGET --prefix=$PREFIX || exit 1
-  make || exit 1
-  make install || exit 1
-  cd ..
-else
-  echo $SRC_BINUTILS is already built.
-fi
-
-# ---------------------------------------------------------------
-# 2. GMP bauen und installieren
-# ---------------------------------------------------------------
-if [ ! -e $SRC_GMP.tar.bz2 ]; then
-  echo Downloading $SRC_GMP
-  wget http://ftp.sunet.se/pub/gnu/gmp/$SRC_GMP.tar.bz2 || exit 1
-else
-  echo Skipped downloading $SRC_GMP
-fi  
-
-if [ ! -e ./$SRC_GMP ]; then
-  echo Unpacking $SRC_GMP
-  tar -xjf $SRC_GMP.tar.bz2 || exit 1
-else
-  echo Skipped unpacking $SRC_GMP
-fi
-
-if [ ! -e ./$SRC_GMP-build ]; then
-  echo Building $SRC_GMP
-  mkdir -p $SRC_GMP-build
-  cd $SRC_GMP-build
-  ../$SRC_GMP/configure --prefix=$PREFIX || exit 1
-  make || exit 1
-  make check || exit 1
-  make install || exit 1
-  cd ..
-else
-  echo $SRC_GMP is already built.
-fi
-
-# ---------------------------------------------------------------
-# 3. MPFR bauen und installieren
-# ---------------------------------------------------------------
-if [ ! -e $SRC_MPFR.tar.bz2 ]; then
-  echo Downloading $SRC_MPFR
-  wget http://www.mpfr.org/mpfr-current/$SRC_MPFR.tar.bz2 || exit 1
-else
-  echo Skipped downloading $SRC_MPFR
-fi  
-
-if [ ! -e ./$SRC_MPFR ]; then
-  echo Unpacking $SRC_MPFR
-  tar -xjf $SRC_MPFR.tar.bz2 || exit 1
-else
-  echo Skipped unpacking $SRC_MPFR
-fi
-
-if [ ! -e ./$SRC_MPFR-build ]; then
-  echo Building $SRC_MPFR
-  mkdir -p $SRC_MPFR-build
-  cd $SRC_MPFR-build
-  ../$SRC_MPFR/configure --prefix=$PREFIX || exit 1
-  make || exit 1
-  make check || exit 1
-  make install || exit 1
-  cd ..
-else
-  echo $SRC_MPFR is already built.
-fi
-
-# ---------------------------------------------------------------
-# 4. GCC & newlib bauen und installieren
-# ---------------------------------------------------------------
-if [ ! -e $SRC_NEWLIB.tar.gz ]; then
-  echo Downloading $SRC_NEWLIB
-  wget ftp://sources.redhat.com/pub/newlib/$SRC_NEWLIB.tar.gz || exit 1
-else
-  echo Skipped downloading $SRC_NEWLIB
-fi  
-
-if [ ! -e ./$SRC_NEWLIB ]; then
-  echo Unpacking $SRC_NEWLIB
-  tar -xzf $SRC_NEWLIB.tar.gz || exit 1
-  if [ -e  $SRC_NEWLIB-jens.patch ]; then
-    echo Patching $SRC_NEWLIB
-    patch -p0 < $SRC_NEWLIB-jens.patch || exit 1
-  fi	
-else
-  echo Skipped unpacking $SRC_NEWLIB
-fi
-
-if [ ! -e $SRC_GCC.tar.bz2 ]; then
-  echo Downloading $SRC_GCC
-  wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/gcc/$SRC_GCC/$SRC_GCC.tar.bz2 || exit 1
-else
-  echo Skipped downloading $SRC_GCC
-fi  
-
-if [ ! -e ./$SRC_GCC ]; then
-  echo Unpacking $SRC_GCC
-  tar -xjf $SRC_GCC.tar.bz2 || exit 1
-  cd ./$SRC_GCC
-  ln -sf ../$SRC_NEWLIB/newlib/ .
-  cd ..
-else
-  echo Skipped unpacking $SRC_GCC
-fi
-
-if [ ! -e ./$SRC_GCC-build ]; then
-  echo Building $SRC_GCC
-  mkdir -p $SRC_GCC-build
-  cd $SRC_GCC-build
-  ../$SRC_GCC/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++" || exit 1
-  LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PREFIX/lib make all || exit 1
-  make info || exit 1
-  make install || exit 1
-  cd ..
-  echo $PREFIX/lib >/etc/ld.so.conf.d/local.conf
-  ldconfig
-else
-  echo $SRC_GCC is already built.
-fi
diff --git a/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch b/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch
deleted file mode 100644
index bf61a14..0000000
--- a/lib/CPUs/MIPS/doc/toolchain/newlib-1.16.0-jens.patch
+++ /dev/null
@@ -1,11 +0,0 @@
-diff -Naur newlib-1.16.0/newlib/libc/machine/mips/strlen.c newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c
---- newlib-1.16.0/newlib/libc/machine/mips/strlen.c	2002-03-14 03:41:43.000000000 +0100
-+++ newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c	2009-02-14 15:52:58.000000000 +0100
-@@ -60,6 +60,7 @@
- 	"	addiu	$2,$4,1\n"
- 	"\n"
- 	"1:	lbu	$3,0($4)\n"
-+	"	nop\n"
- 	"	bnez	$3,1b\n"
- 	"	addiu	$4,$4,1\n"
- 	"\n"
diff --git a/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch b/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch
deleted file mode 100644
index bc28abc..0000000
--- a/lib/CPUs/MIPS/doc/toolchain/newlib-1.17.0-jens.patch
+++ /dev/null
@@ -1,11 +0,0 @@
-diff -Naur newlib-1.17.0/newlib/libc/machine/mips/strlen.c newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c
---- newlib-1.17.0/newlib/libc/machine/mips/strlen.c	2002-03-14 03:41:43.000000000 +0100
-+++ newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c	2009-02-14 15:45:19.000000000 +0100
-@@ -60,6 +60,7 @@
- 	"	addiu	$2,$4,1\n"
- 	"\n"
- 	"1:	lbu	$3,0($4)\n"
-+	"	nop\n"
- 	"	bnez	$3,1b\n"
- 	"	addiu	$4,$4,1\n"
- 	"\n"
diff --git a/lib/CPUs/MIPS/sim/ModelSim SE .lnk b/lib/CPUs/MIPS/sim/ModelSim SE .lnk
deleted file mode 100644
index d30cd7a..0000000
Binary files a/lib/CPUs/MIPS/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/CPUs/MIPS/sim/asm/exception.s b/lib/CPUs/MIPS/sim/asm/exception.s
deleted file mode 100644
index 20c0aaa..0000000
--- a/lib/CPUs/MIPS/sim/asm/exception.s
+++ /dev/null
@@ -1,249 +0,0 @@
-		.file	"exception.s"
-
-		.section .kdata,"a"
-		.align	2
-_k_stack:	.space	256, 0
-_k_msg1:	.asciiz	"Exception at "
-_k_msg2:	.asciiz	"EPC      : "
-_k_msg3:	.asciiz	"Cause    : "
-_k_msg4:	.asciiz	"Status   : "
-_k_msg5:	.asciiz	"BadVAddr : "
-_k_crlf:	.asciiz	"\r\n"
-_k_hextbl:	.ascii "0123456789ABCDEF"
-
-		.section .ktext,"ax"
-		.align	2
-
-		.equ	LED_STAT, 0x80000000
-		.equ	UART_DATA, 0x80000004
-		.equ	UART_STAT, 0x80000008
-	
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		sw		$sp, _k_stack
-		la		$sp, _k_stack
-		kpush	$8
-		kpush	$9
-		kpush	$10
-		kpush	$11
-		kpush	$12
-		kpush	$31
-
-		.set	noreorder
-		# Get BadVAddr
-		mfc0	$10, $8
-		kpush	$10
-		# Get Status
-		mfc0	$10, $12
-		kpush	$10
-		# Get Cause
-		mfc0	$10, $13
-		kpush	$10
-		srl		$10, 29
-		andi	$11, $10, 4
-		# Get EPC
-		mfc0	$10, $14
-		kpush	$10
-
-		# Get real EPC
-		addu	$10, $11
-		kpush	$10
-		
-		# Print CRLF
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-
-		# Print real EPC
-		la		$11, _k_msg1
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print EPC
-		la		$11, _k_msg2
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Cause
-		la		$11, _k_msg3
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Status
-		la		$11, _k_msg4
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print BadVAddr
-		la		$11, _k_msg5
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		li 		$27, LED_STAT
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		sw 		$26, 0($27)
-
-		# wait for exception = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 1
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		kpop	$31
-		kpop	$12
-		kpop	$11
-		kpop	$10
-		kpop	$9
-		kpop	$8
-		lw		$sp, _k_stack
-
-		# Return
-		jr	$26
-		rfe
-		.set	reorder
-
-# word = $10
-_kprint_word:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 16
-		jal		_kprint_halfword
-		nop
-		kpop	$10
-		jal		_kprint_halfword
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# halfword = $10
-_kprint_halfword:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 8
-		jal		_kprint_byte
-		nop
-		kpop	$10
-		jal		_kprint_byte
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# byte = $10
-_kprint_byte:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 4
-		jal		_kprint_nibble
-		nop
-		kpop	$10
-		jal		_kprint_nibble
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-_kprint_nibble:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		la		$12, _k_hextbl
-		andi	$10, 0xF
-		addu	$12, $10
-		lbu		$10, 0($12)
-		jal		_ksaus
-		nop
-		kpop	$10
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# char = $10
-_ksaus:
-		.set	noreorder
-		li		$8, UART_STAT
-		lbu		$8, 0($8)
-		li		$9, UART_DATA
-		andi	$8, 0x02
-		bnez	$8, _ksaus
-		nop
-		j		$31
-		sb		$10, 0($9)
-		.set	reorder
-	
-_kputs:
-		.set	noreorder
-		kpush	$11
-		kpush	$31
-$kpl:	lbu		$10, 0($11)
-		addiu	$11, 1
-		blez	$10, $kpex
-		nop
-		jal		_ksaus
-		nop
-		j		$kpl
-		nop
-$kpex:	kpop	$31
-		kpop	$11
-		jr		$31
-		nop		
-		.set	reorder
-	
diff --git a/lib/CPUs/MIPS/sim/asm/faculty.c b/lib/CPUs/MIPS/sim/asm/faculty.c
deleted file mode 100644
index 5419715..0000000
--- a/lib/CPUs/MIPS/sim/asm/faculty.c
+++ /dev/null
@@ -1,96 +0,0 @@
-//#include <stdio.h>
-//#include <stdlib.h>
-//#include <string.h>
-
-int faculty(int f0, int *pDst, int len)
-{
-	int i=0;
-
-	pDst[i++] = f0;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-1] * i;
-	}
-
-	return i;
-}
-
-#define	NUM_ELEMENTS	20
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 8; i++)
-
-	{
-		nibble = (char)((word >> 28) & 0xF);
-		word <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-
-}
-
-int main (void)
-{
-	int buf[NUM_ELEMENTS], result, i, j, cnt;
-	volatile int *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	char msg[] = "MIPS R3000 CPU\r\nReady\r\n";
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	cnt = 0;
-	memset(buf, 0, sizeof(buf));
-
-	sputs(msg);
-
-	buf[NUM_ELEMENTS-1] = 1;
-	while (1)
-	{
-		result = faculty(buf[NUM_ELEMENTS-1], buf, NUM_ELEMENTS);
-
-		for (i=0; i < NUM_ELEMENTS; i++)
-		{
-			print_word(buf[i]);
-			saus(13);
-			saus(10);
-		}
-		cnt++;
-
-		while(1);
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/faculty.s b/lib/CPUs/MIPS/sim/asm/faculty.s
deleted file mode 100644
index 9bbdd09..0000000
--- a/lib/CPUs/MIPS/sim/asm/faculty.s
+++ /dev/null
@@ -1,255 +0,0 @@
-	.file	1 "faculty.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	faculty
-	.ent	faculty
-faculty:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$7,1			# 0x1
-	slt	$2,$7,$6
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$4,0($5)
-	.set	macro
-	.set	reorder
-
-	addiu	$5,$5,4
-$L5:
-	lw	$2,-4($5)
-	mult	$2,$7
-	addiu	$7,$7,1
-	slt	$3,$7,$6
-	mflo	$2
-	sw	$2,0($5)
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L5
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$7
-	.set	macro
-	.set	reorder
-
-	.end	faculty
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L10:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L10
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L18
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L19:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L18:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L19
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,7			# 0x7
-	srl	$3,$16,28
-$L29:
-	sltu	$2,$3,10
-	addiu	$17,$17,-1
-	sll	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L25
-	addiu	$4,$3,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$3,55
-$L25:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L29
-	srl	$3,$16,28
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Ready\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,136,$31		# vars= 104, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	lw	$3,$LC0+4
-	addiu	$sp,$sp,-136
-	sw	$2,96($sp)
-	sw	$3,100($sp)
-	lw	$2,$LC0+8
-	lw	$3,$LC0+12
-	sw	$2,104($sp)
-	sw	$3,108($sp)
-	lw	$2,$LC0+16
-	lw	$3,$LC0+20
-	li	$7,-2147483648			# 0xffffffff80000000
-	ori	$8,$7,0x9
-	sw	$2,112($sp)
-	sw	$3,116($sp)
-	ori	$7,$7,0x8
-	li	$3,85
-	sw	$16,120($sp)
-	li	$2,53
-	addiu	$16,$sp,16
-	sb	$2,0($8)
-	move	$4,$16
-	sb	$3,0($7)
-	move	$5,$0
-	li	$6,80			# 0x50
-	sw	$31,128($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	sw	$17,124($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,96
-	.set	macro
-	.set	reorder
-
-	li	$3,1			# 0x1
-	sw	$3,92($sp)
-	li	$4,1			# 0x1
-	move	$5,$16
-	li	$6,20			# 0x14
-	.set	noreorder
-	.set	nomacro
-	jal	faculty
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-	li	$16,19			# 0x13
-$L36:
-	lw	$4,0($17)
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	addiu	$16,$16,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,13			# 0xd
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,10			# 0xa
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$16,$L36
-	addiu	$17,$17,4
-	.set	macro
-	.set	reorder
-
-$L37:
-	j	$L37
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.c b/lib/CPUs/MIPS/sim/asm/fibonacci.c
deleted file mode 100644
index b707efb..0000000
--- a/lib/CPUs/MIPS/sim/asm/fibonacci.c
+++ /dev/null
@@ -1,179 +0,0 @@
-//#include <stdio.h>
-#include <stdlib.h>
-//#include <string.h>
-
-int fibonacci(int f0, int f1, int *pDst, int len)
-{
-	int i;
-
-	i = 0;
-
-	pDst[i++] = f0;
-	pDst[i++] = f1;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-2] + pDst[i-1];
-	}
-
-	return i;
-}
-
-#define	NUM_ELEMENTS	100
-#define	NUM_RUNS		1000
-
-typedef struct _sstat_t
-{
-	char v1;
-	int v2;
-	char v3;
-	short v4;
-
-} __attribute__ ((__packed__)) stat_t;
-
-void test_func(stat_t *pObj)
-{
-	int *pReg = (int*)0x80000000;
-
-
-	*pReg = (int)pObj->v4;
-
-}
-
-char sein(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 8; i++)
-
-	{
-		nibble = (char)((word >> 28) & 0xF);
-		word <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-
-}
-
-int main (void)
-{
-	int buf[NUM_ELEMENTS], result, i, j, diff, num_right_elements, num_right_runs;
-	int fill, cnt, *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	int testbuf[2] = {0x12345678, 0x5555aaaa};
-	stat_t stat = {0x0D, 0xFF5A3FC1, 0x1E, 0x0F07};
-	char msg[] = "MIPS R3000 CPU\r\nReady\r\n";
-	char msg2[32];
-	char baud;
-	char *pPtr;
-	long long product;
-	int op1, op2;
-
-	div_t div_res;
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	cnt = 0;
-	fill = 0xAAAAAAAA;
-	memset(msg2, 0, sizeof(msg2));
-	memcpy(msg2, msg, strlen(msg));
-
-	srand(0x19701031);
-	for (i=0; i < sizeof(msg2)-1; i++)
-		msg2[i] = sein();
-
-	sputs(msg2);
-	test_func(&stat);
-
-//	div_res = div(testbuf[1], testbuf[0]);
-	while (1)
-	{
-		num_right_runs = 0;
-		for (i=0; i < NUM_RUNS; i++)
-		{
-			for (j=0;  j < NUM_ELEMENTS; j++)
-				buf[j] = fill;
-
-			fill = ((fill ^ i) - 1) << 1;
-			num_right_elements = 2;
-			result = fibonacci(i, i+1, buf, NUM_ELEMENTS);
-			for (j=2;  j < NUM_ELEMENTS; j++)
-			{
-				diff = buf[j] - buf[j-1];
-				if (diff == buf[j-2])
-					num_right_elements++;
-			}
-			if (num_right_elements == NUM_ELEMENTS)
-				num_right_runs++;
-		}
-
-		if (num_right_runs == NUM_RUNS)
-		{
-			*pReg = cnt & 0x3FFFFFFF;
-			cnt++;
-		}
-		else
-		{
-			*pReg = 0x40000000 | cnt;
-			saus('X');
-		}
-		op1 = (int)-cnt;
-		op2 = (int)((op1 & 8) << 28) ^ rand();
-		product = (long long)op1 * (long long)op2;
-		print_word((int)op1);
-		saus(' ');
-		saus('x');
-		saus(' ');
-		print_word((int)op2);
-		saus(' ');
-		saus('=');
-		saus(' ');
-		print_word((int)(product >> 32));
-		print_word((int)product);
-		saus(13);
-		saus(10);
-
-	}
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/fibonacci.s b/lib/CPUs/MIPS/sim/asm/fibonacci.s
deleted file mode 100644
index e042654..0000000
--- a/lib/CPUs/MIPS/sim/asm/fibonacci.s
+++ /dev/null
@@ -1,555 +0,0 @@
-	.file	1 "fibonacci.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	fibonacci
-	.ent	fibonacci
-fibonacci:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$8,2			# 0x2
-	slt	$2,$8,$7
-	sw	$4,0($6)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$5,4($6)
-	.set	macro
-	.set	reorder
-
-	addiu	$6,$6,8
-$L5:
-	lw	$2,-8($6)
-	lw	$3,-4($6)
-	addiu	$8,$8,1
-	addu	$2,$2,$3
-	slt	$4,$8,$7
-	sw	$2,0($6)
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L5
-	addiu	$6,$6,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$8
-	.set	macro
-	.set	reorder
-
-	.end	fibonacci
-	.align	2
-	.globl	test_func
-	.ent	test_func
-test_func:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	lbu	$2,7($4)
-	lbu	$3,6($4)
-	sll	$2,$2,8
-	or	$2,$2,$3
-	sll	$2,$2,16
-	sra	$2,$2,16
-	li	$3,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sw	$2,0($3)
-	.set	macro
-	.set	reorder
-
-	.end	test_func
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L11:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L11
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L14:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L14
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L22
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L23:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L22:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L23
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,7			# 0x7
-	srl	$3,$16,28
-$L33:
-	sltu	$2,$3,10
-	addiu	$17,$17,-1
-	sll	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L29
-	addiu	$4,$3,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$3,55
-$L29:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L33
-	srl	$3,$16,28
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.sdata,"aw",@progbits
-	.align	2
-$LC0:
-	.word	305419896
-	.word	1431677610
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC2:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Ready\r\n\000"
-	.section	.sdata
-	.align	2
-$LC1:
-	.byte	13
-	.4byte	-10862655
-	.byte	30
-	.half	3847
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,536,$31		# vars= 480, regs= 10/0, args= 16, gp= 0
-	.mask	0xc0ff0000,-4
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	addiu	$sp,$sp,-536
-	lw	$3,$LC0+4
-	sw	$2,416($sp)
-	lw	$2,$LC2
-	lwl	$4,$LC1+3
-	lwl	$5,$LC1+7
-	sw	$3,420($sp)
-	sw	$2,432($sp)
-	lw	$3,$LC2+4
-	lw	$2,$LC2+8
-	lwr	$5,$LC1+4
-	lwr	$4,$LC1
-	sw	$3,436($sp)
-	sw	$2,440($sp)
-	lw	$3,$LC2+12
-	lw	$2,$LC2+16
-	sw	$31,532($sp)
-	sw	$5,428($sp)
-	sw	$23,524($sp)
-	sw	$22,520($sp)
-	sw	$21,516($sp)
-	sw	$20,512($sp)
-	sw	$18,504($sp)
-	sw	$17,500($sp)
-	sw	$16,496($sp)
-	sw	$4,424($sp)
-	sw	$3,444($sp)
-	sw	$fp,528($sp)
-	sw	$19,508($sp)
-	sw	$2,448($sp)
-	lw	$3,$LC2+20
-	li	$23,-2147483648			# 0xffffffff80000000
-	ori	$7,$23,0x9
-	sw	$3,452($sp)
-	ori	$6,$23,0x8
-	li	$3,85
-	addiu	$16,$sp,432
-	li	$2,53
-	sb	$2,0($7)
-	move	$4,$16
-	sb	$3,0($6)
-	li	$2,-1431699456			# 0xffffffffaaaa0000
-	sw	$0,456($sp)
-	sw	$0,460($sp)
-	sw	$0,464($sp)
-	sw	$0,468($sp)
-	sw	$0,472($sp)
-	sw	$0,476($sp)
-	sw	$0,480($sp)
-	sw	$0,484($sp)
-	ori	$20,$2,0xaaaa
-	.set	noreorder
-	.set	nomacro
-	jal	strlen
-	addiu	$18,$sp,456
-	.set	macro
-	.set	reorder
-
-	move	$6,$2
-	move	$5,$16
-	.set	noreorder
-	.set	nomacro
-	jal	memcpy
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	li	$4,426770432			# 0x19700000
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	ori	$4,$4,0x1031
-	.set	macro
-	.set	reorder
-
-	move	$22,$0
-	move	$17,$0
-	addiu	$21,$sp,16
-$L38:
-	addu	$16,$21,$17
-	.set	noreorder
-	.set	nomacro
-	jal	sein
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	sltu	$3,$17,31
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L38
-	sb	$2,440($16)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	test_func
-	addiu	$4,$sp,424
-	.set	macro
-	.set	reorder
-
-	li	$fp,100			# 0x64
-	move	$18,$0
-	move	$17,$0
-$L54:
-	move	$2,$21
-	li	$6,99			# 0x63
-$L47:
-	addiu	$6,$6,-1
-	sw	$20,0($2)
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L47
-	addiu	$2,$2,4
-	.set	macro
-	.set	reorder
-
-	xor	$2,$20,$17
-	addiu	$16,$17,1
-	addiu	$2,$2,-1
-	move	$5,$16
-	addiu	$6,$sp,16
-	li	$7,100			# 0x64
-	move	$4,$17
-	.set	noreorder
-	.set	nomacro
-	jal	fibonacci
-	sll	$20,$2,1
-	.set	macro
-	.set	reorder
-
-	li	$7,2			# 0x2
-	addiu	$5,$21,8
-	.set	noreorder
-	.set	nomacro
-	j	$L52
-	li	$6,97			# 0x61
-	.set	macro
-	.set	reorder
-
-$L50:
-	bltz	$6,$L65
-$L52:
-	lw	$2,0($5)
-	lw	$3,-4($5)
-	lw	$4,-8($5)
-	subu	$2,$2,$3
-	addiu	$6,$6,-1
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$2,$L50
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L52
-	addiu	$7,$7,1
-	.set	macro
-	.set	reorder
-
-$L65:
-	beq	$7,$fp,$L66
-$L43:
-	slt	$2,$16,1000
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L54
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-	li	$2,1000			# 0x3e8
-	.set	noreorder
-	.set	nomacro
-	bne	$18,$2,$L55
-	li	$3,1073676288			# 0x3fff0000
-	.set	macro
-	.set	reorder
-
-	ori	$3,$3,0xffff
-	and	$2,$22,$3
-	sw	$2,0($23)
-	addiu	$22,$22,1
-	subu	$16,$0,$22
-$L67:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	andi	$17,$16,0x8
-	.set	macro
-	.set	reorder
-
-	sll	$17,$17,28
-	xor	$17,$17,$2
-	mult	$16,$17
-	mflo	$18
-	mfhi	$19
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,120			# 0x78
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,61			# 0x3d
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,32			# 0x20
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	sra	$4,$19,0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,13			# 0xd
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	li	$4,10			# 0xa
-	.set	macro
-	.set	reorder
-
-	move	$18,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L54
-	move	$17,$0
-	.set	macro
-	.set	reorder
-
-$L66:
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-$L55:
-	li	$2,1073741824			# 0x40000000
-	or	$2,$22,$2
-	li	$4,88			# 0x58
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	sw	$2,0($23)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L67
-	subu	$16,$0,$22
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/idata.ld b/lib/CPUs/MIPS/sim/asm/idata.ld
deleted file mode 100644
index 5913b2c..0000000
--- a/lib/CPUs/MIPS/sim/asm/idata.ld
+++ /dev/null
@@ -1,24 +0,0 @@
-MEMORY
-{
-  imem       : ORIGIN = 0x00000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-
-SECTIONS
-{
-   .stext 0x00000000 :
-   {
-     *(.stext)
-   }  > imem
-   
-   .ktext 0x00000180 :
-   {
-     *(.ktext)
-   }  > imem
-
-   .text 0x00000200 :
-   {
-     *(.text)
-   }  > imem
-
-}
diff --git a/lib/CPUs/MIPS/sim/asm/init.s b/lib/CPUs/MIPS/sim/asm/init.s
deleted file mode 100644
index 41a35da..0000000
--- a/lib/CPUs/MIPS/sim/asm/init.s
+++ /dev/null
@@ -1,28 +0,0 @@
-		.file	"init.s"
-	
-		.text
-		.align	2
-		.globl _init
-		.extern end
-	
-_init:
-		.set	noreorder
-
-		# set uart
-		la	$26, sys_uart_baud
-		addiu	$27, $0, baudrate
-		sb	$27, 0($26)
-		
-		# set stack pointer 
-		la $sp, end
-
-		# jump main
-		la $26, main
-		jalr $26
-
-_terminate:
-		nop
-		j		_terminate
-		nop
-		
-		.set	reorder
diff --git a/lib/CPUs/MIPS/sim/asm/jtag.sh b/lib/CPUs/MIPS/sim/asm/jtag.sh
deleted file mode 100644
index f03567f..0000000
--- a/lib/CPUs/MIPS/sim/asm/jtag.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-#!/bin/sh
-
-TARGET=$(basename $1 .c)
-
-xtclsh.exe $TARGET.RAM.tcl
-xtclsh.exe $TARGET.ROM.tcl
-
diff --git a/lib/CPUs/MIPS/sim/asm/kernel.s b/lib/CPUs/MIPS/sim/asm/kernel.s
deleted file mode 100644
index 7ec783f..0000000
--- a/lib/CPUs/MIPS/sim/asm/kernel.s
+++ /dev/null
@@ -1,251 +0,0 @@
-		.file	"exception.s"
-
-		.section .kdata,"a"
-		.align	2
-_k_stack:	.space	256, 0
-_k_msg1:	.asciiz	"Exception at "
-_k_msg2:	.asciiz	"EPC      : "
-_k_msg3:	.asciiz	"Cause    : "
-_k_msg4:	.asciiz	"Status   : "
-_k_msg5:	.asciiz	"BadVAddr : "
-_k_crlf:	.asciiz	"\r\n"
-_k_hextbl:	.ascii "0123456789ABCDEF"
-
-		.section .ktext,"ax"
-		.align	2
-		.globl _kputs
-
-		.macro kpush reg
-		addiu	$sp, 4
-		sw		\reg, 0($sp)
-		.endm
-		
-		.macro kpop reg
-		lw		\reg, 0($sp)
-		addiu	$sp, -4
-		.endm
-
-_exc_handler:
-
-		sw		$sp, _k_stack
-		la		$sp, _k_stack
-		kpush	$8
-		kpush	$9
-		kpush	$10
-		kpush	$11
-		kpush	$12
-		kpush	$31
-
-		.set	noreorder
-		# Get BadVAddr
-		mfc0	$10, $8
-		kpush	$10
-		# Get Status
-		mfc0	$10, $12
-		kpush	$10
-		# Get Cause
-		mfc0	$10, $13
-		kpush	$10
-		srl		$10, 29
-		andi	$11, $10, 4
-		# Get EPC
-		mfc0	$10, $14
-		kpush	$10
-
-		# Get real EPC
-		addu	$10, $11
-		kpush	$10
-		
-		# set uart
-		la	$26, sys_uart_baud
-		addiu	$27, $0, baudrate
-		sb	$27, 0($26)
-
-		# Print CRLF
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-
-		# Print real EPC
-		la		$11, _k_msg1
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print EPC
-		la		$11, _k_msg2
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Cause
-		la		$11, _k_msg3
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print Status
-		la		$11, _k_msg4
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Print BadVAddr
-		la		$11, _k_msg5
-		jal		_kputs
-		nop
-		kpop	$10
-		jal		_kprint_word		
-		nop
-		la		$11, _k_crlf
-		jal		_kputs
-		nop
-		
-		# Set Error LED and ExcCode LEDs
-		# Get Cause
-		mfc0	$26, $13
-		la 		$27, sys_led_port
-		srl		$26, 2
-		andi	$26, 0x000F
-		or 		$26, $27
-		sw 		$26, 0($27)
-
-		# wait for all interrupts = 0
-$w4x:	mfc0	$26, $13
-		nop
-		srl		$26, 8
-		andi	$26, 0xFF
-		bnez	$26, $w4x
-		nop
-		
-		# Get return address
-		mfc0	$26, $14
-
-		kpop	$31
-		kpop	$12
-		kpop	$11
-		kpop	$10
-		kpop	$9
-		kpop	$8
-		lw		$sp, _k_stack
-
-		# Return
-		jr	$26
-		rfe
-		.set	reorder
-
-# word = $10
-_kprint_word:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 16
-		jal		_kprint_halfword
-		nop
-		kpop	$10
-		jal		_kprint_halfword
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# halfword = $10
-_kprint_halfword:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 8
-		jal		_kprint_byte
-		nop
-		kpop	$10
-		jal		_kprint_byte
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# byte = $10
-_kprint_byte:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		srl		$10, 4
-		jal		_kprint_nibble
-		nop
-		kpop	$10
-		jal		_kprint_nibble
-		nop
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-_kprint_nibble:
-		.set	noreorder
-		kpush	$31
-		kpush	$10
-		la		$12, _k_hextbl
-		andi	$10, 0xF
-		addu	$12, $10
-		lbu		$10, 0($12)
-		jal		_ksaus
-		nop
-		kpop	$10
-		kpop	$31
-		jr		$31
-		nop
-		.set	noreorder
-		
-# char = $10
-_ksaus:
-		.set	noreorder
-		la		$8, sys_uart_stat
-		lbu		$8, 0($8)
-		la		$9, sys_uart_data
-		andi	$8, 0x02
-		bnez	$8, _ksaus
-		nop
-		j		$31
-		sb		$10, 0($9)
-		.set	reorder
-	
-_kputs:
-		.set	noreorder
-		kpush	$11
-		kpush	$31
-$kpl:	lbu		$10, 0($11)
-		addiu	$11, 1
-		blez	$10, $kpex
-		nop
-		jal		_ksaus
-		nop
-		j		$kpl
-		nop
-$kpex:	kpop	$31
-		kpop	$11
-		jr		$31
-		nop		
-		.set	reorder
-	
diff --git a/lib/CPUs/MIPS/sim/asm/link.ld b/lib/CPUs/MIPS/sim/asm/link.ld
deleted file mode 100644
index e175fa8..0000000
--- a/lib/CPUs/MIPS/sim/asm/link.ld
+++ /dev/null
@@ -1,47 +0,0 @@
-MEMORY
-{
-  imem       : ORIGIN = 0x00400000, LENGTH = 0x00004000  /*   8K    */
-  dmem       : ORIGIN = 0x00000000, LENGTH = 0x00002000  /*   8K    */
-}
-
-end = 0x7FFFEFFC;
-baudrate = 0x0D;
-sys_led_port = 0x80000000;
-sys_uart_baud = 0x80000009;
-sys_uart_stat = 0x80000008;
-sys_uart_data = 0x80000004;
-sys_timer_sec = 0x80000014;
-sys_timer_usec = 0x80000010;
-
-SECTIONS
-{
-   .stext 0x00400000 :
-   {
-     *(.stext)
-   }  > imem
-   
-   .ktext 0x00400180 :
-   {
-     *(.ktext)
-   }  > imem
-
-   .text . :
-   {
-     *(.text)
-   }  > imem
-
-   .data 0x00000000 : ALIGN(2)
-   {
-      *(.rodata*) *(.data) *(.sdata) *(.sbss) *(.kdata)
-   }  > dmem
-
-   .bss . :
-   {
-      *(.bss)
-   }  > dmem
-
-   .eh_frame . :
-   {
-      *(.eh_frame)
-   }  > dmem
-}
diff --git a/lib/CPUs/MIPS/sim/asm/load_store.c b/lib/CPUs/MIPS/sim/asm/load_store.c
deleted file mode 100644
index b39630e..0000000
--- a/lib/CPUs/MIPS/sim/asm/load_store.c
+++ /dev/null
@@ -1,64 +0,0 @@
-//#include <stdio.h>
-//#include <stdlib.h>
-//#include <string.h>
-
-int main (void)
-{
-
-
-__asm
-(
-	".set	noreorder\n"
-	"li		$8, 0x81234678\n"
-	"li		$15, 0x10000000\n"
-	"li		$16, 0xAAAAAAAA\n"
-	"li		$17, 0xBBBBBBBB\n"
-	"li		$18, 0xCCCCCCCC\n"
-	"li		$19, 0xDDDDDDDD\n"
-	"li		$24, 0x11111111\n"
-	"li		$25, 0x22222222\n"
-	"li		$26, 0x33333333\n"
-	"li		$27, 0x44444444\n"
-	"sw		$8, 0($15)\n"
-	"nop\n"
-	"lwl	$16, 0($15)\n"
-	"lwl	$17, 1($15)\n"
-	"lwl	$18, 2($15)\n"
-	"lwl	$19, 3($15)\n"
-	"nop\n"
-	"lwr	$24, 0($15)\n"
-	"lwr	$25, 1($15)\n"
-	"lwr	$26, 2($15)\n"
-	"lwr	$27, 3($15)\n"
-	"nop\n"
-	"lbu	$16, 0($15)\n"
-	"lbu	$17, 1($15)\n"
-	"lbu	$18, 2($15)\n"
-	"lbu	$19, 3($15)\n"
-	"nop\n"
-	"lb		$16, 0($15)\n"
-	"lb		$17, 1($15)\n"
-	"lb		$18, 2($15)\n"
-	"lb		$19, 3($15)\n"
-	"nop\n"
-	"swl	$8, 4($15)\n"
-	"swl	$8, 9($15)\n"
-	"swl	$8, 14($15)\n"
-	"swl	$8, 19($15)\n"
-	"nop\n"
-	"swr	$8, 20($15)\n"
-	"swr	$8, 25($15)\n"
-	"swr	$8, 30($15)\n"
-	"swr	$8, 35($15)\n"
-	"nop\n"
-	"sb		$8, 4($15)\n"
-	"sb		$8, 5($15)\n"
-	"sb		$8, 6($15)\n"
-	"sb		$8, 7($15)\n"
-	"nop\n"
-	".set	reorder\n"
-
-);
-
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/load_store.s b/lib/CPUs/MIPS/sim/asm/load_store.s
deleted file mode 100644
index 9aa8fca..0000000
--- a/lib/CPUs/MIPS/sim/asm/load_store.s
+++ /dev/null
@@ -1,64 +0,0 @@
-	.file	1 "load_store.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-li		$8, 0x81234678
-li		$15, 0x10000000
-li		$16, 0xAAAAAAAA
-li		$17, 0xBBBBBBBB
-li		$18, 0xCCCCCCCC
-li		$19, 0xDDDDDDDD
-li		$24, 0x11111111
-li		$25, 0x22222222
-li		$26, 0x33333333
-li		$27, 0x44444444
-sw		$8, 0($15)
-nop
-lwl	$16, 0($15)
-lwl	$17, 1($15)
-lwl	$18, 2($15)
-lwl	$19, 3($15)
-nop
-lwr	$24, 0($15)
-lwr	$25, 1($15)
-lwr	$26, 2($15)
-lwr	$27, 3($15)
-nop
-lbu	$16, 0($15)
-lbu	$17, 1($15)
-lbu	$18, 2($15)
-lbu	$19, 3($15)
-nop
-lb		$16, 0($15)
-lb		$17, 1($15)
-lb		$18, 2($15)
-lb		$19, 3($15)
-nop
-swl	$8, 4($15)
-swl	$8, 9($15)
-swl	$8, 14($15)
-swl	$8, 19($15)
-nop
-swr	$8, 20($15)
-swr	$8, 25($15)
-swr	$8, 30($15)
-swr	$8, 35($15)
-nop
-sb		$8, 4($15)
-sb		$8, 5($15)
-sb		$8, 6($15)
-sb		$8, 7($15)
-nop
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/make.sh b/lib/CPUs/MIPS/sim/asm/make.sh
deleted file mode 100644
index 2f39996..0000000
--- a/lib/CPUs/MIPS/sim/asm/make.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/bin/sh
-
-TARGET=$(basename $1 .c)
-TARGET_CPU=r3000
-ROM_WORDADDR_WIDTH=12
-RAM_WORDADDR_WIDTH=11
-
-echo Building $TARGET...
-
-mipsel-elf-as.exe -march=$TARGET_CPU startup.s -o startup.o
-mipsel-elf-as.exe -march=$TARGET_CPU init.s -o init.o
-mipsel-elf-as.exe -march=$TARGET_CPU kernel.s -o kernel.o
-
-#mipsel-elf-gcc -O2 -march=$TARGET_CPU $TARGET.c -o $TARGET.s -L $LIBDIR
-
-mipsel-elf-gcc -msoft-float -O2 -c utils.c -o utils.o
-mipsel-elf-gcc -msoft-float -O2 -c $TARGET.c -o $TARGET.o
-mipsel-elf-ld.exe -G 0 -M -T link.ld startup.o init.o kernel.o utils.o $TARGET.o -o $TARGET.elf -L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/3.4.6 -lc -lgcc >$TARGET.map
-mipsel-elf-objdump.exe -d $TARGET.elf > $TARGET.dis
-
-mipsel-elf-objcopy.exe -j .stext -j .ktext -j .text $TARGET.elf -O binary $TARGET.ROM.bin
-mipsel-elf-objcopy.exe -j .data $TARGET.elf -O binary $TARGET.RAM.bin
-
-./romgen.exe $TARGET.ROM.bin $ROM_WORDADDR_WIDTH
-./ramgen.exe $TARGET.RAM.bin $RAM_WORDADDR_WIDTH
-
-#xtclsh.exe $TARGET.RAM.tcl
-#xtclsh.exe $TARGET.ROM.tcl
-
-echo done.
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/mips_exception.s b/lib/CPUs/MIPS/sim/asm/mips_exception.s
deleted file mode 100644
index c8c88a1..0000000
--- a/lib/CPUs/MIPS/sim/asm/mips_exception.s
+++ /dev/null
@@ -1,31 +0,0 @@
-main:
-		j	lab
-#		nop
-#		break 52
-lab:			
-		li, $8, 0x81234678
-
-# SB
-		li, $15, 0x10000000
-		li  $16, 0x00400014
-		mtc0, $16, $14
-		nop
-		nop
-		rfe
-
-# Address error exception
-		sw	$8, 1($15)
-		sw	$8, 2($15)
-		sw	$8, 3($15)
-		
-# Address error exception
-		sh  $8, 1($15)
-
-# Address error exception
-		sh  $8, 3($15)
-
-
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt b/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt
deleted file mode 100644
index 30b75bc..0000000
--- a/lib/CPUs/MIPS/sim/asm/mips_load_store_.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-SB (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0001            0
-1              0010            1
-2              0100            2
-3              1000            3
-
-SH (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0011            0
-2              1100            2
-
-SWL (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              0001            1 
-1              0011            2
-2              0111            3
-3              1111            0
-
-SWR (tested by SPIM)
-VA(1..0)       DMEM_WE        ROL
-0              1111            0
-1              1110            1
-2              1100            2
-3              1000            3
-
-LB (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0   
-1              1111            1   
-2              1111            2   
-3              1111            3   
-
-LH (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0      
-2              1111            2   
-
-LWL (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1000            1
-1              1100            2
-2              1110            3
-3              1111            0
-
-LWR (tested by SPIM)
-VA(1..0)       REG_WE         ROR
-0              1111            0   
-1              0111            1   
-2              0011            2   
-3              0001            3   
-
-
-
-*SHIFTER*        SB      SH      SWL      SWR     SW
-shift_byp        0       0        0        0      1               
-shift_off        0       0        1        0      x
-
-SHL = VA + shift_off
-
-*Byte Enable*    SB      SH      SWL      SWR     SW
-be_byp           0       0        0        0      1               
-quarter_word_en  1       0        0        0      x
-half_word_en     0       1        0        0      x
-align_left       x       x        0        1      x  
-
-
-*SHIFTER*        LB      LH      LWL      LWR     LW
-shift_byp        0       0        0        0      1               
-shift_off        0       0        1        0      x 
-
-SHL = VA + shift_off
-
-*Byte Enable*    LB      LH      LWL      LWR     LW
-be_byp           1       1        0        0      1
-align_left       x       x        1        0      x
-
-
-* Sign ext*    
-se_byp =  shift_byp and (shift_byp and not be_byp)
-
-
-00 11
-01 10
-10 01
-11 00
diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.c b/lib/CPUs/MIPS/sim/asm/muldiv.c
deleted file mode 100644
index 1f15755..0000000
--- a/lib/CPUs/MIPS/sim/asm/muldiv.c
+++ /dev/null
@@ -1,134 +0,0 @@
-//#include <stdio.h>
-#include <stdlib.h>
-//#include <string.h>
-
-#define	NUM_ELEMENTS	100
-#define	NUM_RUNS		1000
-
-char sein(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void saus(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		saus(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		saus(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
-int main (void)
-{
-	int cnt, i, j;
-	int mix, *pReg = (int*)0x80000000;
-	volatile char *pUART_data = (char*)0x80000004;
-	volatile char *pUART_ctrl = (char*)0x80000008;
-	volatile char *pUART_baud = (char*)0x80000009;
-	char msg[] = "MIPS R3000 CPU\r\nMul/Div Test\r\n";
-	int s1, s2, sp, st;
-
-	div_t div_res;
-
-	*pUART_baud = 0x35;
-	*pUART_ctrl = 0x55;
-
-	srand(0x19701031);
-
-	sputs(msg);
-
-	cnt = 0;
-	while(1)
-	{
-		for (i=0; i < 1000; i++)
-		{
-			for (j=1; j < 1000; j++)
-			{
-				mix = (int)rand();
-				mix = (mix << 8) ^ (mix << 16);
-				s1 = (int)rand() ^ mix;
-				mix = (int)rand();
-				mix = (mix << 8) ^ (mix << 16);
-				s2 = (int)rand() ^ mix;
-	//			s1 = i;
-	//			s2 = j;
-
-				div_res = div(s1, s2);
-
-	//			print_word(s1);
-	//			sputs(" / ");
-	//			print_word(s2);
-	//			sputs(" = ");
-	//			print_word(div_res.quot);
-	//			sputs(" R: ");
-	//			print_word(div_res.rem);
-	//			sputs(" -- ");
-
-				sp = s2*div_res.quot;
-				st = div_res.rem + sp;
-				if (st != s1)
-				{
-					sputs("Failed: ");
-					sputs("d*quot = ");
-					print_word(sp);
-					sputs("\r\n");
-					return -1;
-				}
-			}
-		}
-		sputs("Iteration ");
-		print_word(cnt++);
-		sputs(": Passed\r\n");
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/muldiv.s b/lib/CPUs/MIPS/sim/asm/muldiv.s
deleted file mode 100644
index c6de7d9..0000000
--- a/lib/CPUs/MIPS/sim/asm/muldiv.s
+++ /dev/null
@@ -1,391 +0,0 @@
-	.file	1 "muldiv.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L2
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L6:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L6
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L14
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L15:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L14:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L15
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L25:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L21
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L21:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L25
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L30:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L30
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"MIPS R3000 CPU\r\n"
-	.ascii	"Mul/Div Test\r\n\000"
-	.align	2
-$LC1:
-	.ascii	"Failed: \000"
-	.align	2
-$LC2:
-	.ascii	"d*quot = \000"
-	.align	2
-$LC3:
-	.ascii	"\r\n\000"
-	.align	2
-$LC4:
-	.ascii	"Iteration \000"
-	.align	2
-$LC5:
-	.ascii	": Passed\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,88,$31		# vars= 40, regs= 7/0, args= 16, gp= 0
-	.mask	0x803f0000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC0
-	addiu	$sp,$sp,-88
-	sw	$2,16($sp)
-	lw	$3,$LC0+4
-	lw	$2,$LC0+8
-	sw	$3,20($sp)
-	sw	$2,24($sp)
-	lw	$3,$LC0+12
-	lw	$2,$LC0+16
-	sw	$3,28($sp)
-	sw	$2,32($sp)
-	lw	$3,$LC0+20
-	lw	$2,$LC0+24
-	sw	$3,36($sp)
-	sw	$2,40($sp)
-	lhu	$3,$LC0+28
-	lbu	$2,$LC0+30
-	li	$5,-2147483648			# 0xffffffff80000000
-	ori	$6,$5,0x9
-	sh	$3,44($sp)
-	sb	$2,46($sp)
-	ori	$5,$5,0x8
-	li	$3,53
-	li	$2,85
-	li	$4,426770432			# 0x19700000
-	sb	$3,0($6)
-	ori	$4,$4,0x1031
-	sb	$2,0($5)
-	sw	$31,80($sp)
-	sw	$21,76($sp)
-	sw	$19,68($sp)
-	sw	$20,72($sp)
-	sw	$18,64($sp)
-	sw	$17,60($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	sw	$16,56($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	move	$21,$0
-	addiu	$19,$sp,48
-	move	$20,$0
-$L44:
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-$L51:
-	beq	$3,$0,$L50
-$L43:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$17,$2,$16
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	xor	$16,$2,$16
-	move	$6,$16
-	move	$4,$19
-	.set	noreorder
-	.set	nomacro
-	jal	div
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	lw	$2,48($sp)
-	mult	$2,$16
-	lw	$2,52($sp)
-	mflo	$16
-	addu	$2,$2,$16
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$17,$L51
-	slt	$3,$18,1000
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC1
-	jal	sputs
-	la	$4,$LC2
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC3
-	jal	sputs
-	lw	$31,80($sp)
-	lw	$21,76($sp)
-	lw	$20,72($sp)
-	lw	$19,68($sp)
-	lw	$18,64($sp)
-	lw	$17,60($sp)
-	lw	$16,56($sp)
-	li	$2,-1			# 0xffffffffffffffff
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,88
-	.set	macro
-	.set	reorder
-
-$L50:
-	addiu	$20,$20,1
-	slt	$2,$20,1000
-	bne	$2,$0,$L44
-	la	$4,$LC4
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$20,$0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$21
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC5
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$21,$21,1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L43
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/mult.txt b/lib/CPUs/MIPS/sim/asm/mult.txt
deleted file mode 100644
index 72f9226..0000000
--- a/lib/CPUs/MIPS/sim/asm/mult.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-0x12345678 x 0x87654321
-HI      = f76c768d   LO      = 70b88d78		signed
-HI      = 09a0cd05   LO      = 70b88d78		unsigned
-
-0x87654321 x 0x12345678
-HI      = f76c768d   LO      = 70b88d78		signed
-HI      = 09a0cd05   LO      = 70b88d78		unsigned
-
-0x12345678 x 0x12345678
-HI      = 014b66dc   LO      = 1df4d840		signed
-HI      = 014b66dc   LO      = 1df4d840		unsigned
-
-0x87654321 x 0x87654321
-HI      = 38d16e98   LO      = d7a44a41		signed
-HI      = 479bf4da   LO      = d7a44a41		unsigned
-
-
-p1 * n2 = not(p1 * (1 + not(n2)))
-
-n1 * p1 = not((1 + not(n1)) * p2)
-
-p1 * p2 = p1 * p2
-
-n1 * n2 = not(n1) * not(n2);
-
-
-12345678 * ( 87654321 not and FFFFFFFF ) = + 12345677 =
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/rmd160.s b/lib/CPUs/MIPS/sim/asm/rmd160.s
deleted file mode 100644
index 6028ab9..0000000
--- a/lib/CPUs/MIPS/sim/asm/rmd160.s
+++ /dev/null
@@ -1,2482 +0,0 @@
-	.file	1 "rmd160.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	MDinit
-	.ent	MDinit
-MDinit:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-1009647616			# 0xffffffffc3d20000
-	ori	$2,$2,0xe1f0
-	sw	$2,16($4)
-	li	$3,1732575232			# 0x67450000
-	li	$2,-271777792			# 0xffffffffefcd0000
-	ori	$3,$3,0x2301
-	ori	$2,$2,0xab89
-	sw	$3,0($4)
-	sw	$2,4($4)
-	li	$3,-1732640768			# 0xffffffff98ba0000
-	li	$2,271712256			# 0x10320000
-	ori	$3,$3,0xdcfe
-	ori	$2,$2,0x5476
-	sw	$3,8($4)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sw	$2,12($4)
-	.set	macro
-	.set	reorder
-
-	.end	MDinit
-	.align	2
-	.globl	compress
-	.ent	compress
-compress:
-	.frame	$sp,128,$31		# vars= 88, regs= 9/0, args= 0, gp= 0
-	.mask	0x40ff0000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-128
-	sw	$19,100($sp)
-	lw	$19,12($4)
-	sw	$20,104($sp)
-	lw	$24,4($4)
-	lw	$20,8($4)
-	sw	$fp,120($sp)
-	sw	$23,116($sp)
-	sw	$22,112($sp)
-	sw	$21,108($sp)
-	sw	$18,96($sp)
-	sw	$17,92($sp)
-	sw	$16,88($sp)
-	nor	$2,$0,$19
-	lw	$6,20($5)
-	lw	$7,0($5)
-	lw	$21,0($4)
-	xor	$3,$24,$20
-	or	$2,$2,$20
-	xor	$3,$3,$19
-	xor	$2,$2,$24
-	addu	$3,$3,$7
-	move	$17,$21
-	addu	$2,$2,$6
-	li	$11,1352794112			# 0x50a20000
-	ori	$11,$11,0x8be6
-	addu	$21,$21,$3
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	lw	$25,16($4)
-	sw	$6,12($sp)
-	srl	$3,$21,21
-	srl	$8,$20,22
-	sll	$6,$20,10
-	sll	$2,$21,11
-	or	$23,$6,$8
-	or	$2,$2,$3
-	srl	$7,$17,24
-	sll	$3,$17,8
-	addu	$21,$2,$25
-	or	$3,$3,$7
-	nor	$2,$0,$23
-	addu	$17,$3,$25
-	lw	$8,56($5)
-	lw	$6,4($5)
-	xor	$3,$21,$24
-	or	$2,$2,$24
-	xor	$3,$3,$23
-	xor	$2,$2,$17
-	move	$fp,$25
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$25,$25,$3
-	addu	$2,$2,$fp
-	addu	$fp,$2,$11
-	sw	$8,36($sp)
-	srl	$3,$25,18
-	srl	$8,$24,22
-	sll	$6,$24,10
-	sll	$2,$25,14
-	or	$22,$6,$8
-	or	$2,$2,$3
-	srl	$7,$fp,23
-	sll	$3,$fp,9
-	addu	$25,$2,$19
-	or	$3,$3,$7
-	nor	$2,$0,$22
-	addu	$fp,$3,$19
-	lw	$7,8($5)
-	lw	$8,28($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$22
-	xor	$2,$2,$fp
-	move	$18,$19
-	addu	$3,$3,$7
-	addu	$2,$2,$8
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	sw	$7,0($sp)
-	srl	$6,$17,22
-	srl	$7,$19,17
-	sll	$3,$19,15
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,23
-	sll	$6,$18,9
-	addu	$19,$3,$23
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$2,$0,$17
-	sll	$3,$21,10
-	addu	$18,$6,$23
-	or	$21,$3,$7
-	lw	$6,0($5)
-	lw	$7,12($5)
-	xor	$3,$19,$25
-	or	$2,$2,$fp
-	xor	$3,$3,$21
-	xor	$2,$2,$18
-	addu	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$20,$23,$3
-	addu	$2,$2,$23
-	addu	$23,$2,$11
-	sw	$6,8($sp)
-	srl	$7,$20,20
-	srl	$6,$fp,22
-	sll	$3,$20,12
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,21
-	sll	$6,$23,11
-	addu	$20,$3,$22
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$2,$0,$fp
-	sll	$3,$25,10
-	addu	$23,$6,$22
-	or	$25,$3,$7
-	lw	$6,16($5)
-	sw	$8,20($sp)
-	xor	$3,$20,$19
-	lw	$8,36($5)
-	or	$2,$2,$18
-	xor	$3,$3,$25
-	xor	$2,$2,$23
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$24,$22,$3
-	addu	$2,$2,$22
-	addu	$22,$2,$11
-	srl	$7,$24,27
-	srl	$6,$18,22
-	sll	$3,$24,5
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$3,$3,$7
-	srl	$2,$22,19
-	sll	$6,$22,13
-	addu	$24,$3,$21
-	or	$6,$6,$2
-	srl	$7,$19,22
-	nor	$2,$0,$18
-	sll	$3,$19,10
-	addu	$22,$6,$17
-	or	$19,$3,$7
-	or	$2,$2,$23
-	lw	$7,0($sp)
-	sw	$8,16($sp)
-	xor	$3,$24,$20
-	lw	$8,20($5)
-	xor	$2,$2,$22
-	xor	$3,$3,$19
-	addu	$2,$2,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	addu	$21,$21,$3
-	srl	$6,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$6
-	sw	$7,28($sp)
-	srl	$2,$17,17
-	srl	$7,$21,24
-	sll	$3,$21,8
-	sll	$6,$17,15
-	or	$3,$3,$7
-	or	$6,$6,$2
-	srl	$7,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$7
-	lw	$2,44($5)
-	addu	$21,$3,$25
-	nor	$3,$0,$23
-	sw	$2,44($sp)
-	addu	$17,$6,$fp
-	lw	$7,44($sp)
-	lw	$6,24($5)
-	xor	$2,$21,$24
-	or	$3,$3,$22
-	xor	$2,$2,$20
-	xor	$3,$3,$17
-	addu	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$25,$25,$2
-	addu	$3,$3,$fp
-	addu	$fp,$3,$11
-	srl	$7,$25,25
-	srl	$6,$22,22
-	sll	$3,$25,7
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$2,$fp,17
-	sll	$6,$fp,15
-	addu	$25,$3,$19
-	or	$6,$6,$2
-	srl	$7,$24,22
-	nor	$2,$0,$22
-	sll	$3,$24,10
-	addu	$fp,$6,$18
-	or	$24,$3,$7
-	lw	$8,16($5)
-	lw	$6,28($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$24
-	xor	$2,$2,$fp
-	addu	$3,$3,$6
-	addu	$2,$2,$8
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	srl	$7,$19,23
-	srl	$6,$17,22
-	sll	$3,$19,9
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,27
-	sll	$6,$18,5
-	addu	$19,$3,$20
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$3,$0,$17
-	sll	$2,$21,10
-	addu	$18,$6,$23
-	or	$21,$2,$7
-	sw	$8,4($sp)
-	lw	$7,52($5)
-	lw	$8,32($5)
-	xor	$2,$19,$25
-	or	$3,$3,$fp
-	xor	$2,$2,$21
-	xor	$3,$3,$18
-	addu	$2,$2,$8
-	addu	$3,$3,$7
-	addu	$20,$20,$2
-	addu	$3,$3,$23
-	addu	$23,$3,$11
-	sw	$7,52($sp)
-	srl	$6,$fp,22
-	srl	$7,$20,21
-	sll	$3,$20,11
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,25
-	sll	$6,$23,7
-	addu	$20,$3,$24
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$3,$0,$fp
-	sll	$2,$25,10
-	lw	$12,24($5)
-	addu	$23,$6,$22
-	or	$25,$2,$7
-	lw	$6,36($5)
-	xor	$2,$20,$19
-	or	$3,$3,$18
-	xor	$2,$2,$25
-	xor	$3,$3,$23
-	addu	$2,$2,$6
-	addu	$3,$3,$12
-	addu	$24,$24,$2
-	addu	$3,$3,$22
-	addu	$22,$3,$11
-	srl	$7,$24,19
-	srl	$6,$18,22
-	sll	$3,$24,13
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$3,$3,$7
-	srl	$2,$22,25
-	sll	$6,$22,7
-	addu	$24,$3,$21
-	or	$6,$6,$2
-	srl	$7,$19,22
-	nor	$3,$0,$18
-	sll	$2,$19,10
-	addu	$22,$6,$17
-	or	$19,$2,$7
-	lw	$8,40($5)
-	lw	$7,60($5)
-	xor	$2,$24,$20
-	or	$3,$3,$23
-	xor	$2,$2,$19
-	xor	$3,$3,$22
-	addu	$2,$2,$8
-	addu	$3,$3,$7
-	addu	$21,$21,$2
-	addu	$3,$3,$17
-	sw	$7,48($sp)
-	addu	$17,$3,$11
-	srl	$7,$21,18
-	srl	$6,$23,22
-	sll	$3,$21,14
-	sll	$2,$23,10
-	or	$23,$2,$6
-	or	$3,$3,$7
-	srl	$2,$17,24
-	sll	$6,$17,8
-	addu	$21,$3,$25
-	or	$6,$6,$2
-	srl	$7,$20,22
-	nor	$3,$0,$23
-	sll	$2,$20,10
-	lw	$13,32($5)
-	addu	$17,$6,$fp
-	or	$20,$2,$7
-	lw	$6,44($5)
-	xor	$2,$21,$24
-	or	$3,$3,$22
-	xor	$2,$2,$20
-	xor	$3,$3,$17
-	addu	$2,$2,$6
-	addu	$3,$3,$13
-	addu	$25,$25,$2
-	addu	$3,$3,$fp
-	addu	$fp,$3,$11
-	srl	$7,$25,17
-	srl	$6,$22,22
-	sll	$3,$25,15
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$2,$fp,21
-	sll	$6,$fp,11
-	addu	$25,$3,$19
-	or	$6,$6,$2
-	srl	$7,$24,22
-	nor	$2,$0,$22
-	sll	$3,$24,10
-	addu	$fp,$6,$18
-	or	$24,$3,$7
-	lw	$8,48($5)
-	lw	$7,4($5)
-	xor	$3,$25,$21
-	or	$2,$2,$17
-	xor	$3,$3,$24
-	xor	$2,$2,$fp
-	addu	$3,$3,$8
-	addu	$2,$2,$7
-	addu	$19,$19,$3
-	addu	$2,$2,$18
-	sw	$7,40($sp)
-	addu	$18,$2,$11
-	srl	$7,$19,26
-	srl	$6,$17,22
-	sll	$3,$19,6
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$2,$18,18
-	sll	$6,$18,14
-	addu	$19,$3,$20
-	or	$6,$6,$2
-	srl	$7,$21,22
-	nor	$2,$0,$17
-	sll	$3,$21,10
-	addu	$18,$6,$23
-	or	$21,$3,$7
-	lw	$6,40($5)
-	lw	$7,52($5)
-	xor	$3,$19,$25
-	or	$2,$2,$fp
-	xor	$3,$3,$21
-	xor	$2,$2,$18
-	addu	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$20,$20,$3
-	addu	$2,$2,$23
-	sw	$6,32($sp)
-	addu	$23,$2,$11
-	srl	$7,$20,25
-	srl	$6,$fp,22
-	sll	$3,$20,7
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$7
-	srl	$2,$23,18
-	sll	$6,$23,14
-	addu	$20,$3,$24
-	or	$6,$6,$2
-	srl	$7,$25,22
-	nor	$3,$0,$fp
-	sll	$2,$25,10
-	lw	$16,12($5)
-	addu	$23,$6,$22
-	or	$25,$2,$7
-	lw	$8,56($5)
-	xor	$2,$20,$19
-	or	$3,$3,$18
-	xor	$2,$2,$25
-	xor	$3,$3,$23
-	addu	$2,$2,$8
-	addu	$3,$3,$16
-	addu	$24,$24,$2
-	addu	$3,$3,$22
-	addu	$22,$3,$11
-	srl	$7,$24,23
-	sll	$3,$24,9
-	or	$3,$3,$7
-	srl	$6,$18,22
-	sll	$2,$18,10
-	addu	$24,$3,$21
-	or	$18,$2,$6
-	srl	$7,$19,22
-	srl	$2,$22,20
-	sll	$6,$22,12
-	sll	$3,$19,10
-	or	$19,$3,$7
-	or	$6,$6,$2
-	lw	$7,60($5)
-	xor	$3,$24,$20
-	nor	$2,$0,$18
-	addu	$22,$6,$17
-	or	$2,$2,$23
-	lw	$6,48($5)
-	xor	$3,$3,$19
-	addu	$3,$3,$7
-	xor	$2,$2,$22
-	addu	$21,$21,$3
-	addu	$2,$2,$6
-	sw	$6,24($sp)
-	srl	$3,$21,24
-	addu	$2,$2,$17
-	sll	$6,$21,8
-	addu	$17,$2,$11
-	or	$6,$6,$3
-	srl	$7,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$7
-	addu	$21,$6,$25
-	srl	$8,$17,26
-	sll	$3,$17,6
-	srl	$7,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$3,$3,$8
-	nor	$6,$0,$21
-	addu	$17,$3,$fp
-	lw	$8,28($5)
-	and	$6,$6,$20
-	and	$2,$21,$24
-	nor	$7,$0,$23
-	and	$7,$7,$22
-	and	$3,$17,$23
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$8
-	li	$11,1518469120			# 0x5a820000
-	ori	$11,$11,0x7999
-	addu	$2,$2,$25
-	addu	$3,$3,$12
-	li	$10,1548550144			# 0x5c4d0000
-	ori	$10,$10,0xd124
-	addu	$25,$2,$11
-	addu	$3,$3,$fp
-	addu	$fp,$3,$10
-	srl	$8,$25,25
-	sll	$3,$25,7
-	srl	$9,$fp,23
-	or	$3,$3,$8
-	srl	$7,$22,22
-	sll	$6,$fp,9
-	sll	$2,$22,10
-	addu	$25,$3,$19
-	or	$22,$2,$7
-	or	$6,$6,$9
-	srl	$3,$24,22
-	sll	$2,$24,10
-	addu	$fp,$6,$18
-	or	$24,$2,$3
-	nor	$6,$0,$25
-	and	$6,$6,$24
-	and	$2,$25,$21
-	nor	$7,$0,$22
-	and	$7,$7,$17
-	and	$3,$fp,$22
-	or	$2,$2,$6
-	lw	$6,44($sp)
-	or	$3,$3,$7
-	lw	$7,16($5)
-	addu	$3,$3,$6
-	addu	$3,$3,$18
-	addu	$2,$2,$7
-	addu	$18,$3,$10
-	addu	$2,$2,$19
-	addu	$19,$2,$11
-	srl	$7,$18,19
-	srl	$6,$17,22
-	sll	$3,$18,13
-	sll	$2,$17,10
-	or	$17,$2,$6
-	or	$3,$3,$7
-	srl	$6,$19,26
-	sll	$2,$19,6
-	addu	$18,$3,$23
-	or	$2,$2,$6
-	nor	$6,$0,$17
-	addu	$19,$2,$20
-	and	$6,$6,$fp
-	and	$2,$18,$17
-	srl	$7,$21,22
-	sll	$3,$21,10
-	or	$2,$2,$6
-	or	$21,$3,$7
-	addu	$2,$2,$16
-	nor	$3,$0,$19
-	lw	$8,52($5)
-	and	$3,$3,$21
-	and	$6,$19,$25
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	or	$6,$6,$3
-	addu	$6,$6,$8
-	srl	$7,$fp,22
-	srl	$8,$23,17
-	sll	$3,$23,15
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$3,$3,$8
-	addu	$6,$6,$20
-	addu	$23,$3,$22
-	addu	$20,$6,$11
-	nor	$2,$0,$fp
-	srl	$7,$20,24
-	and	$2,$2,$18
-	and	$3,$23,$fp
-	sll	$6,$20,8
-	or	$6,$6,$7
-	or	$3,$3,$2
-	srl	$7,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$7
-	lw	$2,20($sp)
-	addu	$20,$6,$24
-	addu	$3,$3,$2
-	addu	$3,$3,$22
-	nor	$2,$0,$20
-	addu	$22,$3,$10
-	and	$2,$2,$25
-	lw	$3,4($5)
-	and	$6,$20,$19
-	or	$6,$6,$2
-	srl	$8,$22,25
-	addu	$6,$6,$3
-	srl	$7,$18,22
-	sll	$3,$22,7
-	sll	$2,$18,10
-	or	$18,$2,$7
-	or	$3,$3,$8
-	addu	$22,$3,$17
-	nor	$7,$0,$18
-	and	$7,$7,$23
-	and	$3,$22,$18
-	addu	$6,$6,$24
-	addu	$24,$6,$11
-	or	$3,$3,$7
-	lw	$7,8($sp)
-	srl	$6,$24,19
-	sll	$2,$24,13
-	or	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$24,$2,$21
-	srl	$6,$19,22
-	sll	$2,$19,10
-	addu	$3,$3,$17
-	or	$19,$2,$6
-	addu	$17,$3,$10
-	nor	$2,$0,$24
-	and	$2,$2,$19
-	and	$3,$24,$20
-	srl	$8,$17,20
-	sll	$7,$17,12
-	or	$7,$7,$8
-	or	$3,$3,$2
-	lw	$8,40($5)
-	srl	$6,$23,22
-	sll	$2,$23,10
-	or	$23,$2,$6
-	addu	$17,$7,$fp
-	addu	$3,$3,$8
-	nor	$6,$0,$23
-	and	$6,$6,$22
-	and	$2,$17,$23
-	addu	$3,$3,$21
-	addu	$21,$3,$11
-	or	$2,$2,$6
-	lw	$6,52($sp)
-	srl	$7,$21,21
-	sll	$3,$21,11
-	or	$3,$3,$7
-	addu	$2,$2,$6
-	addu	$21,$3,$25
-	addu	$2,$2,$fp
-	srl	$6,$20,22
-	sll	$3,$20,10
-	or	$20,$3,$6
-	addu	$fp,$2,$10
-	nor	$7,$0,$21
-	and	$7,$7,$20
-	srl	$9,$fp,24
-	and	$6,$21,$24
-	srl	$8,$22,22
-	sll	$3,$fp,8
-	sll	$2,$22,10
-	or	$22,$2,$8
-	or	$3,$3,$9
-	or	$6,$6,$7
-	addu	$fp,$3,$18
-	addu	$6,$6,$12
-	nor	$3,$0,$22
-	lw	$8,12($sp)
-	and	$3,$3,$17
-	and	$2,$fp,$22
-	addu	$6,$6,$25
-	addu	$25,$6,$11
-	or	$2,$2,$3
-	srl	$7,$25,23
-	addu	$2,$2,$8
-	sll	$3,$25,9
-	or	$3,$3,$7
-	addu	$2,$2,$18
-	addu	$25,$3,$19
-	addu	$18,$2,$10
-	srl	$3,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$3
-	srl	$6,$17,22
-	nor	$3,$0,$25
-	sll	$2,$17,10
-	or	$17,$2,$6
-	srl	$8,$18,23
-	and	$3,$3,$24
-	and	$2,$25,$21
-	sll	$7,$18,9
-	or	$7,$7,$8
-	or	$2,$2,$3
-	lw	$3,60($5)
-	addu	$18,$7,$23
-	nor	$6,$0,$17
-	and	$6,$6,$fp
-	addu	$2,$2,$3
-	and	$3,$18,$17
-	or	$3,$3,$6
-	lw	$6,32($sp)
-	addu	$2,$2,$19
-	addu	$19,$2,$11
-	addu	$3,$3,$6
-	addu	$3,$3,$23
-	srl	$6,$19,25
-	sll	$2,$19,7
-	addu	$23,$3,$10
-	or	$2,$2,$6
-	addu	$19,$2,$20
-	srl	$9,$23,21
-	srl	$8,$21,22
-	srl	$7,$fp,22
-	sll	$3,$23,11
-	sll	$6,$21,10
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$21,$6,$8
-	or	$3,$3,$9
-	nor	$2,$0,$19
-	addu	$23,$3,$22
-	and	$2,$2,$21
-	and	$3,$19,$25
-	nor	$6,$0,$fp
-	lw	$8,36($sp)
-	and	$6,$6,$18
-	or	$3,$3,$2
-	and	$2,$23,$fp
-	or	$2,$2,$6
-	addu	$3,$3,$16
-	addu	$3,$3,$20
-	addu	$2,$2,$8
-	addu	$20,$3,$11
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$20,17
-	sll	$6,$20,15
-	or	$6,$6,$3
-	srl	$8,$22,25
-	srl	$7,$18,22
-	sll	$3,$22,7
-	sll	$2,$18,10
-	or	$18,$2,$7
-	addu	$20,$6,$24
-	or	$3,$3,$8
-	srl	$7,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$7
-	addu	$22,$3,$17
-	nor	$6,$0,$20
-	nor	$7,$0,$18
-	and	$6,$6,$25
-	and	$7,$7,$23
-	and	$2,$20,$19
-	and	$3,$22,$18
-	or	$2,$2,$6
-	or	$3,$3,$7
-	lw	$6,48($5)
-	lw	$7,48($sp)
-	addu	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$2,$2,$24
-	addu	$3,$3,$17
-	addu	$24,$2,$11
-	addu	$17,$3,$10
-	srl	$8,$24,25
-	srl	$9,$17,25
-	srl	$7,$23,22
-	sll	$3,$24,7
-	sll	$6,$17,7
-	sll	$2,$23,10
-	or	$23,$2,$7
-	or	$3,$3,$8
-	or	$6,$6,$9
-	addu	$24,$3,$21
-	addu	$17,$6,$fp
-	srl	$3,$19,22
-	nor	$7,$0,$23
-	sll	$2,$19,10
-	or	$19,$2,$3
-	and	$7,$7,$22
-	and	$3,$17,$23
-	nor	$6,$0,$24
-	lw	$8,0($5)
-	and	$6,$6,$19
-	and	$2,$24,$20
-	or	$3,$3,$7
-	or	$2,$2,$6
-	addu	$3,$3,$13
-	addu	$3,$3,$fp
-	addu	$2,$2,$8
-	addu	$fp,$3,$10
-	addu	$2,$2,$21
-	addu	$21,$2,$11
-	srl	$7,$fp,20
-	srl	$6,$22,22
-	sll	$3,$fp,12
-	sll	$2,$22,10
-	or	$22,$2,$6
-	or	$3,$3,$7
-	srl	$6,$21,20
-	sll	$2,$21,12
-	addu	$fp,$3,$18
-	or	$2,$2,$6
-	nor	$6,$0,$22
-	addu	$21,$2,$25
-	and	$6,$6,$17
-	and	$2,$fp,$22
-	srl	$7,$20,22
-	sll	$3,$20,10
-	or	$2,$2,$6
-	lw	$6,24($sp)
-	or	$20,$3,$7
-	nor	$3,$0,$21
-	lw	$7,36($5)
-	and	$3,$3,$20
-	addu	$2,$2,$6
-	and	$6,$21,$24
-	or	$6,$6,$3
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	addu	$6,$6,$7
-	srl	$8,$18,25
-	addu	$6,$6,$25
-	srl	$7,$17,22
-	sll	$3,$18,7
-	sll	$2,$17,10
-	or	$17,$2,$7
-	addu	$25,$6,$11
-	or	$3,$3,$8
-	addu	$18,$3,$23
-	srl	$7,$25,17
-	sll	$6,$25,15
-	nor	$2,$0,$17
-	or	$6,$6,$7
-	and	$2,$2,$fp
-	and	$3,$18,$17
-	addu	$25,$6,$19
-	lw	$8,4($sp)
-	or	$3,$3,$2
-	srl	$7,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$7
-	nor	$2,$0,$25
-	and	$2,$2,$24
-	and	$6,$25,$21
-	addu	$3,$3,$8
-	addu	$3,$3,$23
-	or	$6,$6,$2
-	lw	$2,20($5)
-	addu	$23,$3,$10
-	srl	$8,$23,26
-	addu	$6,$6,$2
-	srl	$7,$fp,22
-	sll	$3,$23,6
-	sll	$2,$fp,10
-	or	$fp,$2,$7
-	or	$3,$3,$8
-	addu	$23,$3,$22
-	addu	$6,$6,$19
-	nor	$7,$0,$fp
-	addu	$19,$6,$11
-	and	$7,$7,$18
-	and	$3,$23,$fp
-	srl	$6,$19,23
-	sll	$2,$19,9
-	or	$3,$3,$7
-	lw	$7,16($sp)
-	or	$2,$2,$6
-	addu	$19,$2,$20
-	srl	$6,$21,22
-	addu	$3,$3,$7
-	sll	$2,$21,10
-	or	$21,$2,$6
-	addu	$3,$3,$22
-	nor	$2,$0,$19
-	addu	$22,$3,$10
-	and	$2,$2,$21
-	and	$3,$19,$25
-	srl	$8,$22,17
-	or	$3,$3,$2
-	srl	$6,$18,22
-	sll	$7,$22,15
-	sll	$2,$18,10
-	or	$18,$2,$6
-	or	$7,$7,$8
-	lw	$8,0($sp)
-	addu	$22,$7,$17
-	nor	$6,$0,$18
-	and	$6,$6,$23
-	and	$2,$22,$18
-	addu	$3,$3,$8
-	addu	$3,$3,$20
-	or	$2,$2,$6
-	lw	$6,40($sp)
-	addu	$20,$3,$11
-	srl	$7,$20,21
-	sll	$3,$20,11
-	addu	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$17
-	addu	$20,$3,$24
-	addu	$17,$2,$10
-	srl	$6,$25,22
-	sll	$3,$25,10
-	or	$25,$3,$6
-	srl	$9,$17,19
-	nor	$7,$0,$20
-	srl	$8,$23,22
-	sll	$3,$17,13
-	sll	$2,$23,10
-	or	$23,$2,$8
-	and	$7,$7,$25
-	and	$6,$20,$19
-	or	$3,$3,$9
-	addu	$17,$3,$fp
-	or	$6,$6,$7
-	nor	$3,$0,$23
-	lw	$7,56($5)
-	lw	$8,28($sp)
-	and	$3,$3,$22
-	and	$2,$17,$23
-	addu	$6,$6,$7
-	or	$2,$2,$3
-	addu	$6,$6,$24
-	addu	$2,$2,$8
-	addu	$24,$6,$11
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$7,$24,25
-	sll	$3,$24,7
-	srl	$6,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$6
-	or	$3,$3,$7
-	sll	$6,$fp,11
-	srl	$7,$fp,21
-	addu	$24,$3,$21
-	or	$6,$6,$7
-	addu	$fp,$6,$18
-	nor	$3,$0,$24
-	srl	$7,$22,22
-	sll	$6,$22,10
-	or	$22,$6,$7
-	and	$3,$3,$19
-	lw	$6,44($5)
-	and	$2,$24,$20
-	or	$2,$2,$3
-	nor	$3,$0,$17
-	lw	$7,48($sp)
-	or	$3,$3,$fp
-	addu	$2,$2,$6
-	addu	$2,$2,$21
-	xor	$3,$3,$22
-	addu	$21,$2,$11
-	addu	$3,$3,$7
-	li	$10,1836056576			# 0x6d700000
-	ori	$10,$10,0x3ef3
-	srl	$6,$21,19
-	addu	$3,$3,$18
-	sll	$2,$21,13
-	addu	$18,$3,$10
-	or	$2,$2,$6
-	addu	$21,$2,$25
-	srl	$8,$18,23
-	srl	$6,$20,22
-	sll	$3,$18,9
-	sll	$2,$20,10
-	or	$20,$2,$6
-	or	$3,$3,$8
-	nor	$7,$0,$21
-	addu	$18,$3,$23
-	and	$8,$7,$20
-	and	$3,$21,$24
-	srl	$9,$17,22
-	nor	$2,$0,$fp
-	sll	$6,$17,10
-	or	$17,$6,$9
-	or	$3,$3,$8
-	lw	$6,12($sp)
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$3,$3,$13
-	addu	$3,$3,$25
-	addu	$2,$2,$6
-	addu	$25,$3,$11
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,20
-	sll	$2,$25,12
-	or	$2,$2,$3
-	srl	$6,$23,25
-	sll	$3,$23,7
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	sll	$2,$24,10
-	srl	$6,$24,22
-	addu	$23,$3,$22
-	or	$24,$2,$6
-	or	$7,$7,$25
-	srl	$6,$fp,22
-	nor	$2,$0,$18
-	sll	$3,$fp,10
-	or	$fp,$3,$6
-	xor	$7,$7,$24
-	lw	$3,40($sp)
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$7,$7,$16
-	li	$9,1859715072			# 0x6ed90000
-	ori	$9,$9,0xeba1
-	addu	$7,$7,$19
-	addu	$2,$2,$3
-	addu	$19,$7,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,21
-	sll	$2,$19,11
-	or	$2,$2,$3
-	srl	$6,$22,17
-	sll	$3,$22,15
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	nor	$6,$0,$25
-	srl	$7,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$7
-	or	$6,$6,$19
-	lw	$7,40($5)
-	nor	$2,$0,$23
-	xor	$6,$6,$21
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$7
-	addu	$6,$6,$20
-	addu	$2,$2,$16
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,19
-	sll	$2,$20,13
-	or	$2,$2,$3
-	srl	$6,$17,21
-	sll	$3,$17,11
-	addu	$20,$2,$24
-	or	$3,$3,$6
-	srl	$7,$25,22
-	nor	$6,$0,$19
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	lw	$8,56($5)
-	or	$6,$6,$20
-	srl	$7,$23,22
-	nor	$2,$0,$22
-	sll	$3,$23,10
-	or	$23,$3,$7
-	xor	$6,$6,$25
-	lw	$3,20($sp)
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$8
-	addu	$6,$6,$24
-	addu	$2,$2,$3
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,26
-	sll	$2,$24,6
-	or	$2,$2,$3
-	srl	$6,$fp,24
-	sll	$3,$fp,8
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$7
-	or	$6,$6,$24
-	lw	$7,16($5)
-	nor	$2,$0,$17
-	xor	$6,$6,$19
-	or	$2,$2,$fp
-	xor	$2,$2,$22
-	addu	$6,$6,$7
-	addu	$6,$6,$21
-	addu	$2,$2,$8
-	addu	$21,$6,$9
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	srl	$3,$21,25
-	sll	$2,$21,7
-	or	$2,$2,$3
-	srl	$6,$18,26
-	sll	$3,$18,6
-	addu	$21,$2,$25
-	or	$3,$3,$6
-	srl	$7,$20,22
-	sll	$2,$20,10
-	addu	$18,$3,$23
-	or	$20,$2,$7
-	nor	$6,$0,$24
-	srl	$7,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$7
-	or	$6,$6,$21
-	lw	$3,36($5)
-	nor	$2,$0,$fp
-	xor	$6,$6,$20
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$6,$6,$3
-	addu	$6,$6,$25
-	addu	$2,$2,$12
-	addu	$25,$6,$9
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,18
-	sll	$2,$25,14
-	or	$2,$2,$3
-	srl	$6,$23,26
-	sll	$3,$23,6
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$3,$22
-	or	$24,$2,$7
-	nor	$6,$0,$21
-	srl	$7,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$7
-	or	$6,$6,$25
-	lw	$7,60($5)
-	nor	$2,$0,$18
-	lw	$8,16($sp)
-	xor	$6,$6,$24
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$6,$6,$7
-	addu	$6,$6,$19
-	addu	$2,$2,$8
-	addu	$19,$6,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,23
-	sll	$2,$19,9
-	or	$2,$2,$3
-	srl	$6,$22,18
-	sll	$3,$22,14
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	nor	$6,$0,$25
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	or	$6,$6,$19
-	srl	$7,$18,22
-	nor	$2,$0,$23
-	sll	$3,$18,10
-	or	$18,$3,$7
-	xor	$6,$6,$21
-	lw	$7,44($sp)
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$13
-	addu	$6,$6,$20
-	addu	$2,$2,$7
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,19
-	sll	$2,$20,13
-	or	$2,$2,$3
-	srl	$6,$17,20
-	sll	$3,$17,12
-	addu	$20,$2,$24
-	or	$3,$3,$6
-	srl	$7,$25,22
-	nor	$6,$0,$19
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	lw	$8,4($5)
-	or	$6,$6,$20
-	srl	$7,$23,22
-	nor	$2,$0,$22
-	sll	$3,$23,10
-	or	$23,$3,$7
-	xor	$6,$6,$25
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$8
-	addu	$6,$6,$24
-	addu	$2,$2,$13
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,17
-	sll	$2,$24,15
-	or	$2,$2,$3
-	srl	$6,$fp,19
-	sll	$3,$fp,13
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$7
-	or	$6,$6,$24
-	lw	$3,0($sp)
-	nor	$2,$0,$17
-	lw	$7,24($sp)
-	xor	$6,$6,$19
-	or	$2,$2,$fp
-	xor	$2,$2,$22
-	addu	$6,$6,$3
-	addu	$6,$6,$21
-	addu	$2,$2,$7
-	addu	$21,$6,$9
-	addu	$2,$2,$18
-	addu	$18,$2,$10
-	srl	$3,$21,18
-	sll	$2,$21,14
-	or	$2,$2,$3
-	srl	$6,$18,27
-	sll	$3,$18,5
-	addu	$21,$2,$25
-	or	$3,$3,$6
-	srl	$7,$20,22
-	nor	$6,$0,$24
-	sll	$2,$20,10
-	addu	$18,$3,$23
-	or	$20,$2,$7
-	lw	$8,28($5)
-	or	$6,$6,$21
-	srl	$7,$17,22
-	nor	$2,$0,$fp
-	sll	$3,$17,10
-	or	$17,$3,$7
-	xor	$6,$6,$20
-	lw	$3,28($sp)
-	or	$2,$2,$18
-	xor	$2,$2,$17
-	addu	$6,$6,$8
-	addu	$6,$6,$25
-	addu	$2,$2,$3
-	addu	$25,$6,$9
-	addu	$2,$2,$23
-	addu	$23,$2,$10
-	srl	$3,$25,24
-	sll	$2,$25,8
-	or	$2,$2,$3
-	srl	$6,$23,18
-	sll	$3,$23,14
-	addu	$25,$2,$19
-	or	$3,$3,$6
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$3,$22
-	or	$24,$2,$7
-	nor	$6,$0,$21
-	srl	$7,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$7
-	or	$6,$6,$25
-	lw	$7,0($5)
-	nor	$2,$0,$18
-	lw	$8,32($sp)
-	xor	$6,$6,$24
-	or	$2,$2,$23
-	xor	$2,$2,$fp
-	addu	$6,$6,$7
-	addu	$6,$6,$19
-	addu	$2,$2,$8
-	addu	$19,$6,$9
-	addu	$2,$2,$22
-	addu	$22,$2,$10
-	srl	$3,$19,19
-	sll	$2,$19,13
-	or	$2,$2,$3
-	srl	$6,$22,19
-	sll	$3,$22,13
-	addu	$19,$2,$20
-	or	$3,$3,$6
-	srl	$7,$21,22
-	nor	$6,$0,$25
-	sll	$2,$21,10
-	addu	$22,$3,$17
-	or	$21,$2,$7
-	or	$6,$6,$19
-	srl	$7,$18,22
-	nor	$2,$0,$23
-	sll	$3,$18,10
-	or	$18,$3,$7
-	xor	$6,$6,$21
-	lw	$7,8($sp)
-	or	$2,$2,$22
-	xor	$2,$2,$18
-	addu	$6,$6,$12
-	addu	$6,$6,$20
-	addu	$2,$2,$7
-	addu	$20,$6,$9
-	addu	$2,$2,$17
-	addu	$17,$2,$10
-	srl	$3,$20,26
-	sll	$2,$20,6
-	or	$2,$2,$3
-	srl	$6,$17,19
-	sll	$3,$17,13
-	addu	$20,$2,$24
-	lw	$8,16($5)
-	or	$3,$3,$6
-	srl	$7,$25,22
-	sll	$2,$25,10
-	addu	$17,$3,$fp
-	or	$25,$2,$7
-	nor	$6,$0,$19
-	srl	$7,$23,22
-	sll	$3,$23,10
-	sw	$8,56($sp)
-	or	$23,$3,$7
-	or	$6,$6,$20
-	lw	$3,52($5)
-	nor	$2,$0,$22
-	xor	$6,$6,$25
-	or	$2,$2,$17
-	xor	$2,$2,$23
-	addu	$6,$6,$3
-	addu	$6,$6,$24
-	addu	$2,$2,$8
-	addu	$24,$6,$9
-	addu	$2,$2,$fp
-	addu	$fp,$2,$10
-	srl	$3,$24,27
-	sll	$2,$24,5
-	or	$2,$2,$3
-	srl	$6,$fp,25
-	sll	$3,$fp,7
-	addu	$24,$2,$21
-	or	$3,$3,$6
-	srl	$7,$19,22
-	sll	$2,$19,10
-	addu	$fp,$3,$18
-	or	$19,$2,$7
-	nor	$6,$0,$20
-	srl	$7,$22,22
-	nor	$2,$0,$17
-	sll	$3,$22,10
-	or	$22,$3,$7
-	lw	$8,52($sp)
-	lw	$7,44($5)
-	or	$6,$6,$24
-	or	$2,$2,$fp
-	xor	$6,$6,$19
-	xor	$2,$2,$22
-	addu	$6,$6,$7
-	addu	$2,$2,$8
-	addu	$6,$6,$21
-	addu	$2,$2,$18
-	addu	$21,$6,$9
-	addu	$18,$2,$10
-	srl	$3,$21,20
-	srl	$7,$18,27
-	sll	$2,$21,12
-	sll	$6,$18,5
-	or	$2,$2,$3
-	or	$6,$6,$7
-	sll	$3,$20,10
-	srl	$7,$20,22
-	addu	$18,$6,$23
-	addu	$21,$2,$25
-	or	$20,$3,$7
-	nor	$2,$0,$24
-	srl	$6,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$6
-	or	$2,$2,$21
-	lw	$3,20($5)
-	xor	$2,$2,$20
-	nor	$6,$0,$18
-	and	$6,$6,$17
-	addu	$2,$2,$3
-	and	$3,$18,$fp
-	or	$3,$3,$6
-	addu	$2,$2,$25
-	addu	$3,$3,$13
-	li	$11,2053963776			# 0x7a6d0000
-	ori	$11,$11,0x76e9
-	addu	$25,$2,$9
-	addu	$3,$3,$23
-	addu	$23,$3,$11
-	srl	$6,$25,25
-	sll	$2,$25,7
-	or	$2,$2,$6
-	srl	$8,$23,17
-	sll	$6,$23,15
-	addu	$25,$2,$19
-	or	$6,$6,$8
-	srl	$7,$24,22
-	sll	$2,$24,10
-	addu	$23,$6,$22
-	or	$24,$2,$7
-	nor	$3,$0,$21
-	srl	$6,$fp,22
-	sll	$2,$fp,10
-	or	$fp,$2,$6
-	or	$3,$3,$25
-	lw	$6,48($5)
-	xor	$3,$3,$24
-	addu	$3,$3,$6
-	nor	$6,$0,$23
-	and	$6,$6,$fp
-	and	$2,$23,$18
-	addu	$3,$3,$19
-	or	$2,$2,$6
-	addu	$19,$3,$9
-	addu	$2,$2,$12
-	srl	$8,$19,27
-	srl	$7,$21,22
-	sll	$6,$19,5
-	sll	$3,$21,10
-	addu	$2,$2,$22
-	or	$21,$3,$7
-	or	$6,$6,$8
-	addu	$22,$2,$11
-	addu	$19,$6,$20
-	srl	$7,$22,27
-	nor	$6,$0,$21
-	sll	$2,$22,5
-	and	$6,$6,$25
-	and	$3,$19,$21
-	or	$2,$2,$7
-	lw	$7,4($5)
-	or	$3,$3,$6
-	addu	$22,$2,$17
-	addu	$3,$3,$7
-	srl	$6,$18,22
-	sll	$2,$18,10
-	li	$10,-1894055936			# 0xffffffff8f1b0000
-	ori	$10,$10,0xbcdc
-	or	$18,$2,$6
-	addu	$3,$3,$20
-	nor	$2,$0,$22
-	addu	$20,$3,$10
-	and	$2,$2,$18
-	and	$3,$22,$23
-	srl	$8,$20,21
-	or	$3,$3,$2
-	srl	$6,$25,22
-	sll	$7,$20,11
-	sll	$2,$25,10
-	or	$25,$2,$6
-	or	$7,$7,$8
-	lw	$8,56($sp)
-	addu	$20,$7,$24
-	nor	$6,$0,$25
-	and	$6,$6,$19
-	and	$2,$20,$25
-	addu	$3,$3,$8
-	addu	$3,$3,$17
-	or	$2,$2,$6
-	lw	$6,36($5)
-	addu	$17,$3,$11
-	srl	$7,$17,24
-	sll	$3,$17,8
-	addu	$2,$2,$6
-	or	$3,$3,$7
-	addu	$2,$2,$24
-	addu	$17,$3,$fp
-	addu	$24,$2,$10
-	srl	$6,$23,22
-	lw	$2,4($5)
-	sll	$3,$23,10
-	or	$23,$3,$6
-	srl	$9,$24,20
-	sll	$3,$24,12
-	sw	$2,60($sp)
-	or	$3,$3,$9
-	nor	$7,$0,$17
-	addu	$24,$3,$21
-	and	$7,$7,$23
-	lw	$3,60($sp)
-	and	$6,$17,$22
-	srl	$8,$19,22
-	sll	$2,$19,10
-	or	$6,$6,$7
-	or	$19,$2,$8
-	addu	$6,$6,$3
-	addu	$6,$6,$fp
-	nor	$3,$0,$19
-	addu	$fp,$6,$11
-	and	$3,$3,$20
-	lw	$6,44($5)
-	and	$2,$24,$19
-	or	$2,$2,$3
-	addu	$2,$2,$6
-	sll	$3,$fp,11
-	srl	$6,$fp,21
-	or	$3,$3,$6
-	addu	$2,$2,$21
-	addu	$fp,$3,$18
-	addu	$21,$2,$10
-	srl	$3,$22,22
-	sll	$2,$22,10
-	or	$22,$2,$3
-	srl	$8,$21,18
-	srl	$6,$20,22
-	sll	$7,$21,14
-	nor	$3,$0,$fp
-	sll	$2,$20,10
-	or	$20,$2,$6
-	or	$7,$7,$8
-	and	$3,$3,$22
-	and	$2,$fp,$17
-	addu	$21,$7,$25
-	or	$2,$2,$3
-	nor	$6,$0,$20
-	lw	$7,40($5)
-	and	$6,$6,$24
-	and	$3,$21,$20
-	addu	$2,$2,$16
-	or	$3,$3,$6
-	addu	$2,$2,$18
-	addu	$18,$2,$11
-	addu	$3,$3,$7
-	srl	$6,$18,18
-	addu	$3,$3,$25
-	sll	$2,$18,14
-	addu	$25,$3,$10
-	or	$2,$2,$6
-	addu	$18,$2,$23
-	srl	$9,$25,17
-	srl	$7,$24,22
-	srl	$8,$17,22
-	sll	$3,$25,15
-	sll	$2,$24,10
-	sll	$6,$17,10
-	or	$24,$2,$7
-	or	$17,$6,$8
-	or	$3,$3,$9
-	nor	$2,$0,$18
-	addu	$25,$3,$19
-	and	$2,$2,$17
-	and	$3,$18,$fp
-	nor	$6,$0,$24
-	lw	$8,44($sp)
-	and	$6,$6,$21
-	or	$3,$3,$2
-	and	$2,$25,$24
-	or	$2,$2,$6
-	lw	$6,0($5)
-	addu	$3,$3,$8
-	addu	$3,$3,$23
-	addu	$2,$2,$6
-	addu	$23,$3,$11
-	addu	$2,$2,$19
-	addu	$19,$2,$10
-	srl	$3,$23,18
-	sll	$6,$23,14
-	or	$6,$6,$3
-	srl	$8,$19,18
-	srl	$7,$21,22
-	sll	$3,$19,14
-	sll	$2,$21,10
-	addu	$23,$6,$22
-	or	$21,$2,$7
-	or	$3,$3,$8
-	srl	$7,$fp,22
-	sll	$2,$fp,10
-	addu	$19,$3,$20
-	or	$fp,$2,$7
-	nor	$6,$0,$21
-	nor	$7,$0,$23
-	lw	$8,48($sp)
-	and	$6,$6,$25
-	and	$7,$7,$fp
-	and	$2,$19,$21
-	and	$3,$23,$18
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$13
-	addu	$2,$2,$20
-	addu	$3,$3,$22
-	addu	$20,$2,$10
-	addu	$22,$3,$11
-	srl	$8,$20,17
-	srl	$9,$22,26
-	srl	$7,$25,22
-	sll	$6,$20,15
-	sll	$3,$22,6
-	sll	$2,$25,10
-	or	$25,$2,$7
-	or	$6,$6,$8
-	or	$3,$3,$9
-	addu	$22,$3,$17
-	addu	$20,$6,$24
-	srl	$3,$18,22
-	nor	$7,$0,$25
-	sll	$2,$18,10
-	or	$18,$2,$3
-	lw	$8,48($5)
-	and	$7,$7,$19
-	and	$3,$20,$25
-	nor	$6,$0,$22
-	and	$6,$6,$18
-	and	$2,$22,$23
-	or	$3,$3,$7
-	lw	$7,0($5)
-	or	$2,$2,$6
-	addu	$3,$3,$8
-	addu	$3,$3,$24
-	addu	$2,$2,$7
-	addu	$24,$3,$10
-	addu	$2,$2,$17
-	addu	$17,$2,$11
-	sw	$7,64($sp)
-	srl	$6,$19,22
-	srl	$7,$24,23
-	sll	$3,$24,9
-	sll	$2,$19,10
-	or	$19,$2,$6
-	or	$3,$3,$7
-	srl	$6,$17,18
-	sll	$2,$17,14
-	addu	$24,$3,$21
-	or	$2,$2,$6
-	nor	$7,$0,$19
-	srl	$6,$23,22
-	sll	$3,$23,10
-	addu	$17,$2,$fp
-	or	$23,$3,$6
-	and	$7,$7,$20
-	lw	$3,16($5)
-	and	$2,$24,$19
-	or	$2,$2,$7
-	nor	$6,$0,$17
-	lw	$15,20($5)
-	and	$6,$6,$23
-	addu	$2,$2,$3
-	and	$3,$17,$22
-	addu	$2,$2,$21
-	or	$3,$3,$6
-	addu	$21,$2,$10
-	addu	$3,$3,$15
-	srl	$8,$21,24
-	addu	$3,$3,$fp
-	srl	$7,$20,22
-	sll	$6,$21,8
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$6,$6,$8
-	addu	$fp,$3,$11
-	addu	$21,$6,$25
-	srl	$3,$fp,26
-	nor	$2,$0,$20
-	sll	$6,$fp,6
-	or	$6,$6,$3
-	and	$2,$2,$24
-	and	$3,$21,$20
-	or	$3,$3,$2
-	srl	$7,$22,22
-	sll	$2,$22,10
-	addu	$fp,$6,$18
-	or	$22,$2,$7
-	lw	$6,52($5)
-	lw	$7,48($5)
-	nor	$2,$0,$fp
-	sw	$7,68($sp)
-	and	$2,$2,$22
-	addu	$3,$3,$6
-	and	$6,$fp,$17
-	addu	$3,$3,$25
-	or	$6,$6,$2
-	lw	$2,68($sp)
-	addu	$25,$3,$10
-	srl	$8,$25,23
-	srl	$7,$24,22
-	addu	$6,$6,$2
-	sll	$3,$25,9
-	sll	$2,$24,10
-	or	$24,$2,$7
-	or	$3,$3,$8
-	addu	$6,$6,$18
-	addu	$25,$3,$19
-	addu	$18,$6,$11
-	nor	$7,$0,$24
-	and	$7,$7,$21
-	srl	$6,$18,23
-	and	$2,$25,$24
-	sll	$3,$18,9
-	or	$3,$3,$6
-	or	$2,$2,$7
-	addu	$18,$3,$23
-	addu	$2,$2,$16
-	srl	$6,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$6
-	addu	$2,$2,$19
-	nor	$3,$0,$18
-	addu	$19,$2,$10
-	and	$3,$3,$17
-	and	$6,$18,$fp
-	lw	$14,8($5)
-	srl	$8,$19,18
-	or	$6,$6,$3
-	sll	$7,$19,14
-	srl	$3,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$3
-	or	$7,$7,$8
-	addu	$19,$7,$20
-	nor	$3,$0,$21
-	addu	$6,$6,$14
-	lw	$7,28($5)
-	and	$3,$3,$25
-	and	$2,$19,$21
-	addu	$6,$6,$23
-	addu	$23,$6,$11
-	or	$2,$2,$3
-	srl	$6,$23,20
-	sll	$3,$23,12
-	addu	$2,$2,$7
-	or	$3,$3,$6
-	addu	$2,$2,$20
-	addu	$23,$3,$22
-	addu	$20,$2,$10
-	srl	$6,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$6
-	srl	$9,$20,27
-	nor	$7,$0,$23
-	srl	$8,$25,22
-	sll	$3,$20,5
-	sll	$2,$25,10
-	or	$25,$2,$8
-	and	$7,$7,$fp
-	lw	$8,52($sp)
-	and	$6,$23,$18
-	or	$3,$3,$9
-	addu	$20,$3,$24
-	or	$6,$6,$7
-	nor	$3,$0,$25
-	and	$3,$3,$19
-	and	$2,$20,$25
-	addu	$6,$6,$8
-	addu	$6,$6,$22
-	or	$2,$2,$3
-	lw	$3,60($5)
-	addu	$22,$6,$11
-	srl	$6,$22,23
-	addu	$2,$2,$3
-	sll	$3,$22,9
-	or	$3,$3,$6
-	addu	$2,$2,$24
-	addu	$22,$3,$17
-	addu	$24,$2,$10
-	srl	$3,$18,22
-	sll	$2,$18,10
-	or	$18,$2,$3
-	srl	$8,$24,26
-	srl	$3,$19,22
-	sll	$7,$24,6
-	nor	$6,$0,$22
-	sll	$2,$19,10
-	or	$19,$2,$3
-	or	$7,$7,$8
-	and	$6,$6,$18
-	lw	$8,36($5)
-	and	$3,$22,$23
-	or	$3,$3,$6
-	addu	$3,$3,$8
-	addu	$24,$7,$21
-	nor	$6,$0,$19
-	addu	$3,$3,$17
-	addu	$17,$3,$11
-	and	$6,$6,$20
-	lw	$3,56($5)
-	and	$2,$24,$19
-	or	$2,$2,$6
-	addu	$2,$2,$3
-	srl	$6,$17,20
-	addu	$2,$2,$21
-	sll	$3,$17,12
-	addu	$21,$2,$10
-	sw	$8,72($sp)
-	or	$3,$3,$6
-	srl	$8,$23,22
-	sll	$6,$23,10
-	addu	$17,$3,$fp
-	or	$23,$6,$8
-	srl	$9,$21,24
-	lw	$6,28($5)
-	srl	$7,$20,22
-	sll	$3,$21,8
-	sll	$2,$20,10
-	or	$20,$2,$7
-	or	$3,$3,$9
-	nor	$2,$0,$17
-	sw	$6,76($sp)
-	addu	$21,$3,$25
-	lw	$7,76($sp)
-	and	$2,$2,$23
-	and	$3,$17,$22
-	nor	$6,$0,$20
-	and	$6,$6,$24
-	or	$3,$3,$2
-	and	$2,$21,$20
-	or	$2,$2,$6
-	addu	$3,$3,$7
-	addu	$3,$3,$fp
-	addu	$2,$2,$15
-	addu	$fp,$3,$11
-	addu	$2,$2,$25
-	addu	$25,$2,$10
-	srl	$3,$fp,27
-	sll	$6,$fp,5
-	or	$6,$6,$3
-	srl	$8,$25,26
-	srl	$7,$24,22
-	sll	$3,$25,6
-	sll	$2,$24,10
-	addu	$fp,$6,$18
-	or	$24,$2,$7
-	or	$3,$3,$8
-	srl	$7,$22,22
-	sll	$2,$22,10
-	addu	$25,$3,$19
-	or	$22,$2,$7
-	nor	$6,$0,$24
-	nor	$7,$0,$fp
-	lw	$8,40($5)
-	and	$6,$6,$21
-	and	$7,$7,$22
-	and	$2,$25,$24
-	and	$3,$fp,$17
-	or	$2,$2,$6
-	or	$3,$3,$7
-	addu	$3,$3,$8
-	addu	$2,$2,$12
-	addu	$2,$2,$19
-	addu	$3,$3,$18
-	addu	$19,$2,$10
-	addu	$18,$3,$11
-	sw	$8,80($sp)
-	srl	$9,$18,17
-	srl	$8,$19,27
-	srl	$7,$21,22
-	sll	$6,$19,5
-	sll	$3,$18,15
-	sll	$2,$21,10
-	or	$21,$2,$7
-	or	$6,$6,$8
-	or	$3,$3,$9
-	addu	$18,$3,$23
-	addu	$19,$6,$20
-	srl	$7,$17,22
-	nor	$3,$0,$21
-	sll	$2,$17,10
-	or	$17,$2,$7
-	and	$3,$3,$25
-	and	$2,$19,$21
-	nor	$6,$0,$18
-	lw	$7,56($5)
-	and	$6,$6,$17
-	or	$2,$2,$3
-	and	$3,$18,$fp
-	or	$3,$3,$6
-	addu	$2,$2,$14
-	addu	$2,$2,$20
-	addu	$3,$3,$7
-	addu	$20,$2,$10
-	addu	$3,$3,$23
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	addu	$23,$3,$11
-	srl	$2,$20,20
-	sll	$5,$20,12
-	or	$5,$5,$2
-	srl	$6,$23,24
-	sll	$2,$23,8
-	or	$2,$2,$6
-	addu	$20,$5,$24
-	addu	$23,$2,$22
-	nor	$3,$0,$25
-	srl	$5,$fp,22
-	sll	$2,$fp,10
-	or	$fp,$2,$5
-	or	$3,$3,$19
-	lw	$2,4($sp)
-	lw	$6,68($sp)
-	xor	$5,$23,$18
-	xor	$3,$3,$20
-	addu	$3,$3,$2
-	xor	$5,$5,$fp
-	li	$8,-1454178304			# 0xffffffffa9530000
-	ori	$8,$8,0xfd4e
-	addu	$5,$5,$6
-	addu	$3,$3,$24
-	addu	$24,$3,$8
-	addu	$22,$22,$5
-	srl	$6,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$6
-	sll	$5,$24,9
-	srl	$2,$24,23
-	srl	$6,$22,24
-	sll	$3,$22,8
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	nor	$2,$0,$19
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	or	$2,$2,$20
-	lw	$3,8($sp)
-	xor	$2,$2,$24
-	lw	$5,48($sp)
-	addu	$2,$2,$3
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$3,$3,$5
-	addu	$2,$2,$21
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,27
-	srl	$2,$21,17
-	sll	$5,$21,15
-	sll	$3,$17,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$20
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	or	$2,$2,$24
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	xor	$2,$2,$21
-	lw	$5,80($sp)
-	xor	$3,$17,$22
-	xor	$3,$3,$23
-	addu	$2,$2,$15
-	addu	$3,$3,$5
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,20
-	srl	$2,$25,27
-	sll	$5,$25,5
-	sll	$3,$fp,12
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	lw	$6,16($sp)
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	lw	$5,56($sp)
-	xor	$3,$fp,$17
-	addu	$2,$2,$6
-	xor	$3,$3,$22
-	addu	$3,$3,$5
-	addu	$2,$2,$19
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,23
-	srl	$2,$19,21
-	sll	$5,$19,11
-	sll	$3,$18,9
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$21
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	lw	$6,20($sp)
-	or	$2,$2,$25
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	xor	$2,$2,$19
-	lw	$5,60($sp)
-	xor	$3,$18,$fp
-	addu	$2,$2,$6
-	xor	$3,$3,$17
-	addu	$3,$3,$5
-	addu	$2,$2,$20
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$6,$23,20
-	srl	$2,$20,26
-	sll	$5,$20,6
-	sll	$3,$23,12
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$25
-	addu	$20,$5,$24
-	addu	$23,$3,$22
-	lw	$6,24($sp)
-	or	$2,$2,$19
-	srl	$5,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$5
-	xor	$2,$2,$20
-	xor	$3,$23,$18
-	addu	$2,$2,$6
-	xor	$3,$3,$fp
-	addu	$2,$2,$24
-	addu	$3,$3,$15
-	addu	$24,$2,$8
-	addu	$22,$22,$3
-	srl	$5,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$5
-	srl	$6,$22,27
-	srl	$2,$24,24
-	sll	$5,$24,8
-	sll	$3,$22,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$19
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	or	$2,$2,$20
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	xor	$2,$2,$24
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$2,$2,$14
-	addu	$2,$2,$21
-	addu	$3,$3,$13
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,18
-	srl	$2,$21,19
-	sll	$5,$21,13
-	sll	$3,$17,14
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	nor	$2,$0,$20
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	or	$2,$2,$24
-	lw	$5,32($sp)
-	lw	$6,76($sp)
-	xor	$3,$17,$22
-	xor	$2,$2,$21
-	addu	$2,$2,$5
-	xor	$3,$3,$23
-	addu	$3,$3,$6
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,26
-	srl	$2,$25,20
-	sll	$5,$25,12
-	sll	$3,$fp,6
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	xor	$3,$fp,$17
-	addu	$2,$2,$7
-	xor	$3,$3,$22
-	addu	$2,$2,$19
-	addu	$3,$3,$12
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,24
-	srl	$2,$19,27
-	sll	$5,$19,5
-	sll	$3,$18,8
-	or	$5,$5,$2
-	or	$3,$3,$6
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	nor	$2,$0,$21
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	or	$2,$2,$25
-	lw	$5,40($sp)
-	xor	$3,$18,$fp
-	xor	$2,$2,$19
-	addu	$2,$2,$5
-	xor	$3,$3,$17
-	addu	$2,$2,$20
-	addu	$3,$3,$14
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$6,$23,19
-	srl	$2,$20,20
-	sll	$5,$20,12
-	sll	$3,$23,13
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$25
-	addu	$20,$5,$24
-	addu	$23,$3,$22
-	or	$2,$2,$19
-	srl	$5,$fp,22
-	sll	$3,$fp,10
-	or	$fp,$3,$5
-	lw	$6,52($sp)
-	xor	$3,$23,$18
-	xor	$2,$2,$20
-	addu	$2,$2,$16
-	xor	$3,$3,$fp
-	addu	$3,$3,$6
-	addu	$2,$2,$24
-	addu	$24,$2,$8
-	addu	$22,$22,$3
-	srl	$5,$19,22
-	sll	$2,$19,10
-	or	$19,$2,$5
-	srl	$6,$22,26
-	srl	$2,$24,19
-	sll	$5,$24,13
-	sll	$3,$22,6
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$19
-	addu	$24,$5,$21
-	addu	$22,$3,$17
-	or	$2,$2,$20
-	srl	$5,$18,22
-	sll	$3,$18,10
-	or	$18,$3,$5
-	xor	$2,$2,$24
-	xor	$3,$22,$23
-	xor	$3,$3,$18
-	addu	$2,$2,$13
-	addu	$3,$3,$7
-	addu	$2,$2,$21
-	addu	$21,$2,$8
-	addu	$17,$17,$3
-	srl	$5,$20,22
-	sll	$2,$20,10
-	or	$20,$2,$5
-	srl	$6,$17,27
-	srl	$2,$21,18
-	sll	$5,$21,14
-	sll	$3,$17,5
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$20
-	addu	$21,$5,$25
-	addu	$17,$3,$fp
-	lw	$7,44($sp)
-	or	$2,$2,$24
-	srl	$5,$23,22
-	sll	$3,$23,10
-	or	$23,$3,$5
-	xor	$2,$2,$21
-	lw	$5,64($sp)
-	xor	$3,$17,$22
-	addu	$2,$2,$7
-	xor	$3,$3,$23
-	addu	$3,$3,$5
-	addu	$2,$2,$25
-	addu	$25,$2,$8
-	addu	$fp,$fp,$3
-	srl	$5,$24,22
-	sll	$2,$24,10
-	or	$24,$2,$5
-	srl	$6,$fp,17
-	srl	$2,$25,21
-	sll	$5,$25,11
-	sll	$3,$fp,15
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$24
-	addu	$25,$5,$19
-	addu	$fp,$3,$18
-	or	$2,$2,$21
-	srl	$5,$22,22
-	sll	$3,$22,10
-	or	$22,$3,$5
-	xor	$2,$2,$25
-	xor	$3,$fp,$17
-	xor	$3,$3,$22
-	addu	$2,$2,$12
-	addu	$3,$3,$16
-	addu	$2,$2,$19
-	addu	$19,$2,$8
-	addu	$18,$18,$3
-	srl	$5,$21,22
-	sll	$2,$21,10
-	or	$21,$2,$5
-	srl	$6,$18,19
-	srl	$2,$19,24
-	sll	$5,$19,8
-	sll	$3,$18,13
-	or	$5,$5,$2
-	or	$3,$3,$6
-	nor	$2,$0,$21
-	addu	$19,$5,$20
-	addu	$18,$3,$23
-	lw	$6,48($sp)
-	or	$2,$2,$25
-	srl	$5,$17,22
-	sll	$3,$17,10
-	or	$17,$3,$5
-	lw	$7,72($sp)
-	xor	$3,$18,$fp
-	xor	$2,$2,$19
-	addu	$2,$2,$6
-	xor	$3,$3,$17
-	addu	$3,$3,$7
-	addu	$2,$2,$20
-	addu	$20,$2,$8
-	addu	$23,$23,$3
-	srl	$5,$25,22
-	sll	$2,$25,10
-	or	$25,$2,$5
-	srl	$3,$20,27
-	srl	$6,$23,21
-	sll	$5,$20,5
-	sll	$2,$23,11
-	or	$5,$5,$3
-	or	$2,$2,$6
-	addu	$20,$5,$24
-	addu	$23,$2,$22
-	srl	$5,$fp,22
-	sll	$2,$fp,10
-	nor	$3,$0,$25
-	or	$fp,$2,$5
-	or	$3,$3,$19
-	lw	$2,52($sp)
-	xor	$3,$3,$20
-	addu	$3,$3,$2
-	addu	$3,$3,$24
-	addu	$24,$3,$8
-	xor	$2,$23,$18
-	lw	$3,44($sp)
-	lw	$6,8($4)
-	srl	$7,$19,22
-	sll	$5,$19,10
-	or	$19,$5,$7
-	xor	$2,$2,$fp
-	addu	$2,$2,$3
-	addu	$6,$6,$19
-	addu	$22,$22,$2
-	addu	$6,$6,$fp
-	srl	$2,$24,26
-	sll	$5,$24,6
-	srl	$3,$22,21
-	lw	$10,4($4)
-	lw	$7,12($4)
-	lw	$8,0($4)
-	or	$5,$5,$2
-	sll	$9,$22,11
-	sw	$6,4($4)
-	lw	$6,16($4)
-	or	$9,$9,$3
-	addu	$24,$5,$21
-	srl	$3,$18,22
-	sll	$2,$18,10
-	addu	$22,$9,$17
-	addu	$10,$10,$20
-	addu	$6,$6,$21
-	or	$18,$2,$3
-	addu	$7,$7,$25
-	addu	$8,$8,$24
-	addu	$18,$18,$10
-	addu	$7,$7,$17
-	addu	$6,$6,$22
-	addu	$8,$8,$23
-	sw	$18,0($4)
-	sw	$7,8($4)
-	sw	$6,12($4)
-	sw	$8,16($4)
-	lw	$fp,120($sp)
-	lw	$23,116($sp)
-	lw	$22,112($sp)
-	lw	$21,108($sp)
-	lw	$20,104($sp)
-	lw	$19,100($sp)
-	lw	$18,96($sp)
-	lw	$17,92($sp)
-	lw	$16,88($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,128
-	.set	macro
-	.set	reorder
-
-	.end	compress
-	.align	2
-	.globl	MDfinish
-	.ent	MDfinish
-MDfinish:
-	.frame	$sp,104,$31		# vars= 64, regs= 6/0, args= 16, gp= 0
-	.mask	0x801f0000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-104
-	sw	$17,84($sp)
-	addiu	$17,$sp,16
-	sw	$20,96($sp)
-	sw	$18,88($sp)
-	sw	$16,80($sp)
-	move	$18,$6
-	move	$20,$4
-	li	$6,64			# 0x40
-	move	$16,$5
-	move	$4,$17
-	move	$5,$0
-	sw	$19,92($sp)
-	sw	$31,100($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	move	$19,$7
-	.set	macro
-	.set	reorder
-
-	andi	$7,$18,0x3f
-	.set	noreorder
-	.set	nomacro
-	beq	$7,$0,$L10
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L7:
-	srl	$5,$6,2
-	sll	$5,$5,2
-	lbu	$4,0($16)
-	addu	$5,$5,$17
-	andi	$2,$6,0x3
-	sll	$2,$2,3
-	lw	$3,0($5)
-	sll	$4,$4,$2
-	addiu	$6,$6,1
-	xor	$3,$3,$4
-	sltu	$2,$6,$7
-	sw	$3,0($5)
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L7
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-$L10:
-	andi	$5,$18,0x3c
-	andi	$3,$18,0x3
-	addu	$5,$5,$17
-	sll	$3,$3,3
-	addiu	$3,$3,7
-	lw	$4,0($5)
-	li	$2,1			# 0x1
-	sll	$2,$2,$3
-	xor	$4,$4,$2
-	sltu	$3,$7,56
-	.set	noreorder
-	.set	nomacro
-	beq	$3,$0,$L12
-	sw	$4,0($5)
-	.set	macro
-	.set	reorder
-
-	sll	$3,$19,3
-	srl	$2,$18,29
-	or	$2,$2,$3
-	move	$4,$20
-	sll	$3,$18,3
-	move	$5,$17
-	sw	$3,72($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	sw	$2,76($sp)
-	.set	macro
-	.set	reorder
-
-	lw	$31,100($sp)
-	lw	$20,96($sp)
-	lw	$19,92($sp)
-	lw	$18,88($sp)
-	lw	$17,84($sp)
-	lw	$16,80($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,104
-	.set	macro
-	.set	reorder
-
-$L12:
-	move	$4,$20
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	move	$4,$17
-	move	$5,$0
-	.set	noreorder
-	.set	nomacro
-	jal	memset
-	li	$6,64			# 0x40
-	.set	macro
-	.set	reorder
-
-	sll	$3,$19,3
-	srl	$2,$18,29
-	or	$2,$2,$3
-	move	$4,$20
-	sll	$3,$18,3
-	move	$5,$17
-	sw	$3,72($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	sw	$2,76($sp)
-	.set	macro
-	.set	reorder
-
-	lw	$31,100($sp)
-	lw	$20,96($sp)
-	lw	$19,92($sp)
-	lw	$18,88($sp)
-	lw	$17,84($sp)
-	lw	$16,80($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,104
-	.set	macro
-	.set	reorder
-
-	.end	MDfinish
diff --git a/lib/CPUs/MIPS/sim/asm/rmd160_test.s b/lib/CPUs/MIPS/sim/asm/rmd160_test.s
deleted file mode 100644
index ec7382d..0000000
--- a/lib/CPUs/MIPS/sim/asm/rmd160_test.s
+++ /dev/null
@@ -1,556 +0,0 @@
-	.file	1 "rmd160_test.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L2
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L11
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L12:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L11:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L12
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L22:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L18
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L18:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L22
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L27:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L27
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
-
-	.lcomm	hashcode.0,20
-	.align	2
-	.globl	RMD
-	.ent	RMD
-RMD:
-	.frame	$sp,128,$31		# vars= 88, regs= 6/0, args= 16, gp= 0
-	.mask	0x801f0000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-128
-	sw	$16,104($sp)
-	move	$16,$4
-	addiu	$4,$sp,16
-	sw	$31,124($sp)
-	sw	$20,120($sp)
-	sw	$18,112($sp)
-	sw	$17,108($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	MDinit
-	sw	$19,116($sp)
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	strlen
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	move	$18,$2
-	sltu	$2,$2,64
-	move	$17,$18
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L44
-	addiu	$20,$sp,16
-	.set	macro
-	.set	reorder
-
-	addiu	$19,$sp,40
-	addiu	$5,$20,24
-$L50:
-	li	$11,15			# 0xf
-$L37:
-	lbu	$2,3($16)
-	lbu	$3,2($16)
-	lbu	$4,1($16)
-	sll	$3,$3,16
-	sll	$2,$2,24
-	or	$2,$2,$3
-	sll	$4,$4,8
-	lbu	$3,0($16)
-	or	$2,$2,$4
-	or	$2,$2,$3
-	addiu	$11,$11,-1
-	sw	$2,0($5)
-	addiu	$16,$16,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$11,$L37
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	addiu	$17,$17,-64
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	compress
-	move	$5,$19
-	.set	macro
-	.set	reorder
-
-	sltu	$2,$17,64
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L50
-	addiu	$5,$20,24
-	.set	macro
-	.set	reorder
-
-$L44:
-	move	$5,$16
-	move	$6,$18
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	MDfinish
-	move	$7,$0
-	.set	macro
-	.set	reorder
-
-	move	$11,$0
-	la	$15,hashcode.0
-	la	$13,hashcode.0+1
-	la	$14,hashcode.0+2
-	la	$12,hashcode.0+3
-$L42:
-	srl	$2,$11,2
-	sll	$2,$2,2
-	addu	$2,$2,$20
-	lw	$3,0($2)
-	addu	$7,$11,$15
-	addu	$8,$11,$13
-	addu	$9,$11,$14
-	addu	$10,$11,$12
-	addiu	$11,$11,4
-	srl	$6,$3,24
-	srl	$2,$3,8
-	srl	$4,$3,16
-	sltu	$5,$11,20
-	sb	$3,0($7)
-	sb	$2,0($8)
-	sb	$4,0($9)
-	.set	noreorder
-	.set	nomacro
-	bne	$5,$0,$L42
-	sb	$6,0($10)
-	.set	macro
-	.set	reorder
-
-	lw	$31,124($sp)
-	lw	$20,120($sp)
-	lw	$19,116($sp)
-	lw	$18,112($sp)
-	lw	$17,108($sp)
-	lw	$16,104($sp)
-	la	$2,hashcode.0
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,128
-	.set	macro
-	.set	reorder
-
-	.end	RMD
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"\r\n\000"
-	.align	2
-$LC1:
-	.ascii	"* message: \000"
-	.align	2
-$LC2:
-	.ascii	"  hashcode: \000"
-	.text
-	.align	2
-	.globl	RMDstring
-	.ent	RMDstring
-RMDstring:
-	.frame	$sp,40,$31		# vars= 8, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lbu	$3,$LC0+2
-	lhu	$2,$LC0
-	addiu	$sp,$sp,-40
-	sw	$31,32($sp)
-	sb	$3,18($sp)
-	sw	$17,28($sp)
-	sw	$16,24($sp)
-	sh	$2,16($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	RMD
-	move	$16,$5
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC1
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC2
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$16,$0
-	.set	macro
-	.set	reorder
-
-	addu	$2,$17,$16
-$L58:
-	lb	$4,0($2)
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	sltu	$2,$16,20
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L58
-	addu	$2,$17,$16
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$4,$sp,16
-	.set	macro
-	.set	reorder
-
-	lw	$31,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,40
-	.set	macro
-	.set	reorder
-
-	.end	RMDstring
-	.rdata
-	.align	2
-$LC3:
-	.byte	-1
-	.byte	35
-	.byte	-100
-	.byte	-42
-	.byte	89
-	.byte	-118
-	.byte	121
-	.byte	46
-	.byte	-89
-	.byte	-85
-	.byte	108
-	.byte	-8
-	.byte	117
-	.byte	-74
-	.byte	53
-	.byte	94
-	.byte	93
-	.byte	-128
-	.byte	106
-	.byte	54
-	.section	.rodata.str1.4
-	.align	2
-$LC4:
-	.ascii	"MIPS R3000 CPU\000"
-	.align	2
-$LC5:
-	.ascii	"Failed\r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,88,$31		# vars= 48, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	lwl	$2,$LC3+3
-	lwl	$3,$LC3+7
-	lwr	$2,$LC3
-	lwr	$3,$LC3+4
-	lwl	$4,$LC3+11
-	lwl	$5,$LC3+15
-	lwl	$6,$LC3+19
-	addiu	$sp,$sp,-88
-	lwr	$4,$LC3+8
-	lwr	$5,$LC3+12
-	lwr	$6,$LC3+16
-	sw	$2,16($sp)
-	sw	$3,20($sp)
-	lw	$2,$LC4
-	lw	$3,$LC4+4
-	sw	$19,76($sp)
-	sw	$18,72($sp)
-	sw	$17,68($sp)
-	sw	$4,24($sp)
-	sw	$5,28($sp)
-	sw	$2,40($sp)
-	sw	$31,80($sp)
-	sw	$16,64($sp)
-	sw	$6,32($sp)
-	sw	$3,44($sp)
-	lw	$2,$LC4+8
-	lhu	$3,$LC4+12
-	sw	$2,48($sp)
-	lbu	$2,$LC4+14
-	sh	$3,52($sp)
-	sb	$2,54($sp)
-	lbu	$3,$LC0+2
-	lhu	$2,$LC0
-	li	$4,-2147483648			# 0xffffffff80000000
-	sh	$2,56($sp)
-	sb	$3,58($sp)
-	ori	$5,$4,0x9
-	li	$2,53
-	ori	$4,$4,0x8
-	li	$3,85
-	sb	$2,0($5)
-	move	$18,$0
-	sb	$3,0($4)
-	addiu	$19,$sp,56
-	addiu	$17,$sp,40
-$L60:
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$18
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$4,$19
-	.set	macro
-	.set	reorder
-
-	addiu	$18,$18,1
-	.set	noreorder
-	.set	nomacro
-	j	$L66
-	li	$16,32249			# 0x7df9
-	.set	macro
-	.set	reorder
-
-$L64:
-	.set	noreorder
-	.set	nomacro
-	bltz	$16,$L70
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-$L66:
-	.set	noreorder
-	.set	nomacro
-	jal	RMD
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	move	$4,$2
-	addiu	$5,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	memcmp
-	li	$6,20			# 0x14
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC5
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L64
-	addiu	$16,$16,-1
-	.set	macro
-	.set	reorder
-
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	bgez	$16,$L66
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-$L70:
-	.set	noreorder
-	.set	nomacro
-	jal	RMDstring
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	j	$L60
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/spim_load_store.s b/lib/CPUs/MIPS/sim/asm/spim_load_store.s
deleted file mode 100644
index 864d660..0000000
--- a/lib/CPUs/MIPS/sim/asm/spim_load_store.s
+++ /dev/null
@@ -1,50 +0,0 @@
-main:
-		li, $8, 0x81234678
-
-# SB
-		li, $15, 0x10000000
-		sw	$8, 0($15)
-		
-		
-		mfc0 $9, $12
-		li	$10, 0x02000000
-		or	$9, $9, $10
-		mtc0 $9, $12
-		lwl	$16, 0($15)
-		lwl	$17, 1($15)
-		lwl	$18, 2($15)
-		lwl	$19, 3($15)
-		nop
-		lwr	$24, 0($15)
-		lwr	$25, 1($15)
-		lwr	$26, 2($15)
-		lwr	$27, 3($15)
-		nop
-		lbu	$16, 0($15)
-		lbu	$17, 1($15)
-		lbu	$18, 2($15)
-		lbu	$19, 3($15)
-		nop
-		lb	$24, 0($15)
-		lb	$25, 1($15)
-		lb	$26, 2($15)
-		lb	$27, 3($15)
-		nop
-		swl	$8, 4($15)
-		swl	$8, 9($15)
-		swl	$8, 14($15)
-		swl	$8, 19($15)
-		nop
-		swr	$8, 20($15)
-		swr	$8, 25($15)
-		swr	$8, 30($15)
-		swr	$8, 35($15)
-		nop
-		sb	$8, 0($15)
-		sb	$8, 1($15)
-		sb	$8, 2($15)
-		sb	$8, 3($15)
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/startup.s b/lib/CPUs/MIPS/sim/asm/startup.s
deleted file mode 100644
index a53059e..0000000
--- a/lib/CPUs/MIPS/sim/asm/startup.s
+++ /dev/null
@@ -1,27 +0,0 @@
-		.file	"startup.s"
-	
-		.section .stext,"ax"
-		.extern _init
-		.align	2
-	
-_start:
-		.set	noreorder
-
-		# Set Kernel mode
-		li		$26, 0x1040040C
-		mtc0	$26, $12
-		li		$26, 0x00000000
-		mtc0	$26, $13
-
-		mfc0	$26, $15
-		nop
-		mtc0	$26, $31
-
-		# jump init
-		la $26, _init
-		jr $26
-
-		# set user mode
-		rfe
-	
-		.set	reorder
diff --git a/lib/CPUs/MIPS/sim/asm/test1.s b/lib/CPUs/MIPS/sim/asm/test1.s
deleted file mode 100644
index 73f2ec3..0000000
--- a/lib/CPUs/MIPS/sim/asm/test1.s
+++ /dev/null
@@ -1,39 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5678
-			andi $1, $1, 0xF00F
-			addi $1, -0x5004
-loop:		addi $1, -1		
-			bgtz $1, loop
-			lui $2, 0
-			ori $2, 1
-			lui $1, 0
-			ori $1, 4
-loop2:		sub	 $1, $1, $2
-			bgtz $1, loop2
-			lui  $31, 0x0040
-			jr   $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test2.s b/lib/CPUs/MIPS/sim/asm/test2.s
deleted file mode 100644
index 30353ab..0000000
--- a/lib/CPUs/MIPS/sim/asm/test2.s
+++ /dev/null
@@ -1,40 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5678
-			lui $3, 0x5555
-			ori $3, $3, 0xAAAA
-			lui $2, 0x1000
-			sw	$1, 0($2)
-			sw	$3, 4($2)
-			sw	$2, 0($2)
-			sw	$1, 4($2)
-			lw  $1, 4($2)
-			lw  $4, 0($2)
-			lui $5, 0x0001
-			lui $6, 0x0002
-			lui $7, 0x0003
-			lui $8, 0x0004
-			add $4, $4, $5
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			j   main
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test3.s b/lib/CPUs/MIPS/sim/asm/test3.s
deleted file mode 100644
index f24d9a4..0000000
--- a/lib/CPUs/MIPS/sim/asm/test3.s
+++ /dev/null
@@ -1,40 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x1234
-			ori $1, $1, 0x5A5A
-			sll $1, $1, 1
-			sll $1, $1, 4
-			sll $1, $1, 2
-			sll $1, $1, 1
-			sll $1, $1, 8
-			srl $1, $1, 2
-			srl $1, $1, 5
-			srl $1, $1, 1
-			srl $1, $1, 8
-			xori $1, $1, 0xFFFF
-			lui  $31, 0x0040
-			jr   $31
-			xor $1, $1, $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test4.s b/lib/CPUs/MIPS/sim/asm/test4.s
deleted file mode 100644
index 830808f..0000000
--- a/lib/CPUs/MIPS/sim/asm/test4.s
+++ /dev/null
@@ -1,34 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		sll $0, $0, 0
-		lui $1, 0x1000
-		addi $2, $1, 0
-		lui $7, 0x1234
-		lui $5, 0x0001
-		sw	$7, 0($1)
-		lw  $3, 0($2)
-		add $8, $3, $5
-		add $9, $3, $5
-		add $10, $3, $5
-		add $11, $3, $5
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		j   main
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-		sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test5.s b/lib/CPUs/MIPS/sim/asm/test5.s
deleted file mode 100644
index 89d8a63..0000000
--- a/lib/CPUs/MIPS/sim/asm/test5.s
+++ /dev/null
@@ -1,39 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $1, 0x8000
-			lui $2, 0
-			lui $3, 0
-			ori $2, 1
-			ori $3, 3
-			srl $1, $1, 1
-			sll $1, $1, 1
-			sra $1, $1, 1
-			sra $1, $1, 3
-			sllv $4, $1, $3
-			srav $5, $1, $2
-			srav $6, $1, $3
-			lui  $31, 0x0040
-			jr   $31
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test6.s b/lib/CPUs/MIPS/sim/asm/test6.s
deleted file mode 100644
index 65809dd..0000000
--- a/lib/CPUs/MIPS/sim/asm/test6.s
+++ /dev/null
@@ -1,31 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		lui $8, 0
-loop:		sll $0, $0, 0	
-			jal subr1
-			la $2, subr2
-			jalr $15, $2
-			sll $0, $0, 0
-			j	loop
-			
-subr1:		addi $8, 1
-			sll $0, $0, 0
-			jr   $31
-subr2:		addi $8, 16
-			sll $0, $0, 0
-			jr   $15
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test7.s b/lib/CPUs/MIPS/sim/asm/test7.s
deleted file mode 100644
index 05d9457..0000000
--- a/lib/CPUs/MIPS/sim/asm/test7.s
+++ /dev/null
@@ -1,17 +0,0 @@
-
-main:		li $2, 0x12345678
-			li $3, 0x87654321
-			mult $2, $3
-			multu $2, $3
-			mult $3, $2
-			multu $3, $2
-			
-			mult $2, $2
-			multu $2, $2
-			mult $3, $3
-			multu $3, $3
-			
-			sll $0, $0, 0
-			j main
-			sll $0, $0, 0
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_addsub.s b/lib/CPUs/MIPS/sim/asm/test_addsub.s
deleted file mode 100644
index 0e0c700..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_addsub.s
+++ /dev/null
@@ -1,76 +0,0 @@
-		.text
-		.globl	main
-		.globl	__start
-		
-__start:	j main
-
-main:		li $2, 0x12345678
-			li $4, 0x12345678
-			li $6, 0x12345678
-			li $8, 0x12345678
-			li $3, 0x77654321
-			li $5, 0x77654321
-			li $7, 0x77654321
-			li $9, 0x77654321
-			addu $15, $2, $3
-			addu $15, $3, $2
-			addu $15, $2, $2
-			addu $15, $3, $3
-
-			sll $0, $0, 0
-
-			subu $15, $2, $3
-			subu $15, $3, $2
-			subu $15, $2, $2
-			subu $15, $3, $3
-
-			sll $0, $0, 0
-
-			addiu $4, 0x1234
-			addiu $8, -0x1234
-			addiu $5, 0x1234
-			addiu $9, -0x1234
-
-			sll $0, $0, 0
-
-			add $15, $2, $3
-			add $15, $3, $2
-			add $15, $2, $2
-			add $15, $3, $3
-
-			sll $0, $0, 0
-
-			sub $15, $2, $3
-			sub $15, $3, $2
-			sub $15, $2, $2
-			sub $15, $3, $3
-
-			sll $0, $0, 0
-
-			addi $2, 0x1234
-			addi $6, -0x1234
-			addi $3, 0x1234
-			addi $7, -0x1234
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-			sll $0, $0, 0
-
-			
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_muldiv.s b/lib/CPUs/MIPS/sim/asm/test_muldiv.s
deleted file mode 100644
index 9c85e8a..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_muldiv.s
+++ /dev/null
@@ -1,17 +0,0 @@
-main:
-		li $8, 0x12345678
-		li $9, 0x87654321
-		mthi $8
-		mfhi $10
-		addu $16, $10, $9
-
-		mtlo $9
-		mflo $11
-		multu $8, $9
-#		addu $17, $11, $8
-
-		nop
-		nop
-		nop
-		nop
-		
\ No newline at end of file
diff --git a/lib/CPUs/MIPS/sim/asm/test_slt.s b/lib/CPUs/MIPS/sim/asm/test_slt.s
deleted file mode 100644
index 0f55466..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_slt.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			sltu $15, $2, $2
-			sltu $15, $2, $3
-			sltu $15, $2, $4
-			sltu $15, $2, $5
-			
-			sltu $15, $3, $2
-			sltu $15, $3, $3
-			sltu $15, $3, $4
-			sltu $15, $3, $5
-
-			sltu $15, $4, $2
-			sltu $15, $4, $3
-			sltu $15, $4, $4
-			sltu $15, $4, $5
-			
-			sltu $15, $5, $2
-			sltu $15, $5, $3
-			sltu $15, $5, $4
-			sltu $15, $5, $5
-
-			sll $0, $0, 0
-
-			slt $15, $2, $2
-			slt $15, $2, $3
-			slt $15, $2, $4
-			slt $15, $2, $5
-			
-			slt $15, $3, $2
-			slt $15, $3, $3
-			slt $15, $3, $4
-			slt $15, $3, $5
-
-			slt $15, $4, $2
-			slt $15, $4, $3
-			slt $15, $4, $4
-			slt $15, $4, $5
-			
-			slt $15, $5, $2
-			slt $15, $5, $3
-			slt $15, $5, $4
-			slt $15, $5, $5
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/test_slti.s b/lib/CPUs/MIPS/sim/asm/test_slti.s
deleted file mode 100644
index 7c47f70..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_slti.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			sltiu $15, $2, 0x1234
-			sltiu $15, $2, 0x2345
-			sltiu $15, $2, -0x1234
-			sltiu $15, $2, -0x2345
-			
-			sltiu $15, $3, 0x1234
-			sltiu $15, $3, 0x2345
-			sltiu $15, $3, -0x1234
-			sltiu $15, $3, -0x2345
-
-			sltiu $15, $4, 0x1234
-			sltiu $15, $4, 0x2345
-			sltiu $15, $4, -0x1234
-			sltiu $15, $4, -0x2345
-			
-			sltiu $15, $5, 0x1234
-			sltiu $15, $5, 0x2345
-			sltiu $15, $5, -0x1234
-			sltiu $15, $5, -0x2345
-
-			sll $0, $0, 0
-
-			slti $15, $2, 0x1234
-			slti $15, $2, 0x2345
-			slti $15, $2, -0x1234
-			slti $15, $2, -0x2345
-			
-			slti $15, $3, 0x1234
-			slti $15, $3, 0x2345
-			slti $15, $3, -0x1234
-			slti $15, $3, -0x2345
-
-			slti $15, $4, 0x1234
-			slti $15, $4, 0x2345
-			slti $15, $4, -0x1234
-			slti $15, $4, -0x2345
-			
-			slti $15, $5, 0x1234
-			slti $15, $5, 0x2345
-			slti $15, $5, -0x1234
-			slti $15, $5, -0x2345
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/test_sub.s b/lib/CPUs/MIPS/sim/asm/test_sub.s
deleted file mode 100644
index f3ee61d..0000000
--- a/lib/CPUs/MIPS/sim/asm/test_sub.s
+++ /dev/null
@@ -1,57 +0,0 @@
-#		.ktext 0x80000180
-		.text 0x00410000
-		.globl	main
-		
-main:		li $2, 0x12345678
-			li $3, 0x23456789
-			li $4, 0x87654321
-			li $5, 0x98765432
-			li $8, 0x10000000
-			sll $0, $0, 0
-
-			subu $15, $2, $2
-			subu $15, $2, $3
-			subu $15, $2, $4
-			subu $15, $2, $5
-			
-			subu $15, $3, $2
-			subu $15, $3, $3
-			subu $15, $3, $4
-			subu $15, $3, $5
-
-			subu $15, $4, $2
-			subu $15, $4, $3
-			subu $15, $4, $4
-			subu $15, $4, $5
-			
-			subu $15, $5, $2
-			subu $15, $5, $3
-			subu $15, $5, $4
-			subu $15, $5, $5
-
-			sll $0, $0, 0
-
-			sub $15, $2, $2
-			sub $15, $2, $3
-			sub $15, $2, $4
-			sub $15, $2, $5
-			
-			sub $15, $3, $2
-			sub $15, $3, $3
-			sub $15, $3, $4
-			sub $15, $3, $5
-
-			sub $15, $4, $2
-			sub $15, $4, $3
-			sub $15, $4, $4
-			sub $15, $4, $5
-			
-			sub $15, $5, $2
-			sub $15, $5, $3
-			sub $15, $5, $4
-			sub $15, $5, $5
-
-			sll $0, $0, 0
-
-			j   main
-			sll $0, $0, 0
diff --git a/lib/CPUs/MIPS/sim/asm/testbench.c b/lib/CPUs/MIPS/sim/asm/testbench.c
deleted file mode 100644
index 1cbf3b6..0000000
--- a/lib/CPUs/MIPS/sim/asm/testbench.c
+++ /dev/null
@@ -1,322 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <time.h>
-#include "utils.h"
-
-#define	NO_ERROR		0x00000000
-#define	ERROR			0x80000000
-#define	IS_ERROR(e)		((e & ERROR) == ERROR)
-
-#define	TEST10_ERROR	(ERROR | 0x10)
-#define	TEST11_ERROR	(ERROR | 0x11)
-#define	TEST12_ERROR	(ERROR | 0x12)
-
-int fibonacci(int f0, int f1, int *pDst, int len)
-{
-	int i;
-
-	i = 0;
-
-	pDst[i++] = f0;
-	pDst[i++] = f1;
-
-	for (; i < len; i++)
-	{
-		pDst[i] = pDst[i-2] + pDst[i-1];
-	}
-
-	return i;
-}
-
-int StatusRegister_read(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"mfc0   $2, $12\n"
-		".set	reorder\n"
-
-	);
-}
-
-int RevisionRegister_read(void)
-{
-	__asm
-	(
-		".set	noreorder\n"
-		"mfc0   $2, $15\n"
-		".set	reorder\n"
-
-	);
-}
-
-void PrintCPUinfo(void)
-{
-	int result, rev_id;
-
-	char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"};
-
-	// Print Status register
-	result = StatusRegister_read();
-	sputs("Status  : ");
-	print_word(result);
-	sputs("\r\n");
-
-	// Print Revision
-	result = RevisionRegister_read();
-	rev_id = (result >> 8) & 0xFF;
-	sputs("CPU type: ");
-	if ((rev_id > 0) && (rev_id < 0x07))
-	{
-		sputs(cpu_type_str[rev_id]);
-		sputs(" Rev.");
-		rev_id = result & 0xFF;
-		print_byte((char)rev_id);
-	}
-	else
-		sputs("Unknown");
-
-	sputs("\r\n");
-
-}
-
-int Test10_LoadStore()
-{
-	int *buf, i, result, data, err;
-	volatile int *pPtr;
-
-	buf = (int*)malloc(32*sizeof(int));
-	while(1)
-	{
-		err = TEST10_ERROR;
-		// Basic Load/Store
-		pPtr = buf;
-		*pPtr++ = 0x00000000;
-		*pPtr++ = 0x55555555;
-		*pPtr++ = 0xAAAAAAAA;
-		*pPtr++ = 0xFFFFFFFF;
-		pPtr = buf;
-		if (*pPtr++ != 0x00000000)
-			break;
-		if (*pPtr++ != 0x55555555)
-			break;
-		if (*pPtr++ != 0xAAAAAAAA)
-			break;
-		if (*pPtr++ != 0xFFFFFFFF)
-			break;
-
-		// Filling from left
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data >> 1 | 0x80000000;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data >> 1 | 0x80000000;
-		}
-		if (i != 32)
-			break;
-
-		// Filling from right
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000000;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking ones
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1;
-
-		}
-		pPtr = buf;
-		data = 0x00000001;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1;
-		}
-		if (i != 32)
-			break;
-
-		// Walking zeros
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-			*pPtr++ = data;
-			data = data << 1 | 1;
-
-		}
-		pPtr = buf;
-		data = 0xFFFFFFFE;
-		for (i=0; i < 32; i++)
-		{
-
-			if (*pPtr++ != data)
-				break;
-
-			data = data << 1 | 1;
-
-		}
-		if (i != 32)
-			break;
-
-		err = NO_ERROR;
-		break;
-	}
-	free(buf);
-	return err;
-
-}
-
-
-#define	NUM_ELEMENTS	20
-#define	NUM_RUNS		3
-int Test11_AddSub()
-{
-	int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs;
-
-	fill = 0xAAAAAAAA;
-
-	num_right_runs = 0;
-
-	for (i=0; i < NUM_RUNS; i++)
-	{
-		for (j=0;  j < NUM_ELEMENTS; j++)
-			buf[j] = fill;
-
-		fill = ((fill ^ i) - 1) << 1;
-		num_right_elements = 2;
-		result = fibonacci(i, i+1, buf, NUM_ELEMENTS);
-		for (j=2;  j < NUM_ELEMENTS; j++)
-		{
-			diff = buf[j] - buf[j-1];
-			if (diff == buf[j-2])
-				num_right_elements++;
-		}
-		if (num_right_elements == NUM_ELEMENTS)
-			num_right_runs++;
-	}
-
-	if (num_right_runs != NUM_RUNS)
-		return TEST11_ERROR;
-
-	return NO_ERROR;
-}
-
-int Test12_MulDiv()
-{
-	int mix, i, j;
-	int s1, s2, sp, st;
-	div_t div_res;
-
-	srand(0x19701031);
-	for (i=0; i < 100; i++)
-	{
-		for (j=1; j < 1000; j++)
-		{
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s1 = (int)rand() ^ mix;
-			mix = (int)rand();
-			mix = (mix << 8) ^ (mix << 16);
-			s2 = (int)rand() ^ mix;
-
-			div_res = div(s1, s2);
-
-			sp = s2*div_res.quot;
-			st = div_res.rem + sp;
-			if (st != s1)
-				return TEST12_ERROR;
-		}
-	}
-	return NO_ERROR;
-}
-
-int main (void)
-{
-	int result, i, j, cnt;
-	volatile char *pUART_baud = (char*)0x80000009;
-	volatile int *pReg = (int*)0x80000000;
-	volatile int *pReg_usec = (int*)0x80000010;
-	volatile int *pReg_sec = (int*)0x80000014;
-	time_t clock;
-	struct tm *pDate;
-//	*pUART_baud = 0x35/4;
-
-	PrintCPUinfo();
-
-	cnt = 0;
-//	*pReg_sec = 0x12345678;
-	while (1)
-	{
-		*pReg = cnt & 0x3FFFFFFF;
-
-		result = Test10_LoadStore();
-		if (IS_ERROR(result))
-			break;
-
-		result = Test11_AddSub();
-		if (IS_ERROR(result))
-			break;
-
-		result = Test12_MulDiv();
-		if (IS_ERROR(result))
-			break;
-
-//		printf("Iteration %d: Passed\r\n", cnt++);
-		sputs("Iteration ");
-		print_word(cnt++);
-		sputs(": Passed\r\n");
-
-		clock = time(NULL);
-		pDate = gmtime(&clock);
-		print_byte(pDate->tm_hour);
-		sputs(":");
-		print_byte(pDate->tm_min);
-		sputs(":");
-		print_byte(pDate->tm_sec);
-		sputs("\r\n");
-	}
-	*pReg = 0x40000000 | cnt;
-	sputs("Failed with error ");
-	print_word(result);
-	sputs(" \r\n");
-
-	return 1;
-
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/testbench.s b/lib/CPUs/MIPS/sim/asm/testbench.s
deleted file mode 100644
index acc1d4d..0000000
--- a/lib/CPUs/MIPS/sim/asm/testbench.s
+++ /dev/null
@@ -1,924 +0,0 @@
-	.file	1 "testbench.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	fibonacci
-	.ent	fibonacci
-fibonacci:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$8,2			# 0x2
-	slt	$2,$8,$7
-	sw	$4,0($6)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L7
-	sw	$5,4($6)
-	.set	macro
-	.set	reorder
-
-	addiu	$6,$6,8
-$L5:
-	lw	$2,-8($6)
-	lw	$3,-4($6)
-	addiu	$8,$8,1
-	addu	$2,$2,$3
-	slt	$4,$8,$7
-	sw	$2,0($6)
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L5
-	addiu	$6,$6,4
-	.set	macro
-	.set	reorder
-
-$L7:
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	move	$2,$8
-	.set	macro
-	.set	reorder
-
-	.end	fibonacci
-	.align	2
-	.globl	StatusRegister_read
-	.ent	StatusRegister_read
-StatusRegister_read:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-mfc0   $2, $12
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	StatusRegister_read
-	.align	2
-	.globl	RevisionRegister_read
-	.ent	RevisionRegister_read
-RevisionRegister_read:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
- #APP
-	.set	noreorder
-mfc0   $2, $15
-.set	reorder
-
- #NO_APP
-	j	$31
-	.end	RevisionRegister_read
-	.section	.rodata.str1.4,"aMS",@progbits,1
-	.align	2
-$LC0:
-	.ascii	"invalid\000"
-	.align	2
-$LC1:
-	.ascii	"R2000\000"
-	.align	2
-$LC2:
-	.ascii	"R3000\000"
-	.align	2
-$LC3:
-	.ascii	"R6000\000"
-	.align	2
-$LC4:
-	.ascii	"R4000\000"
-	.align	2
-$LC5:
-	.ascii	"reserved\000"
-	.align	2
-$LC6:
-	.ascii	"R6000A\000"
-	.rdata
-	.align	2
-$LC7:
-	.word	$LC0
-	.word	$LC1
-	.word	$LC2
-	.word	$LC3
-	.word	$LC4
-	.word	$LC5
-	.word	$LC6
-	.section	.rodata.str1.4
-	.align	2
-$LC8:
-	.ascii	"Status  : \000"
-	.align	2
-$LC9:
-	.ascii	"\r\n\000"
-	.align	2
-$LC10:
-	.ascii	"CPU type: \000"
-	.align	2
-$LC12:
-	.ascii	"Unknown\000"
-	.align	2
-$LC11:
-	.ascii	" Rev.\000"
-	.text
-	.align	2
-	.globl	PrintCPUinfo
-	.ent	PrintCPUinfo
-PrintCPUinfo:
-	.frame	$sp,64,$31		# vars= 32, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	lw	$2,$LC7
-	addiu	$sp,$sp,-64
-	lw	$3,$LC7+4
-	sw	$2,16($sp)
-	lw	$2,$LC7+8
-	sw	$3,20($sp)
-	sw	$2,24($sp)
-	lw	$3,$LC7+12
-	lw	$2,$LC7+16
-	sw	$3,28($sp)
-	sw	$2,32($sp)
-	lw	$3,$LC7+20
-	lw	$2,$LC7+24
-	sw	$3,36($sp)
-	sw	$31,56($sp)
-	sw	$17,52($sp)
-	sw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	StatusRegister_read
-	sw	$2,40($sp)
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC8
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC9
-	jal	sputs
-	jal	RevisionRegister_read
-	sra	$16,$2,8
-	andi	$16,$16,0xff
-	la	$4,$LC10
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	move	$17,$2
-	.set	macro
-	.set	reorder
-
-	sll	$3,$16,2
-	addiu	$16,$16,-1
-	sltu	$16,$16,6
-	la	$4,$LC12
-	.set	noreorder
-	.set	nomacro
-	beq	$16,$0,$L12
-	addu	$2,$sp,$3
-	.set	macro
-	.set	reorder
-
-	lw	$4,16($2)
-	jal	sputs
-	la	$4,$LC11
-	jal	sputs
-	sll	$4,$17,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	sra	$4,$4,24
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC9
-	jal	sputs
-	lw	$31,56($sp)
-	lw	$17,52($sp)
-	lw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,64
-	.set	macro
-	.set	reorder
-
-$L12:
-	jal	sputs
-	la	$4,$LC9
-	jal	sputs
-	lw	$31,56($sp)
-	lw	$17,52($sp)
-	lw	$16,48($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,64
-	.set	macro
-	.set	reorder
-
-	.end	PrintCPUinfo
-	.align	2
-	.globl	Test10_LoadStore
-	.ent	Test10_LoadStore
-Test10_LoadStore:
-	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
-	.mask	0x80010000,-4
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-24
-	li	$4,128			# 0x80
-	sw	$31,20($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	malloc
-	sw	$16,16($sp)
-	.set	macro
-	.set	reorder
-
-	move	$4,$2
-	li	$2,1431633920			# 0x55550000
-	li	$3,-1431699456			# 0xffffffffaaaa0000
-	ori	$5,$2,0x5555
-	ori	$6,$3,0xaaaa
-	li	$7,-1			# 0xffffffffffffffff
-	sw	$0,0($4)
-	sw	$5,4($4)
-	sw	$6,8($4)
-	sw	$7,12($4)
-	lw	$3,0($4)
-	li	$2,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L16
-	ori	$16,$2,0x10
-	.set	macro
-	.set	reorder
-
-	lw	$2,4($4)
-	beq	$2,$5,$L73
-$L16:
-	jal	free
-	move	$2,$16
-	lw	$31,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,24
-	.set	macro
-	.set	reorder
-
-$L73:
-	lw	$2,8($4)
-	bne	$2,$6,$L16
-	lw	$2,12($4)
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$7,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	move	$5,$0
-	li	$7,-2147483648			# 0xffffffff80000000
-	li	$6,31			# 0x1f
-$L24:
-	sra	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L24
-	or	$5,$2,$7
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	move	$5,$0
-	move	$6,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L29
-	li	$8,-2147483648			# 0xffffffff80000000
-	.set	macro
-	.set	reorder
-
-$L74:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L26
-	or	$5,$7,$8
-	.set	macro
-	.set	reorder
-
-$L29:
-	lw	$2,0($3)
-	sra	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L74
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L26:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	move	$5,$0
-	li	$6,31			# 0x1f
-$L34:
-	sll	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L34
-	ori	$5,$2,0x1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	move	$5,$0
-	.set	noreorder
-	.set	nomacro
-	j	$L39
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L75:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L36
-	ori	$5,$7,0x1
-	.set	macro
-	.set	reorder
-
-$L39:
-	lw	$2,0($3)
-	sll	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L75
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L36:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	li	$5,1			# 0x1
-	li	$6,31			# 0x1f
-$L44:
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L44
-	sll	$5,$5,1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	li	$5,1			# 0x1
-	.set	noreorder
-	.set	nomacro
-	j	$L49
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L76:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L46
-	sll	$5,$5,1
-	.set	macro
-	.set	reorder
-
-$L49:
-	lw	$2,0($3)
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L76
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L46:
-	li	$2,32			# 0x20
-	.set	noreorder
-	.set	nomacro
-	bne	$6,$2,$L16
-	move	$3,$4
-	.set	macro
-	.set	reorder
-
-	li	$5,-2			# 0xfffffffffffffffe
-	li	$6,31			# 0x1f
-$L54:
-	sll	$2,$5,1
-	addiu	$6,$6,-1
-	sw	$5,0($3)
-	addiu	$3,$3,4
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L54
-	ori	$5,$2,0x1
-	.set	macro
-	.set	reorder
-
-	move	$3,$4
-	li	$5,-2			# 0xfffffffffffffffe
-	.set	noreorder
-	.set	nomacro
-	j	$L59
-	move	$6,$0
-	.set	macro
-	.set	reorder
-
-$L77:
-	addiu	$6,$6,1
-	slt	$2,$6,32
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$0,$L56
-	ori	$5,$7,0x1
-	.set	macro
-	.set	reorder
-
-$L59:
-	lw	$2,0($3)
-	sll	$7,$5,1
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$5,$L77
-	addiu	$3,$3,4
-	.set	macro
-	.set	reorder
-
-$L56:
-	li	$2,32			# 0x20
-	bne	$6,$2,$L16
-	.set	noreorder
-	.set	nomacro
-	j	$L16
-	move	$16,$0
-	.set	macro
-	.set	reorder
-
-	.end	Test10_LoadStore
-	.align	2
-	.globl	Test11_AddSub
-	.ent	Test11_AddSub
-Test11_AddSub:
-	.frame	$sp,120,$31		# vars= 80, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-120
-	li	$2,-1431699456			# 0xffffffffaaaa0000
-	sw	$19,108($sp)
-	sw	$18,104($sp)
-	sw	$16,96($sp)
-	sw	$31,112($sp)
-	sw	$17,100($sp)
-	ori	$16,$2,0xaaaa
-	move	$19,$0
-	move	$4,$0
-	addiu	$18,$sp,16
-$L92:
-	move	$2,$18
-	li	$6,19			# 0x13
-$L85:
-	addiu	$6,$6,-1
-	sw	$16,0($2)
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L85
-	addiu	$2,$2,4
-	.set	macro
-	.set	reorder
-
-	xor	$2,$16,$4
-	addiu	$17,$4,1
-	addiu	$2,$2,-1
-	move	$5,$17
-	addiu	$6,$sp,16
-	li	$7,20			# 0x14
-	.set	noreorder
-	.set	nomacro
-	jal	fibonacci
-	sll	$16,$2,1
-	.set	macro
-	.set	reorder
-
-	li	$7,2			# 0x2
-	addiu	$5,$18,8
-	.set	noreorder
-	.set	nomacro
-	j	$L90
-	li	$6,17			# 0x11
-	.set	macro
-	.set	reorder
-
-$L88:
-	bltz	$6,$L100
-$L90:
-	lw	$2,0($5)
-	lw	$3,-4($5)
-	lw	$4,-8($5)
-	subu	$2,$2,$3
-	addiu	$6,$6,-1
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$2,$L88
-	addiu	$5,$5,4
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$6,$L90
-	addiu	$7,$7,1
-	.set	macro
-	.set	reorder
-
-$L100:
-	li	$6,20			# 0x14
-	beq	$7,$6,$L101
-$L81:
-	slt	$2,$17,3
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L92
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	li	$2,3			# 0x3
-	.set	noreorder
-	.set	nomacro
-	bne	$19,$2,$L102
-	move	$3,$0
-	.set	macro
-	.set	reorder
-
-	lw	$31,112($sp)
-	lw	$19,108($sp)
-	lw	$18,104($sp)
-	lw	$17,100($sp)
-	lw	$16,96($sp)
-	move	$2,$3
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,120
-	.set	macro
-	.set	reorder
-
-$L101:
-	.set	noreorder
-	.set	nomacro
-	j	$L81
-	addiu	$19,$19,1
-	.set	macro
-	.set	reorder
-
-$L102:
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$3,$2,0x11
-	lw	$31,112($sp)
-	lw	$19,108($sp)
-	lw	$18,104($sp)
-	lw	$17,100($sp)
-	lw	$16,96($sp)
-	move	$2,$3
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,120
-	.set	macro
-	.set	reorder
-
-	.end	Test11_AddSub
-	.align	2
-	.globl	Test12_MulDiv
-	.ent	Test12_MulDiv
-Test12_MulDiv:
-	.frame	$sp,48,$31		# vars= 8, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	li	$4,426770432			# 0x19700000
-	addiu	$sp,$sp,-48
-	ori	$4,$4,0x1031
-	sw	$19,36($sp)
-	sw	$31,40($sp)
-	sw	$18,32($sp)
-	sw	$17,28($sp)
-	sw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	srand
-	move	$19,$0
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L111
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-$L109:
-	beq	$4,$0,$L117
-$L111:
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	addiu	$18,$18,1
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$17,$2,$16
-	.set	macro
-	.set	reorder
-
-	sll	$3,$2,16
-	sll	$2,$2,8
-	.set	noreorder
-	.set	nomacro
-	jal	rand
-	xor	$16,$2,$3
-	.set	macro
-	.set	reorder
-
-	xor	$16,$2,$16
-	addiu	$4,$sp,16
-	move	$5,$17
-	.set	noreorder
-	.set	nomacro
-	jal	div
-	move	$6,$16
-	.set	macro
-	.set	reorder
-
-	lw	$3,16($sp)
-	lw	$2,20($sp)
-	mult	$3,$16
-	mflo	$3
-	addu	$2,$2,$3
-	.set	noreorder
-	.set	nomacro
-	beq	$2,$17,$L109
-	slt	$4,$18,1000
-	.set	macro
-	.set	reorder
-
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$2,$2,0x12
-$L103:
-	lw	$31,40($sp)
-	lw	$19,36($sp)
-	lw	$18,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,48
-	.set	macro
-	.set	reorder
-
-$L117:
-	addiu	$19,$19,1
-	slt	$2,$19,100
-	.set	noreorder
-	.set	nomacro
-	bne	$2,$0,$L111
-	li	$18,1			# 0x1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	j	$L103
-	move	$2,$0
-	.set	macro
-	.set	reorder
-
-	.end	Test12_MulDiv
-	.section	.rodata.str1.4
-	.align	2
-$LC13:
-	.ascii	"Iteration %d: Passed\r\n\000"
-	.align	2
-$LC14:
-	.ascii	"Iteration \000"
-	.align	2
-$LC15:
-	.ascii	": Passed\r\n\000"
-	.align	2
-$LC16:
-	.ascii	":\000"
-	.align	2
-$LC17:
-	.ascii	"Failed with error \000"
-	.align	2
-$LC18:
-	.ascii	" \r\n\000"
-	.text
-	.align	2
-	.globl	main
-	.ent	main
-main:
-	.frame	$sp,48,$31		# vars= 8, regs= 5/0, args= 16, gp= 0
-	.mask	0x800f0000,-8
-	.fmask	0x00000000,0
-	li	$3,-2147483648			# 0xffffffff80000000
-	li	$2,13
-	ori	$3,$3,0x9
-	addiu	$sp,$sp,-48
-	sb	$2,0($3)
-	sw	$19,36($sp)
-	sw	$18,32($sp)
-	sw	$17,28($sp)
-	sw	$31,40($sp)
-	.set	noreorder
-	.set	nomacro
-	jal	PrintCPUinfo
-	sw	$16,24($sp)
-	.set	macro
-	.set	reorder
-
-	li	$2,1073676288			# 0x3fff0000
-	ori	$19,$2,0xffff
-	li	$18,-2147483648			# 0xffffffff80000000
-	.set	noreorder
-	.set	nomacro
-	j	$L119
-	move	$17,$0
-	.set	macro
-	.set	reorder
-
-$L124:
-	jal	Test11_AddSub
-	.set	noreorder
-	.set	nomacro
-	bltz	$2,$L120
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-	jal	Test12_MulDiv
-	move	$16,$2
-	la	$4,$LC13
-	.set	noreorder
-	.set	nomacro
-	bltz	$2,$L120
-	move	$5,$17
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	printf
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC14
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$17
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC15
-	.set	noreorder
-	.set	nomacro
-	jal	sputs
-	addiu	$17,$17,1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	jal	time
-	move	$4,$0
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$sp,16
-	.set	noreorder
-	.set	nomacro
-	jal	gmtime
-	sw	$2,16($sp)
-	.set	macro
-	.set	reorder
-
-	lb	$4,8($2)
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC16
-	jal	sputs
-	lb	$4,4($16)
-	jal	print_byte
-	la	$4,$LC16
-	jal	sputs
-	lb	$4,0($16)
-	jal	print_byte
-	la	$4,$LC9
-	jal	sputs
-$L119:
-	and	$2,$17,$19
-	sw	$2,0($18)
-	jal	Test10_LoadStore
-	.set	noreorder
-	.set	nomacro
-	bgez	$2,$L124
-	move	$16,$2
-	.set	macro
-	.set	reorder
-
-$L120:
-	li	$2,1073741824			# 0x40000000
-	or	$2,$17,$2
-	la	$4,$LC17
-	sw	$2,0($18)
-	jal	sputs
-	.set	noreorder
-	.set	nomacro
-	jal	print_word
-	move	$4,$16
-	.set	macro
-	.set	reorder
-
-	la	$4,$LC18
-	jal	sputs
-	lw	$31,40($sp)
-	lw	$19,36($sp)
-	lw	$18,32($sp)
-	lw	$17,28($sp)
-	lw	$16,24($sp)
-	li	$2,1			# 0x1
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,48
-	.set	macro
-	.set	reorder
-
-	.end	main
diff --git a/lib/CPUs/MIPS/sim/asm/utils.c b/lib/CPUs/MIPS/sim/asm/utils.c
deleted file mode 100644
index b704173..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.c
+++ /dev/null
@@ -1,179 +0,0 @@
-#include <sys/times.h>
-#include <sys/time.h>
-#include <sys/stat.h>
-#include <stdlib.h>
-
-char readchar(void)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while(!(0x10 & *pUART_stat));
-
-	return *pUART_data;
-}
-
-void writechar(char c)
-{
-	volatile char *pUART_stat = (char*)0x80000008;
-	volatile char *pUART_data = (char*)0x80000004;
-
-	while((0x02 & *pUART_stat) != 0);
-
-	*pUART_data = c;
-}
-
-clock_t times(struct tms *buffer)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-	long sec;
-
-	sec = *pReg_sec;
-
-	if (buffer)
-	{
-		buffer->tms_utime = sec;
-		buffer->tms_stime = 0;
-		buffer->tms_cutime = 0;
-		buffer->tms_cstime = 0;
-	}
-
-	return (clock_t)sec;
-}
-
-int gettimeofday(struct timeval *tp, void *tzp)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-
-	if (tp)
-	{
-		tp->tv_sec = *pReg_sec;
-		tp->tv_usec = *pReg_usec;
-	}
-
-	return 0;
-}
-
-int settimeofday(const struct timeval *tp, const struct timezone *tzp)
-{
-	volatile long *pReg_usec = (long*)0x80000010;
-	volatile long *pReg_sec = (long*)0x80000014;
-	div_t res;
-
-	res = div(tp->tv_usec, 1E6);
-
-	if (tp)
-	{
-		*pReg_usec = res.rem;
-		*pReg_sec  = tp->tv_sec + res.quot;
-	}
-
-	return 0;
-}
-
-caddr_t sbrk(int incr)
-{
-	extern char end;
-	static char *heap_end;
-	char *prev_heap_end;
-
-	if (heap_end == 0)
-		heap_end = &end;
-
-	prev_heap_end = heap_end;
-//	if (heap_end + incr > stack_ptr)
-//	{
-//		_write(1, "Heap and stack collision\n", 25);
-//		abort();
-//	}
-
-	heap_end += incr;
-	return (caddr_t) prev_heap_end;
-}
-
-int fstat(int file, struct stat *st)
-{
-	st->st_mode = S_IFCHR;
-	return 0;
-}
-
-int lseek(int file, int ptr, int dir)
-{
-	return 0;
-}
-
-int open(const char *name, int flags, int mode)
-{
-	return -1;
-}
-
-int close(int file)
-{
-	return -1;
-}
-
-int read(int file, char *ptr, int len)
-{
-	return 0;
-}
-
-int write(int file, char *ptr, int len)
-{
-	int i;
-
-	for (i=0; i < len; i++)
-		writechar(*ptr++);
-
-	return i;
-}
-
-int isatty(int file)
-{
-	return 1;
-}
-
-int sputs(char *pStr)
-{
-	char *start;
-	start = pStr;
-
-	while(*pStr)
-		writechar(*(pStr++));
-
-	return pStr - start;
-}
-
-void print_byte(char byte)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 2; i++)
-	{
-		nibble = (char)((byte >> 4) & 0xF);
-		byte <<= 4;
-
-		if (nibble < 10)
-			c = nibble + '0';
-		else
-			c = nibble + 'A' - 10;
-
-		writechar(c);
-	}
-}
-
-void print_word(int word)
-{
-	int i;
-	unsigned char c, nibble;
-
-	for (i=0; i < 4; i++)
-	{
-		c = (char) (word >> 24);
-		print_byte(c);
-		word <<= 8;
-	}
-}
-
diff --git a/lib/CPUs/MIPS/sim/asm/utils.h b/lib/CPUs/MIPS/sim/asm/utils.h
deleted file mode 100644
index aab48c4..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef UTILS_H
-#define UTILS_H
-
-char readchar(void);
-void writechar(char c);
-int write(int file, char *ptr, int len);
-int sputs(char *pStr);
-void print_byte(char byte);
-void print_word(int word);
-
-#endif // UTILS_H
-
diff --git a/lib/CPUs/MIPS/sim/asm/utils.s b/lib/CPUs/MIPS/sim/asm/utils.s
deleted file mode 100644
index 56b6d8c..0000000
--- a/lib/CPUs/MIPS/sim/asm/utils.s
+++ /dev/null
@@ -1,184 +0,0 @@
-	.file	1 "utils.c"
-	.set	nobopt
-	.text
-	.align	2
-	.globl	sein
-	.ent	sein
-sein:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	ori	$4,$2,0x4
-	ori	$3,$2,0x8
-$L2:
-	lbu	$2,0($3)
-	andi	$2,$2,0x10
-	beq	$2,$0,$L2
-	lbu	$2,0($4)
-	sll	$2,$2,24
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	sra	$2,$2,24
-	.set	macro
-	.set	reorder
-
-	.end	sein
-	.align	2
-	.globl	saus
-	.ent	saus
-saus:
-	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
-	.mask	0x00000000,0
-	.fmask	0x00000000,0
-	li	$2,-2147483648			# 0xffffffff80000000
-	sll	$4,$4,24
-	sra	$4,$4,24
-	ori	$5,$2,0x4
-	ori	$3,$2,0x8
-$L6:
-	lbu	$2,0($3)
-	andi	$2,$2,0x2
-	bne	$2,$0,$L6
-	sb	$4,0($5)
-	j	$31
-	.end	saus
-	.align	2
-	.globl	sputs
-	.ent	sputs
-sputs:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	lb	$4,0($4)
-	.set	noreorder
-	.set	nomacro
-	j	$L14
-	move	$17,$16
-	.set	macro
-	.set	reorder
-
-$L15:
-	.set	noreorder
-	.set	nomacro
-	jal	saus
-	addiu	$16,$16,1
-	.set	macro
-	.set	reorder
-
-	lb	$4,0($16)
-$L14:
-	.set	noreorder
-	.set	nomacro
-	bne	$4,$0,$L15
-	subu	$2,$16,$17
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	sputs
-	.align	2
-	.globl	print_byte
-	.ent	print_byte
-print_byte:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$16,16($sp)
-	sll	$16,$4,24
-	sw	$17,20($sp)
-	sw	$31,24($sp)
-	sra	$16,$16,24
-	li	$17,1			# 0x1
-	sra	$2,$16,4
-$L25:
-	andi	$5,$2,0xf
-	sll	$2,$16,4
-	sll	$16,$2,24
-	sltu	$3,$5,10
-	addiu	$17,$17,-1
-	sra	$16,$16,24
-	.set	noreorder
-	.set	nomacro
-	bne	$3,$0,$L21
-	addiu	$4,$5,48
-	.set	macro
-	.set	reorder
-
-	addiu	$4,$5,55
-$L21:
-	jal	saus
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L25
-	sra	$2,$16,4
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_byte
-	.align	2
-	.globl	print_word
-	.ent	print_word
-print_word:
-	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
-	.mask	0x80030000,-8
-	.fmask	0x00000000,0
-	addiu	$sp,$sp,-32
-	sw	$17,20($sp)
-	sw	$16,16($sp)
-	sw	$31,24($sp)
-	move	$16,$4
-	li	$17,3			# 0x3
-$L30:
-	sra	$4,$16,24
-	.set	noreorder
-	.set	nomacro
-	jal	print_byte
-	addiu	$17,$17,-1
-	.set	macro
-	.set	reorder
-
-	.set	noreorder
-	.set	nomacro
-	bgez	$17,$L30
-	sll	$16,$16,8
-	.set	macro
-	.set	reorder
-
-	lw	$31,24($sp)
-	lw	$17,20($sp)
-	lw	$16,16($sp)
-	.set	noreorder
-	.set	nomacro
-	j	$31
-	addiu	$sp,$sp,32
-	.set	macro
-	.set	reorder
-
-	.end	print_word
diff --git a/lib/CPUs/MIPS/sim/hello.flash.bin b/lib/CPUs/MIPS/sim/hello.flash.bin
deleted file mode 100644
index cd652ef..0000000
Binary files a/lib/CPUs/MIPS/sim/hello.flash.bin and /dev/null differ
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
deleted file mode 100644
index efb8705..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd"
-vcom -explicit  -93 "../src/core/mips_types.vhd"
-vcom -explicit  -93 "../src/core/mips_instr.vhd"
-vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../src/tb_mips_muldiv.vhd"
-vsim -t 1ps   -lib work tb_mips_muldiv
-do {tb_mips_muldiv.wdo}
-view wave
-
-view structure
-view signals
-run 8ms
diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
deleted file mode 100644
index 046f859..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo
+++ /dev/null
@@ -1,78 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mips_muldiv/rst
-add wave -noupdate -format Logic /tb_mips_muldiv/clk
-add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn
-add wave -noupdate -format Logic /tb_mips_muldiv/start
-add wave -noupdate -format Logic /tb_mips_muldiv/busy
-add wave -noupdate -format Logic /tb_mips_muldiv/s_un
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
-add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel
-add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/md_result
-add wave -noupdate -format Logic /tb_mips_muldiv/check
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en
-add wave -noupdate -divider FSM
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
-add wave -noupdate -divider {Multiplier internals}
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg
-add wave -noupdate -divider {Divider internals}
-add wave -noupdate -format Logic /tb_mips_muldiv/busy
-add wave -noupdate -format Logic /tb_mips_muldiv/s_un
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en
-add wave -noupdate -divider FSM
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt
-add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/s
-add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {7735999838 ps} 0} {{Cursor 2} {512321 ps} 0}
-configure wave -namecolwidth 149
-configure wave -valuecolwidth 171
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {8400 us}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_sys.fdo b/lib/CPUs/MIPS/sim/tb_mips_sys.fdo
deleted file mode 100644
index bca6968..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_sys.fdo
+++ /dev/null
@@ -1,42 +0,0 @@
-vlib work
-vcom -explicit  -93 "../src/dpram_2w2r.vhd"
-vcom -explicit  -93 "../src/dpram_1w1r.vhd"
-vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../src/gray_counter.vhd"
-vcom -explicit  -93 "../src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../src/fifo_async.vhd"
-vcom -explicit  -93 "../src/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../src/kcuart_rx.vhd"
-vcom -explicit  -93 "../src/kcuart_tx.vhd"
-vcom -explicit  -93 "../src/uart_rx.vhd"
-vcom -explicit  -93 "../src/uart_tx.vhd"
-vcom -explicit  -93 "../src/uart_wb.vhd"
-vcom -explicit  -93 "../src/gpio_wb.vhd"
-vcom -explicit  -93 "../src/async_types.vhd"
-vcom -explicit  -93 "../src/async_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs.vhd"
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../src/rom_wb.vhd"
-vcom -explicit  -93 "../src/mips_types.vhd"
-vcom -explicit  -93 "../src/mips_instr.vhd"
-vcom -explicit  -93 "../src/mips_reg.vhd"
-vcom -explicit  -93 "../src/mips_shifter.vhd"
-vcom -explicit  -93 "../src/mips_alu.vhd"
-vcom -explicit  -93 "../src/mips_muldiv.vhd"
-vcom -explicit  -93 "../src/mips_cop.vhd"
-vcom -explicit  -93 "../src/mips_icache.vhd"
-vcom -explicit  -93 "../src/mips_dcache.vhd"
-vcom -explicit  -93 "../src/mips_biu.vhd"
-vcom -explicit  -93 "../src/mips_bcu.vhd"
-vcom -explicit  -93 "../src/mips_pipeline.vhd"
-vcom -explicit  -93 "../src/mips_top.vhd"
-vcom -explicit  -93 "../src/mips_sys.vhd"
-vcom -explicit  -93 "../src/tb_mips_sys.vhd"
-vsim -t 1ps -lib work tb_mips_sys
-do {tb_mips_sys.wdo}
-view wave
-view structure
-view signals
-run 3000us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_sys.wdo b/lib/CPUs/MIPS/sim/tb_mips_sys.wdo
deleted file mode 100644
index 4d0670a..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_sys.wdo
+++ /dev/null
@@ -1,45 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {MIPS top}
-add wave -noupdate -format Literal /tb_mips_sys/debug
-add wave -noupdate -format Logic /tb_mips_sys/rst
-add wave -noupdate -format Logic /tb_mips_sys/clk
-add wave -noupdate -divider Flash
-add wave -noupdate -format Logic /tb_mips_sys/clk
-add wave -noupdate -format Logic /tb_mips_sys/flash_cs_n
-add wave -noupdate -format Logic /tb_mips_sys/flash_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/flash_d
-add wave -noupdate -divider SRAM
-add wave -noupdate -format Logic /tb_mips_sys/clk
-add wave -noupdate -format Logic /tb_mips_sys/sram_cs_n
-add wave -noupdate -format Literal /tb_mips_sys/sram_wr_n
-add wave -noupdate -format Logic /tb_mips_sys/sram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sram_d
-add wave -noupdate -divider GPIO
-add wave -noupdate -format Logic /tb_mips_sys/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpo1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/gpi1
-add wave -noupdate -divider UART
-add wave -noupdate -format Logic /tb_mips_sys/clk
-add wave -noupdate -format Logic /tb_mips_sys/rx
-add wave -noupdate -format Logic /tb_mips_sys/tx
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1165707237 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {3150 us}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo
deleted file mode 100644
index 1f1298b..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo
+++ /dev/null
@@ -1,61 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-
-# RAMS
-vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
-
-
-# FIFOS
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
-
-# UART
-#vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
-#vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
-#vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
-#vcom -explicit  -93 "../../../uart/uart_rx.vhd"
-#vcom -explicit  -93 "../../../uart/uart_tx.vhd"
-vcom -explicit  -93 "../../../uart/uart_wb.vhd"
-
-# GPIO
-vcom -explicit  -93 "../../../misc/gpio_wb.vhd"
-
-# Async port
-vcom -explicit  -93 "../../../misc/async_types.vhd"
-vcom -explicit  -93 "../../../misc/async_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs.vhd"
-
-# ROM
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../../../misc/rom_wb.vhd"
-
-# MIPS
-vcom -explicit  -93 "../src/core/mips_types.vhd"
-vcom -explicit  -93 "../src/core/mips_instr.vhd"
-vcom -explicit  -93 "../src/core/mips_reg.vhd"
-vcom -explicit  -93 "../src/core/mips_shifter.vhd"
-vcom -explicit  -93 "../src/core/mips_alu.vhd"
-vcom -explicit  -93 "../src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../src/core/mips_cop.vhd"
-vcom -explicit  -93 "../src/core/mips_icache.vhd"
-vcom -explicit  -93 "../src/core/mips_dcache.vhd"
-vcom -explicit  -93 "../src/core/mips_biu.vhd"
-vcom -explicit  -93 "../src/core/mips_bcu.vhd"
-vcom -explicit  -93 "../src/core/mips_pipeline.vhd"
-vcom -explicit  -93 "../src/core/mips_top.vhd"
-
-vcom -explicit  -93 "../src/tb_mips_top.vhd"
-vsim -t 1ps   -lib work tb_mips_top
-do {tb_mips_top.wdo}
-view wave
-view structure
-view signals
-run 1500us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
deleted file mode 100644
index 12b16c3..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo
+++ /dev/null
@@ -1,223 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {TOP interface}
-add wave -noupdate -format Logic /tb_mips_top/nmi
-add wave -noupdate -format Logic /tb_mips_top/rst
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/debug
-add wave -noupdate -format Logic /tb_mips_top/stb_o
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
-add wave -noupdate -format Logic /tb_mips_top/we_o
-add wave -noupdate -format Literal /tb_mips_top/sel_o
-add wave -noupdate -format Logic /tb_mips_top/cyc_o
-add wave -noupdate -format Logic /tb_mips_top/mrdy_o
-add wave -noupdate -format Literal /tb_mips_top/int
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout
-add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst
-add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst
-add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run
-add wave -noupdate -divider BIU
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en
-add wave -noupdate -divider {External components}
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0
-add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
-add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
-add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
-add wave -noupdate -format Logic /tb_mips_top/rx
-add wave -noupdate -format Logic /tb_mips_top/tx
-add wave -noupdate -divider {Interrupt Timer}
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/mem_area
-add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
-add wave -noupdate -format Logic /tb_mips_top/stb_o
-add wave -noupdate -format Logic /tb_mips_top/srdy_i
-add wave -noupdate -format Logic /tb_mips_top/we_o
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
-add wave -noupdate -format Logic /tb_mips_top/flash_we_n
-add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
-add wave -noupdate -format Literal /tb_mips_top/flash_be_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
-add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
-add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
-add wave -noupdate -format Literal /tb_mips_top/sram_be_n
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy
-add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
-add wave -noupdate -divider ALU
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu
-add wave -noupdate -divider PC
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc
-add wave -noupdate -divider COP0
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state
-add wave -noupdate -divider Pipestages
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -divider I-Cache
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
-add wave -noupdate -divider D-Cache
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
-add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din
-add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {Cursor {5877623 ps} 0}
-configure wave -namecolwidth 188
-configure wave -valuecolwidth 154
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {5846736 ps} {5910641 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
deleted file mode 100644
index 4c72deb..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.fdo
+++ /dev/null
@@ -1,55 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-
-# RAMS
-vcom -explicit  -93 "../../../misc/dpram_2w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w2r1c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r1c_sim.vhd"
-
-vcom -explicit  -93 "../../../misc/dpram_1w1r2c_sim.vhd"
-vcom -explicit  -93 "../../../misc/dpram_2w2r2c_sim.vhd"
-
-
-# FIFOS
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
-
-# UART
-vcom -explicit  -93 "../../../uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../uart/uart_tx.vhd"
-vcom -explicit  -93 "../../../uart/uart_wb.vhd"
-
-# GPIO
-vcom -explicit  -93 "../../../misc/gpio_wb.vhd"
-
-# Async port
-vcom -explicit  -93 "../../../misc/async_types.vhd"
-vcom -explicit  -93 "../../../misc/async_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs.vhd"
-
-# ROM
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../../../misc/rom_wb.vhd"
-
-# MIPS
-
-vcom -explicit  -93 "../syn/ise101/netgen/synthesis/mips_top_synthesis.vhd"
-vcom -explicit  -93 "../src/mips_top_syn.vhd"
-
-vcom -explicit  -93 "../src/tb_mips_top.vhd"
-vsim -t 1ps   -lib work tb_mips_top
-do {tb_mips_top_syn.wdo}
-view wave
-view structure
-view signals
-run 1500us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo
deleted file mode 100644
index 1dde5b7..0000000
--- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo
+++ /dev/null
@@ -1,104 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {TOP interface}
-add wave -noupdate -format Logic /tb_mips_top/nmi
-add wave -noupdate -format Logic /tb_mips_top/rst
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/debug
-add wave -noupdate -format Logic /tb_mips_top/stb_o
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
-add wave -noupdate -format Logic /tb_mips_top/we_o
-add wave -noupdate -format Literal /tb_mips_top/sel_o
-add wave -noupdate -format Logic /tb_mips_top/cyc_o
-add wave -noupdate -format Logic /tb_mips_top/mrdy_o
-add wave -noupdate -format Literal /tb_mips_top/int
-add wave -noupdate -divider BIU
-add wave -noupdate -divider {External components}
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1
-add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
-add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
-add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
-add wave -noupdate -format Logic /tb_mips_top/rx
-add wave -noupdate -format Logic /tb_mips_top/tx
-add wave -noupdate -divider {Interrupt Timer}
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
-add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal /tb_mips_top/mem_area
-add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
-add wave -noupdate -format Logic /tb_mips_top/stb_o
-add wave -noupdate -format Logic /tb_mips_top/srdy_i
-add wave -noupdate -format Logic /tb_mips_top/we_o
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en
-add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
-add wave -noupdate -format Logic /tb_mips_top/flash_we_n
-add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
-add wave -noupdate -format Literal /tb_mips_top/flash_be_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
-add wave -noupdate -format Logic /tb_mips_top/ack_i
-add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
-add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
-add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
-add wave -noupdate -format Literal /tb_mips_top/sram_be_n
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read
-add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy
-add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
-add wave -noupdate -divider ALU
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -divider PC
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -divider COP0
-add wave -noupdate -divider Pipestages
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -divider I-Cache
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -divider D-Cache
-add wave -noupdate -format Logic /tb_mips_top/rst
-add wave -noupdate -format Logic /tb_mips_top/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {Cursor {521186431 ps} 0}
-configure wave -namecolwidth 188
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {168108075 ps} {1570099575 ps}
diff --git a/lib/CPUs/MIPS/src/async_defs.vhd b/lib/CPUs/MIPS/src/async_defs.vhd
deleted file mode 100644
index ecb9f09..0000000
--- a/lib/CPUs/MIPS/src/async_defs.vhd
+++ /dev/null
@@ -1,68 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file: 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.async_types.all;
-
-package async_defs is
-
-	constant ts_flash : async_timespec_t :=
-	(
-		T_leadin			=> 00.0,
-		T_pulse_rd			=> 120.0,
-		T_pulse_wr			=> 70.0,
-		T_leadout			=> 00.0,
-		T_release			=> 40.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 30.0,
-		can_page_rd			=> true,
-		nbits_page_rd		=> 4,
-		pol_cs				=> '0',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-	constant ts_sram : async_timespec_t :=
-	(
-		T_leadin			=> 00.0,
-		T_pulse_rd			=> 10.0,
-		T_pulse_wr			=> 10.0,
-		T_leadout			=> 00.0,
-		T_release			=> 00.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 20.0,
-		can_page_rd			=> false,
-		nbits_page_rd		=> 5,
-		pol_cs				=> '0',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-end async_defs;
diff --git a/lib/CPUs/MIPS/src/bootloader.ROM.vhd b/lib/CPUs/MIPS/src/bootloader.ROM.vhd
deleted file mode 100644
index 1b0920c..0000000
--- a/lib/CPUs/MIPS/src/bootloader.ROM.vhd
+++ /dev/null
@@ -1,2082 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	constant word_array : word_array_t :=
-	(
-
-		X"3C1D8000", -- 00000000
-		X"27BDEFF0", -- 00000004
-		X"3C1A1040", -- 00000008
-		X"375A000C", -- 0000000C
-		X"409A6000", -- 00000010
-		X"241A0000", -- 00000014
-		X"409A6800", -- 00000018
-		X"401A7800", -- 0000001C
-		X"00000000", -- 00000020
-		X"409AF800", -- 00000024
-		X"42000020", -- 00000028
-		X"42000022", -- 0000002C
-		X"3C1ABFC0", -- 00000030
-		X"275A005C", -- 00000034
-		X"0340F809", -- 00000038
-		X"00000000", -- 0000003C
-		X"3C1ABFC0", -- 00000040
-		X"275A114C", -- 00000044
-		X"0340F809", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"0BF00014", -- 00000054
-		X"00000000", -- 00000058
-		X"3C1AA001", -- 0000005C
-		X"275A0008", -- 00000060
-		X"241B000D", -- 00000064
-		X"AF5B0000", -- 00000068
-		X"03E00008", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BC000", -- 00000184
-		X"001AD082", -- 00000188
-		X"335A000F", -- 0000018C
-		X"035BD025", -- 00000190
-		X"3C1BA000", -- 00000194
-		X"277B0000", -- 00000198
-		X"AF7A0000", -- 0000019C
-		X"401A6800", -- 000001A0
-		X"00000000", -- 000001A4
-		X"001AD202", -- 000001A8
-		X"335A00FF", -- 000001AC
-		X"1740FFFB", -- 000001B0
-		X"00000000", -- 000001B4
-		X"401A7000", -- 000001B8
-		X"00000000", -- 000001BC
-		X"03400008", -- 000001C0
-		X"42000010", -- 000001C4
-		X"40026000", -- 000001C8
-		X"03E00008", -- 000001CC
-		X"00000000", -- 000001D0
-		X"40846000", -- 000001D4
-		X"03E00008", -- 000001D8
-		X"00000000", -- 000001DC
-		X"40026800", -- 000001E0
-		X"03E00008", -- 000001E4
-		X"00000000", -- 000001E8
-		X"40846800", -- 000001EC
-		X"03E00008", -- 000001F0
-		X"00000000", -- 000001F4
-		X"40027800", -- 000001F8
-		X"03E00008", -- 000001FC
-		X"00000000", -- 00000200
-		X"3C02A001", -- 00000204
-		X"34430004", -- 00000208
-		X"8C620000", -- 0000020C
-		X"00000000", -- 00000210
-		X"30420010", -- 00000214
-		X"1040FFFC", -- 00000218
-		X"3C02A001", -- 0000021C
-		X"8C420000", -- 00000220
-		X"00000000", -- 00000224
-		X"00021600", -- 00000228
-		X"03E00008", -- 0000022C
-		X"00021603", -- 00000230
-		X"00042600", -- 00000234
-		X"3C02A001", -- 00000238
-		X"00042603", -- 0000023C
-		X"34430004", -- 00000240
-		X"8C620000", -- 00000244
-		X"00000000", -- 00000248
-		X"30420002", -- 0000024C
-		X"1440FFFC", -- 00000250
-		X"3C02A001", -- 00000254
-		X"AC440000", -- 00000258
-		X"03E00008", -- 0000025C
-		X"00000000", -- 00000260
-		X"00042600", -- 00000264
-		X"00042603", -- 00000268
-		X"2402000A", -- 0000026C
-		X"1482000A", -- 00000270
-		X"3C02A001", -- 00000274
-		X"34430004", -- 00000278
-		X"8C620000", -- 0000027C
-		X"00000000", -- 00000280
-		X"30420002", -- 00000284
-		X"1440FFFC", -- 00000288
-		X"3C02A001", -- 0000028C
-		X"2403000D", -- 00000290
-		X"AC430000", -- 00000294
-		X"3C02A001", -- 00000298
-		X"34430004", -- 0000029C
-		X"8C620000", -- 000002A0
-		X"00000000", -- 000002A4
-		X"30420002", -- 000002A8
-		X"1440FFFC", -- 000002AC
-		X"3C02A001", -- 000002B0
-		X"AC440000", -- 000002B4
-		X"03E00008", -- 000002B8
-		X"00000000", -- 000002BC
-		X"3C02A001", -- 000002C0
-		X"34470004", -- 000002C4
-		X"00802821", -- 000002C8
-		X"2409000A", -- 000002CC
-		X"3C06A001", -- 000002D0
-		X"0BF000C6", -- 000002D4
-		X"2408000D", -- 000002D8
-		X"14690007", -- 000002DC
-		X"00000000", -- 000002E0
-		X"8CE20000", -- 000002E4
-		X"00000000", -- 000002E8
-		X"30420002", -- 000002EC
-		X"1440FFFC", -- 000002F0
-		X"00000000", -- 000002F4
-		X"ACC80000", -- 000002F8
-		X"8CE20000", -- 000002FC
-		X"00000000", -- 00000300
-		X"30420002", -- 00000304
-		X"1440FFFC", -- 00000308
-		X"00000000", -- 0000030C
-		X"ACC30000", -- 00000310
-		X"24A50001", -- 00000314
-		X"80A30000", -- 00000318
-		X"00000000", -- 0000031C
-		X"1460FFEE", -- 00000320
-		X"00A41023", -- 00000324
-		X"03E00008", -- 00000328
-		X"00000000", -- 0000032C
-		X"00042600", -- 00000330
-		X"3C02A001", -- 00000334
-		X"00042603", -- 00000338
-		X"344A0004", -- 0000033C
-		X"00003821", -- 00000340
-		X"3C09A001", -- 00000344
-		X"24080002", -- 00000348
-		X"308200FF", -- 0000034C
-		X"00022902", -- 00000350
-		X"00041100", -- 00000354
-		X"00022600", -- 00000358
-		X"2CA3000A", -- 0000035C
-		X"00042603", -- 00000360
-		X"14600002", -- 00000364
-		X"24A60030", -- 00000368
-		X"24A60037", -- 0000036C
-		X"8D420000", -- 00000370
-		X"00000000", -- 00000374
-		X"30420002", -- 00000378
-		X"1440FFFC", -- 0000037C
-		X"00061600", -- 00000380
-		X"00021603", -- 00000384
-		X"24E70001", -- 00000388
-		X"AD220000", -- 0000038C
-		X"14E8FFEF", -- 00000390
-		X"308200FF", -- 00000394
-		X"03E00008", -- 00000398
-		X"00000000", -- 0000039C
-		X"27BDFFE0", -- 000003A0
-		X"AFB20018", -- 000003A4
-		X"AFB10014", -- 000003A8
-		X"AFB00010", -- 000003AC
-		X"AFBF001C", -- 000003B0
-		X"00808821", -- 000003B4
-		X"00008021", -- 000003B8
-		X"24120004", -- 000003BC
-		X"00112603", -- 000003C0
-		X"0FF000CC", -- 000003C4
-		X"26100001", -- 000003C8
-		X"1612FFFC", -- 000003CC
-		X"00118A00", -- 000003D0
-		X"8FBF001C", -- 000003D4
-		X"8FB20018", -- 000003D8
-		X"8FB10014", -- 000003DC
-		X"8FB00010", -- 000003E0
-		X"03E00008", -- 000003E4
-		X"27BD0020", -- 000003E8
-		X"27BDFFC8", -- 000003EC
-		X"AFB60028", -- 000003F0
-		X"AFBF0034", -- 000003F4
-		X"AFBE0030", -- 000003F8
-		X"AFB7002C", -- 000003FC
-		X"AFB50024", -- 00000400
-		X"AFB40020", -- 00000404
-		X"AFB3001C", -- 00000408
-		X"AFB20018", -- 0000040C
-		X"AFB10014", -- 00000410
-		X"AFB00010", -- 00000414
-		X"00801021", -- 00000418
-		X"10A00002", -- 0000041C
-		X"00C0B021", -- 00000420
-		X"00002021", -- 00000424
-		X"00409821", -- 00000428
-		X"3C02A001", -- 0000042C
-		X"00E09021", -- 00000430
-		X"0080A821", -- 00000434
-		X"345E0004", -- 00000438
-		X"00E0A021", -- 0000043C
-		X"3C17A001", -- 00000440
-		X"0FF000E8", -- 00000444
-		X"02A02021", -- 00000448
-		X"3C04BFC0", -- 0000044C
-		X"0FF000B0", -- 00000450
-		X"2484169C", -- 00000454
-		X"02608821", -- 00000458
-		X"0BF00128", -- 0000045C
-		X"00008021", -- 00000460
-		X"12400009", -- 00000464
-		X"00000000", -- 00000468
-		X"82240000", -- 0000046C
-		X"0FF000CC", -- 00000470
-		X"2652FFFF", -- 00000474
-		X"3C04BFC0", -- 00000478
-		X"0FF000B0", -- 0000047C
-		X"24841774", -- 00000480
-		X"0BF00128", -- 00000484
-		X"26310001", -- 00000488
-		X"3C04BFC0", -- 0000048C
-		X"0FF000B0", -- 00000490
-		X"248416A0", -- 00000494
-		X"0BF0012C", -- 00000498
-		X"3C04BFC0", -- 0000049C
-		X"0216102A", -- 000004A0
-		X"1440FFEF", -- 000004A4
-		X"26100001", -- 000004A8
-		X"3C04BFC0", -- 000004AC
-		X"0FF000B0", -- 000004B0
-		X"248416A0", -- 000004B4
-		X"02602821", -- 000004B8
-		X"0BF00155", -- 000004BC
-		X"00002021", -- 000004C0
-		X"1280001E", -- 000004C4
-		X"00000000", -- 000004C8
-		X"90A30000", -- 000004CC
-		X"00000000", -- 000004D0
-		X"2462FFE0", -- 000004D4
-		X"304200FF", -- 000004D8
-		X"2C420060", -- 000004DC
-		X"14400003", -- 000004E0
-		X"00031E00", -- 000004E4
-		X"2403002E", -- 000004E8
-		X"00031E00", -- 000004EC
-		X"00031E03", -- 000004F0
-		X"2402000A", -- 000004F4
-		X"14620007", -- 000004F8
-		X"00000000", -- 000004FC
-		X"8FC20000", -- 00000500
-		X"00000000", -- 00000504
-		X"30420002", -- 00000508
-		X"1440FFFC", -- 0000050C
-		X"2402000D", -- 00000510
-		X"AEE20000", -- 00000514
-		X"8FC20000", -- 00000518
-		X"00000000", -- 0000051C
-		X"30420002", -- 00000520
-		X"1440FFFC", -- 00000524
-		X"00000000", -- 00000528
-		X"AEE30000", -- 0000052C
-		X"2694FFFF", -- 00000530
-		X"24840001", -- 00000534
-		X"0BF00155", -- 00000538
-		X"24A50001", -- 0000053C
-		X"3C04BFC0", -- 00000540
-		X"0FF000B0", -- 00000544
-		X"24841774", -- 00000548
-		X"0BF00159", -- 0000054C
-		X"3C04BFC0", -- 00000550
-		X"0096102A", -- 00000554
-		X"1440FFDA", -- 00000558
-		X"00000000", -- 0000055C
-		X"3C04BFC0", -- 00000560
-		X"0FF000B0", -- 00000564
-		X"248416C8", -- 00000568
-		X"02B6A821", -- 0000056C
-		X"1640FFB4", -- 00000570
-		X"02769821", -- 00000574
-		X"8FBF0034", -- 00000578
-		X"8FBE0030", -- 0000057C
-		X"8FB7002C", -- 00000580
-		X"8FB60028", -- 00000584
-		X"8FB50024", -- 00000588
-		X"8FB40020", -- 0000058C
-		X"8FB3001C", -- 00000590
-		X"8FB20018", -- 00000594
-		X"8FB10014", -- 00000598
-		X"8FB00010", -- 0000059C
-		X"03E00008", -- 000005A0
-		X"27BD0038", -- 000005A4
-		X"00C03821", -- 000005A8
-		X"00A03021", -- 000005AC
-		X"0BF000FB", -- 000005B0
-		X"24050001", -- 000005B4
-		X"8C840000", -- 000005B8
-		X"3C020070", -- 000005BC
-		X"34420070", -- 000005C0
-		X"3C0300FF", -- 000005C4
-		X"AC820000", -- 000005C8
-		X"346300FF", -- 000005CC
-		X"8C820000", -- 000005D0
-		X"AC830000", -- 000005D4
-		X"03E00008", -- 000005D8
-		X"00000000", -- 000005DC
-		X"27BDFFF8", -- 000005E0
-		X"AC850000", -- 000005E4
-		X"24820008", -- 000005E8
-		X"0BF0017F", -- 000005EC
-		X"24830020", -- 000005F0
-		X"A0400000", -- 000005F4
-		X"24420001", -- 000005F8
-		X"1443FFFD", -- 000005FC
-		X"00000000", -- 00000600
-		X"24020001", -- 00000604
-		X"AC820004", -- 00000608
-		X"03E00008", -- 0000060C
-		X"27BD0008", -- 00000610
-		X"8C870000", -- 00000614
-		X"3C020098", -- 00000618
-		X"34420098", -- 0000061C
-		X"ACE20000", -- 00000620
-		X"3C0200FF", -- 00000624
-		X"344200FF", -- 00000628
-		X"ACE20000", -- 0000062C
-		X"3C020090", -- 00000630
-		X"34420090", -- 00000634
-		X"ACE20000", -- 00000638
-		X"00804021", -- 0000063C
-		X"94E4009C", -- 00000640
-		X"24030002", -- 00000644
-		X"24020020", -- 00000648
-		X"AD030008", -- 0000064C
-		X"AD03001C", -- 00000650
-		X"AD020018", -- 00000654
-		X"3084FFFF", -- 00000658
-		X"0BF0019D", -- 0000065C
-		X"00001821", -- 00000660
-		X"8D020008", -- 00000664
-		X"00000000", -- 00000668
-		X"00021040", -- 0000066C
-		X"AD020008", -- 00000670
-		X"0064102B", -- 00000674
-		X"1440FFFA", -- 00000678
-		X"24630001", -- 0000067C
-		X"94E200AC", -- 00000680
-		X"94E300A8", -- 00000684
-		X"3042FFFF", -- 00000688
-		X"8D04001C", -- 0000068C
-		X"3063FFFF", -- 00000690
-		X"00021200", -- 00000694
-		X"00432825", -- 00000698
-		X"AD040014", -- 0000069C
-		X"0BF001AE", -- 000006A0
-		X"00001821", -- 000006A4
-		X"8D020014", -- 000006A8
-		X"00000000", -- 000006AC
-		X"00021040", -- 000006B0
-		X"AD020014", -- 000006B4
-		X"0065102B", -- 000006B8
-		X"1440FFFA", -- 000006BC
-		X"24630001", -- 000006C0
-		X"94E300B8", -- 000006C4
-		X"94E600B4", -- 000006C8
-		X"94E200C0", -- 000006CC
-		X"94E400BC", -- 000006D0
-		X"8D05001C", -- 000006D4
-		X"3042FFFF", -- 000006D8
-		X"3084FFFF", -- 000006DC
-		X"00021200", -- 000006E0
-		X"00441025", -- 000006E4
-		X"00052A00", -- 000006E8
-		X"00A20018", -- 000006EC
-		X"3063FFFF", -- 000006F0
-		X"30C6FFFF", -- 000006F4
-		X"00031A00", -- 000006F8
-		X"00661825", -- 000006FC
-		X"24630001", -- 00000700
-		X"AD030010", -- 00000704
-		X"3C0300FF", -- 00000708
-		X"346300FF", -- 0000070C
-		X"00001021", -- 00000710
-		X"00002812", -- 00000714
-		X"AD05000C", -- 00000718
-		X"ACE30000", -- 0000071C
-		X"03E00008", -- 00000720
-		X"00000000", -- 00000724
-		X"8C820008", -- 00000728
-		X"8C860000", -- 0000072C
-		X"00021082", -- 00000730
-		X"00A2102B", -- 00000734
-		X"14400004", -- 00000738
-		X"3C030090", -- 0000073C
-		X"3C028010", -- 00000740
-		X"03E00008", -- 00000744
-		X"34420002", -- 00000748
-		X"8C820010", -- 0000074C
-		X"00000000", -- 00000750
-		X"2442FFFF", -- 00000754
-		X"00021400", -- 00000758
-		X"00A21024", -- 0000075C
-		X"24420002", -- 00000760
-		X"34630090", -- 00000764
-		X"00021080", -- 00000768
-		X"ACC30000", -- 0000076C
-		X"00C21021", -- 00000770
-		X"8C430000", -- 00000774
-		X"3C020001", -- 00000778
-		X"34420001", -- 0000077C
-		X"00621824", -- 00000780
-		X"3C0200FF", -- 00000784
-		X"344200FF", -- 00000788
-		X"ACC20000", -- 0000078C
-		X"03E00008", -- 00000790
-		X"0003102B", -- 00000794
-		X"8C820008", -- 00000798
-		X"00A01821", -- 0000079C
-		X"00021082", -- 000007A0
-		X"00A2102B", -- 000007A4
-		X"8C850000", -- 000007A8
-		X"14400003", -- 000007AC
-		X"3C028010", -- 000007B0
-		X"0BF0020C", -- 000007B4
-		X"34430002", -- 000007B8
-		X"8C820010", -- 000007BC
-		X"00000000", -- 000007C0
-		X"2442FFFF", -- 000007C4
-		X"00021400", -- 000007C8
-		X"00621024", -- 000007CC
-		X"00021080", -- 000007D0
-		X"00A22021", -- 000007D4
-		X"3C020020", -- 000007D8
-		X"34420020", -- 000007DC
-		X"AC820000", -- 000007E0
-		X"3C0200D0", -- 000007E4
-		X"344200D0", -- 000007E8
-		X"AC820000", -- 000007EC
-		X"3C020080", -- 000007F0
-		X"34430080", -- 000007F4
-		X"8C860000", -- 000007F8
-		X"00000000", -- 000007FC
-		X"00C31024", -- 00000800
-		X"1443FFFC", -- 00000804
-		X"3C02002A", -- 00000808
-		X"3442002A", -- 0000080C
-		X"00C21024", -- 00000810
-		X"10400003", -- 00000814
-		X"00001821", -- 00000818
-		X"3C029010", -- 0000081C
-		X"00C21825", -- 00000820
-		X"3C0200FF", -- 00000824
-		X"344200FF", -- 00000828
-		X"AC820000", -- 0000082C
-		X"03E00008", -- 00000830
-		X"00601021", -- 00000834
-		X"8C820008", -- 00000838
-		X"00A01821", -- 0000083C
-		X"00021082", -- 00000840
-		X"00A2102B", -- 00000844
-		X"8C850000", -- 00000848
-		X"14400003", -- 0000084C
-		X"3C028010", -- 00000850
-		X"0BF00234", -- 00000854
-		X"34430002", -- 00000858
-		X"8C820010", -- 0000085C
-		X"00000000", -- 00000860
-		X"2442FFFF", -- 00000864
-		X"00021400", -- 00000868
-		X"00621024", -- 0000086C
-		X"00021080", -- 00000870
-		X"00A22021", -- 00000874
-		X"3C020060", -- 00000878
-		X"34420060", -- 0000087C
-		X"AC820000", -- 00000880
-		X"3C020001", -- 00000884
-		X"34420001", -- 00000888
-		X"AC820000", -- 0000088C
-		X"3C020080", -- 00000890
-		X"34430080", -- 00000894
-		X"8C860000", -- 00000898
-		X"00000000", -- 0000089C
-		X"00C31024", -- 000008A0
-		X"1443FFFC", -- 000008A4
-		X"3C020038", -- 000008A8
-		X"34420038", -- 000008AC
-		X"00C21024", -- 000008B0
-		X"10400003", -- 000008B4
-		X"00001821", -- 000008B8
-		X"3C029010", -- 000008BC
-		X"00C21825", -- 000008C0
-		X"3C0200FF", -- 000008C4
-		X"344200FF", -- 000008C8
-		X"AC820000", -- 000008CC
-		X"03E00008", -- 000008D0
-		X"00601021", -- 000008D4
-		X"8C820008", -- 000008D8
-		X"00A01821", -- 000008DC
-		X"00021082", -- 000008E0
-		X"00A2102B", -- 000008E4
-		X"8C850000", -- 000008E8
-		X"14400003", -- 000008EC
-		X"3C028010", -- 000008F0
-		X"0BF0025C", -- 000008F4
-		X"34430002", -- 000008F8
-		X"8C820010", -- 000008FC
-		X"00000000", -- 00000900
-		X"2442FFFF", -- 00000904
-		X"00021400", -- 00000908
-		X"00621024", -- 0000090C
-		X"00021080", -- 00000910
-		X"00A22021", -- 00000914
-		X"3C020060", -- 00000918
-		X"34420060", -- 0000091C
-		X"AC820000", -- 00000920
-		X"3C0200D0", -- 00000924
-		X"344200D0", -- 00000928
-		X"AC820000", -- 0000092C
-		X"3C020080", -- 00000930
-		X"34430080", -- 00000934
-		X"8C860000", -- 00000938
-		X"00000000", -- 0000093C
-		X"00C31024", -- 00000940
-		X"1443FFFC", -- 00000944
-		X"3C020038", -- 00000948
-		X"34420038", -- 0000094C
-		X"00C21024", -- 00000950
-		X"10400003", -- 00000954
-		X"00001821", -- 00000958
-		X"3C029010", -- 0000095C
-		X"00C21825", -- 00000960
-		X"3C0200FF", -- 00000964
-		X"344200FF", -- 00000968
-		X"AC820000", -- 0000096C
-		X"03E00008", -- 00000970
-		X"00601021", -- 00000974
-		X"8C820008", -- 00000978
-		X"8C840000", -- 0000097C
-		X"00021082", -- 00000980
-		X"00A2102B", -- 00000984
-		X"14400003", -- 00000988
-		X"3C028010", -- 0000098C
-		X"0BF0027C", -- 00000990
-		X"34430002", -- 00000994
-		X"00051080", -- 00000998
-		X"00822021", -- 0000099C
-		X"3C020040", -- 000009A0
-		X"34420040", -- 000009A4
-		X"AC820000", -- 000009A8
-		X"3C020080", -- 000009AC
-		X"AC860000", -- 000009B0
-		X"34430080", -- 000009B4
-		X"8C860000", -- 000009B8
-		X"00000000", -- 000009BC
-		X"00C31024", -- 000009C0
-		X"1443FFFC", -- 000009C4
-		X"3C02001A", -- 000009C8
-		X"3442001A", -- 000009CC
-		X"00C21024", -- 000009D0
-		X"10400003", -- 000009D4
-		X"00001821", -- 000009D8
-		X"3C029010", -- 000009DC
-		X"00C21825", -- 000009E0
-		X"3C0200FF", -- 000009E4
-		X"344200FF", -- 000009E8
-		X"AC820000", -- 000009EC
-		X"03E00008", -- 000009F0
-		X"00601021", -- 000009F4
-		X"8C820008", -- 000009F8
-		X"27BDFFE8", -- 000009FC
-		X"00021082", -- 00000A00
-		X"00A2102B", -- 00000A04
-		X"AFB40014", -- 00000A08
-		X"AFB30010", -- 00000A0C
-		X"AFB2000C", -- 00000A10
-		X"AFB10008", -- 00000A14
-		X"AFB00004", -- 00000A18
-		X"0080C021", -- 00000A1C
-		X"8C8E0000", -- 00000A20
-		X"14400004", -- 00000A24
-		X"00C0A021", -- 00000A28
-		X"3C028010", -- 00000A2C
-		X"0BF002E3", -- 00000A30
-		X"34440002", -- 00000A34
-		X"8C820010", -- 00000A38
-		X"00006821", -- 00000A3C
-		X"2442FFFF", -- 00000A40
-		X"0002CC00", -- 00000A44
-		X"3C0200E8", -- 00000A48
-		X"345300E8", -- 00000A4C
-		X"3C020080", -- 00000A50
-		X"344F0080", -- 00000A54
-		X"3C02001A", -- 00000A58
-		X"3446001A", -- 00000A5C
-		X"3C0200D0", -- 00000A60
-		X"345200D0", -- 00000A64
-		X"3C0200FF", -- 00000A68
-		X"345100FF", -- 00000A6C
-		X"0BF002E1", -- 00000A70
-		X"3C100001", -- 00000A74
-		X"01851023", -- 00000A78
-		X"00505021", -- 00000A7C
-		X"00EA102B", -- 00000A80
-		X"10400002", -- 00000A84
-		X"000C1080", -- 00000A88
-		X"00E05021", -- 00000A8C
-		X"0BF002D7", -- 00000A90
-		X"01C25821", -- 00000A94
-		X"AD730000", -- 00000A98
-		X"8D630000", -- 00000A9C
-		X"00000000", -- 00000AA0
-		X"006F1024", -- 00000AA4
-		X"144FFFFC", -- 00000AA8
-		X"00661024", -- 00000AAC
-		X"14400026", -- 00000AB0
-		X"3C029010", -- 00000AB4
-		X"8F020014", -- 00000AB8
-		X"00000000", -- 00000ABC
-		X"00021882", -- 00000AC0
-		X"006A102B", -- 00000AC4
-		X"10400002", -- 00000AC8
-		X"01404021", -- 00000ACC
-		X"00604021", -- 00000AD0
-		X"2503FFFF", -- 00000AD4
-		X"00031400", -- 00000AD8
-		X"00431025", -- 00000ADC
-		X"00052080", -- 00000AE0
-		X"000D1880", -- 00000AE4
-		X"02834821", -- 00000AE8
-		X"AD620000", -- 00000AEC
-		X"01C42021", -- 00000AF0
-		X"0BF002C3", -- 00000AF4
-		X"00001821", -- 00000AF8
-		X"8D220000", -- 00000AFC
-		X"25290004", -- 00000B00
-		X"AC820000", -- 00000B04
-		X"24840004", -- 00000B08
-		X"0068102B", -- 00000B0C
-		X"1440FFFA", -- 00000B10
-		X"24630001", -- 00000B14
-		X"01A86821", -- 00000B18
-		X"00A82821", -- 00000B1C
-		X"00E83823", -- 00000B20
-		X"AD720000", -- 00000B24
-		X"8D630000", -- 00000B28
-		X"00000000", -- 00000B2C
-		X"006F1024", -- 00000B30
-		X"144FFFFC", -- 00000B34
-		X"00661024", -- 00000B38
-		X"10400005", -- 00000B3C
-		X"01485023", -- 00000B40
-		X"01485021", -- 00000B44
-		X"3C029010", -- 00000B48
-		X"0BF002D9", -- 00000B4C
-		X"00622025", -- 00000B50
-		X"AD710000", -- 00000B54
-		X"00002021", -- 00000B58
-		X"1540FFCE", -- 00000B5C
-		X"00000000", -- 00000B60
-		X"04810007", -- 00000B64
-		X"000C1880", -- 00000B68
-		X"3C0200FF", -- 00000B6C
-		X"01C31821", -- 00000B70
-		X"344200FF", -- 00000B74
-		X"AC620000", -- 00000B78
-		X"0BF002E4", -- 00000B7C
-		X"00801021", -- 00000B80
-		X"14E0FFBC", -- 00000B84
-		X"00B96024", -- 00000B88
-		X"00801021", -- 00000B8C
-		X"8FB40014", -- 00000B90
-		X"8FB30010", -- 00000B94
-		X"8FB2000C", -- 00000B98
-		X"8FB10008", -- 00000B9C
-		X"8FB00004", -- 00000BA0
-		X"03E00008", -- 00000BA4
-		X"27BD0018", -- 00000BA8
-		X"27BDFFE0", -- 00000BAC
-		X"AFBF001C", -- 00000BB0
-		X"AC850000", -- 00000BB4
-		X"24820008", -- 00000BB8
-		X"0BF002F3", -- 00000BBC
-		X"24830020", -- 00000BC0
-		X"A0400000", -- 00000BC4
-		X"24420001", -- 00000BC8
-		X"1443FFFD", -- 00000BCC
-		X"00000000", -- 00000BD0
-		X"3C021234", -- 00000BD4
-		X"34425678", -- 00000BD8
-		X"00021E02", -- 00000BDC
-		X"AFA20010", -- 00000BE0
-		X"24020012", -- 00000BE4
-		X"14620003", -- 00000BE8
-		X"AC800004", -- 00000BEC
-		X"24020001", -- 00000BF0
-		X"AC820004", -- 00000BF4
-		X"0FF00185", -- 00000BF8
-		X"00000000", -- 00000BFC
-		X"8FBF001C", -- 00000C00
-		X"00000000", -- 00000C04
-		X"03E00008", -- 00000C08
-		X"27BD0020", -- 00000C0C
-		X"27BDFFD8", -- 00000C10
-		X"30C20003", -- 00000C14
-		X"AFB2001C", -- 00000C18
-		X"AFBF0024", -- 00000C1C
-		X"AFB30020", -- 00000C20
-		X"AFB10018", -- 00000C24
-		X"AFB00014", -- 00000C28
-		X"10400004", -- 00000C2C
-		X"00809021", -- 00000C30
-		X"00061082", -- 00000C34
-		X"24420001", -- 00000C38
-		X"00023080", -- 00000C3C
-		X"00C59821", -- 00000C40
-		X"0BF00324", -- 00000C44
-		X"00A08821", -- 00000C48
-		X"0FF001CA", -- 00000C4C
-		X"00000000", -- 00000C50
-		X"02402021", -- 00000C54
-		X"10400005", -- 00000C58
-		X"02002821", -- 00000C5C
-		X"0FF00236", -- 00000C60
-		X"00000000", -- 00000C64
-		X"04400011", -- 00000C68
-		X"00401821", -- 00000C6C
-		X"02002821", -- 00000C70
-		X"0FF001E6", -- 00000C74
-		X"02402021", -- 00000C78
-		X"0440000C", -- 00000C7C
-		X"00401821", -- 00000C80
-		X"8E42000C", -- 00000C84
-		X"00000000", -- 00000C88
-		X"02228821", -- 00000C8C
-		X"001117C3", -- 00000C90
-		X"00021782", -- 00000C94
-		X"00511021", -- 00000C98
-		X"00028083", -- 00000C9C
-		X"0233102B", -- 00000CA0
-		X"02402021", -- 00000CA4
-		X"1440FFE8", -- 00000CA8
-		X"02002821", -- 00000CAC
-		X"8FBF0024", -- 00000CB0
-		X"00601021", -- 00000CB4
-		X"8FB30020", -- 00000CB8
-		X"8FB2001C", -- 00000CBC
-		X"8FB10018", -- 00000CC0
-		X"8FB00014", -- 00000CC4
-		X"03E00008", -- 00000CC8
-		X"27BD0028", -- 00000CCC
-		X"30E20003", -- 00000CD0
-		X"10400003", -- 00000CD4
-		X"00071082", -- 00000CD8
-		X"24420001", -- 00000CDC
-		X"00023880", -- 00000CE0
-		X"00052882", -- 00000CE4
-		X"0BF0027E", -- 00000CE8
-		X"00073882", -- 00000CEC
-		X"8C820000", -- 00000CF0
-		X"00002021", -- 00000CF4
-		X"0BF00347", -- 00000CF8
-		X"00454021", -- 00000CFC
-		X"90630000", -- 00000D00
-		X"90A20000", -- 00000D04
-		X"00000000", -- 00000D08
-		X"10620003", -- 00000D0C
-		X"3C028010", -- 00000D10
-		X"03E00008", -- 00000D14
-		X"34420003", -- 00000D18
-		X"0087102B", -- 00000D1C
-		X"01041821", -- 00000D20
-		X"00C42821", -- 00000D24
-		X"1440FFF5", -- 00000D28
-		X"24840001", -- 00000D2C
-		X"03E00008", -- 00000D30
-		X"00000000", -- 00000D34
-		X"8C82000C", -- 00000D38
-		X"00000000", -- 00000D3C
-		X"14400002", -- 00000D40
-		X"00A2001B", -- 00000D44
-		X"0007000D", -- 00000D48
-		X"00001010", -- 00000D4C
-		X"0002102B", -- 00000D50
-		X"00002812", -- 00000D54
-		X"03E00008", -- 00000D58
-		X"00A21021", -- 00000D5C
-		X"8C830010", -- 00000D60
-		X"00000000", -- 00000D64
-		X"00A3102B", -- 00000D68
-		X"14400002", -- 00000D6C
-		X"00000000", -- 00000D70
-		X"2465FFFF", -- 00000D74
-		X"8C82000C", -- 00000D78
-		X"00000000", -- 00000D7C
-		X"00A20018", -- 00000D80
-		X"00001012", -- 00000D84
-		X"03E00008", -- 00000D88
-		X"00000000", -- 00000D8C
-		X"27BDFFE8", -- 00000D90
-		X"AFBF0014", -- 00000D94
-		X"AFB00010", -- 00000D98
-		X"0FF0034E", -- 00000D9C
-		X"00808021", -- 00000DA0
-		X"8E03000C", -- 00000DA4
-		X"8FBF0014", -- 00000DA8
-		X"00430018", -- 00000DAC
-		X"8FB00010", -- 00000DB0
-		X"00001012", -- 00000DB4
-		X"03E00008", -- 00000DB8
-		X"27BD0018", -- 00000DBC
-		X"90830000", -- 00000DC0
-		X"00000000", -- 00000DC4
-		X"2C620041", -- 00000DC8
-		X"14400002", -- 00000DCC
-		X"2462FFD0", -- 00000DD0
-		X"2462FFC9", -- 00000DD4
-		X"90840001", -- 00000DD8
-		X"304200FF", -- 00000DDC
-		X"304300FF", -- 00000DE0
-		X"2C820041", -- 00000DE4
-		X"14400003", -- 00000DE8
-		X"00000000", -- 00000DEC
-		X"0BF0037F", -- 00000DF0
-		X"2482FFC9", -- 00000DF4
-		X"2482FFD0", -- 00000DF8
-		X"304400FF", -- 00000DFC
-		X"00031100", -- 00000E00
-		X"00821025", -- 00000E04
-		X"03E00008", -- 00000E08
-		X"304200FF", -- 00000E0C
-		X"10C00094", -- 00000E10
-		X"00805021", -- 00000E14
-		X"24020003", -- 00000E18
-		X"AC820008", -- 00000E1C
-		X"90A40001", -- 00000E20
-		X"00000000", -- 00000E24
-		X"2482FFCF", -- 00000E28
-		X"304200FF", -- 00000E2C
-		X"2C420003", -- 00000E30
-		X"10400005", -- 00000E34
-		X"2482FFC9", -- 00000E38
-		X"24020002", -- 00000E3C
-		X"AD420008", -- 00000E40
-		X"0BF003A1", -- 00000E44
-		X"2489FFD1", -- 00000E48
-		X"304200FF", -- 00000E4C
-		X"2C420003", -- 00000E50
-		X"10400006", -- 00000E54
-		X"24020030", -- 00000E58
-		X"2402003B", -- 00000E5C
-		X"00444823", -- 00000E60
-		X"24020004", -- 00000E64
-		X"0BF003A1", -- 00000E68
-		X"AD420008", -- 00000E6C
-		X"14820004", -- 00000E70
-		X"00004821", -- 00000E74
-		X"24020001", -- 00000E78
-		X"AD420008", -- 00000E7C
-		X"24090002", -- 00000E80
-		X"90A30002", -- 00000E84
-		X"00000000", -- 00000E88
-		X"2C620041", -- 00000E8C
-		X"10400003", -- 00000E90
-		X"24A40002", -- 00000E94
-		X"0BF003A9", -- 00000E98
-		X"2462FFD0", -- 00000E9C
-		X"2462FFC9", -- 00000EA0
-		X"90830001", -- 00000EA4
-		X"304200FF", -- 00000EA8
-		X"304400FF", -- 00000EAC
-		X"2C620041", -- 00000EB0
-		X"10400002", -- 00000EB4
-		X"2462FFC9", -- 00000EB8
-		X"2462FFD0", -- 00000EBC
-		X"304300FF", -- 00000EC0
-		X"00041100", -- 00000EC4
-		X"00621025", -- 00000EC8
-		X"304200FF", -- 00000ECC
-		X"AD420004", -- 00000ED0
-		X"AD400000", -- 00000ED4
-		X"00405821", -- 00000ED8
-		X"00A03021", -- 00000EDC
-		X"0BF003D5", -- 00000EE0
-		X"00003821", -- 00000EE4
-		X"90C20004", -- 00000EE8
-		X"00000000", -- 00000EEC
-		X"2443FFC9", -- 00000EF0
-		X"2444FFD0", -- 00000EF4
-		X"2C420041", -- 00000EF8
-		X"10400002", -- 00000EFC
-		X"306300FF", -- 00000F00
-		X"308300FF", -- 00000F04
-		X"90C20005", -- 00000F08
-		X"306800FF", -- 00000F0C
-		X"2444FFC9", -- 00000F10
-		X"2443FFD0", -- 00000F14
-		X"2C420041", -- 00000F18
-		X"10400002", -- 00000F1C
-		X"308400FF", -- 00000F20
-		X"306400FF", -- 00000F24
-		X"8D430000", -- 00000F28
-		X"00081100", -- 00000F2C
-		X"00821025", -- 00000F30
-		X"304200FF", -- 00000F34
-		X"00031A00", -- 00000F38
-		X"004B2021", -- 00000F3C
-		X"00431025", -- 00000F40
-		X"AD420000", -- 00000F44
-		X"308B00FF", -- 00000F48
-		X"24E70001", -- 00000F4C
-		X"24C60002", -- 00000F50
-		X"00E9102A", -- 00000F54
-		X"1440FFE3", -- 00000F58
-		X"25220002", -- 00000F5C
-		X"8D440004", -- 00000F60
-		X"00021040", -- 00000F64
-		X"00091827", -- 00000F68
-		X"00832021", -- 00000F6C
-		X"00A21021", -- 00000F70
-		X"AD440004", -- 00000F74
-		X"AD42000C", -- 00000F78
-		X"0BF003F9", -- 00000F7C
-		X"00003021", -- 00000F80
-		X"90E20000", -- 00000F84
-		X"00000000", -- 00000F88
-		X"2444FFC9", -- 00000F8C
-		X"2445FFD0", -- 00000F90
-		X"2C420041", -- 00000F94
-		X"10400002", -- 00000F98
-		X"308400FF", -- 00000F9C
-		X"30A400FF", -- 00000FA0
-		X"90E20001", -- 00000FA4
-		X"308700FF", -- 00000FA8
-		X"2445FFC9", -- 00000FAC
-		X"2444FFD0", -- 00000FB0
-		X"2C420041", -- 00000FB4
-		X"14400002", -- 00000FB8
-		X"308400FF", -- 00000FBC
-		X"30A400FF", -- 00000FC0
-		X"00071100", -- 00000FC4
-		X"00821025", -- 00000FC8
-		X"304200FF", -- 00000FCC
-		X"00661821", -- 00000FD0
-		X"004B2021", -- 00000FD4
-		X"A0620000", -- 00000FD8
-		X"308B00FF", -- 00000FDC
-		X"24C60001", -- 00000FE0
-		X"8D420004", -- 00000FE4
-		X"8D43000C", -- 00000FE8
-		X"00062040", -- 00000FEC
-		X"00C2102A", -- 00000FF0
-		X"1440FFE3", -- 00000FF4
-		X"00643821", -- 00000FF8
-		X"90E40000", -- 00000FFC
-		X"00000000", -- 00001000
-		X"2C820041", -- 00001004
-		X"10400003", -- 00001008
-		X"00E01821", -- 0000100C
-		X"0BF00407", -- 00001010
-		X"2482FFD0", -- 00001014
-		X"2482FFC9", -- 00001018
-		X"90630001", -- 0000101C
-		X"304200FF", -- 00001020
-		X"304400FF", -- 00001024
-		X"2C620041", -- 00001028
-		X"10400002", -- 0000102C
-		X"2462FFC9", -- 00001030
-		X"2462FFD0", -- 00001034
-		X"304200FF", -- 00001038
-		X"00041900", -- 0000103C
-		X"00431825", -- 00001040
-		X"000B1027", -- 00001044
-		X"304200FF", -- 00001048
-		X"306300FF", -- 0000104C
-		X"14430004", -- 00001050
-		X"00000000", -- 00001054
-		X"8D420008", -- 00001058
-		X"03E00008", -- 0000105C
-		X"00000000", -- 00001060
-		X"03E00008", -- 00001064
-		X"00001021", -- 00001068
-		X"00800008", -- 0000106C
-		X"00000000", -- 00001070
-		X"03E00008", -- 00001074
-		X"00000000", -- 00001078
-		X"3C1A1000", -- 0000107C
-		X"409A6000", -- 00001080
-		X"00800008", -- 00001084
-		X"42000010", -- 00001088
-		X"03E00008", -- 0000108C
-		X"00000000", -- 00001090
-		X"401A6000", -- 00001094
-		X"3C1BFFBF", -- 00001098
-		X"377BFFFF", -- 0000109C
-		X"035BD024", -- 000010A0
-		X"3C1B0200", -- 000010A4
-		X"035BD025", -- 000010A8
-		X"409A6000", -- 000010AC
-		X"00800008", -- 000010B0
-		X"42000010", -- 000010B4
-		X"03E00008", -- 000010B8
-		X"00000000", -- 000010BC
-		X"27BDFFD8", -- 000010C0
-		X"AFB30020", -- 000010C4
-		X"AFB10018", -- 000010C8
-		X"AFB00014", -- 000010CC
-		X"AFBF0024", -- 000010D0
-		X"AFB2001C", -- 000010D4
-		X"00809821", -- 000010D8
-		X"24110073", -- 000010DC
-		X"24100053", -- 000010E0
-		X"0FF00081", -- 000010E4
-		X"00000000", -- 000010E8
-		X"14510005", -- 000010EC
-		X"00000000", -- 000010F0
-		X"00008021", -- 000010F4
-		X"2412000A", -- 000010F8
-		X"0BF00449", -- 000010FC
-		X"2411000D", -- 00001100
-		X"1450FFF7", -- 00001104
-		X"00000000", -- 00001108
-		X"0BF0043E", -- 0000110C
-		X"00008021", -- 00001110
-		X"0FF00081", -- 00001114
-		X"A0620000", -- 00001118
-		X"10510003", -- 0000111C
-		X"26100001", -- 00001120
-		X"1452FFFB", -- 00001124
-		X"02701821", -- 00001128
-		X"8FBF0024", -- 0000112C
-		X"02001021", -- 00001130
-		X"8FB30020", -- 00001134
-		X"8FB2001C", -- 00001138
-		X"8FB10018", -- 0000113C
-		X"8FB00014", -- 00001140
-		X"03E00008", -- 00001144
-		X"27BD0028", -- 00001148
-		X"27BDFD98", -- 0000114C
-		X"27A40140", -- 00001150
-		X"00002821", -- 00001154
-		X"24060100", -- 00001158
-		X"AFB20248", -- 0000115C
-		X"AFB10244", -- 00001160
-		X"AFB00240", -- 00001164
-		X"3C11A000", -- 00001168
-		X"AFBF0264", -- 0000116C
-		X"AFBE0260", -- 00001170
-		X"AFB7025C", -- 00001174
-		X"AFB60258", -- 00001178
-		X"AFB50254", -- 0000117C
-		X"AFB40250", -- 00001180
-		X"0FF0056B", -- 00001184
-		X"AFB3024C", -- 00001188
-		X"3C036000", -- 0000118C
-		X"36220004", -- 00001190
-		X"3463B1FF", -- 00001194
-		X"AC430000", -- 00001198
-		X"3C022000", -- 0000119C
-		X"27B20020", -- 000011A0
-		X"34421000", -- 000011A4
-		X"AE220000", -- 000011A8
-		X"02402021", -- 000011AC
-		X"3C05A400", -- 000011B0
-		X"8E300000", -- 000011B4
-		X"0FF002EB", -- 000011B8
-		X"00000000", -- 000011BC
-		X"04410004", -- 000011C0
-		X"00102C02", -- 000011C4
-		X"3C04BFC0", -- 000011C8
-		X"0BF00494", -- 000011CC
-		X"248416A4", -- 000011D0
-		X"02402021", -- 000011D4
-		X"0FF00358", -- 000011D8
-		X"30A5007F", -- 000011DC
-		X"00409021", -- 000011E0
-		X"8E220000", -- 000011E4
-		X"00000000", -- 000011E8
-		X"00021602", -- 000011EC
-		X"30420008", -- 000011F0
-		X"14400044", -- 000011F4
-		X"3C11BFC0", -- 000011F8
-		X"0FF000B0", -- 000011FC
-		X"26241758", -- 00001200
-		X"3C02A400", -- 00001204
-		X"02428021", -- 00001208
-		X"8E030000", -- 0000120C
-		X"3C023149", -- 00001210
-		X"3442464A", -- 00001214
-		X"10620011", -- 00001218
-		X"3C024A46", -- 0000121C
-		X"34424931", -- 00001220
-		X"1062000E", -- 00001224
-		X"00000000", -- 00001228
-		X"0FF000B0", -- 0000122C
-		X"26241758", -- 00001230
-		X"3C04BFC0", -- 00001234
-		X"0FF000B0", -- 00001238
-		X"248416CC", -- 0000123C
-		X"0FF000E8", -- 00001240
-		X"02402021", -- 00001244
-		X"3C04BFC0", -- 00001248
-		X"248416E4", -- 0000124C
-		X"0FF000B0", -- 00001250
-		X"00000000", -- 00001254
-		X"0BF0055F", -- 00001258
-		X"24020001", -- 0000125C
-		X"3C04BFC0", -- 00001260
-		X"0FF000B0", -- 00001264
-		X"248416F0", -- 00001268
-		X"0FF000E8", -- 0000126C
-		X"02402021", -- 00001270
-		X"3C04BFC0", -- 00001274
-		X"0FF000B0", -- 00001278
-		X"24841714", -- 0000127C
-		X"8E02000C", -- 00001280
-		X"8E110004", -- 00001284
-		X"00024082", -- 00001288
-		X"8E070008", -- 0000128C
-		X"00002021", -- 00001290
-		X"0BF004AA", -- 00001294
-		X"00001821", -- 00001298
-		X"8CC20000", -- 0000129C
-		X"00000000", -- 000012A0
-		X"ACA20000", -- 000012A4
-		X"0088102B", -- 000012A8
-		X"00673021", -- 000012AC
-		X"00712821", -- 000012B0
-		X"24840001", -- 000012B4
-		X"1440FFF8", -- 000012B8
-		X"24630004", -- 000012BC
-		X"3C04BFC0", -- 000012C0
-		X"0FF000B0", -- 000012C4
-		X"2484171C", -- 000012C8
-		X"3C04BFC0", -- 000012CC
-		X"0FF000B0", -- 000012D0
-		X"24841724", -- 000012D4
-		X"8E040004", -- 000012D8
-		X"0FF000E8", -- 000012DC
-		X"00000000", -- 000012E0
-		X"3C04BFC0", -- 000012E4
-		X"0FF000B0", -- 000012E8
-		X"24841758", -- 000012EC
-		X"3C1A1000", -- 000012F0
-		X"409A6000", -- 000012F4
-		X"02200008", -- 000012F8
-		X"42000010", -- 000012FC
-		X"0BF0055F", -- 00001300
-		X"00001021", -- 00001304
-		X"0FF000B0", -- 00001308
-		X"26241758", -- 0000130C
-		X"3C04BFC0", -- 00001310
-		X"0FF000B0", -- 00001314
-		X"24841730", -- 00001318
-		X"3C024000", -- 0000131C
-		X"3C034010", -- 00001320
-		X"AC400000", -- 00001324
-		X"24420004", -- 00001328
-		X"1443FFFD", -- 0000132C
-		X"00009821", -- 00001330
-		X"3C02BFC0", -- 00001334
-		X"245516C8", -- 00001338
-		X"3C02BFC0", -- 0000133C
-		X"2456171C", -- 00001340
-		X"3C02BFC0", -- 00001344
-		X"245E17D0", -- 00001348
-		X"3C02BFC0", -- 0000134C
-		X"245717F0", -- 00001350
-		X"3C04BFC0", -- 00001354
-		X"0FF000B0", -- 00001358
-		X"24841750", -- 0000135C
-		X"3C14BFC0", -- 00001360
-		X"27B00040", -- 00001364
-		X"0FF00430", -- 00001368
-		X"02002021", -- 0000136C
-		X"00403021", -- 00001370
-		X"02002821", -- 00001374
-		X"27A40010", -- 00001378
-		X"0FF00384", -- 0000137C
-		X"00408821", -- 00001380
-		X"00401821", -- 00001384
-		X"24020002", -- 00001388
-		X"10620005", -- 0000138C
-		X"24020004", -- 00001390
-		X"1462FFEF", -- 00001394
-		X"00000000", -- 00001398
-		X"0BF004FE", -- 0000139C
-		X"3C04BFC0", -- 000013A0
-		X"8FA50010", -- 000013A4
-		X"8FA60014", -- 000013A8
-		X"0BF004F3", -- 000013AC
-		X"00001821", -- 000013B0
-		X"8FA2001C", -- 000013B4
-		X"00000000", -- 000013B8
-		X"00431021", -- 000013BC
-		X"90420000", -- 000013C0
-		X"24630001", -- 000013C4
-		X"A0820000", -- 000013C8
-		X"8FA20014", -- 000013CC
-		X"00000000", -- 000013D0
-		X"0062102B", -- 000013D4
-		X"1440FFF6", -- 000013D8
-		X"00652021", -- 000013DC
-		X"00C51821", -- 000013E0
-		X"0263102B", -- 000013E4
-		X"10400060", -- 000013E8
-		X"02208021", -- 000013EC
-		X"0BF0055B", -- 000013F0
-		X"00609821", -- 000013F4
-		X"0FF000B0", -- 000013F8
-		X"24841754", -- 000013FC
-		X"8FA60010", -- 00001400
-		X"26470100", -- 00001404
-		X"02661823", -- 00001408
-		X"27B10020", -- 0000140C
-		X"3C024A46", -- 00001410
-		X"00E32821", -- 00001414
-		X"02202021", -- 00001418
-		X"34424931", -- 0000141C
-		X"AFA60144", -- 00001420
-		X"AFA3014C", -- 00001424
-		X"AFA70148", -- 00001428
-		X"0FF00364", -- 0000142C
-		X"AFA20140", -- 00001430
-		X"3C04BFC0", -- 00001434
-		X"2484175C", -- 00001438
-		X"0FF000B0", -- 0000143C
-		X"AFA20150", -- 00001440
-		X"8FA4014C", -- 00001444
-		X"0FF000E8", -- 00001448
-		X"00000000", -- 0000144C
-		X"0FF000B0", -- 00001450
-		X"02A02021", -- 00001454
-		X"3C04BFC0", -- 00001458
-		X"0FF000B0", -- 0000145C
-		X"24841778", -- 00001460
-		X"0FF000E8", -- 00001464
-		X"02402021", -- 00001468
-		X"0FF000B0", -- 0000146C
-		X"02A02021", -- 00001470
-		X"3C04BFC0", -- 00001474
-		X"0FF000B0", -- 00001478
-		X"24841794", -- 0000147C
-		X"8FA40150", -- 00001480
-		X"0FF000E8", -- 00001484
-		X"00000000", -- 00001488
-		X"0FF000B0", -- 0000148C
-		X"02A02021", -- 00001490
-		X"3C04BFC0", -- 00001494
-		X"0FF000B0", -- 00001498
-		X"248417B0", -- 0000149C
-		X"8FA6014C", -- 000014A0
-		X"02202021", -- 000014A4
-		X"24C60100", -- 000014A8
-		X"0FF00304", -- 000014AC
-		X"02402821", -- 000014B0
-		X"0440001F", -- 000014B4
-		X"00408021", -- 000014B8
-		X"0FF000B0", -- 000014BC
-		X"02C02021", -- 000014C0
-		X"0FF000B0", -- 000014C4
-		X"03C02021", -- 000014C8
-		X"02202021", -- 000014CC
-		X"02402821", -- 000014D0
-		X"27A60140", -- 000014D4
-		X"0FF00334", -- 000014D8
-		X"24070100", -- 000014DC
-		X"04400014", -- 000014E0
-		X"00408021", -- 000014E4
-		X"8FA50148", -- 000014E8
-		X"8FA60144", -- 000014EC
-		X"8FA7014C", -- 000014F0
-		X"0FF00334", -- 000014F4
-		X"02202021", -- 000014F8
-		X"0440000D", -- 000014FC
-		X"00408021", -- 00001500
-		X"0FF000B0", -- 00001504
-		X"02C02021", -- 00001508
-		X"3C04BFC0", -- 0000150C
-		X"0FF000B0", -- 00001510
-		X"248417E0", -- 00001514
-		X"8FA50148", -- 00001518
-		X"8FA60144", -- 0000151C
-		X"8FA7014C", -- 00001520
-		X"0FF0033C", -- 00001524
-		X"02202021", -- 00001528
-		X"0441000A", -- 0000152C
-		X"00408021", -- 00001530
-		X"0FF000B0", -- 00001534
-		X"268417C0", -- 00001538
-		X"0FF000E8", -- 0000153C
-		X"02002021", -- 00001540
-		X"3C04BFC0", -- 00001544
-		X"0FF000B0", -- 00001548
-		X"248417CC", -- 0000154C
-		X"0BF0055B", -- 00001550
-		X"00000000", -- 00001554
-		X"0FF000B0", -- 00001558
-		X"02E02021", -- 0000155C
-		X"3C02BFC0", -- 00001560
-		X"00400008", -- 00001564
-		X"00000000", -- 00001568
-		X"0601FF7E", -- 0000156C
-		X"27B00040", -- 00001570
-		X"0BF004D6", -- 00001574
-		X"3C04BFC0", -- 00001578
-		X"8FBF0264", -- 0000157C
-		X"8FBE0260", -- 00001580
-		X"8FB7025C", -- 00001584
-		X"8FB60258", -- 00001588
-		X"8FB50254", -- 0000158C
-		X"8FB40250", -- 00001590
-		X"8FB3024C", -- 00001594
-		X"8FB20248", -- 00001598
-		X"8FB10244", -- 0000159C
-		X"8FB00240", -- 000015A0
-		X"03E00008", -- 000015A4
-		X"27BD0268", -- 000015A8
-		X"2CC20010", -- 000015AC
-		X"00804821", -- 000015B0
-		X"1440002D", -- 000015B4
-		X"00804021", -- 000015B8
-		X"30870003", -- 000015BC
-		X"10E0000E", -- 000015C0
-		X"24820004", -- 000015C4
-		X"00052600", -- 000015C8
-		X"00471023", -- 000015CC
-		X"00042603", -- 000015D0
-		X"01201821", -- 000015D4
-		X"A0640000", -- 000015D8
-		X"24630001", -- 000015DC
-		X"1462FFFD", -- 000015E0
-		X"00000000", -- 000015E4
-		X"00071027", -- 000015E8
-		X"24C3FFFB", -- 000015EC
-		X"24440005", -- 000015F0
-		X"00623023", -- 000015F4
-		X"01244021", -- 000015F8
-		X"30A500FF", -- 000015FC
-		X"01003821", -- 00001600
-		X"10A00005", -- 00001604
-		X"00A01821", -- 00001608
-		X"00051200", -- 0000160C
-		X"00451025", -- 00001610
-		X"00021C00", -- 00001614
-		X"00621825", -- 00001618
-		X"000610C2", -- 0000161C
-		X"1040001C", -- 00001620
-		X"30C60007", -- 00001624
-		X"01002021", -- 00001628
-		X"00403821", -- 0000162C
-		X"24E7FFFF", -- 00001630
-		X"AC830000", -- 00001634
-		X"AC830004", -- 00001638
-		X"14E0FFFC", -- 0000163C
-		X"24840008", -- 00001640
-		X"000210C0", -- 00001644
-		X"01023821", -- 00001648
-		X"00E02021", -- 0000164C
-		X"2CC20004", -- 00001650
-		X"14400005", -- 00001654
-		X"00804021", -- 00001658
-		X"ACE30000", -- 0000165C
-		X"24E40004", -- 00001660
-		X"24C6FFFC", -- 00001664
-		X"00804021", -- 00001668
-		X"10C00007", -- 0000166C
-		X"00000000", -- 00001670
-		X"00051600", -- 00001674
-		X"00021603", -- 00001678
-		X"24C6FFFF", -- 0000167C
-		X"A1020000", -- 00001680
-		X"14C0FFFD", -- 00001684
-		X"25080001", -- 00001688
-		X"03E00008", -- 0000168C
-		X"01201021", -- 00001690
-		X"0BF00594", -- 00001694
-		X"01002021", -- 00001698
-		X"3A200000", -- 0000169C
-		X"20202000", -- 000016A0
-		X"43616E6E", -- 000016A4
-		X"6F742066", -- 000016A8
-		X"696E6420", -- 000016AC
-		X"666C6173", -- 000016B0
-		X"68206465", -- 000016B4
-		X"76696365", -- 000016B8
-		X"2E204578", -- 000016BC
-		X"6974206E", -- 000016C0
-		X"6F77210A", -- 000016C4
-		X"0A000000", -- 000016C8
-		X"496E7661", -- 000016CC
-		X"6C696420", -- 000016D0
-		X"696D6167", -- 000016D4
-		X"6520666F", -- 000016D8
-		X"756E6420", -- 000016DC
-		X"61742000", -- 000016E0
-		X"2E204162", -- 000016E4
-		X"6F72742E", -- 000016E8
-		X"0A000000", -- 000016EC
-		X"426F6F74", -- 000016F0
-		X"696E6720", -- 000016F4
-		X"6170706C", -- 000016F8
-		X"69636174", -- 000016FC
-		X"696F6E20", -- 00001700
-		X"66726F6D", -- 00001704
-		X"20666C61", -- 00001708
-		X"73682028", -- 0000170C
-		X"00000000", -- 00001710
-		X"292E2E2E", -- 00001714
-		X"00000000", -- 00001718
-		X"646F6E65", -- 0000171C
-		X"0A000000", -- 00001720
-		X"45786563", -- 00001724
-		X"75746520", -- 00001728
-		X"61742000", -- 0000172C
-		X"52656164", -- 00001730
-		X"696E6720", -- 00001734
-		X"4845582D", -- 00001738
-		X"5265636F", -- 0000173C
-		X"72642066", -- 00001740
-		X"726F6D20", -- 00001744
-		X"55415254", -- 00001748
-		X"2E2E0000", -- 0000174C
-		X"2E000000", -- 00001750
-		X"646F6E65", -- 00001754
-		X"0A0A0000", -- 00001758
-		X"53697A65", -- 0000175C
-		X"206F6620", -- 00001760
-		X"6170706C", -- 00001764
-		X"69636174", -- 00001768
-		X"696F6E20", -- 0000176C
-		X"2020203A", -- 00001770
-		X"20000000", -- 00001774
-		X"50726F67", -- 00001778
-		X"72616D6D", -- 0000177C
-		X"696E6720", -- 00001780
-		X"666C6173", -- 00001784
-		X"68206174", -- 00001788
-		X"2020203A", -- 0000178C
-		X"20000000", -- 00001790
-		X"4E657874", -- 00001794
-		X"20667265", -- 00001798
-		X"6520666C", -- 0000179C
-		X"61736820", -- 000017A0
-		X"6F666673", -- 000017A4
-		X"6574203A", -- 000017A8
-		X"20000000", -- 000017AC
-		X"466C6173", -- 000017B0
-		X"68206572", -- 000017B4
-		X"6173652E", -- 000017B8
-		X"2E2E0000", -- 000017BC
-		X"6661696C", -- 000017C0
-		X"65642028", -- 000017C4
-		X"00000000", -- 000017C8
-		X"290A0000", -- 000017CC
-		X"466C6173", -- 000017D0
-		X"68207772", -- 000017D4
-		X"6974652E", -- 000017D8
-		X"2E2E0000", -- 000017DC
-		X"466C6173", -- 000017E0
-		X"68207665", -- 000017E4
-		X"72696679", -- 000017E8
-		X"2E2E2E00", -- 000017EC
-		X"70617373", -- 000017F0
-		X"65640A00", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
-		end if;
-	end process;
-
-end data;
diff --git a/lib/CPUs/MIPS/src/bootloader.dis b/lib/CPUs/MIPS/src/bootloader.dis
deleted file mode 100644
index 40da0e3..0000000
--- a/lib/CPUs/MIPS/src/bootloader.dis
+++ /dev/null
@@ -1,1467 +0,0 @@
-
-bootloader.elf:     file format elf32-bigmips
-
-
-Disassembly of section .init:
-
-bfc00000 <__entry>:
-bfc00000:	3c1d8000 	lui	sp,0x8000
-bfc00004:	27bdeff0 	addiu	sp,sp,-4112
-bfc00008:	3c1a1040 	lui	k0,0x1040
-bfc0000c:	375a000c 	ori	k0,k0,0xc
-bfc00010:	409a6000 	mtc0	k0,c0_sr
-bfc00014:	241a0000 	li	k0,0
-bfc00018:	409a6800 	mtc0	k0,c0_cause
-bfc0001c:	401a7800 	mfc0	k0,c0_prid
-bfc00020:	00000000 	nop
-bfc00024:	409af800 	mtc0	k0,$31
-bfc00028:	42000020 	c0	0x20
-bfc0002c:	42000022 	c0	0x22
-bfc00030:	3c1abfc0 	lui	k0,0xbfc0
-bfc00034:	275a005c 	addiu	k0,k0,92
-bfc00038:	0340f809 	jalr	k0
-bfc0003c:	00000000 	nop
-bfc00040:	3c1abfc0 	lui	k0,0xbfc0
-bfc00044:	275a114c 	addiu	k0,k0,4428
-bfc00048:	0340f809 	jalr	k0
-bfc0004c:	00000000 	nop
-
-bfc00050 <_terminate>:
-bfc00050:	00000000 	nop
-bfc00054:	0bf00014 	j	bfc00050 <_terminate>
-bfc00058:	00000000 	nop
-
-bfc0005c <_init>:
-bfc0005c:	3c1aa001 275a0008 241b000d af5b0000     <...'Z..$....[..
-bfc0006c:	03e00008                                ....
-
-Disassembly of section .ktext:
-
-bfc00180 <_exc_handler>:
-bfc00180:	401a6800 	mfc0	k0,c0_cause
-bfc00184:	3c1bc000 	lui	k1,0xc000
-bfc00188:	001ad082 	srl	k0,k0,0x2
-bfc0018c:	335a000f 	andi	k0,k0,0xf
-bfc00190:	035bd025 	or	k0,k0,k1
-bfc00194:	3c1ba000 	lui	k1,0xa000
-bfc00198:	277b0000 	addiu	k1,k1,0
-bfc0019c:	af7a0000 	sw	k0,0(k1)
-bfc001a0:	401a6800 	mfc0	k0,c0_cause
-bfc001a4:	00000000 	nop
-bfc001a8:	001ad202 	srl	k0,k0,0x8
-bfc001ac:	335a00ff 	andi	k0,k0,0xff
-bfc001b0:	1740fffb 	bnez	k0,bfc001a0 <_exc_handler+0x20>
-bfc001b4:	00000000 	nop
-bfc001b8:	401a7000 	mfc0	k0,c0_epc
-bfc001bc:	00000000 	nop
-bfc001c0:	03400008 	jr	k0
-bfc001c4:	42000010 	rfe
-
-Disassembly of section .text:
-
-bfc001c8 <CP0_SR_read>:
-bfc001c8:	40026000 	mfc0	v0,c0_sr
-bfc001cc:	03e00008 	jr	ra
-bfc001d0:	00000000 	nop
-
-bfc001d4 <CP0_SR_write>:
-bfc001d4:	40846000 	mtc0	a0,c0_sr
-bfc001d8:	03e00008 	jr	ra
-bfc001dc:	00000000 	nop
-
-bfc001e0 <CP0_CR_read>:
-bfc001e0:	40026800 	mfc0	v0,c0_cause
-bfc001e4:	03e00008 	jr	ra
-bfc001e8:	00000000 	nop
-
-bfc001ec <CP0_CR_write>:
-bfc001ec:	40846800 	mtc0	a0,c0_cause
-bfc001f0:	03e00008 	jr	ra
-bfc001f4:	00000000 	nop
-
-bfc001f8 <CP0_PRID_read>:
-bfc001f8:	40027800 	mfc0	v0,c0_prid
-bfc001fc:	03e00008 	jr	ra
-bfc00200:	00000000 	nop
-
-bfc00204 <readchar>:
-bfc00204:	3c02a001 	lui	v0,0xa001
-bfc00208:	34430004 	ori	v1,v0,0x4
-bfc0020c:	8c620000 	lw	v0,0(v1)
-bfc00210:	00000000 	nop
-bfc00214:	30420010 	andi	v0,v0,0x10
-bfc00218:	1040fffc 	beqz	v0,bfc0020c <readchar+0x8>
-bfc0021c:	3c02a001 	lui	v0,0xa001
-bfc00220:	8c420000 	lw	v0,0(v0)
-bfc00224:	00000000 	nop
-bfc00228:	00021600 	sll	v0,v0,0x18
-bfc0022c:	03e00008 	jr	ra
-bfc00230:	00021603 	sra	v0,v0,0x18
-
-bfc00234 <writechar>:
-bfc00234:	00042600 	sll	a0,a0,0x18
-bfc00238:	3c02a001 	lui	v0,0xa001
-bfc0023c:	00042603 	sra	a0,a0,0x18
-bfc00240:	34430004 	ori	v1,v0,0x4
-bfc00244:	8c620000 	lw	v0,0(v1)
-bfc00248:	00000000 	nop
-bfc0024c:	30420002 	andi	v0,v0,0x2
-bfc00250:	1440fffc 	bnez	v0,bfc00244 <writechar+0x10>
-bfc00254:	3c02a001 	lui	v0,0xa001
-bfc00258:	ac440000 	sw	a0,0(v0)
-bfc0025c:	03e00008 	jr	ra
-bfc00260:	00000000 	nop
-
-bfc00264 <_putchar>:
-bfc00264:	00042600 	sll	a0,a0,0x18
-bfc00268:	00042603 	sra	a0,a0,0x18
-bfc0026c:	2402000a 	li	v0,10
-bfc00270:	1482000a 	bne	a0,v0,bfc0029c <_putchar+0x38>
-bfc00274:	3c02a001 	lui	v0,0xa001
-bfc00278:	34430004 	ori	v1,v0,0x4
-bfc0027c:	8c620000 	lw	v0,0(v1)
-bfc00280:	00000000 	nop
-bfc00284:	30420002 	andi	v0,v0,0x2
-bfc00288:	1440fffc 	bnez	v0,bfc0027c <_putchar+0x18>
-bfc0028c:	3c02a001 	lui	v0,0xa001
-bfc00290:	2403000d 	li	v1,13
-bfc00294:	ac430000 	sw	v1,0(v0)
-bfc00298:	3c02a001 	lui	v0,0xa001
-bfc0029c:	34430004 	ori	v1,v0,0x4
-bfc002a0:	8c620000 	lw	v0,0(v1)
-bfc002a4:	00000000 	nop
-bfc002a8:	30420002 	andi	v0,v0,0x2
-bfc002ac:	1440fffc 	bnez	v0,bfc002a0 <_putchar+0x3c>
-bfc002b0:	3c02a001 	lui	v0,0xa001
-bfc002b4:	ac440000 	sw	a0,0(v0)
-bfc002b8:	03e00008 	jr	ra
-bfc002bc:	00000000 	nop
-
-bfc002c0 <sputs>:
-bfc002c0:	3c02a001 	lui	v0,0xa001
-bfc002c4:	34470004 	ori	a3,v0,0x4
-bfc002c8:	00802821 	move	a1,a0
-bfc002cc:	2409000a 	li	t1,10
-bfc002d0:	3c06a001 	lui	a2,0xa001
-bfc002d4:	0bf000c6 	j	bfc00318 <sputs+0x58>
-bfc002d8:	2408000d 	li	t0,13
-bfc002dc:	14690007 	bne	v1,t1,bfc002fc <sputs+0x3c>
-bfc002e0:	00000000 	nop
-bfc002e4:	8ce20000 	lw	v0,0(a3)
-bfc002e8:	00000000 	nop
-bfc002ec:	30420002 	andi	v0,v0,0x2
-bfc002f0:	1440fffc 	bnez	v0,bfc002e4 <sputs+0x24>
-bfc002f4:	00000000 	nop
-bfc002f8:	acc80000 	sw	t0,0(a2)
-bfc002fc:	8ce20000 	lw	v0,0(a3)
-bfc00300:	00000000 	nop
-bfc00304:	30420002 	andi	v0,v0,0x2
-bfc00308:	1440fffc 	bnez	v0,bfc002fc <sputs+0x3c>
-bfc0030c:	00000000 	nop
-bfc00310:	acc30000 	sw	v1,0(a2)
-bfc00314:	24a50001 	addiu	a1,a1,1
-bfc00318:	80a30000 	lb	v1,0(a1)
-bfc0031c:	00000000 	nop
-bfc00320:	1460ffee 	bnez	v1,bfc002dc <sputs+0x1c>
-bfc00324:	00a41023 	subu	v0,a1,a0
-bfc00328:	03e00008 	jr	ra
-bfc0032c:	00000000 	nop
-
-bfc00330 <print_byte>:
-bfc00330:	00042600 	sll	a0,a0,0x18
-bfc00334:	3c02a001 	lui	v0,0xa001
-bfc00338:	00042603 	sra	a0,a0,0x18
-bfc0033c:	344a0004 	ori	t2,v0,0x4
-bfc00340:	00003821 	move	a3,zero
-bfc00344:	3c09a001 	lui	t1,0xa001
-bfc00348:	24080002 	li	t0,2
-bfc0034c:	308200ff 	andi	v0,a0,0xff
-bfc00350:	00022902 	srl	a1,v0,0x4
-bfc00354:	00041100 	sll	v0,a0,0x4
-bfc00358:	00022600 	sll	a0,v0,0x18
-bfc0035c:	2ca3000a 	sltiu	v1,a1,10
-bfc00360:	00042603 	sra	a0,a0,0x18
-bfc00364:	14600002 	bnez	v1,bfc00370 <print_byte+0x40>
-bfc00368:	24a60030 	addiu	a2,a1,48
-bfc0036c:	24a60037 	addiu	a2,a1,55
-bfc00370:	8d420000 	lw	v0,0(t2)
-bfc00374:	00000000 	nop
-bfc00378:	30420002 	andi	v0,v0,0x2
-bfc0037c:	1440fffc 	bnez	v0,bfc00370 <print_byte+0x40>
-bfc00380:	00061600 	sll	v0,a2,0x18
-bfc00384:	00021603 	sra	v0,v0,0x18
-bfc00388:	24e70001 	addiu	a3,a3,1
-bfc0038c:	ad220000 	sw	v0,0(t1)
-bfc00390:	14e8ffef 	bne	a3,t0,bfc00350 <print_byte+0x20>
-bfc00394:	308200ff 	andi	v0,a0,0xff
-bfc00398:	03e00008 	jr	ra
-bfc0039c:	00000000 	nop
-
-bfc003a0 <print_word>:
-bfc003a0:	27bdffe0 	addiu	sp,sp,-32
-bfc003a4:	afb20018 	sw	s2,24(sp)
-bfc003a8:	afb10014 	sw	s1,20(sp)
-bfc003ac:	afb00010 	sw	s0,16(sp)
-bfc003b0:	afbf001c 	sw	ra,28(sp)
-bfc003b4:	00808821 	move	s1,a0
-bfc003b8:	00008021 	move	s0,zero
-bfc003bc:	24120004 	li	s2,4
-bfc003c0:	00112603 	sra	a0,s1,0x18
-bfc003c4:	0ff000cc 	jal	bfc00330 <print_byte>
-bfc003c8:	26100001 	addiu	s0,s0,1
-bfc003cc:	1612fffc 	bne	s0,s2,bfc003c0 <print_word+0x20>
-bfc003d0:	00118a00 	sll	s1,s1,0x8
-bfc003d4:	8fbf001c 	lw	ra,28(sp)
-bfc003d8:	8fb20018 	lw	s2,24(sp)
-bfc003dc:	8fb10014 	lw	s1,20(sp)
-bfc003e0:	8fb00010 	lw	s0,16(sp)
-bfc003e4:	03e00008 	jr	ra
-bfc003e8:	27bd0020 	addiu	sp,sp,32
-
-bfc003ec <memdump>:
-bfc003ec:	27bdffc8 	addiu	sp,sp,-56
-bfc003f0:	afb60028 	sw	s6,40(sp)
-bfc003f4:	afbf0034 	sw	ra,52(sp)
-bfc003f8:	afbe0030 	sw	s8,48(sp)
-bfc003fc:	afb7002c 	sw	s7,44(sp)
-bfc00400:	afb50024 	sw	s5,36(sp)
-bfc00404:	afb40020 	sw	s4,32(sp)
-bfc00408:	afb3001c 	sw	s3,28(sp)
-bfc0040c:	afb20018 	sw	s2,24(sp)
-bfc00410:	afb10014 	sw	s1,20(sp)
-bfc00414:	afb00010 	sw	s0,16(sp)
-bfc00418:	00801021 	move	v0,a0
-bfc0041c:	10a00002 	beqz	a1,bfc00428 <memdump+0x3c>
-bfc00420:	00c0b021 	move	s6,a2
-bfc00424:	00002021 	move	a0,zero
-bfc00428:	00409821 	move	s3,v0
-bfc0042c:	3c02a001 	lui	v0,0xa001
-bfc00430:	00e09021 	move	s2,a3
-bfc00434:	0080a821 	move	s5,a0
-bfc00438:	345e0004 	ori	s8,v0,0x4
-bfc0043c:	00e0a021 	move	s4,a3
-bfc00440:	3c17a001 	lui	s7,0xa001
-bfc00444:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc00448:	02a02021 	move	a0,s5
-bfc0044c:	3c04bfc0 	lui	a0,0xbfc0
-bfc00450:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00454:	2484169c 	addiu	a0,a0,5788
-bfc00458:	02608821 	move	s1,s3
-bfc0045c:	0bf00128 	j	bfc004a0 <memdump+0xb4>
-bfc00460:	00008021 	move	s0,zero
-bfc00464:	12400009 	beqz	s2,bfc0048c <memdump+0xa0>
-bfc00468:	00000000 	nop
-bfc0046c:	82240000 	lb	a0,0(s1)
-bfc00470:	0ff000cc 	jal	bfc00330 <print_byte>
-bfc00474:	2652ffff 	addiu	s2,s2,-1
-bfc00478:	3c04bfc0 	lui	a0,0xbfc0
-bfc0047c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00480:	24841774 	addiu	a0,a0,6004
-bfc00484:	0bf00128 	j	bfc004a0 <memdump+0xb4>
-bfc00488:	26310001 	addiu	s1,s1,1
-bfc0048c:	3c04bfc0 	lui	a0,0xbfc0
-bfc00490:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00494:	248416a0 	addiu	a0,a0,5792
-bfc00498:	0bf0012c 	j	bfc004b0 <memdump+0xc4>
-bfc0049c:	3c04bfc0 	lui	a0,0xbfc0
-bfc004a0:	0216102a 	slt	v0,s0,s6
-bfc004a4:	1440ffef 	bnez	v0,bfc00464 <memdump+0x78>
-bfc004a8:	26100001 	addiu	s0,s0,1
-bfc004ac:	3c04bfc0 	lui	a0,0xbfc0
-bfc004b0:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc004b4:	248416a0 	addiu	a0,a0,5792
-bfc004b8:	02602821 	move	a1,s3
-bfc004bc:	0bf00155 	j	bfc00554 <memdump+0x168>
-bfc004c0:	00002021 	move	a0,zero
-bfc004c4:	1280001e 	beqz	s4,bfc00540 <memdump+0x154>
-bfc004c8:	00000000 	nop
-bfc004cc:	90a30000 	lbu	v1,0(a1)
-bfc004d0:	00000000 	nop
-bfc004d4:	2462ffe0 	addiu	v0,v1,-32
-bfc004d8:	304200ff 	andi	v0,v0,0xff
-bfc004dc:	2c420060 	sltiu	v0,v0,96
-bfc004e0:	14400003 	bnez	v0,bfc004f0 <memdump+0x104>
-bfc004e4:	00031e00 	sll	v1,v1,0x18
-bfc004e8:	2403002e 	li	v1,46
-bfc004ec:	00031e00 	sll	v1,v1,0x18
-bfc004f0:	00031e03 	sra	v1,v1,0x18
-bfc004f4:	2402000a 	li	v0,10
-bfc004f8:	14620007 	bne	v1,v0,bfc00518 <memdump+0x12c>
-bfc004fc:	00000000 	nop
-bfc00500:	8fc20000 	lw	v0,0(s8)
-bfc00504:	00000000 	nop
-bfc00508:	30420002 	andi	v0,v0,0x2
-bfc0050c:	1440fffc 	bnez	v0,bfc00500 <memdump+0x114>
-bfc00510:	2402000d 	li	v0,13
-bfc00514:	aee20000 	sw	v0,0(s7)
-bfc00518:	8fc20000 	lw	v0,0(s8)
-bfc0051c:	00000000 	nop
-bfc00520:	30420002 	andi	v0,v0,0x2
-bfc00524:	1440fffc 	bnez	v0,bfc00518 <memdump+0x12c>
-bfc00528:	00000000 	nop
-bfc0052c:	aee30000 	sw	v1,0(s7)
-bfc00530:	2694ffff 	addiu	s4,s4,-1
-bfc00534:	24840001 	addiu	a0,a0,1
-bfc00538:	0bf00155 	j	bfc00554 <memdump+0x168>
-bfc0053c:	24a50001 	addiu	a1,a1,1
-bfc00540:	3c04bfc0 	lui	a0,0xbfc0
-bfc00544:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00548:	24841774 	addiu	a0,a0,6004
-bfc0054c:	0bf00159 	j	bfc00564 <memdump+0x178>
-bfc00550:	3c04bfc0 	lui	a0,0xbfc0
-bfc00554:	0096102a 	slt	v0,a0,s6
-bfc00558:	1440ffda 	bnez	v0,bfc004c4 <memdump+0xd8>
-bfc0055c:	00000000 	nop
-bfc00560:	3c04bfc0 	lui	a0,0xbfc0
-bfc00564:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00568:	248416c8 	addiu	a0,a0,5832
-bfc0056c:	02b6a821 	addu	s5,s5,s6
-bfc00570:	1640ffb4 	bnez	s2,bfc00444 <memdump+0x58>
-bfc00574:	02769821 	addu	s3,s3,s6
-bfc00578:	8fbf0034 	lw	ra,52(sp)
-bfc0057c:	8fbe0030 	lw	s8,48(sp)
-bfc00580:	8fb7002c 	lw	s7,44(sp)
-bfc00584:	8fb60028 	lw	s6,40(sp)
-bfc00588:	8fb50024 	lw	s5,36(sp)
-bfc0058c:	8fb40020 	lw	s4,32(sp)
-bfc00590:	8fb3001c 	lw	s3,28(sp)
-bfc00594:	8fb20018 	lw	s2,24(sp)
-bfc00598:	8fb10014 	lw	s1,20(sp)
-bfc0059c:	8fb00010 	lw	s0,16(sp)
-bfc005a0:	03e00008 	jr	ra
-bfc005a4:	27bd0038 	addiu	sp,sp,56
-
-bfc005a8 <PrintBuffer8>:
-bfc005a8:	00c03821 	move	a3,a2
-bfc005ac:	00a03021 	move	a2,a1
-bfc005b0:	0bf000fb 	j	bfc003ec <memdump>
-bfc005b4:	24050001 	li	a1,1
-
-bfc005b8 <cfi_get_status>:
-bfc005b8:	8c840000 	lw	a0,0(a0)
-bfc005bc:	3c020070 	lui	v0,0x70
-bfc005c0:	34420070 	ori	v0,v0,0x70
-bfc005c4:	3c0300ff 	lui	v1,0xff
-bfc005c8:	ac820000 	sw	v0,0(a0)
-bfc005cc:	346300ff 	ori	v1,v1,0xff
-bfc005d0:	8c820000 	lw	v0,0(a0)
-bfc005d4:	ac830000 	sw	v1,0(a0)
-bfc005d8:	03e00008 	jr	ra
-bfc005dc:	00000000 	nop
-
-bfc005e0 <cfi_init>:
-bfc005e0:	27bdfff8 	addiu	sp,sp,-8
-bfc005e4:	ac850000 	sw	a1,0(a0)
-bfc005e8:	24820008 	addiu	v0,a0,8
-bfc005ec:	0bf0017f 	j	bfc005fc <cfi_init+0x1c>
-bfc005f0:	24830020 	addiu	v1,a0,32
-bfc005f4:	a0400000 	sb	zero,0(v0)
-bfc005f8:	24420001 	addiu	v0,v0,1
-bfc005fc:	1443fffd 	bne	v0,v1,bfc005f4 <cfi_init+0x14>
-bfc00600:	00000000 	nop
-bfc00604:	24020001 	li	v0,1
-bfc00608:	ac820004 	sw	v0,4(a0)
-bfc0060c:	03e00008 	jr	ra
-bfc00610:	27bd0008 	addiu	sp,sp,8
-
-bfc00614 <cfi_find>:
-bfc00614:	8c870000 	lw	a3,0(a0)
-bfc00618:	3c020098 	lui	v0,0x98
-bfc0061c:	34420098 	ori	v0,v0,0x98
-bfc00620:	ace20000 	sw	v0,0(a3)
-bfc00624:	3c0200ff 	lui	v0,0xff
-bfc00628:	344200ff 	ori	v0,v0,0xff
-bfc0062c:	ace20000 	sw	v0,0(a3)
-bfc00630:	3c020090 	lui	v0,0x90
-bfc00634:	34420090 	ori	v0,v0,0x90
-bfc00638:	ace20000 	sw	v0,0(a3)
-bfc0063c:	00804021 	move	t0,a0
-bfc00640:	94e4009c 	lhu	a0,156(a3)
-bfc00644:	24030002 	li	v1,2
-bfc00648:	24020020 	li	v0,32
-bfc0064c:	ad030008 	sw	v1,8(t0)
-bfc00650:	ad03001c 	sw	v1,28(t0)
-bfc00654:	ad020018 	sw	v0,24(t0)
-bfc00658:	3084ffff 	andi	a0,a0,0xffff
-bfc0065c:	0bf0019d 	j	bfc00674 <cfi_find+0x60>
-bfc00660:	00001821 	move	v1,zero
-bfc00664:	8d020008 	lw	v0,8(t0)
-bfc00668:	00000000 	nop
-bfc0066c:	00021040 	sll	v0,v0,0x1
-bfc00670:	ad020008 	sw	v0,8(t0)
-bfc00674:	0064102b 	sltu	v0,v1,a0
-bfc00678:	1440fffa 	bnez	v0,bfc00664 <cfi_find+0x50>
-bfc0067c:	24630001 	addiu	v1,v1,1
-bfc00680:	94e200ac 	lhu	v0,172(a3)
-bfc00684:	94e300a8 	lhu	v1,168(a3)
-bfc00688:	3042ffff 	andi	v0,v0,0xffff
-bfc0068c:	8d04001c 	lw	a0,28(t0)
-bfc00690:	3063ffff 	andi	v1,v1,0xffff
-bfc00694:	00021200 	sll	v0,v0,0x8
-bfc00698:	00432825 	or	a1,v0,v1
-bfc0069c:	ad040014 	sw	a0,20(t0)
-bfc006a0:	0bf001ae 	j	bfc006b8 <cfi_find+0xa4>
-bfc006a4:	00001821 	move	v1,zero
-bfc006a8:	8d020014 	lw	v0,20(t0)
-bfc006ac:	00000000 	nop
-bfc006b0:	00021040 	sll	v0,v0,0x1
-bfc006b4:	ad020014 	sw	v0,20(t0)
-bfc006b8:	0065102b 	sltu	v0,v1,a1
-bfc006bc:	1440fffa 	bnez	v0,bfc006a8 <cfi_find+0x94>
-bfc006c0:	24630001 	addiu	v1,v1,1
-bfc006c4:	94e300b8 	lhu	v1,184(a3)
-bfc006c8:	94e600b4 	lhu	a2,180(a3)
-bfc006cc:	94e200c0 	lhu	v0,192(a3)
-bfc006d0:	94e400bc 	lhu	a0,188(a3)
-bfc006d4:	8d05001c 	lw	a1,28(t0)
-bfc006d8:	3042ffff 	andi	v0,v0,0xffff
-bfc006dc:	3084ffff 	andi	a0,a0,0xffff
-bfc006e0:	00021200 	sll	v0,v0,0x8
-bfc006e4:	00441025 	or	v0,v0,a0
-bfc006e8:	00052a00 	sll	a1,a1,0x8
-bfc006ec:	00a20018 	mult	a1,v0
-bfc006f0:	3063ffff 	andi	v1,v1,0xffff
-bfc006f4:	30c6ffff 	andi	a2,a2,0xffff
-bfc006f8:	00031a00 	sll	v1,v1,0x8
-bfc006fc:	00661825 	or	v1,v1,a2
-bfc00700:	24630001 	addiu	v1,v1,1
-bfc00704:	ad030010 	sw	v1,16(t0)
-bfc00708:	3c0300ff 	lui	v1,0xff
-bfc0070c:	346300ff 	ori	v1,v1,0xff
-bfc00710:	00001021 	move	v0,zero
-bfc00714:	00002812 	mflo	a1
-bfc00718:	ad05000c 	sw	a1,12(t0)
-bfc0071c:	ace30000 	sw	v1,0(a3)
-bfc00720:	03e00008 	jr	ra
-bfc00724:	00000000 	nop
-
-bfc00728 <cfi_block_is_locked>:
-bfc00728:	8c820008 	lw	v0,8(a0)
-bfc0072c:	8c860000 	lw	a2,0(a0)
-bfc00730:	00021082 	srl	v0,v0,0x2
-bfc00734:	00a2102b 	sltu	v0,a1,v0
-bfc00738:	14400004 	bnez	v0,bfc0074c <cfi_block_is_locked+0x24>
-bfc0073c:	3c030090 	lui	v1,0x90
-bfc00740:	3c028010 	lui	v0,0x8010
-bfc00744:	03e00008 	jr	ra
-bfc00748:	34420002 	ori	v0,v0,0x2
-bfc0074c:	8c820010 	lw	v0,16(a0)
-bfc00750:	00000000 	nop
-bfc00754:	2442ffff 	addiu	v0,v0,-1
-bfc00758:	00021400 	sll	v0,v0,0x10
-bfc0075c:	00a21024 	and	v0,a1,v0
-bfc00760:	24420002 	addiu	v0,v0,2
-bfc00764:	34630090 	ori	v1,v1,0x90
-bfc00768:	00021080 	sll	v0,v0,0x2
-bfc0076c:	acc30000 	sw	v1,0(a2)
-bfc00770:	00c21021 	addu	v0,a2,v0
-bfc00774:	8c430000 	lw	v1,0(v0)
-bfc00778:	3c020001 	lui	v0,0x1
-bfc0077c:	34420001 	ori	v0,v0,0x1
-bfc00780:	00621824 	and	v1,v1,v0
-bfc00784:	3c0200ff 	lui	v0,0xff
-bfc00788:	344200ff 	ori	v0,v0,0xff
-bfc0078c:	acc20000 	sw	v0,0(a2)
-bfc00790:	03e00008 	jr	ra
-bfc00794:	0003102b 	sltu	v0,zero,v1
-
-bfc00798 <cfi_block_erase>:
-bfc00798:	8c820008 	lw	v0,8(a0)
-bfc0079c:	00a01821 	move	v1,a1
-bfc007a0:	00021082 	srl	v0,v0,0x2
-bfc007a4:	00a2102b 	sltu	v0,a1,v0
-bfc007a8:	8c850000 	lw	a1,0(a0)
-bfc007ac:	14400003 	bnez	v0,bfc007bc <cfi_block_erase+0x24>
-bfc007b0:	3c028010 	lui	v0,0x8010
-bfc007b4:	0bf0020c 	j	bfc00830 <cfi_block_erase+0x98>
-bfc007b8:	34430002 	ori	v1,v0,0x2
-bfc007bc:	8c820010 	lw	v0,16(a0)
-bfc007c0:	00000000 	nop
-bfc007c4:	2442ffff 	addiu	v0,v0,-1
-bfc007c8:	00021400 	sll	v0,v0,0x10
-bfc007cc:	00621024 	and	v0,v1,v0
-bfc007d0:	00021080 	sll	v0,v0,0x2
-bfc007d4:	00a22021 	addu	a0,a1,v0
-bfc007d8:	3c020020 	lui	v0,0x20
-bfc007dc:	34420020 	ori	v0,v0,0x20
-bfc007e0:	ac820000 	sw	v0,0(a0)
-bfc007e4:	3c0200d0 	lui	v0,0xd0
-bfc007e8:	344200d0 	ori	v0,v0,0xd0
-bfc007ec:	ac820000 	sw	v0,0(a0)
-bfc007f0:	3c020080 	lui	v0,0x80
-bfc007f4:	34430080 	ori	v1,v0,0x80
-bfc007f8:	8c860000 	lw	a2,0(a0)
-bfc007fc:	00000000 	nop
-bfc00800:	00c31024 	and	v0,a2,v1
-bfc00804:	1443fffc 	bne	v0,v1,bfc007f8 <cfi_block_erase+0x60>
-bfc00808:	3c02002a 	lui	v0,0x2a
-bfc0080c:	3442002a 	ori	v0,v0,0x2a
-bfc00810:	00c21024 	and	v0,a2,v0
-bfc00814:	10400003 	beqz	v0,bfc00824 <cfi_block_erase+0x8c>
-bfc00818:	00001821 	move	v1,zero
-bfc0081c:	3c029010 	lui	v0,0x9010
-bfc00820:	00c21825 	or	v1,a2,v0
-bfc00824:	3c0200ff 	lui	v0,0xff
-bfc00828:	344200ff 	ori	v0,v0,0xff
-bfc0082c:	ac820000 	sw	v0,0(a0)
-bfc00830:	03e00008 	jr	ra
-bfc00834:	00601021 	move	v0,v1
-
-bfc00838 <cfi_block_lock>:
-bfc00838:	8c820008 	lw	v0,8(a0)
-bfc0083c:	00a01821 	move	v1,a1
-bfc00840:	00021082 	srl	v0,v0,0x2
-bfc00844:	00a2102b 	sltu	v0,a1,v0
-bfc00848:	8c850000 	lw	a1,0(a0)
-bfc0084c:	14400003 	bnez	v0,bfc0085c <cfi_block_lock+0x24>
-bfc00850:	3c028010 	lui	v0,0x8010
-bfc00854:	0bf00234 	j	bfc008d0 <cfi_block_lock+0x98>
-bfc00858:	34430002 	ori	v1,v0,0x2
-bfc0085c:	8c820010 	lw	v0,16(a0)
-bfc00860:	00000000 	nop
-bfc00864:	2442ffff 	addiu	v0,v0,-1
-bfc00868:	00021400 	sll	v0,v0,0x10
-bfc0086c:	00621024 	and	v0,v1,v0
-bfc00870:	00021080 	sll	v0,v0,0x2
-bfc00874:	00a22021 	addu	a0,a1,v0
-bfc00878:	3c020060 	lui	v0,0x60
-bfc0087c:	34420060 	ori	v0,v0,0x60
-bfc00880:	ac820000 	sw	v0,0(a0)
-bfc00884:	3c020001 	lui	v0,0x1
-bfc00888:	34420001 	ori	v0,v0,0x1
-bfc0088c:	ac820000 	sw	v0,0(a0)
-bfc00890:	3c020080 	lui	v0,0x80
-bfc00894:	34430080 	ori	v1,v0,0x80
-bfc00898:	8c860000 	lw	a2,0(a0)
-bfc0089c:	00000000 	nop
-bfc008a0:	00c31024 	and	v0,a2,v1
-bfc008a4:	1443fffc 	bne	v0,v1,bfc00898 <cfi_block_lock+0x60>
-bfc008a8:	3c020038 	lui	v0,0x38
-bfc008ac:	34420038 	ori	v0,v0,0x38
-bfc008b0:	00c21024 	and	v0,a2,v0
-bfc008b4:	10400003 	beqz	v0,bfc008c4 <cfi_block_lock+0x8c>
-bfc008b8:	00001821 	move	v1,zero
-bfc008bc:	3c029010 	lui	v0,0x9010
-bfc008c0:	00c21825 	or	v1,a2,v0
-bfc008c4:	3c0200ff 	lui	v0,0xff
-bfc008c8:	344200ff 	ori	v0,v0,0xff
-bfc008cc:	ac820000 	sw	v0,0(a0)
-bfc008d0:	03e00008 	jr	ra
-bfc008d4:	00601021 	move	v0,v1
-
-bfc008d8 <cfi_block_unlock>:
-bfc008d8:	8c820008 	lw	v0,8(a0)
-bfc008dc:	00a01821 	move	v1,a1
-bfc008e0:	00021082 	srl	v0,v0,0x2
-bfc008e4:	00a2102b 	sltu	v0,a1,v0
-bfc008e8:	8c850000 	lw	a1,0(a0)
-bfc008ec:	14400003 	bnez	v0,bfc008fc <cfi_block_unlock+0x24>
-bfc008f0:	3c028010 	lui	v0,0x8010
-bfc008f4:	0bf0025c 	j	bfc00970 <cfi_block_unlock+0x98>
-bfc008f8:	34430002 	ori	v1,v0,0x2
-bfc008fc:	8c820010 	lw	v0,16(a0)
-bfc00900:	00000000 	nop
-bfc00904:	2442ffff 	addiu	v0,v0,-1
-bfc00908:	00021400 	sll	v0,v0,0x10
-bfc0090c:	00621024 	and	v0,v1,v0
-bfc00910:	00021080 	sll	v0,v0,0x2
-bfc00914:	00a22021 	addu	a0,a1,v0
-bfc00918:	3c020060 	lui	v0,0x60
-bfc0091c:	34420060 	ori	v0,v0,0x60
-bfc00920:	ac820000 	sw	v0,0(a0)
-bfc00924:	3c0200d0 	lui	v0,0xd0
-bfc00928:	344200d0 	ori	v0,v0,0xd0
-bfc0092c:	ac820000 	sw	v0,0(a0)
-bfc00930:	3c020080 	lui	v0,0x80
-bfc00934:	34430080 	ori	v1,v0,0x80
-bfc00938:	8c860000 	lw	a2,0(a0)
-bfc0093c:	00000000 	nop
-bfc00940:	00c31024 	and	v0,a2,v1
-bfc00944:	1443fffc 	bne	v0,v1,bfc00938 <cfi_block_unlock+0x60>
-bfc00948:	3c020038 	lui	v0,0x38
-bfc0094c:	34420038 	ori	v0,v0,0x38
-bfc00950:	00c21024 	and	v0,a2,v0
-bfc00954:	10400003 	beqz	v0,bfc00964 <cfi_block_unlock+0x8c>
-bfc00958:	00001821 	move	v1,zero
-bfc0095c:	3c029010 	lui	v0,0x9010
-bfc00960:	00c21825 	or	v1,a2,v0
-bfc00964:	3c0200ff 	lui	v0,0xff
-bfc00968:	344200ff 	ori	v0,v0,0xff
-bfc0096c:	ac820000 	sw	v0,0(a0)
-bfc00970:	03e00008 	jr	ra
-bfc00974:	00601021 	move	v0,v1
-
-bfc00978 <cfi_program_single>:
-bfc00978:	8c820008 	lw	v0,8(a0)
-bfc0097c:	8c840000 	lw	a0,0(a0)
-bfc00980:	00021082 	srl	v0,v0,0x2
-bfc00984:	00a2102b 	sltu	v0,a1,v0
-bfc00988:	14400003 	bnez	v0,bfc00998 <cfi_program_single+0x20>
-bfc0098c:	3c028010 	lui	v0,0x8010
-bfc00990:	0bf0027c 	j	bfc009f0 <cfi_program_single+0x78>
-bfc00994:	34430002 	ori	v1,v0,0x2
-bfc00998:	00051080 	sll	v0,a1,0x2
-bfc0099c:	00822021 	addu	a0,a0,v0
-bfc009a0:	3c020040 	lui	v0,0x40
-bfc009a4:	34420040 	ori	v0,v0,0x40
-bfc009a8:	ac820000 	sw	v0,0(a0)
-bfc009ac:	3c020080 	lui	v0,0x80
-bfc009b0:	ac860000 	sw	a2,0(a0)
-bfc009b4:	34430080 	ori	v1,v0,0x80
-bfc009b8:	8c860000 	lw	a2,0(a0)
-bfc009bc:	00000000 	nop
-bfc009c0:	00c31024 	and	v0,a2,v1
-bfc009c4:	1443fffc 	bne	v0,v1,bfc009b8 <cfi_program_single+0x40>
-bfc009c8:	3c02001a 	lui	v0,0x1a
-bfc009cc:	3442001a 	ori	v0,v0,0x1a
-bfc009d0:	00c21024 	and	v0,a2,v0
-bfc009d4:	10400003 	beqz	v0,bfc009e4 <cfi_program_single+0x6c>
-bfc009d8:	00001821 	move	v1,zero
-bfc009dc:	3c029010 	lui	v0,0x9010
-bfc009e0:	00c21825 	or	v1,a2,v0
-bfc009e4:	3c0200ff 	lui	v0,0xff
-bfc009e8:	344200ff 	ori	v0,v0,0xff
-bfc009ec:	ac820000 	sw	v0,0(a0)
-bfc009f0:	03e00008 	jr	ra
-bfc009f4:	00601021 	move	v0,v1
-
-bfc009f8 <cfi_program_multi>:
-bfc009f8:	8c820008 	lw	v0,8(a0)
-bfc009fc:	27bdffe8 	addiu	sp,sp,-24
-bfc00a00:	00021082 	srl	v0,v0,0x2
-bfc00a04:	00a2102b 	sltu	v0,a1,v0
-bfc00a08:	afb40014 	sw	s4,20(sp)
-bfc00a0c:	afb30010 	sw	s3,16(sp)
-bfc00a10:	afb2000c 	sw	s2,12(sp)
-bfc00a14:	afb10008 	sw	s1,8(sp)
-bfc00a18:	afb00004 	sw	s0,4(sp)
-bfc00a1c:	0080c021 	move	t8,a0
-bfc00a20:	8c8e0000 	lw	t6,0(a0)
-bfc00a24:	14400004 	bnez	v0,bfc00a38 <cfi_program_multi+0x40>
-bfc00a28:	00c0a021 	move	s4,a2
-bfc00a2c:	3c028010 	lui	v0,0x8010
-bfc00a30:	0bf002e3 	j	bfc00b8c <cfi_program_multi+0x194>
-bfc00a34:	34440002 	ori	a0,v0,0x2
-bfc00a38:	8c820010 	lw	v0,16(a0)
-bfc00a3c:	00006821 	move	t5,zero
-bfc00a40:	2442ffff 	addiu	v0,v0,-1
-bfc00a44:	0002cc00 	sll	t9,v0,0x10
-bfc00a48:	3c0200e8 	lui	v0,0xe8
-bfc00a4c:	345300e8 	ori	s3,v0,0xe8
-bfc00a50:	3c020080 	lui	v0,0x80
-bfc00a54:	344f0080 	ori	t7,v0,0x80
-bfc00a58:	3c02001a 	lui	v0,0x1a
-bfc00a5c:	3446001a 	ori	a2,v0,0x1a
-bfc00a60:	3c0200d0 	lui	v0,0xd0
-bfc00a64:	345200d0 	ori	s2,v0,0xd0
-bfc00a68:	3c0200ff 	lui	v0,0xff
-bfc00a6c:	345100ff 	ori	s1,v0,0xff
-bfc00a70:	0bf002e1 	j	bfc00b84 <cfi_program_multi+0x18c>
-bfc00a74:	3c100001 	lui	s0,0x1
-bfc00a78:	01851023 	subu	v0,t4,a1
-bfc00a7c:	00505021 	addu	t2,v0,s0
-bfc00a80:	00ea102b 	sltu	v0,a3,t2
-bfc00a84:	10400002 	beqz	v0,bfc00a90 <cfi_program_multi+0x98>
-bfc00a88:	000c1080 	sll	v0,t4,0x2
-bfc00a8c:	00e05021 	move	t2,a3
-bfc00a90:	0bf002d7 	j	bfc00b5c <cfi_program_multi+0x164>
-bfc00a94:	01c25821 	addu	t3,t6,v0
-bfc00a98:	ad730000 	sw	s3,0(t3)
-bfc00a9c:	8d630000 	lw	v1,0(t3)
-bfc00aa0:	00000000 	nop
-bfc00aa4:	006f1024 	and	v0,v1,t7
-bfc00aa8:	144ffffc 	bne	v0,t7,bfc00a9c <cfi_program_multi+0xa4>
-bfc00aac:	00661024 	and	v0,v1,a2
-bfc00ab0:	14400026 	bnez	v0,bfc00b4c <cfi_program_multi+0x154>
-bfc00ab4:	3c029010 	lui	v0,0x9010
-bfc00ab8:	8f020014 	lw	v0,20(t8)
-bfc00abc:	00000000 	nop
-bfc00ac0:	00021882 	srl	v1,v0,0x2
-bfc00ac4:	006a102b 	sltu	v0,v1,t2
-bfc00ac8:	10400002 	beqz	v0,bfc00ad4 <cfi_program_multi+0xdc>
-bfc00acc:	01404021 	move	t0,t2
-bfc00ad0:	00604021 	move	t0,v1
-bfc00ad4:	2503ffff 	addiu	v1,t0,-1
-bfc00ad8:	00031400 	sll	v0,v1,0x10
-bfc00adc:	00431025 	or	v0,v0,v1
-bfc00ae0:	00052080 	sll	a0,a1,0x2
-bfc00ae4:	000d1880 	sll	v1,t5,0x2
-bfc00ae8:	02834821 	addu	t1,s4,v1
-bfc00aec:	ad620000 	sw	v0,0(t3)
-bfc00af0:	01c42021 	addu	a0,t6,a0
-bfc00af4:	0bf002c3 	j	bfc00b0c <cfi_program_multi+0x114>
-bfc00af8:	00001821 	move	v1,zero
-bfc00afc:	8d220000 	lw	v0,0(t1)
-bfc00b00:	25290004 	addiu	t1,t1,4
-bfc00b04:	ac820000 	sw	v0,0(a0)
-bfc00b08:	24840004 	addiu	a0,a0,4
-bfc00b0c:	0068102b 	sltu	v0,v1,t0
-bfc00b10:	1440fffa 	bnez	v0,bfc00afc <cfi_program_multi+0x104>
-bfc00b14:	24630001 	addiu	v1,v1,1
-bfc00b18:	01a86821 	addu	t5,t5,t0
-bfc00b1c:	00a82821 	addu	a1,a1,t0
-bfc00b20:	00e83823 	subu	a3,a3,t0
-bfc00b24:	ad720000 	sw	s2,0(t3)
-bfc00b28:	8d630000 	lw	v1,0(t3)
-bfc00b2c:	00000000 	nop
-bfc00b30:	006f1024 	and	v0,v1,t7
-bfc00b34:	144ffffc 	bne	v0,t7,bfc00b28 <cfi_program_multi+0x130>
-bfc00b38:	00661024 	and	v0,v1,a2
-bfc00b3c:	10400005 	beqz	v0,bfc00b54 <cfi_program_multi+0x15c>
-bfc00b40:	01485023 	subu	t2,t2,t0
-bfc00b44:	01485021 	addu	t2,t2,t0
-bfc00b48:	3c029010 	lui	v0,0x9010
-bfc00b4c:	0bf002d9 	j	bfc00b64 <cfi_program_multi+0x16c>
-bfc00b50:	00622025 	or	a0,v1,v0
-bfc00b54:	ad710000 	sw	s1,0(t3)
-bfc00b58:	00002021 	move	a0,zero
-bfc00b5c:	1540ffce 	bnez	t2,bfc00a98 <cfi_program_multi+0xa0>
-bfc00b60:	00000000 	nop
-bfc00b64:	04810007 	bgez	a0,bfc00b84 <cfi_program_multi+0x18c>
-bfc00b68:	000c1880 	sll	v1,t4,0x2
-bfc00b6c:	3c0200ff 	lui	v0,0xff
-bfc00b70:	01c31821 	addu	v1,t6,v1
-bfc00b74:	344200ff 	ori	v0,v0,0xff
-bfc00b78:	ac620000 	sw	v0,0(v1)
-bfc00b7c:	0bf002e4 	j	bfc00b90 <cfi_program_multi+0x198>
-bfc00b80:	00801021 	move	v0,a0
-bfc00b84:	14e0ffbc 	bnez	a3,bfc00a78 <cfi_program_multi+0x80>
-bfc00b88:	00b96024 	and	t4,a1,t9
-bfc00b8c:	00801021 	move	v0,a0
-bfc00b90:	8fb40014 	lw	s4,20(sp)
-bfc00b94:	8fb30010 	lw	s3,16(sp)
-bfc00b98:	8fb2000c 	lw	s2,12(sp)
-bfc00b9c:	8fb10008 	lw	s1,8(sp)
-bfc00ba0:	8fb00004 	lw	s0,4(sp)
-bfc00ba4:	03e00008 	jr	ra
-bfc00ba8:	27bd0018 	addiu	sp,sp,24
-
-bfc00bac <flash_find>:
-bfc00bac:	27bdffe0 	addiu	sp,sp,-32
-bfc00bb0:	afbf001c 	sw	ra,28(sp)
-bfc00bb4:	ac850000 	sw	a1,0(a0)
-bfc00bb8:	24820008 	addiu	v0,a0,8
-bfc00bbc:	0bf002f3 	j	bfc00bcc <flash_find+0x20>
-bfc00bc0:	24830020 	addiu	v1,a0,32
-bfc00bc4:	a0400000 	sb	zero,0(v0)
-bfc00bc8:	24420001 	addiu	v0,v0,1
-bfc00bcc:	1443fffd 	bne	v0,v1,bfc00bc4 <flash_find+0x18>
-bfc00bd0:	00000000 	nop
-bfc00bd4:	3c021234 	lui	v0,0x1234
-bfc00bd8:	34425678 	ori	v0,v0,0x5678
-bfc00bdc:	00021e02 	srl	v1,v0,0x18
-bfc00be0:	afa20010 	sw	v0,16(sp)
-bfc00be4:	24020012 	li	v0,18
-bfc00be8:	14620003 	bne	v1,v0,bfc00bf8 <flash_find+0x4c>
-bfc00bec:	ac800004 	sw	zero,4(a0)
-bfc00bf0:	24020001 	li	v0,1
-bfc00bf4:	ac820004 	sw	v0,4(a0)
-bfc00bf8:	0ff00185 	jal	bfc00614 <cfi_find>
-bfc00bfc:	00000000 	nop
-bfc00c00:	8fbf001c 	lw	ra,28(sp)
-bfc00c04:	00000000 	nop
-bfc00c08:	03e00008 	jr	ra
-bfc00c0c:	27bd0020 	addiu	sp,sp,32
-
-bfc00c10 <flash_erase>:
-bfc00c10:	27bdffd8 	addiu	sp,sp,-40
-bfc00c14:	30c20003 	andi	v0,a2,0x3
-bfc00c18:	afb2001c 	sw	s2,28(sp)
-bfc00c1c:	afbf0024 	sw	ra,36(sp)
-bfc00c20:	afb30020 	sw	s3,32(sp)
-bfc00c24:	afb10018 	sw	s1,24(sp)
-bfc00c28:	afb00014 	sw	s0,20(sp)
-bfc00c2c:	10400004 	beqz	v0,bfc00c40 <flash_erase+0x30>
-bfc00c30:	00809021 	move	s2,a0
-bfc00c34:	00061082 	srl	v0,a2,0x2
-bfc00c38:	24420001 	addiu	v0,v0,1
-bfc00c3c:	00023080 	sll	a2,v0,0x2
-bfc00c40:	00c59821 	addu	s3,a2,a1
-bfc00c44:	0bf00324 	j	bfc00c90 <flash_erase+0x80>
-bfc00c48:	00a08821 	move	s1,a1
-bfc00c4c:	0ff001ca 	jal	bfc00728 <cfi_block_is_locked>
-bfc00c50:	00000000 	nop
-bfc00c54:	02402021 	move	a0,s2
-bfc00c58:	10400005 	beqz	v0,bfc00c70 <flash_erase+0x60>
-bfc00c5c:	02002821 	move	a1,s0
-bfc00c60:	0ff00236 	jal	bfc008d8 <cfi_block_unlock>
-bfc00c64:	00000000 	nop
-bfc00c68:	04400011 	bltz	v0,bfc00cb0 <flash_erase+0xa0>
-bfc00c6c:	00401821 	move	v1,v0
-bfc00c70:	02002821 	move	a1,s0
-bfc00c74:	0ff001e6 	jal	bfc00798 <cfi_block_erase>
-bfc00c78:	02402021 	move	a0,s2
-bfc00c7c:	0440000c 	bltz	v0,bfc00cb0 <flash_erase+0xa0>
-bfc00c80:	00401821 	move	v1,v0
-bfc00c84:	8e42000c 	lw	v0,12(s2)
-bfc00c88:	00000000 	nop
-bfc00c8c:	02228821 	addu	s1,s1,v0
-bfc00c90:	001117c3 	sra	v0,s1,0x1f
-bfc00c94:	00021782 	srl	v0,v0,0x1e
-bfc00c98:	00511021 	addu	v0,v0,s1
-bfc00c9c:	00028083 	sra	s0,v0,0x2
-bfc00ca0:	0233102b 	sltu	v0,s1,s3
-bfc00ca4:	02402021 	move	a0,s2
-bfc00ca8:	1440ffe8 	bnez	v0,bfc00c4c <flash_erase+0x3c>
-bfc00cac:	02002821 	move	a1,s0
-bfc00cb0:	8fbf0024 	lw	ra,36(sp)
-bfc00cb4:	00601021 	move	v0,v1
-bfc00cb8:	8fb30020 	lw	s3,32(sp)
-bfc00cbc:	8fb2001c 	lw	s2,28(sp)
-bfc00cc0:	8fb10018 	lw	s1,24(sp)
-bfc00cc4:	8fb00014 	lw	s0,20(sp)
-bfc00cc8:	03e00008 	jr	ra
-bfc00ccc:	27bd0028 	addiu	sp,sp,40
-
-bfc00cd0 <flash_program>:
-bfc00cd0:	30e20003 	andi	v0,a3,0x3
-bfc00cd4:	10400003 	beqz	v0,bfc00ce4 <flash_program+0x14>
-bfc00cd8:	00071082 	srl	v0,a3,0x2
-bfc00cdc:	24420001 	addiu	v0,v0,1
-bfc00ce0:	00023880 	sll	a3,v0,0x2
-bfc00ce4:	00052882 	srl	a1,a1,0x2
-bfc00ce8:	0bf0027e 	j	bfc009f8 <cfi_program_multi>
-bfc00cec:	00073882 	srl	a3,a3,0x2
-
-bfc00cf0 <flash_verify>:
-bfc00cf0:	8c820000 	lw	v0,0(a0)
-bfc00cf4:	00002021 	move	a0,zero
-bfc00cf8:	0bf00347 	j	bfc00d1c <flash_verify+0x2c>
-bfc00cfc:	00454021 	addu	t0,v0,a1
-bfc00d00:	90630000 	lbu	v1,0(v1)
-bfc00d04:	90a20000 	lbu	v0,0(a1)
-bfc00d08:	00000000 	nop
-bfc00d0c:	10620003 	beq	v1,v0,bfc00d1c <flash_verify+0x2c>
-bfc00d10:	3c028010 	lui	v0,0x8010
-bfc00d14:	03e00008 	jr	ra
-bfc00d18:	34420003 	ori	v0,v0,0x3
-bfc00d1c:	0087102b 	sltu	v0,a0,a3
-bfc00d20:	01041821 	addu	v1,t0,a0
-bfc00d24:	00c42821 	addu	a1,a2,a0
-bfc00d28:	1440fff5 	bnez	v0,bfc00d00 <flash_verify+0x10>
-bfc00d2c:	24840001 	addiu	a0,a0,1
-bfc00d30:	03e00008 	jr	ra
-bfc00d34:	00000000 	nop
-
-bfc00d38 <flash_get_blocknum_by_offset>:
-bfc00d38:	8c82000c 	lw	v0,12(a0)
-bfc00d3c:	00000000 	nop
-bfc00d40:	14400002 	bnez	v0,bfc00d4c <flash_get_blocknum_by_offset+0x14>
-bfc00d44:	00a2001b 	divu	zero,a1,v0
-bfc00d48:	0007000d 	break	0x7
-bfc00d4c:	00001010 	mfhi	v0
-bfc00d50:	0002102b 	sltu	v0,zero,v0
-bfc00d54:	00002812 	mflo	a1
-bfc00d58:	03e00008 	jr	ra
-bfc00d5c:	00a21021 	addu	v0,a1,v0
-
-bfc00d60 <flash_get_offset_by_blocknum>:
-bfc00d60:	8c830010 	lw	v1,16(a0)
-bfc00d64:	00000000 	nop
-bfc00d68:	00a3102b 	sltu	v0,a1,v1
-bfc00d6c:	14400002 	bnez	v0,bfc00d78 <flash_get_offset_by_blocknum+0x18>
-bfc00d70:	00000000 	nop
-bfc00d74:	2465ffff 	addiu	a1,v1,-1
-bfc00d78:	8c82000c 	lw	v0,12(a0)
-bfc00d7c:	00000000 	nop
-bfc00d80:	00a20018 	mult	a1,v0
-bfc00d84:	00001012 	mflo	v0
-bfc00d88:	03e00008 	jr	ra
-bfc00d8c:	00000000 	nop
-
-bfc00d90 <flash_get_offset_blockaligned>:
-bfc00d90:	27bdffe8 	addiu	sp,sp,-24
-bfc00d94:	afbf0014 	sw	ra,20(sp)
-bfc00d98:	afb00010 	sw	s0,16(sp)
-bfc00d9c:	0ff0034e 	jal	bfc00d38 <flash_get_blocknum_by_offset>
-bfc00da0:	00808021 	move	s0,a0
-bfc00da4:	8e03000c 	lw	v1,12(s0)
-bfc00da8:	8fbf0014 	lw	ra,20(sp)
-bfc00dac:	00430018 	mult	v0,v1
-bfc00db0:	8fb00010 	lw	s0,16(sp)
-bfc00db4:	00001012 	mflo	v0
-bfc00db8:	03e00008 	jr	ra
-bfc00dbc:	27bd0018 	addiu	sp,sp,24
-
-bfc00dc0 <h2i>:
-bfc00dc0:	90830000 	lbu	v1,0(a0)
-bfc00dc4:	00000000 	nop
-bfc00dc8:	2c620041 	sltiu	v0,v1,65
-bfc00dcc:	14400002 	bnez	v0,bfc00dd8 <h2i+0x18>
-bfc00dd0:	2462ffd0 	addiu	v0,v1,-48
-bfc00dd4:	2462ffc9 	addiu	v0,v1,-55
-bfc00dd8:	90840001 	lbu	a0,1(a0)
-bfc00ddc:	304200ff 	andi	v0,v0,0xff
-bfc00de0:	304300ff 	andi	v1,v0,0xff
-bfc00de4:	2c820041 	sltiu	v0,a0,65
-bfc00de8:	14400003 	bnez	v0,bfc00df8 <h2i+0x38>
-bfc00dec:	00000000 	nop
-bfc00df0:	0bf0037f 	j	bfc00dfc <h2i+0x3c>
-bfc00df4:	2482ffc9 	addiu	v0,a0,-55
-bfc00df8:	2482ffd0 	addiu	v0,a0,-48
-bfc00dfc:	304400ff 	andi	a0,v0,0xff
-bfc00e00:	00031100 	sll	v0,v1,0x4
-bfc00e04:	00821025 	or	v0,a0,v0
-bfc00e08:	03e00008 	jr	ra
-bfc00e0c:	304200ff 	andi	v0,v0,0xff
-
-bfc00e10 <decode_srec>:
-bfc00e10:	10c00094 	beqz	a2,bfc01064 <decode_srec+0x254>
-bfc00e14:	00805021 	move	t2,a0
-bfc00e18:	24020003 	li	v0,3
-bfc00e1c:	ac820008 	sw	v0,8(a0)
-bfc00e20:	90a40001 	lbu	a0,1(a1)
-bfc00e24:	00000000 	nop
-bfc00e28:	2482ffcf 	addiu	v0,a0,-49
-bfc00e2c:	304200ff 	andi	v0,v0,0xff
-bfc00e30:	2c420003 	sltiu	v0,v0,3
-bfc00e34:	10400005 	beqz	v0,bfc00e4c <decode_srec+0x3c>
-bfc00e38:	2482ffc9 	addiu	v0,a0,-55
-bfc00e3c:	24020002 	li	v0,2
-bfc00e40:	ad420008 	sw	v0,8(t2)
-bfc00e44:	0bf003a1 	j	bfc00e84 <decode_srec+0x74>
-bfc00e48:	2489ffd1 	addiu	t1,a0,-47
-bfc00e4c:	304200ff 	andi	v0,v0,0xff
-bfc00e50:	2c420003 	sltiu	v0,v0,3
-bfc00e54:	10400006 	beqz	v0,bfc00e70 <decode_srec+0x60>
-bfc00e58:	24020030 	li	v0,48
-bfc00e5c:	2402003b 	li	v0,59
-bfc00e60:	00444823 	subu	t1,v0,a0
-bfc00e64:	24020004 	li	v0,4
-bfc00e68:	0bf003a1 	j	bfc00e84 <decode_srec+0x74>
-bfc00e6c:	ad420008 	sw	v0,8(t2)
-bfc00e70:	14820004 	bne	a0,v0,bfc00e84 <decode_srec+0x74>
-bfc00e74:	00004821 	move	t1,zero
-bfc00e78:	24020001 	li	v0,1
-bfc00e7c:	ad420008 	sw	v0,8(t2)
-bfc00e80:	24090002 	li	t1,2
-bfc00e84:	90a30002 	lbu	v1,2(a1)
-bfc00e88:	00000000 	nop
-bfc00e8c:	2c620041 	sltiu	v0,v1,65
-bfc00e90:	10400003 	beqz	v0,bfc00ea0 <decode_srec+0x90>
-bfc00e94:	24a40002 	addiu	a0,a1,2
-bfc00e98:	0bf003a9 	j	bfc00ea4 <decode_srec+0x94>
-bfc00e9c:	2462ffd0 	addiu	v0,v1,-48
-bfc00ea0:	2462ffc9 	addiu	v0,v1,-55
-bfc00ea4:	90830001 	lbu	v1,1(a0)
-bfc00ea8:	304200ff 	andi	v0,v0,0xff
-bfc00eac:	304400ff 	andi	a0,v0,0xff
-bfc00eb0:	2c620041 	sltiu	v0,v1,65
-bfc00eb4:	10400002 	beqz	v0,bfc00ec0 <decode_srec+0xb0>
-bfc00eb8:	2462ffc9 	addiu	v0,v1,-55
-bfc00ebc:	2462ffd0 	addiu	v0,v1,-48
-bfc00ec0:	304300ff 	andi	v1,v0,0xff
-bfc00ec4:	00041100 	sll	v0,a0,0x4
-bfc00ec8:	00621025 	or	v0,v1,v0
-bfc00ecc:	304200ff 	andi	v0,v0,0xff
-bfc00ed0:	ad420004 	sw	v0,4(t2)
-bfc00ed4:	ad400000 	sw	zero,0(t2)
-bfc00ed8:	00405821 	move	t3,v0
-bfc00edc:	00a03021 	move	a2,a1
-bfc00ee0:	0bf003d5 	j	bfc00f54 <decode_srec+0x144>
-bfc00ee4:	00003821 	move	a3,zero
-bfc00ee8:	90c20004 	lbu	v0,4(a2)
-bfc00eec:	00000000 	nop
-bfc00ef0:	2443ffc9 	addiu	v1,v0,-55
-bfc00ef4:	2444ffd0 	addiu	a0,v0,-48
-bfc00ef8:	2c420041 	sltiu	v0,v0,65
-bfc00efc:	10400002 	beqz	v0,bfc00f08 <decode_srec+0xf8>
-bfc00f00:	306300ff 	andi	v1,v1,0xff
-bfc00f04:	308300ff 	andi	v1,a0,0xff
-bfc00f08:	90c20005 	lbu	v0,5(a2)
-bfc00f0c:	306800ff 	andi	t0,v1,0xff
-bfc00f10:	2444ffc9 	addiu	a0,v0,-55
-bfc00f14:	2443ffd0 	addiu	v1,v0,-48
-bfc00f18:	2c420041 	sltiu	v0,v0,65
-bfc00f1c:	10400002 	beqz	v0,bfc00f28 <decode_srec+0x118>
-bfc00f20:	308400ff 	andi	a0,a0,0xff
-bfc00f24:	306400ff 	andi	a0,v1,0xff
-bfc00f28:	8d430000 	lw	v1,0(t2)
-bfc00f2c:	00081100 	sll	v0,t0,0x4
-bfc00f30:	00821025 	or	v0,a0,v0
-bfc00f34:	304200ff 	andi	v0,v0,0xff
-bfc00f38:	00031a00 	sll	v1,v1,0x8
-bfc00f3c:	004b2021 	addu	a0,v0,t3
-bfc00f40:	00431025 	or	v0,v0,v1
-bfc00f44:	ad420000 	sw	v0,0(t2)
-bfc00f48:	308b00ff 	andi	t3,a0,0xff
-bfc00f4c:	24e70001 	addiu	a3,a3,1
-bfc00f50:	24c60002 	addiu	a2,a2,2
-bfc00f54:	00e9102a 	slt	v0,a3,t1
-bfc00f58:	1440ffe3 	bnez	v0,bfc00ee8 <decode_srec+0xd8>
-bfc00f5c:	25220002 	addiu	v0,t1,2
-bfc00f60:	8d440004 	lw	a0,4(t2)
-bfc00f64:	00021040 	sll	v0,v0,0x1
-bfc00f68:	00091827 	nor	v1,zero,t1
-bfc00f6c:	00832021 	addu	a0,a0,v1
-bfc00f70:	00a21021 	addu	v0,a1,v0
-bfc00f74:	ad440004 	sw	a0,4(t2)
-bfc00f78:	ad42000c 	sw	v0,12(t2)
-bfc00f7c:	0bf003f9 	j	bfc00fe4 <decode_srec+0x1d4>
-bfc00f80:	00003021 	move	a2,zero
-bfc00f84:	90e20000 	lbu	v0,0(a3)
-bfc00f88:	00000000 	nop
-bfc00f8c:	2444ffc9 	addiu	a0,v0,-55
-bfc00f90:	2445ffd0 	addiu	a1,v0,-48
-bfc00f94:	2c420041 	sltiu	v0,v0,65
-bfc00f98:	10400002 	beqz	v0,bfc00fa4 <decode_srec+0x194>
-bfc00f9c:	308400ff 	andi	a0,a0,0xff
-bfc00fa0:	30a400ff 	andi	a0,a1,0xff
-bfc00fa4:	90e20001 	lbu	v0,1(a3)
-bfc00fa8:	308700ff 	andi	a3,a0,0xff
-bfc00fac:	2445ffc9 	addiu	a1,v0,-55
-bfc00fb0:	2444ffd0 	addiu	a0,v0,-48
-bfc00fb4:	2c420041 	sltiu	v0,v0,65
-bfc00fb8:	14400002 	bnez	v0,bfc00fc4 <decode_srec+0x1b4>
-bfc00fbc:	308400ff 	andi	a0,a0,0xff
-bfc00fc0:	30a400ff 	andi	a0,a1,0xff
-bfc00fc4:	00071100 	sll	v0,a3,0x4
-bfc00fc8:	00821025 	or	v0,a0,v0
-bfc00fcc:	304200ff 	andi	v0,v0,0xff
-bfc00fd0:	00661821 	addu	v1,v1,a2
-bfc00fd4:	004b2021 	addu	a0,v0,t3
-bfc00fd8:	a0620000 	sb	v0,0(v1)
-bfc00fdc:	308b00ff 	andi	t3,a0,0xff
-bfc00fe0:	24c60001 	addiu	a2,a2,1
-bfc00fe4:	8d420004 	lw	v0,4(t2)
-bfc00fe8:	8d43000c 	lw	v1,12(t2)
-bfc00fec:	00062040 	sll	a0,a2,0x1
-bfc00ff0:	00c2102a 	slt	v0,a2,v0
-bfc00ff4:	1440ffe3 	bnez	v0,bfc00f84 <decode_srec+0x174>
-bfc00ff8:	00643821 	addu	a3,v1,a0
-bfc00ffc:	90e40000 	lbu	a0,0(a3)
-bfc01000:	00000000 	nop
-bfc01004:	2c820041 	sltiu	v0,a0,65
-bfc01008:	10400003 	beqz	v0,bfc01018 <decode_srec+0x208>
-bfc0100c:	00e01821 	move	v1,a3
-bfc01010:	0bf00407 	j	bfc0101c <decode_srec+0x20c>
-bfc01014:	2482ffd0 	addiu	v0,a0,-48
-bfc01018:	2482ffc9 	addiu	v0,a0,-55
-bfc0101c:	90630001 	lbu	v1,1(v1)
-bfc01020:	304200ff 	andi	v0,v0,0xff
-bfc01024:	304400ff 	andi	a0,v0,0xff
-bfc01028:	2c620041 	sltiu	v0,v1,65
-bfc0102c:	10400002 	beqz	v0,bfc01038 <decode_srec+0x228>
-bfc01030:	2462ffc9 	addiu	v0,v1,-55
-bfc01034:	2462ffd0 	addiu	v0,v1,-48
-bfc01038:	304200ff 	andi	v0,v0,0xff
-bfc0103c:	00041900 	sll	v1,a0,0x4
-bfc01040:	00431825 	or	v1,v0,v1
-bfc01044:	000b1027 	nor	v0,zero,t3
-bfc01048:	304200ff 	andi	v0,v0,0xff
-bfc0104c:	306300ff 	andi	v1,v1,0xff
-bfc01050:	14430004 	bne	v0,v1,bfc01064 <decode_srec+0x254>
-bfc01054:	00000000 	nop
-bfc01058:	8d420008 	lw	v0,8(t2)
-bfc0105c:	03e00008 	jr	ra
-bfc01060:	00000000 	nop
-bfc01064:	03e00008 	jr	ra
-bfc01068:	00001021 	move	v0,zero
-
-bfc0106c <Jump_to>:
-bfc0106c:	00800008 	jr	a0
-bfc01070:	00000000 	nop
-bfc01074:	03e00008 	jr	ra
-bfc01078:	00000000 	nop
-
-bfc0107c <Exec_at>:
-bfc0107c:	3c1a1000 	lui	k0,0x1000
-bfc01080:	409a6000 	mtc0	k0,c0_sr
-bfc01084:	00800008 	jr	a0
-bfc01088:	42000010 	rfe
-bfc0108c:	03e00008 	jr	ra
-bfc01090:	00000000 	nop
-
-bfc01094 <Exec_RE_at>:
-bfc01094:	401a6000 	mfc0	k0,c0_sr
-bfc01098:	3c1bffbf 	lui	k1,0xffbf
-bfc0109c:	377bffff 	ori	k1,k1,0xffff
-bfc010a0:	035bd024 	and	k0,k0,k1
-bfc010a4:	3c1b0200 	lui	k1,0x200
-bfc010a8:	035bd025 	or	k0,k0,k1
-bfc010ac:	409a6000 	mtc0	k0,c0_sr
-bfc010b0:	00800008 	jr	a0
-bfc010b4:	42000010 	rfe
-bfc010b8:	03e00008 	jr	ra
-bfc010bc:	00000000 	nop
-
-bfc010c0 <srec_getline>:
-bfc010c0:	27bdffd8 	addiu	sp,sp,-40
-bfc010c4:	afb30020 	sw	s3,32(sp)
-bfc010c8:	afb10018 	sw	s1,24(sp)
-bfc010cc:	afb00014 	sw	s0,20(sp)
-bfc010d0:	afbf0024 	sw	ra,36(sp)
-bfc010d4:	afb2001c 	sw	s2,28(sp)
-bfc010d8:	00809821 	move	s3,a0
-bfc010dc:	24110073 	li	s1,115
-bfc010e0:	24100053 	li	s0,83
-bfc010e4:	0ff00081 	jal	bfc00204 <readchar>
-bfc010e8:	00000000 	nop
-bfc010ec:	14510005 	bne	v0,s1,bfc01104 <srec_getline+0x44>
-bfc010f0:	00000000 	nop
-bfc010f4:	00008021 	move	s0,zero
-bfc010f8:	2412000a 	li	s2,10
-bfc010fc:	0bf00449 	j	bfc01124 <srec_getline+0x64>
-bfc01100:	2411000d 	li	s1,13
-bfc01104:	1450fff7 	bne	v0,s0,bfc010e4 <srec_getline+0x24>
-bfc01108:	00000000 	nop
-bfc0110c:	0bf0043e 	j	bfc010f8 <srec_getline+0x38>
-bfc01110:	00008021 	move	s0,zero
-bfc01114:	0ff00081 	jal	bfc00204 <readchar>
-bfc01118:	a0620000 	sb	v0,0(v1)
-bfc0111c:	10510003 	beq	v0,s1,bfc0112c <srec_getline+0x6c>
-bfc01120:	26100001 	addiu	s0,s0,1
-bfc01124:	1452fffb 	bne	v0,s2,bfc01114 <srec_getline+0x54>
-bfc01128:	02701821 	addu	v1,s3,s0
-bfc0112c:	8fbf0024 	lw	ra,36(sp)
-bfc01130:	02001021 	move	v0,s0
-bfc01134:	8fb30020 	lw	s3,32(sp)
-bfc01138:	8fb2001c 	lw	s2,28(sp)
-bfc0113c:	8fb10018 	lw	s1,24(sp)
-bfc01140:	8fb00014 	lw	s0,20(sp)
-bfc01144:	03e00008 	jr	ra
-bfc01148:	27bd0028 	addiu	sp,sp,40
-
-bfc0114c <main>:
-bfc0114c:	27bdfd98 	addiu	sp,sp,-616
-bfc01150:	27a40140 	addiu	a0,sp,320
-bfc01154:	00002821 	move	a1,zero
-bfc01158:	24060100 	li	a2,256
-bfc0115c:	afb20248 	sw	s2,584(sp)
-bfc01160:	afb10244 	sw	s1,580(sp)
-bfc01164:	afb00240 	sw	s0,576(sp)
-bfc01168:	3c11a000 	lui	s1,0xa000
-bfc0116c:	afbf0264 	sw	ra,612(sp)
-bfc01170:	afbe0260 	sw	s8,608(sp)
-bfc01174:	afb7025c 	sw	s7,604(sp)
-bfc01178:	afb60258 	sw	s6,600(sp)
-bfc0117c:	afb50254 	sw	s5,596(sp)
-bfc01180:	afb40250 	sw	s4,592(sp)
-bfc01184:	0ff0056b 	jal	bfc015ac <memset>
-bfc01188:	afb3024c 	sw	s3,588(sp)
-bfc0118c:	3c036000 	lui	v1,0x6000
-bfc01190:	36220004 	ori	v0,s1,0x4
-bfc01194:	3463b1ff 	ori	v1,v1,0xb1ff
-bfc01198:	ac430000 	sw	v1,0(v0)
-bfc0119c:	3c022000 	lui	v0,0x2000
-bfc011a0:	27b20020 	addiu	s2,sp,32
-bfc011a4:	34421000 	ori	v0,v0,0x1000
-bfc011a8:	ae220000 	sw	v0,0(s1)
-bfc011ac:	02402021 	move	a0,s2
-bfc011b0:	3c05a400 	lui	a1,0xa400
-bfc011b4:	8e300000 	lw	s0,0(s1)
-bfc011b8:	0ff002eb 	jal	bfc00bac <flash_find>
-bfc011bc:	00000000 	nop
-bfc011c0:	04410004 	bgez	v0,bfc011d4 <main+0x88>
-bfc011c4:	00102c02 	srl	a1,s0,0x10
-bfc011c8:	3c04bfc0 	lui	a0,0xbfc0
-bfc011cc:	0bf00494 	j	bfc01250 <main+0x104>
-bfc011d0:	248416a4 	addiu	a0,a0,5796
-bfc011d4:	02402021 	move	a0,s2
-bfc011d8:	0ff00358 	jal	bfc00d60 <flash_get_offset_by_blocknum>
-bfc011dc:	30a5007f 	andi	a1,a1,0x7f
-bfc011e0:	00409021 	move	s2,v0
-bfc011e4:	8e220000 	lw	v0,0(s1)
-bfc011e8:	00000000 	nop
-bfc011ec:	00021602 	srl	v0,v0,0x18
-bfc011f0:	30420008 	andi	v0,v0,0x8
-bfc011f4:	14400044 	bnez	v0,bfc01308 <main+0x1bc>
-bfc011f8:	3c11bfc0 	lui	s1,0xbfc0
-bfc011fc:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01200:	26241758 	addiu	a0,s1,5976
-bfc01204:	3c02a400 	lui	v0,0xa400
-bfc01208:	02428021 	addu	s0,s2,v0
-bfc0120c:	8e030000 	lw	v1,0(s0)
-bfc01210:	3c023149 	lui	v0,0x3149
-bfc01214:	3442464a 	ori	v0,v0,0x464a
-bfc01218:	10620011 	beq	v1,v0,bfc01260 <main+0x114>
-bfc0121c:	3c024a46 	lui	v0,0x4a46
-bfc01220:	34424931 	ori	v0,v0,0x4931
-bfc01224:	1062000e 	beq	v1,v0,bfc01260 <main+0x114>
-bfc01228:	00000000 	nop
-bfc0122c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01230:	26241758 	addiu	a0,s1,5976
-bfc01234:	3c04bfc0 	lui	a0,0xbfc0
-bfc01238:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0123c:	248416cc 	addiu	a0,a0,5836
-bfc01240:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01244:	02402021 	move	a0,s2
-bfc01248:	3c04bfc0 	lui	a0,0xbfc0
-bfc0124c:	248416e4 	addiu	a0,a0,5860
-bfc01250:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01254:	00000000 	nop
-bfc01258:	0bf0055f 	j	bfc0157c <main+0x430>
-bfc0125c:	24020001 	li	v0,1
-bfc01260:	3c04bfc0 	lui	a0,0xbfc0
-bfc01264:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01268:	248416f0 	addiu	a0,a0,5872
-bfc0126c:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01270:	02402021 	move	a0,s2
-bfc01274:	3c04bfc0 	lui	a0,0xbfc0
-bfc01278:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0127c:	24841714 	addiu	a0,a0,5908
-bfc01280:	8e02000c 	lw	v0,12(s0)
-bfc01284:	8e110004 	lw	s1,4(s0)
-bfc01288:	00024082 	srl	t0,v0,0x2
-bfc0128c:	8e070008 	lw	a3,8(s0)
-bfc01290:	00002021 	move	a0,zero
-bfc01294:	0bf004aa 	j	bfc012a8 <main+0x15c>
-bfc01298:	00001821 	move	v1,zero
-bfc0129c:	8cc20000 	lw	v0,0(a2)
-bfc012a0:	00000000 	nop
-bfc012a4:	aca20000 	sw	v0,0(a1)
-bfc012a8:	0088102b 	sltu	v0,a0,t0
-bfc012ac:	00673021 	addu	a2,v1,a3
-bfc012b0:	00712821 	addu	a1,v1,s1
-bfc012b4:	24840001 	addiu	a0,a0,1
-bfc012b8:	1440fff8 	bnez	v0,bfc0129c <main+0x150>
-bfc012bc:	24630004 	addiu	v1,v1,4
-bfc012c0:	3c04bfc0 	lui	a0,0xbfc0
-bfc012c4:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012c8:	2484171c 	addiu	a0,a0,5916
-bfc012cc:	3c04bfc0 	lui	a0,0xbfc0
-bfc012d0:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012d4:	24841724 	addiu	a0,a0,5924
-bfc012d8:	8e040004 	lw	a0,4(s0)
-bfc012dc:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc012e0:	00000000 	nop
-bfc012e4:	3c04bfc0 	lui	a0,0xbfc0
-bfc012e8:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012ec:	24841758 	addiu	a0,a0,5976
-bfc012f0:	3c1a1000 	lui	k0,0x1000
-bfc012f4:	409a6000 	mtc0	k0,c0_sr
-bfc012f8:	02200008 	jr	s1
-bfc012fc:	42000010 	rfe
-bfc01300:	0bf0055f 	j	bfc0157c <main+0x430>
-bfc01304:	00001021 	move	v0,zero
-bfc01308:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0130c:	26241758 	addiu	a0,s1,5976
-bfc01310:	3c04bfc0 	lui	a0,0xbfc0
-bfc01314:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01318:	24841730 	addiu	a0,a0,5936
-bfc0131c:	3c024000 	lui	v0,0x4000
-bfc01320:	3c034010 	lui	v1,0x4010
-bfc01324:	ac400000 	sw	zero,0(v0)
-bfc01328:	24420004 	addiu	v0,v0,4
-bfc0132c:	1443fffd 	bne	v0,v1,bfc01324 <main+0x1d8>
-bfc01330:	00009821 	move	s3,zero
-bfc01334:	3c02bfc0 	lui	v0,0xbfc0
-bfc01338:	245516c8 	addiu	s5,v0,5832
-bfc0133c:	3c02bfc0 	lui	v0,0xbfc0
-bfc01340:	2456171c 	addiu	s6,v0,5916
-bfc01344:	3c02bfc0 	lui	v0,0xbfc0
-bfc01348:	245e17d0 	addiu	s8,v0,6096
-bfc0134c:	3c02bfc0 	lui	v0,0xbfc0
-bfc01350:	245717f0 	addiu	s7,v0,6128
-bfc01354:	3c04bfc0 	lui	a0,0xbfc0
-bfc01358:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0135c:	24841750 	addiu	a0,a0,5968
-bfc01360:	3c14bfc0 	lui	s4,0xbfc0
-bfc01364:	27b00040 	addiu	s0,sp,64
-bfc01368:	0ff00430 	jal	bfc010c0 <srec_getline>
-bfc0136c:	02002021 	move	a0,s0
-bfc01370:	00403021 	move	a2,v0
-bfc01374:	02002821 	move	a1,s0
-bfc01378:	27a40010 	addiu	a0,sp,16
-bfc0137c:	0ff00384 	jal	bfc00e10 <decode_srec>
-bfc01380:	00408821 	move	s1,v0
-bfc01384:	00401821 	move	v1,v0
-bfc01388:	24020002 	li	v0,2
-bfc0138c:	10620005 	beq	v1,v0,bfc013a4 <main+0x258>
-bfc01390:	24020004 	li	v0,4
-bfc01394:	1462ffef 	bne	v1,v0,bfc01354 <main+0x208>
-bfc01398:	00000000 	nop
-bfc0139c:	0bf004fe 	j	bfc013f8 <main+0x2ac>
-bfc013a0:	3c04bfc0 	lui	a0,0xbfc0
-bfc013a4:	8fa50010 	lw	a1,16(sp)
-bfc013a8:	8fa60014 	lw	a2,20(sp)
-bfc013ac:	0bf004f3 	j	bfc013cc <main+0x280>
-bfc013b0:	00001821 	move	v1,zero
-bfc013b4:	8fa2001c 	lw	v0,28(sp)
-bfc013b8:	00000000 	nop
-bfc013bc:	00431021 	addu	v0,v0,v1
-bfc013c0:	90420000 	lbu	v0,0(v0)
-bfc013c4:	24630001 	addiu	v1,v1,1
-bfc013c8:	a0820000 	sb	v0,0(a0)
-bfc013cc:	8fa20014 	lw	v0,20(sp)
-bfc013d0:	00000000 	nop
-bfc013d4:	0062102b 	sltu	v0,v1,v0
-bfc013d8:	1440fff6 	bnez	v0,bfc013b4 <main+0x268>
-bfc013dc:	00652021 	addu	a0,v1,a1
-bfc013e0:	00c51821 	addu	v1,a2,a1
-bfc013e4:	0263102b 	sltu	v0,s3,v1
-bfc013e8:	10400060 	beqz	v0,bfc0156c <main+0x420>
-bfc013ec:	02208021 	move	s0,s1
-bfc013f0:	0bf0055b 	j	bfc0156c <main+0x420>
-bfc013f4:	00609821 	move	s3,v1
-bfc013f8:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc013fc:	24841754 	addiu	a0,a0,5972
-bfc01400:	8fa60010 	lw	a2,16(sp)
-bfc01404:	26470100 	addiu	a3,s2,256
-bfc01408:	02661823 	subu	v1,s3,a2
-bfc0140c:	27b10020 	addiu	s1,sp,32
-bfc01410:	3c024a46 	lui	v0,0x4a46
-bfc01414:	00e32821 	addu	a1,a3,v1
-bfc01418:	02202021 	move	a0,s1
-bfc0141c:	34424931 	ori	v0,v0,0x4931
-bfc01420:	afa60144 	sw	a2,324(sp)
-bfc01424:	afa3014c 	sw	v1,332(sp)
-bfc01428:	afa70148 	sw	a3,328(sp)
-bfc0142c:	0ff00364 	jal	bfc00d90 <flash_get_offset_blockaligned>
-bfc01430:	afa20140 	sw	v0,320(sp)
-bfc01434:	3c04bfc0 	lui	a0,0xbfc0
-bfc01438:	2484175c 	addiu	a0,a0,5980
-bfc0143c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01440:	afa20150 	sw	v0,336(sp)
-bfc01444:	8fa4014c 	lw	a0,332(sp)
-bfc01448:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc0144c:	00000000 	nop
-bfc01450:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01454:	02a02021 	move	a0,s5
-bfc01458:	3c04bfc0 	lui	a0,0xbfc0
-bfc0145c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01460:	24841778 	addiu	a0,a0,6008
-bfc01464:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01468:	02402021 	move	a0,s2
-bfc0146c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01470:	02a02021 	move	a0,s5
-bfc01474:	3c04bfc0 	lui	a0,0xbfc0
-bfc01478:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0147c:	24841794 	addiu	a0,a0,6036
-bfc01480:	8fa40150 	lw	a0,336(sp)
-bfc01484:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01488:	00000000 	nop
-bfc0148c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01490:	02a02021 	move	a0,s5
-bfc01494:	3c04bfc0 	lui	a0,0xbfc0
-bfc01498:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0149c:	248417b0 	addiu	a0,a0,6064
-bfc014a0:	8fa6014c 	lw	a2,332(sp)
-bfc014a4:	02202021 	move	a0,s1
-bfc014a8:	24c60100 	addiu	a2,a2,256
-bfc014ac:	0ff00304 	jal	bfc00c10 <flash_erase>
-bfc014b0:	02402821 	move	a1,s2
-bfc014b4:	0440001f 	bltz	v0,bfc01534 <main+0x3e8>
-bfc014b8:	00408021 	move	s0,v0
-bfc014bc:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc014c0:	02c02021 	move	a0,s6
-bfc014c4:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc014c8:	03c02021 	move	a0,s8
-bfc014cc:	02202021 	move	a0,s1
-bfc014d0:	02402821 	move	a1,s2
-bfc014d4:	27a60140 	addiu	a2,sp,320
-bfc014d8:	0ff00334 	jal	bfc00cd0 <flash_program>
-bfc014dc:	24070100 	li	a3,256
-bfc014e0:	04400014 	bltz	v0,bfc01534 <main+0x3e8>
-bfc014e4:	00408021 	move	s0,v0
-bfc014e8:	8fa50148 	lw	a1,328(sp)
-bfc014ec:	8fa60144 	lw	a2,324(sp)
-bfc014f0:	8fa7014c 	lw	a3,332(sp)
-bfc014f4:	0ff00334 	jal	bfc00cd0 <flash_program>
-bfc014f8:	02202021 	move	a0,s1
-bfc014fc:	0440000d 	bltz	v0,bfc01534 <main+0x3e8>
-bfc01500:	00408021 	move	s0,v0
-bfc01504:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01508:	02c02021 	move	a0,s6
-bfc0150c:	3c04bfc0 	lui	a0,0xbfc0
-bfc01510:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01514:	248417e0 	addiu	a0,a0,6112
-bfc01518:	8fa50148 	lw	a1,328(sp)
-bfc0151c:	8fa60144 	lw	a2,324(sp)
-bfc01520:	8fa7014c 	lw	a3,332(sp)
-bfc01524:	0ff0033c 	jal	bfc00cf0 <flash_verify>
-bfc01528:	02202021 	move	a0,s1
-bfc0152c:	0441000a 	bgez	v0,bfc01558 <main+0x40c>
-bfc01530:	00408021 	move	s0,v0
-bfc01534:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01538:	268417c0 	addiu	a0,s4,6080
-bfc0153c:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01540:	02002021 	move	a0,s0
-bfc01544:	3c04bfc0 	lui	a0,0xbfc0
-bfc01548:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0154c:	248417cc 	addiu	a0,a0,6092
-bfc01550:	0bf0055b 	j	bfc0156c <main+0x420>
-bfc01554:	00000000 	nop
-bfc01558:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0155c:	02e02021 	move	a0,s7
-bfc01560:	3c02bfc0 	lui	v0,0xbfc0
-bfc01564:	00400008 	jr	v0
-bfc01568:	00000000 	nop
-bfc0156c:	0601ff7e 	bgez	s0,bfc01368 <main+0x21c>
-bfc01570:	27b00040 	addiu	s0,sp,64
-bfc01574:	0bf004d6 	j	bfc01358 <main+0x20c>
-bfc01578:	3c04bfc0 	lui	a0,0xbfc0
-bfc0157c:	8fbf0264 	lw	ra,612(sp)
-bfc01580:	8fbe0260 	lw	s8,608(sp)
-bfc01584:	8fb7025c 	lw	s7,604(sp)
-bfc01588:	8fb60258 	lw	s6,600(sp)
-bfc0158c:	8fb50254 	lw	s5,596(sp)
-bfc01590:	8fb40250 	lw	s4,592(sp)
-bfc01594:	8fb3024c 	lw	s3,588(sp)
-bfc01598:	8fb20248 	lw	s2,584(sp)
-bfc0159c:	8fb10244 	lw	s1,580(sp)
-bfc015a0:	8fb00240 	lw	s0,576(sp)
-bfc015a4:	03e00008 	jr	ra
-bfc015a8:	27bd0268 	addiu	sp,sp,616
-
-bfc015ac <memset>:
-bfc015ac:	2cc20010 	sltiu	v0,a2,16
-bfc015b0:	00804821 	move	t1,a0
-bfc015b4:	1440002d 	bnez	v0,bfc0166c <memset+0xc0>
-bfc015b8:	00804021 	move	t0,a0
-bfc015bc:	30870003 	andi	a3,a0,0x3
-bfc015c0:	10e0000e 	beqz	a3,bfc015fc <memset+0x50>
-bfc015c4:	24820004 	addiu	v0,a0,4
-bfc015c8:	00052600 	sll	a0,a1,0x18
-bfc015cc:	00471023 	subu	v0,v0,a3
-bfc015d0:	00042603 	sra	a0,a0,0x18
-bfc015d4:	01201821 	move	v1,t1
-bfc015d8:	a0640000 	sb	a0,0(v1)
-bfc015dc:	24630001 	addiu	v1,v1,1
-bfc015e0:	1462fffd 	bne	v1,v0,bfc015d8 <memset+0x2c>
-bfc015e4:	00000000 	nop
-bfc015e8:	00071027 	nor	v0,zero,a3
-bfc015ec:	24c3fffb 	addiu	v1,a2,-5
-bfc015f0:	24440005 	addiu	a0,v0,5
-bfc015f4:	00623023 	subu	a2,v1,v0
-bfc015f8:	01244021 	addu	t0,t1,a0
-bfc015fc:	30a500ff 	andi	a1,a1,0xff
-bfc01600:	01003821 	move	a3,t0
-bfc01604:	10a00005 	beqz	a1,bfc0161c <memset+0x70>
-bfc01608:	00a01821 	move	v1,a1
-bfc0160c:	00051200 	sll	v0,a1,0x8
-bfc01610:	00451025 	or	v0,v0,a1
-bfc01614:	00021c00 	sll	v1,v0,0x10
-bfc01618:	00621825 	or	v1,v1,v0
-bfc0161c:	000610c2 	srl	v0,a2,0x3
-bfc01620:	1040001c 	beqz	v0,bfc01694 <memset+0xe8>
-bfc01624:	30c60007 	andi	a2,a2,0x7
-bfc01628:	01002021 	move	a0,t0
-bfc0162c:	00403821 	move	a3,v0
-bfc01630:	24e7ffff 	addiu	a3,a3,-1
-bfc01634:	ac830000 	sw	v1,0(a0)
-bfc01638:	ac830004 	sw	v1,4(a0)
-bfc0163c:	14e0fffc 	bnez	a3,bfc01630 <memset+0x84>
-bfc01640:	24840008 	addiu	a0,a0,8
-bfc01644:	000210c0 	sll	v0,v0,0x3
-bfc01648:	01023821 	addu	a3,t0,v0
-bfc0164c:	00e02021 	move	a0,a3
-bfc01650:	2cc20004 	sltiu	v0,a2,4
-bfc01654:	14400005 	bnez	v0,bfc0166c <memset+0xc0>
-bfc01658:	00804021 	move	t0,a0
-bfc0165c:	ace30000 	sw	v1,0(a3)
-bfc01660:	24e40004 	addiu	a0,a3,4
-bfc01664:	24c6fffc 	addiu	a2,a2,-4
-bfc01668:	00804021 	move	t0,a0
-bfc0166c:	10c00007 	beqz	a2,bfc0168c <memset+0xe0>
-bfc01670:	00000000 	nop
-bfc01674:	00051600 	sll	v0,a1,0x18
-bfc01678:	00021603 	sra	v0,v0,0x18
-bfc0167c:	24c6ffff 	addiu	a2,a2,-1
-bfc01680:	a1020000 	sb	v0,0(t0)
-bfc01684:	14c0fffd 	bnez	a2,bfc0167c <memset+0xd0>
-bfc01688:	25080001 	addiu	t0,t0,1
-bfc0168c:	03e00008 	jr	ra
-bfc01690:	01201021 	move	v0,t1
-bfc01694:	0bf00594 	j	bfc01650 <memset+0xa4>
-bfc01698:	01002021 	move	a0,t0
diff --git a/lib/CPUs/MIPS/src/core/.directory_history b/lib/CPUs/MIPS/src/core/.directory_history
deleted file mode 100644
index 1dd52df..0000000
--- a/lib/CPUs/MIPS/src/core/.directory_history
+++ /dev/null
@@ -1,12 +0,0 @@
-VHDL/lib/CPUs/MIPS/src/core/dcache.vhd
-VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd
-VHDL/lib/CPUs/MIPS/src/core/icache.vhd
-VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd
-VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd
-
-VHDL/lib/CPUs/MIPS/src/core/mips_bui.vhd
-VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd
-VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd
-
-VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd
-
diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd
deleted file mode 100644
index 85d1639..0000000
--- a/lib/CPUs/MIPS/src/core/dcache.vhd
+++ /dev/null
@@ -1,513 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: JIPS top file 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library work;
-use work.mips_types.all;
-
-ENTITY dcache IS
-	Generic
-	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
-	);
-	Port
-	(
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		STB_O		: out STD_LOGIC;
-		CYC_O		: out STD_LOGIC;
-		ctrl		: in  cache_ctrl_t;
-		cpu_en		: in  STD_LOGIC;
-		cpu_we		: in  STD_LOGIC;
-		cpu_be		: in  unsigned(3 downto 0);
-		cpu_addr	: in  word_t;
-		cpu_din		: in  word_t;
-		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC
-	);
-END dcache;
-
-ARCHITECTURE behavior OF dcache IS
-
-
-COMPONENT dpram_2w2r2c_ra is
-	GENERIC 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	PORT
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-END COMPONENT;
-
-	constant addr_width			: natural := 32;
-	constant word_index_width	: natural := lg2(line_size);
-	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
-	constant tag_width			: natural := addr_width - word_index_width - cache_index_width - 2;
-	constant tag_parity_width	: natural := 3;
-	constant tag_ram_data_width	: natural := 1 + tag_parity_width + tag_width;
-	constant tag_ram_addr_width	: natural := cache_index_width;
-	
-	subtype	tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
-
-	type dcache_entry_t is record
-		valid	: std_logic;
-		tv_p	: unsigned(tag_parity_width-1 downto 0);
-		tag		: unsigned(tag_width-1 downto 0);
-	end record;
-	
-	function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is
-	variable result : dcache_entry_t;
-	begin
-		result.valid	:= x(0);
-		result.tv_p		:= x(3 downto 1);
-		result.tag		:= x(tag_width+3 downto 4);
-		
-		return result;
-	end to_dcache_entry;
-
-	function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is
-	variable result : tag_ram_data_t;
-	begin
-		result(0)										:= x.valid;
-		result(3 downto 1)								:= x.tv_p;
-		result(tag_width+3 downto 4)					:= x.tag;
-		
-		return result;
-	end to_tag_ram_data;
-
-	type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache);
-	signal s, sn : cache_state_t;
-	
-	signal	cache_req			: std_logic;
-	signal	cache_ack			: std_logic;
-	signal	cache_busy			: std_logic;
-	signal	cache_hit			: std_logic;
-	signal	tag_match			: std_logic;
-	signal	cache_hit_inv		: std_logic;
-	signal	tag_match_inv		: std_logic;
-	
-	signal  request_addr		: unsigned(addr_width-1 downto 0);
-	signal  fill_addr			: unsigned(addr_width-1 downto 0);
-
-	signal  cache_index_inv		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_inv				: unsigned(tag_width-1 downto 0);
-	signal  tag_reg_inv			: unsigned(tag_width-1 downto 0);
-	
-	signal	cache_entry_in		: dcache_entry_t;
-	signal	cache_entry_out		: dcache_entry_t;
-	signal	cache_entry_out_inv	: dcache_entry_t;
-	signal  cpu_data_ram_addr	: unsigned(lg2(cache_size)-1 downto 0);
-	signal  cpu_data_ram_dout	: word_t;
-	signal  cpu_data_reg		: word_t;
-	signal  cpu_be_reg			: unsigned(3 downto 0);
-	signal  cpu_we_reg			: std_logic;
-	signal  ctrl_data_ram_addr	: unsigned(lg2(cache_size)-1 downto 0);
-	signal	ctrl_data_ram_we	: unsigned(3 downto 0);
-	signal	cpu_data_ram_we		: unsigned(3 downto 0);
-	signal	cpu_we2				: std_logic;
-
-	signal  tag_ram_addr_rd		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_ram_dout		: tag_ram_data_t;
-	signal  tag_ram_dout_inv	: tag_ram_data_t;
-	signal  tag_ram_addr_wr		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_ram_din			: tag_ram_data_t;
-	signal	tag_ram_we			: std_logic;
-	
-	signal	fill_count			: natural range 0 to 2**word_index_width-1;
-	signal	fill_count_en		: std_logic;
-	signal	fill_count_rdy		: std_logic;
-	signal	flush_count			: natural range 0 to 2**cache_index_width-1;
-	signal	flush_count_rst		: std_logic;
-	signal	flush_count_en		: std_logic;
-	signal	flush_count_rdy		: std_logic;
-	signal	request_count		: natural range 0 to 2**word_index_width-1;
-	signal	request_count_en	: std_logic;
-	signal	request_count_rdy	: std_logic;
-	signal	was_miss			: std_logic;
-	signal	invalidate_all		: std_logic;
-	signal	invalidate_ack		: std_logic;
-	signal  invalidate_en		: std_logic;
-	signal  invalidate_req		: std_logic;
-	signal	cpu_hit_we			: std_logic;
-	signal	instant_raw			: std_logic;
-	signal  hit_cache_index		: unsigned(cache_index_width-1 downto 0);
-
-	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
-	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-	
-	alias fill_word_index is fill_addr(word_index_width+1 downto 2);
-	alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-	alias req_word_index is request_addr(word_index_width+1 downto 2);
-	alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-begin
-
-	cache_index_inv	<= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	tag_inv			<= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-	cpu_hit_we	<= cpu_we2 and cache_hit;
-	
-fill_address_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if fill_count_en = '1' then
-				if ACK_I = '1' then
-					fill_word_index	<= fill_word_index + 1;
-				end if;	
-			elsif cache_busy = '0' then
-				fill_addr	<= cpu_addr(addr_width-1 downto 2) & "00";
-			end if;
-		end if;
-	end process;	
-
-request_address_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_count_en = '1'then
-				if SRDY_I = '1' then
-					req_word_index	<= req_word_index + 1;
-				end if;	
-			elsif cache_busy = '0' then
-				request_addr	<= cpu_addr(addr_width-1 downto 2) & "00";
-			end if;
-		end if;
-	end process;	
-
-cpu_request_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				cpu_we_reg	<= '0';
-				cache_req	<= '0';
-			elsif cpu_en = '1' then
-				if cache_busy = '0' then
-					cpu_we2				<= cpu_we;
-					cache_req			<= '1';
-					cpu_data_reg		<= cpu_din;
-					cpu_be_reg			<= cpu_be;
-					cpu_we_reg			<= cpu_we;
-					if cpu_we = '1' then
-						hit_cache_index		<= cpu_cache_index;
-					end if;
-				end if;	
-			elsif cache_ack = '1' then
-				cache_req			<= '0';
-				cpu_we2				<= '0';
-			end if;
-		end if;
-	end process;	
-
-instant_raw_logic:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			instant_raw <= '0';
-			if cpu_word_index = fill_word_index and cpu_cache_index = hit_cache_index then
-				instant_raw	<= cpu_hit_we and cpu_en and not cpu_we;
-			end if;	
-		end if;
-	end process;	
-
-inst_tag_ram : dpram_2w2r2c_ra
-	GENERIC MAP 
-	(
-		addr_width	=> tag_ram_addr_width,
-		data_width	=> tag_ram_data_width
-	)
-	PORT MAP 
-	(
-		clk_a	=> CLK_I,
-		clk_b	=> CLK_I,
-		en_a	=> '1',
-		en_b	=> '1',
-		we_a	=> tag_ram_we,
-		we_b	=> '0',
-		addr_a	=> tag_ram_addr_wr,
-		addr_b	=> tag_ram_addr_rd,
-		din_a	=> tag_ram_din,
-		din_b	=> tag_ram_din,
-		dout_a	=> tag_ram_dout_inv,
-		dout_b	=> tag_ram_dout
-	);
-
-gen_data_ram:
-	for i in 0 to 3 generate
-	begin
-	
-	inst_data_ram : dpram_2w2r2c_ra
-		GENERIC MAP 
-		(
-			addr_width	=> lg2(cache_size),
-			data_width	=> word_t'length/4
-		)
-		PORT MAP 
-		(
-			clk_a	=> CLK_I,
-			clk_b	=> CLK_I,
-			en_a	=> '1',
-			en_b	=> '1',
-			we_a	=> cpu_data_ram_we(i),
-			we_b	=> ctrl_data_ram_we(i),
-			addr_a	=> ctrl_data_ram_addr,
-			addr_b	=> cpu_data_ram_addr,
-			din_a	=> cpu_data_reg(8*(i+1)-1 downto 8*i),
-			din_b	=> DAT_I(8*(i+1)-1 downto 8*i),
-			dout_a	=> open,
-			dout_b	=> cpu_data_ram_dout(8*(i+1)-1 downto 8*i)
-		);
-	end generate;	
-	
-	
-	
-cache_invalidate_request:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
-				invalidate_req	<= '1';
-				invalidate_all	<= ctrl.inv_all or RST_I;
-				tag_reg_inv	<= tag_inv;
-			elsif invalidate_ack = '1' then
-				invalidate_req	<= '0';
-				invalidate_all	<= '0';
-			end if;
-		end if;
-	end process;	
-
-cache_state_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s	<= init;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-
-	MRDY_O				<= fill_count_en;
-	ADDR_O				<= request_addr;
-	
-	cpu_busy			<= cache_busy;
-	cpu_dout			<= cpu_data_ram_dout;
-	
-	tag_match			<= '1' when fill_tag = cache_entry_out.tag else '0';
-	cache_hit			<= tag_match and cache_entry_out.valid;
-	tag_match_inv		<= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
-	cache_hit_inv		<= tag_match_inv and cache_entry_out_inv.valid;
-	tag_ram_din			<= to_tag_ram_data(cache_entry_in);
-	tag_ram_addr_wr		<= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
-	tag_ram_addr_rd		<= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else fill_cache_index;
-
-	cache_entry_out		<= to_dcache_entry(tag_ram_dout);
-	cache_entry_out_inv	<= to_dcache_entry(tag_ram_dout_inv);
-	
-	cpu_data_ram_addr	<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index);
-	ctrl_data_ram_addr	<= fill_cache_index & fill_word_index;
-	ctrl_data_ram_we	<= (others => fill_count_en and ACK_I);
-	cpu_data_ram_we		<= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
-	
-cache_state:
-	process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all)
-	begin
-		cache_busy 				<= cache_req;
-		cache_ack 				<= '0';
-		tag_ram_we				<= '0';
-		flush_count_en			<= '0';
-		flush_count_rst			<= '0';
-		invalidate_en			<= '0';
-		request_count_en		<= '0';
-		fill_count_en			<= '0';
-		CYC_O					<= '0';
-		STB_O					<= '0';
-		was_miss				<= '0';
-		invalidate_ack			<= '0';
-
-		cache_entry_in.tv_p		<= (others => '0');
-		cache_entry_in.tag		<= fill_tag;
-		cache_entry_in.valid	<= '0';
-		sn	<= s;
-		
-		case s is
-		when init =>
-				sn <= ready;
-		when ready =>
-			if invalidate_req = '1' then
-				sn <= invalidate;
-				invalidate_en	<= '1';
-			else	
-				if cache_req = '1' then
-					if cache_hit = '0' and cpu_we_reg = '0' then
-						sn						<= mem_request;
-						CYC_O					<= '1';
-					else
-						cache_busy 		<= instant_raw;
-						cache_ack 		<= not instant_raw;
-					end if;	
-				end if;	
-			end if;	
-		when invalidate =>
-			sn <= rd_cache;
-			invalidate_en			<= '1';
-			invalidate_ack			<= '1';
-			if invalidate_all = '1' then
-				sn	<= flush;
-				flush_count_rst		<= '1';
-			elsif cache_hit_inv = '1' then
-				tag_ram_we				<= '1';
-				cache_entry_in.valid	<= '0';
-				cache_entry_in.tag		<= (others => '0');
-				sn						<= rd_cache;
-			end if;	
-				
-		when flush =>
-			flush_count_en			<= '1';
-			invalidate_en			<= '1';
-			tag_ram_we				<= '1';
-			cache_entry_in.valid	<= '0';
-			cache_entry_in.tag		<= (others => '0');
-			if flush_count_rdy = '1' then
-				tag_ram_we			<= '0';
-				sn					<= rd_cache;
-			end if;
-		when mem_request =>
-			CYC_O		<= '1';
-			if SRDY_I = '1' then
-				sn <= mem_access;
-			end if;	
-		when mem_access =>
-			fill_count_en		<= '1';
-			request_count_en	<= '1';
-			CYC_O				<= '1';
-			STB_O				<= '1';
-			if request_count_rdy = '1' then
-				STB_O			<= '0';
-				sn 				<= mem_data;
-			end if;	
-		when mem_data =>
-			CYC_O			<= '1';
-			fill_count_en	<= '1';
-			if fill_count_rdy = '1' then
-				tag_ram_we				<= '1';
-				cache_entry_in.valid	<= '1';
-				sn						<= rd_cache;
-			end if;	
-		when rd_cache =>
-			was_miss				<= '1';
-			sn	<= ready;
-
-		when others => 
-			sn	<= ready;
-		end case;
-
-	end process;
-
-flush_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if ctrl.inv_at = '1' then
-				flush_count		<= to_integer(cache_index_inv);
-			elsif flush_count_rst = '1' then
-				flush_count_rdy	<= '0';
-				flush_count		<= 2**cache_index_width-1;
-			elsif flush_count_en = '1' then
-				if flush_count /= 0 then
-					flush_count	<= flush_count - 1;
-				else
-					flush_count_rdy	<= '1';
-				end if;	
-			end if;
-		end if;
-	end process;	
-		
-request_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_count_en = '0' then
-				request_count_rdy	<= '0';
-				request_count		<= 2**word_index_width-1;
-			else	
-				if SRDY_I = '1' then
-					if request_count /= 0 then
-						request_count 	<= request_count - 1;
-					else
-						request_count_rdy	<= '1';
-					end if;
-				end if;	
-			end if;	
-		end if;
-	end process;	
-
-fill_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if fill_count_en = '0' then
-				fill_count_rdy	<= '0';
-				fill_count		<= 2**word_index_width-1;
-			else	
-				if ACK_I = '1' then
-					if fill_count /= 0 then
-						fill_count 	<= fill_count - 1;
-					else
-						fill_count_rdy	<= '1';
-					end if;
-				end if;
-			end if;	
-		end if;
-	end process;	
-
-end behavior;
diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd
deleted file mode 100644
index 259952a..0000000
--- a/lib/CPUs/MIPS/src/core/icache.vhd
+++ /dev/null
@@ -1,488 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: JIPS top file 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library work;
-use work.mips_types.all;
-
-ENTITY icache IS
-	Generic
-	(
-		cache_size	: natural := 2048;	-- words
-		line_size	: natural := 8		-- words
-	);
-	Port
-	(
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		STB_O		: out STD_LOGIC;
-		CYC_O		: out STD_LOGIC;
-		ctrl		: in  cache_ctrl_t;
-		cpu_en		: in  STD_LOGIC;
-		cpu_addr	: in  word_t;
-		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC
-	);
-END icache;
-
-ARCHITECTURE behavior OF icache IS
-
-COMPONENT dpram_1w1r2c_ra
-	GENERIC
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	PORT (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-END COMPONENT;
-
-COMPONENT dpram_2w2r2c_ra is
-	GENERIC 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	PORT
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-END COMPONENT;
-
-	constant addr_width			: natural := 32;
-	constant word_index_width	: natural := lg2(line_size);
-	constant cache_index_width	: natural := lg2(cache_size) - word_index_width;
-	constant tag_width			: natural := addr_width - word_index_width - cache_index_width - 2;
-	constant tag_parity_width	: natural := 3;
-	constant tag_ram_data_width	: natural := 1 + tag_parity_width + tag_width;
-	constant tag_ram_addr_width	: natural := cache_index_width;
-	
-	subtype	tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0);
-
-	type icache_entry_t is record
-		valid	: std_logic;
-		tv_p	: unsigned(tag_parity_width-1 downto 0);
-		tag		: unsigned(tag_width-1 downto 0);
-	end record;
-	
-	function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is
-	variable result : icache_entry_t;
-	begin
-		result.valid	:= x(0);
-		result.tv_p		:= x(3 downto 1);
-		result.tag		:= x(tag_width+3 downto 4);
-		
-		return result;
-	end to_icache_entry;
-
-	function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is
-	variable result : tag_ram_data_t;
-	begin
-		result(0)										:= x.valid;
-		result(3 downto 1)								:= x.tv_p;
-		result(tag_width+3 downto 4)					:= x.tag;
-		
-		return result;
-	end to_tag_ram_data;
-
-	type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache, upd_cache);
-	signal s, sn : cache_state_t;
-	
-	signal	cache_req			: std_logic;
-	signal	cache_ack			: std_logic;
-	signal	cache_busy			: std_logic;
-	signal	cache_miss			: std_logic;
-	signal	tag_match			: std_logic;
-	signal	cache_miss_inv		: std_logic;
-	signal	tag_match_inv		: std_logic;
-	signal  request_addr		: unsigned(addr_width-1 downto 0);
-	signal  fill_addr			: unsigned(addr_width-1 downto 0);
-	
-	signal  cache_index_inv		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_inv				: unsigned(tag_width-1 downto 0);
-	signal  tag_reg_inv			: unsigned(tag_width-1 downto 0);
-	
-	signal	cache_entry_in		: icache_entry_t;
-	signal	cache_entry_out		: icache_entry_t;
-	signal	cache_entry_out_inv	: icache_entry_t;
-	signal  data_ram_addr_rd	: unsigned(lg2(cache_size)-1 downto 0);
-	signal  data_ram_data_rd	: word_t;
-	signal  data_ram_addr_wr	: unsigned(lg2(cache_size)-1 downto 0);
-	signal  data_ram_data_wr	: word_t;
-	signal	data_ram_we			: std_logic;
-
-	signal  tag_ram_addr_rd		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_ram_data_rd		: tag_ram_data_t;
-	signal  tag_ram_data_rd_inv	: tag_ram_data_t;
-	signal  tag_ram_addr_wr		: unsigned(cache_index_width-1 downto 0);
-	signal  tag_ram_data_wr		: tag_ram_data_t;
-	signal	tag_ram_we			: std_logic;
-	
-	signal	fill_count			: natural range 0 to 2**word_index_width-1;
-	signal	fill_count_en		: std_logic;
-	signal	fill_count_rdy		: std_logic;
-	signal	flush_count			: natural range 0 to 2**cache_index_width-1;
-	signal	flush_count_rst		: std_logic;
-	signal	flush_count_en		: std_logic;
-	signal	flush_count_rdy		: std_logic;
-	signal	request_count		: natural range 0 to 2**word_index_width-1;
-	signal	request_count_en	: std_logic;
-	signal	request_count_rdy	: std_logic;
-	signal  ram_read_en			: std_logic;
-	signal	was_miss			: std_logic;
-	signal	invalidate_all		: std_logic;
-	signal	invalidate_ack		: std_logic;
-	signal  invalidate_en		: std_logic;
-	signal  invalidate_req		: std_logic;
-	
-	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
-	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-	alias fill_word_index is fill_addr(word_index_width+1 downto 2);
-	alias fill_cache_index is fill_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias fill_tag is fill_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-	alias req_word_index is request_addr(word_index_width+1 downto 2);
-	alias req_cache_index is request_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	alias req_tag is request_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-begin
-
-	ram_read_en		<= cpu_en or was_miss;
-	cache_index_inv	<= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
-	tag_inv			<= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
-
-	
-fill_address_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if fill_count_en = '1' then
-				if ACK_I = '1' then
-					fill_word_index	<= fill_word_index + 1;
-				end if;	
-			elsif cache_busy = '0' then
-				fill_addr	<= cpu_addr(addr_width-1 downto 2) & "00";
-			end if;
-		end if;
-	end process;	
-
-request_address_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_count_en = '1'then
-				if SRDY_I = '1' then
-					req_word_index	<= req_word_index + 1;
-				end if;	
-			elsif cache_busy = '0' then
-				request_addr	<= cpu_addr(addr_width-1 downto 2) & "00";
-			end if;
-		end if;
-	end process;	
-
-cpu_request_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				cache_req	<= '0';
-			elsif cpu_en = '1' then
-				if cache_busy = '0' then
-					cache_req			<= '1';
-				end if;	
-			elsif cache_ack = '1' then
-				cache_req			<= '0';
-			end if;
-		end if;
-	end process;	
-
-cache_invalidate_request:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then
-				invalidate_req	<= '1';
-				invalidate_all	<= ctrl.inv_all or RST_I;
-				tag_reg_inv	<= tag_inv;
-			elsif invalidate_ack = '1' then
-				invalidate_req	<= '0';
-				invalidate_all	<= '0';
-			end if;
-		end if;
-	end process;	
-
-inst_tag_ram : dpram_2w2r2c_ra
-	GENERIC MAP 
-	(
-		addr_width	=> tag_ram_addr_width,
-		data_width	=> tag_ram_data_width
-	)
-	PORT MAP
-	(
-		clk_a	=> CLK_I,
-		clk_b	=> CLK_I,
-		en_a	=> '1',
-		en_b	=> ram_read_en,
-		we_a	=> tag_ram_we,
-		we_b	=> '0',
-		addr_a	=> tag_ram_addr_wr,
-		addr_b	=> tag_ram_addr_rd,
-		din_a	=> tag_ram_data_wr,
-		din_b	=> tag_ram_data_wr,
-		dout_a	=> tag_ram_data_rd_inv,
-		dout_b	=> tag_ram_data_rd
-	);
-
-inst_data_ram : dpram_1w1r2c_ra
-	GENERIC MAP
-	(
-		addr_width	=> lg2(cache_size),
-		data_width	=> word_t'length
-	)
-	PORT MAP
-	(
-		clk_a	=> CLK_I,
-		clk_b	=> CLK_I,
-		en_a	=> '1',
-		en_b	=> ram_read_en,
-		we_a	=> data_ram_we,
-		addr_a	=> data_ram_addr_wr,
-		addr_b	=> data_ram_addr_rd,
-		din_a	=> data_ram_data_wr,
-		dout_b	=> data_ram_data_rd
-	);
-	
-cache_state_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s	<= init;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-
-	MRDY_O			<= fill_count_en;
-	ADDR_O				<= fill_tag & fill_cache_index & req_word_index & "00";
-	
-	cpu_busy			<= cache_busy;
-	cpu_dout			<= data_ram_data_rd;
-	
-	cache_entry_out		<= to_icache_entry(tag_ram_data_rd);
-	tag_match			<= '1' when fill_tag = cache_entry_out.tag else '0';
-	cache_miss			<= not (tag_match and cache_entry_out.valid);
-
-	cache_entry_out_inv	<= to_icache_entry(tag_ram_data_rd_inv);
-	tag_match_inv		<= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0';
-	cache_miss_inv		<= not (tag_match_inv and cache_entry_out_inv.valid);
-
-	tag_ram_data_wr		<= to_tag_ram_data(cache_entry_in);
-	tag_ram_addr_wr		<= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else fill_cache_index;
-	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else fill_cache_index;
-	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index);
-	data_ram_addr_wr	<= fill_cache_index & fill_word_index;
-	data_ram_data_wr	<= DAT_I;
-	data_ram_we			<= fill_count_en and ACK_I;
-
-cache_state:
-	process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, fill_tag, SRDY_I, invalidate_req, invalidate_all)
-	begin
-		cache_busy 				<= cache_req;
-		cache_ack 				<= '0';
-		tag_ram_we				<= '0';
-		flush_count_en			<= '0';
-		flush_count_rst			<= '0';
-		invalidate_en			<= '0';
-		request_count_en		<= '0';
-		fill_count_en			<= '0';
-		CYC_O					<= '0';
-		STB_O					<= '0';
-		was_miss				<= '0';
-		invalidate_ack			<= '0';
-
-		cache_entry_in.tv_p		<= (others => '0');
-		cache_entry_in.tag		<= fill_tag;
-		cache_entry_in.valid	<= '0';
-		sn	<= s;
-		
-		case s is
-		when init =>
-			sn <= ready;
-		when ready =>
-			if invalidate_req = '1' then
-				sn 				<= invalidate;
-				invalidate_en	<= '1';
-			elsif cache_req = '1' then
-				if cache_miss = '1' then
-					sn						<= mem_request;
-					CYC_O					<= '1';
-				else
-					cache_busy 		<= '0';
-					cache_ack 		<= '1';
-				end if;	
-			end if;	
-		when invalidate =>
-			sn <= rd_cache;
-			invalidate_en			<= '1';
-			invalidate_ack			<= '1';
-			if invalidate_all = '1' then
-				sn					<= flush;
-				flush_count_rst		<= '1';
-			elsif cache_miss_inv = '0' then
-				tag_ram_we				<= '1';
-				cache_entry_in.valid	<= '0';
-				cache_entry_in.tag		<= (others => '0');
-				sn						<= rd_cache;
-			end if;	
-				
-		when flush =>
-			flush_count_en			<= '1';
-			invalidate_en			<= '1';
-			tag_ram_we				<= '1';
-			cache_entry_in.valid	<= '0';
-			cache_entry_in.tag		<= (others => '0');
-			if flush_count_rdy = '1' then
-				tag_ram_we			<= '0';
-				sn					<= rd_cache;
-			end if;
-		when mem_request =>
-			CYC_O		<= '1';
-			if SRDY_I = '1' then
-				sn <= mem_access;
-			end if;	
-		when mem_access =>
-			request_count_en	<= '1';
-			fill_count_en		<= '1';
-			CYC_O				<= '1';
-			STB_O				<= '1';
-			if request_count_rdy = '1' then
-				STB_O			<= '0';
-				sn				<= mem_data;
-			end if;	
-		when mem_data =>
-			CYC_O			<= '1';
-			fill_count_en	<= '1';
-			if fill_count_rdy = '1' then
-				tag_ram_we				<= '1';
-				cache_entry_in.valid	<= '1';
-				sn						<= rd_cache;
-			end if;	
-		when rd_cache =>
-			was_miss	<= '1';
-			sn			<= ready;
-		when others => 
-			sn	<= ready;
-		end case;
-
-	end process;
-
-flush_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if ctrl.inv_at = '1' then
-				flush_count		<= to_integer(cache_index_inv);
-			elsif flush_count_rst = '1' then
-				flush_count_rdy	<= '0';
-				flush_count		<= 2**cache_index_width-1;
-			elsif flush_count_en = '1' then
-				if flush_count /= 0 then
-					flush_count	<= flush_count - 1;
-				else
-					flush_count_rdy	<= '1';
-				end if;	
-			end if;
-		end if;
-	end process;	
-		
-request_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_count_en = '0' then
-				request_count_rdy	<= '0';
-				request_count		<= 2**word_index_width-1;
-			else	
-				if SRDY_I = '1' then
-					if request_count /= 0 then
-						request_count 	<= request_count - 1;
-					else
-						request_count_rdy	<= '1';
-					end if;
-				end if;	
-			end if;	
-		end if;
-	end process;	
-
-fill_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if fill_count_en = '0' then
-				fill_count_rdy	<= '0';
-				fill_count		<= 2**word_index_width-1;
-			else	
-				if ACK_I = '1' then
-					if fill_count /= 0 then
-						fill_count 	<= fill_count - 1;
-					else
-						fill_count_rdy	<= '1';
-					end if;
-				end if;
-			end if;	
-		end if;
-	end process;	
-
-end behavior;
diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd
deleted file mode 100644
index a64b5a4..0000000
--- a/lib/CPUs/MIPS/src/core/mips_alu.vhd
+++ /dev/null
@@ -1,184 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity alu is
-	Generic 
-	(
-		data_width : integer := 8
-	);
-	Port 
-	(
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		op2_shifted	: in  unsigned (data_width-1 downto 0);
-		ctrl		: in  alu_ctrl_t;
-		result		: out unsigned (data_width-1 downto 0);
-		flags		: out alu_flags_t
-	);
-end alu;
-
-architecture Behavioral of alu is
-
-	signal sum_res			: unsigned (data_width-1 downto 0);
-	signal and_res			: unsigned (data_width-1 downto 0);
-	signal xor_res			: unsigned (data_width-1 downto 0);
-	signal nor_res			: unsigned (data_width-1 downto 0);
-	signal or_res			: unsigned (data_width-1 downto 0);
-	signal eq, sa, sb, sr, c, z	: STD_LOGIC;
-	signal lts, ltu			: STD_LOGIC;
-
---------------------------------------------------------------------------
-begin
-
-	eq			<= '1' when op1_in = op2_in else '0' after 3 ns;
-	sa			<= op1_in(op1_in'left);
-	sb			<= op2_in(op2_in'left);
-	sr			<= sum_res(sum_res'left);
-	z			<= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns;
-	
-	flags.uvf	<= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr));
-	flags.ovf	<= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr));
---	lts			<= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb))));
-	lts			<= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr));
-	
-	ltu			<= (not eq) and (not c);
-	flags.lts	<= lts;
-	flags.ltu	<= ltu;
-	flags.c		<= c;
-	
---------------------------------------------------------------------------
-proc_op_and:
-	process(op1_in, op2_in)
-	variable x1, x2	: unsigned (data_width-1 downto 0);
-	begin
-		x1 := op1_in;
-		x2 := op2_in;
-
-		and_res <= (x1 and x2) after 1 ns;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_proc_xor:
-	process(op1_in, op2_in)
-	variable x1, x2	: unsigned (data_width-1 downto 0);
-	begin
-		x1 := op1_in;
-		x2 := op2_in;
-		
-		xor_res <= (x1 xor x2) after 2 ns;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_proc_nor:
-	process(op1_in, op2_in)
-	variable x1, x2	: unsigned (data_width-1 downto 0);
-	begin
-		x1 := op1_in;
-		x2 := op2_in;
-		
-		nor_res <= (x1 nor x2) after 1 ns;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_proc_or:
-	process(op1_in, op2_in)
-	variable x1, x2	: unsigned (data_width-1 downto 0);
-	begin
-		x1 := op1_in;
-		x2 := op2_in;
-		
-		or_res <= (x1 or x2) after 1 ns;
-		
-	end process;
-
---------------------------------------------------------------------------
-proc_alu_out:
-	process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu)
-	begin
-		
-		result		<= sum_res;
-		
-		case ctrl.outsel is
-		
-		when alu_adder =>
-			result 		<= sum_res;
-
-		when alu_and =>
-			result 		<= and_res;
-			
-		when alu_xor =>
-			result 		<= xor_res;
-
-		when alu_nor =>
-			result 		<= nor_res;
-
-		when alu_or =>
-			result 		<= or_res;
-
-		when alu_shift2 =>
-			result 		<= op2_shifted;
-
-		when alu_ltu =>
-			result		<= (data_width-1 downto 1 => '0') & ltu;
-
-		when alu_lts =>
-			result		<= (data_width-1 downto 1 => '0') & lts;
-
-		when others => null;
-
-		end case;
-		
-	end process;
-
---------------------------------------------------------------------------
-alu_addsub:
-	process(op1_in, op2_in, ctrl)
-	variable sum  : unsigned(data_width+1 downto 0);
-	variable op1, op2 : unsigned(data_width+1 downto 0);
-	begin
-		
-		op1 := '0' & op1_in & not ctrl.add;
-		if (ctrl.add = '1') then
-			op2 := '0' & op2_in & '0';
-		else
-			op2 := '0' & not op2_in & '1';
-		end if;
-		sum := op1 + op2; 
-
-		-- Form sum + carry
-		sum_res <= unsigned(sum(data_width downto 1)) after 4 ns;
-		c <= sum(sum'left) after 4 ns;
-		
-	end process;	
-
---------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd
deleted file mode 100644
index 51b5ed7..0000000
--- a/lib/CPUs/MIPS/src/core/mips_bcu.vhd
+++ /dev/null
@@ -1,52 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity bcu is
-	Generic 
-	(
-		data_width : integer := 8
-	);
-	Port 
-	(
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		flags		: out bcu_flags_t
-	);
-end bcu;
-
-architecture Behavioral of bcu is
-
---------------------------------------------------------------------------
-begin
-
-	flags.eq	<= '1' when op1_in = op2_in else '0' after 3 ns;
-	flags.ltz	<= op1_in(op1_in'left) after 1 ns;
-
---------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
deleted file mode 100644
index e2aae9f..0000000
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ /dev/null
@@ -1,552 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: JIPS top file 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-
-entity biu is
-	Generic
-	(
-		icache_size	: natural := 2048;	-- words
-		icache_line	: natural := 8;		-- words
-		dcache_size	: natural := 2048;	-- words
-		dcache_line	: natural := 8		-- words
-	);
-	Port
-	(
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(3 downto 0);
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		cop0_ctrl_in	: in cop0_ctrl_out_t;
-		cpu_clk			: in  STD_LOGIC;
-		cpu_imem_err	: out STD_LOGIC;
-		cpu_imem_rdy	: out STD_LOGIC;
-		cpu_imem_en		: in  STD_LOGIC;
-		cpu_imem_addr	: in  word_t;
-		cpu_imem_din	: out word_t;
-		cpu_dmem_err	: out STD_LOGIC;
-		cpu_dmem_rdy	: out STD_LOGIC;
-		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_we		: in  STD_LOGIC;
-		cpu_dmem_be		: in  unsigned(3 downto 0);
-		cpu_dmem_dout	: in  word_t;
-		cpu_dmem_din	: out word_t;
-		cpu_dmem_addr	: in  word_t
-	);
-end biu;
-
-architecture behavior of biu is
-
-	COMPONENT icache
-	GENERIC
-	(
-		cache_size	: natural;	-- words
-		line_size	: natural	-- words
-	);
-	PORT
-	(
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		STB_O		: out STD_LOGIC;
-		CYC_O		: out STD_LOGIC;
-		ctrl		: in  cache_ctrl_t;
-		cpu_en		: in  STD_LOGIC;
-		cpu_addr	: in  word_t;
-		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	COMPONENT dcache
-	GENERIC
-	(
-		cache_size	: natural;	-- words
-		line_size	: natural	-- words
-	);
-	PORT
-	(
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		ADDR_O		: out word_t;
-		DAT_I		: in  word_t;
-		STB_O		: out STD_LOGIC;
-		CYC_O		: out STD_LOGIC;
-		ctrl		: in  cache_ctrl_t;
-		cpu_en		: in  STD_LOGIC;
-		cpu_we		: in  STD_LOGIC;
-		cpu_be		: in  unsigned(3 downto 0);
-		cpu_addr	: in  word_t;
-		cpu_din		: in  word_t;
-		cpu_dout	: out word_t;
-		cpu_busy	: out STD_LOGIC
-	);
-	END COMPONENT;
-
-	type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish);
-	
-	signal s, sn 			: bus_state_t;
-	signal bus_idle			: std_logic;
-	signal busy				: std_logic;
-	signal dmem_be			: unsigned(3 downto 0);
-	signal dcache_dout		: word_t;
-	signal dcache_mem_gnt	: std_logic;
-	signal icache_mem_gnt 	: std_logic;
-	signal dmem_mem_wr_gnt	: std_logic;
-	signal dmem_mem_rd_gnt	: std_logic;
-	signal dcache_busy		: std_logic;
-	signal icache_busy 		: std_logic;
-	signal CYC_O_icache		: std_logic;
-	signal CYC_O_dcache		: std_logic;
-	signal CYC_O_dmem_rd	: std_logic;
-	signal CYC_O_dmem_wr	: std_logic;
-	signal SRDY_I_icache	: std_logic;
-	signal SRDY_I_dcache	: std_logic;
-	signal MRDY_O_icache	: std_logic;
-	signal MRDY_O_dcache	: std_logic;
-	signal ADDR_O_icache	: word_t;
-	signal ADDR_O_dcache	: word_t;
-	signal ADDR_O_dmem_rd	: word_t;
-	signal ADDR_O_dmem_wr	: word_t;
-	signal STB_O_icache		: std_logic;
-	signal STB_O_dcache		: std_logic;
-	signal STB_O_dmem_rd	: std_logic;
-	signal STB_O_dmem_wr	: std_logic;
-	signal DAT_I_dmem_rd	: word_t;
-	signal DAT_O_dmem_wr	: word_t;
-	signal SEL_O_dmem_wr	: unsigned(3 downto 0);
-	signal SEL_O_dmem_rd	: unsigned(3 downto 0);
-	signal dcached			: std_logic;
-	signal dcache_en2		: std_logic;
-	signal dcache_en		: std_logic;
-	signal uncached_access	: std_logic;
-	signal ACK				: std_logic;
-	signal DAT				: unsigned(31 downto 0);
-
-	type timeout_cnt_t is range 0 to 1E5-1;	
-	signal bus_timeout_cnt	: timeout_cnt_t;
-	signal bus_timeout		: std_logic;
-	
-	signal bout_fifo_din	: unsigned(68 downto 0);
-	signal bout_fifo_dout	: unsigned(68 downto 0);
-	signal bout_fifo_re		: std_logic;
-	signal bout_fifo_we		: std_logic;
-	signal bout_fifo_full	: std_logic;
-	signal bout_fifo_empty	: std_logic;
-	signal bout_rdy			: std_logic;
-
-	signal bin_fifo_din		: unsigned(31 downto 0);
-	signal bin_fifo_dout	: unsigned(31 downto 0);
-	signal bin_fifo_re		: std_logic;
-	signal bin_fifo_we		: std_logic;
-	signal bin_fifo_full	: std_logic;
-	signal bin_fifo_empty	: std_logic;
-
-	alias bout_fifo_addr_in is bout_fifo_din(31 downto 0);
-	alias bout_fifo_data_in is bout_fifo_din(63 downto 32);
-	alias bout_fifo_sel_in is bout_fifo_din(67 downto 64);
-	alias bout_fifo_we_in is bout_fifo_din(68);
-	alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0);
-	alias bout_fifo_data_out is bout_fifo_dout(63 downto 32);
-	alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64);
-	alias bout_fifo_we_out is bout_fifo_dout(68);
-
-	signal write_fifo_din	: unsigned(67 downto 0);
-	signal write_fifo_dout	: unsigned(67 downto 0);
-	signal write_fifo_re	: std_logic;
-	signal write_fifo_we	: std_logic;
-	signal write_fifo_full	: std_logic;
-	signal write_fifo_empty	: std_logic;
-
-	alias write_fifo_addr_in is write_fifo_din(31 downto 0);
-	alias write_fifo_data_in is write_fifo_din(63 downto 32);
-	alias write_fifo_sel_in is write_fifo_din(67 downto 64);
-	alias write_fifo_addr_out is write_fifo_dout(31 downto 0);
-	alias write_fifo_data_out is write_fifo_dout(63 downto 32);
-	alias write_fifo_sel_out is write_fifo_dout(67 downto 64);
-
-	signal read_cycle	: std_logic;
-
-begin
-
-read_cyc_register:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if RST_I = '1' then
-				read_cycle		<= '0';
-			else
-				read_cycle 		<= (dmem_mem_rd_gnt and CYC_O_dmem_rd) 
-								or (dcache_mem_gnt and CYC_O_dcache) 
-								or (icache_mem_gnt and CYC_O_icache);
-			end if;
-		end if;
-	end process;	
-					
-	MRDY_O			<= not bin_fifo_full;
-	CYC_O			<= not bout_fifo_empty or read_cycle;
-	STB_O			<= not bout_fifo_empty;
-	ADDR_O			<= bout_fifo_addr_out;
-	DAT_O			<= bout_fifo_data_out;
-	SEL_O			<= bout_fifo_sel_out;
-	WE_O			<= bout_fifo_we_out;
-
-	cpu_imem_rdy	<= not icache_busy after 4.5 ns;
-	busy			<= CYC_O_dmem_rd or dcache_busy or (write_fifo_full);
-	cpu_dmem_rdy	<= not busy after 4.5 ns;
-	
-inst_icache : icache
-	GENERIC MAP
-	(
-		cache_size	=> icache_size,	-- words
-		line_size	=> icache_line	-- words
-	)	
-	PORT MAP
-	(
-		CLK_I		=> cpu_clk,
-		RST_I		=> RST_I,
-		STB_O		=> STB_O_icache,
-		CYC_O		=> CYC_O_icache,
-		ADDR_O		=> ADDR_O_icache,
-		MRDY_O		=> MRDY_O_icache,
-		DAT_I		=> DAT,
-		ACK_I		=> ACK,
-		SRDY_I		=> SRDY_I_icache,
-		ctrl		=> cop0_ctrl_in.icache,
-		cpu_en		=> cpu_imem_en,
-		cpu_addr	=> cpu_imem_addr,
-		cpu_dout	=> cpu_imem_din,
-		cpu_busy	=> icache_busy
-	);
-
-	SRDY_I_icache	<= bout_rdy and icache_mem_gnt;
-
-inst_dcache : dcache
-	GENERIC MAP
-	(
-		cache_size	=> dcache_size,	-- words
-		line_size	=> dcache_line	-- words
-	)
-	PORT MAP
-	(
-		CLK_I		=> cpu_clk,
-		RST_I		=> RST_I,
-		CYC_O		=> CYC_O_dcache,
-		STB_O		=> STB_O_dcache,
-		ADDR_O		=> ADDR_O_dcache,
-		MRDY_O		=> MRDY_O_dcache,
-		DAT_I		=> DAT,
-		ACK_I		=> ACK,
-		SRDY_I		=> SRDY_I_dcache,
-		ctrl		=> cop0_ctrl_in.dcache,
-		cpu_en		=> dcache_en,
-		cpu_we		=> cpu_dmem_we,
-		cpu_be		=> cpu_dmem_be,
-		cpu_addr	=> cpu_dmem_addr,
-		cpu_din		=> cpu_dmem_dout,
-		cpu_dout	=> dcache_dout,
-		cpu_busy	=> dcache_busy
-	);
-
-	SRDY_I_dcache	<= bout_rdy and dcache_mem_gnt;
-
-	dcached			<= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0';
-	cpu_dmem_din	<= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd;
-	dcache_en		<= dcached and cpu_dmem_en and dcache_en2; -- or write_fifo_full);
-	
--- Instantiate synchronous FIFO
-inst_bin_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> 4,
-		data_width			=> 32,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	CLK_I,
-		clk_r		=>	cpu_clk,
-		we			=>	bin_fifo_we,
-		re			=>	bin_fifo_re,
-		fifo_full	=>	bin_fifo_full,
-		fifo_empty	=>	bin_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  bin_fifo_din,
-		data_r		=>  bin_fifo_dout
-	);
-	
-	bin_fifo_din	<= DAT_I;
-	DAT				<= bin_fifo_dout;
-	ACK				<= not bin_fifo_empty;
-	bin_fifo_we		<= ACK_I;
-	bin_fifo_re		<= dmem_mem_rd_gnt or MRDY_O_icache or MRDY_O_dcache;
-	
--- Instantiate synchronous FIFO
-inst_bout_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> 4,
-		data_width			=> 69,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	cpu_clk,
-		clk_r		=>	CLK_I,
-		we			=>	bout_fifo_we,
-		re			=>	bout_fifo_re,
-		fifo_full	=>	bout_fifo_full,
-		fifo_empty	=>	bout_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  bout_fifo_din,
-		data_r		=>  bout_fifo_dout
-	);
-	bout_rdy			<= not bout_fifo_full;
-	bout_fifo_re		<= SRDY_I and not bin_fifo_full;
-	
-	bout_fifo_we		<= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache;
-
-	bout_fifo_data_in	<= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-');
-	
-	bout_fifo_addr_in	<= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else
-						   ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else
-						   ADDR_O_dcache when dcache_mem_gnt = '1' else
-						   ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
-
-	bout_fifo_sel_in	<= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
-						   SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
-
-	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
-
--- Instantiate synchronous FIFO
-inst_write_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> 4,
-		data_width			=> 68,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	cpu_clk,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  write_fifo_din,
-		data_r		=>  write_fifo_dout
-	);
-
-	CYC_O_dmem_wr	<= not write_fifo_empty;
-	DAT_O_dmem_wr	<= write_fifo_data_out;
-	ADDR_O_dmem_wr	<= write_fifo_addr_out;
-	SEL_O_dmem_wr	<= write_fifo_sel_out;
-
-	write_fifo_data_in	<= cpu_dmem_dout;
-	write_fifo_addr_in	<= cpu_dmem_addr;
-	write_fifo_sel_in	<= cpu_dmem_be;
-	write_fifo_re		<= STB_O_dmem_wr;
-	write_fifo_we		<= cpu_dmem_en and not busy and cpu_dmem_we;
-	
-dmem_rd_flags:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			uncached_access	<= '0';
-			if RST_I = '1' then
-				CYC_O_dmem_rd		<= '0';
-				dcache_en2			<= '1';
-			else	
-				if ACK = '1' and dmem_mem_rd_gnt = '1' then
-					uncached_access		<= '1';
-					CYC_O_dmem_rd		<= '0';
-					dcache_en2			<= '1';
-				end if;	
-				if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then
-					if dcached = '0' then
-						CYC_O_dmem_rd	<= '1';
-						dcache_en2		<= '0';
-					end if;	
-				end if;
-			end if;
-		end if;
-	end process;	
-	
-dmem_rd_data:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if RST_I = '1' then
-				DAT_I_dmem_rd		<= (others => '0');
-			elsif ACK = '1' and CYC_O_dmem_rd = '1' then
-				DAT_I_dmem_rd		<= DAT;
-			end if;
-		end if;
-	end process;	
-	
-dmem_rd_regs:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if cpu_dmem_en = '1' and busy = '0' then
-				ADDR_O_dmem_rd		<= cpu_dmem_addr;
-				SEL_O_dmem_rd		<= cpu_dmem_be;
-			end if;
-		end if;
-	end process;	
-	
-bus_state_next:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if RST_I = '1' then
-				s	<= init;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-	
-bus_state:
-	process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK)
-	begin
-		
-		icache_mem_gnt		<= '0';
-		dcache_mem_gnt		<= '0';
-		dmem_mem_rd_gnt		<= '0';	
-		dmem_mem_wr_gnt		<= '0';	
-		STB_O_dmem_rd		<= '0';
-		STB_O_dmem_wr		<= '0';
-		bus_idle			<= '0';
-		sn					<= s;
-		case s is
-		when init =>
-			sn		<= ready;
-		when ready =>
-			bus_idle	<= '1';
-			if CYC_O_dmem_wr = '1' then
-				sn			<= write_bus;
-			elsif CYC_O_dmem_rd = '1' then
-				sn			<= read_bus;
-			elsif CYC_O_icache = '1' then
-				sn			<= icache_bus_access;
-			elsif CYC_O_dcache = '1' then
-				sn			<= dcache_bus_access;
-			end if;
-		when icache_bus_access =>
-			icache_mem_gnt	<= '1';
-			if CYC_O_icache = '0' then
-				sn			<= ready;
-			end if;	
-		when dcache_bus_access =>
-			dcache_mem_gnt	<= '1';
-			if CYC_O_dcache = '0' then
-				sn			<= ready;
-			end if;	
-		when write_bus =>
-			dmem_mem_wr_gnt	<= '1';	
-			if CYC_O_dmem_wr = '1' then
-				if bout_rdy = '1' then
-					STB_O_dmem_wr	<= '1';
-				end if;
-			else
-				sn			<= ready;
-			end if;	
-		when read_bus =>
-			dmem_mem_rd_gnt	<= '1';	
-			if bout_rdy = '1' then
-				STB_O_dmem_rd	<= '1';
-				sn				<= read_finish;
-			end if;	
-		when read_finish =>
-			dmem_mem_rd_gnt	<= '1';	
-			if ACK = '1' then
-				sn			<= ready;
-			end if;
-		when others =>
-			sn	<= ready;
-		end case;		
-				
-	end process;	
-
-bus_timeout_counter:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if bus_idle = '0' then
-				if bus_timeout_cnt /= 0 then
-					bus_timeout_cnt	<= bus_timeout_cnt - 1;
-				else
-					bus_timeout	<= '1';
-				end if;	
-			else
-				bus_timeout_cnt	<= timeout_cnt_t'high;
-				bus_timeout		<= '0';
-			end if;
-		end if;
-	end process;	
-
-bus_err:
-	process(cpu_clk)
-	begin
-		if rising_edge(cpu_clk) then
-			if RST_I = '1' then
-				cpu_imem_err	<= '0';
-				cpu_dmem_err	<= '0';
-			elsif bus_timeout = '1' then
-				cpu_imem_err	<= icache_mem_gnt;
-				cpu_dmem_err	<= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt;
-			end if;
-		end if;
-	end process;	
-
--------------------------------------------------------------------
-	
-end behavior;
diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd
deleted file mode 100644
index af898eb..0000000
--- a/lib/CPUs/MIPS/src/core/mips_cop.vhd
+++ /dev/null
@@ -1,546 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-use work.mips_instr.all;
-
-entity cop is
-	Generic
-	(
-		icache_size	: natural := 2048;	-- words
-		icache_line	: natural := 8;		-- words
-		dcache_size	: natural := 2048;	-- words
-		dcache_line	: natural := 8		-- words
-	);
-	Port 
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		eb			: in  STD_LOGIC;
-		int			: in  unsigned(5 downto 0);
-		nmi			: in  STD_LOGIC;
-		ir_en		: in  STD_LOGIC;
-		ir			: in  word_t;
-		ctrl_in		: in  cop0_ctrl_in_t;
-		ctrl_out	: out cop0_ctrl_out_t;
-		din			: in  word_t;
-		dout		: out word_t
-	);
-end cop;
-
-architecture Behavioral of cop is
-
-	signal epc				: word_t;
-	signal cause			: word_t;
-	signal status			: word_t;
-	signal imem_addr		: word_t;
-	signal imem_addr_we		: STD_LOGIC;
-	signal BadVAddr			: word_t;
-	signal exc_code			: unsigned(4 downto 0);
-	signal test_reg			: word_t;
-	signal test_reg_we		: STD_LOGIC;
-	signal stat_reg_we		: STD_LOGIC;
-	signal eflags_reg_we	: STD_LOGIC;
-	signal epc_reg_we		: STD_LOGIC;
-	signal code_reg_we		: STD_LOGIC;
-	signal ip_reg_we		: STD_LOGIC;
-	signal bd				: STD_LOGIC;
-	signal sw_int			: unsigned(1 downto 0);
-	signal ip				: unsigned(7 downto 0);
-	signal im				: unsigned(7 downto 0);
-	signal status_save		: STD_LOGIC;
-	signal status_rest		: STD_LOGIC;
-	signal eflags			: exc_flags_t;
-	signal EB_reg			: STD_LOGIC;
-	signal icache_info		: unsigned(7 downto 0);
-	signal dcache_info		: unsigned(7 downto 0);
-	signal reg_rptr			: reg_ptr_t;
-	signal reg_wptr			: reg_ptr_t;
-	signal inject_exc		: STD_LOGIC;
-	signal latch_vect_en	: STD_LOGIC;
-	signal int_nmi			: STD_LOGIC;
-	signal nmi_asserted		: std_logic;
-	
-	type cop_pipe_t is record
-		opc			: opcode_t;
-		RFE			: std_logic;
-		CO			: std_logic;
-		reg_ptr		: reg_ptr_t;
-		rs			: reg_ptr_t;
-		rd			: reg_ptr_t;
-		rt			: reg_ptr_t;
-		func		: func_t;
-		we			: std_logic;
-		re			: std_logic;
-		cs			: std_logic;
-	end record;
-	
-	signal cop_pipe_ID : cop_pipe_t;
-	signal cop_pipe_EX : cop_pipe_t;
-	
-	function eval_int(ip : unsigned) return STD_LOGIC is
-	variable result : STD_LOGIC;
-	begin
-			result := '0';
-			for i in ip'range loop
-				result := result or ip(i);
-			end loop;
-
-			return result;
-	end eval_int;
-
-	type exc_state_t is (exc_idle, exc_pipe_flush, exc_commit, exc_inject, exc_enter, exc_leave, exc_left);
-	signal exc_state, exc_staten : exc_state_t;
-	
---------------------------------------------------------------------------
-begin
-
-	icache_info 					<= "00" & to_unsigned(lg2(icache_line), 3) & to_unsigned(lg2(icache_size)-8, 3);
-	dcache_info 					<= "00" & to_unsigned(lg2(dcache_line), 3) & to_unsigned(lg2(dcache_size)-8, 3);
-	cop_pipe_ID.cs					<= ir_en;
-	cop_pipe_ID.opc					<= extract_opc(ir);
-	cop_pipe_ID.rs					<= extract_rs(ir);
-	cop_pipe_ID.rd					<= extract_rd(ir);
-	cop_pipe_ID.rt					<= extract_rt(ir);
-	cop_pipe_ID.func				<= extract_func(ir);
-	cop_pipe_ID.CO					<= ir(25);
-	cop_pipe_ID.re					<= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0';
-	cop_pipe_ID.we					<= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0';
-	cop_pipe_ID.RFE					<= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0';
-	ctrl_out.EB						<= EB_reg xor (status(25) and status(1));
-	ctrl_out.user_mode				<= status(1);
-	ctrl_out.exc_inject				<= inject_exc or rst;
-	cop_pipe_ID.reg_ptr				<= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt;
-	
-	im				<= status(15 downto 8);
-	cause			<= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00";
-
-	eflags.Ov		<= ctrl_in.events.alu_ovf or ctrl_in.events.alu_uvf;
-	eflags.DAdEL	<= ctrl_in.events.data_load_err;
-	eflags.DAdES	<= ctrl_in.events.data_store_err;
-	eflags.IAdEL	<= ctrl_in.events.inst_load_err;
-	eflags.IAdEK	<= ctrl_in.events.inst_priv_addr and status(1);
-	eflags.Sys		<= ctrl_in.events.syscall;
-	eflags.Bp		<= ctrl_in.events.break;
-	eflags.RI		<= ctrl_in.events.illegal;
-	eflags.Int		<= ctrl_in.events.int;
-
--- NMI/RST transition detector
-proc_nmi_transition:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				int_nmi			<= '0';
-				nmi_asserted	<= '0';
-			elsif latch_vect_en = '1' then
-				int_nmi	<= '0';
-			elsif nmi_asserted = '1' then
-				if nmi = '0' then
-					nmi_asserted	<= '0';
-					int_nmi			<= '1';
-				end if;	
-			elsif nmi = '1' then
-				nmi_asserted	<= '1';
-			end if;	
-		end if;
-	end process;
-
-
--- Main exception FSM
-proc_exc_state:
-	process(exc_state, ctrl_in, cop_pipe_ID)
-	begin
-	
-		ctrl_out.exc_commit		<= '0';
-		ctrl_out.exc_pending	<= '0';
-		ctrl_out.exc_exit 		<= '0';
-		epc_reg_we				<= '0';	
-		code_reg_we				<= '0';	
-		status_save				<= '0';
-		status_rest				<= '0';
-		inject_exc				<= '0';
-		imem_addr_we			<= '0';
-		latch_vect_en			<= '0';
-
-		exc_staten	<= exc_state;
-		
-		case exc_state is
-		
-		when exc_idle =>
-			if cop_pipe_ID.RFE = '1' then
-				exc_staten			<= exc_leave;
-				ctrl_out.exc_exit 	<= '1';
-				ctrl_out.exc_commit	<= '1';
-			elsif ctrl_in.exc_req = '1' then
-				exc_staten			<= exc_pipe_flush;
-				imem_addr_we		<= '1';
-			end if;
-			
-		when exc_pipe_flush =>
-			ctrl_out.exc_pending	<= '1';
-			ctrl_out.exc_commit		<= '1';
-			if ctrl_in.exc_ack = '1' then
-				exc_staten			<= exc_commit;
-			end if;
-			
-		when exc_commit =>
-			latch_vect_en			<= '1';
-			ctrl_out.exc_pending	<= '1';
-			ctrl_out.exc_commit		<= '1';
-			if ctrl_in.sdu.ID_stall = '0' then
-				exc_staten			<= exc_inject;
-			end if;
-
-		when exc_inject =>
-			ctrl_out.exc_pending	<= '1';
-			ctrl_out.exc_commit		<= '1';
-			code_reg_we				<= '1';
-			status_save				<= '1';
-			epc_reg_we				<= '1';
-			inject_exc				<= '1';
-			exc_staten				<= exc_enter;
-
-		when exc_enter =>
-			ctrl_out.exc_pending	<= '1';
-			exc_staten				<= exc_idle;
-
-		when exc_leave =>
-			exc_staten				<= exc_left;
-			status_rest				<= '1';
-			ctrl_out.exc_exit 		<= '1';
-			ctrl_out.exc_commit		<= '1';
-
-		when exc_left =>
-			exc_staten				<= exc_idle;
-
-		when others =>
-			exc_staten <= exc_idle;
-		
-		end case;
-	end process;	
-
-proc_exc_state_next:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				exc_state <= exc_idle;
-			else
-				exc_state <= exc_staten;
-			end if;	
-		end if;
-	end process;
-
--- Endian switch sampled at hard reset
-sample_endian:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				EB_reg <= eb;
-			end if;	
-		end if;
-	end process;
-
--- Sample imem_addr for later use
-exception_last_imem_addr:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if imem_addr_we = '1' then
-				imem_addr <= ctrl_in.imem_addr;
-			end if;	
-		end if;
-	end process;
-
--- EPC reg and BD-bit write
-cop_exception_epc_write:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				bd		<= '0';
-				epc		<= (others => '0');
-			elsif epc_reg_we = '1' then
-				bd			<= '0';
-				epc			<= ctrl_in.epc_mem;
-				if ctrl_in.bd_wb = '1' then
-					bd			<= '1';
-					epc			<= ctrl_in.epc_wb;
-				end if;
-			end if;
-		end if;
-	end process;
-
--- BadVaddr and exception code write
-cop_exception_map:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				exc_code	<= (others => '0');
-				BadVAddr	<= (others => '0');
-			elsif code_reg_we = '1' then
-				if eflags.Ov = '1'	then
-					exc_code	<= "01100";
-				elsif eflags.Sys = '1'	then
-					exc_code	<= "01000";
-				elsif eflags.Bp = '1'	then
-					exc_code	<= "01001";
-				elsif eflags.RI = '1'	then
-					exc_code	<= "01010";
-				elsif eflags.IAdEL = '1'	then
-					exc_code	<= "00100";
-					BadVAddr	<= imem_addr;
-				elsif eflags.IAdEK = '1'	then
-					exc_code	<= "00100";
-					BadVAddr	<= imem_addr;
-				elsif eflags.DAdEL = '1'	then
-					exc_code	<= "00100";
-					BadVAddr	<= ctrl_in.dmem_addr;
-				elsif eflags.DAdES = '1'	then
-					exc_code	<= "00101";
-					BadVAddr	<= ctrl_in.dmem_addr;
-				elsif eflags.Int = '1' then
-					exc_code	<= "00000";
-				end if;
-			end if;
-		end if;
-	end process;
-
-	ctrl_out.icache.inv_addr	<= test_reg;
-	ctrl_out.dcache.inv_addr	<= test_reg;
-	
--- Custom I/D-Cache operations:  invalidate all/line
-cop_cache_op:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			ctrl_out.icache.inv_at	<= '0';
-			ctrl_out.icache.inv_all	<= '0';
-			ctrl_out.dcache.inv_at	<= '0';
-			ctrl_out.dcache.inv_all	<= '0';
-			if cop_pipe_ID.cs = '1' and cop_pipe_ID.CO = '1' then
-				case cop_pipe_ID.func is
-					when "100000" =>
-						ctrl_out.icache.inv_all	<= '1';
-					when "100001" =>
-						ctrl_out.icache.inv_at	<= '1';
-					when "100010" =>
-						ctrl_out.dcache.inv_all	<= '1';
-					when "100011" =>
-						ctrl_out.dcache.inv_at	<= '1';
-
-					when others => null;
-				end case;
-			end if;	
-		end if;
-	end process;
-
--- IP register write and signalling Int to pipeline
-cop_ip_reg_write:
-	process(clk)
-	variable ip_v  : unsigned(7 downto 0);
-	variable ipm_v : unsigned(7 downto 0);
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				sw_int	<= (others => '0');
-			elsif ctrl_in.sdu.WB_nop = '0' then
-				if ip_reg_we = '1' then
-					sw_int	<= din(9 downto 8);
-				end if;	
-			end if;	
-			ip_v			:= (int & sw_int);
-			ipm_v			:= ip_v and im;
-			ip				<= ip_v;
-			ctrl_out.int	<= (eval_int(ipm_v) and status(0));
-			ctrl_out.NMI	<= int_nmi;
-		end if;
-	end process;
-
--- Exception vector dispatch
-cop_exc_vector:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				ctrl_out.exc_vec		<= X"BFC00000";
-			elsif latch_vect_en = '1' then
-				if ctrl_in.events.nmi = '1' then
-					ctrl_out.exc_vec		<= X"BFC00000";
-				else
-					ctrl_out.exc_vec		<= X"80000080";
-					if status(22) = '1' then
-						ctrl_out.exc_vec	<= X"BFC00180";
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--- Cop pipeline
-cop_pipe:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cop_pipe_EX.cs	<= '0';
-				cop_pipe_EX.we	<= '0';
-				cop_pipe_EX.re	<= '0';
-			elsif ctrl_in.sdu.stall_all = '0' then
-				cop_pipe_EX		<= cop_pipe_ID;
-				if cop_pipe_ID.we = '1' then
-					reg_wptr	<= cop_pipe_ID.reg_ptr;
-				end if;
-				if cop_pipe_ID.re = '1' then
-					reg_rptr	<= cop_pipe_ID.reg_ptr;
-				end if;
-			end if;
-		end if;
-	end process;
-
--- COP Register read
-cop_register_read:
-	process(reg_rptr, BadVAddr, status, cause, epc, dcache_info, icache_info, test_reg)
-	variable reg : word_t;
-	begin
-	
-		case reg_rptr is
-		when "01000" =>			-- BadVAddr
-			reg	:= BadVAddr;
-
-		when "01100" =>			-- Status
-			reg	:= status;
-
-		when "01101" =>			-- Cause
-			reg	:= cause;
-
-		when "01110" =>			-- EPC (Exception Program Counter)
-			reg	:= epc;
-
-		when "01111" =>			-- PRId (Processor Revision Register)
-			reg	:= dcache_info & icache_info & X"02" & to_unsigned(REVISION ,8);
-
-		when "11111" =>			-- test_reg
-			reg	:= test_reg;
-
-		when others =>
-			reg	:= (others => '-');
-
-		end case;	
-
-		dout	<= reg after 2 ns;
-
-	end process;
-
--- COP Register write strobe generation
-cop_we_gen:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				test_reg_we	<= '0';
-				stat_reg_we	<= '0';
-				ip_reg_we	<= '0';
-			elsif ctrl_in.sdu.stall_all = '0' then
-				test_reg_we	<= '0';
-				stat_reg_we	<= '0';
-				ip_reg_we	<= '0';
-				if cop_pipe_EX.we = '1' then
-
-					case reg_wptr is
-
-					when "01100" =>
-						stat_reg_we	<= '1'; -- not status(1) or status(28);
-					when "01101" =>			
-						ip_reg_we	<= '1'; -- not status(1) or status(28);
-					when "11111" =>
-						test_reg_we	<= '1'; -- not status(1) or status(28);
-					when others => null;
-
-					end case;
-
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
--- COP Test Register
-cop_test_reg_write:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				test_reg	<= (others => '0');
-			elsif ctrl_in.sdu.WB_nop = '0' then
-				if test_reg_we = '1' then
-					test_reg	<= din;
-				end if;
-			end if;
-		end if;
-	end process;
-
--- COP Status Register
-cop_status_reg_write:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				status	<= X"00600000";
-			elsif status_save = '1' then
-				if ctrl_in.events.nmi = '0' then
-					status(5 downto 4)	<= status(3 downto 2);
-					status(3 downto 2)	<= status(1 downto 0);
-				else	
-					status(22)	<= '1';
-				end if;
-				status(1 downto 0)	<= "00";
-			elsif status_rest = '1' then
-				status(1 downto 0)	<= status(3 downto 2);
-				status(3 downto 2)	<= status(5 downto 4);
-			elsif ctrl_in.sdu.WB_nop = '0' then
-				if stat_reg_we = '1' then
-					if status(1) = '0' then
-						status(0)			<= din(0);	-- IEc
-						status(1)			<= din(1);	-- KUc
-						status(2)			<= din(2);	-- IEp
-						status(3)			<= din(3);	-- KUp
-						status(4)			<= din(4);	-- IEo
-						status(5)			<= din(5);	-- KUo
-					end if;	
-					status(15 downto 8)		<= din(15 downto 8);	-- IM
-					status(22)				<= din(22);				-- BEV
-					status(25)				<= din(25);				-- RE
-				end if;
-			end if;	
-		end if;
-	end process;
-	
---------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd
deleted file mode 100644
index cdb6115..0000000
--- a/lib/CPUs/MIPS/src/core/mips_instr.vhd
+++ /dev/null
@@ -1,1062 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Types, constants and functions for JCPU
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-
---------------------------------------------------------------------------
-package mips_instr is
-
-	function extract_opc(instr : word_t) return opcode_t;
-	function extract_rs(instr : word_t) return reg_ptr_t;
-	function extract_rt(instr : word_t) return reg_ptr_t;
-	function extract_rd(instr : word_t) return reg_ptr_t;
-	function extract_shamt(instr : word_t) return shamt_t;
-	function extract_func(instr : word_t) return func_t;
-	function extract_simm32(instr : word_t) return word_t;
-	function extract_uimm16(instr : word_t) return word_t;
-	function extract_jimm32(instr, pc : word_t) return word_t;
-	function extract_bimm18(instr, pc : word_t) return word_t;
-	function decode_op(instr : word_t) return op_t;
-	function ctrl_lines_default return ctrl_lines_t;
-	function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t;
-
-end mips_instr;
-
---------------------------------------------------------------------------
-library work;
-use work.mips_types.all;
-
-package body mips_instr is
-
-	function extract_opc(instr : word_t) return opcode_t is
-	variable result : opcode_t;
-	begin
-		result := instr(31 downto 26);
-		
-		return result;
-
-	end extract_opc;
-	
-	function extract_rs(instr : word_t) return reg_ptr_t is
-	variable result : reg_ptr_t;
-	begin
-		result := instr(25 downto 21);
-		
-		return result;
-
-	end extract_rs;
-	
-	function extract_rt(instr : word_t) return reg_ptr_t is
-	variable result : reg_ptr_t;
-	begin
-		result := instr(20 downto 16);
-		
-		return result;
-
-	end extract_rt;
-
-	function extract_rd(instr : word_t) return reg_ptr_t is
-	variable result : reg_ptr_t;
-	begin
-		result := instr(15 downto 11);
-		
-		return result;
-
-	end extract_rd;
-
-	function extract_shamt(instr : word_t) return shamt_t is
-	variable result : shamt_t;
-	begin
-		result := instr(10 downto 6);
-		
-		return result;
-
-	end extract_shamt;
-
-	function extract_func(instr : word_t) return func_t is
-	variable result : func_t;
-	begin
-		result := instr(5 downto 0);
-		
-		return result;
-
-	end extract_func;
-
-	function extract_simm32(instr : word_t) return word_t is
-	variable result : word_t;
-	begin
-		result := (31 downto 16 => instr(15)) & instr(15 downto 0);
-		
-		return result;
-
-	end extract_simm32;
-
-	function extract_uimm16(instr : word_t) return word_t is
-	variable result : word_t;
-	begin
-		result := (31 downto 16 => '0') & instr(15 downto 0);
-		
-		return result;
-
-	end extract_uimm16;
-
-	function extract_jimm32(instr, pc : word_t) return word_t is
-	variable result : word_t;
-	begin
-		result := pc(31 downto 28) & instr(25 downto 0) & "00";
-		
-		return result;
-
-	end extract_jimm32;
-
-	function extract_bimm18(instr, pc : word_t) return word_t is
-	variable result : word_t;
-	begin
-		result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00";
-		
-		return result;
-
-	end extract_bimm18;
-
-	function decode_op(instr : word_t) return op_t is
-	variable result : op_t;
-	variable opc : natural range 0 to 63;
-	variable func : natural range 0 to 63;
-	variable rt : natural range 0 to 31;
-	variable rs : natural range 0 to 31;
-	
-	begin
-		
-		opc		:= to_integer(extract_opc(instr));
-		func	:= to_integer(extract_func(instr));
-		rt		:= to_integer(extract_rt(instr));
-		rs		:= to_integer(extract_rs(instr));
-		
-		result := op_illegal;
-		
-		case opc is
-
-		when 0 =>
-			case func is
-
-			when 0 =>
-				result := op_sll;
-			
-			when 2 =>
-				result := op_srl;
-
-			when 3 =>
-				result := op_sra;
-
-			when 4 =>
-				result := op_sllv;
-
-			when 6 =>
-				result := op_srlv;
-
-			when 7 =>
-				result := op_srav;
-
-			when 8 =>
-				result := op_jr;
-
-			when 9 =>
-				result := op_jalr;
-
-			when 12 =>
-				result := op_syscall;
-
-			when 13 =>
-				result := op_break;
-
-			when 16 =>
-				result := op_mfhi;
-
-			when 17 =>
-				result := op_mthi;
-
-			when 18 =>
-				result := op_mflo;
-
-			when 19 =>
-				result := op_mtlo;
-
-			when 24 =>
-				result := op_mult;
-
-			when 25 =>
-				result := op_multu;
-
-			when 26 =>
-				result := op_div;
-
-			when 27 =>
-				result := op_divu;
-
-			when 32 =>
-				result := op_add;
-			
-			when 33 =>
-				result := op_addu;
-			
-			when 34 =>
-				result := op_sub;
-			
-			when 35 =>
-				result := op_subu;
-			
-			when 36 =>
-				result := op_and;
-			
-			when 37 =>
-				result := op_or;
-			
-			when 38 =>
-				result := op_xor;
-			
-			when 39 =>
-				result := op_nor;
-			
-			when 42 =>
-				result := op_slt;
-			
-			when 43 =>
-				result := op_sltu;
-				
-			when others => null; -- undef
-			
-			end case;
-			
-		when 1 =>
-			case rt is
-
-			when 0 =>
-				result := op_bltz;
-				
-			when 1 =>
-				result := op_bgez;
-			
-			when 16 =>
-				result := op_bltzal;
-
-			when 17 =>
-				result := op_bgezal;
-				
-			when others => null; -- undef
-			
-			end case;
-
-		when 2 =>
-			result	:= op_j;
-			
-		when 3 =>
-			result	:= op_jal;
-			
-		when 4 =>
-			result	:= op_beq;
-			
-		when 5 =>
-			result	:= op_bne;
-
-		when 6 =>
-			result	:= op_blez;
-
-		when 7 =>
-			result	:= op_bgtz;
-
-		when 8 =>
-			result	:= op_addi;
-
-		when 9 =>
-			result	:= op_addiu;
-
-		when 10 =>
-			result	:= op_slti;
-
-		when 11 =>
-			result	:= op_sltiu;
-
-		when 12 =>
-			result	:= op_andi;
-
-		when 13 =>
-			result	:= op_ori;
-
-		when 14 =>
-			result	:= op_xori;
-
-		when 15 =>
-			result	:= op_lui;
-
-		when 16 =>
-			result	:= op_cop0;
-			case rs is
-				when 0 =>
-					result	:= op_mfc0;
-				when 2 =>
-					result	:= op_cfc0;	-- illegal
-				when 4 =>
-					result	:= op_mtc0;
-				when 6 =>
-					result	:= op_ctc0;	-- illegal
-				when 8 =>
-					case rt is
-						when 0 =>
-							result := op_bcf0;	-- illegal
-						when 1 =>
-							result := op_bct0;	-- illegal
-			
-						when others => null; -- undef
-					end case;	
-							
-				when others => null; -- undef
-			
-			end case;
-
-		when 17 =>
-			result	:= op_cop1;
-			case rs is
-				when 0 =>
-					result	:= op_mfc1;
-				when 2 =>
-					result	:= op_cfc1;
-				when 4 =>
-					result	:= op_mtc1;
-				when 6 =>
-					result	:= op_ctc1;
-				when 8 =>
-					case rt is
-						when 0 =>
-							result := op_bcf1;
-						when 1 =>
-							result := op_bct1;
-			
-						when others => null; -- undef
-					end case;	
-							
-				when others => null; -- undef
-			
-			end case;
-
-		when 18 =>
-			result	:= op_cop2;
-			case rs is
-				when 0 =>
-					result	:= op_mfc2;
-				when 2 =>
-					result	:= op_cfc2;
-				when 4 =>
-					result	:= op_mtc2;
-				when 6 =>
-					result	:= op_ctc2;
-				when 8 =>
-					case rt is
-						when 0 =>
-							result := op_bcf2;
-						when 1 =>
-							result := op_bct2;
-			
-						when others => null; -- undef
-					end case;	
-							
-				when others => null; -- undef
-			
-			end case;
-
-		when 19 =>
-			result	:= op_cop3;
-			case rs is
-				when 0 =>
-					result	:= op_mfc3;
-				when 2 =>
-					result	:= op_cfc3;
-				when 4 =>
-					result	:= op_mtc3;
-				when 6 =>
-					result	:= op_ctc3;
-				when 8 =>
-					case rt is
-						when 0 =>
-							result := op_bcf3;
-						when 1 =>
-							result := op_bct3;
-			
-						when others => null; -- undef
-					end case;	
-							
-				when others => null; -- undef
-			
-			end case;
-
-		when 32 =>
-			result	:= op_lb;
-
-		when 33 =>
-			result	:= op_lh;
-
-		when 34 =>
-			result	:= op_lwl;
-
-		when 35 =>
-			result	:= op_lw;
-
-		when 36 =>
-			result	:= op_lbu;
-
-		when 37 =>
-			result	:= op_lhu;
-
-		when 38 =>
-			result	:= op_lwr;
-
-		when 40 =>
-			result	:= op_sb;
-
-		when 41 =>
-			result	:= op_sh;
-
-		when 42 =>
-			result	:= op_swl;
-
-		when 43 =>
-			result	:= op_sw;
-
-		when 46 =>
-			result	:= op_swr;
-
-		when 48 =>
-			result	:= op_lwc0;	-- illegal
-			
-		when 49 =>
-			result	:= op_lwc1;
-			
-		when 50 =>
-			result	:= op_lwc2;
-
-		when 51 =>
-			result	:= op_lwc3;
-
-		when 56 =>
-			result	:= op_swc0;	-- illegal
-
-		when 57 =>
-			result	:= op_swc1;
-			
-		when 58 =>
-			result	:= op_swc2;
-
-		when 59 =>
-			result	:= op_swc3;
-
-		when others => null; -- undef
-
-		end case;
-
-		return result;
-
-	end decode_op;
-
-	function ctrl_lines_default return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	begin
-		result.cop_instr_en				:= '0';
-		result.cop_read					:= '0';
-		result.jump						:= '0';
-		result.jump_long				:= '0';
-		result.branch					:= '0';
-		result.bc_src					:= bc_eq_ne;
-		result.bc_not					:= '0';
-		result.alu.outsel				:= alu_adder;
-		result.alu.add					:= '1';
-		result.alu.shift_right			:= '0';
-		result.alu.shift_arith			:= '0';
-		result.shamt2_srcsel			:= sa_src_imm;
-		result.alu.op1_src				:= alu_src_reg;
-		result.alu.op2_src				:= alu_src_reg;
-		result.imm_src					:= src_imm16;
-		result.reg_write				:= '0';
-		result.dmem_we					:= '0';
-		result.dmem_en					:= '0';
-		result.wptr_srcsel				:= wptr_src_imm;
-		result.reg_link					:= '0';
-		result.shift_offset				:= "00";
-		result.shift_byp				:= '1';
-		result.byte_en_byp				:= '1';
-		result.sign_ext_byp				:= '1';
-		result.word4_en					:= '0';
-		result.word2_en					:= '0';
-		result.align_left				:= '0';
-		result.load_signed				:= '0';
-		result.mul_access				:= '0';
-		result.mul_hilo_we				:= '0';
-		result.mul_start				:= '0';
-		result.mul_s_un					:= '0';
-		result.mul_mul_divn				:= '0';
-		result.mul_hilo_sel				:= '1';
-		result.exc_break				:= '0';
-		result.exc_syscall				:= '0';
-		result.exc_illegal				:= '0';
-		result.except_en				:= '0';
-		result.alu_exc_en				:= '0';
-
-		return result;
-	
-	end ctrl_lines_default;
-
-	function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t is
-	variable result : ctrl_lines_t;
-	variable opc	: integer range 0 to 2**opcode_t'length-1;
-	variable func	: integer range 0 to 2**func_t'length-1;
-	variable rt		: integer range 0 to 2**reg_ptr_t'length-1;
-	variable rs		: integer range 0 to 2**reg_ptr_t'length-1;
-	begin
-	
-		result	:= ctrl_lines_default;
-		opc		:= to_integer(extract_opc(instr));
-		func 	:= to_integer(extract_func(instr));
-		rt 		:= to_integer(extract_rt(instr));
-		rs 		:= to_integer(extract_rs(instr));
-
-		case opc is
---		SPECIAL
-		when 0 =>	
-			case func is
-
-	--		when op_add  =>
-			when 32 =>
-				result.alu.outsel		:= alu_adder;
-				result.alu.add			:= '1';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-				result.alu_exc_en		:= '1';
-
-	--		when op_addu =>
-			when 33 =>
-				result.alu.outsel		:= alu_adder;
-				result.alu.add			:= '1';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_and =>
-			when 36 =>
-				result.alu.outsel		:= alu_and;
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_break =>
-			when 13 =>
-				result.exc_break		:= '1';
-				result.except_en		:= '1';
-
-	--		when op_div =>
-			when 26 =>
-				result.mul_access		:= '1';
-				result.mul_start		:= '1';
-				result.mul_s_un			:= '1';
-				result.mul_mul_divn		:= '0';
-
-	--		when op_divu =>
-			when 27 =>
-				result.mul_access		:= '1';
-				result.mul_start		:= '1';
-				result.mul_s_un			:= '0';
-				result.mul_mul_divn		:= '0';
-
-	--		when op_jalr =>
-			when 9 =>
-				result.jump_long		:= '1';
-				result.wptr_srcsel		:= wptr_src_imm;
-				result.reg_write		:= '1';
-				result.reg_link			:= '1';
-
-	--		when op_jr =>
-			when 8 =>
-				result.jump_long		:= '1';
-
-	--		when op_mfhi =>
-			when 16 =>
-				result.reg_write		:= '1';
-				result.mul_access		:= '1';
-				result.mul_hilo_sel		:= '1';
-
-	--		when op_mflo =>
-			when 18 =>
-				result.reg_write		:= '1';
-				result.mul_access		:= '1';
-				result.mul_hilo_sel		:= '0';
-
-	--		when op_mthi =>
-			when 17 =>
-				result.mul_hilo_we		:= '1';
-				result.mul_hilo_sel		:= '1';
-
-	--		when op_mtlo =>
-			when 19 =>
-				result.mul_hilo_we		:= '1';
-				result.mul_hilo_sel		:= '0';
-
-	--		when op_mult =>
-			when 24 =>
-				result.mul_access		:= '1';
-				result.mul_start		:= '1';
-				result.mul_s_un			:= '1';
-				result.mul_mul_divn		:= '1';
-
-	--		when op_multu =>
-			when 25 =>
-				result.mul_access		:= '1';
-				result.mul_start		:= '1';
-				result.mul_s_un			:= '0';
-				result.mul_mul_divn		:= '1';
-
-	--		when op_or =>
-			when 37 =>
-				result.alu.outsel		:= alu_or;
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_nor =>
-			when 39 =>
-				result.alu.outsel		:= alu_nor;
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_sll =>
-			when 0 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '0';
-				result.shamt2_srcsel	:= sa_src_imm;
-				result.reg_write		:= '1';
-
-	--		when op_sllv =>
-			when 4 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '0';
-				result.shamt2_srcsel	:= sa_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_slt =>
-			when 42 =>
-				result.alu.outsel		:= alu_lts;
-				result.alu.add			:= '0';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_sltu =>
-			when 43 =>
-				result.alu.outsel		:= alu_ltu;
-				result.alu.add			:= '0';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_sra =>
-			when 3 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '1';
-				result.alu.shift_arith	:= '1';
-				result.shamt2_srcsel	:= sa_src_imm;
-				result.reg_write		:= '1';
-
-	--		when op_srav =>
-			when 7 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '1';
-				result.alu.shift_arith	:= '1';
-				result.shamt2_srcsel	:= sa_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_srl =>
-			when 2 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '1';
-				result.alu.shift_arith	:= '0';
-				result.shamt2_srcsel	:= sa_src_imm;
-				result.reg_write		:= '1';
-
-	--		when op_srlv =>
-			when 6 =>
-				result.alu.op2_src		:= alu_src_reg;
-				result.alu.outsel		:= alu_shift2;
-				result.alu.shift_right	:= '1';
-				result.alu.shift_arith	:= '0';
-				result.shamt2_srcsel	:= sa_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_sub =>
-			when 34 =>
-				result.alu.outsel		:= alu_adder;
-				result.alu.add			:= '0';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-				result.alu_exc_en		:= '1';
-
-	--		when op_subu =>
-			when 35 =>
-				result.alu.outsel		:= alu_adder;
-				result.alu.add			:= '0';
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-	--		when op_syscall =>
-			when 12 =>
-				result.exc_syscall		:= '1';
-				result.except_en		:= '1';
-
-	--		when op_xor =>
-			when 38 =>
-				result.alu.outsel		:= alu_xor;
-				result.alu.op1_src		:= alu_src_reg;
-				result.alu.op2_src		:= alu_src_reg;
-				result.reg_write		:= '1';
-
-			when others => 
-				result.exc_illegal		:= '1';
-
-			end case;
-
---		REGIMM
-		when 1 =>	
-			case rt is
-
-	--		when op_bgez =>
-			when 1 =>
-				result.branch			:= '1';
-				result.bc_src			:= bc_ltz_gez;
-				result.bc_not			:= '1';
-
-	--		when op_bgezal =>
-			when 17 =>
-				result.branch			:= '1';
-				result.bc_src			:= bc_ltz_gez;
-				result.bc_not			:= '1';
-				result.wptr_srcsel		:= wptr_src_const;
-				result.reg_write		:= '1';
-				result.reg_link			:= '1';
-
-	--		when op_bltz =>
-			when 0 =>
-				result.branch			:= '1';
-				result.bc_src			:= bc_ltz_gez;
-				result.bc_not			:= '0';
-
-	--		when op_bltzal =>
-			when 16 =>
-				result.branch			:= '1';
-				result.bc_src			:= bc_ltz_gez;
-				result.bc_not			:= '0';
-				result.wptr_srcsel		:= wptr_src_const;
-				result.reg_write		:= '1';
-				result.reg_link			:= '1';
-
-			when others => 
-				result.exc_illegal		:= '1';
-
-			end case;
-
---		when COPz =>
-		when 16 | 17 | 18 | 19 =>			
-			result.cop_instr_en		:= '1';
-			case rs is
-				when 0 =>	-- MFCz
-					result.cop_read		:= '1';
-					result.reg_write	:= '1';
-				when 2 =>	-- CFCz
-					result.cop_read		:= '1';
-					result.reg_write	:= '1';
-							
-				when others => null; -- undef
-			
-			end case;
-			
-			
---		when op_addi =>
-		when 8 =>
-			result.imm_src			:= src_imm32;
-			result.alu.outsel		:= alu_adder;
-			result.alu.add			:= '1';
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.reg_write		:= '1';
-			result.alu_exc_en		:= '1';
-
---		when op_addiu =>
-		when 9 =>
-			result.imm_src			:= src_imm32;
-			result.alu.outsel		:= alu_adder;
-			result.alu.add			:= '1';
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.reg_write		:= '1';
-
---		when op_andi =>
-		when 12 =>
-			result.imm_src			:= src_imm16;
-			result.alu.outsel		:= alu_and;
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.reg_write		:= '1';
-
---		when op_beq =>
-		when 4 =>
-			result.branch			:= '1';
-			result.bc_src			:= bc_eq_ne;
-			result.bc_not			:= '0';
-			
---		when op_bgtz =>
-		when 7 =>
-			result.branch			:= '1';
-			result.bc_src			:= bc_lez_gtz;
-			result.bc_not			:= '1';
-			
---		when op_blez =>
-		when 6 =>
-			result.branch			:= '1';
-			result.bc_src			:= bc_lez_gtz;
-			result.bc_not			:= '0';
-			
---		when op_bne =>
-		when 5 =>
-			result.branch			:= '1';
-			result.bc_src			:= bc_eq_ne;
-			result.bc_not			:= '1';
-
---		when op_j =>
-		when 2 =>
-			result.jump				:= '1';
-
---		when op_jal =>
-		when 3 =>
-			result.jump				:= '1';
-			result.wptr_srcsel		:= wptr_src_const;
-			result.reg_write		:= '1';
-			result.reg_link			:= '1';
-
---		when op_lb =>
-		when 32 =>
-			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '1';
-			result.sign_ext_byp		:= '0';
-			result.load_signed		:= '1';
-			result.word4_en			:= '1';
-			
---		when op_lbu =>
-		when 36 =>
-			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '1';
-			result.sign_ext_byp		:= '0';
-			result.load_signed		:= '0';
-			result.word4_en			:= '1';
-			
---		when op_lh =>
-		when 33 =>
-			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.sign_ext_byp		:= '0';
-			result.byte_en_byp		:= '1';
-			result.load_signed		:= '1';
-			result.word2_en			:= '1';
-			result.except_en		:= '1';
-			
---		when op_lhu =>
-		when 37 =>
-			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.sign_ext_byp		:= '0';
-			result.byte_en_byp		:= '1';
-			result.load_signed		:= '0';
-			result.word2_en			:= '1';
-			result.except_en		:= '1';
-			
---		when op_lui =>
-		when 15 =>
-			result.imm_src			:= src_imm16_high;
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.alu.outsel		:= alu_adder;
-			result.reg_write		:= '1';
-			result.alu.add			:= '1';
-
---		when op_lw =>
-		when 35 =>
---			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.except_en		:= '1';
-			
---		when op_lwcz =>
-		when 48 | 49 | 50 | 51 =>
---			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.except_en		:= '1';
-			result.cop_instr_en		:= '1';
-			
---		when op_lwl =>
-		when 34 =>
---			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.shift_offset		:= "01";
-			result.align_left		:= '1';
-			
---		when op_lwr =>
-		when 38 =>
---			result.imm_src			:= src_imm32;
-			result.dmem_en			:= '1';
-			result.reg_write		:= '1';
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.shift_offset		:= "00";
-			result.align_left		:= '0';
-			
---		when op_ori =>
-		when 13 =>
-			result.imm_src			:= src_imm16;
-			result.alu.outsel		:= alu_or;
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.reg_write		:= '1';
-
---		when op_sb =>
-		when 40 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.word4_en			:= '1';
-			
---		when op_sh =>
-		when 41 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.word2_en			:= '1';
-			result.except_en		:= '1';
-			
---		when op_slti =>
-		when 10 =>
-			result.alu.outsel		:= alu_lts;
-			result.alu.add			:= '0';
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.imm_src			:= src_imm32;
-			result.reg_write		:= '1';
-
---		when op_sltiu =>
-		when 11 =>
-			result.alu.outsel		:= alu_ltu;
-			result.alu.add			:= '0';
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.imm_src			:= src_imm32;
-			result.reg_write		:= '1';
-
---		when op_sw =>
-		when 43 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.except_en		:= '1';
-			
---		when op_swcz =>
-		when 56 | 57 | 58 | 59 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.except_en		:= '1';
-			result.cop_instr_en		:= '1';
-			result.cop_read			:= '1';
-
---		when op_swl =>
-		when 42 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.shift_offset		:= "01";
-			
---		when op_swr =>
-		when 46 =>
-			result.dmem_en			:= '1';
-			result.dmem_we			:= '1';
---			result.imm_src			:= src_imm32;
-			result.shift_byp		:= '0';
-			result.byte_en_byp		:= '0';
-			result.align_left		:= '1';
-			
---		when op_xori =>
-		when 14 =>
-			result.imm_src			:= src_imm16;
-			result.alu.outsel		:= alu_xor;
-			result.alu.op1_src		:= alu_src_reg;
-			result.alu.op2_src		:= alu_src_imm;
-			result.reg_write		:= '1';
-
-		when others => 
-			result.exc_illegal		:= '1';
-
-		end case;
-		
-		return result;
-	
-	end opcode_ctrl_lines;
-
-end mips_instr;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd
deleted file mode 100644
index efce36b..0000000
--- a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd
+++ /dev/null
@@ -1,454 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The arithmetic logic unit
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity muldiv is
-	Port 
-	(
-		rst			: in  std_logic;
-		clk			: in  std_logic;
-		hilo_we		: in  std_logic;
-		din_hi		: in  word_t;
-		din_lo		: in  word_t;
-		mul_divn	: in  std_logic;
-		start		: in  std_logic;
-		s_un		: in  std_logic;
-		hilo_sel	: in  std_logic;
-		busy		: out std_logic;
-		dout		: out word_t
-	);
-end muldiv;
-
-architecture Behavioral of muldiv is
-
-	subtype pprod_t is unsigned (39 downto 0);
-	subtype prod_t is unsigned (63 downto 0);
-	subtype byte_t is unsigned (7 downto 0);
-	
-	type pprod_array_t is array (natural range <>) of pprod_t;
-	type word_array_t is array (natural range <>) of word_t;
-	type byte_array_t is array (natural range <>) of byte_t;
-
-	signal pprod : pprod_array_t(0 to 3);
-	signal sign1 : std_logic;
-	signal sign2 : std_logic;
-	signal s1_r : std_logic;
-	signal s2_r : std_logic;
-	signal sr_r : std_logic;
-	signal cy : unsigned (3 downto 0);
-	signal mul_start : std_logic;
-	signal mul_en : std_logic;
-	signal sum_en : std_logic;
-	signal pre_sum_vld : std_logic;
-	signal pp_reg  : unsigned (63 downto 8);
-	signal pre_const : word_array_t(0 to 1);
-	signal result : prod_t;
-	signal add_op1 : unsigned (39 downto 0);
-	signal add_op2 : unsigned (39 downto 0);
-	signal add_res : unsigned (39 downto 0);
-	signal ppadd_op1 : word_array_t(0 to 3);
-	signal ppadd_op2 : word_array_t(0 to 3);
-	signal ppadd_res : word_array_t(0 to 3);
-	signal ppadd_cyi : unsigned (3 downto 0);
-	signal ppadd_cyo : unsigned (3 downto 0);
-
-	signal pp_op1_r : word_t;
-	signal pp_op1 : word_t;
-	signal pp_op2 : word_t;
-	signal pp_op2_r : byte_array_t(0 to 3);
-	signal bsy : std_logic;
-
-	signal div_add_res : unsigned (32 downto 0);
-	signal div_add_op1 : unsigned (32 downto 0);
-	signal div_add_op2 : unsigned (32 downto 0);
-	signal div_add_cyi : std_logic;
-	signal div_qbit : std_logic;
-	signal div_start : std_logic;
-	signal div_en : std_logic;
-
-	signal div_A : unsigned (32 downto 0);
-	signal div_M : unsigned (32 downto 0);
-	signal div_M_n : unsigned (32 downto 0);
-	signal div_Q : word_t;
-	
-	type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3);
-	signal s, sn : md_state_t;
-	signal cycle_cnt : natural range 0 to 31;
-	signal cycle_cnt_preset : natural range 0 to 31;
-	signal cycle_cnt_load : std_logic;
-	signal div_fin_en : unsigned (2 downto 0);
-	
---------------------------------------------------------------------------
-begin
--- 9A0CD0570B88D78	
-
-	busy		<= bsy;
-
-	sign1		<= din_hi(din_hi'left) and s_un;
-	sign2		<= din_lo(din_lo'left) and s_un;
-	pp_op1		<= not din_hi when sign1 = '1' else din_hi;
-	pp_op2		<= not din_lo when sign2 = '1' else din_lo;
-	
---------------------------------------------------------------------------
-md_state:
-	process(s, start, mul_divn, cycle_cnt)
-	begin
-		
-		bsy					<= '1';
-		cycle_cnt_load		<= '0';
-		cycle_cnt_preset	<= 7;
-	
-		mul_en		<= '0';
-		div_en		<= '0';
-		sum_en		<= '0';
-		pre_sum_vld	<= '0';
-		mul_start	<= '0';
-		div_start	<= '0';
-		div_fin_en	<= "000";
-		sn	<= s;
-		case s is
-		when md_rdy =>
-			bsy	<= '0';
-			if start = '1' then
-				if mul_divn = '1' then
-					sn	<= mul_pre1;
-					cycle_cnt_load <= '1';
-					cycle_cnt_preset <= 7;
-					mul_start	<= '1';
-				else
-					sn	<= div_process;
-					cycle_cnt_load <= '1';
-					cycle_cnt_preset <= 31;
-					div_start	<= '1';
-				end if;
-			end if;
-		when mul_pre1 =>
-			pre_sum_vld <= '1';
-			mul_en	<= '1';
-			sn	<= mul_pre2;
-		when mul_pre2 =>
-			pre_sum_vld <= '1';
-			mul_en	<= '1';
-			sn	<= mul_pp;
-		when mul_pp =>
-			mul_en	<= '1';
-			if cycle_cnt = 0 then
-				cycle_cnt_load <= '1';
-				cycle_cnt_preset <= 3;
-				sn	<= mul_sum;
-			end if;
-		when mul_sum =>
-			sum_en	<= '1';
-			if cycle_cnt = 0 then
-				bsy	<= '0';
-				sn	<= md_rdy;
-			end if;
-		when div_process =>
-			div_en	<= '1';
-			if cycle_cnt = 0 then
-				sn	<= div_post1;
-			end if;
-		when div_post1 =>
-			div_fin_en	<= "001";
-			sn	<= div_post2;
-		when div_post2 =>
-			div_fin_en	<= "010";
-			sn	<= div_post3;
-		when div_post3 =>
-			div_fin_en	<= "100";
-			sn	<= md_rdy;
-			bsy	<= '0';
-		when others =>
-			sn	<= md_rdy;
-		end case;		
-				
-	end process;	
-
-md_state_next:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				s	<= md_rdy;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-	
-md_cycle_cnt:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cycle_cnt		<= 0;
-			elsif cycle_cnt_load = '1' then
-				cycle_cnt	<= cycle_cnt_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt		<= cycle_cnt - 1;
-			end if;	
-		end if;
-	end process;	
-	
-proc_out_reg:
-	process(hilo_sel, result)
-	begin
-		if hilo_sel = '1' then
-			dout <= result(63 downto 32);
-		else	
-			dout <= result(31 downto 0);
-		end if;
-	end process;	
-	
-proc_in_reg:
-	process(clk)
-	variable pre_cond : unsigned(1 downto 0);
-	begin
-		if rising_edge(clk) then
-			if mul_start = '1' or div_start = '1' then
-				pp_op1_r		<= pp_op1;
-				pre_const(0)	<= (others => '0');
-				pre_const(1)	<= (others => '0');
-				pre_cond		:= (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un);
-				s1_r			<= pre_cond(1);
-				s2_r			<= pre_cond(0);
-				sr_r			<= pre_cond(0) xor pre_cond(1);
-				case pre_cond is
-				when "01" =>
-					pre_const(0)	<= din_hi;
-					pre_const(1)	<= X"FFFF_FFFF";
-				when "10" =>	
-					pre_const(0) 	<= X"0000_0000";
-					pre_const(1)	<= X"FFFF_FFFF";
-				when "11" =>	
-					pre_const(0)	<= not din_hi;
-					pre_const(1)	<= X"0000_0001";
-				when others => null;
-				end case;
-			elsif pre_sum_vld = '1' then
-				pre_const(0) <= pre_const(1);
-			end if;
-		end if;
-	end process;	
-	
-proc_mul_sr:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if mul_start = '1' then
-				for i in 0 to 3 loop
-					cy(i) <= '0';
-					pprod(i) <= ppadd_res(i) & X"00";
-				end loop;	
-			elsif mul_en = '1' then
-				for i in 0 to 3 loop
-					cy(i) <= ppadd_cyo(i);
-					pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1);
-				end loop;
-			elsif sum_en = '1' then
-				for i in 1 to 3 loop
-					pprod(i-1) <= pprod(i);
-				end loop;
-			end if;
-		end if;
-	end process;	
-		
-gen_mul32x8pp:
-	for i in 0 to 3 generate
-	begin
-	
-	pp_adder_mux:
-		process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i))
-		variable v2 : unsigned(7 downto 0);
-		begin
-			ppadd_cyi(i) <= '0';
-			ppadd_op1(i) <= (others => '0');
-			if mul_start = '1' then
-				ppadd_op2(i) <= (others => '0');
-				v2	:= pp_op2(8*(i+1)-1 downto 8*i);
-				if v2(0) = '1' then
-					ppadd_cyi(i) <= sign1;
-					ppadd_op1(i) <= pp_op1;
-				end if;
-			else
-				ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9);
-				v2 := pp_op2_r(i);
-				if v2(0) = '1' then
-					ppadd_cyi(i) <= s1_r;
-					ppadd_op1(i) <= pp_op1_r;
-				end if;
-			end if;	
-		end process;	
-
-	pp_adder:
-		process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i))
-		variable sum_pp : unsigned(33 downto 0);
-		begin
-			sum_pp			:= ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i));
-			ppadd_res(i)	<= sum_pp(sum_pp'left-1 downto 1);
-			ppadd_cyo(i)	<= sum_pp(sum_pp'left);
-		end process;	
-
-	proc_mul_ctrl:
-		process(clk)
-		begin
-			if rising_edge(clk) then
-				if mul_start = '1' then
-					pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1);
-				elsif mul_en = '1' then
-					pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1);
-				end if;
-			end if;
-		end process;	
-		
-	end generate;
-	
-comb_mul_adder:
-	process(add_op1, add_op2)
-	variable sum_mul : unsigned(39 downto 0);
-	begin
-		sum_mul		:= (add_op1) + (add_op2);
-		add_res		<= sum_mul(sum_mul'left downto 0);
-	end process;	
-
-comb_mul_adder_mux:
-	process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r)
-	variable s_ext : std_logic;
-	begin
-		if pre_sum_vld = '1' then
-			add_op1 <= pp_reg(63 downto 24);
-			add_op2	<= pre_const(0) & X"00";
-		else
-			s_ext := pp_reg(63) and sr_r;
-			add_op1	<= (7 downto 0 => s_ext) & pp_reg(63 downto 32);
-			add_op2	<= pprod(0);
-		end if;	
-	end process;	
-
-comb_mul:
-	process(clk)
-	variable tmp : prod_t;
-	begin
-		if rising_edge(clk) then
-			if mul_start = '1' then
-				pp_reg	<= (others => '0');
-			elsif pre_sum_vld = '1' then
-				pp_reg	<= add_res & X"0000";
-			elsif sum_en = '1' then
-				tmp		:= add_res & pp_reg(31 downto 8);
-				pp_reg	<= tmp(63 downto 8);
-				result	<= tmp;
-				if sr_r = '1' then
-					result	<= not tmp;
-				end if;
-			elsif div_fin_en(1) = '1' then
-				result(63 downto 32)		<= div_A(31 downto 0);
-				if s1_r = '1' then
-					result(63 downto 32)	<= div_add_res(31 downto 0);
-				end if;	
-			elsif div_fin_en(2) = '1' then
-				result(31 downto 0)		<= div_Q;
-				if sr_r = '1' then
-					result(31 downto 0)	<= div_add_res(31 downto 0);
-				end if;
-			elsif hilo_we = '1' then
-				if hilo_sel = '1' then
-					result(63 downto 32) <= din_hi;
-				else	
-					result(31 downto 0) <= din_hi;
-				end if;
-			end if;
-		end if;
-	end process;	
-
-div_adder:
-	process(div_add_op1, div_add_op2, div_add_cyi)
-	variable sum_div : unsigned(33 downto 0);
-	begin
-		sum_div			:= (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi);
-		div_add_res		<= sum_div(sum_div'left downto 1);
-	end process;	
-
-div_adder_mux:
-	process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n)
-	begin
-	
-		div_add_cyi	<= s2_r xor div_qbit;
-		div_add_op1	<= div_A(31 downto 0) & div_Q(31);
-		div_add_op2	<= (others => '0');
-		if div_start = '1' then
-			div_add_op1	<= '0' & pp_op1;
-			div_add_cyi	<= sign1;
-		elsif div_en = '1' then
-			div_add_op2	<= div_M;
-			if div_qbit = '1' then
-				div_add_op2	<= div_M_n;
-			end if;
-		elsif div_fin_en(0) = '1' then
-			div_add_op2	<= div_M;
-			div_add_cyi	<= s2_r;
-			div_add_op1	<= '0' & div_A(31 downto 0);
-		elsif div_fin_en(1) = '1' then
-			div_add_cyi	<= s1_r;
-			div_add_op1	<= '0' & not div_A(31 downto 0);
-		elsif div_fin_en(2) = '1' then
-			div_add_cyi	<= sr_r;
-			div_add_op1	<= '0' & not div_Q;
-		end if;	
-	end process;	
-
-divide:
-	process(clk)
-	variable quo : std_logic;
-	begin
-		if rising_edge(clk) then
-			if div_start = '1' then
-				div_qbit	<= '1';
-				div_Q		<= div_add_res(31 downto 0);
-				div_A		<= (others => '0');
-				if sign2 = '1' then
-					div_M_n		<= '1' & din_lo;
-					div_M		<= '0' & not din_lo;
-				else
-					div_M_n		<= '1' & not din_lo;
-					div_M		<= '0' & din_lo;
-				end	if;
-			elsif div_en = '1' then
-				div_qbit	<= not div_add_res(32);
-				div_A		<= div_add_res(32 downto 0);
-				div_Q		<= div_Q(30 downto 0) & not div_add_res(32);
-			elsif div_fin_en(0) = '1' then
-				if div_A(32) = '1' then
-					div_A		<= '0' & div_add_res(31 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;	
-
---------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
deleted file mode 100644
index 38dd440..0000000
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ /dev/null
@@ -1,867 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The pipeline
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-
-entity pipeline is
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		imem_err	: in  STD_LOGIC;
-		imem_rdy	: in  STD_LOGIC;
-		imem_en		: out STD_LOGIC;
-		imem_addr	: out word_t;
-		imem_data	: in  word_t;
-		dmem_err	: in  STD_LOGIC;
-		dmem_rdy	: in  STD_LOGIC;
-		dmem_en		: out STD_LOGIC;
-		dmem_we		: out STD_LOGIC;
-		dmem_be		: out unsigned(3 downto 0);
-		dmem_addr	: out word_t;
-		dmem_din	: in  word_t;
-		dmem_dout	: out word_t;
-		cop_ir		: out word_t;
-		cop_ir_en	: out STD_LOGIC;
-		cop_din		: in  word_t;
-		cop_dout	: out word_t;
-		c0_ctrl_out	: out cop0_ctrl_in_t;
-		c0_ctrl_in	: in  cop0_ctrl_out_t
-		
-	);
-end pipeline;
-
-architecture Behavioral of pipeline is
-
---------------------------------------------------------------------------
-	COMPONENT reg_dual is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port 
-	(
-		clk_w		: in  STD_LOGIC;
-		en			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		wptr		: in  unsigned (addr_width-1 downto 0);
-		din			: in  unsigned (data_width-1 downto 0);
-		rptr_a		: in  unsigned (addr_width-1 downto 0);
-		rptr_b		: in  unsigned (addr_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
---------------------------------------------------------------------------
-	COMPONENT shifter is
-	Generic 
-	(
-		data_width : integer
-	);
-	Port 
-	(
-		shift_ctrl	: in  shift_ctrl_t;
-		din			: in  unsigned (data_width-1 downto 0);
-		dout		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-	
---------------------------------------------------------------------------
-	COMPONENT alu is
-	Generic 
-	(
-		data_width : integer
-	);
-	Port 
-	(
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		op2_shifted	: in  unsigned (data_width-1 downto 0);
-		ctrl		: in  alu_ctrl_t;
-		result		: out unsigned (data_width-1 downto 0);
-		flags		: out alu_flags_t
-	);
-	END COMPONENT;
-
---------------------------------------------------------------------------
-	COMPONENT bcu is
-	Generic 
-	(
-		data_width : integer
-	);
-	Port 
-	(
-		op1_in		: in  unsigned (data_width-1 downto 0);
-		op2_in		: in  unsigned (data_width-1 downto 0);
-		flags		: out bcu_flags_t
-	);
-	END COMPONENT;
-	
---------------------------------------------------------------------------
-	COMPONENT muldiv is
-	Port 
-	(
-		rst			: in  std_logic;
-		clk			: in  std_logic;
-		hilo_we		: in  std_logic;
-		din_hi		: in  word_t;
-		din_lo		: in  word_t;
-		mul_divn	: in  std_logic;
-		start		: in  std_logic;
-		s_un		: in  std_logic;
-		hilo_sel	: in  std_logic;
-		busy		: out std_logic;
-		dout		: out word_t
-	);
-	END COMPONENT;
-
---------------------------------------------------------------------------
-	signal ID_stage			: ID_t;
-	signal EX_stage			: EX_t;
-	signal MEM_stage		: MEM_t;
-	signal WB_stage			: WB_t;
-	signal clk_2, clk_1		: STD_LOGIC;
-	signal hdu				: hdu_t;
-	signal sdu				: sdu_t;
-	signal reg_a			: word_t;
-	signal reg_b			: word_t;
-	signal branch_ce		: STD_LOGIC;
-	signal cpu_run			: STD_LOGIC;
-	signal alu_result		: word_t;
-	signal mul_result		: word_t;
-	signal mul_busy			: STD_LOGIC;
-	signal EX_events_instr	: event_t;
-	signal EX_events_alu	: event_t;
-	signal EX_events_mem	: event_t;
-	signal EX_events		: event_t;
-	signal MEM_events		: event_t;
-	signal bcu_op_a			: word_t;
-	signal bcu_op_b			: word_t;
-	signal bcu_flags		: bcu_flags_t;
-	signal vaddr			: word_t;
-	signal dmem_src			: word_t;
-	signal stage_rst		: unsigned(3 downto 0);
-	signal pipe_rst			: STD_LOGIC;
-	
-	signal pc : pc_t;
-	
---------------------------------------------------------------------------
-begin
-	
-	clk_1					<= clk;
-	clk_2					<= not clk;
-	cpu_run					<= ce;
-	
-	-- Stall Detection Unit ---------------------------------------------------
-	sdu.ID_nop				<= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc;
-	sdu.EX_nop				<= sdu.mul_dep or ID_stage.nop or ID_stage.exc;
-	sdu.MEM_nop				<= EX_stage.nop or EX_stage.exc;
-	sdu.WB_nop				<= sdu.dmem_dep or MEM_stage.nop;
-
-	sdu.stall_all			<= sdu.dmem_dep;
-	sdu.ID_stall			<= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit;
-	sdu.EX_stall			<= sdu.stall_all;
-	sdu.MEM_stall			<= sdu.stall_all;
-	sdu.WB_stall			<= '0';
-
-	sdu.mul_dep				<= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy);
-	sdu.imem_dep			<= not imem_rdy;
-	sdu.dmem_dep			<= not dmem_rdy and MEM_stage.ctrl.dmem_en;
-	---------------------------------------------------------------------------
-	imem_en 				<= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit);
-
---------------------------------------------------------------------------
--- Coprocessor assignments
---------------------------------------------------------------------------
-	c0_ctrl_out.bd_wb		<= WB_stage.bd;
-	c0_ctrl_out.epc_mem		<= MEM_stage.pcn;
-	c0_ctrl_out.epc_wb		<= MEM_stage.epc;
-	c0_ctrl_out.imem_addr	<= EX_stage.epc;
-	c0_ctrl_out.dmem_addr	<= MEM_stage.va;
-	c0_ctrl_out.sdu			<= sdu;
-	c0_ctrl_out.events		<= WB_stage.events;
-	c0_ctrl_out.exc_req		<= MEM_stage.exc;
-	c0_ctrl_out.exc_ack		<= WB_stage.exc;
-	cop_ir					<= ID_stage.IR;
-	cop_ir_en				<= ID_stage.ctrl.cop_instr_en;
-	cop_dout				<= dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result;
-
---------------------------------------------------------------------------
--- Muldiv
---------------------------------------------------------------------------
-inst_muldiv: muldiv
-	PORT MAP
-	(
-		rst			=> rst,
-		clk			=> clk,
-		hilo_we		=> EX_stage.ctrl.mul_hilo_we,
-		din_hi		=> EX_stage.reg_a,
-		din_lo		=> EX_stage.reg_b,
-		mul_divn	=> EX_stage.ctrl.mul_mul_divn,
-		start		=> EX_stage.ctrl.mul_start,
-		s_un		=> EX_stage.ctrl.mul_s_un,
-		hilo_sel	=> EX_stage.ctrl.mul_hilo_sel,
-		busy		=> mul_busy,
-		dout		=> mul_result
-	);
-
---------------------------------------------------------------------------
--- IF stage
---------------------------------------------------------------------------
-	imem_addr		<= pc.curr;
-
-	pipe_rst		<= stage_rst(0);
-	
-proc_stage_reset:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if rst = '1' then
-				stage_rst <= (others => '1');
-			else
-				stage_rst <= stage_rst(stage_rst'left-1 downto 0) & '0';
-			end if;	
-		end if;	
-	end process;
-
-proc_stage_pc:
-	process(pc)
-	begin
-		if pc.branch_take = '1' then
-			pc.curr	<= pc.pc_branch after 2 ns;
-		else
-			pc.curr	<= pc.nxt after 2 ns;
-		end if;	
-	end process;
-
-proc_stage_pc_branch:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if sdu.ID_stall = '0' then
-				pc.pc_branch	<= pc.curr + ID_stage.bimm18;
-			end if;	
-		end if;	
-	end process;
-
-proc_stage_branch_ce:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if pipe_rst = '1' then
-				branch_ce	<= '1';
-			else
-				branch_ce	<= c0_ctrl_in.exc_pending;
-				if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then
-					branch_ce	<= '1';
-				end if;
-			end if;
-		end if;	
-	end process;
-
-proc_stage_pc_next:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if c0_ctrl_in.exc_inject = '1' then
-				pc.nxt	<= c0_ctrl_in.exc_vec;
-			elsif sdu.ID_stall = '0' then
-				pc.last	<= pc.curr;
-				if ID_stage.ctrl.jump = '1' then
-					pc.nxt	<= ID_stage.jimm32;
-				elsif ID_stage.ctrl.jump_long = '1' then
-					pc.nxt	<= ID_stage.reg_a;
-				else
-					pc.nxt	<= pc.curr + 4;
-				end if;
-			end if;
-		end if;	
-	end process;
-
-proc_stage_branch:
-	process(clk_2)
-	begin
-		if rising_edge(clk_2) and branch_ce = '1' then
-			pc.branch_take	<= '0';
-			if EX_stage.ctrl.branch = '1' then
-
-				case EX_stage.ctrl.bc_src is
-
-				when bc_eq_ne =>
-					pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq;
-
-				when bc_lez_gtz =>
-					pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz);
-
-				when bc_ltz_gez =>
-					pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz;
-
-				when others => null;
-				end case;
-			end if;	
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
--- ID stage
---------------------------------------------------------------------------
-	ID_stage.IR					<= to_01(imem_data);
-	ID_stage.pcn				<= pc.curr;
-	ID_stage.op					<= decode_op(ID_stage.IR);
-	ID_stage.jimm32				<= extract_jimm32(ID_stage.IR, ID_stage.pcn);
-	ID_stage.bimm18				<= extract_bimm18(ID_stage.IR, ID_stage.pcn);
-	ID_stage.shamt				<= extract_shamt(ID_stage.IR);
-	ID_stage.reg_a_rptr			<= extract_rs(ID_stage.IR);
-	ID_stage.reg_b_rptr			<= extract_rt(ID_stage.IR);
-	ID_stage.ctrl				<= opcode_ctrl_lines(ID_stage.IR) when sdu.ID_nop = '0' else ctrl_lines_default;
-	ID_stage.reg_write			<= ID_stage.ctrl.reg_write;
-	ID_stage.epc				<= pc.last;
-	ID_stage.exc				<= event_is_active(ID_stage.events); -- Todo: works
-	ID_stage.nop				<= sdu.ID_nop;
-	
-proc_ID_except:
-	process(ID_stage, c0_ctrl_in, pc)
-	begin	
-		ID_stage.events					<= events_clr;
-		ID_stage.events.inst_load_err	<= not c0_ctrl_in.exc_pending and (pc.nxt(1) or pc.nxt(0));
-		ID_stage.events.inst_priv_addr	<= not c0_ctrl_in.exc_pending and (pc.nxt(word_t'left) and c0_ctrl_in.user_mode);
-	end process;
-	
-proc_stage_hdu:
-	process(ID_stage, EX_stage, MEM_stage, WB_stage)
-	variable read_a, read_b : boolean;
-	variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean;
-	variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean;
-	variable reg_ptr_a : reg_ptr_t;
-	variable reg_ptr_b : reg_ptr_t;
-	begin
-		
-		reg_ptr_a			:= ID_stage.reg_a_rptr;
-		reg_ptr_b			:= ID_stage.reg_b_rptr;
-		raw_a_EX			:= reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
-		raw_a_MEM			:= reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
-		raw_a_WB			:= reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
-		raw_b_EX			:= reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1';
-		raw_b_MEM			:= reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1';
-		raw_b_WB			:= reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1';
-
-		hdu.alu_fwd_a_ex	<= raw_a_EX after 1 ns;
-		hdu.alu_fwd_a_mem	<= raw_a_MEM after 1 ns;
-		hdu.alu_fwd_a_wb	<= raw_a_WB after 1 ns;
-		hdu.alu_fwd_b_ex	<= raw_b_EX after 1 ns;
-		hdu.alu_fwd_b_mem	<= raw_b_MEM after 1 ns;
-		hdu.alu_fwd_b_wb	<= raw_b_WB after 1 ns;
-
-	end process;
-	
-proc_stage_fwd_a:
-	process(reg_a, hdu, EX_stage, MEM_stage, WB_stage)
-	variable data : word_t;
-	begin
-		data		:= reg_a;
-		if hdu.alu_fwd_a_ex then
-			data	:= EX_stage.result;
-		elsif hdu.alu_fwd_a_mem then
-			data 	:= MEM_stage.data;
-		elsif hdu.alu_fwd_a_wb then
-			data 	:= WB_stage.data;
-		end if;
-		
-		for i in 0 to 31 loop
-			if data(i) = '1' then
-				ID_stage.reg_a(i)	<= '1' after 2 ns;
-			else 
-				ID_stage.reg_a(i)	<= '0' after 2 ns;
-			end if;
-		end loop;
-
-	end process;
-
-proc_stage_fwd_b:
-	process(reg_b, hdu, EX_stage, MEM_stage, WB_stage)
-	variable data : word_t;
-	begin
-		data		:= reg_b;
-		if hdu.alu_fwd_b_ex then
-			data	:= EX_stage.result;
-		elsif hdu.alu_fwd_b_mem then
-			data	:= MEM_stage.data;
-		elsif hdu.alu_fwd_b_wb then
-			data	:= WB_stage.data;
-		end if;
-
-		for i in 0 to 31 loop
-			if data(i) = '1' then
-				ID_stage.reg_b(i)	<= '1' after 2 ns;
-			else 
-				ID_stage.reg_b(i)	<= '0' after 2 ns;
-			end if;
-		end loop;
-
-	end process;
-	
-proc_imm_mux:
-	process(ID_stage)
-	variable data : word_t;
-	begin
-		data := extract_uimm16(ID_stage.IR);
-
-		case ID_stage.ctrl.imm_src is
-
-		when src_imm32 =>
-			data := extract_simm32(ID_stage.IR);
-
-		when src_imm16 =>
-			data := extract_uimm16(ID_stage.IR);
-
-		when src_imm16_high =>
-			data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0');
-			
-		when others => null;
-
-		end case;
-
-		ID_stage.imm <= data after 2 ns;
-
-	end process;
-
---------------------------------------------------------------------------
-inst_reg_dual: reg_dual
-	GENERIC MAP
-	(
-		addr_width	=> reg_ptr_t'length,
-		data_width	=> word_t'length
-	)
-	PORT MAP
-	(
-		clk_w		=> clk_1,
-		we			=> WB_stage.wreg_we,
-		en			=> '1',
-		wptr		=> WB_stage.reg_wptr,
-		din			=> WB_stage.data,
-		rptr_a		=> ID_stage.reg_a_rptr,
-		rptr_b		=> ID_stage.reg_b_rptr,
-		dout_a		=> reg_a,
-		dout_b		=> reg_b
-	);
-
---------------------------------------------------------------------------
--- EX stage
---------------------------------------------------------------------------
-	EX_stage.reg_a_rptr		<= extract_rs(EX_stage.IR);
-	EX_stage.reg_b_rptr		<= extract_rt(EX_stage.IR);
-	EX_stage.result			<= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
-	
-proc_stage_ID_EX_1:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if stage_rst(1) = '1' then
-				EX_stage.op						<= op_nop;
-				EX_stage.IR						<= (others => '0');
-				EX_stage.ctrl					<= ctrl_lines_default;
-				EX_stage.reg_write				<= '0';
-				EX_stage.epc					<= (others => '0');
-				EX_stage.pcn					<= (others => '0');
-				EX_stage.events_in				<= events_clr;
-			elsif sdu.EX_stall = '0' then
-				EX_stage.reg_a			<= ID_stage.reg_a;
-				EX_stage.reg_b			<= ID_stage.reg_b;
-				EX_stage.events_in		<= ID_stage.events;
-				EX_stage.op				<= ID_stage.op;
-				EX_stage.ctrl			<= ID_stage.ctrl;
-				EX_stage.reg_write		<= ID_stage.reg_write;
-				EX_stage.nop			<= sdu.EX_nop;
-				EX_stage.IR				<= ID_stage.IR;
-				EX_stage.pcn			<= ID_stage.pcn;
-				EX_stage.epc			<= ID_stage.epc;
-				if sdu.EX_nop = '1' then
-					EX_stage.op				<= op_nop;
-					EX_stage.IR				<= (others => '0');
-					EX_stage.ctrl			<= ctrl_lines_default;
-					EX_stage.reg_write		<= '0';
-				end if;
-			end if;	
-		end if;
-	end process;
-
-proc_stage_EX_instr_except:
-	process(EX_stage)
-	begin
-		EX_events_instr					<= events_clr;
-		EX_events_instr.illegal			<= EX_stage.ctrl.exc_illegal;
-		EX_events_instr.break			<= EX_stage.ctrl.exc_break;
-		EX_events_instr.syscall			<= EX_stage.ctrl.exc_syscall;
-	end process;
-
-proc_stage_EX_alu_except:
-	process(EX_stage)
-	begin
-		EX_events_alu	<= events_clr;
-		if EX_stage.ctrl.alu_exc_en = '1' then
-			if EX_stage.alu_flags.ovf = '1' then
-				EX_events_alu.alu_ovf	<= '1';
-			end if;	
-			if EX_stage.alu_flags.uvf = '1' then
-				EX_events_alu.alu_uvf	<= '1';
-			end if;	
-		end if;	
-	end process;
-
-	vaddr			<= ID_stage.reg_a + extract_simm32(ID_stage.IR);
-	
-proc_stage_EX_mem_except:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if pipe_rst = '1' then
-				dmem_en		<= '0';
-			elsif sdu.EX_stall = '0' then
-				EX_events_mem	<= events_clr;
-				dmem_en		<= '0';
-				if ID_stage.ctrl.dmem_en = '1' then
-					dmem_en		<= '1';
-					if ID_stage.ctrl.except_en = '1' then
-						if ID_stage.ctrl.word2_en = '1' then
-							if vaddr(0) = '1' then
-								EX_events_mem.data_load_err		<= not ID_stage.ctrl.dmem_we;
-								EX_events_mem.data_store_err	<= ID_stage.ctrl.dmem_we;
-								dmem_en							<= '0';
-							end if;
-						elsif vaddr(1 downto 0) /= "00" then
-							EX_events_mem.data_load_err		<= not ID_stage.ctrl.dmem_we;
-							EX_events_mem.data_store_err	<= ID_stage.ctrl.dmem_we;
-							dmem_en							<= '0';
-						end if;	
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-proc_stage_DMEM_ADDR:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if sdu.EX_stall = '0' then
-				EX_stage.va		<= vaddr;
-				if c0_ctrl_in.EB = '1' then
-					if ID_stage.ctrl.word2_en = '0' then
-						EX_stage.pa_off	<= not vaddr(1 downto 0);
-					else	
-						EX_stage.pa_off	<= not vaddr(1) & vaddr(0);
-					end if;
-				else	
-					EX_stage.pa_off	<= vaddr(1 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;
-	dmem_src	<= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b;
-	dmem_be		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
-	dmem_we		<= EX_stage.ctrl.dmem_we;
-	dmem_dout	<= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
-	dmem_addr	<= EX_stage.va;
-	EX_stage.events			<= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
-	EX_stage.exc			<= event_is_active(EX_stage.events);
-	
---------------------------------------------------------------------------
-proc_wptr_mux:
-	process(EX_stage)
-	variable opclass : opcode_t;
-	variable reg_wptr : reg_ptr_t;
-	begin
-	
-		opclass := extract_opc(EX_stage.IR);
-		case opclass is
-		when "000000" =>
-			reg_wptr					:= extract_rd(EX_stage.IR);
-		when others =>
-			reg_wptr					:= extract_rt(EX_stage.IR);
-		end case;
-		
-		EX_stage.wreg_we <= EX_stage.reg_write after 1 ns;
-		if reg_wptr = "00000" then
-			EX_stage.wreg_we <= '0' after 1 ns;
-		end if;	
-
-		EX_stage.reg_wptr	<= reg_wptr after 1 ns;
-		case EX_stage.ctrl.wptr_srcsel is
-			when wptr_src_imm =>
-				EX_stage.reg_wptr	<= reg_wptr after 1 ns;
-
-			when wptr_src_const =>
-				EX_stage.reg_wptr	<= to_unsigned(31, reg_ptr_t'length) after 1 ns;
-				EX_stage.wreg_we <= '1' after 1 ns;
-
-			when others => null;
-		end case;
-
-	end process;
-
---------------------------------------------------------------------------
-proc_stage_bcu_op:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) and sdu.EX_stall = '0' then
-			bcu_op_a		<= ID_stage.reg_a;
-			bcu_op_b		<= ID_stage.reg_b;
-		end if;
-	end process;
-
-EX_stage.alu_op1 <= EX_stage.reg_a;
-
-alu_op2_mux:
-	process(clk_1)
-	variable data : word_t;
-	begin
-
-		if rising_edge(clk_1) and sdu.EX_stall = '0' then
-			data := ID_stage.reg_b;
-
-			case ID_stage.ctrl.alu.op2_src is
-
-			when alu_src_reg =>
-				data := ID_stage.reg_b;
-
-			when alu_src_imm =>
-				data := ID_stage.imm;
-
-			when others => null;
-
-			end case;
-
-			EX_stage.alu_op2 <= data;
-		end if;
-
-	end process;
-
-shifter_sa_mux:
-	process(clk_1)
-	variable data 		: shamt_t;
-	variable data_inv 	: shamt_t;
-
-	begin
-		if rising_edge(clk_1) and sdu.EX_stall = '0' then
-			data 		:= ID_stage.reg_a(4 downto 0);
-			case ID_stage.ctrl.shamt2_srcsel is
-
-				when sa_src_reg =>
-					data := ID_stage.reg_a(4 downto 0);
-
-				when sa_src_imm =>
-					data := ID_stage.shamt;
-
-				when others => null;
-
-			end case;
-			data_inv := not data + 1;
-			if ID_stage.ctrl.alu.shift_right = '0' then
-				EX_stage.shift_ctrl.shamt_rnd	<= data_inv after 2 ns;
-			else	
-				EX_stage.shift_ctrl.shamt_rnd	<= data after 2 ns;
-			end if;
-			EX_stage.shift_ctrl.shamt_nrm	<= data after 1 ns;
-			EX_stage.shift_ctrl.shift_right	<= ID_stage.ctrl.alu.shift_right;
-			EX_stage.shift_ctrl.shift_arith	<= ID_stage.ctrl.alu.shift_arith;
-		end if;
-		
-	end process;
-
---------------------------------------------------------------------------
-inst_shifter: shifter
-	GENERIC MAP
-	(
-		data_width	=> word_t'length
-	)
-	PORT MAP
-	(
-		shift_ctrl	=> EX_stage.shift_ctrl,
-		din			=> EX_stage.reg_b,
-		dout		=> EX_stage.alu_op2_s
-	);
-
-inst_alu: alu
-	GENERIC MAP
-	(
-		data_width	=> word_t'length
-	)
-	PORT MAP
-	(
-		op1_in			=> EX_stage.alu_op1,
-		op2_in			=> EX_stage.alu_op2,
-		op2_shifted		=> EX_stage.alu_op2_s,
-		ctrl			=> EX_stage.ctrl.alu,
-		result			=> alu_result,
-		flags			=> EX_stage.alu_flags
-	);
-
-inst_bcu: bcu
-	GENERIC MAP
-	(
-		data_width	=> word_t'length
-	)
-	PORT MAP
-	(
-		op1_in		=> bcu_op_a,
-		op2_in		=> bcu_op_b,
-		flags		=> bcu_flags
-	);
-
---------------------------------------------------------------------------
--- MEM stage
---------------------------------------------------------------------------
-proc_stage_MEM_n:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if stage_rst(2) = '1' then
-				MEM_stage.op		<= op_nop;
-				MEM_stage.wreg_we	<= '0';
-				MEM_stage.ctrl		<= ctrl_lines_default;
-				MEM_stage.pa_off	<= (others => '0');
-				MEM_stage.events_in	<= events_clr;
-			elsif sdu.MEM_stall = '0' then
-				MEM_stage.events_in		<= EX_stage.events;
-				MEM_stage.op			<= EX_stage.op;
-				MEM_stage.wreg_we		<= EX_stage.wreg_we;
-				MEM_stage.ctrl			<= EX_stage.ctrl;
-				if EX_stage.ctrl.dmem_en = '1' then
-					MEM_stage.va			<= EX_stage.va;
-				end if;	
-				MEM_stage.pa_off		<= EX_stage.pa_off;
-				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
-				MEM_stage.nop			<= sdu.MEM_nop;
-				if MEM_stage.reg_wptr = EX_stage.reg_wptr then
-					if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
-						MEM_stage.ex_result	<= MEM_stage.data;
-					end if;
-				else
-					MEM_stage.ex_result		<= EX_stage.reg_b;
-				end if;
-				if EX_stage.ctrl.cop_instr_en = '1' then
-					if EX_stage.ctrl.cop_read = '1' then
-						MEM_stage.ex_result	<= cop_din;
-					end if;	
-				elsif EX_stage.ctrl.dmem_en = '0' then
-					MEM_stage.ex_result		<= EX_stage.result;
-				end if;	
-				if sdu.MEM_nop = '1' then
-					MEM_stage.op		<= op_nop;
-					MEM_stage.wreg_we	<= '0';
-					MEM_stage.ctrl		<= ctrl_lines_default;
-				else
-					MEM_stage.pcn			<= EX_stage.pcn;
-					MEM_stage.epc			<= EX_stage.epc;
-				end if;
-			end if;	
-		end if;
-	end process;
-
-proc_stage_MEM_mux:
-	process(MEM_stage, dmem_din)
-	variable temp1 : word_t;
-	variable temp2 : word_t;
-	variable data : word_t;
-	variable be : unsigned(3 downto 0);
-	begin
-		data	:= MEM_stage.ex_result;
-		if MEM_stage.ctrl.reg_link = '1' then
-			data		:= MEM_stage.epc + 8;
-		elsif MEM_stage.ctrl.dmem_en = '1' then
-			temp1		:= load_shift(dmem_din,  MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp);
-			temp2		:= load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en);
-			be			:= load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp);
-			if be(0) = '1' then
-				data(7 downto 0)	:= temp2(7 downto 0);
-			end if;	
-			if be(1) = '1' then
-				data(15 downto 8)	:= temp2(15 downto 8);
-			end if;	
-			if be(2) = '1' then
-				data(23 downto 16)	:= temp2(23 downto 16);
-			end if;	
-			if be(3) = '1' then
-				data(31 downto 24)	:= temp2(31 downto 24);
-			end if;	
-		end if;
-		MEM_stage.data				<= data after 1 ns;
-		
-	end process;
-
-proc_stage_MEM_except:
-	process(MEM_stage, c0_ctrl_in)
-	begin
-		MEM_stage.events				<= MEM_stage.events_in;
-		MEM_stage.events.Int			<= c0_ctrl_in.int;
-		MEM_stage.events.NMI			<= c0_ctrl_in.NMI;
-	end process;
-
-	MEM_stage.exc	<= event_is_active(MEM_stage.events);
-
---------------------------------------------------------------------------
--- WB stage
---------------------------------------------------------------------------
-proc_stage_WB_p:
-	process(clk_1)
-	begin
-		if rising_edge(clk_1) then
-			if stage_rst(3) = '1' then
-				WB_stage.op				<= op_nop;
-				WB_stage.wreg_we		<= '1';
-				WB_stage.reg_wptr		<= (others => '0');
-				WB_stage.data			<= (others => '0');
-				WB_stage.events			<= events_clr;
-			elsif sdu.WB_stall = '0' then
-				WB_stage.op				<= MEM_stage.op;
-				WB_stage.wreg_we		<= MEM_stage.wreg_we;
-				WB_stage.reg_wptr		<= MEM_stage.reg_wptr;
-				WB_stage.data			<= MEM_stage.data;
-				WB_stage.exc			<= '0';
-				if sdu.stall_all = '0' then
-					WB_stage.exc			<= MEM_stage.exc;
-					if MEM_stage.exc = '1' then
-						WB_stage.events			<= MEM_stage.events;
-					end if;	
-				end if;	
-				WB_stage.nop			<= sdu.WB_nop;
-				if sdu.WB_nop = '1' then
-					WB_stage.op				<= op_nop;
-					WB_stage.wreg_we		<= '0';
-				else
-					WB_stage.bd				<= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd
deleted file mode 100644
index e7b72da..0000000
--- a/lib/CPUs/MIPS/src/core/mips_reg.vhd
+++ /dev/null
@@ -1,72 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: On-Chip work registers
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity reg_dual is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_w		: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		en			: in  STD_LOGIC;
-		wptr		: in  unsigned (addr_width-1 downto 0);
-		din			: in  unsigned (data_width-1 downto 0);
-		rptr_a		: in  unsigned (addr_width-1 downto 0);
-		rptr_b		: in  unsigned (addr_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end reg_dual;
-
-architecture Behavioral of reg_dual is
-
-	constant depth : integer := 2**addr_width;
-	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-
-	signal reg_mem : mem_t;
-	
-begin
-
-reg_in:
-	process(clk_w)
-	begin
-		if rising_edge(clk_w) then
-			if we = '1' and en = '1' then
-				reg_mem(to_integer(wptr)) <= din;
-			end if;
-		end if;	
-	end process;
-
-	dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns;
-	dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns;
-
-end Behavioral;
-
diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd
deleted file mode 100644
index 7f047ec..0000000
--- a/lib/CPUs/MIPS/src/core/mips_shifter.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The shifter unit
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.mips_types.all;
-
-entity shifter is
-	Generic 
-	(
-		data_width : integer := 8
-	);
-	Port
-	(
-		shift_ctrl	: in  shift_ctrl_t;
-		din			: in  unsigned (data_width-1 downto 0);
-		dout		: out unsigned (data_width-1 downto 0)
-	);
-end shifter;
-
-architecture Behavioral of shifter is
-
-	subtype word_t is unsigned(data_width-1 downto 0);
-	type word_array_t is array (0 to 5) of word_t;
-
-	signal rot_data			: word_array_t;
-	signal sa_rnd			: unsigned (4 downto 0);
-	signal fill	: std_logic;
-	
-	type fill_mask_rom_t is array (0 to 2*data_width-1) of unsigned(data_width-1 downto 0);
---------------------------------------------------------------------------
-function gen_fill_mask_rom(data_width : natural) return fill_mask_rom_t is
-	variable result : fill_mask_rom_t;
-	begin
-	    result(0) := (data_width-1 downto 0 => '0');
-		for i in 1 to data_width-1 loop
-			result(i) := (data_width-1-i downto 0 => '0') & (i-1 downto 0 => '1');
-		end loop;	
-	    result(data_width) := (data_width-1 downto 0 => '0');
-		for i in 1 to data_width-1 loop
-			result(data_width+i) := (i-1 downto 0 => '1') & (data_width-1-i downto 0 => '0');
-		end loop;	
-	return result;
-	
-end gen_fill_mask_rom;
-
-function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is
-	variable result : unsigned(x'range);
-	constant sa : natural := 2**stage_num;
-	begin
-	if en = '1' then
-		result := x(sa-1 downto 0) & x(x'left downto sa);
-	else
-		result := x;
-	end if;	
-	return result;
-	
-end rot_stage;
-
-	constant fill_mask_rom	: fill_mask_rom_t := gen_fill_mask_rom(data_width);
-	signal fill_mask		: unsigned(data_width-1 downto 0);
-	signal fill_mask_addr	: unsigned(5 downto 0);
-	signal dout_filled		: unsigned (data_width-1 downto 0);
-	
---------------------------------------------------------------------------
-begin
-
-	rot_data(0)		<= din;
-	
-gen_rotate_right:
-	for stage in 0 to 4 generate
-	begin
-		rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage);
-	end generate;
-	
-	sa_rnd			<= shift_ctrl.shamt_rnd;
-	fill			<= shift_ctrl.shift_arith and din(data_width-1);
-	fill_mask_addr	<= shift_ctrl.shift_right & shift_ctrl.shamt_nrm;
-	fill_mask		<= fill_mask_rom(to_integer(fill_mask_addr));
-
-proc_fill_neu:
-	process(fill_mask, fill, rot_data(5))
-	begin
-		if fill = '1' then
-			dout_filled	<= rot_data(5) or fill_mask;
-		else	
-			dout_filled	<= rot_data(5) and not fill_mask;
-		end if;
-	end process;
-	
-	dout	<= dout_filled after 5 ns;
-	
---------------------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd
deleted file mode 100644
index 5c90a86..0000000
--- a/lib/CPUs/MIPS/src/core/mips_top.vhd
+++ /dev/null
@@ -1,308 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: JIPS top file 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-
-entity mips_top is
-	Generic
-	(
-		icache_size	: natural := 8192;	-- words
-		icache_line	: natural := 8;		-- words
-		dcache_size	: natural := 4096;	-- words
-		dcache_line	: natural := 8		-- words
-	);
-	Port
-	(
-		debug		: out unsigned(1 downto 0);
-		eb			: in  STD_LOGIC;
-		nmi			: in  STD_LOGIC;
-		cpu_clk		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		ADDR_O		: out unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		WE_O		: out STD_LOGIC;
-		SEL_O		: out unsigned(3 downto 0);
-		CYC_O		: out STD_LOGIC;
-		STB_O		: out STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		INT			: in  unsigned (5 downto 0)
-	);
-	
-end mips_top;
-
-architecture rtl of mips_top is
-
---------------------------------------------------------------------------
--- Pipeline
---------------------------------------------------------------------------
-	COMPONENT pipeline is
-	Port 
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		imem_err	: in  STD_LOGIC;
-		imem_rdy	: in  STD_LOGIC;
-		imem_en		: out STD_LOGIC;
-		imem_addr	: out word_t;
-		imem_data	: in  word_t;
-		dmem_err	: in  STD_LOGIC;
-		dmem_rdy	: in  STD_LOGIC;
-		dmem_en		: out STD_LOGIC;
-		dmem_we		: out STD_LOGIC;
-		dmem_be		: out unsigned(3 downto 0);
-		dmem_addr	: out word_t;
-		dmem_din	: in  word_t;
-		dmem_dout	: out word_t;
-		cop_ir		: out word_t;
-		cop_ir_en	: out STD_LOGIC;
-		cop_din		: in  word_t;
-		cop_dout	: out word_t;
-		c0_ctrl_out	: out cop0_ctrl_in_t;
-		c0_ctrl_in	: in  cop0_ctrl_out_t
-	);
-	END COMPONENT;
-	signal imem_err			: std_logic;
-	signal imem_rdy			: std_logic;
-	signal imem_en			: std_logic;
-	signal imem_addr		: word_t;
-	signal imem_din			: word_t;
-	signal dmem_err			: std_logic;
-	signal dmem_rdy			: std_logic;
-	signal dmem_en			: std_logic;
-	signal dmem_we			: std_logic;
-	signal dmem_addr		: word_t;
-	signal dmem_dout		: word_t;
-	signal dmem_din			: word_t;
-	signal dmem_be			: unsigned(3 downto 0);
-
-	signal biu_rst			: STD_LOGIC;
-	signal cpu_rst			: STD_LOGIC;
-	signal cpu_run			: STD_LOGIC;
-
-	signal pipe_cop_ir		: word_t;
-	signal pipe_cop_ir_en	: STD_LOGIC;
-	signal pipe_cop_din		: word_t;
-	signal pipe_cop_dout	: word_t;
-	signal pipe_c0_ctrl_out	: cop0_ctrl_in_t;
-	signal pipe_c0_ctrl_in	: cop0_ctrl_out_t;
-	
---------------------------------------------------------------------------
--- Coprocessor
---------------------------------------------------------------------------
-	COMPONENT cop is
-	GENERIC
-	(
-		icache_size	: natural;
-		icache_line	: natural;
-		dcache_size	: natural;
-		dcache_line	: natural
-	);
-	Port 
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		nmi			: in  STD_LOGIC;
-		eb			: in  STD_LOGIC;
-		int			: in  unsigned (5 downto 0);
-		ir_en		: in  STD_LOGIC;
-		ir			: in  word_t;
-		ctrl_in		: in  cop0_ctrl_in_t;
-		ctrl_out	: out cop0_ctrl_out_t;
-		din			: in  word_t;
-		dout		: out word_t
-	);
-	END COMPONENT;
-	
---------------------------------------------------------------------------
--- Bus Interface Unit
---------------------------------------------------------------------------
-	COMPONENT biu
-	GENERIC
-	(
-		icache_size	: natural;
-		icache_line	: natural;
-		dcache_size	: natural;
-		dcache_line	: natural
-	);
-	PORT
-	(
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(3 downto 0);
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		cop0_ctrl_in	: in cop0_ctrl_out_t;
-		cpu_clk			: in  STD_LOGIC;
-		cpu_imem_err	: out STD_LOGIC;
-		cpu_imem_rdy	: out STD_LOGIC;
-		cpu_imem_en		: in  STD_LOGIC;
-		cpu_imem_addr	: in  word_t;
-		cpu_imem_din	: out word_t;
-		cpu_dmem_err	: out STD_LOGIC;
-		cpu_dmem_rdy	: out STD_LOGIC;
-		cpu_dmem_en		: in  STD_LOGIC;
-		cpu_dmem_we		: in  STD_LOGIC;
-		cpu_dmem_be		: in  unsigned(3 downto 0);
-		cpu_dmem_dout	: in  word_t;
-		cpu_dmem_din	: out word_t;
-		cpu_dmem_addr	: in  word_t
-	);
-	END COMPONENT;
-
-begin
-
--------------------------------------------------------------------
-	debug(0)		<= imem_err;
-	debug(1)		<= dmem_err;
-	
-	process(CLK_I)
-	variable reset_delay : unsigned (31 downto 0);
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				reset_delay := (others => '0');
-				biu_rst	<= '1';
-				cpu_rst <= '1';
-				cpu_run	<= '0';
-			else
-				reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1';
-				if reset_delay(20) = '1' then
-					biu_rst <= '0';
-				end if;	
-				if reset_delay(31) = '1' then
-					cpu_rst <= '0';
-				end if;	
-				if reset_delay(16) = '1' then
-					cpu_run	<= '1';
-				end if;	
-			end if;
-		end if;
-	end process;
-
-inst_pipeline: pipeline
-	PORT MAP
-	(
-		rst			=> cpu_rst,
-		clk			=> cpu_clk,
-		ce			=> cpu_run,
-		imem_err	=> imem_err,
-		imem_rdy	=> imem_rdy,
-		imem_en		=> imem_en,
-		imem_addr	=> imem_addr,
-		imem_data	=> imem_din,
-		dmem_err	=> dmem_err,
-		dmem_rdy	=> dmem_rdy,
-		dmem_en		=> dmem_en,
-		dmem_we		=> dmem_we,
-		dmem_be		=> dmem_be,
-		dmem_addr	=> dmem_addr,
-		dmem_din	=> dmem_din,
-		dmem_dout	=> dmem_dout,
-		cop_ir		=> pipe_cop_ir,
-		cop_ir_en	=> pipe_cop_ir_en,
-		cop_din		=> pipe_cop_din,
-		cop_dout	=> pipe_cop_dout,
-		c0_ctrl_out	=> pipe_c0_ctrl_out,
-		c0_ctrl_in	=> pipe_c0_ctrl_in
-	);
-
-inst_cop: cop
-	GENERIC MAP
-	(
-		icache_size	=> icache_size,	-- words
-		icache_line	=> icache_line,	-- words
-		dcache_size	=> dcache_size,	-- words
-		dcache_line	=> dcache_line	-- words
-	)
-	PORT MAP
-	(
-		rst			=> cpu_rst,
-		clk			=> cpu_clk,
-		nmi			=> nmi,
-		eb			=> eb,
-		int			=> INT,
-		ir_en		=> pipe_cop_ir_en,
-		ir			=> pipe_cop_ir,
-		ctrl_in		=> pipe_c0_ctrl_out,
-		ctrl_out	=> pipe_c0_ctrl_in,
-		dout		=> pipe_cop_din,
-		din			=> pipe_cop_dout
-	);
-	
-inst_biu: biu
-	GENERIC MAP
-	(
-		icache_size	=> icache_size,	-- words
-		icache_line	=> icache_line,	-- words
-		dcache_size	=> dcache_size,	-- words
-		dcache_line	=> dcache_line	-- words
-	)
-	PORT MAP
-	(
-		RST_I			=> biu_rst,
-		CLK_I			=> CLK_I,
-		ACK_I			=> ACK_I,
-		SRDY_I			=> SRDY_I,
-		ADDR_O			=> ADDR_O,
-		DAT_I			=> DAT_I,
-		DAT_O			=> DAT_O,
-		WE_O			=> WE_O,
-		SEL_O			=> SEL_O,
-		CYC_O			=> CYC_O,
-		STB_O			=> STB_O,
-		MRDY_O			=> MRDY_O,
-		cop0_ctrl_in	=> pipe_c0_ctrl_in,
-		cpu_clk			=> cpu_clk,
-		cpu_imem_err	=> imem_err,
-		cpu_imem_rdy	=> imem_rdy,
-		cpu_imem_en		=> imem_en,
-		cpu_imem_addr	=> imem_addr,
-		cpu_imem_din	=> imem_din,
-		cpu_dmem_err	=> dmem_err,
-		cpu_dmem_rdy	=> dmem_rdy,
-		cpu_dmem_en		=> dmem_en,
-		cpu_dmem_we		=> dmem_we,
-		cpu_dmem_be		=> dmem_be,
-		cpu_dmem_addr	=> dmem_addr,
-		cpu_dmem_din	=> dmem_din,
-		cpu_dmem_dout	=> dmem_dout
-	);
-
-end rtl;
diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd
deleted file mode 100644
index d861c41..0000000
--- a/lib/CPUs/MIPS/src/core/mips_types.vhd
+++ /dev/null
@@ -1,673 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Types, constants and functions for JIPS
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
---------------------------------------------------------------------------
-package mips_types is
-
-	-- Revision of the CPU
-	constant REVISION : integer := 13;
-	constant WORD_WIDTH : integer := 32;
-	
-	--Types
-	subtype instr_name_t is string(1 to 12);
-	type instr_name_array_t is array (0 to 63) of instr_name_t;
-	subtype opcode_t is unsigned (5 downto 0);
-	subtype word_t is unsigned (WORD_WIDTH-1 downto 0);
-	subtype reg_ptr_t is unsigned (4 downto 0);
-	subtype shamt_t is unsigned(4 downto 0);
-	subtype sa_t is natural range 0 to 63;
-	subtype func_t is unsigned(5 downto 0);
-
-	type chip_debug_t is record	
-		imem_err			: std_logic;
-		dmem_err			: std_logic;
-	end record;
-
-	type op_t is
-	(
-		op_illegal,
-		op_nop,
-		op_sll,
-		op_srl,
-		op_sra,
-		op_sllv,
-		op_srlv,
-		op_srav,
-		op_jr,
-		op_jalr,
-		op_syscall,
-		op_break,
-		op_mfhi,
-		op_mthi,
-		op_mflo,
-		op_mtlo,
-		op_mult,
-		op_multu,
-		op_div,
-		op_divu,
-		op_add,
-		op_addu,
-		op_sub,
-		op_subu,
-		op_and,
-		op_or,
-		op_xor,
-		op_nor,
-		op_slt,
-		op_sltu,
-		op_bltz,
-		op_bgez,
-		op_bltzal,
-		op_bgezal,
-		op_j,
-		op_jal,
-		op_beq,
-		op_bne,
-		op_blez,
-		op_bgtz,
-		op_addi,
-		op_addiu,
-		op_slti,
-		op_sltiu,
-		op_andi,
-		op_ori,
-		op_xori,
-		op_lui,
-		op_lb,
-		op_lh,
-		op_lwl,
-		op_lw,
-		op_lbu,
-		op_lhu,
-		op_lwr,
-		op_sb,
-		op_sh,
-		op_swl,
-		op_sw,
-		op_swr,
-		op_cop0,
-		op_cop1,
-		op_cop2,
-		op_cop3,
-		op_mfc0,
-		op_cfc0,
-		op_mtc0,
-		op_ctc0,
-		op_bcf0,
-		op_bct0,
-		op_mfc1,
-		op_cfc1,
-		op_mtc1,
-		op_ctc1,
-		op_bcf1,
-		op_bct1,
-		op_mfc2,
-		op_cfc2,
-		op_mtc2,
-		op_ctc2,
-		op_bcf2,
-		op_bct2,
-		op_mfc3,
-		op_cfc3,
-		op_mtc3,
-		op_ctc3,
-		op_bcf3,
-		op_bct3,
-		op_lwc0,
-		op_lwc1,
-		op_lwc2,
-		op_lwc3,
-		op_swc0,
-		op_swc1,
-		op_swc2,
-		op_swc3
-	);
-	
-	attribute ENUM_ENCODING : string;
-	
-	type imm_src_t is (src_imm32, src_imm16, src_imm16_high);
-	type sa_src_t is (sa_src_reg, sa_src_imm);
-	type alu_src1_t is (alu_src_reg);
-	type alu_src2_t is (alu_src_reg, alu_src_imm);
-	type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez);
-	type shift_opsel_t is (shift_sll, shift_srl, shift_sra);
-	type wptr_src_t is (wptr_src_imm, wptr_src_const);
-	
-	type pc_t is record	
-		curr			: word_t;
-		last			: word_t;
-		nxt				: word_t;
-		pc_branch		: word_t;
-		branch_take		: std_logic;
-	end record;
-	
-	type alu_outsel_t is
-	(
-		alu_adder,
-		alu_shift2,
-		alu_and,
-		alu_or,
-		alu_xor,
-		alu_nor,
-		alu_ltu,
-		alu_lts
-	);
-
-	type sdu_t is record
-		imem_dep		: STD_LOGIC;
-		dmem_dep		: STD_LOGIC;
-		mul_dep			: STD_LOGIC;
-		ID_nop			: STD_LOGIC;
-		EX_nop			: STD_LOGIC;
-		MEM_nop			: STD_LOGIC;
-		WB_nop			: STD_LOGIC;
-		ID_stall		: STD_LOGIC;
-		EX_stall		: STD_LOGIC;
-		MEM_stall		: STD_LOGIC;
-		WB_stall		: STD_LOGIC;
-		stall_all		: STD_LOGIC;
-	end record;
-
-	type hdu_t is record
-		alu_fwd_a_ex	: boolean;
-		alu_fwd_a_mem	: boolean;
-		alu_fwd_a_wb	: boolean;
-		alu_fwd_b_ex	: boolean;
-		alu_fwd_b_mem	: boolean;
-		alu_fwd_b_wb	: boolean;
-	end record;
-
-	type alu_flags_t is record
-		c				: STD_LOGIC;
-		uvf				: STD_LOGIC;
-		ovf				: STD_LOGIC;
-		ltu				: STD_LOGIC;
-		lts				: STD_LOGIC;
-	end record;
-		
-	type bcu_flags_t is record
-		eq				: STD_LOGIC;
-		ltz				: STD_LOGIC;
-	end record;
-
-	type event_t is record
-		NMI				: STD_LOGIC;
-		Int				: STD_LOGIC;
-		data_load_err	: STD_LOGIC;
-		data_store_err	: STD_LOGIC;
-		inst_load_err	: STD_LOGIC;
-		inst_priv_addr	: STD_LOGIC;
-		alu_ovf			: STD_LOGIC;
-		alu_uvf			: STD_LOGIC;
-		syscall			: STD_LOGIC;
-		break			: STD_LOGIC;
-		illegal			: STD_LOGIC;
-	end record;
-	
-	type exc_flags_t is record
-		Int				: STD_LOGIC;
-		DAdEL			: STD_LOGIC;
-		DAdES			: STD_LOGIC;
-		IAdEL			: STD_LOGIC;
-		IAdEK			: STD_LOGIC;
-		Ov				: STD_LOGIC;
-		Sys				: STD_LOGIC;
-		Bp				: STD_LOGIC;
-		RI				: STD_LOGIC;
-		IBE				: STD_LOGIC;
-		DBE				: STD_LOGIC;
-	end record;
-
-	type except_t is record
-		act				: STD_LOGIC;
-		epc				: word_t;
-		cause			: word_t;
-	end record;
-	
-	type cache_ctrl_t is record
-		inv_addr		: word_t;
-		inv_at			: STD_LOGIC;
-		inv_all			: STD_LOGIC;
-	end record;
-	
-	type cop0_ctrl_in_t is record
-		sdu				: sdu_t;
-		events			: event_t;
-		bd_wb			: STD_LOGIC;
-		epc_mem			: word_t;
-		epc_wb			: word_t;
-		imem_addr		: word_t;
-		dmem_addr		: word_t;
-		exc_req			: STD_LOGIC;
-		exc_ack			: STD_LOGIC;
-	end record;
-
-	type cop0_ctrl_out_t is record
-		EB				: STD_LOGIC;
-		exc_inject		: STD_LOGIC;
-		exc_commit		: STD_LOGIC;
-		exc_pending		: STD_LOGIC;
-		exc_exit		: STD_LOGIC;
-		user_mode		: STD_LOGIC;
-		NMI				: STD_LOGIC;
-		int				: STD_LOGIC;
-		exc_vec			: word_t;
-		icache			: cache_ctrl_t;
-		dcache			: cache_ctrl_t;
-	end record;
-	
-	type alu_ctrl_t is record
-		outsel			: alu_outsel_t;
-		add				: STD_LOGIC;
-		shift_right		: STD_LOGIC;
-		shift_arith		: STD_LOGIC;
-		op1_src			: alu_src1_t;
-		op2_src			: alu_src2_t;
-	end record;
-	
-	type shift_ctrl_t is record
-		shamt_nrm		: shamt_t;
-		shamt_rnd		: shamt_t;
-		shift_right		: STD_LOGIC;
-		shift_arith		: STD_LOGIC;
-	end record;
-
-	type ctrl_lines_t is record
-		branch			: STD_LOGIC;
-		jump_long		: STD_LOGIC;
-		jump			: STD_LOGIC;
-		bc_not			: STD_LOGIC;
-		bc_src			: bc_src_t;
-		imm_src			: imm_src_t;
-		alu				: alu_ctrl_t;
-		reg_write		: STD_LOGIC;
-		reg_link		: STD_LOGIC;
-		dmem_we			: STD_LOGIC;
-		dmem_en			: STD_LOGIC;
-		shamt2_srcsel	: sa_src_t;
-		wptr_srcsel		: wptr_src_t;
-		cop_instr_en	: STD_LOGIC;
-		cop_read		: STD_LOGIC;
-		shift_offset	: unsigned(1 downto 0);
-		shift_byp		: STD_LOGIC;
-		byte_en_byp		: STD_LOGIC;
-		sign_ext_byp	: STD_LOGIC;
-		word4_en		: STD_LOGIC;
-		word2_en		: STD_LOGIC;
-		align_left		: STD_LOGIC;
-		load_signed		: STD_LOGIC;
-		mul_access		: STD_LOGIC;
-		mul_hilo_we		: STD_LOGIC;
-		mul_mul_divn	: STD_LOGIC;
-		mul_start		: STD_LOGIC;
-		mul_s_un		: STD_LOGIC;
-		mul_hilo_sel	: STD_LOGIC;
-		exc_break		: STD_LOGIC;
-		exc_syscall		: STD_LOGIC;
-		exc_illegal		: STD_LOGIC;
-		except_en		: STD_LOGIC;
-		alu_exc_en		: STD_LOGIC;
-	end record;
-
-	type ID_t is record
-		nop			: STD_LOGIC;
-		exc			: std_logic;
-		IR			: word_t;
-		op			: op_t;
-		pcn			: word_t;
-		epc			: word_t;
-		jimm32		: word_t;
-		bimm18		: word_t;
-		imm			: word_t;
-		shamt		: shamt_t;
-		ctrl		: ctrl_lines_t;
-		reg_write	: STD_LOGIC;
-		reg_a_rptr	: reg_ptr_t;
-		reg_b_rptr	: reg_ptr_t;
-		reg_a		: word_t;
-		reg_b		: word_t;
-		events		: event_t;
-	end record;
-	
-	type EX_t is record
-		nop			: STD_LOGIC;
-		exc			: std_logic;
-		IR			: word_t;
-		op			: op_t;
-		pcn			: word_t;
-		epc			: word_t;
-		reg_a		: word_t;
-		reg_b		: word_t;
-		ctrl		: ctrl_lines_t;
-		shift_ctrl	: shift_ctrl_t;
-		alu_op1		: word_t;
-		alu_op2		: word_t;
-		alu_op2_s	: word_t;
-		alu_flags	: alu_flags_t;
-		result		: word_t;
-		reg_write	: STD_LOGIC;
-		wreg_we		: STD_LOGIC;
-		reg_wptr	: reg_ptr_t;
-		reg_a_rptr	: reg_ptr_t;
-		reg_b_rptr	: reg_ptr_t;
-		va			: word_t;
-		pa_off		: unsigned(1 downto 0);
-		events_in	: event_t;
-		events		: event_t;
-	end record;
-	
-	type MEM_t is record
-		nop			: STD_LOGIC;
-		exc			: std_logic;
-		op			: op_t;
-		pcn			: word_t;
-		epc			: word_t;
-		ctrl		: ctrl_lines_t;
-		ex_result	: word_t;
-		reg_wptr	: reg_ptr_t;
-		wreg_we		: STD_LOGIC;
-		data		: word_t;
-		va			: word_t;
-		pa_off		: unsigned(1 downto 0);
-		events_in	: event_t;
-		events		: event_t;
-	end record;
-	
-	type WB_t is record
-		nop			: STD_LOGIC;
-		exc			: std_logic;
-		events		: event_t;
-		op			: op_t;
-		reg_wptr	: reg_ptr_t;
-		wreg_we		: STD_LOGIC;
-		data		: word_t;
-		bd			: STD_LOGIC;
-	end record;
-
-	
-	type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t;
-	type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t;
-	type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t;
-
-	function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t;
-	function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned;
-	function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t;
-	function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned;
-	function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t;
-	function events_clr return event_t;
-	function event_is_active(e : event_t) return std_logic;
-	function "or" (a, b : event_t) return event_t;
-
-	function lg2(x : natural) return natural;
-	function po2(x : natural) return natural;
-
-end mips_types;
-
---------------------------------------------------------------------------
-package body mips_types is
-
-	function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is
-	variable stage1 : word_t;
-	variable result : word_t;
-	variable sa : unsigned(1 downto 0);
-	begin
-		
-		if bypass = '1'	then
-			sa := "00";
-		else
-			sa := va + shift_off;
-		end if;
-		
-		stage1 := x;
-		if sa(0) = '1' then
-			stage1 := x(23 downto 0) & x(31 downto 24);
-		end if;
-		result := stage1;
-		if sa(1) = '1' then
-			result := stage1(15 downto 0) & stage1(31 downto 16);
-		end if;
-		
-		return result;
-	end store_shift;
-	
---------------------------------------------------------------------------
-	function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is
-	variable result : unsigned(3 downto 0);
-	begin
-		result := (3 downto 0 => be_src);
-		if bypass = '0' then
-			if word2_en = '1' then
-				case va is
-					when "00" =>
-						result := "00" & be_src & be_src;
-					when "10" =>
-						result := be_src & be_src & "00";
-					when others => null;
-				end case;
-			elsif word4_en = '1' then
-				case va is
-					when "00" =>
-						result := "000" & be_src;
-					when "01" =>
-						result := "00" & be_src & '0';
-					when "10" =>
-						result := '0' & be_src & "00";
-					when "11" =>
-						result := be_src & "000";
-					when others => null;
-				end case;
-			elsif align_left = '1' then
-				case va is
-					when "00" =>
-						result := be_src & be_src & be_src & be_src;
-					when "01" =>
-						result := be_src & be_src & be_src & '0';
-					when "10" =>
-						result := be_src & be_src & "00";
-					when "11" =>
-						result := be_src & "000";
-					when others => null;
-				end case;
-			else
-				case va is
-					when "00" =>
-						result := "000" & be_src;
-					when "01" =>
-						result := "00" & be_src & be_src;
-					when "10" =>
-						result := '0' & be_src & be_src & be_src;
-					when "11" =>
-						result := be_src & be_src & be_src & be_src;
-					when others => null;
-				end case;
-			end if;
-		end if;
-		
-		return result;
-	
-	end store_be;
-	
---------------------------------------------------------------------------
-	function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is
-	variable stage1 : word_t;
-	variable result : word_t;
-	variable sa : unsigned(1 downto 0);
-	
-	begin
-		if bypass = '1' then
-			sa 		:= "00";
-		else
-			sa		:= va + shift_off;
-		end if;
-		
-		stage1 := x;
-		if sa(0) = '1' then
-			stage1 :=  x(7 downto 0) & x(31 downto 8);
-		end if;
-		result := stage1;
-		if sa(1) = '1' then
-			result := stage1(15 downto 0) & stage1(31 downto 16);
-		end if;
-		
-		return result;
-	end load_shift;
-	
---------------------------------------------------------------------------
-	function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is
-	variable result : unsigned(3 downto 0);
-	begin
-		result := (3 downto 0 => '1');
-		if bypass = '0' then
-			if align_left = '1' then
-				case va is
-					when "00" =>
-						result := "1000";
-					when "01" =>
-						result := "1100";
-					when "10" =>
-						result := "1110";
-					when "11" =>
-						result := "1111";
-					when others => null;
-				end case;
-			else
-				case va is
-					when "00" =>
-						result := "1111";
-					when "01" =>
-						result := "0111";
-					when "10" =>
-						result := "0011";
-					when "11" =>
-						result := "0001";
-					when others => null;
-				end case;
-			end if;
-		end if;
-		
-		return result;
-	
-	end load_be;
-	
---------------------------------------------------------------------------
-	function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is
-	variable result : word_t;
-	variable sign : std_logic;
-	
-	begin
-		if bypass = '1' then
-			result := x;
-		elsif word2_en = '1' then
-			sign	:= signed and x(15);
-			result := (31 downto 16 => sign) & x(15 downto 0);
-		else
-			sign	:= signed and x(7);
-			result := (31 downto 8 => sign) & x(7 downto 0);
-		end if;
-		
-		return result;
-	end load_sign_ext;
-	
---------------------------------------------------------------------------
-	function events_clr return event_t is
-	variable result : event_t;
-	begin
-		result.NMI				:= '0';
-		result.Int				:= '0';
-		result.data_load_err	:= '0';
-		result.data_store_err	:= '0';
-		result.inst_load_err	:= '0';
-		result.inst_priv_addr	:= '0';
-		result.alu_ovf			:= '0';
-		result.alu_uvf			:= '0';
-		result.syscall			:= '0';
-		result.break			:= '0';
-		result.illegal			:= '0';
-		
-		return result;
-		
-	end events_clr;
-
---------------------------------------------------------------------------
-	function event_is_active(e : event_t) return std_logic is
-	variable result : std_logic;
-	begin
-		result := '0';
-		
-		result	:= result or e.NMI;
-		result	:= result or e.Int;
-		result	:= result or e.data_load_err;
-		result	:= result or e.data_store_err;
-		result	:= result or e.inst_load_err;
-		result	:= result or e.inst_priv_addr;
-		result	:= result or e.alu_ovf;
-		result	:= result or e.alu_uvf;
-		result	:= result or e.syscall;
-		result	:= result or e.break;
-		result	:= result or e.illegal;
-
-		return result;
-		
-	end event_is_active;
-
---------------------------------------------------------------------------
-	function "or" (a, b : event_t) return event_t is
-	variable result : event_t;
-	begin
-		result.NMI				:= a.NMI or b.NMI;
-		result.Int				:= a.Int or b.Int;
-		result.data_load_err	:= a.data_load_err or b.data_load_err;
-		result.data_store_err	:= a.data_store_err or b.data_store_err;
-		result.inst_load_err	:= a.inst_load_err or b.inst_load_err;
-		result.inst_priv_addr	:= a.inst_priv_addr or b.inst_priv_addr;
-		result.alu_ovf			:= a.alu_ovf or b.alu_ovf;
-		result.alu_uvf			:= a.alu_uvf or b.alu_uvf;
-		result.syscall			:= a.syscall or b.syscall;
-		result.break			:= a.break or b.break;
-		result.illegal			:= a.illegal or b.illegal;
-		
-		return result;
-		
-	end "or";
-
---------------------------------------------------------------------------
-	function lg2(x : natural) return natural is
-	begin
-		return natural(ceil(log2(real(x))));
-	end lg2;	
-	
---------------------------------------------------------------------------
-	function po2(x : natural) return natural is
-	begin
-
-		return 2**lg2(x);
-	end po2;	
-
---------------------------------------------------------------------------
-end mips_types;
-
diff --git a/lib/CPUs/MIPS/src/mips_sys.vhd b/lib/CPUs/MIPS/src/mips_sys.vhd
deleted file mode 100644
index 76e3bf5..0000000
--- a/lib/CPUs/MIPS/src/mips_sys.vhd
+++ /dev/null
@@ -1,341 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Testbench for JCPU
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-ENTITY mips_sys IS
-	GENERIC 
-	(
-		ICACHE_SIZE			: natural := 512;	-- words
-		DCACHE_SIZE			: natural := 512;	-- words
-		SRAM_ADDR_WIDTH		: integer := 14;
-		FLASH_ADDR_WIDTH	: integer := 14
-	);
-	PORT
-	(
-		eb				: in  std_logic;
-		nmi				: in  std_logic;
-		rst				: in  std_logic;
-		clk				: in  std_logic;
-		flash_cs_n		: out std_logic;
-		flash_oe_n		: out std_logic;
-		flash_we_n		: out std_logic;
-		flash_be_n		: out unsigned(3 downto 0);
-		sram_cs_n		: out std_logic;
-		sram_we_n		: out std_logic;
-		sram_oe_n		: out std_logic;
-		sram_be_n		: out unsigned(3 downto 0);
-		sram_a			: out unsigned(SRAM_ADDR_WIDTH-1 downto 0);
-		sram_d			: inout unsigned(31 downto 0);
-		flash_a			: out unsigned(FLASH_ADDR_WIDTH-1 downto 0);
-		flash_d			: inout unsigned(31 downto 0);
-		
-		gpo0			: out unsigned(31 downto 0);
-		gpo1			: out unsigned(31 downto 0);
-		gpi0			: in  unsigned(31 downto 0);
-		gpi1			: in  unsigned(31 downto 0);
-
-		rx				: in std_logic;
-		tx				: out std_logic;
-
-		debug			: out unsigned(1 downto 0)
-	);
-END mips_sys;
-
-ARCHITECTURE behavior OF mips_sys IS 
-
-	-- Master 
-	signal ACK_I		: STD_LOGIC := '0';
-	signal SRDY_I		: STD_LOGIC := '0';
-	signal ADDR_O		: unsigned(31 downto 0);
-	signal DAT_I		: unsigned(31 downto 0) := (others => '0');
-	signal DAT_O		: unsigned(31 downto 0);
-	signal WE_O			: STD_LOGIC;
-	signal SEL_O		: unsigned(3 downto 0);
-	signal CYC_O		: STD_LOGIC;
-	signal STB_O		: STD_LOGIC;
-	signal MRDY_O		: STD_LOGIC;
-	signal INT			: unsigned (5 downto 0) := (others => '0');
-	
-	-- Slaves
-	signal CYC_I_rom	: std_logic;
-	signal ACK_O_rom	: std_logic;
-	signal SRDY_O_rom	: std_logic;
-	signal DAT_O_rom	: unsigned(31 downto 0);
-
-	signal CYC_I_flash	: std_logic;
-	signal ACK_O_flash	: std_logic;
-	signal SRDY_O_flash	: std_logic;
-	signal DAT_O_flash	: unsigned(31 downto 0);
-
-	signal CYC_I_sram	: std_logic;
-	signal ACK_O_sram	: std_logic;
-	signal SRDY_O_sram	: std_logic;
-	signal DAT_O_sram	: unsigned(31 downto 0);
-
-	signal CYC_I_gpio	: std_logic;
-	signal ACK_O_gpio	: std_logic;
-	signal SRDY_O_gpio	: std_logic;
-	signal DAT_O_gpio	: unsigned(31 downto 0);
-
-	signal CYC_I_uart	: std_logic;
-	signal ACK_O_uart	: std_logic;
-	signal SRDY_O_uart	: std_logic;
-	signal DAT_O_uart	: unsigned(31 downto 0);
-
-	signal int_timer	: std_logic;
-	signal int_uart		: std_logic;
-
-	type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
-	signal mem_area : mem_area_t;
-
-BEGIN
-
-------------------------------------------------------------------
--- Memory mux
-------------------------------------------------------------------
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area	<= mem_dead;
-		if ADDR_O(31 downto 28) = X"0" then
-			mem_area	<= mem_flash;
-		elsif ADDR_O(31 downto 28) = X"A" then
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					mem_area	<= mem_uart;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sram		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart =>
-			CYC_I_uart		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sram =>
-			CYC_I_sram		<= CYC_O;
-		
-		when others => null;
-		
-		end case;
-		
-	end process;
-
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
- 	ACK_I		<=	ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
- 	DAT_I		<=	DAT_O_sram when CYC_I_sram = '1' else
-					DAT_O_rom when CYC_I_rom = '1' else
-					DAT_O_flash when CYC_I_flash = '1' else
-					DAT_O_uart when CYC_I_uart = '1' else
-					DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-
-------------------------------------------------------------------
-inst_mips_top: entity work.mips_top
-	GENERIC MAP
-	(
-		icache_size	=> ICACHE_SIZE,		-- words
-		dcache_size	=> DCACHE_SIZE		-- words
-	)
-	PORT MAP
-	(
-		debug	=> debug,
-		nmi		=> nmi,
-		eb		=> eb,
-		cpu_clk	=> clk,
-		RST_I	=> rst,
-		CLK_I	=> clk,
-		ACK_I	=> ACK_I,
-		SRDY_I	=> SRDY_I,
-		ADDR_O	=> ADDR_O,
-		DAT_I	=> DAT_I,
-		DAT_O	=> DAT_O,
-		WE_O	=> WE_O,
-		SEL_O	=> SEL_O,
-		CYC_O	=> CYC_O,
-		STB_O	=> STB_O,
-		MRDY_O	=> MRDY_O,
-		INT		=> INT
-	);
-	INT(1)	<= int_uart;
-	INT(5)	<= int_timer;
-	
-inst_rom : entity work.rom_wb
-	PORT MAP
-	(
-		CLK_I	=> clk,
-		RST_I	=> rst,
-		CYC_I	=> CYC_I_rom,
-		STB_I	=> STB_O,
-		ACK_O	=> ACK_O_rom,
-		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_O_rom,
-		ADDR_I	=> ADDR_O,
-		DAT_O	=> DAT_O_rom
-	);
-
-inst_gpio : entity work.gpio_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_gpio,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_gpio,
-		SRDY_O		=> SRDY_O_gpio,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_O_gpio,
-		INT_TIM_O	=> int_timer,
-		sys_gpo0	=> gpo0,
-		sys_gpo1	=> gpo1,
-		sys_gpi0	=> gpi0,
-		sys_gpi1	=> gpi1
-	);
-
-inst_flash_port : entity work.async_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> FLASH_ADDR_WIDTH,
-		data_width		=> 32,
-		byte_sel_width	=> 4,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_flash,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_flash,
-		SRDY_O		=> SRDY_O_flash,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_O_flash,
-		page_mode_en	=> '0',
-		async_a		=> flash_a,
-		async_d		=> flash_d,
-		async_cs	=> flash_cs_n,
-		async_wr	=> flash_we_n,
-		async_rd	=> flash_oe_n,
-		async_be	=> flash_be_n,
-		async_rst	=> open
-	);
-
-inst_sram_port : entity work.async_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> SRAM_ADDR_WIDTH,
-		data_width		=> 32,
-		byte_sel_width	=> 4,
-		async_timespec	=> ts_sram
-	)
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_sram,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_sram,
-		SRDY_O		=> SRDY_O_sram,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_O_sram,
-		page_mode_en	=> '0',
-		async_a		=> sram_a,
-		async_d		=> sram_d,
-		async_cs	=> sram_cs_n,
-		async_wr	=> sram_we_n,
-		async_rd	=> sram_oe_n,
-		async_be	=> sram_be_n,
-		async_rst	=> open
-	);
-
-inst_uart : entity work.uart_wb
-	PORT MAP
-	(
-		CLK_I		=> clk,
-		RST_I		=> rst,
-		CYC_I		=> CYC_I_uart,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart,
-		SRDY_O		=> SRDY_O_uart,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_O_uart,
-		INT_O		=> int_uart,
-		ser_rx		=> rx,
-		ser_tx		=> tx
-	);
-	
-END;
diff --git a/lib/CPUs/MIPS/src/mips_top_syn.vhd b/lib/CPUs/MIPS/src/mips_top_syn.vhd
deleted file mode 100644
index c7c99e8..0000000
--- a/lib/CPUs/MIPS/src/mips_top_syn.vhd
+++ /dev/null
@@ -1,100 +0,0 @@
---------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: JIPS top file 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-
-entity mips_top is
-	Generic
-	(
-		icache_size	: natural := 8192;	-- words
-		icache_line	: natural := 8;		-- words
-		dcache_size	: natural := 4096;	-- words
-		dcache_line	: natural := 8		-- words
-	);
-	Port
-	(
-		debug		: out unsigned(1 downto 0);
-		eb			: in  STD_LOGIC;
-		nmi			: in  STD_LOGIC;
-		cpu_clk		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CLK_I		: in  STD_LOGIC;
-		ACK_I		: in  STD_LOGIC;
-		SRDY_I		: in  STD_LOGIC;
-		ADDR_O		: out unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		WE_O		: out STD_LOGIC;
-		SEL_O		: out unsigned(3 downto 0);
-		CYC_O		: out STD_LOGIC;
-		STB_O		: out STD_LOGIC;
-		MRDY_O		: out STD_LOGIC;
-		INT			: in  unsigned (5 downto 0)
-	);
-	
-end mips_top;
-
-architecture rtl of mips_top is
-
-	signal SEL_O_SLV	: STD_LOGIC_VECTOR (3 downto 0);
-	signal DAT_O_SLV	: STD_LOGIC_VECTOR (31 downto 0);
-	signal ADDR_O_SLV	: STD_LOGIC_VECTOR (31 downto 0);
-	signal DEBUG_SLV	: STD_LOGIC_VECTOR (1 downto 0);
-
-begin
-
-	SEL_O	<= unsigned(SEL_O_SLV);
-	DAT_O	<= unsigned(DAT_O_SLV);
-	ADDR_O	<= unsigned(ADDR_O_SLV);
-	DEBUG	<= unsigned(DEBUG_SLV);
-	
-inst_mips_top_syn : entity work.mips_top_syn
-  PORT MAP 
-  (
-    RST_I	=> RST_I, 
-    eb		=> eb, 
-    WE_O	=> WE_O, 
-    CYC_O	=> CYC_O, 
-    cpu_clk	=> cpu_clk, 
-    ACK_I	=> ACK_I, 
-    nmi		=> nmi, 
-    STB_O	=> STB_O, 
-    CLK_I	=> CLK_I, 
-    MRDY_O	=> MRDY_O, 
-    SRDY_I	=> SRDY_I, 
-    debug	=> DEBUG_SLV, 
-    DAT_O	=> DAT_O_SLV, 
-    SEL_O	=> SEL_O_SLV, 
-    ADDR_O	=> ADDR_O_SLV, 
-    DAT_I	=> STD_LOGIC_VECTOR(DAT_I), 
-    INT		=> STD_LOGIC_VECTOR(INT)
-  );
-
-
-
-end rtl;
diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
deleted file mode 100644
index ba364eb..0000000
--- a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd
+++ /dev/null
@@ -1,332 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Testbench for JCPU
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-
-ENTITY tb_mips_muldiv IS
-END tb_mips_muldiv;
-
-ARCHITECTURE behavior OF tb_mips_muldiv IS 
-
-	COMPONENT muldiv is
-	Port 
-	(
-		rst			: in  std_logic;
-		clk			: in  std_logic;
-		hilo_we		: in  std_logic;
-		din_hi		: in  word_t;
-		din_lo		: in  word_t;
-		mul_divn	: in  std_logic;
-		s_un		: in  std_logic;
-		start		: in  std_logic;
-		hilo_sel	: in  std_logic;
-		busy		: out std_logic;
-		dout		: out word_t
-	);
-	END COMPONENT;
-
-	constant CLK_PERIOD : time := 10 ns;
-	signal ENABLE_FAIL_REPORT : boolean := true;
-	signal rst 			: std_logic := '1';
-	signal clk 			: std_logic := '1';
-	signal busy			: std_logic;
-	signal mul_divn		: std_logic := '0';
-	signal s_un			: std_logic := '1';
-	signal hilo_we		: std_logic := '0';
-	signal start		: std_logic := '0';
-	signal din_hi		: word_t := (others => '-');
-	signal din_lo		: word_t := (others => '-');
-	signal dout			: word_t;
-	signal hilo_sel		: std_logic := '0';
-	signal md_result	: unsigned (2*word_t'length-1 downto 0) := (others => '0');
-	signal ref_result	: unsigned (2*word_t'length-1 downto 0);
-	signal ref_hi		: unsigned (word_t'length-1 downto 0);
-	signal rtmp 		: unsigned (2*word_t'length-1 downto 0);
-	signal tmp2 		: unsigned (word_t'length-1 downto 0);
-	signal check		: std_logic;
-	
-	type word_array_t is array (natural range <>) of word_t;
-	
-	constant operands : word_array_t(0 to 63) := 
-	(
-		X"00000000",
-		X"00000001",
-		X"00000010",
-		X"00000100",
-		X"00001000",
-		X"00010000",
-		X"00100000",
-		X"01000000",
-		X"10000000",
-		X"0000000F",
-		X"000000FF",
-		X"00000FFF",
-		X"0000FFFF",
-		X"000FFFFF",
-		X"00FFFFFF",
-		X"0FFFFFFF",
-		X"12345678",
-		X"23456789",
-		X"7FFFFFFF",
-		X"80000000",
-		X"A541B3B9",
-		X"80000001",
-		X"80000010",
-		X"80000100",
-		X"80001000",
-		X"80010000",
-		X"80100000",
-		X"81000000",
-		X"87654321",
-		X"98765432",
-		X"FFFFFFFF",
-		X"FFFFFFFE",
-		X"FFFFFFFD",
-		X"FFFFFFFB",
-		X"FFFFFFF7",
-		X"FFFFFFEF",
-		X"FFFFFFDF",
-		X"FFFFFFBF",
-		X"FFFFFF7F",
-		X"FFFFFEFF",
-		X"FFFFFDFF",
-		X"FFFFFBFF",
-		X"FFFFF7FF",
-		X"FFFFEFFF",
-		X"FFFFDFFF",
-		X"FFFFBFFF",
-		X"FFFF7FFF",
-		X"FFFEFFFF",
-		X"FFFDFFFF",
-		X"FFFBFFFF",
-		X"FFF7FFFF",
-		X"FFEFFFFF",
-		X"FFDFFFFF",
-		X"FFBFFFFF",
-		X"FF7FFFFF",
-		X"FEFFFFFF",
-		X"FDFFFFFF",
-		X"FBFFFFFF",
-		X"F7FFFFFF",
-		X"EFFFFFFF",
-		X"DFFFFFFF",
-		X"BFFFFFFF",
-		X"CFFFFFFF",
-		X"7FFFFFFF"
-	);
-	
-BEGIN
-
-uut: muldiv
-	PORT MAP(
-		rst				=> rst,
-		clk				=> clk,
-		hilo_we			=> hilo_we,
-		din_hi			=> din_hi,
-		din_lo			=> din_lo,
-		mul_divn		=> mul_divn,
-		s_un			=> s_un,
-		start			=> start,
-		hilo_sel		=> hilo_sel,
-		busy			=> busy,
-		dout			=> dout
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-REF_GEN: process
-	begin
-		if mul_divn = '0' then
-			wait until rising_edge(clk) and check = '1';
-			if s_un = '1' then
-				rtmp		<= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
-				wait until rising_edge(clk);
-				tmp2 		<= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
-				wait until rising_edge(clk);
-				ref_hi		<= tmp2(31 downto 0);
-			else
-				rtmp		<= md_result(31 downto 0) * din_lo;
-				wait until rising_edge(clk);
-				tmp2 		<= rtmp(31 downto 0) + md_result(63 downto 32);
-				wait until rising_edge(clk);
-				ref_hi		<= tmp2(31 downto 0);
-			end if;	
-			wait until rising_edge(clk);
-				
-			if din_lo /= X"00000000" then
-				if ENABLE_FAIL_REPORT  then
-					assert din_hi = ref_hi report "Error on divison" severity failure;
-				end if;	
-			end if;	
-		else
-			wait until rising_edge(clk) and check = '1';
-			if s_un = '1' then
-				ref_result <= unsigned(signed(din_hi) * signed(din_lo));
-			else
-				ref_result <= unsigned(din_hi) * unsigned(din_lo);
-			end if;	
-			wait until rising_edge(clk);
-			wait until rising_edge(clk);
-			wait until rising_edge(clk);
-			if ENABLE_FAIL_REPORT then
-				assert ref_result = md_result report "Error on multiplication" severity failure;
-			end if;	
-		end if;
-		
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(clk);
-		rst <= '0';
-		wait for 2*CLK_PERIOD;
-	
-		mul_divn	<= '0';
-		s_un		<= '0';
-		for i in 0 to operands'length-1 loop
-			for j in 0 to operands'length-1 loop
-				check	<= '0';
-				wait until rising_edge(clk) and busy = '0';
-				din_hi		<= operands(i);
-				din_lo		<= operands(j);
-				start		<= '1';
-				wait until rising_edge(clk);
-				start		<= '0';
-				hilo_sel	<= '0';
-
-				-- Read result
-				wait until rising_edge(clk) and busy = '0';
-				wait until rising_edge(clk);
-				md_result(31 downto 0) <= dout;
-				wait until rising_edge(clk);
-				hilo_sel	<= '1';
-				wait until rising_edge(clk);
-				md_result(63 downto 32) <= dout;
-				check	<= '1';
-				wait until rising_edge(clk);
-				check	<= '0';
- 				wait for 8*CLK_PERIOD;
-			end loop;
-		end loop;
-
-		s_un	<= '1';
-		for i in 0 to operands'length-1 loop
-			for j in 0 to operands'length-1 loop
-				check	<= '0';
-				wait until rising_edge(clk) and busy = '0';
-				din_hi		<= operands(i);
-				din_lo		<= operands(j);
-				start		<= '1';
-				wait until rising_edge(clk);
-				start		<= '0';
-				hilo_sel	<= '0';
-
-				-- Read result
-				wait until rising_edge(clk) and busy = '0';
-				wait until rising_edge(clk);
-				md_result(31 downto 0) <= dout;
-				wait until rising_edge(clk);
-				hilo_sel	<= '1';
-				wait until rising_edge(clk);
-				md_result(63 downto 32) <= dout;
-				check	<= '1';
-				wait until rising_edge(clk);
-				check	<= '0';
- 				wait for 8*CLK_PERIOD;
-			end loop;
-		end loop;
-	
-		mul_divn	<= '1';
-		s_un		<= '0';
-		for i in 0 to operands'length-1 loop
-			for j in 0 to operands'length-1 loop
-				check	<= '0';
-				wait until rising_edge(clk) and busy = '0';
-				din_hi		<= operands(i);
-				din_lo		<= operands(j);
-				start		<= '1';
-				wait until rising_edge(clk);
-				start		<= '0';
-				hilo_sel	<= '0';
-
-				-- Read result
-				wait until rising_edge(clk) and busy = '0';
-				wait until rising_edge(clk);
-				md_result(31 downto 0) <= dout;
-				wait until rising_edge(clk);
-				hilo_sel	<= '1';
-				wait until rising_edge(clk);
-				md_result(63 downto 32) <= dout;
-				check	<= '1';
-				wait until rising_edge(clk);
-				check	<= '0';
- 				wait for 8*CLK_PERIOD;
-			end loop;
-		end loop;
-
-		s_un	<= '1';
-		for i in 0 to operands'length-1 loop
-			for j in 0 to operands'length-1 loop
-				check	<= '0';
-				wait until rising_edge(clk) and busy = '0';
-				din_hi		<= operands(i);
-				din_lo		<= operands(j);
-				start		<= '1';
-				wait until rising_edge(clk);
-				start		<= '0';
-				hilo_sel	<= '0';
-
-				-- Read result
-				wait until rising_edge(clk) and busy = '0';
-				wait until rising_edge(clk);
-				md_result(31 downto 0) <= dout;
-				wait until rising_edge(clk);
-				hilo_sel	<= '1';
-				wait until rising_edge(clk);
-				md_result(63 downto 32) <= dout;
-				check	<= '1';
-				wait until rising_edge(clk);
-				check	<= '0';
- 				wait for 8*CLK_PERIOD;
-			end loop;
-		end loop;
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_sys.vhd b/lib/CPUs/MIPS/src/tb_mips_sys.vhd
deleted file mode 100644
index 88479ae..0000000
--- a/lib/CPUs/MIPS/src/tb_mips_sys.vhd
+++ /dev/null
@@ -1,233 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Testbench for JCPU
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-ENTITY tb_mips_sys IS
-END tb_mips_sys;
-
-ARCHITECTURE behavior OF tb_mips_sys IS 
-
-	constant CLK_PERIOD 			: time := 10 ns;
-	constant ICACHE_SIZE			: natural := 512;	-- words
-	constant DCACHE_SIZE			: natural := 512;	-- words
-	constant SRAM_ADDR_WIDTH		: integer := 17;	-- bits
-	constant FLASH_ADDR_WIDTH		: integer := 17;	-- bits
-	
-	signal debug				: unsigned(1 downto 0);
-
-	-- Master 
-	signal nmi					: STD_LOGIC := '0';
-	signal rst					: STD_LOGIC := '1';
-	signal clk					: STD_LOGIC := '0';
-	signal eb					: STD_LOGIC := '1';
-
-	signal flash_cs_n			: std_logic;
-	signal flash_we_n			: std_logic;
-	signal flash_oe_n			: std_logic;
-	signal flash_be_n			: unsigned(3 downto 0);
-	signal sram_cs_n			: std_logic;
-	signal sram_be_n			: unsigned(3 downto 0);
-	signal sram_wr_n			: std_logic;
-	signal sram_oe_n			: std_logic;
-	signal sram_a				: unsigned(SRAM_ADDR_WIDTH-1 downto 0);
-	signal sram_d				: unsigned(31 downto 0);
-	signal flash_a				: unsigned(FLASH_ADDR_WIDTH-1 downto 0);
-	signal flash_d				: unsigned(31 downto 0);
-	
-	signal gpo0					: unsigned(31 downto 0);
-	signal gpo1					: unsigned(31 downto 0);
-	signal gpi0					: unsigned(31 downto 0) := (others => '0');
-	signal gpi1					: unsigned(31 downto 0) := (others => '0');
-
-	signal int_timer			: std_logic;
-	signal int_uart				: std_logic;
-	signal rx					: std_logic := '1';
-	signal tx					: std_logic;
-
-	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
-	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
-	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
-	
-BEGIN
-
-------------------------------------------------------------------
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------
-uut : entity work.mips_sys
-	GENERIC MAP 
-	(
-		ICACHE_SIZE			=> ICACHE_SIZE,	-- words
-		DCACHE_SIZE			=> DCACHE_SIZE,	-- words
-		SRAM_ADDR_WIDTH		=> SRAM_ADDR_WIDTH,
-		FLASH_ADDR_WIDTH	=> FLASH_ADDR_WIDTH
-	)
-	PORT MAP
-	(
-		eb			=> eb,
-		nmi			=> nmi,
-		rst			=> rst,
-		clk			=> clk,
-		flash_cs_n	=> flash_cs_n,
-		flash_oe_n	=> flash_oe_n,
-		flash_we_n	=> flash_we_n,
-		flash_be_n	=> flash_be_n,
-		sram_cs_n	=> sram_cs_n,
-		sram_we_n	=> sram_wr_n,
-		sram_oe_n	=> sram_oe_n,
-		sram_be_n	=> sram_be_n,
-		sram_a		=> sram_a,
-		sram_d		=> sram_d,
-		flash_a		=> flash_a,
-		flash_d		=> flash_d,
-		
-		gpo0		=> gpo0,
-		gpo1		=> gpo1,
-		gpi0		=> gpi0,
-		gpi1		=> gpi1,
-
-		rx			=> rx,
-		tx			=> tx,
-
-		debug		=> debug
-	);
-
-------------------------------------------------------------------
-SRAM_READ:
-	process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
-	begin
-		sram_d	<= (others => 'Z') after 10 ns;
-		if sram_oe_n = '0' then
-			if sram_cs_n = '0' then
-				if sram_be_n(0) = '0' then
-					sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
-				end if;	
-				if sram_be_n(1) = '0' then
-					sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
-				end if;	
-				if sram_be_n(2) = '0' then
-					sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
-				end if;	
-				if sram_be_n(3) = '0' then
-					sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
-				end if;	
-			end if;				
-		end if;	
-	end process;
-
-SRAM_WRITE:
-	process(sram_wr_n)
-	begin
-		if rising_edge(sram_wr_n) then
-			if sram_cs_n = '0' then
-				if sram_be_n(0) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
-				end if;		
-				if sram_be_n(1) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
-				end if;				
-				if sram_be_n(2) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
-				end if;				
-				if sram_be_n(3) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
-				end if;				
-			end if;	
-		end if;	
-	end process;
-
-------------------------------------------------------------------
-FLASH_READ:
-	process(rst, flash_cs_n, flash_oe_n, flash_a)
-	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "hello.flash.bin";
-	variable instr : integer;
-	variable index : natural;
-	variable temp : signed(31 downto 0);
-	constant tpd : time := 25 ns;
-	begin
-		if rst = '1' then
-			index := 0;
-			while not endfile(load_flash) loop
-				read(load_flash, instr);
-				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
-				index := index + 1;
-			end loop;
-		else
-	 		flash_d <= (others => 'Z') after tpd;
-			index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
-			if flash_oe_n = '0' then
-				if flash_cs_n = '0' then
-					if flash_be_n(0) = '0' then
-						flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
-					end if;	
-					if flash_be_n(1) = '0' then
-						flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
-					end if;	
-					if flash_be_n(2) = '0' then
-						flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
-					end if;	
-					if flash_be_n(3) = '0' then
-						flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
-					end if;	
-				end if;				
-			end if;	
-		end if;	
-	end process;
-
-------------------------------------------------------------------
-STIMULUS: process
-
-	begin
-
-
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(clk);
-		rst <= '0';
-		wait for 778254*CLK_PERIOD;
-		wait until rising_edge(clk);
-		nmi <= '0';
-		wait for 3000*CLK_PERIOD;
-		wait until rising_edge(clk);
-		nmi <= '0';
-
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
deleted file mode 100644
index c044a61..0000000
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ /dev/null
@@ -1,460 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: Testbench for JCPU
---            also writes 'opc.lst' for JASM-assembler
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library work;
-use work.mips_types.all;
-use work.mips_instr.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-ENTITY tb_mips_top IS
-END tb_mips_top;
-
-ARCHITECTURE behavior OF tb_mips_top IS 
-
-	constant SYS_FREQ	 			: real := 100.0;
-	constant CLK_PERIOD 			: time := 10 ns;
-	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
-	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
-	
-	signal debug				: chip_debug_t;
-
-	-- Master 
-	signal nmi					: STD_LOGIC := '0';
-	signal rst					: STD_LOGIC := '1';
-	signal clk					: STD_LOGIC := '0';
-	signal eb					: STD_LOGIC := '1';
-	signal ACK_I				: STD_LOGIC := '0';
-	signal SRDY_I				: STD_LOGIC := '0';
-	signal ADDR_O				: unsigned(31 downto 0);
-	signal DAT_I				: unsigned(31 downto 0) := (others => '0');
-	signal DAT_O				: unsigned(31 downto 0);
-	signal WE_O					: STD_LOGIC;
-	signal SEL_O				: unsigned(3 downto 0);
-	signal CYC_O				: STD_LOGIC;
-	signal STB_O				: STD_LOGIC;
-	signal MRDY_O				: STD_LOGIC;
-	signal INT					: unsigned (5 downto 0) := (others => '0');
-	
-	-- Slaves
-	signal CYC_I_rom			: std_logic;
-	signal ACK_O_rom			: std_logic;
-	signal SRDY_O_rom			: std_logic;
-	signal DAT_O_rom			: unsigned(31 downto 0);
-
-	signal CYC_I_flash			: std_logic;
-	signal ACK_O_flash			: std_logic;
-	signal SRDY_O_flash			: std_logic;
-	signal DAT_O_flash			: unsigned(31 downto 0);
-
-	signal CYC_I_sram			: std_logic;
-	signal ACK_O_sram			: std_logic;
-	signal SRDY_O_sram			: std_logic;
-	signal DAT_O_sram			: unsigned(31 downto 0);
-
-	signal CYC_I_gpio			: std_logic;
-	signal ACK_O_gpio			: std_logic;
-	signal SRDY_O_gpio			: std_logic;
-	signal DAT_O_gpio			: unsigned(31 downto 0);
-
-	signal CYC_I_uart			: std_logic;
-	signal ACK_O_uart			: std_logic;
-	signal SRDY_O_uart			: std_logic;
-	signal DAT_O_uart			: unsigned(31 downto 0);
-
-	signal flash_cs_n			: std_logic;
-	signal flash_we_n			: std_logic;
-	signal flash_oe_n			: std_logic;
-	signal flash_be_n			: unsigned(3 downto 0);
-	signal sram_cs_n			: std_logic;
-	signal sram_be_n			: unsigned(3 downto 0);
-	signal sram_wr_n			: std_logic;
-	signal sram_oe_n			: std_logic;
-	signal sram_a				: unsigned(SRAM_ADDR_WIDTH-1 downto 0);
-	signal sram_d				: unsigned(31 downto 0);
-	signal flash_a				: unsigned(FLASH_ADDR_WIDTH-1 downto 0);
-	signal flash_d				: unsigned(31 downto 0);
-	signal flash_page_mode_en	: std_logic;
-	
-	signal gpi_0				: unsigned(31 downto 0);
-	signal gpo_0				: unsigned(31 downto 0);
-
-	signal int_timer			: std_logic;
-	signal int_uart				: std_logic;
-	signal rx					: std_logic := '1';
-	signal tx					: std_logic;
-
-	type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
-	signal mem_area : mem_area_t;
-
-	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
-	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
-	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
-	
-BEGIN
-
-------------------------------------------------------------------
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------
--- Memory mux
-------------------------------------------------------------------
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area			<= mem_dead;
-		flash_page_mode_en	<= '0';
-		if ADDR_O(31 downto 28) = X"0" then
-			mem_area			<= mem_flash;
-			flash_page_mode_en	<= '1';
-		elsif ADDR_O(31 downto 28) = X"A" then
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					mem_area	<= mem_uart;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sram		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart =>
-			CYC_I_uart		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sram =>
-			CYC_I_sram		<= CYC_O;
-		
-		when others => null;
-		
-		end case;
-		
-	end process;
-
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio;
- 	ACK_I		<=	ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio;
- 	DAT_I		<=	DAT_O_sram when CYC_I_sram = '1' else
-					DAT_O_rom when CYC_I_rom = '1' else
-					DAT_O_flash when CYC_I_flash = '1' else
-					DAT_O_uart when CYC_I_uart = '1' else
-					DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-
-------------------------------------------------------------------
-uut: entity work.mips_top
-	GENERIC MAP
-	(
-		icache_size		=> 1024,	-- words
-		dcache_size		=> 1024		-- words
-	)
-	PORT MAP
-	(
-		debug			=> debug,
-		eb				=> eb,
-		cpu_clk			=> clk,
-		RST_I			=> rst,
-		CLK_I			=> clk,
-		ACK_I			=> ACK_I,
-		SRDY_I			=> SRDY_I,
-		ADDR_O			=> ADDR_O,
-		DAT_I			=> DAT_I,
-		DAT_O			=> DAT_O,
-		WE_O			=> WE_O,
-		SEL_O			=> SEL_O,
-		CYC_O			=> CYC_O,
-		STB_O			=> STB_O,
-		MRDY_O			=> MRDY_O,
-		INT				=> INT,
-		nmi				=> nmi
-	);
-	INT(1)	<= int_uart;
-	INT(5)	<= int_timer;
-	
-inst_rom : entity work.rom_wb
-	PORT MAP
-	(
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_rom,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_rom,
-		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_O_rom,
-		ADDR_I			=> ADDR_O,
-		DAT_O			=> DAT_O_rom
-	);
-
-inst_gpio : entity work.gpio_wb
-	PORT MAP
-	(
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_gpio,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_gpio,
-		SRDY_O			=> SRDY_O_gpio,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_O_gpio,
-		INT_TIM_O		=> int_timer,
-
-		sys_gpi_0		=> gpi_0,
-		sys_gpo_0		=> gpo_0
-	);
-
-inst_flash_port : entity work.async_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> SYS_FREQ,
-		addr_width		=> FLASH_ADDR_WIDTH,
-		data_width		=> 32,
-		byte_sel_width	=> 4,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_flash,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_flash,
-		SRDY_O			=> SRDY_O_flash,
-		MRDY_I			=> MRDY_O,
-		SEL_I			=> SEL_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_O_flash,
-		page_mode_en	=> flash_page_mode_en,
-		async_a			=> flash_a,
-		async_d			=> flash_d,
-		async_cs		=> flash_cs_n,
-		async_wr		=> flash_we_n,
-		async_rd		=> flash_oe_n,
-		async_be		=> flash_be_n,
-		async_rst		=> open
-	);
-
-inst_sram_port : entity work.async_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> SYS_FREQ,
-		addr_width		=> SRAM_ADDR_WIDTH,
-		data_width		=> 32,
-		byte_sel_width	=> 4,
-		async_timespec	=> ts_sram
-	)
-	PORT MAP
-	(
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_sram,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_sram,
-		SRDY_O			=> SRDY_O_sram,
-		MRDY_I			=> MRDY_O,
-		SEL_I			=> SEL_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_O_sram,
-		page_mode_en	=> '0',
-		async_a			=> sram_a,
-		async_d			=> sram_d,
-		async_cs		=> sram_cs_n,
-		async_wr		=> sram_wr_n,
-		async_rd		=> sram_oe_n,
-		async_be		=> sram_be_n,
-		async_rst		=> open
-	);
-
-inst_uart : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
-	PORT MAP
-	(
-		CLK_I			=> clk,
-		RST_I			=> rst,
-		CYC_I			=> CYC_I_uart,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_uart,
-		SRDY_O			=> SRDY_O_uart,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_O_uart,
-		INT_O			=> int_uart,
-		ser_rx			=> rx,
-		ser_tx			=> tx
-	);
-
-------------------------------------------------------------------
-SRAM_READ:
-	process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
-	begin
-		sram_d	<= (others => 'Z') after 10 ns;
-		if sram_oe_n = '0' then
-			if sram_cs_n = '0' then
-				if sram_be_n(0) = '0' then
-					sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
-				end if;	
-				if sram_be_n(1) = '0' then
-					sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
-				end if;	
-				if sram_be_n(2) = '0' then
-					sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
-				end if;	
-				if sram_be_n(3) = '0' then
-					sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
-				end if;	
-			end if;				
-		end if;	
-	end process;
-
-SRAM_WRITE:
-	process(sram_wr_n)
-	begin
-		if rising_edge(sram_wr_n) then
-			if sram_cs_n = '0' then
-				if sram_be_n(0) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
-				end if;		
-				if sram_be_n(1) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
-				end if;				
-				if sram_be_n(2) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
-				end if;				
-				if sram_be_n(3) = '0' then
-					sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
-				end if;				
-			end if;	
-		end if;	
-	end process;
-
-------------------------------------------------------------------
-FLASH_READ:
-	process(rst, flash_cs_n, flash_oe_n, flash_a)
-	type file_t is file of integer;
---	file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-	file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
---	file load_flash : file_t open read_mode is "test_dcache.flash.bin";
-	variable instr : integer;
-	variable index : natural;
-	variable temp : signed(31 downto 0);
-	constant tpd : time := 25 ns;
-	begin
-		if rst = '1' then
-			index := 0;
-			while not endfile(load_flash) loop
-				read(load_flash, instr);
-				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
-				index := index + 1;
-			end loop;
-		else
-	 		flash_d <= (others => 'Z') after tpd;
-			index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
-			if flash_oe_n = '0' then
-				if flash_cs_n = '0' then
-					if flash_be_n(0) = '0' then
-						flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd;
-					end if;	
-					if flash_be_n(1) = '0' then
-						flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd;
-					end if;	
-					if flash_be_n(2) = '0' then
-						flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd;
-					end if;	
-					if flash_be_n(3) = '0' then
-						flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd;
-					end if;	
-				end if;				
-			end if;	
-		end if;	
-	end process;
-
-------------------------------------------------------------------
-STIMULUS: process
-
-	begin
-
-		gpi_0	<= X"00000000";
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(clk);
-		rst <= '0';
-		wait for 778254*CLK_PERIOD;
-		wait until rising_edge(clk);
-		nmi <= '0';
-		wait for 3000*CLK_PERIOD;
-		wait until rising_edge(clk);
-		nmi <= '0';
-
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf b/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf
deleted file mode 100644
index 1c877f4..0000000
--- a/lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf
+++ /dev/null
@@ -1,13 +0,0 @@
-# Bus clock nets
-NET "CLK_I" TNM_NET = "sys_clk";
-TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
-
-NET "cpu_clk" TNM_NET = "cpu_clk";
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
-
-BEGIN MODEL biu
-	INST inst_bin_fifo ram_style = distributed;
-	INST inst_bout_fifo ram_style = distributed;
-	INST inst_write_fifo ram_style = distributed;
-END;
-
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj
deleted file mode 100644
index ea45b69..0000000
--- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj
+++ /dev/null
@@ -1,21 +0,0 @@
-vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../../FIFO/src/gray_counter.vhd"
-vhdl work "../../../../misc/dpram_2w2r.vhd"
-vhdl work "../../../../misc/dpram_1w1r.vhd"
-vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd"
-vhdl work "../../../../FIFO/src/fifo_async_ctrl.vhd"
-vhdl work "../../src/core/mips_types.vhd"
-vhdl work "../../../../FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../FIFO/src/fifo_async.vhd"
-vhdl work "../../src/core/mips_shifter.vhd"
-vhdl work "../../src/core/mips_reg.vhd"
-vhdl work "../../src/core/mips_muldiv.vhd"
-vhdl work "../../src/core/mips_instr.vhd"
-vhdl work "../../src/core/mips_icache.vhd"
-vhdl work "../../src/core/mips_dcache.vhd"
-vhdl work "../../src/core/mips_bcu.vhd"
-vhdl work "../../src/core/mips_alu.vhd"
-vhdl work "../../src/core/mips_pipeline.vhd"
-vhdl work "../../src/core/mips_cop.vhd"
-vhdl work "../../src/core/mips_biu.vhd"
-vhdl work "../../src/core/mips_top.vhd"
diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
deleted file mode 100644
index 7676319..0000000
--- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj
+++ /dev/null
@@ -1,21 +0,0 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
diff --git a/lib/CPUs/MIPS/todo.txt b/lib/CPUs/MIPS/todo.txt
deleted file mode 100644
index 551e1a0..0000000
--- a/lib/CPUs/MIPS/todo.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-2008-10-26
-- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen
-- Area-Optimierung: MUL32x32 primitive für Virtex-4
-- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27)
-- External COP 1..3 interface
-- FPU (COP1)
-- MMU
-
-2008-10-27
-- Area vs. speed : Pipeline-stall statt forwarding
-- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit)
-          - 1,2,4-way assoziative
-          - 2nd-Level cache in System
-          - Write-back policy
-
-2008-11-15
-- Bus exceptions IBE DBE (BUI/Cache restart notwendig)
-
-2009-03-18
-- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths
-
-2009-8-8
-- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done)
-- CP_COND
-
-2009-10-17
-- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert. 
-  TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren
-
-- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird.
-  Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde).
-  Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer).
-
-2010-01-09
-- COP dependency einführen => Pipeline stall, wenn COP Daten nicht verfügbar
diff --git a/lib/CPUs/MIPS/tools/Makefile b/lib/CPUs/MIPS/tools/Makefile
deleted file mode 100644
index 852df6b..0000000
--- a/lib/CPUs/MIPS/tools/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-CFLAGS=-O2
-CC=gcc
-PREFIX=/usr/local
-all: romgen ramgen flashgen
-
-romgen: ./src/romgen.c
-	$(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen
-
-ramgen: ./src/ramgen.c
-	$(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen
-
-flashgen: ./src/flashgen.c
-	$(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen
-
-install:
-	cp romgen $(PREFIX)/bin
-	cp ramgen $(PREFIX)/bin
-	cp flashgen $(PREFIX)/bin
-clean:
-	rm -rf romgen* ramgen* flashgen*
diff --git a/lib/CPUs/MIPS/tools/flashgen.exe b/lib/CPUs/MIPS/tools/flashgen.exe
deleted file mode 100644
index da4a7c1..0000000
Binary files a/lib/CPUs/MIPS/tools/flashgen.exe and /dev/null differ
diff --git a/lib/CPUs/MIPS/tools/flashgen_big.exe b/lib/CPUs/MIPS/tools/flashgen_big.exe
deleted file mode 100644
index 6837b3d..0000000
Binary files a/lib/CPUs/MIPS/tools/flashgen_big.exe and /dev/null differ
diff --git a/lib/CPUs/MIPS/tools/flashgen_little.exe b/lib/CPUs/MIPS/tools/flashgen_little.exe
deleted file mode 100644
index 8d55c83..0000000
Binary files a/lib/CPUs/MIPS/tools/flashgen_little.exe and /dev/null differ
diff --git a/lib/CPUs/MIPS/tools/ramgen.exe b/lib/CPUs/MIPS/tools/ramgen.exe
deleted file mode 100644
index 9fe3751..0000000
Binary files a/lib/CPUs/MIPS/tools/ramgen.exe and /dev/null differ
diff --git a/lib/CPUs/MIPS/tools/romgen.exe b/lib/CPUs/MIPS/tools/romgen.exe
deleted file mode 100644
index 5cddd1f..0000000
Binary files a/lib/CPUs/MIPS/tools/romgen.exe and /dev/null differ
diff --git a/lib/CPUs/MIPS/tools/src/flashgen.c b/lib/CPUs/MIPS/tools/src/flashgen.c
deleted file mode 100644
index a6b5470..0000000
--- a/lib/CPUs/MIPS/tools/src/flashgen.c
+++ /dev/null
@@ -1,140 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define SDRAM_BASE			0x40000000
-#define	FLASH_OFFSET		0x00000000
-
-#define	MAGIC_EB	0x4A464931	// "JFI1" in big-endian;
-#define	MAGIC_EL	0x3149464A	// "JFI1" in little-endian;
-
-UINT32 conv_endian32(UINT32 src)
-{
-	UINT32 dst;
-
-	dst = (0xFF000000 & (src << 24))
-		| (0x00FF0000 & (src << 8))
-		| (0x0000FF00 & (src >> 8))
-		| (0x000000FF & (src >> 24));
-
-	return dst;
-};
-
-// --------------------------------------------------------------
-typedef struct _sflash_img_hdr_t
-{
-	UINT32 magic;
-	UINT32 target_addr;
-	UINT32 img_offset;
-	UINT32 img_size;
-	UINT32 hdr_next;
-	UINT8 img_name[128];
-	UINT8 res[108];
-
-} flash_img_hdr_t;
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-// --------------------------------------------------------------
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_flash[1024];
-	char name_prj[1024];
-	char *pBuf;
-	UINT32 *pBuf32;
-	flash_img_hdr_t img_hdr = {0};
-
-	FILE *pFile;
-	int filesize;
-	long start, end;
-	int i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: flashgen <input file> [-{EL|EB}]\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	pFile = fopen(pFilenameIn, "rb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_flash, "%s.flash.bin", name_prj);
-
-	// determine filesize
-	fseek(pFile, 0, SEEK_SET);
-	start = ftell(pFile);
-	fseek(pFile, 0, SEEK_END);
-	end = ftell(pFile);
-	fseek(pFile, 0, SEEK_SET);
-	filesize = (end-start);
-
-	pBuf = (char*)malloc(filesize);
-	fread(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	pFile = fopen(name_flash, "wb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", name_flash);
-		return 1;
-	}
-
-	img_hdr.magic = MAGIC_EL;
-	img_hdr.target_addr = SDRAM_BASE;
-	img_hdr.img_size = filesize;
-	img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
-	img_hdr.hdr_next = FLASH_OFFSET;
-
-	if (argc == 3)
-	{
-		if ((argv[2][0] == '-') && (toupper(argv[2][1]) == 'E') && (toupper(argv[2][2]) == 'B'))
-		{
-			img_hdr.magic = MAGIC_EB;
-			pBuf32 = (UINT32*)pBuf;
-			for (i=0; i < filesize/4; i ++)
-				pBuf32[i] = conv_endian32(pBuf32[i]);
-		}
-	}
-	fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
-	fwrite(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c
deleted file mode 100644
index 8f61118..0000000
--- a/lib/CPUs/MIPS/tools/src/ramgen.c
+++ /dev/null
@@ -1,385 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"ram"
-#define JTAG_ADDR_WIDTH		16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 2\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom_tcl[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	if (argc == 3)
-		nbits_addr = atoi(argv[2]);
-
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-
diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c
deleted file mode 100644
index f674a6a..0000000
--- a/lib/CPUs/MIPS/tools/src/romgen.c
+++ /dev/null
@@ -1,428 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"rom"
-#define JTAG_ADDR_WIDTH		16
-
-UINT32 g_endianess_EB;
-
-// --------------------------------------------------------------
-UINT32 conv_endian32(UINT32 src)
-{
-	UINT32 dst;
-
-	dst = (0xFF000000 & (src << 24))
-		| (0x00FF0000 & (src << 8))
-		| (0x0000FF00 & (src >> 8))
-		| (0x000000FF & (src >> 24));
-
-	return dst;
-};
-
-UINT32 to_big_endian32(UINT32 src)
-{
-#ifndef NATIVE_IS_BIG_ENDIAN
-	return conv_endian32(src);
-#else
-	return src;
-#endif
-}
-
-UINT32 from_big_endian32(UINT32 src)
-{
-#ifndef NATIVE_IS_BIG_ENDIAN
-	return conv_endian32(src);
-#else
-	return src;
-#endif
-}
-
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		if (g_endianess_EB)
-			fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
-		else
-			fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		if (g_endianess_EB)
-			fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word));
-		else
-			fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] =
-	{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 1\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		if (g_endianess_EB)
-			fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word));
-		else
-			fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-	char name_rom_tcl[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: romgen <input file> <num. word address bits> [-{EL|EB}]\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	nbits_addr = atoi(argv[2]);
-
-	g_endianess_EB = 0;
-	if (argc == 4)
-	{
-		if ((argv[3][0] == '-') && (toupper(argv[3][1]) == 'E') && (toupper(argv[3][2]) == 'B'))
-			g_endianess_EB = 1;
-	}
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-
diff --git a/lib/FIFO/sim/tb_fifo_async.fdo b/lib/FIFO/sim/tb_fifo_async.fdo
deleted file mode 100644
index c164ab6..0000000
--- a/lib/FIFO/sim/tb_fifo_async.fdo
+++ /dev/null
@@ -1,16 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../src/gray_counter.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../src/fifo_async.vhd"
-vcom -explicit  -93 "../src/tb_fifo_async.vhd"
-vsim -t 1ps   -lib work tb_fifo_async
-view wave
-do {tb_fifo_async.wdo}
-view structure
-view signals
-
-run 5us
diff --git a/lib/FIFO/sim/tb_fifo_async.wdo b/lib/FIFO/sim/tb_fifo_async.wdo
deleted file mode 100644
index 4b40ab1..0000000
--- a/lib/FIFO/sim/tb_fifo_async.wdo
+++ /dev/null
@@ -1,39 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fifo_async/rst
-add wave -noupdate -format Logic /tb_fifo_async/clk_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/din
-add wave -noupdate -format Logic /tb_fifo_async/fifo_full
-add wave -noupdate -format Logic /tb_fifo_async/we
-add wave -noupdate -format Logic /tb_fifo_async/write_en
-add wave -noupdate -format Logic /tb_fifo_async/clk_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/dout
-add wave -noupdate -format Logic /tb_fifo_async/fifo_empty
-add wave -noupdate -format Logic /tb_fifo_async/re
-add wave -noupdate -format Logic /tb_fifo_async/read_en
-add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_full
-add wave -noupdate -format Logic /tb_fifo_async/fifo_almost_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_async/ref_r
-add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/empty
-add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/full
-add wave -noupdate -format Logic /tb_fifo_async/uut/pre_full
-add wave -noupdate -format Logic /tb_fifo_async/uut/pre_empty
-add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_w
-add wave -noupdate -format Literal /tb_fifo_async/uut/ptr_r
-add wave -noupdate -format Logic /tb_fifo_async/uut/inst_fifo_async_ctrl/rinc
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {155864 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {112771 ps} {210880 ps}
diff --git a/lib/FIFO/sim/tb_fifo_sync.fdo b/lib/FIFO/sim/tb_fifo_sync.fdo
deleted file mode 100644
index 6922e87..0000000
--- a/lib/FIFO/sim/tb_fifo_sync.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/tb_fifo_sync.vhd"
-vsim -t 1ps   -lib work tb_fifo_sync
-view wave
-do {tb_fifo_sync.wdo}
-view structure
-view signals
-
-run 5us
diff --git a/lib/FIFO/sim/tb_fifo_sync.wdo b/lib/FIFO/sim/tb_fifo_sync.wdo
deleted file mode 100644
index 6888c72..0000000
--- a/lib/FIFO/sim/tb_fifo_sync.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fifo_sync/rst
-add wave -noupdate -format Logic /tb_fifo_sync/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/din
-add wave -noupdate -format Logic /tb_fifo_sync/fifo_full
-add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_full
-add wave -noupdate -format Logic /tb_fifo_sync/we
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/dout
-add wave -noupdate -format Logic /tb_fifo_sync/fifo_empty
-add wave -noupdate -format Logic /tb_fifo_sync/fifo_almost_empty
-add wave -noupdate -format Logic /tb_fifo_sync/re
-add wave -noupdate -format Logic /tb_fifo_sync/write_en
-add wave -noupdate -format Logic /tb_fifo_sync/read_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_fifo_sync/ref_r
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1360023 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {4760828 ps} {5012588 ps}
diff --git a/lib/FIFO/sim/tb_gray_counter.fdo b/lib/FIFO/sim/tb_gray_counter.fdo
deleted file mode 100644
index b619f71..0000000
--- a/lib/FIFO/sim/tb_gray_counter.fdo
+++ /dev/null
@@ -1,13 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-vcom -explicit  -93 "../src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../src/gray_counter.vhd"
-vcom -explicit  -93 "../src/tb_gray_counter.vhd"
-vsim -t 1ps   -lib work tb_gray_counter
-view wave
-do {tb_gray_counter.wdo}
-view structure
-view signals
-
-run 1us
diff --git a/lib/FIFO/sim/tb_gray_counter.wdo b/lib/FIFO/sim/tb_gray_counter.wdo
deleted file mode 100644
index dd0c3c2..0000000
--- a/lib/FIFO/sim/tb_gray_counter.wdo
+++ /dev/null
@@ -1,29 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_gray_counter/rst
-add wave -noupdate -format Logic /tb_gray_counter/ce
-add wave -noupdate -format Logic /tb_gray_counter/clk
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Literal /tb_gray_counter/bcnt
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Literal /tb_gray_counter/bnxt
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Literal /tb_gray_counter/gcnt
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Literal /tb_gray_counter/gnxt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {61919 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {915144 ps} {1004467 ps}
diff --git a/lib/FIFO/src/.directory_history b/lib/FIFO/src/.directory_history
deleted file mode 100644
index d1192e2..0000000
--- a/lib/FIFO/src/.directory_history
+++ /dev/null
@@ -1,8 +0,0 @@
-VHDL/lib/FIFO/src/async_fifo_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_async_ctrl.vhd
-
-VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
-
-VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd
-VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd
diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd
deleted file mode 100644
index 17733b6..0000000
--- a/lib/FIFO/src/async_fifo_ctrl.vhd
+++ /dev/null
@@ -1,248 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-LIBRARY WORK;
-USE WORK.FIFO_CTRL_PKG.ALL;
-
-entity fifo_async_ctrl is
-	Generic 
-	(
-		addr_width : integer := 3;
-		almost_full_thresh : integer := 6;
-		almost_empty_thresh : integer := 2
-	);
-	Port
-	(
-		rst					: in  STD_LOGIC;
-		clk_w				: in  STD_LOGIC;
-		clk_r				: in  STD_LOGIC;
-		winc				: in  STD_LOGIC;
-		rinc				: in  STD_LOGIC;
-		ptr_w				: out unsigned (addr_width-1 downto 0);
-		ptr_r				: out unsigned (addr_width-1 downto 0);
-		fifo_pre_full		: out STD_LOGIC;
-		fifo_pre_empty		: out STD_LOGIC;
-		fifo_full			: out STD_LOGIC;
-		fifo_empty			: out STD_LOGIC;
-		fifo_afull			: out STD_LOGIC;
-		fifo_aempty			: out STD_LOGIC
-	);
-end fifo_async_ctrl;
-
-architecture Behavioral of fifo_async_ctrl is
-
-	signal gcnt_w		: unsigned (addr_width downto 0);
-	signal gcnt2_w		: unsigned (addr_width downto 0);
-	signal bcnt2_aw		: unsigned (addr_width downto 0);
-	signal bcnt_w		: unsigned (addr_width downto 0);
-	signal gnxt_w		: unsigned (addr_width downto 0);
-	signal bnxt_w		: unsigned (addr_width downto 0);
-	signal gcnt_r		: unsigned (addr_width downto 0);
-	signal gcnt2_r		: unsigned (addr_width downto 0);
-	signal bcnt2_ar		: unsigned (addr_width downto 0);
-	signal bcnt_r		: unsigned (addr_width downto 0);
-	signal gnxt_r		: unsigned (addr_width downto 0);
-	signal bnxt_r		: unsigned (addr_width downto 0);
-
-	signal pre_empty, pre_full : std_logic;
-	signal full, empty : std_logic;
-
-	-- synthesis translate_off
-	signal diffw		: signed (addr_width downto 0);
-	signal diffr		: signed (addr_width downto 0);
-	-- synthesis translate_on
-
-begin
-
-	ptr_w			<= bcnt_w(addr_width-1 downto 0);
-	ptr_r			<= bnxt_r(addr_width-1 downto 0);
-	fifo_full		<= full;
-	fifo_empty		<= empty;
-	fifo_pre_full	<= pre_full;
-	fifo_pre_empty	<= pre_empty;
-	
-proc_write_inhibit:
-	process(rst, clk_w)
-	begin
-		if rst = '1' then
-			full	<= '0';
-		elsif rising_edge(clk_w) then
-			full	<= pre_full;
-		end if;
-	end process;
-	
-proc_read_inhibit:
-	process(rst, clk_r)
-	begin
-		if rst = '1' then
-			empty	<= '1';
-		elsif rising_edge(clk_r) then
-			empty	<= pre_empty;
-		end if;
-	end process;
-
-proc_sync_grptr:
-	process(clk_w)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_w) then
-			gcnt2_r <= p2;
-			p2 := p1;
-			p1 := gcnt_r;
-		end if;
-	end process;
-
-proc_ptr_gwptr:
-	process(clk_r)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_r) then
-			gcnt2_w <= p2;
-			p2 := p1;
-			p1 := gcnt_w;
-		end if;
-	end process;
-	
-proc_status_full:
-	process(gnxt_w, gcnt2_r)
-	begin
-		if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then
-			pre_full <= '1';
-		else
-			pre_full <= '0';
-		end if;
-	end process;
-
-proc_status_empty:
-	process(gnxt_r, gcnt2_w)
-	begin
-		if (gnxt_r = gcnt2_w) then
-			pre_empty <= '1';
-		else
-			pre_empty <= '0';
-		end if;
-	end process;
-	
-proc_sync_arptr:
-	process(clk_w)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_w) then
-			bcnt2_ar <= p2;
-			p2 := p1;
-			p1 := bcnt_r;
-		end if;
-	end process;
-
-proc_ptr_awptr:
-	process(clk_r)
-	variable p1, p2	: unsigned (addr_width downto 0);
-	begin
-		if rising_edge(clk_r) then
-			bcnt2_aw <= p2;
-			p2 := p1;
-			p1 := bcnt_w;
-		end if;
-	end process;
-	
-proc_status_almost_full:
-	process(rst, clk_w)
-	variable diff : unsigned (addr_width downto 0);
-	begin
-	-- synthesis translate_off
-		diffw <= signed(diff);
-	-- synthesis translate_on
-		if rst = '1' then
-			fifo_afull <= '0';
-			diff := (others => '0');
-		elsif rising_edge(clk_w) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar)));
-		end if;
-	end process;
-
-proc_status_almost_empty:
-	process(rst, clk_r)
-	variable diff : unsigned (addr_width downto 0);
-	begin
-	-- synthesis translate_off
-		diffr <= signed(diff);
-	-- synthesis translate_on
-		if rst = '1' then
-			fifo_aempty <= '1';
-			diff := (others => '0');
-		elsif rising_edge(clk_r) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
-			diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r)));
-		end if;
-	end process;
-
-inst_gray_counter_w : entity work.gray_counter
-	generic map
-	(
-		width => addr_width+1,
-		init_value => 0
-		)
-	port map
-	(
-		rst			=> rst,
-		clk			=> clk_w,
-		ce			=> winc, 
-		bcnt		=> bcnt_w,
-		bnxt		=> bnxt_w,
-		gcnt		=> gcnt_w,
-		gnxt		=> gnxt_w
-	);
-
-inst_gray_counter_r : entity work.gray_counter
-	generic map
-	(
-		width => addr_width+1,
-		init_value => 0
-		)
-	port map
-	(
-		rst			=> rst,
-		clk			=> clk_r,
-		ce			=> rinc, 
-		bcnt		=> bcnt_r,
-		bnxt		=> bnxt_r,
-		gcnt		=> gcnt_r,
-		gnxt		=> gnxt_r
-	);
-
-end Behavioral;
-
diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd
deleted file mode 100644
index 35340e7..0000000
--- a/lib/FIFO/src/fifo_async.vhd
+++ /dev/null
@@ -1,124 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_async is
-	Generic
-	(
-		addr_width					: natural := 4;
-		data_width					: natural := 8;
-		almost_full_thresh			: integer := 12;
-		almost_empty_thresh			: integer := 4;
-		allow_full_writes			: boolean := false;
-		allow_empty_reads			: boolean := false;
-		do_last_read_update			: boolean := true
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk_w		: in  STD_LOGIC;
-		clk_r		: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_async;
-
-architecture Behavioral of fifo_async is
-	
-	signal mem_wr_en	: STD_LOGIC;
-	signal mem_rd_en	: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: std_logic;
-	signal empty		: std_logic;
-	signal pre_full		: STD_LOGIC;
-	signal pre_empty	: STD_LOGIC;
-	signal rinc			: std_logic;
-	
-begin
-
-	fifo_full	<= full;
-	fifo_empty	<= empty;
-	
-	mem_wr_en	<= (we and not full) when allow_full_writes = false else we;
-	rinc		<= (re and not empty) when allow_empty_reads = false else re;
-	mem_rd_en	<= not pre_empty when do_last_read_update = false else '1';
-	
-	
-	inst_fifo_async_ctrl: entity work.fifo_async_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=>	rst,
-		clk_w			=>	clk_w,
-		clk_r			=>	clk_r,
-		winc			=>	mem_wr_en,
-		rinc			=>	rinc,
-		ptr_w			=>	ptr_w,
-		ptr_r			=>	ptr_r,
-		fifo_full		=>	full,
-		fifo_empty		=>	empty,
-		fifo_pre_full	=>	pre_full,
-		fifo_pre_empty	=>	pre_empty,
-		fifo_afull		=>	fifo_afull,
-		fifo_aempty		=>	fifo_aempty
-
-	);
-
-inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
-	GENERIC MAP
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clk_a		=> clk_w,
-		clk_b		=> clk_r,
-		en_a		=> '1',
-		en_b		=> mem_rd_en,
-		we_a		=> mem_wr_en,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-
-end Behavioral;
-
diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd
deleted file mode 100644
index 7404fc2..0000000
--- a/lib/FIFO/src/fifo_ctrl_pkg.vhd
+++ /dev/null
@@ -1,67 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package fifo_ctrl_pkg is
-
-	-- Constants
-	-- Types
-	
-	-- Functions
-	function bin2gray(xb : unsigned) return unsigned;
-	function gray2bin(xg : unsigned) return unsigned;
-
-end fifo_ctrl_pkg;
-
-package body fifo_ctrl_pkg is
-
-	function bin2gray(xb : unsigned) return unsigned is
-	variable xg : unsigned(xb'left downto xb'right);
-	begin
-	
-    	xg(xg'left) := xb(xb'left);
-		for i in 1 to xb'left loop
-			xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i);
-		end loop;
-	
-		return xg;
-	end bin2gray;
-	
-	function gray2bin(xg : unsigned) return unsigned is
-	variable xb : unsigned(xg'left downto xg'right);
-	begin
-
-     	xb(xb'left) := xg(xg'left);
-		for i in 1 to xg'left loop
-			xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i);
-		end loop;
-		
-		return xb;
-	end gray2bin;
-
-end fifo_ctrl_pkg;
-
diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd
deleted file mode 100644
index 5c8d8c8..0000000
--- a/lib/FIFO/src/fifo_sync.vhd
+++ /dev/null
@@ -1,123 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_sync is
-	Generic 
-	(
-		addr_width					: natural := 4;
-		data_width					: natural := 8;
-		almost_full_thresh			: integer := 12;
-		almost_empty_thresh			: integer := 4;
-		allow_full_writes			: boolean := false;
-		allow_empty_reads			: boolean := false;
-		do_last_read_update			: boolean := true
-		
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_sync;
-
-architecture Behavioral of fifo_sync is
-	
-	signal mem_wr_en	: STD_LOGIC;
-	signal mem_rd_en	: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: STD_LOGIC;
-	signal empty		: std_logic;
-	signal pre_full		: STD_LOGIC;
-	signal pre_empty	: STD_LOGIC;
-	signal rinc			: std_logic;
-	
-begin
-
-	fifo_full	<= full;
-	fifo_empty	<= empty;
-
-	mem_wr_en	<= (we and not full) when allow_full_writes = false else we;
-	rinc		<= (re and not empty) when allow_empty_reads = false else re;
-	mem_rd_en	<= not pre_empty when do_last_read_update = false else '1';
-
-
-inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=>	rst,
-		clk				=>	clk,
-		winc			=>	mem_wr_en,
-		rinc			=>	rinc,
-		ptr_w			=>	ptr_w,
-		ptr_r			=>	ptr_r,
-		fifo_full		=>	full,
-		fifo_empty		=>	empty,
-		fifo_pre_full	=>	pre_full,
-		fifo_pre_empty	=>	pre_empty,
-		fifo_afull		=>	fifo_afull,
-		fifo_aempty		=>	fifo_aempty
-
-	);
-
-inst_dpram_1w1r2c: entity work.dpram_1w1r2c_ro
-	GENERIC MAP
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clk_a		=> clk,
-		clk_b		=> clk,
-		en_a		=> '1',
-		en_b		=> mem_rd_en,
-		we_a		=> mem_wr_en,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-
-end Behavioral;
-
diff --git a/lib/FIFO/src/fifo_sync_dist.vhd b/lib/FIFO/src/fifo_sync_dist.vhd
deleted file mode 100644
index beb89f5..0000000
--- a/lib/FIFO/src/fifo_sync_dist.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_sync_dist is
-	Generic (
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_sync_dist;
-
-architecture Behavioral of fifo_sync_dist is
-	
-	signal mem_wr_en	: STD_LOGIC;
-	signal mem_rd_en	: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: STD_LOGIC;
-	signal empty		: STD_LOGIC;
-	signal almost_full	: STD_LOGIC;
-	signal almost_empty	: STD_LOGIC;
-	signal pre_full		: STD_LOGIC;
-	signal pre_empty	: STD_LOGIC;
-	
-begin
-
-	mem_wr_en	<= not full;
-	mem_rd_en	<= not pre_empty;
-	fifo_full	<= full;
-	fifo_empty	<= empty;
-	fifo_afull	<= almost_full;
-	fifo_aempty	<= almost_empty;
-
-	inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=>	rst,
-		clk				=>	clk,
-		we				=>	we,
-		re				=>	re,
-		ptr_w			=>	ptr_w,
-		ptr_r			=>	ptr_r,
-		fifo_full		=>	full,
-		fifo_empty		=>	empty,
-		fifo_pre_full	=>	pre_full,
-		fifo_pre_empty	=>	pre_empty,
-		fifo_afull		=>	almost_full,
-		fifo_aempty		=>	almost_empty
-
-	);
-
-	inst_dpram_1w1r: entity work.dpram_1w1r_dist
-	GENERIC MAP (
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
-		en_a		=> mem_wr_en,
-		en_b		=> mem_rd_en,
-		we_a		=> we,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-	
-end Behavioral;
-
diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd
deleted file mode 100644
index 990f15b..0000000
--- a/lib/FIFO/src/gray_counter.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-LIBRARY WORK;
-USE WORK.FIFO_CTRL_PKG.ALL;
-
-entity gray_counter is
-	Generic (
-		width : natural := 3;
-		init_value : natural := 0
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		bcnt		: out unsigned (width-1 downto 0);
-		bnxt		: out unsigned (width-1 downto 0);
-		gcnt		: out unsigned (width-1 downto 0);
-		gnxt		: out unsigned (width-1 downto 0)
-	);
-end gray_counter;
-
-architecture Behavioral of gray_counter is
-
-	signal cntg : unsigned (width-1 downto 0);
-	signal cntb : unsigned (width-1 downto 0);
-	signal nxtb : unsigned (width-1 downto 0);
-	signal nxtg : unsigned (width-1 downto 0);
-
-begin
-
-	bnxt	<= nxtb;
-	gnxt	<= nxtg;
-	bcnt	<= cntb;
-	gcnt	<= cntg;
-
-	process(rst, clk, ce, cntb, nxtb)
-	begin
-		if rst = '1' then
-			cntb	<= to_unsigned(init_value, width);
-			nxtb	<= to_unsigned(init_value, width);
-			nxtg	<= to_unsigned(init_value, width);
-			cntg	<= to_unsigned(init_value, width);
-		else
-			if rising_edge(clk) then
-				cntg	<= nxtg;
-				cntb	<= nxtb;
-			end if;	
-			nxtg <= bin2gray(nxtb);
-			nxtb <= cntb;
-			if ce = '1' then
-				nxtb <= cntb + 1;
-			end if;	
-		end if;	
-	end process;
-
-end Behavioral;
-
diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd
deleted file mode 100644
index a198fa1..0000000
--- a/lib/FIFO/src/sync_fifo_ctrl.vhd
+++ /dev/null
@@ -1,198 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity fifo_sync_ctrl is
-	Generic
-	(
-		addr_width : integer := 3;
-		almost_full_thresh : integer := 6;
-		almost_empty_thresh : integer := 2
-	);
-	Port
-	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		winc			: in  STD_LOGIC;
-		rinc			: in  STD_LOGIC;
-		ptr_w			: out unsigned (addr_width-1 downto 0);
-		ptr_r			: out unsigned (addr_width-1 downto 0);
-		fifo_pre_full	: out STD_LOGIC;
-		fifo_pre_empty	: out STD_LOGIC;
-		fifo_full		: out STD_LOGIC;
-		fifo_empty		: out STD_LOGIC;
-		fifo_afull		: out STD_LOGIC;
-		fifo_aempty		: out STD_LOGIC
-	);
-end fifo_sync_ctrl;
-
-architecture Behavioral of fifo_sync_ctrl is
-
-	signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0);
-	signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0);
-	signal empty, full : std_logic;
-	signal pre_empty, pre_full : std_logic;
-	signal was_write : std_logic;
-	signal diff : unsigned (addr_width downto 0);
-	
-begin
-
-	fifo_full		<= full;
-	fifo_empty		<= empty;
-	fifo_pre_full	<= pre_full;
-	fifo_pre_empty	<= pre_empty;
-
-
-proc_diff_gen:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			diff <= (others => '0');
-		elsif rising_edge(clk) then
-			if winc = '1' and rinc = '0' then
-				diff <= diff + 1;
-			elsif winc = '0' and rinc = '1' then
-				diff <= diff - 1;
-			end if;
-		end if;
-	end process;
-
-proc_status_almost_full:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			fifo_afull <= '0';
-		elsif rising_edge(clk) then
-			if diff >= almost_full_thresh-1 then
-				fifo_afull <= '1';
-			else
-				fifo_afull <= '0';
-			end if;	
-		end if;
-	end process;
-
-proc_status_almost_empty:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			fifo_aempty <= '1';
-		elsif rising_edge(clk) then
-			if diff <= almost_empty_thresh+1 then
-				fifo_aempty <= '1';
-			else
-				fifo_aempty <= '0';
-			end if;	
-		end if;
-	end process;
-
-proc_full_reg:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			full <= '0';
-		elsif rising_edge(clk) then
-			full <= pre_full;
-		end if;
-	end process;
-	
-proc_empty_reg:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			empty <= '1';
-		elsif rising_edge(clk) then
-			empty <= pre_empty;
-		end if;
-	end process;
-	
-proc_status_w:
-	process(was_write, pW_next, pR_next, pW, pR, winc, rinc)
-	begin
-		if (pW_next = pR) and (winc = '1' or was_write = '1') then
-			pre_full <= '1';
-		else
-			pre_full <= '0';
-		end if;
-		if (pR_next = pW) and (rinc = '1' or was_write = '0') then
-			pre_empty <= '1';
-		else
-			pre_empty <= '0';
-		end if;
-	end process;
-
-proc_flag_write:
-	process(rst, clk)
-	begin
-		if rst = '1' then
-			was_write <= '0';
-		elsif rising_edge(clk) then
-			if winc = '1' then
-				was_write <= '1';
-			elsif rinc = '1' then
-				was_write <= '0';
-			end if;
-		end if;
-	end process;
-	
-proc_ptr_w:
-	process(rst, clk, pW, winc)
-	begin
-		if rst = '1' then
-			pW <= to_unsigned(0, addr_width);
-			pW_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if winc = '1' then 
-				pW <= pW_next;
-			end if;
-		end if;
-		pW_next <= pW;
-		if winc = '1' then 
-			pW_next <= pW + 1;
-		end if;
-		ptr_w		<= pW;
-	end process;
-
-proc_ptr_r:
-	process(rst, clk, pR_next, pR, rinc)
-	begin
-		if rst = '1' then
-			pR <= to_unsigned(0, addr_width);
-			pR_next <= to_unsigned(0, addr_width);
-		elsif rising_edge(clk) then
-			if rinc = '1' then
-				pR <= pR_next;
-			end if;	
-		end if;
-		pR_next	<= pR;
-		if rinc = '1' then
-			pR_next	<= pR + 1;
-		end if;
-		ptr_r		<= pR_next;
-	end process;
-
-end Behavioral;
-
diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd
deleted file mode 100644
index 31e6b36..0000000
--- a/lib/FIFO/src/tb_fifo_async.vhd
+++ /dev/null
@@ -1,225 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE STD.TEXTIO.ALL;
-
--- LIBRARY WORK;
--- USE.YOURLIB.WHATELSE
-
-ENTITY tb_fifo_async IS
-END tb_fifo_async;
-
-ARCHITECTURE behavior OF tb_fifo_async IS 
-
-	--Constants
-	constant PERIOD_W 	: time := 10 ns;
-	constant PERIOD_R 	: time := 7.5 ns;
-	constant ADDR_WIDTH : integer := 3;
-	constant DATA_WIDTH : integer := 8;
-
-	--Inputs
-	signal rst					: STD_LOGIC := '1';
-	signal clk_w				: STD_LOGIC := '0';
-	signal clk_r				: STD_LOGIC := '0';
-	signal we					: STD_LOGIC := '0';
-	signal re					: STD_LOGIC := '0';
-	signal din					: unsigned (7 downto 0);
-	--Outputs
-
-	signal dout					: unsigned (7 downto 0);
-	signal fifo_full			: STD_LOGIC;
-	signal fifo_empty			: STD_LOGIC;
-	signal fifo_almost_full		: STD_LOGIC;
-	signal fifo_almost_empty	: STD_LOGIC;
-
-	signal write_en				: STD_LOGIC := '0';
-	signal read_en				: STD_LOGIC := '0';
-
-	signal ref_r				: unsigned (7 downto 0);
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width					=> ADDR_WIDTH,
-		data_width					=> DATA_WIDTH,
-		almost_full_thresh			=> 6,
-		almost_empty_thresh			=> 2,
-		allow_full_writes			=> false,
-		allow_empty_reads			=> false,
-		do_last_read_update			=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk_w		=>	clk_w,
-		clk_r		=>	clk_r,
-		we			=>	we,
-		re			=>	re,
-		data_w		=>	din,
-		data_r		=>	dout,
-		fifo_full	=>	fifo_full,
-		fifo_empty	=>	fifo_empty,
-		fifo_afull	=>	fifo_almost_full,
-		fifo_aempty	=>	fifo_almost_empty
-
-	);
-
- 	tb_clk_w : PROCESS
-	BEGIN
-		clk_w <= not clk_w;
-		wait for PERIOD_W/2;
-	END PROCESS;
-
- 	tb_clk_r : PROCESS
-	BEGIN
-		clk_r <= not clk_r;
-		wait for PERIOD_R/2;
-	END PROCESS;
-
- 	tb_write : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 5*PERIOD_W;
-		rst			<= '0';
-		wait for 7*PERIOD_W;
-		write_en <= '1';
-		wait for 25*PERIOD_W;
-		write_en <= '0';
-		wait for 7*PERIOD_W;
-		write_en <= '1';
-		wait for 25*PERIOD_W;
-		write_en <= '0';
-		wait for 7*PERIOD_W;
-		write_en <= '1';
-		wait for 1*PERIOD_W;
-		write_en <= '0';
-		wait for 1*PERIOD_W;
-		write_en <= '1';
-		wait for 1*PERIOD_W;
-		write_en <= '0';
-		wait for 3*PERIOD_W;
-		write_en <= '1';
-		wait for 4*PERIOD_W;
-		write_en <= '0';
-		wait for 17*PERIOD_W;
-		write_en <= '1';
-		wait for 55*PERIOD_W;
-		write_en <= '0';
-		wait for 1*PERIOD_W;
-		write_en <= '1';
-		wait for 1*PERIOD_W;
-		write_en <= '0';
-		wait for 3*PERIOD_W;
-		write_en <= '1';
-		wait for 44*PERIOD_W;
-		write_en <= '0';
-		
-		wait; 
-		
-	END PROCESS;
-
- 	tb_read : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 25*PERIOD_R;
-		read_en <= '1';
-		wait for 25*PERIOD_R;
-		read_en <= '0';
-		wait for 25*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 5*PERIOD_R;
-		read_en <= '1';
-		wait for 1*PERIOD_R;
-		read_en <= '0';
-		wait for 7*PERIOD_R;
-		read_en <= '1';
-		wait for 15*PERIOD_R;
-		read_en <= '0';
-		wait; 
-		
-	END PROCESS;
-	
-	we <= write_en;
-	
- 	tb_w : PROCESS(rst, clk_w)
-	BEGIN
-
-		if rst = '1' then
-			din <= (others => '0');
-		elsif rising_edge(clk_w) then
-			if we = '1' and fifo_full = '0' then
-				din <= din + 1;
-			end if;				
-		end if;	
-
-	END PROCESS;
-	
-	re	<= read_en;
-	
- 	tb_r : PROCESS(rst, clk_r)
-	BEGIN
-
-		if rst = '1' then
-			ref_r <= (others => '0');
-		elsif rising_edge(clk_r) then
-			if re = '1' and fifo_empty = '0' then
-				assert ref_r = dout report "FIFO read error!" severity failure;
-				ref_r <= ref_r + 1;
-			end if;				
-		end if;	
-		
-	END PROCESS;
-
-END behavior;
\ No newline at end of file
diff --git a/lib/FIFO/src/tb_fifo_sync.vhd b/lib/FIFO/src/tb_fifo_sync.vhd
deleted file mode 100644
index f7fb6a5..0000000
--- a/lib/FIFO/src/tb_fifo_sync.vhd
+++ /dev/null
@@ -1,207 +0,0 @@
--------------------------------------------------------------------------
--- Project: FIFO, generic FIFOs written in VHDL
--- Release 1
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
---
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
---
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE STD.TEXTIO.ALL;
-
--- LIBRARY WORK;
--- USE.YOURLIB.WHATELSE
-
-ENTITY tb_fifo_sync IS
-END tb_fifo_sync;
-
-ARCHITECTURE behavior OF tb_fifo_sync IS 
-
-	--Constants
-	constant PERIOD 	: time := 10 ns;
-	constant ADDR_WIDTH : integer := 3;
-	constant DATA_WIDTH : integer := 8;
-
-	--Inputs
-	signal rst					: STD_LOGIC := '1';
-	signal clk					: STD_LOGIC := '0';
-	signal we					: STD_LOGIC := '0';
-	signal re					: STD_LOGIC := '0';
-	signal din					: unsigned (7 downto 0);
-	--Outputs
-
-	signal dout					: unsigned (7 downto 0);
-	signal fifo_full			: STD_LOGIC;
-	signal fifo_empty			: STD_LOGIC;
-	signal fifo_almost_full		: STD_LOGIC;
-	signal fifo_almost_empty	: STD_LOGIC;
-
-	signal write_en				: STD_LOGIC := '0';
-	signal read_en				: STD_LOGIC := '0';
-
-	signal ref_r				: unsigned (7 downto 0) := (others => '0');
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: entity work.fifo_sync
-	GENERIC MAP
-	(
-		data_width					=> DATA_WIDTH,
-		addr_width					=> ADDR_WIDTH,
-		almost_full_thresh			=> 6,
-		almost_empty_thresh			=> 2,
-		do_last_read_update			=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	we,
-		re			=>	re,
-		data_w		=>	din,
-		data_r		=>	dout,
-		fifo_full	=>	fifo_full,
-		fifo_empty	=>	fifo_empty,
-		fifo_afull	=>	fifo_almost_full,
-		fifo_aempty	=>	fifo_almost_empty
-
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
- 	tb_write : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 5*PERIOD;
-		rst			<= '0';
-		wait for 7*PERIOD;
-		write_en <= '1';
-		wait for 25*PERIOD;
-		write_en <= '0';
-		wait for 7*PERIOD;
-		write_en <= '1';
-		wait for 25*PERIOD;
-		write_en <= '0';
-		wait for 7*PERIOD;
-		write_en <= '1';
-		wait for 1*PERIOD;
-		write_en <= '0';
-		wait for 1*PERIOD;
-		write_en <= '1';
-		wait for 1*PERIOD;
-		write_en <= '0';
-		wait for 3*PERIOD;
-		write_en <= '1';
-		wait for 4*PERIOD;
-		write_en <= '0';
-		wait for 17*PERIOD;
-		write_en <= '1';
-		wait for 25*PERIOD;
-		write_en <= '0';
-		
-		wait; 
-		
-	END PROCESS;
-
- 	tb_read : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 25*PERIOD;
-		read_en <= '1';
-		wait for 25*PERIOD;
-		read_en <= '0';
-		wait for 25*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 5*PERIOD;
-		read_en <= '1';
-		wait for 1*PERIOD;
-		read_en <= '0';
-		wait for 7*PERIOD;
-		read_en <= '1';
-		wait for 20*PERIOD;
-		read_en <= '0';
-		
-		wait; 
-		
-	END PROCESS;
-
-	we <= write_en and not fifo_full;
-
- 	tb_w : PROCESS(rst, clk)
-	BEGIN
-
-		if rst = '1' then
-			din <= (others => '0');
-		elsif rising_edge(clk) then
-			if we = '1' then
-				din <= din + 1;
-			end if;				
-		end if;	
-
-	END PROCESS;
-	
-	re	<= read_en and not fifo_empty;
-
- 	tb_r : PROCESS(rst, clk)
-	BEGIN
-
-		if rst = '1' then
-			ref_r <= (others => '0');
-		elsif rising_edge(clk) then
-			if re = '1' then
-				assert ref_r = dout report "FIFO read error!" severity failure;
-				ref_r <= ref_r + 1;
-			end if;				
-		end if;	
-		
-	END PROCESS;
-
-END behavior;
\ No newline at end of file
diff --git a/lib/FIFO/src/tb_gray_counter.vhd b/lib/FIFO/src/tb_gray_counter.vhd
deleted file mode 100644
index 1fd241d..0000000
--- a/lib/FIFO/src/tb_gray_counter.vhd
+++ /dev/null
@@ -1,85 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_gray_counter
--- Module Name:   tb_gray_counter.vhd
--- Project Name:  gray_counter package
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.2 2010-02-13 10:50:47 Jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE STD.TEXTIO.ALL;
-
-LIBRARY WORK;
-USE WORK.FIFO_CTRL_PKG.ALL;
-
-ENTITY tb_gray_counter IS
-END tb_gray_counter;
-
-ARCHITECTURE behavior OF tb_gray_counter IS 
-
-	constant PERIOD		: time := 10 ns;
-	constant WIDTH		: integer := 3;
-
-	--Signals
-	signal gcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
-	signal bcnt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
-	signal gnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
-	signal bnxt			: unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH);
-	signal rst			: STD_LOGIC := '1';
-	signal clk			: STD_LOGIC := '0';
-	signal ce			: STD_LOGIC := '0';
-
-BEGIN
-
-inst_gray_counter : entity work.gray_counter
-	generic map (width => WIDTH)
-	port map (
-		rst			=> rst,
-		clk			=> clk,
-		ce			=> ce, 
-		bcnt		=> bcnt,
-		bnxt		=> bnxt,
-		gcnt		=> gcnt,
-		gnxt		=> gnxt
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
- 	tb_counter : PROCESS
- 	
-	BEGIN
-
-		wait for 4*PERIOD;
-		rst <= '0';
-		wait until rising_edge(clk);
-		ce <= '1';
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		ce <= '0';
-		wait for 3*PERIOD;
-		wait until rising_edge(clk);
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-		wait until rising_edge(clk);
-		ce <= '1';
-		
-		wait;
-		
-	END PROCESS;
-
-END behavior;
\ No newline at end of file
diff --git a/lib/JBUS/sim/tb_busmaster_async.fdo b/lib/JBUS/sim/tb_busmaster_async.fdo
deleted file mode 100644
index a368bf7..0000000
--- a/lib/JBUS/sim/tb_busmaster_async.fdo
+++ /dev/null
@@ -1,21 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../src/busmaster_types.vhd"
-vcom -explicit  -93 "../src/busmaster_async.vhd"
-vcom -explicit  -93 "../src/tb_busmaster_async.vhd"
-vsim -t 1ps   -lib work tb_busmaster_async
-view wave
-do {tb_busmaster_async.wdo}
-view structure
-view signals
-
-run 80us
diff --git a/lib/JBUS/sim/tb_busmaster_async.wdo b/lib/JBUS/sim/tb_busmaster_async.wdo
deleted file mode 100644
index b45143d..0000000
--- a/lib/JBUS/sim/tb_busmaster_async.wdo
+++ /dev/null
@@ -1,59 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
-add wave -noupdate -divider J-BUS
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/ack_i
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/mdat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/addr_o
-add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/sel_o
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/we_o
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/stb_o
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/mrdy_o
-add wave -noupdate -divider Busmaster
-add wave -noupdate -format Logic /tb_busmaster_async/clk_o
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_finished
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_cycle_en
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_rdy
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_we
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/inst_uut/cmd_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/din
-add wave -noupdate -format Logic /tb_busmaster_async/din_rdy
-add wave -noupdate -format Logic /tb_busmaster_async/din_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/inst_uut/dout
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_vld
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/dout_re
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cycle_busy
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_en
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cmd_read_en
-add wave -noupdate -format Literal /tb_busmaster_async/inst_uut/read_cnt
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/cyc_o
-add wave -noupdate -divider RAM
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_async/inst_uut/rst
-add wave -noupdate -format Literal /tb_busmaster_async/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_async/read_reg
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_async/ram64
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {31500000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/JBUS/sim/tb_busmaster_sync.fdo b/lib/JBUS/sim/tb_busmaster_sync.fdo
deleted file mode 100644
index 51438b6..0000000
--- a/lib/JBUS/sim/tb_busmaster_sync.fdo
+++ /dev/null
@@ -1,20 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/busmaster_types.vhd"
-vcom -explicit  -93 "../src/busmaster_sync.vhd"
-vcom -explicit  -93 "../src/tb_busmaster_sync.vhd"
-vsim -t 1ps   -lib work tb_busmaster_sync
-view wave
-do {tb_busmaster_sync.wdo}
-view structure
-view signals
-
-run 40us
diff --git a/lib/JBUS/sim/tb_busmaster_sync.wdo b/lib/JBUS/sim/tb_busmaster_sync.wdo
deleted file mode 100644
index e6e10cc..0000000
--- a/lib/JBUS/sim/tb_busmaster_sync.wdo
+++ /dev/null
@@ -1,54 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst
-add wave -noupdate -divider J-BUS
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/ack_i
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/mdat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/addr_o
-add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/sel_o
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/we_o
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cyc_o
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/stb_o
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/mrdy_o
-add wave -noupdate -divider Busmaster
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_finished
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_cycle_en
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_rdy
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_we
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_busmaster_sync/inst_uut/cmd_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/inst_uut/dout
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_vld
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/dout_re
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cycle_busy
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_en
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/cmd_read_en
-add wave -noupdate -format Literal /tb_busmaster_sync/inst_uut/read_cnt
-add wave -noupdate -divider RAM
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/clk
-add wave -noupdate -format Logic /tb_busmaster_sync/inst_uut/rst
-add wave -noupdate -format Literal /tb_busmaster_sync/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/read_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_busmaster_sync/ram64
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {7559494 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {50 ns} {21050 ns}
diff --git a/lib/JBUS/sim/tb_dmac.fdo b/lib/JBUS/sim/tb_dmac.fdo
deleted file mode 100644
index ca0cbf8..0000000
--- a/lib/JBUS/sim/tb_dmac.fdo
+++ /dev/null
@@ -1,21 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/busmaster_types.vhd"
-vcom -explicit  -93 "../src/busmaster_sync.vhd"
-vcom -explicit  -93 "../src/dmac.vhd"
-vcom -explicit  -93 "../src/tb_dmac.vhd"
-vsim -t 1ps   -lib work tb_dmac
-view wave
-do {tb_dmac.wdo}
-view structure
-view signals
-
-run 6us
diff --git a/lib/JBUS/sim/tb_dmac.wdo b/lib/JBUS/sim/tb_dmac.wdo
deleted file mode 100644
index 6f86009..0000000
--- a/lib/JBUS/sim/tb_dmac.wdo
+++ /dev/null
@@ -1,177 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_reg
-add wave -noupdate -format Literal /tb_dmac/dma_master_req
-add wave -noupdate -format Literal /tb_dmac/dma_master_gnt
-add wave -noupdate -format Literal /tb_dmac/dma_req_rdy
-add wave -noupdate -format Literal /tb_dmac/dma_req_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/dma_req_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/dma_req_num_xfers
-add wave -noupdate -format Literal /tb_dmac/dma_req_complete
-add wave -noupdate -format Literal /tb_dmac/dma_req_complete_ack
-add wave -noupdate -format Logic /tb_dmac/bus_cmd_cycle_finished
-add wave -noupdate -format Logic /tb_dmac/bus_cmd_cycle_en
-add wave -noupdate -format Logic /tb_dmac/bus_cmd_rdy
-add wave -noupdate -format Logic /tb_dmac/bus_cmd_we
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dmac/bus_cmd
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/bus_dout
-add wave -noupdate -format Logic /tb_dmac/bus_dout_vld
-add wave -noupdate -format Logic /tb_dmac/bus_dout_re
-add wave -noupdate -format Logic /tb_dmac/bus_din_rdy
-add wave -noupdate -format Logic /tb_dmac/bus_din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/bus_din
-add wave -noupdate -divider Busmaster
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/din
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/din_rdy
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/din_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/dout
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/dout_vld
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/dout_re
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/ack_i
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/mdat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/addr_o
-add wave -noupdate -format Literal /tb_dmac/inst_busmaster_sync/sel_o
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/we_o
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cyc_o
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/stb_o
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/mrdy_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/inst_busmaster_sync/cmd_fifo_dout
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_re
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_we
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_full
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_re
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_we
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_full
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/read_fifo_empty
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_re
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_we
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_full
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write_fifo_empty
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cycle_busy
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_en
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/cmd_read_en
-add wave -noupdate -format Literal /tb_dmac/inst_busmaster_sync/read_cnt
-add wave -noupdate -format Logic /tb_dmac/inst_busmaster_sync/write
-add wave -noupdate -divider JBUS
-add wave -noupdate -format Logic /tb_dmac/clk_o
-add wave -noupdate -format Logic /tb_dmac/rst_o
-add wave -noupdate -format Logic /tb_dmac/int_o
-add wave -noupdate -format Logic /tb_dmac/cyc_o
-add wave -noupdate -format Logic /tb_dmac/stb_o
-add wave -noupdate -format Logic /tb_dmac/we_o
-add wave -noupdate -format Literal /tb_dmac/sel_o
-add wave -noupdate -format Logic /tb_dmac/ack_i
-add wave -noupdate -format Logic /tb_dmac/mrdy_o
-add wave -noupdate -format Logic /tb_dmac/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/mdat_o
-add wave -noupdate -divider {DMA 0}
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/clk
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/rst
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/master_req
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/master_gnt
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_start
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_active
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/dma_end
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_rw
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_addr_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_num_xfers
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_addr_auto_inc
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_complete_ack
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cyc_complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_we
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/bus_cmd_cycle_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/bus_cmd_out
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/start_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/finish_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/addr_inc_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/addr
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/rw
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_count_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/req_count_next
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/req_count_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_rst
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/chunk_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__0/inst_uut/chunk_count_next
-add wave -noupdate -format Logic /tb_dmac/gen_uut__0/inst_uut/chunk_count_rdy
-add wave -noupdate -format Literal /tb_dmac/gen_uut__0/inst_uut/s
-add wave -noupdate -divider {DMA 1}
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/clk
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/rst
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/master_req
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/master_gnt
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_start
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_active
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/dma_end
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_rw
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_addr_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_num_xfers
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_addr_auto_inc
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_complete_ack
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cyc_complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_we
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/bus_cmd_cycle_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/bus_cmd_out
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/start_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/finish_en
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/complete
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/addr_inc_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/addr
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/rw
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_count_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/req_count_next
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/req_count_rdy
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_rst
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/chunk_count
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/gen_uut__1/inst_uut/chunk_count_next
-add wave -noupdate -format Logic /tb_dmac/gen_uut__1/inst_uut/chunk_count_rdy
-add wave -noupdate -format Literal /tb_dmac/gen_uut__1/inst_uut/s
-add wave -noupdate -divider {Read FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/data_gen_reg
-add wave -noupdate -format Logic /tb_dmac/data_gen_reg_inc
-add wave -noupdate -format Literal /tb_dmac/dma_write_source
-add wave -noupdate -format Logic /tb_dmac/read_fifo_re
-add wave -noupdate -format Logic /tb_dmac/read_fifo_we
-add wave -noupdate -format Logic /tb_dmac/read_fifo_full
-add wave -noupdate -format Logic /tb_dmac/read_fifo_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/read_fifo_dout
-add wave -noupdate -divider RAM
-add wave -noupdate -format Literal /tb_dmac/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_dmac/ram64
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3159968 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {6300 ns}
diff --git a/lib/JBUS/src/busmaster_async.vhd b/lib/JBUS/src/busmaster_async.vhd
deleted file mode 100644
index 3c5a90b..0000000
--- a/lib/JBUS/src/busmaster_async.vhd
+++ /dev/null
@@ -1,277 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.2 2013-08-04 17:58:37 jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.busmaster_types.all;
-
-------------------------------------------------------------------
-entity busmaster_async is
-	Generic
-	(
-		DATA_WIDTH			: natural := 32;
-		FIFO_DEPTH			: natural := 4
-	);
-	Port 
-	(
-		clk					: in std_logic;
-		rst					: in std_logic;
-
-		cmd_cycle_finished	: out std_logic;
-		cmd_cycle_en		: in std_logic;
-		cmd_rdy				: out std_logic;
-		cmd_we				: in std_logic;
-		
-		cmd_in				: in bm_cmd_t;
-		
-		din					: in unsigned(DATA_WIDTH-1 downto 0);
-		din_rdy				: out std_logic;
-		din_we				: in std_logic;
-
-		dout				: out unsigned(DATA_WIDTH-1 downto 0);
-		dout_vld			: out std_logic;
-		dout_re				: in std_logic;
-		
-		-- J-BUS signals
-		RST_I				: in  STD_LOGIC;
-		CLK_I				: in  STD_LOGIC;
-		ACK_I				: in std_logic;
-		SRDY_I				: in std_logic;
-		MDAT_I				: in unsigned(DATA_WIDTH-1 downto 0);
-		MDAT_O				: out unsigned(DATA_WIDTH-1 downto 0);
-		ADDR_O				: out unsigned(31 downto 0);
-		SEL_O				: out unsigned(DATA_WIDTH/8-1 downto 0);
-		WE_O				: out std_logic;
-		CYC_O				: out std_logic;
-		STB_O				: out std_logic;
-		MRDY_O				: out std_logic
-	);
-	end busmaster_async;
-
-architecture Behavioral of busmaster_async is
-
-	-- Bus Command FIFO
-	signal cmd_fifo_din		: unsigned(32+DATA_WIDTH/8+1-1 downto 0);
-	signal cmd_fifo_dout	: unsigned(32+DATA_WIDTH/8+1-1 downto 0);
-	signal cmd_fifo_re		: std_logic;
-	signal cmd_fifo_we		: std_logic;
-	signal cmd_fifo_full	: std_logic;
-	signal cmd_fifo_empty	: std_logic;
-	
-	-- Bus Read FIFO
-	signal read_fifo_re		: std_logic;
-	signal read_fifo_we		: std_logic;
-	signal read_fifo_full	: std_logic;
-	signal read_fifo_empty	: std_logic;
-	signal write_fifo_re	: std_logic;
-	signal write_fifo_we	: std_logic;
-	signal write_fifo_full	: std_logic;
-	signal write_fifo_empty	: std_logic;
-	signal cycle_busy		: std_logic;
-	signal cmd_en			: std_logic;
-	signal cmd_read_en		: std_logic;
-	signal read_cnt			: integer range 0 to 65535;
-	signal write			: std_logic;
-
-	signal jbus_cycle_busy	: std_logic;
-
-	type jbus_state_t is (init, ready, start, wait_finish, finish1, finish2, finish3);
-	signal jbus_state		: jbus_state_t;
-	signal jbus_state_next	: jbus_state_t;
-	
-begin
-
-	cmd_en				<= cmd_cycle_en and cmd_we and not cmd_fifo_full;
-	cmd_read_en			<= cmd_en and not cmd_in.rw;
-	write				<= cmd_fifo_dout(32+DATA_WIDTH/8);
-	
-	dout_vld			<= not read_fifo_empty;
-	MRDY_O				<= not read_fifo_full;
-	read_fifo_we		<= ACK_I and jbus_cycle_busy;
-	read_fifo_re		<= dout_re;
-	ADDR_O				<= cmd_fifo_dout(31 downto 0);
-	SEL_O				<= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
-	WE_O				<= write;
-	
-	cmd_fifo_din		<= cmd_in.rw & cmd_in.sel & cmd_in.addr;
-	
-	cmd_rdy				<= not cmd_fifo_full;
-	
-	cmd_fifo_we			<= cmd_en;
-	cmd_fifo_re			<= SRDY_I and jbus_cycle_busy;
-	
-	din_rdy				<= not write_fifo_full;
-	write_fifo_we		<= din_we;
-	write_fifo_re		<= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
-	
-	CYC_O				<= jbus_cycle_busy;
-	STB_O				<= not cmd_fifo_empty;
-	
-	
--- J-Bus domain
-proc_JBUS_to_local_cmd_cycle_finished:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			cmd_cycle_finished	 <= not jbus_cycle_busy;
-		end if;
-	end process;	
-
-proc_JBUS_cycle:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			jbus_cycle_busy	 <= cycle_busy;
-		end if;
-	end process;	
-
-proc_bus_read_counter:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				read_cnt	<= 0;
-			elsif cmd_read_en = '1' and read_fifo_empty = '1' then
-				read_cnt <= read_cnt + 1;
-			elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
-				read_cnt <= read_cnt - 1;
-			end if;	
-		end if;
-	end process;	
-
-jbus_state_fsm_next:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				jbus_state	 <= init;
-			else
-				jbus_state	 <= jbus_state_next;
-			end if;
-		end if;
-	end process;	
-
-jbus_state_fsm:
-	process(jbus_state, cmd_we, cmd_fifo_empty, write_fifo_empty, read_cnt)
-	begin
-
-		cycle_busy	 		<= '0';
-		jbus_state_next		<= jbus_state;
-		
-		case jbus_state is 
-		
-		when init =>
-			jbus_state_next		<= ready;
-		
-		when ready =>
-			if cmd_we = '1' or cmd_fifo_empty = '0' then
-				jbus_state_next		<= start;
-			end if;
-				
-		when start =>
-			cycle_busy	 <= '1';
-			if cmd_fifo_empty = '0' then
-				jbus_state_next		<= wait_finish;
-			end if;
-
-		when wait_finish =>
-			cycle_busy	 <= '1';
-			if read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
-				jbus_state_next		<= finish1;
-			end if;
-			
-		-- Quick and dirty hack
-		-- avoid buscycle to finish even if data available,
-		-- caused by latency of async-FIFO empty flag
-		when finish1 =>
-			jbus_state_next		<= finish2;
-		
-		when finish2 =>
-			jbus_state_next		<= finish3;
-
-		when finish3 =>
-			jbus_state_next		<= ready;
-			if cmd_fifo_empty = '0' then
-				jbus_state_next		<= wait_finish;
-			end if;
-		-- Quick and dirty hack
-
-		when others =>
-		jbus_state_next		<= ready;
-		
-		end case;
-	end process;	
-
--- Bus READ FIFO
-inst_BM_READ_FIFO: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> DATA_WIDTH,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk_r		=>	clk,
-		clk_w		=>	CLK_I,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_r		=>  dout,
-		data_w		=>  MDAT_I
-	);
-	
--- Bus WRITE FIFO
-inst_BM_WRITE_FIFO: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> DATA_WIDTH,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk_r		=>	CLK_I,
-		clk_w		=>	clk,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_r		=>  MDAT_O,
-		data_w		=>  din
-	);
-
--- Bus command FIFO
-inst_BM_CMD_FIFO: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> cmd_fifo_din'length,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk_r		=>	CLK_I,
-		clk_w		=>	clk,
-		we			=>	cmd_fifo_we,
-		re			=>	cmd_fifo_re,
-		fifo_full	=>	cmd_fifo_full,
-		fifo_empty	=>	cmd_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_r		=>  cmd_fifo_dout,
-		data_w		=>  cmd_fifo_din
-	);
-
-end Behavioral;
diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd
deleted file mode 100644
index 406e1d3..0000000
--- a/lib/JBUS/src/busmaster_sync.vhd
+++ /dev/null
@@ -1,216 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.6 2013-08-03 19:31:19 jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.busmaster_types.all;
-
-------------------------------------------------------------------
-entity busmaster_sync is
-	Generic
-	(
-		DATA_WIDTH			: natural := 32;
-		FIFO_DEPTH			: natural := 4
-	);
-	Port 
-	(
-		clk					: in std_logic;
-		rst					: in std_logic;
-
-		cmd_cycle_finished	: out std_logic;
-		cmd_cycle_en		: in std_logic;
-		cmd_rdy				: out std_logic;
-		cmd_we				: in std_logic;
-		
-		cmd_in				: in bm_cmd_t;
-		
-		din					: in unsigned(DATA_WIDTH-1 downto 0);
-		din_rdy				: out std_logic;
-		din_we				: in std_logic;
-
-		dout				: out unsigned(DATA_WIDTH-1 downto 0);
-		dout_vld			: out std_logic;
-		dout_re				: in std_logic;
-		
-		-- J-BUS signals
-		ACK_I				: in std_logic;
-		SRDY_I				: in std_logic;
-		MDAT_I				: in unsigned(DATA_WIDTH-1 downto 0);
-		MDAT_O				: out unsigned(DATA_WIDTH-1 downto 0);
-		ADDR_O				: out unsigned(31 downto 0);
-		SEL_O				: out unsigned(DATA_WIDTH/8-1 downto 0);
-		WE_O				: out std_logic;
-		CYC_O				: out std_logic;
-		STB_O				: out std_logic;
-		MRDY_O				: out std_logic
-	);
-	end busmaster_sync;
-
-architecture Behavioral of busmaster_sync is
-
-	-- Bus Command FIFO
-	signal cmd_fifo_din		: unsigned(32+DATA_WIDTH/8+1-1 downto 0);
-	signal cmd_fifo_dout	: unsigned(32+DATA_WIDTH/8+1-1 downto 0);
-	signal cmd_fifo_re		: std_logic;
-	signal cmd_fifo_we		: std_logic;
-	signal cmd_fifo_full	: std_logic;
-	signal cmd_fifo_empty	: std_logic;
-	
-	-- Bus Read FIFO
-	signal read_fifo_re		: std_logic;
-	signal read_fifo_we		: std_logic;
-	signal read_fifo_full	: std_logic;
-	signal read_fifo_empty	: std_logic;
-	signal write_fifo_re	: std_logic;
-	signal write_fifo_we	: std_logic;
-	signal write_fifo_full	: std_logic;
-	signal write_fifo_empty	: std_logic;
-	signal cycle_busy		: std_logic;
-	signal cmd_en			: std_logic;
-	signal cmd_read_en		: std_logic;
-	signal read_cnt			: integer range 0 to 65535;
-	signal write			: std_logic;
-
-begin
-
-	cmd_en				<= cmd_cycle_en and cmd_we and not cmd_fifo_full;
-	cmd_read_en			<= cmd_en and not cmd_in.rw;
-	write				<= cmd_fifo_dout(32+DATA_WIDTH/8);
-	
-	dout_vld			<= not read_fifo_empty;
-	MRDY_O				<= not read_fifo_full;
-	read_fifo_we		<= ACK_I and cycle_busy;
-	read_fifo_re		<= dout_re;
-	ADDR_O				<= cmd_fifo_dout(31 downto 0);
-	SEL_O				<= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
-	WE_O				<= write;
-	
-	cmd_fifo_din		<= cmd_in.rw & cmd_in.sel & cmd_in.addr;
-	
-	cmd_rdy				<= not cmd_fifo_full;
-	
-	cmd_fifo_we			<= cmd_en;
-	cmd_fifo_re			<= SRDY_I and cycle_busy;
-	
-	din_rdy				<= not write_fifo_full;
-	write_fifo_we		<= din_we;
-	write_fifo_re		<= SRDY_I and cycle_busy and write and not cmd_fifo_empty;
-	
-	STB_O				<= not cmd_fifo_empty;
-	CYC_O				<= cycle_busy;
-	cmd_cycle_finished	<= not cycle_busy;
-	
--- proc_bus_read_counter:
--- 	process(clk)
--- 	begin
--- 		if rising_edge(clk) then
--- 			if rst = '1' then
--- 				read_cnt	<= 0;
--- 			elsif cmd_read_en = '1' and read_fifo_we = '0' then
--- 				read_cnt <= read_cnt + 1;
--- 			elsif cmd_read_en = '0' and read_fifo_we = '1' then
--- 				read_cnt <= read_cnt - 1;
--- 			end if;	
--- 		end if;
--- 	end process;	
-
-proc_bus_read_counter:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				read_cnt	<= 0;
-			elsif cmd_read_en = '1' and read_fifo_empty = '1' then
-				read_cnt <= read_cnt + 1;
-			elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
-				read_cnt <= read_cnt - 1;
-			end if;	
-		end if;
-	end process;	
-
-proc_cycle_busy:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cycle_busy	 <= '0';
-			elsif cmd_cycle_en = '1' then
-				if cmd_we = '1' then
-					cycle_busy	 <= '1';
-				end if;
-			elsif read_cnt = 0 and cmd_fifo_empty = '1' and write_fifo_empty = '1' then
-				cycle_busy	 <= '0';
-			end if;
-		end if;
-	end process;	
-
--- Bus READ FIFO
-inst_BM_READ_FIFO: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> DATA_WIDTH,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  MDAT_I,
-		data_r		=>  dout
-	);
-	
--- Bus WRITE FIFO
-inst_BM_WRITE_FIFO: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> DATA_WIDTH,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  din,
-		data_r		=>  MDAT_O
-	);
-
--- Bus command FIFO
-inst_BM_CMD_FIFO: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> NextExpBaseTwo(FIFO_DEPTH),
-		data_width			=> cmd_fifo_din'length,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	cmd_fifo_we,
-		re			=>	cmd_fifo_re,
-		fifo_full	=>	cmd_fifo_full,
-		fifo_empty	=>	cmd_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cmd_fifo_din,
-		data_r		=>  cmd_fifo_dout
-	);
-
-end Behavioral;
diff --git a/lib/JBUS/src/busmaster_types.vhd b/lib/JBUS/src/busmaster_types.vhd
deleted file mode 100644
index db77b3d..0000000
--- a/lib/JBUS/src/busmaster_types.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_types.vhd,v 1.2 2013-05-27 11:17:51 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package busmaster_types is
-	
-	-- Constants
-	
-	-- Types
-	
-	type bm_cmd_t is
-	record
-		addr			: unsigned(31 downto 0);
-		sel				: unsigned(3 downto 0);
-		rw				: std_logic;
-	end record;
-
-end busmaster_types;
-
-
-package body busmaster_types is
-
-
-end busmaster_types;
-
-
diff --git a/lib/JBUS/src/dmac.vhd b/lib/JBUS/src/dmac.vhd
deleted file mode 100644
index 0674a36..0000000
--- a/lib/JBUS/src/dmac.vhd
+++ /dev/null
@@ -1,229 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.busmaster_types.all;
-
-------------------------------------------------------------------
-entity dmac is
-	Generic
-	(
-		DATA_WIDTH			: natural := 32;
-		XFER_CHUNK_SIZE		: natural := 512
-	);
-	Port 
-	(
-		clk					: in std_logic;
-		rst					: in std_logic;
-
-		master_req			: out std_logic;
-		master_gnt			: in std_logic;
-
-		dma_start			: out std_logic;
-		dma_active			: out std_logic;
-		dma_end				: out std_logic;
-
-		req_rdy				: out std_logic;
-		req_en				: in std_logic;
-		req_rw				: in std_logic;
-		req_addr_start		: in unsigned(31 downto 0);
-		req_num_xfers		: in unsigned(31 downto 0);
-		req_addr_auto_inc	: in std_logic;
-
-		req_complete		: out std_logic;
-		req_complete_ack	: in std_logic;
-
-		-- busmaster control
-		bus_cyc_complete	: in std_logic;
-		bus_cmd_rdy			: in std_logic;
-		bus_cmd_we			: out std_logic;
-		bus_cmd_cycle_en	: out std_logic;
-
-		-- busmaster command
-		bus_cmd_out			: out bm_cmd_t
-	);
-	end dmac;
-
-architecture Behavioral of dmac is
-	
-	signal start_en				: std_logic;
-	signal finish_en			: std_logic;
-	signal complete				: std_logic;
-	signal addr_inc_en			: std_logic;
-	signal addr					: unsigned(31 downto 0);
-	signal rw					: std_logic;
-
-	signal req_count_en			: std_logic;
-	signal req_count			: unsigned(31 downto 0);
-	signal req_count_next		: unsigned(32 downto 0);
-	signal req_count_rdy		: std_logic;
-	
-	signal chunk_count_rst		: std_logic;
-	signal chunk_count_en		: std_logic;
-	signal chunk_count			: unsigned(31 downto 0);
-	signal chunk_count_next		: unsigned(32 downto 0);
-	signal chunk_count_rdy		: std_logic;
-
-	type state_t is (INIT, READY, START, SETUP, XFER, FINISH, DONE);
-	signal s, sn	: state_t;
-	
-begin
-
-	bus_cmd_out.addr	<= addr;
-	bus_cmd_out.sel		<= (others => '1');
-	bus_cmd_out.rw		<= rw;
-	req_complete		<= complete;
-
-state_next:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				s	<= INIT;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-
-state:
-	process(s, req_en, master_gnt, req_count_rdy, chunk_count_rdy, bus_cyc_complete, bus_cmd_rdy)
-	begin
-		
-		bus_cmd_cycle_en	<= '0';
-		bus_cmd_we			<= '0';
-		start_en			<= '0';
-		finish_en			<= '0';
-		req_count_en		<= '0';
-		req_rdy				<= '0';
-		chunk_count_rst		<= '0';
-		chunk_count_en		<= '0';
-		master_req			<= '0';
-		dma_start			<= '0';
-		dma_active			<= '0';
-		dma_end				<= '0';
-		
-		sn					<= s;
-		case s is
-			when INIT =>
-				sn	<= READY;
-
-			when READY =>
-				req_rdy				<= '1';
-				if req_en = '1' then
-					start_en <= '1';
-					sn	<= SETUP;
-					end if;
-
-			when SETUP =>
-				dma_start			<= '1';
-				sn					<= START;
-
-			when START =>
-				master_req			<= '1';
-				chunk_count_rst		<= '1';
-				if req_count_rdy = '1' then
-					sn			<= READY;
-				elsif master_gnt = '1' and bus_cyc_complete = '1' then
-					sn	<= XFER;
-				end if;
-				
-			when XFER =>
-				dma_active			<= '1';
-				master_req			<= '1';
-				bus_cmd_we			<= '1';
-				bus_cmd_cycle_en	<= '1';
-				req_count_en		<= bus_cmd_rdy;
-				chunk_count_en		<= bus_cmd_rdy;
-				if req_count_rdy = '1' then
-					sn	<= FINISH;
-				elsif chunk_count_rdy = '1' then
-					sn	<= START;
-				end if;
-
-			when FINISH =>
-				master_req			<= '1';
-				if bus_cyc_complete = '1' then
-					sn			<= DONE;
-					finish_en	<= '1';
-				end if;
-				
-			when DONE =>
-				dma_end		<= '1';
-				sn	<= READY;
-
-			when others =>
-				sn	<= READY;
-
-		end case;
-	end process;	
-
-addr_gen:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if start_en = '1' then
-				rw				<= req_rw;
-				addr			<= req_addr_start;
-				addr_inc_en		<= req_addr_auto_inc;
-			elsif req_count_en = '1' and addr_inc_en = '1' then
-				addr			<= addr + DATA_WIDTH/8;
-			end if;
-		end if;
-	end process;	
-
-	req_count_next		<= ('0' & req_num_xfers) - 1 when start_en = '1' else ('0' & req_count) - 1;
-	req_count_rdy		<= req_count_next(32);
-	
-req_counter:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if start_en = '1' then
-				req_count		<= req_count_next(31 downto 0);
-			elsif req_count_en = '1' then
-				if req_count_rdy = '0' then
-					req_count		<= req_count_next(31 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;	
-
-	chunk_count_next	<= to_unsigned(XFER_CHUNK_SIZE, 33) - 1 when chunk_count_rst = '1' else ('0' & chunk_count) - 1;
-	chunk_count_rdy		<= chunk_count_next(32);
-
-chunk_counter:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if chunk_count_rst = '1' then
-				chunk_count		<= chunk_count_next(31 downto 0);
-			elsif chunk_count_en = '1' then
-				if chunk_count_rdy = '0' then
-					chunk_count		<= chunk_count_next(31 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;	
-
-complete_register:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if start_en = '1' or rst = '1' then
-				complete		<= '0';
-			elsif complete = '0' then
-				if finish_en = '1' then
-					complete		<= '1';
-				elsif req_complete_ack = '1' then
-					complete		<= '0';
-				end if;
-			end if;
-		end if;
-	end process;	
-
-end Behavioral;
diff --git a/lib/JBUS/src/tb_busmaster_async.vhd b/lib/JBUS/src/tb_busmaster_async.vhd
deleted file mode 100644
index 353d7d8..0000000
--- a/lib/JBUS/src/tb_busmaster_async.vhd
+++ /dev/null
@@ -1,451 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_async.vhd,v 1.1 2013-07-21 09:21:30 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-use work.busmaster_types.all;
-
-ENTITY tb_busmaster_async IS
-END tb_busmaster_async;
-
-ARCHITECTURE behavior OF tb_busmaster_async IS 
-
-	constant DATA_WIDTH				: integer := 32;
-	constant CLK_PERIOD				: time := 10 ns;
-	constant JBUS_CLK_PERIOD		: time := 20 ns;
-	signal clk						: std_logic := '1';
-	signal rst						: std_logic := '1';
-
-	signal CLK_O					: std_logic := '1';
-	signal RST_O					: std_logic := '1';
-
-	-- Master
-	signal INT_O			: std_logic;
-	signal CYC_O			: std_logic;
-	signal STB_O			: std_logic;
-	signal WE_O				: std_logic;
-	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I			: std_logic := '0';
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I_64		: unsigned(63 downto 0) := (others => '-');
-	signal MDAT_O_64		: unsigned(63 downto 0) := (others => '-');
-
-	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
-
-	signal cmd_cycle_finished	: std_logic;
-	signal cmd_cycle_en			: std_logic := '0';
-	signal cmd_rdy				: std_logic;
-	signal cmd_we				: std_logic := '0';
-	
-	signal cmd_in				: bm_cmd_t;
-		
-	signal din					: unsigned(31 downto 0) := (others => '-');
-	signal din_rdy				: std_logic;
-	signal din_we				: std_logic := '0';
-
-	signal dout					: unsigned(31 downto 0);
-	signal dout_vld				: std_logic;
-	signal dout_re				: std_logic := '0';
-
-	signal read_reg				: unsigned(31 downto 0) := (others => '-');
-
-	type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
-	signal state : state_t := IDLE;
-	
-	type ram_t  is array (0 to 127) of unsigned(63 downto 0);
-
-	signal ram64		: ram_t := 
-	(
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000"
-		
-	);
-
-BEGIN
-	
-	MDAT_I	<= MDAT_I_64(31 downto 0);
-	MDAT_O_64	<= MDAT_O & MDAT_O;
-
-inst_uut : entity work.busmaster_async
-	GENERIC MAP
-	(
-		DATA_WIDTH					=> 32,
-		FIFO_DEPTH					=> 2
-	)
-	PORT MAP
-	(
-		-- System signals
-		rst					=> rst,
-		clk					=> clk,
-
-		cmd_cycle_finished	=> cmd_cycle_finished,
-		cmd_cycle_en		=> cmd_cycle_en,
-		cmd_rdy				=> cmd_rdy,
-		cmd_we				=> cmd_we,
-		cmd_in				=> cmd_in,
-		
-		din					=> din,
-		din_rdy				=> din_rdy,
-		din_we				=> din_we,
-
-		dout				=> dout,
-		dout_vld			=> dout_vld,
-		dout_re				=> dout_re,
-
-		-- JBUS Master signals
-		RST_I				=> RST_O,
-		CLK_I				=> CLK_O,
-		CYC_O				=> CYC_O,
-		STB_O				=> STB_O,
-		WE_O				=> WE_O,
-		SEL_O				=> SEL_O,
-		ACK_I				=> ACK_I,
-		SRDY_I				=> SRDY_I,
-		MRDY_O				=> MRDY_O,
-		ADDR_O				=> ADDR_O,
-		MDAT_I				=> MDAT_I,
-		MDAT_O				=> MDAT_O
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-JBUS_CLK_GEN: process
-	begin
-		wait for JBUS_CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
--- Slave
-	SRDY_I	<= CYC_O;
-	
-	process(CLK_O)
-	variable res: unsigned(63 downto 0);
-	variable ram_data : unsigned(63 downto 0);
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-			else
-				ACK_I	<= '0';
-				if (CYC_O and STB_O) = '1' then
-					if WE_O = '0' then
-						ACK_I	<= '1';
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						if ADDR_O(2) = '0' then
-							res			:= ram_data;
-						else
-							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
-						end if;
-					elsif MRDY_O = '1' then -- WE=1
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						ram_data := (others => '-');
-						if ADDR_O(2) = '0' then
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
-							end if;
-						else
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
-							end if;
-						end if;
-					end if;
-				end if;
-				if (CYC_O and MRDY_O) = '1' then
-					MDAT_I_64	<= res;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				read_reg	<= X"00000000";
-			elsif dout_vld = '1' then
-				read_reg	<= dout;
-			end if;
-		end if;
-	end process;
-	dout_re	<= dout_vld;
-	
--- Master
-STIMULUS: process
-
-	variable result : unsigned(31 downto 0);
-
-	procedure cmd_write_single(addr, sel, data : unsigned) is
-	begin
-	
-		din				<= data;
-		din_we			<= '1';
-		wait until rising_edge(clk) and din_rdy = '1';
-		din_we			<= '0';
-
-		cmd_in.rw		<= '1';
-		cmd_in.sel		<= sel;
-		cmd_in.addr		<= addr;
-		cmd_we			<= '1';
-		wait until rising_edge(clk) and cmd_rdy = '1';
-		cmd_we			<= '0';
-
-	end procedure cmd_write_single;
-
-	procedure cmd_read_single(addr : unsigned) is
-	begin
-	
-		cmd_in.rw		<= '0';
-		cmd_in.sel		<= (others => '0');
-		cmd_in.addr		<= addr;
-		cmd_we			<= '1';
-		wait until rising_edge(clk) and cmd_rdy = '1';
-		cmd_we			<= '0';
-
-	end procedure cmd_read_single;
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		rst <= '0';
-		RST_O <= '0';
-		wait for 60*CLK_PERIOD;
-		wait until rising_edge(clk);
-		state <= IDLE;
-
-		for i in 0 to 9 loop
-
-			cmd_cycle_en	<= '1';
-			cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
-			cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
-			cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
-			cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
-			cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
-			cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
-			cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
-			cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
-			cmd_read_single(X"0000_0000");
-			cmd_read_single(X"0000_0008");
-			cmd_read_single(X"0000_0010");
-			cmd_read_single(X"0000_0018");
-			cmd_read_single(X"0000_0020");
-			cmd_read_single(X"0000_0028");
-			cmd_read_single(X"0000_0030");
-			cmd_read_single(X"0000_0038");
-			cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
-			cmd_read_single(X"0000_0000");
-			cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
-			cmd_read_single(X"0000_0008");
-			cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
-			cmd_read_single(X"0000_0010");
-			cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
-			cmd_read_single(X"0000_0018");
-			cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
-			cmd_read_single(X"0000_0020");
-			cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
-			cmd_read_single(X"0000_0028");
-			cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
-			cmd_read_single(X"0000_0030");
-			cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
-			cmd_read_single(X"0000_0038");
-			cmd_cycle_en	<= '0';
-			wait until rising_edge(clk);
-			wait until rising_edge(clk);
-			cmd_cycle_en	<= '1';
-			cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
-			cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
-			cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
-			cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
-			cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
-			cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
-			cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
-			cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
-			cmd_read_single(X"0000_0100");
-			cmd_read_single(X"0000_0108");
-			cmd_read_single(X"0000_0110");
-			cmd_read_single(X"0000_0118");
-			cmd_read_single(X"0000_0120");
-			cmd_read_single(X"0000_0128");
-			cmd_read_single(X"0000_0130");
-			cmd_read_single(X"0000_0138");
-			cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
-			cmd_read_single(X"0000_0100");
-			cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
-			cmd_read_single(X"0000_0108");
-			cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
-			cmd_read_single(X"0000_0110");
-			cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
-			cmd_read_single(X"0000_0118");
-			cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
-			cmd_read_single(X"0000_0120");
-			cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
-			cmd_read_single(X"0000_0128");
-			cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
-			cmd_read_single(X"0000_0130");
-			cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
-			cmd_read_single(X"0000_0138");
-			cmd_cycle_en	<= '0';
-
-			wait until rising_edge(clk) and cmd_cycle_finished = '1';
-			wait for 60*CLK_PERIOD;
-			wait until rising_edge(clk);
-		
-		end loop;
-		
-		state <= IDLE;
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/JBUS/src/tb_busmaster_sync.vhd b/lib/JBUS/src/tb_busmaster_sync.vhd
deleted file mode 100644
index 1e656f6..0000000
--- a/lib/JBUS/src/tb_busmaster_sync.vhd
+++ /dev/null
@@ -1,446 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-use work.busmaster_types.all;
-
-ENTITY tb_busmaster_sync IS
-END tb_busmaster_sync;
-
-ARCHITECTURE behavior OF tb_busmaster_sync IS 
-
-	constant DATA_WIDTH		: integer := 32;
-	constant CLK_PERIOD		: time := 10 ns;
-	signal CLK_O			: std_logic := '1';
-	signal RST_O			: std_logic := '1';
-
-	-- Master
-	signal INT_O			: std_logic;
-	signal CYC_O			: std_logic;
-	signal STB_O			: std_logic;
-	signal WE_O				: std_logic;
-	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I			: std_logic := '0';
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I_64		: unsigned(63 downto 0) := (others => '-');
-	signal MDAT_O_64		: unsigned(63 downto 0) := (others => '-');
-
-	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
-
-	signal cmd_cycle_finished	: std_logic;
-	signal cmd_cycle_en			: std_logic := '0';
-	signal cmd_rdy				: std_logic;
-	signal cmd_we				: std_logic := '0';
-	
-	signal cmd_in				: bm_cmd_t;
-		
-	signal din					: unsigned(31 downto 0) := (others => '-');
-	signal din_rdy				: std_logic;
-	signal din_we				: std_logic := '0';
-
-	signal dout					: unsigned(31 downto 0);
-	signal dout_vld				: std_logic;
-	signal dout_re				: std_logic := '0';
-
-	signal rdy					: std_logic := '0';
-	signal read_reg				: unsigned(31 downto 0) := (others => '-');
-
-	type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
-	signal state : state_t := IDLE;
-	
-	type ram_t  is array (0 to 127) of unsigned(63 downto 0);
-
-	signal ram64		: ram_t := 
-	(
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000"
-		
-	);
-
-BEGIN
-	
-	MDAT_I	<= MDAT_I_64(31 downto 0);
-	MDAT_O_64	<= MDAT_O & MDAT_O;
-
-inst_uut : entity work.busmaster_sync
-	GENERIC MAP
-	(
-		DATA_WIDTH					=> 32,
-		FIFO_DEPTH					=> 2
-	)
-	PORT MAP
-	(
-		-- System signals
-		rst					=> RST_O,
-		clk					=> CLK_O,
-
-		cmd_cycle_finished	=> cmd_cycle_finished,
-		cmd_cycle_en		=> cmd_cycle_en,
-		cmd_rdy				=> cmd_rdy,
-		cmd_we				=> cmd_we,
-		cmd_in				=> cmd_in,
-		
-		din					=> din,
-		din_rdy				=> din_rdy,
-		din_we				=> din_we,
-
-		dout				=> dout,
-		dout_vld			=> dout_vld,
-		dout_re				=> dout_re,
-
-		-- JBUS Master signals
-		CYC_O				=> CYC_O,
-		STB_O				=> STB_O,
-		WE_O				=> WE_O,
-		SEL_O				=> SEL_O,
-		ACK_I				=> ACK_I,
-		SRDY_I				=> SRDY_I,
-		MRDY_O				=> MRDY_O,
-		ADDR_O				=> ADDR_O,
-		MDAT_I				=> MDAT_I,
-		MDAT_O				=> MDAT_O
-	);
-
-rdy_GEN: process
-	begin
---		wait for 3*CLK_PERIOD/2;
-		wait until rising_edge(CLK_O);
-		rdy <= not rdy;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
--- Slave
-	SRDY_I	<= CYC_O;
-	
-	process(CLK_O)
-	variable res: unsigned(63 downto 0);
-	variable ram_data : unsigned(63 downto 0);
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-			else
-				ACK_I	<= '0';
-				if (CYC_O and STB_O) = '1' then
-					if WE_O = '0' then
-						ACK_I	<= '1';
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						if ADDR_O(2) = '0' then
-							res			:= ram_data;
-						else
-							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
-						end if;
-					elsif MRDY_O = '1' then -- WE=1
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						ram_data := (others => '-');
-						if ADDR_O(2) = '0' then
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
-							end if;
-						else
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
-							end if;
-						end if;
-					end if;
-				end if;
-				if (CYC_O and MRDY_O) = '1' then
-					MDAT_I_64	<= res;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				read_reg	<= X"00000000";
-			elsif dout_vld = '1' then
-				read_reg	<= dout;
-			end if;
-		end if;
-	end process;
-	dout_re	<= dout_vld;
-	
--- Master
-STIMULUS: process
-
-	variable result : unsigned(31 downto 0);
-
-	procedure cmd_write_single(addr, sel, data : unsigned) is
-	begin
-	
-		din				<= data;
-		din_we			<= '1';
-		wait until rising_edge(CLK_O) and din_rdy = '1';
-		din_we			<= '0';
-
-		cmd_in.rw		<= '1';
-		cmd_in.sel		<= sel;
-		cmd_in.addr		<= addr;
-		cmd_we			<= '1';
-		wait until rising_edge(CLK_O) and cmd_rdy = '1';
-		cmd_we			<= '0';
-
-	end procedure cmd_write_single;
-
-	procedure cmd_read_single(addr : unsigned) is
-	begin
-	
-		cmd_in.rw		<= '0';
-		cmd_in.sel		<= (others => '0');
-		cmd_in.addr		<= addr;
-		cmd_we			<= '1';
-		wait until rising_edge(CLK_O) and cmd_rdy = '1';
-		cmd_we			<= '0';
-
-	end procedure cmd_read_single;
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		RST_O <= '0';
-		wait for 60*CLK_PERIOD;
-		wait until rising_edge(CLK_O);
-		state <= IDLE;
-
-		for i in 0 to 9 loop
-
-			cmd_cycle_en	<= '1';
-			cmd_write_single(X"0000_0000", "1111", X"1000_ABCD");
-			cmd_write_single(X"0000_0008", "1111", X"2000_ABCD");
-			cmd_write_single(X"0000_0010", "1111", X"3000_ABCD");
-			cmd_write_single(X"0000_0018", "1111", X"4000_ABCD");
-			cmd_write_single(X"0000_0020", "1111", X"5000_ABCD");
-			cmd_write_single(X"0000_0028", "1111", X"6000_ABCD");
-			cmd_write_single(X"0000_0030", "1111", X"7000_ABCD");
-			cmd_write_single(X"0000_0038", "1111", X"8000_ABCD");
-			cmd_read_single(X"0000_0000");
-			cmd_read_single(X"0000_0008");
-			cmd_read_single(X"0000_0010");
-			cmd_read_single(X"0000_0018");
-			cmd_read_single(X"0000_0020");
-			cmd_read_single(X"0000_0028");
-			cmd_read_single(X"0000_0030");
-			cmd_read_single(X"0000_0038");
-			cmd_write_single(X"0000_0000", "1111", X"1000_BEEF");
-			cmd_read_single(X"0000_0000");
-			cmd_write_single(X"0000_0008", "1111", X"2000_BEEF");
-			cmd_read_single(X"0000_0008");
-			cmd_write_single(X"0000_0010", "1111", X"3000_BEEF");
-			cmd_read_single(X"0000_0010");
-			cmd_write_single(X"0000_0018", "1111", X"4000_BEEF");
-			cmd_read_single(X"0000_0018");
-			cmd_write_single(X"0000_0020", "1111", X"5000_BEEF");
-			cmd_read_single(X"0000_0020");
-			cmd_write_single(X"0000_0028", "1111", X"6000_BEEF");
-			cmd_read_single(X"0000_0028");
-			cmd_write_single(X"0000_0030", "1111", X"7000_BEEF");
-			cmd_read_single(X"0000_0030");
-			cmd_write_single(X"0000_0038", "1111", X"8000_BEEF");
-			cmd_read_single(X"0000_0038");
-			cmd_cycle_en	<= '0';
-			wait until rising_edge(CLK_O);
-			wait until rising_edge(CLK_O);
-			cmd_cycle_en	<= '1';
-			cmd_write_single(X"0000_0100", "1111", X"1100_ABCD");
-			cmd_write_single(X"0000_0108", "1111", X"2200_ABCD");
-			cmd_write_single(X"0000_0110", "1111", X"3300_ABCD");
-			cmd_write_single(X"0000_0118", "1111", X"4400_ABCD");
-			cmd_write_single(X"0000_0120", "1111", X"5500_ABCD");
-			cmd_write_single(X"0000_0128", "1111", X"6600_ABCD");
-			cmd_write_single(X"0000_0130", "1111", X"7700_ABCD");
-			cmd_write_single(X"0000_0138", "1111", X"8800_ABCD");
-			cmd_read_single(X"0000_0100");
-			cmd_read_single(X"0000_0108");
-			cmd_read_single(X"0000_0110");
-			cmd_read_single(X"0000_0118");
-			cmd_read_single(X"0000_0120");
-			cmd_read_single(X"0000_0128");
-			cmd_read_single(X"0000_0130");
-			cmd_read_single(X"0000_0138");
-			cmd_write_single(X"0000_0100", "1111", X"1100_BEEF");
-			cmd_read_single(X"0000_0100");
-			cmd_write_single(X"0000_0108", "1111", X"2200_BEEF");
-			cmd_read_single(X"0000_0108");
-			cmd_write_single(X"0000_0110", "1111", X"3300_BEEF");
-			cmd_read_single(X"0000_0110");
-			cmd_write_single(X"0000_0118", "1111", X"4400_BEEF");
-			cmd_read_single(X"0000_0118");
-			cmd_write_single(X"0000_0120", "1111", X"5500_BEEF");
-			cmd_read_single(X"0000_0120");
-			cmd_write_single(X"0000_0128", "1111", X"6600_BEEF");
-			cmd_read_single(X"0000_0128");
-			cmd_write_single(X"0000_0130", "1111", X"7700_BEEF");
-			cmd_read_single(X"0000_0130");
-			cmd_write_single(X"0000_0138", "1111", X"8800_BEEF");
-			cmd_read_single(X"0000_0138");
-			cmd_cycle_en	<= '0';
-
-			wait until rising_edge(CLK_O) and cmd_cycle_finished = '1';
-			wait for 60*CLK_PERIOD;
-			wait until rising_edge(CLK_O);
-		
-		end loop;
-		
-		state <= IDLE;
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/JBUS/src/tb_dmac.vhd b/lib/JBUS/src/tb_dmac.vhd
deleted file mode 100644
index e22af1f..0000000
--- a/lib/JBUS/src/tb_dmac.vhd
+++ /dev/null
@@ -1,540 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dmac.vhd,v 1.2 2013-05-28 11:23:15 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-use work.busmaster_types.all;
-
-ENTITY tb_dmac IS
-END tb_dmac;
-
-ARCHITECTURE behavior OF tb_dmac IS 
-
-	constant CLK_PERIOD				: time := 10 ns;
-	constant DATA_WIDTH				: integer := 32;
-
-	constant DMA_NUM_CHANNEL		: integer := 2;
-	constant DMA_CH_WRITE			: integer := 0;
-	constant DMA_CH_READ			: integer := 1;
-	constant DMA_RW_CONF			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := "01";
-
-	signal CLK_O					: std_logic := '1';
-	signal RST_O					: std_logic := '1';
-
-	-- Master
-	signal CYC_O					: std_logic;
-	signal STB_O					: std_logic;
-	signal WE_O						: std_logic;
-	signal SEL_O					: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I					: std_logic := '0';
-	signal MRDY_O					: std_logic := '1';
-	signal SRDY_I					: std_logic := '0';
-	signal ADDR_O					: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I_64				: unsigned(63 downto 0) := (others => '-');
-	signal MDAT_O_64				: unsigned(63 downto 0) := (others => '-');
-	
-	signal MDAT_I					: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_O					: unsigned(31 downto 0) := (others => '-');
-
-	-- DMA controller
-	signal dma_master_req			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_master_gnt			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_req_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_req_en				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_req_addr_auto_inc	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	type array32_t is array (0 to DMA_NUM_CHANNEL-1) of unsigned(31 downto 0);
-	signal dma_req_addr				: array32_t;
-	signal dma_req_num_xfers		: array32_t;
-
-	signal dma_req_complete			: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_req_complete_ack		: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-
-	signal dma_start					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_active					: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_end						: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_cycle_finished	: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_cycle_en			: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	signal dma_bus_cmd_rdy				: unsigned(DMA_NUM_CHANNEL-1 downto 0);
-	signal dma_bus_cmd_we				: unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
-	type array_bus_cmd_t is array (0 to DMA_NUM_CHANNEL-1) of bm_cmd_t;
-	signal dma_bus_cmd					: array_bus_cmd_t;
-
-	signal	arb_idx					: natural range 0 to DMA_NUM_CHANNEL-1;
-
-	-- BUS Master controller
-	signal bus_din_re				: std_logic;
-	signal bus_cmd_cycle_finished	: std_logic;
-	signal bus_cmd_cycle_en			: std_logic := '0';
-	signal bus_cmd_rdy				: std_logic;
-	signal bus_cmd_we				: std_logic := '0';
-	signal bus_cmd					: bm_cmd_t;
-		
-	signal bus_din_rdy				: std_logic;
-	signal bus_din_vld				: std_logic := '0';
-	signal bus_din					: unsigned(DATA_WIDTH-1 downto 0) := (others => '-');
-
-	signal bus_dout					: unsigned(31 downto 0);
-	signal bus_dout_vld				: std_logic;
-	signal bus_dout_re				: std_logic := '0';
-
-	signal rdy						: std_logic := '0';
-	signal read_reg					: unsigned(31 downto 0) := (others => '-');
-
-	signal data_gen_reg				: unsigned(31 downto 0) := (others => '-');
-	signal data_gen_reg_inc			: std_logic;
-	signal data_req					: std_logic;
-	
-	type dma_write_source_t is (DATA_GEN, READ_FIFO);
-	signal dma_write_source : dma_write_source_t := DATA_GEN;
-
-	-- Read FIFO
-	signal read_fifo_re		: std_logic;
-	signal read_fifo_we		: std_logic;
-	signal read_fifo_full	: std_logic;
-	signal read_fifo_empty	: std_logic;
-	signal read_fifo_din	: unsigned(31 downto 0);
-	signal read_fifo_dout	: unsigned(31 downto 0);
-
-	type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
-	signal state : state_t := IDLE;
-	
-	type ram_t  is array (0 to 127) of unsigned(63 downto 0);
-
-	signal ram64		: ram_t := 
-	(
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000"
-		
-	);
-
-BEGIN
-	
-	MDAT_I	<= MDAT_I_64(31 downto 0);
-	MDAT_O_64	<= MDAT_O & MDAT_O;
-
-arbiter_proc:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				dma_master_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif dma_master_req(arb_idx) = '0' then
-				if arb_idx /= DMA_NUM_CHANNEL-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				dma_master_gnt	<= (others => '0');
-				dma_master_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-
-arbiter_mux:
-	process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
-	variable v_bus_cmd_we : std_logic;
-	variable v_bus_cmd_cycle_en : std_logic;
-	begin
-		v_bus_cmd_we := '0';
-		v_bus_cmd_cycle_en := '0';
-		for i in 0 to DMA_NUM_CHANNEL-1 loop
-			v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
-			v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
-			if dma_master_gnt(i) = '1' then
-				bus_cmd <= dma_bus_cmd(i);
-			end if;
-		end loop;
-		bus_cmd_we <= v_bus_cmd_we;
-		bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
-end process;
-				
-
-gen_uut:
-for i in 0 to DMA_NUM_CHANNEL-1 generate
-	
-	dma_bus_cmd_cycle_finished(i)	<= bus_cmd_cycle_finished;
-	dma_bus_cmd_rdy(i) 				<= bus_cmd_rdy;
-
-	inst_uut : entity work.dmac
-	Generic map
-	(
-		DATA_WIDTH			=> 32,
-		XFER_CHUNK_SIZE		=> 8
-	)
-	Port map
-	(
-		clk					=> CLK_O,
-		rst					=> RST_O,
-
-		master_req			=> dma_master_req(i),
-		master_gnt			=> dma_master_gnt(i),
-
-		req_rdy				=> dma_req_rdy(i),
-		req_en				=> dma_req_en(i),
-		req_rw				=> DMA_RW_CONF(i),
-		req_addr_auto_inc	=> dma_req_addr_auto_inc(i),
-		req_addr_start		=> dma_req_addr(i),
-		req_num_xfers		=> dma_req_num_xfers(i),
-
-		req_complete		=> dma_req_complete(i),
-		req_complete_ack	=> dma_req_complete_ack(i),
-
-		dma_start			=> dma_start(i),
-		dma_active			=> dma_active(i),
-		dma_end				=> dma_end(i),
-
-		-- busmaster control
-		bus_cyc_complete	=> dma_bus_cmd_cycle_finished(i),
-		bus_cmd_rdy			=> dma_bus_cmd_rdy(i),
-		bus_cmd_we			=> dma_bus_cmd_we(i),
-		bus_cmd_cycle_en	=> dma_bus_cmd_cycle_en(i),
-
-		-- busmaster command
-		bus_cmd_out			=> dma_bus_cmd(i)
-	);
-
-end generate;
-
--- Read buffer
-inst_DMA_READ_FIFO: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> 10,
-		data_width			=> DATA_WIDTH,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	RST_O,
-		clk			=>	CLK_O,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  read_fifo_din,
-		data_r		=>  read_fifo_dout
-	);
-
-inst_busmaster_sync : entity work.busmaster_sync
-	GENERIC MAP
-	(
-		DATA_WIDTH					=> DATA_WIDTH,
-		FIFO_DEPTH					=> 4
-	)
-	PORT MAP
-	(
-		-- System signals
-		rst					=> RST_O,
-		clk					=> CLK_O,
-
-		cmd_cycle_finished	=> bus_cmd_cycle_finished,
-		cmd_cycle_en		=> bus_cmd_cycle_en,
-		
-		cmd_rdy				=> bus_cmd_rdy,
-		cmd_we				=> bus_cmd_we,
-		cmd_in				=> bus_cmd,
-		
-		din_rdy				=> bus_din_rdy,
-		din_we				=> bus_din_vld,
-		din					=> bus_din,
-
-		dout				=> bus_dout,
-		dout_vld			=> bus_dout_vld,
-		dout_re				=> bus_dout_re,
-
-		-- JBUS Master signals
-		CYC_O				=> CYC_O,
-		STB_O				=> STB_O,
-		WE_O				=> WE_O,
-		SEL_O				=> SEL_O,
-		ACK_I				=> ACK_I,
-		SRDY_I				=> SRDY_I,
-		MRDY_O				=> MRDY_O,
-		ADDR_O				=> ADDR_O,
-		MDAT_I				=> MDAT_I,
-		MDAT_O				=> MDAT_O
-	);
-
-rdy_GEN: process
-	begin
---		wait for 3*CLK_PERIOD/2;
-		wait until rising_edge(CLK_O);
-		rdy <= not rdy;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
--- Slave
-	SRDY_I	<= CYC_O;
-	
-	bus_dout_re			<= '1' when dma_write_source = DATA_GEN else not read_fifo_full;
-	bus_din_vld			<= dma_active(DMA_CH_WRITE) when dma_write_source = DATA_GEN else (dma_active(DMA_CH_WRITE) and not read_fifo_empty);
-	bus_din				<= data_gen_reg when dma_write_source = DATA_GEN else read_fifo_dout;
-	data_gen_reg_inc	<= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = DATA_GEN else '0';
-	read_fifo_re		<= (bus_din_rdy and dma_active(DMA_CH_WRITE)) when dma_write_source = READ_FIFO else '0';
-	read_fifo_we		<= bus_dout_vld;
-	read_fifo_din		<= bus_dout;
-	
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				data_gen_reg <= X"BEEF_0000";
-			elsif data_gen_reg_inc = '1' then
-				data_gen_reg <= data_gen_reg + X"0000_0004";
-			end if;
-		end if;
-	end process;
-				
-
-	process(CLK_O)
-	variable res: unsigned(63 downto 0);
-	variable ram_data : unsigned(63 downto 0);
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-			else
-				ACK_I	<= '0';
-				if (CYC_O and STB_O) = '1' then
-					if WE_O = '0' then
-						ACK_I	<= '1';
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-						if ADDR_O(2) = '0' then
-							res			:= ram_data;
-						else
-							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
-						end if;
-					else -- WE=1
-						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
-					--	ram_data := (others => '-');
-						if ADDR_O(2) = '0' then
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64;
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(63 downto 32) & ram_data(31 downto 0);
-							end if;
-						else
-							if SEL_O = "11111111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & MDAT_O_64(63 downto 32);
-							elsif SEL_O = "00001111" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= MDAT_O_64(31 downto 0) & ram_data(31 downto 0);
-							elsif SEL_O = "11110000" then
-								ram64(to_integer(ADDR_O(31 downto 3))) <= ram_data(63 downto 32) & MDAT_O_64(63 downto 32);
-							end if;
-						end if;
-					end if;
-				end if;
-				MDAT_I_64	<= res;
-			end if;
-		end if;
-	end process;
-
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				read_reg	<= X"00000000";
-			elsif bus_dout_vld = '1' then
-				read_reg	<= bus_dout;
-			end if;
-		end if;
-	end process;
-	
-	
--- Master
-STIMULUS: process
-
-	procedure dma_wait_xfer_complete(ch : integer) is
-	begin
-	
-		dma_req_complete_ack(ch)	<= '1';
-
-		wait until rising_edge(CLK_O) and dma_req_complete(ch) = '1';
-		dma_req_complete_ack(ch)	<= '0';
-
-	end procedure dma_wait_xfer_complete;
-
-	procedure dma_request(ch : integer; addr_start, num_xfers : unsigned) is
-	begin
-	
-		dma_req_addr_auto_inc(ch)	<= '1';
-		dma_req_addr(ch)			<= addr_start;
-		dma_req_num_xfers(ch)		<= num_xfers;
-
-		dma_req_en(ch)				<= '1';
-
-		wait until rising_edge(CLK_O) and dma_req_rdy(ch) = '1';
-		dma_req_en(ch)			<= '0';
-
-	end procedure dma_request;
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		RST_O <= '0';
-		wait for 60*CLK_PERIOD;
-		wait until rising_edge(CLK_O);
-		state <= IDLE;
-
-		dma_request(DMA_CH_WRITE, X"00000000", X"00000040");
---		dma_wait_xfer_complete(DMA_CH_WRITE);
-		dma_request(DMA_CH_READ, X"00000000", X"00000040");
-		dma_wait_xfer_complete(DMA_CH_READ);
-		dma_write_source	<= READ_FIFO;
-		dma_request(DMA_CH_WRITE, X"00000100", X"00000040");
---		dma_wait_xfer_complete(DMA_CH_WRITE);
-		
-		state <= IDLE;
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/PCK_FIO-1.16/PCK_FIO.html b/lib/PCK_FIO-1.16/PCK_FIO.html
deleted file mode 100644
index 8b8c8c5..0000000
--- a/lib/PCK_FIO-1.16/PCK_FIO.html
+++ /dev/null
@@ -1,297 +0,0 @@
-<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
-<html>
-<head>
-   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
-   <meta name="GENERATOR" content="Mozilla/4.5 [en] (X11; I; SunOS 5.7 sun4u) [Netscape]">
-   <title>VHDL package for formatted file output</title>
-<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
-</head>
-<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
-
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_name_0"></a>Name</h1>
-<b>PCK_FIO</b> - VHDL package for&nbsp; formatted file output
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-Contents</h1>
-<a href="#PCK_FIO_usage_0">Usage</a>
-<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
-<br><a href="#PCK_FIO_format_0">Format specifiers</a>
-<br><a href="#PCK_FIO_special_0">Special characters</a>
-<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
-<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
-<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
-<br><a href="#PCK_FIO_test_0">Test bench</a>
-<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
-<br><a href="#PCK_FIO_author_0">Author</a>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
-PCK_FIO is a VHDL package that defines&nbsp; <tt>fprint, </tt>a function
-for formatted file output.
-<p>After installing the package you can call <tt>fprint</tt> as follows:
-<pre>&nbsp; fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
-where F is the filehandle and L is the line variable.
-<p>The argument Format is the format string, which consists of ``normal''
-substrings which are copied verbatim, and format specifiers, starting with
-<tt>'%'</tt>.
-A typical format string looks as follows:
-<pre>&nbsp;&nbsp; "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
-The remaining arguments are the expressions whose results you want to write
-to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
-32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
-function exists. String expressions can also be called directly.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
-The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
-return a tagged string representation that is meaningful to format specifiers.
-Here are some examples:
-<pre>&nbsp; fo (signed'("1100"))&nbsp;&nbsp; returns "S:1100"&nbsp;
-&nbsp; fo (unsigned'("1100")) returns "U:1100"&nbsp;
-&nbsp; fo (TRUE)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; returns "L:T"
-&nbsp; fo (127)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; returns "I:127"</pre>
-The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
-<p>The <tt>fo</tt> function is currently overloaded as follows:
-<pre>&nbsp; function fo (Arg: unsigned)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: signed)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: std_logic_vector)&nbsp; return string;
-&nbsp; function fo (Arg: std_ulogic_vector) return string;
-&nbsp; function fo (Arg: bit_vector)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: integer)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: std_ulogic)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: bit)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: boolean)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;&nbsp;
-&nbsp; function fo (Arg: character)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: string)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: time)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;</pre>
-
-<pre>
-<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
-
-<h1>
-<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
-The general format of a format specifier is:
-<pre>&nbsp;&nbsp; %[-][n]c</pre>
-The optional <b>-</b> sign specifies left justified output; default is
-right justified.
-<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
-<tt>fprint</tt>
-does something reasonable.
-<p><b>c</b> is the conversion specifier. Currently the following conversion
-specifiers are supported:
-<dl COMPACT>
-<dt>
-<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
-
-<dd>
-reasonable output format (inspired by Synopsys VSS)</dd>
-
-<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
-unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
-
-<dt>
-<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
-
-<dd>
-bit-oriented output</dd>
-
-<dt>
-<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
-
-<dd>
-decimal output</dd>
-
-<dt>
-<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
-
-<dd>
-string output (e.g. in combination with 'IMAGE for enum types)</dd>
-
-<dt>
-<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
-
-<dd>
-``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
-
-<dt>
-<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
-
-<dd>
-Iteration operator, used as follows:</dd>
-
-<dd>
-<tt>%n{&lt;format-string>}</tt></dd>
-
-<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
-can be nested.</dl>
-
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
-To print a double-quote,&nbsp; use <tt>'""'</tt> in the format string (VHDL
-convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
-escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
-from being interpreted as opening and closing brackets in iteration strings,
-escape them with <tt>'\'</tt>.
-<p>A newline is specified in the format string by <tt>'\n'</tt>.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
-The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
-commands. As in plain VHDL, nothing will be written to the output file
-until a <tt>writeline</tt> is given. Therefore, don't forget to include
-<tt>'\n'</tt>
-commands in the format string, or it ``will not work''.
-<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
-This calls the VHDL <tt>write</tt> for integers. If you specify a field
-width that is too small, the field will automatically be expanded. If you
-use <b>%r</b> for integers, the field is not expanded automatically, which
-means that some digits are simply thrown away. This may sometimes be useful
-but it is also dangerous. Look at the test bench output for differences
-between <b>%d</b> and <b>%r</b> output.
-<p>When using the <b>%d</b> format specifier, the VHDL constraints for
-the allowed integer range apply.
-<p>In VHDL, signed/unsigned types have been standardized only relatively
-recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
-has caused (and is causing) portability issues. The most popular non-standard
-package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
-Synopsys. PCK_FIO has been developed with this latter package, and still
-refers to this package by default. However, PCK_FIO&nbsp; works with
-<tt>IEEE.numeric_std</tt>
-as well. To use <tt>IEEE.numeric_std</tt>, replace the reference to <tt>IEEE.std_logic_arith</tt>
-in the source code.&nbsp; This needs to be done consistently in a design
-database (e.g. in the PCK_FIO test bench as well).
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
-The obvious application for <tt>fprint</tt> is in test benches, to produce
-output files that trace the simulation behavior.
-<p>Another interesting application for <tt>fprint</tt> is to produce info,
-warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
-is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
-statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
-<p>An advanced usage is the generation of test vectors in a specific format.
-Instead of using the <tt>fo </tt>functions, you can write your own set
-of functions that return the symbols of a specific test format in a way
-that is understandable to the <tt>fprint</tt> format specifiers. As an
-example, when a high output value should be represented using the symbol
-'H' it suffices to write a conversion function that returns "B:H" and call
-it in combination with the <b>%b</b> format specifier.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
-Prefix and postfix strings for bit-oriented and hex-oriented output are
-parameterizable in the packages to accommodate different output styles.
-The settings in the distribution are such that hex output is indicated
-by the prefix '0x', while&nbsp; bit output prefix and postfix are empty
-strings.
-<p>You can adapt the output style by modifying the following constants
-in the package header:
-<p>&nbsp;&nbsp;<tt> -- prefix string for hex output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "X"""</tt>
-<br><tt>&nbsp; -- Verilog style: "h'"</tt>
-<br><tt>&nbsp; -- C style:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "0x"</tt>
-<br><tt>&nbsp; constant FIO_h_PRE:&nbsp; string := "0x";</tt>
-<p><tt>&nbsp; -- postfix string for hex output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; """"</tt>
-<br><tt>&nbsp; constant FIO_h_POST: string := "";</tt>
-<p><tt>&nbsp; -- prefix string for bit vector output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "B"""</tt>
-<br><tt>&nbsp; -- Verilog style: "b'"</tt>
-<br><tt>&nbsp; constant FIO_bv_PRE:&nbsp; string := "";</tt>
-<p><tt>&nbsp; -- postfix string for bit vector output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; """"</tt>
-<br><tt>&nbsp; constant FIO_bv_POST: string := "";</tt>
-<p><tt>&nbsp; -- prefix string for bit output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "'"</tt>
-<br><tt>&nbsp; -- Verilog style: "b'"</tt>
-<br><tt>&nbsp; constant FIO_b_PRE:&nbsp; string := "";</tt>
-<p><tt>&nbsp; -- postfix string for bit output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "'"</tt>
-<br><tt>&nbsp; constant FIO_b_POST: string := "";</tt>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
-Included in the distribution is a file <tt>TB_PCK_FIO.vhd</tt> with a test
-bench for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
-the expected output. If you run the test bench it should produce the file
-<tt>PCK_FIO.out</tt>
-that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
-should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
-<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
-and what it produces.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
-This VHDL package is an implementation of a flexible concept. It is likely
-to be extended and modified in the future. Backward compatibility is not
-guaranteed. Therefore, it is not recommended to give this package the status
-of a company-wide standard package (or even worse, a VHDL standard package).
-Rather, it should be linked with a particular project (and it can be regarded
-as a standard package within that project).
-<p>PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some
-simulators/versions have problems with the package. The following is an
-overview of currently known issues:
-<br>&nbsp;
-<center><table BORDER COLS=2 WIDTH="80%" >
-<tr>
-<th>Simulator</th>
-
-<th>PCK_FIO handling</th>
-</tr>
-
-<tr>
-<td>Synopsys VSS 3.5 and earlier</td>
-
-<td>Incorrect (all zero) output in compiled mode</td>
-</tr>
-
-<tr>
-<td>Synopsys VSS 97.01</td>
-
-<td>OK</td>
-</tr>
-
-<tr>
-<td>Mentor quickhdl</td>
-
-<td>OK</td>
-</tr>
-
-<tr>
-<td>Modeltech modelsim</td>
-
-<td>OK</td>
-</tr>
-
-<tr>
-<td>Cadence Leapfrog</td>
-
-<td>Should work with 4.4.1
-<br>Mysterious problems have been reported - please run the test bench
-and report problems</td>
-</tr>
-
-<caption ALIGN=BOTTOM>PCK_FIO and various simulators/versions</caption>
-</table></center>
-
-<p>Although the package name suggests file IO, it only does file output.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_author_0"></a>Author</h1>
-<a href="mailto:jand@easics.be">Jan Decaluwe</a>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-</body>
-</html>
diff --git a/lib/PCK_FIO-1.16/PCK_FIO.out.gold b/lib/PCK_FIO-1.16/PCK_FIO.out.gold
deleted file mode 100644
index dcd183e..0000000
--- a/lib/PCK_FIO-1.16/PCK_FIO.out.gold
+++ /dev/null
@@ -1,206 +0,0 @@
-PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO
------------------------------------------
-
-This is the result of running the PCK_FIO testbench.
-This file should be compared with PCK_FIO.out.gold, which is
-the reference output. Any difference indicates a portability
-issue or a simulator non-compliance or bug.
-
-
---------------------
--- Basic features --
---------------------
-
--- First some auxiliary declarations
-> file     RESULT:    text is out "PCK_FIO.out";
-> variable L:         line;
-> variable BoolTrue:  boolean := TRUE;
-> variable BoolFalse: boolean := FALSE;
-> variable IntPos:    integer := 5678;
-> variable BigIntPos: integer := 12345678;
-> variable IntNeg:    integer := -8765;
-> variable BigIntNeg: integer := -87654321;
-> variable Uns:       unsigned(6 downto 0) := unsigned'("1010010");
-> variable Unk:       unsigned(6 downto 0) := unsigned'("1X10Z10");
-> variable Std:       std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
-> variable SigPos:    signed(6 downto 0) := signed'("0010010");
-> variable SigNeg:    signed(6 downto 0) := signed'("1010010");
-> variable BitX:      std_logic := 'X';
-> variable Bit1:      std_logic := '1';
-> variable Bit0:      std_logic := '0';
-
-
--- fprint call with no arguments
-> fprint(RESULT, L, "No arguments.\n);"
-No arguments.
-
--- Special characters need to be escaped
-> fprint(RESULT, L, "Special characters: \% \\ " \n");
-Special characters: % \ " 
-
--- Various format specifiers interprete the same object differently
-> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);"
->                   fo(Uns), fo(Uns), fo(Uns), fo(Uns)
->       );
-Format specifiers: 0x52 82 1010010 U:1010010
-
--- Format string can be shortened by using the iteration specifier
-> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);"
->                   fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
->       );
-Iteration specifier: 0x52 0x12 0x52 0x12 
-
-------------------------------------
--- Support for bit-oriented types --
-------------------------------------
-
--- Reasonable format
-> fprint(RESULT, L, "Reasonable format: %9{%r }\n",
->                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
->                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) 
->       );
-Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F 
-
--- Decimal format
-> fprint(RESULT, L, "Decimal format: %7{%d }\n",
->                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
->                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) 
->       );
-Decimal format: 18 82 18 -46 -1 1 -1 1 0 
-
--- Bit format
-> fprint(RESULT, L, "Bit format: %7{%b }\n",
->                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
->                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) 
->       );
-Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0 
-
-
--- Alignment
--- Template of the call: (<fs> stands for the format specifier)
-
-> fprint(RESULT, L, "Bitvectors with <fs>:    %4{<fs>|}\n",
->                  fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)
->       );
-
--- Results of the call with various format specifiers
-
-Bitvectors with %1r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %2r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %3r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %4r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %5r:   0x52| 0x12| 0x12| 0x52| 
-Bitvectors with %6r:    0x52|  0x12|  0x12|  0x52| 
-Bitvectors with %7r:     0x52|   0x12|   0x12|   0x52| 
-Bitvectors with %8r:      0x52|    0x12|    0x12|    0x52| 
-Bitvectors with %9r:       0x52|     0x12|     0x12|     0x52| 
-
-Bitvectors with %-1r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %-2r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %-3r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %-4r:  0x52|0x12|0x12|0x52| 
-Bitvectors with %-5r:  0x52 |0x12 |0x12 |0x52 | 
-Bitvectors with %-6r:  0x52  |0x12  |0x12  |0x52  | 
-Bitvectors with %-7r:  0x52   |0x12   |0x12   |0x52   | 
-Bitvectors with %-8r:  0x52    |0x12    |0x12    |0x52    | 
-Bitvectors with %-9r:  0x52     |0x12     |0x12     |0x52     | 
-
-Bitvectors with %1d:  82|18|18|-46| 
-Bitvectors with %2d:  82|18|18|-46| 
-Bitvectors with %3d:   82| 18| 18|-46| 
-Bitvectors with %4d:    82|  18|  18| -46| 
-Bitvectors with %5d:     82|   18|   18|  -46| 
-Bitvectors with %6d:      82|    18|    18|   -46| 
-Bitvectors with %7d:       82|     18|     18|    -46| 
-Bitvectors with %8d:        82|      18|      18|     -46| 
-Bitvectors with %9d:         82|       18|       18|      -46| 
-
-Bitvectors with %-1d:  82|18|18|-46| 
-Bitvectors with %-2d:  82|18|18|-46| 
-Bitvectors with %-3d:  82 |18 |18 |-46| 
-Bitvectors with %-4d:  82  |18  |18  |-46 | 
-Bitvectors with %-5d:  82   |18   |18   |-46  | 
-Bitvectors with %-6d:  82    |18    |18    |-46   | 
-Bitvectors with %-7d:  82     |18     |18     |-46    | 
-Bitvectors with %-8d:  82      |18      |18      |-46     | 
-Bitvectors with %-9d:  82       |18       |18       |-46      | 
-
-
--------------------------------
--- Support for integer types --
--------------------------------
-
-
--- Template of the call: (<fs> stands for the format specifier)
-
-> fprint(RESULT, L, "Integers with <fs>:    %4{<fs>|}\n",
->                  fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
->       );
-
--- Results of the call with various format specifiers
-
-Integers with %5d:     5678|-8765|12345678|-87654321| 
-Integers with %6d:      5678| -8765|12345678|-87654321| 
-Integers with %7d:       5678|  -8765|12345678|-87654321| 
-Integers with %8d:        5678|   -8765|12345678|-87654321| 
-Integers with %9d:         5678|    -8765| 12345678|-87654321| 
-Integers with %10d:         5678|     -8765|  12345678| -87654321| 
-
-Integers with %-5d:    5678 |-8765|12345678|-87654321| 
-Integers with %-6d:    5678  |-8765 |12345678|-87654321| 
-Integers with %-7d:    5678   |-8765  |12345678|-87654321| 
-Integers with %-8d:    5678    |-8765   |12345678|-87654321| 
-Integers with %-9d:    5678     |-8765    |12345678 |-87654321| 
-Integers with %-10d:   5678      |-8765     |12345678  |-87654321 | 
-
-Integers with %5r:     5678|-8765| 5678|-4321| 
-Integers with %6r:      5678|- 8765| 45678|-54321| 
-Integers with %7r:       5678|-  8765| 345678|-654321| 
-Integers with %8r:        5678|-   8765| 2345678|-7654321| 
-Integers with %9r:         5678|-    8765| 12345678|-87654321| 
-Integers with %10r:         5678|-     8765|  12345678|- 87654321| 
-
-Integers with %-5r:     5678|-8765| 1234|-8765| 
-Integers with %-6r:     5678 |-8765 | 12345|-87654| 
-Integers with %-7r:     5678  |-8765  | 123456|-876543| 
-Integers with %-8r:     5678   |-8765   | 1234567|-8765432| 
-Integers with %-9r:     5678    |-8765    | 12345678|-87654321| 
-Integers with %-10r:    5678     |-8765     | 12345678 |-87654321 | 
-
-
-----------------------
--- Support for time --
-----------------------
--- For portability reasons, time is converted 
--- into an integer value (of nanoseconds)
-> wait for 648 ns
-> fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-The time is now 648 ns
-
-----------------------------------------
--- Erroneous calls and error messages --
-----------------------------------------
-
--- Less arguments than formats specifiers
-> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-82 18 
-** Warning: FIO_PrintLastValue: Format specifier beyond last argument
-**  in format string: "%d %d %d %d \n"
-**                     ------^
-
--- Unsupported format specifier
-> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-0x52 
-** Warning: FIO_PrintArg: Unexpected format specifier 'v'
-**   in format string: "%r %v %r %r\n"
-**                      ----^
-**   Assuming 'q' to proceed: V:0010010 0x52 0x12
-
-
-----------------------------------------
--- Things you wouldn't expect to work --
-----------------------------------------
-
--- Nested iteration
-> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>>
diff --git a/lib/PCK_FIO-1.16/PCK_FIO.vhd b/lib/PCK_FIO-1.16/PCK_FIO.vhd
deleted file mode 100644
index e635721..0000000
--- a/lib/PCK_FIO-1.16/PCK_FIO.vhd
+++ /dev/null
@@ -1,919 +0,0 @@
----- File: PCK_FIO.vhd
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 1999 Easics NV 
-----
----- This program is free software; you can redistribute it and/or modify
----- it under the terms of the GNU General Public License as published by
----- the Free Software Foundation; either version 1, or (at your option)
----- any later version.
-----
----- This program is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
----- GNU General Public License for more details.
-----
----- You should have received a copy of the GNU General Public License
----- along with this program; if not, write to the Free Software
----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----- 
----- For suggestions, bug reports, enhancement requests, and info about  
----- our design services, you can contact us at the following address: 
-----   Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----   tel.: +32 16 395 600   fax : +32 16 395 619 
-----   e-mail: jand@easics.be (Jan Decaluwe)
-----
-----
----- Revision history:
-----
----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $
----- $Revision: 1.2 $
----- $Log: not supported by cvs2svn $
----- Revision 1.1  2008/08/23 08:20:28  Jens
----- Initial import
-----
----- Revision 1.16  1999/04/21 08:28:46  jand
----- Tested with IEEE.numeric_std
----- Small patch for Leapfrog
-----
----- Revision 1.14  1997/07/14 10:16:04  jand
----- prefix/postfix for bits/bitvectors set to empty strings by default
-----
----- Revision 1.13  1997/07/11  17:42:57  jand
----- Corrected Easics address
-----
----- Revision 1.12  1997/07/11  17:38:49  jand
----- Improved prefix/postfix support
-----
----- Revision 1.11  1995/11/15  13:46:02  jand
----- Catched integer'low value in fo for integers
-----
----- Revision 1.10  1995/08/11  16:42:26  jand
----- Reimplemented FIO_FormatExpand as a procedure in an attempt to
----- avoid memory leakage problems in VSS
-----
----- Revision 1.9  1995/08/09  13:47:51  jand
----- Removed array of line trick in fprint for less memory, less
----- CPU time, and more conservatism in general
----- Rearranged FIO_PrintValue call so that fprint remains concise
-----
----- Revision 1.8  1995/08/09  10:32:27  jand
----- Removed fprint_flat to have a single call level
----- Added explicit deallocators of line variables (has strong influence
----- on memory usage in VSS - and possibly CPU time)
----- Redefined 'fo' for type time to make it more portable
-----
----- Revision 1.7  1995/08/07  08:56:04  jand
----- Improved conciseness of fprint argument handling through array of line type
-----
----- Revision 1.6  1995/08/04  18:19:13  jand
----- Increase # arguments from 16 to 32
----- Corrected bug within fprint 's call to Arg16
----- Added support for bit format specifier 'b'
-----
----- Revision 1.5  1995/08/02  10:22:37  jand
----- Release 1.1 under GNU
-----
----- Revision 1.4  1995/08/01  11:15:52  jand
----- Added escaping during iteration string read
-----
----- Revision 1.3  1995/08/01  08:23:47  jand
----- Many improvements in robustness, conciseness and coding style
-----
----- Revision 1.2  1995/07/30  16:15:43  jand
----- Improved robustness for release to the world
-----
----- Revision 1.1  1995/07/30  14:21:30  jand
----- Initial revision
-----
-
-use STD.TEXTIO.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
-use IEEE.std_logic_arith.all; -- the Synopsys one
--- use IEEE.numeric_std.all;
-
-package PCK_FIO is
-
-  -- prefix string for hex output
-  -- VHDL style:    "X"""
-  -- Verilog style: "h'"
-  -- C style:       "0x"
-  constant FIO_h_PRE:  string := "";
-
-  -- postfix string for hex output
-  -- VHDL style:    """"
-  constant FIO_h_POST: string := "";
-
-  -- prefix string for bit vector output
-  -- VHDL style:    "B"""
-  -- Verilog style: "b'"
-  constant FIO_bv_PRE:  string := "";
-
-  -- postfix string for bit vector output
-  -- VHDL style:    """"
-  constant FIO_bv_POST: string := "";
-
-  -- prefix string for bit output
-  -- VHDL style:    "'"
-  -- Verilog style: "b'"
-  constant FIO_b_PRE:  string := "";
-
-  -- postfix string for bit output
-  -- VHDL style:    "'"
-  constant FIO_b_POST: string := "";
-
-  -- digit width for the string representation of integers
-  constant FIO_d_WIDTH: integer := 10; 
-
-  -- bit width for the string representation of integers
-  constant FIO_b_WIDTH: integer := 32;
-
-  -- definition of the NIL string (default value for fprint arguments)
-  -- fprint stops consuming arguments at the first NIL argument 
-  constant FIO_NIL: string := "\";
-
-  procedure fprint 
-	     (F:       out   text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     );
-
-  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive);
-
-end PCK_FIO;
-
-
-package body PCK_FIO is
-
-
-  --------------------------
-  -- FIO Warnings support --
-  --------------------------
-
-  procedure FIO_Warning_Fsbla (F:       out   text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
-        	  "Format specifier beyond last argument\n"); 
-    fprint (F, L, "**  in format string: ""%s""\n", Format); 
-    fprint (F, L, "**                     ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n"); 
-  end FIO_Warning_Fsbla;
-
-  procedure FIO_Warning_Ufs   (F:       out   text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive;
-			       Char:    in    character) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintArg: " &
-		  "Unexpected format specifier '%r'\n",
-		  fo(Char));
-    fprint (F, L, "**   in format string: ""%s""\n", Format) ; 
-    fprint (F, L, "**                      ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n**   Assuming 'q' to proceed: "); 
-  end FIO_Warning_Ufs;
-
-
-  ----------------------------------
-  -- bit conversion support --
-  ----------------------------------
-
-  type T_bit_map is array(bit) of character;  
-  
-  constant C_BIT_MAP: T_bit_map 
-             := ('0', '1');
-
-  ----------------------------------
-  -- std_logic conversion support --
-  ----------------------------------
-
-  type T_std_logic_map is array(std_ulogic) of character;  
-  
-  constant C_STD_LOGIC_MAP: T_std_logic_map 
-             := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-
-  ------------------------------
-  -- Digit conversion support --  
-  ------------------------------
-
-  -- types & constants
-
-  subtype S_digit_chars is character range '0' to '9';
-  subtype S_digits      is integer   range  0  to  9 ; 
-
-  type T_digit_chars_map is array(S_digit_chars) of S_digits; 
-
-  constant C_DIGIT_CHARS_MAP: T_digit_chars_map 
-    := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
-
-  type T_digits_map is array(S_digits) of S_digit_chars; 
-
-  constant C_DIGITS_MAP: T_digits_map  
-    := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
-
-
-  --------------------------------
-  -- Decimal conversion support --
-  --------------------------------
-
-  function U_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0;
-  begin
-    for i in Argument'range loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(-1); 
-      end case;
-    end loop;
-    return (Result);
-  end U_To_d;
-
-  function S_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0; 
-  begin
-    case Argument(Argument'left) is 
-      when '1' =>    Result := - 2**(Argument'left-1);   
-      when '0' =>    Result := 0;
-      when others => return (integer'low); 
-    end case;
-    for i in Argument'left-1 downto 1 loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(integer'low); 
-      end case;
-    end loop; 
-    return (Result);
-  end S_To_d;
-
-  function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
-    constant Sign: character := Arg(1);
-    constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
-    variable Char: character;
-    variable Result: integer := 0;
-  begin
-    Result := 0;
-    for i in Value'range loop
-      Result := Result * 10;
-      Char := Value(i);
-      if (Char /= ' ') then
-        Result := Result + C_DIGIT_CHARS_MAP(Char);
-      end if;
-    end loop;
-    case Sign is when '-'    => return(-Result);
-		 when others => return(Result);
-    end case;
-  end I_To_d;
-
-  function B_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "1"    => return(1);
-                when "0"    => return(0);
-                when others => return(-1);
-    end case;
-  end B_To_d;
-
-  function L_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "T"    => return(1);
-                when others => return(0);
-    end case;
-  end L_To_d;
-
-
-
-  ----------------------------
-  -- Hex conversion support --
-  ----------------------------
-
-  -- Constants & types
-
-  constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
-
-  -- Function to return Hex index of a nibble  
-
-  function U_To_h_Index(Arg: string(4 downto 1)) return integer is
-    variable Index: integer := 0;
-  begin
-    for i in Arg'range loop
-      case Arg(i) is when '1'    => Index := 2**(i-1) + Index;   
-	             when '0'    => null;
-                     when others => return (17); 
-      end case;
-    end loop;
-    return (Index+1);
-  end U_To_h_Index;
-
-  -- Hex conversion  
-
-  function U_To_h (Arg: string) return string is
-    variable Result: string((Arg'length-1)/4 +1 downto 1);
-    variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); 
-  begin
-    ExtArg(Arg'length downto 1) := Arg;
-    for i in Result'range loop
-      Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));     
-    end loop;
-    return (FIO_h_PRE & Result & FIO_h_POST);
-  end U_To_h;
-
-
-
-  ----------------------------
-  -- Bit conversion support --
-  ----------------------------
-
-  function L_To_b (Arg: string(1 to 1)) return string is
-    variable Result: string(1 to 1); 
-  begin
-    case Arg is when "T"    => Result := "1";
-                when others => Result := "0";
-    end case;
-    return(FIO_b_PRE & Result & FIO_b_POST);
-  end L_To_b;
-
-
-  function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
-	           Justified: side;
-		   Width: integer) return string is
-
-    variable IntValue: integer := I_To_d(Arg);
-    variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-    constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
-    variable BitWidth: integer range 0 to FIO_b_WIDTH;
-    variable MsPos: integer range 1 to BitValue'length; 
-    variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); 
-
-  begin
-
-    if (IntValue < 0) then
-      Sign := '-';
-      IntValue := -IntValue;
-    end if;
-
-    for i in BitValue'reverse_range loop 
-      BitValue(i) := C_DIGITS_MAP(IntValue mod 2); 
-      IntValue := IntValue / 2;
-      exit when (IntValue = 0);
-    end loop;
-
-    BitValueExtended := BitValue & Blanks; 
-
-    if (Width = 0) or (Width > FIO_b_WIDTH+1) then
-       BitWidth := FIO_b_WIDTH;   
-    else
-       BitWidth := Width-1;   
-    end if;
-
-    if (Justified = RIGHT) then
-      return (FIO_bv_PRE & 
-	      Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & 
-	      FIO_bv_POST);    
-    else
-      for i in BitValue'range loop 
-        if BitValue(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (FIO_bv_PRE & 
- 	      Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & 
-	      FIO_bv_POST);
-    end if;
-
-  end I_To_b;
-
-
-  -----------------------------------
-  -- Reasonable conversion support --
-  -----------------------------------
-
-  function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); 
-	           Justified: side;
-		   Width: integer) return string is
-    constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
-    constant Sign: character := Arg(1);
-    constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
-    variable IntWidth: integer range 0 to FIO_d_WIDTH;
-    variable MsPos: integer range 1 to Value'length; 
-    variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; 
-  begin
-    if (Width = 0) or (Width > FIO_d_WIDTH+1) then
-       IntWidth := FIO_d_WIDTH;   
-    else
-       IntWidth := Width-1;   
-    end if;
-    if (Justified = RIGHT) then
-      return (Sign & Value(Value'length-IntWidth+1 to Value'length));    
-    else
-      for i in Value'range loop 
-        if Value(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
-    end if;
-  end I_To_r;
-
-
-  -------------------------------------------
-  -- Reasonable output conversion function --
-  -------------------------------------------
-
-  function ReasonableOutput (Arg: string;
-			     Justified: side;
-		             Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return U_To_h(Value);  
-      when "I:" =>
-	return I_To_r(Value, Justified, Width);
-      when "B:" | "L:" | "C:" =>
-        return Value;     
-      when others => 
-	return Argument;  
-    end case;
-
-  end ReasonableOutput;
-
-
-  ------------------------------------
-  -- Bit output conversion function --
-  ------------------------------------
-
-  function BitOutput (Arg: string;
-		      Justified: side;
-		      Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return (FIO_bv_PRE & Value & FIO_bv_POST);  
-      when "B:" =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-        return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);  
-      when "I:" =>
-	return I_To_b(Value, Justified, Width);
-      when "L:"  =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-	return L_To_b(Value(1 to 1));
-      when others => 
-	return Argument;  
-    end case;
-
-  end BitOutput;
-
-
-  -------------------------------------------
-  -- Decimal output conversion function --
-  -------------------------------------------
-
-  function DecimalOutput (Arg: string) return integer is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:"| "V:" =>
-	return U_To_d(Value);
-      when "S:" =>
-	return S_To_d(Value);
-      when "I:" =>
-	return I_To_d(Value);
-      when "B:" =>
-	return B_To_d(Value);
-      when "L:" =>
-	return L_To_d(Value);
-      when others => 
-	return integer'low;  
-    end case;
-
-  end DecimalOutput;
-
-
-  ----------------------------
-  -- Atomic print functions --  
-  ----------------------------
-
-  function FIO_EOS (Format: in string;
-		    Pointer: in integer) 
-	   return boolean is 
-  begin
-    return (Pointer > Format'length);
-  end FIO_EOS; 
-
-
-  -- Atomic value print function
-
-  procedure FIO_PrintValue (F:       out   text;
-			    L:       inout line; 
-			    Format:  in    string; 
-			    Pointer: inout integer;
-			    Last:    in    boolean := FALSE) is
-    variable Char: character;  
-  begin
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '\' =>
-	  Pointer := Pointer + 1;
-	  exit when (FIO_EOS(Format, Pointer));
-          Char := Format(Pointer);
-	  case Char is when 'n'    => writeline(F, L); 
-	               when others => write(L, Char);
-	  end case;
-	when '%' => 
-	  if Last then
-	    FIO_Warning_Fsbla(F, L, Format, Pointer);
-	  end if;
-	  Pointer := Pointer + 1; 
-	  exit;
-	when others  => 
-	  write(L, char); 
-      end case;
-      Pointer := Pointer + 1;
-    end loop;
-  end FIO_PrintValue; 
-
-
-  ---- Atomic argument print function
-
-  procedure FIO_PrintArg (F:       out   text;
-			  L:       inout line; 
-			  Format:  in    string; 
-			  Pointer: inout integer;
-			  Arg:     in    string) is
-    variable Char: character;  
-    variable Justified: side;  
-    variable Width: integer;
-  begin
-
-    FIO_PrintValue(F, L, Format, Pointer);
-
-    Justified := RIGHT;  
-    Width := 0; 
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '-' =>
-	  Justified := LEFT;  
-          Pointer := Pointer + 1;
-	when '0' to '9' =>
-	  Width := Width*10 + C_DIGIT_CHARS_MAP(Char); 
-          Pointer := Pointer + 1;
-	when 'r' => 
-	  write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'b' => 
-	  write(L, BitOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'd' => 
-	  write(L, DecimalOutput(Arg), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'q' | 's' => 
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when others  => 
-          FIO_Warning_Ufs(F, L, Format, Pointer, Char);
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-      end case;
-    end loop;
-  end FIO_PrintArg; 
-
-
-  -----------------------------------------------------
-  -- The format string iteration expansion procedure --
-  -----------------------------------------------------
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive) is
-
-    variable Pointer: positive := StartPointer;
-    variable TokenStart: positive;
-    variable IterStringStart: positive;
-    variable IterStringEnd: positive;
-    variable IterCount: natural;
-    variable OpenBrackets: natural;
-    variable L: line;
-
-  begin
-
-    FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop 
-
-      case Format(Pointer) is
-
-        -- look for format specifier
-	when '%' => 
-
-          -- initialize iteration token search 
-	  TokenStart := Pointer;
-          IterCount := 0; 
-	  Pointer := Pointer + 1;
-
-          -- start iteration token search
-	  TOKEN_READ: while not FIO_EOS(Format, Pointer) loop 
-             
-	    case Format(Pointer) is
-                
-              -- read iteration counter
-	      when '0' to '9' =>
-		IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); 
-                Pointer := Pointer + 1;
-               
-              -- expect open bracket
-	      when '{' => 
-
-		-- initialize iteration string read
-		OpenBrackets := 1;
-		IterStringStart := Pointer + 1;
-                Pointer := Pointer + 1;
-		-- quit prematurely when iteration count is 0
-		next FORMAT_SEARCH when (IterCount = 0);
-
-                -- start iteration string read
-	        ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop 
-
-	          case Format(Pointer) is
-                    -- keep track of open brackets
-		    when '{' => 
-		      OpenBrackets := OpenBrackets + 1;
-	              Pointer := Pointer + 1;
-                    -- when closing bracket is found, process iteration string      
-		    when '}' => 
-	 	      OpenBrackets := OpenBrackets - 1;
-		      if (OpenBrackets = 0) then
-			IterStringEnd := Pointer-1;
-			if (TokenStart /= 1) then
-			  write(L, Format(1 to TokenStart-1)); 
-			end if;
-			for i in 1 to IterCount loop
-			  write(L,  Format(IterStringStart to IterStringEnd));
-			end loop;
-			if (IterStringEnd /= Format'length) then
-			  write(L, Format(IterStringEnd+2 to Format'length)); 
-			end if;
-			-- call expansion procedure recursively on expanded format
-			FIO_FormatExpand(FMT, L.all, TokenStart);
-                        deallocate(L);
-                        return; 
-		      end if;
-	              Pointer := Pointer + 1;
-                    -- skip escaped characters
-	            when '\' => 
-	              Pointer := Pointer + 2;
-                    -- read iteration string  
-	            when others => 
-	              Pointer := Pointer + 1;
-
-		  end case; 
-
-		end loop ITER_STRING_READ;
-
-              -- stop iteration token search when no opening bracket found 
-	      when others => 
-                Pointer := Pointer + 1;
-		next FORMAT_SEARCH;
-
-	    end case;
-
-	  end loop TOKEN_READ;
-
-        -- skip escaped characters
-	when '\' => 
-	  Pointer := Pointer + 2;
-
-        -- read other characters
-	when others => 
-          Pointer := Pointer + 1;
-
-      end case;
-
-    end loop FORMAT_SEARCH;
-
-    write(FMT, Format);
-    deallocate(L);
-
-  end FIO_FormatExpand;
-
-
-
-  --------------------------
-  -- The fprint procedure --
-  --------------------------
-
-  procedure fprint 
-	     (F:       out   text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     ) is
-
-    variable Pointer: integer;
-    variable FMT: line;
-		    
-  begin
-
-    Pointer := 1;
-
-    FIO_FormatExpand (FMT, Format, Format'low);
-
-    if (A1  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
-    if (A2  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
-    if (A3  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
-    if (A4  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
-    if (A5  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
-    if (A6  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
-    if (A7  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
-    if (A8  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
-    if (A9  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
-    if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
-    if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
-    if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
-    if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
-    if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
-    if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
-    if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
-    if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
-    if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
-    if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
-    if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
-    if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
-    if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
-    if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
-    if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
-    if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
-    if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
-    if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
-    if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
-    if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
-    if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
-    if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
-    if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-
-    FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
-
-    deallocate(FMT);
-
-  end fprint;
-  
-
-  -------------------------------------------
-  -- Formatted output conversion functions --
-  -------------------------------------------
-
-  function fo (Arg: unsigned) return string is
-    constant Argument: unsigned(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("U:" & Result);
-  end fo;
-
-  function fo (Arg: signed) return string is
-    constant Argument: signed(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("S:" & Result);
-  end fo;
-
-  function fo (Arg: std_logic_vector) return string is
-    constant Argument: std_logic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic_vector) return string is
-    constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: bit_vector) return string is
-    constant Argument: bit_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_BIT_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: integer) return string is
-    variable Argument: integer := Arg;
-    variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-  begin
-    if (Argument < 0) and (Argument /= integer'low) then
-      Sign := '-';
-      Argument := -Argument;
-    end if;
-    for i in Result'reverse_range loop 
-      Result(i) := C_DIGITS_MAP(Argument mod 10); 
-      Argument := Argument / 10;
-      exit when (Argument = 0);
-    end loop;
-    return ("I:" & Sign & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic) return string is
-  begin
-    return ("B:" & C_STD_LOGIC_MAP(Arg));
-  end fo;
-
-  function fo (Arg: bit) return string is
-  begin
-    return ("B:" & C_BIT_MAP(Arg));
-  end fo;
-
-  function fo (Arg: boolean) return string is
-  begin
-    if (ARG = TRUE) then
-      return ("L:T");
-    else 
-      return ("L:F");
-    end if;
-  end fo;
-
-  function fo (Arg: character) return string is
-  begin
-    return ("C:" & Arg);   
-  end fo;
-
-  function fo (Arg: string) return string is
-  begin
-    return Arg;   
-  end fo;
-
-  function fo (Arg: time) return string is
-  begin
-    return fo (integer (Arg / 1 ns));   
-  end fo;
-
-end PCK_FIO;
diff --git a/lib/PCK_FIO-1.16/README b/lib/PCK_FIO-1.16/README
deleted file mode 100644
index 4af4c99..0000000
--- a/lib/PCK_FIO-1.16/README
+++ /dev/null
@@ -1,72 +0,0 @@
-# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
-# $Log: not supported by cvs2svn $
-# Revision 1.3  1999/04/21 08:08:35  jand
-# Tested with IEEE.numeric_std
-# Small patch for Leapfrog
-#
-#
-
-                       PCK_FIO, Version 1.16
-                  Copyright (C) 1995, 1999 Easics NV 
-
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 1999 Easics NV 
-----
----- This program is free software; you can redistribute it and/or modify
----- it under the terms of the GNU General Public License as published by
----- the Free Software Foundation; either version 1, or (at your option)
----- any later version.
-----
----- This program is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
----- GNU General Public License for more details.
-----
----- You should have received a copy of the GNU General Public License
----- along with this program; if not, write to the Free Software
----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----- 
----- For suggestions, bug reports, enhancement requests, and info about  
----- our design services, you can contact us at the following address: 
-----   Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----   tel.: +32 16 395 600   fax : +32 16 395 619 
-----   e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-Contents
---------
-
-This distribution contains the following files:
-
-  PCK_FIO.vhd:         VHDL source of the PCK_FIO package 
-  TB_PCK_FIO.vhd:      VHDL source of the testbench for package PCK_FIO
-  PCK_FIO.out.gold:    Certified test bench output
-  PCK_FIO.html:        Manual for PCK_FIO in html format
-  README:              This file
-
-
-Installation
-------------
-
-To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
-analyze the VHDL file PCK_FIO.vhd into this library.
-
-To install the test bench, analyze TB_PCK_FIO.vhd into the same library.
-
-If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need
-to edit the source code of the package and the test bench and replace the
-package use clause. PCK_FIO works with either of these packages.
-
-To install the documentation, point your web browser to the file PCK_FIO.html
-and bookmark it.
-
-
-Installation check
-------------------
-
-After installing the test bench, you should run it. The corresponding VHDL
-design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
-
-Simulating the test bench should create a file called PCK_FIO.out. This file
-should be identical to PCK_FIO.out.gold. Any difference indicates a portability
-issue or a simulator non-compliance or bug.
diff --git a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd b/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd
deleted file mode 100644
index c64d045..0000000
--- a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd
+++ /dev/null
@@ -1,504 +0,0 @@
----- File: TB_PCK_FIO.vhd
-----
----- TBC_PCK_FIO: a test bench for the PCK_FIO package. 
----- Copyright (C) 1995, 1999 Easics NV 
-----
----- This program is free software; you can redistribute it and/or modify
----- it under the terms of the GNU General Public License as published by
----- the Free Software Foundation; either version 1, or (at your option)
----- any later version.
-----
----- This program is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
----- GNU General Public License for more details.
-----
----- You should have received a copy of the GNU General Public License
----- along with this program; if not, write to the Free Software
----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----- 
----- For suggestions, bug reports, enhancement requests, and info about  
----- our design services, you can contact us at the following address: 
-----   Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----   tel.: +32 16 395 600  fax : +32 16 396 619 
-----   e-mail: jand@easics.be (Jan Decaluwe)
-----
-----
----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $
----- $Revision: 1.1 $
----- $Log: not supported by cvs2svn $
----- Revision 1.7  1999/04/21 08:23:53  jand
----- Tested with IEEE.numeric_std
----- Small patch for Leapfrog
-----
----- Revision 1.3  1998/09/29 10:09:44  vhdl
----- to EASICS_PACKAGES
-----
----- Revision 1.2  1998/09/29 09:17:51  vhdl
----- library EASICS_PACKAGES;
-----
----- Revision 1.1  1998/09/29 09:15:44  vhdl
----- Initial revision
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
-use IEEE.std_logic_arith.all; -- the Synopsys one
--- use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
-  file RESULT:        text is out "PCK_FIO.out"; 
-  variable L:         line;
-  variable Pointer:   integer;
-  variable BoolTrue:  boolean := TRUE;
-  variable BoolFalse: boolean := FALSE;
-  variable IntPos:    integer := 5678; 
-  variable BigIntPos: integer := 12345678; 
-  variable IntNeg:    integer := -8765; 
-  variable BigIntNeg: integer := -87654321; 
-  variable Uns:       unsigned(6 downto 0) := unsigned'("1010010");
-  variable Unk:       unsigned(6 downto 0) := unsigned'("1X10Z10");
-  variable Std:       std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
-  variable SigPos:    signed(6 downto 0) := signed'("0010010");
-  variable SigNeg:    signed(6 downto 0) := signed'("1010010");
-  variable BitX:      std_logic := 'X';
-  variable Bit1:      std_logic := '1';
-  variable Bit0:      std_logic := '0';
-
-  variable parameter_1: integer := 1234;
-  variable parameter_2: integer := 2345;
-  variable parameter_3: integer := 4567;
-
-
-begin
-
-fprint(RESULT, L,
-       "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
-       "-----------------------------------------\n\n" &
-       "This is the result of running the PCK_FIO testbench.\n" &
-       "This file should be compared with PCK_FIO.out.gold, which is\n" &
-       "the reference output. Any difference indicates a portability\n" &
-       "issue or a simulator non-compliance or bug.\n\n"
-      );
-
-  
-fprint(RESULT, L,
-       "\n--------------------\n" &
-         "-- Basic features --\n" &
-         "--------------------\n\n"
-      );
-
-fprint(RESULT, L,
-         "-- First some auxiliary declarations\n"
-      );
-
-fprint(RESULT, L,
-  "> file     RESULT:    text is out ""PCK_FIO.out"";\n" &
-  "> variable L:         line;\n" &
-  "> variable BoolTrue:  boolean := TRUE;\n" &
-  "> variable BoolFalse: boolean := FALSE;\n" &
-  "> variable IntPos:    integer := 5678;\n" & 
-  "> variable BigIntPos: integer := 12345678;\n" & 
-  "> variable IntNeg:    integer := -8765;\n" & 
-  "> variable BigIntNeg: integer := -87654321;\n" & 
-  "> variable Uns:       unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
-  "> variable Unk:       unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
-  "> variable Std:       std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
-  "> variable SigPos:    signed(6 downto 0) := signed'(""0010010"");\n" &
-  "> variable SigNeg:    signed(6 downto 0) := signed'(""1010010"");\n" &
-  "> variable BitX:      std_logic := 'X';\n" &
-  "> variable Bit1:      std_logic := '1';\n" &
-  "> variable Bit0:      std_logic := '0';\n"
-);
-  
-   
-fprint(RESULT, L,
-       "\n\n-- fprint call with no arguments\n" &
-       "> fprint(RESULT, L, ""No arguments.\\n);""\n"
-      );
-fprint(RESULT, L, "No arguments.\n");
-  
-  
-fprint(RESULT, L,
-       "\n-- Special characters need to be escaped\n" &
-       "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
-      );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
-       "\n-- Various format specifiers interprete the same object differently\n" &
-       "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" &
-       ">                   fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
-                  fo(Uns), fo(Uns), fo(Uns), fo(Uns)
-      );
-
-fprint(RESULT, L,
-       "\n-- Format string can be shortened by using the iteration specifier\n" &
-       "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" &
-       ">                   fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
-                  fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
-      );
-
-
-fprint(RESULT, L,
-       "\n------------------------------------\n" &
-         "-- Support for bit-oriented types --\n" &
-         "------------------------------------\n"
-      );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
-                   "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
-                   "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
-                   "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-  
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Bitvectors with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
-       
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-
-fprint(RESULT, L, "Bitvectors with \%1r:  %4{%1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2r:  %4{%2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3r:  %4{%3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4r:  %4{%4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5r:  %4{%5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6r:  %4{%6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7r:  %4{%7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8r:  %4{%8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9r:  %4{%9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r:  %4{%-1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2r:  %4{%-2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3r:  %4{%-3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4r:  %4{%-4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5r:  %4{%-5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6r:  %4{%-6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7r:  %4{%-7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8r:  %4{%-8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9r:  %4{%-9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d:  %4{%1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2d:  %4{%2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3d:  %4{%3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4d:  %4{%4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5d:  %4{%5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6d:  %4{%6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7d:  %4{%7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8d:  %4{%8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9d:  %4{%9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d:  %4{%-1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2d:  %4{%-2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3d:  %4{%-3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4d:  %4{%-4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5d:  %4{%-5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6d:  %4{%-6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7d:  %4{%-7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8d:  %4{%-8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9d:  %4{%-9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-
-  
-  
-fprint(RESULT, L,
-       "\n-------------------------------\n" &
-         "-- Support for integer types --\n" &
-         "-------------------------------\n"
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Integers with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-       
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-  
-  
-fprint(RESULT, L, "Integers with \%5d:    %4{%5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6d:    %4{%6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7d:    %4{%7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8d:    %4{%8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9d:    %4{%9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10d:   %4{%10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d:    %4{%-5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6d:    %4{%-6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7d:    %4{%-7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8d:    %4{%-8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9d:    %4{%-9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10d:   %4{%-10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r:    %4{%5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6r:    %4{%6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7r:    %4{%7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8r:    %4{%8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9r:    %4{%9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10r:   %4{%10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r:    %4{%-5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6r:    %4{%-6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7r:    %4{%-7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8r:    %4{%-8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9r:    %4{%-9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10r:   %4{%-10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
-       "\n----------------------\n" &
-         "-- Support for time --\n" &
-         "----------------------\n"
-      );
-  
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
-                   "-- into an integer value (of nanoseconds)\n"
-       ); 
-fprint (RESULT, L, "> wait for 648 ns\n"); 
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); 
-
-wait for 648 ns;
-  
-fprint (RESULT, L, "The time is now %d ns\n", fo(now)); 
-
-  
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Erroneous calls and error messages --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
-                  "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
-      );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
- 
-fprint(RESULT, L, "\n");
-  
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
-                  "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
-                  "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
-      ); 
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Things you wouldn't expect to work --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-  
-end process USAGE;
-  
-end TB;
diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES
deleted file mode 100644
index b755a56..0000000
--- a/lib/PCK_FIO-2002.7/CHANGES
+++ /dev/null
@@ -1,86 +0,0 @@
-----  $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-Changes from version 1.16 to version 2002.07
-============================================
-
-PCK_FIO is now distributed under the GNU Lesser General Public Licencse
-instead of the ordinary GPL, to better reflect intended usage.
-
-Cosmetic changes in source code to correct some typos in the testbench output.
-A new testbench is also supplied.
-
-The package now uses IEEE.numeric_std as default.
-
-URL http://www.easics.com has been made part of address.
-
-Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
-Because of backwards-incompatibility, it has been necessary to supply
-different sets of files for 1987 and 1993.
-
-Split the packages into a separate file for the header and a
-separate file for the body (in compliance with Easics' guidelines).
-
-These changes resulted in the files:
-
-Files for VHDL-1993: 
---------------------
-  PCK_FIO_1993.vhd : 	 the source code of the header file for the package
-  PCK_FIO_1993_BODY.vhd: the source code of the body of the package
-  TB_PCK_FIO_1993.vhd:   the testbench for the package 
-
-Files for VHDL-1987:
---------------------
-  PCK_FIO_1987.vhd:      the source code of the header file for the package
-  PCK_FIO_1987_BODY.vhd: the source code of the body of the package
-  TB_PCK_FIO_1987.vhd:   the testbench for the package 
-
-Updated README and PCK_FIO.html to support these changes.
-
-Adapted package files to support NUL termination of strings.
-fo(Arg: string) now prints the string until the first NUL.
-Several examples of its use are demonstrated in the supplied testbenches.
-
-Made cosmetic changes to code to improve readability.
-
-Acknowledgment
---------------
-These changes have been implemented by Peter Geens.
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html
deleted file mode 100644
index 6b5fc72..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO.html
+++ /dev/null
@@ -1,339 +0,0 @@
-<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
-<html>
-<head>
-   <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
-   <meta name="GENERATOR" content="Mozilla/4.76 [en] (X11; U; Linux 2.4.13 i686) [Netscape]">
-   <title>VHDL package for formatted file output</title>
-<!-- $Id: PCK_FIO.html,v 1.1 2008-08-23 08:20:28 Jens Exp $ -->
-</head>
-<body text="#000000" bgcolor="#FFFFFF" link="#0000EE" vlink="#551A8B" alink="#FF0000">
-
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_name_0"></a>Name</h1>
-<b>PCK_FIO</b> - VHDL package for&nbsp; formatted file output
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-Contents</h1>
-<a href="#PCK_FIO_usage_0">Usage</a>
-<br><a href="#PCK_FIO_file_0">The file output function 'fo'</a>
-<br><a href="#PCK_FIO_format_0">Format specifiers</a>
-<br><a href="#PCK_FIO_special_0">Special characters</a>
-<br><a href="#PCK_FIO_things_0">Things to watch out for</a>
-<br><a href="#PCK_FIO_methodology_0">Methodology notes</a>
-<br><a href="#PCK_FIO_parametrization_0">Parametrization</a>
-<br><a href="#PCK_FIO_test_0">Test bench</a>
-<br><a href="#PCK_FIO_limitations_0">Known limitations and problems</a>
-<br><a href="#PCK_FIO_author_0">Author</a>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_usage_0"></a>Usage</h1>
-PCK_FIO is a VHDL package that defines&nbsp; <tt>fprint, </tt>a function
-for formatted file output.
-<p>After installing the package you can call <tt>fprint</tt> as follows:
-<pre>&nbsp; fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));</pre>
-where F is the filehandle and L is the line variable.
-<p>The argument Format is the format string, which consists of ``normal''
-substrings which are copied verbatim, and format specifiers, starting with
-<tt>'%'</tt>.
-A typical format string looks as follows:
-<pre>&nbsp;&nbsp; "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"</pre>
-The remaining arguments are the expressions whose results you want to write
-to the file, embedded in <tt>fo</tt> function calls. There can be 0 to
-32 of such arguments. The expressions can be of any type for which an <tt>fo</tt>
-function exists. String expressions can also be called directly.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_file_0"></a>The file output function <tt>'fo'</tt></h1>
-The <tt>fo</tt> (<u>f</u>ile <u>o</u>utput) functions do the trick. They
-return a tagged string representation that is meaningful to format specifiers.
-Here are some examples:
-<pre>&nbsp; fo (signed'("1100"))&nbsp;&nbsp; returns "S:1100"&nbsp;
-&nbsp; fo (unsigned'("1100")) returns "U:1100"&nbsp;
-&nbsp; fo (TRUE)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; returns "L:T"
-&nbsp; fo (127)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; returns "I:127"</pre>
-The internal behavior of <tt>fo</tt> is irrelevant to the typical user.
-<br>&nbsp;
-<pre>The <tt>fo</tt> function is currently overloaded as follows:</pre>
-
-<pre>&nbsp; function fo (Arg: unsigned)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: signed)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: std_logic_vector)&nbsp; return string;
-&nbsp; function fo (Arg: std_ulogic_vector) return string;
-&nbsp; function fo (Arg: bit_vector)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: integer)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: std_ulogic)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: bit)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: boolean)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;&nbsp;
-&nbsp; function fo (Arg: character)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: string)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;
-&nbsp; function fo (Arg: time)&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return string;</pre>
-
-<p><br>To support null-terminated strings, the function <tt>fo</tt>(Arg:
-string) processes <tt>Arg</tt> up to the first <tt>NUL</tt> character,
-if any. If you want the whole string to be outputted you can just enter
-the string as a direct argument in <tt>fprint</tt>.&nbsp; See also the
-examples in the testbench.
-<pre>
-<hr SIZE=1 NOSHADE WIDTH="100%"></pre>
-
-<h1>
-<a NAME="PCK_FIO_format_0"></a>Format specifiers</h1>
-The general format of a format specifier is:
-<pre>&nbsp;&nbsp; %[-][n]c</pre>
-The optional <b>-</b> sign specifies left justified output; default is
-right justified.
-<p>The optional number <b>n</b> specifies a field-width. If it is not specified,
-<tt>fprint</tt>
-does something reasonable.
-<p><b>c</b> is the conversion specifier. Currently the following conversion
-specifiers are supported:
-<dl COMPACT>
-<dt>
-<a NAME="PCK_FIO_r_0"></a><b>r</b></dt>
-
-<dd>
-reasonable output format (inspired by Synopsys VSS)</dd>
-
-<dl COMPACT>Prints the ``most reasonable'' representation e.g. hex for
-unsigned, signed and other bit-like vectors (not preferred for integers)</dl>
-
-<dt>
-<a NAME="PCK_FIO_b_0"></a><b>b</b></dt>
-
-<dd>
-bit-oriented output</dd>
-
-<dt>
-<a NAME="PCK_FIO_d_0"></a><b>d</b></dt>
-
-<dd>
-decimal output</dd>
-
-<dt>
-<a NAME="PCK_FIO_s_0"></a><b>s</b></dt>
-
-<dd>
-string output (e.g. in combination with 'IMAGE for enum types)</dd>
-
-<dt>
-<a NAME="PCK_FIO_q_0"></a><b>q</b></dt>
-
-<dd>
-``qualified'' string output (shows internal representation from <tt>fo</tt>)</dd>
-
-<dt>
-<a NAME="PCK_FIO__0"></a><b>{}</b></dt>
-
-<dd>
-Iteration operator, used as follows:</dd>
-
-<dd>
-<tt>%n{&lt;format-string>}</tt></dd>
-
-<br>In this case, <b>n</b> is the iteration count and is mandatory. Iteration
-can be nested.</dl>
-
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_special_0"></a>Special characters</h1>
-To print a double quote,&nbsp; use <tt>'""'</tt> in the format string (VHDL
-convention). To print the special characters, <tt>'\'</tt>, and <tt>'%'</tt>,
-escape them with <tt>'\'</tt>. To prevent <tt>'{'</tt> and <tt>'}'</tt>
-from being interpreted as opening and closing brackets in iteration strings,
-escape them with <tt>'\'</tt>.
-<p>A newline is specified in the format string by <tt>'\n'</tt>.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_things_0"></a>Things to notice</h1>
-The fprint function expands into VHDL <tt>write</tt> and <tt>writeline</tt>
-commands. As in plain VHDL, nothing will be written to the output file
-until a <tt>writeline</tt> is given. Therefore, don't forget to include
-<tt>'\n'</tt>
-commands in the format string, or it ``will not work''.
-<p>The preferred format specifier for integers is, naturally, <b>%d</b>.
-This calls the VHDL <tt>write</tt> for integers. If you specify a field
-width that is too small, the field will automatically be expanded. If you
-use <b>%r</b> for integers, the field is not expanded automatically, which
-means that some digits are simply thrown away. This may sometimes be useful
-but it is also dangerous. Look at the test bench output for differences
-between <b>%d</b> and <b>%r</b> output.
-<p>When using the <b>%d</b> format specifier, the VHDL constraints for
-the allowed integer range apply.
-<p>In VHDL, signed/unsigned types have been standardized only relatively
-recently, in the package <tt>IEEE.numeric_std</tt>. The lack of a standard
-has caused (and is causing) portability issues. The most popular non-standard
-package that defines signed/unsigned is <tt>IEEE.std_logic_arith</tt> from
-Synopsys. PCK_FIO works with both packages,&nbsp; but refers to the standard
-package <tt>IEEE.numeric_std</tt> by default. To use <tt>IEEE.std_logic_arith</tt>
-instead, replace the reference to <tt>IEEE.numeric_std</tt> in the source
-code.&nbsp; This needs to be done consistently in a design database (e.g.
-in the PCK_FIO test bench as well).
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_methodology_0"></a>Methodology notes</h1>
-The obvious application for <tt>fprint</tt> is in test benches, to produce
-output files that trace the simulation behavior.
-<p>Another interesting application for <tt>fprint</tt> is to produce info,
-warning and error messages in your models. As it can take arguments, <tt>fprint</tt>
-is much better suited for this task than VHDL's <tt>assert</tt> or <tt>report</tt>
-statements. Actually <tt>fprint</tt> produces its own (few) warning messages.
-<p>An advanced usage is the generation of test vectors in a specific format.
-Instead of using the <tt>fo </tt>functions, you can write your own set
-of functions that return the symbols of a specific test format in a way
-that is understandable to the <tt>fprint</tt> format specifiers. As an
-example, when a high output value should be represented using the symbol
-'H' it suffices to write a conversion function that returns "B:H" and call
-it in combination with the <b>%b</b> format specifier.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_parametrization_0"></a>Parametrization</h1>
-Prefix and postfix strings for bit-oriented and hex-oriented output are
-parameterizable in the packages to accommodate different output styles.
-The settings in the distribution are such that hex output is indicated
-by the prefix '0x', while&nbsp; bit output prefix and postfix are empty
-strings.
-<p>You can adapt the output style by modifying the following constants
-in the package header:
-<p>&nbsp;&nbsp;<tt> -- prefix string for hex output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "X"""</tt>
-<br><tt>&nbsp; -- Verilog style: "h'"</tt>
-<br><tt>&nbsp; -- C style:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "0x"</tt>
-<br><tt>&nbsp; constant FIO_h_PRE:&nbsp; string := "0x";</tt>
-<p><tt>&nbsp; -- postfix string for hex output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; """"</tt>
-<br><tt>&nbsp; constant FIO_h_POST: string := "";</tt>
-<p><tt>&nbsp; -- prefix string for bit vector output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "B"""</tt>
-<br><tt>&nbsp; -- Verilog style: "b'"</tt>
-<br><tt>&nbsp; constant FIO_bv_PRE:&nbsp; string := "";</tt>
-<p><tt>&nbsp; -- postfix string for bit vector output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; """"</tt>
-<br><tt>&nbsp; constant FIO_bv_POST: string := "";</tt>
-<p><tt>&nbsp; -- prefix string for bit output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "'"</tt>
-<br><tt>&nbsp; -- Verilog style: "b'"</tt>
-<br><tt>&nbsp; constant FIO_b_PRE:&nbsp; string := "";</tt>
-<p><tt>&nbsp; -- postfix string for bit output</tt>
-<br><tt>&nbsp; -- VHDL style:&nbsp;&nbsp;&nbsp; "'"</tt>
-<br><tt>&nbsp; constant FIO_b_POST: string := "";</tt>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_test_0"></a>Test bench</h1>
-Included in the distribution are the files <tt>TB_PCK_FIO_1987.vhd and
-TB_PCK_FIO_1993</tt> with a test bench,depending on the standard you're
-running, for the PCK_FIO package. The file <tt>PCK_FIO.out.gold </tt>contains
-the expected output. If you run the test bench it should produce the file
-<tt>PCK_FIO.out</tt>
-that should be identical to <tt>PCK_FIO.out.gold</tt>. The source files
-should be analyzed in a VHDL library <tt>EASICS_PACKAGES</tt>.
-<p>A good way to understand <tt>fprint</tt> is to inspect the test bench
-and what it produces.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_limitations_0"></a>Known limitations and problems</h1>
-This VHDL package is an implementation of a flexible concept. It is likely
-to be extended and modified in the future. Backward compatibility is not
-guaranteed. Therefore, it is not recommended to give this package the status
-of a company wide standard package (or even worse, a VHDL standard package).
-Rather, it should be linked with a particular project (and it can be regarded
-as a standard package within that project).
-<p>PCK_FIO is available in either standard VHDL Std1076-1987 or standard
-VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
-with the package. The following is an overview of currently known issues:
-<br>&nbsp;
-<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
-<caption>PCK_FIO_1987 and various simulators/versions</caption>
-
-<tr>
-<th>Simulator</th>
-
-<th>PCK_FIO_1987</th>
-</tr>
-
-<tr>
-<td>Synopsys VSS 3.5 and earlier</td>
-
-<td>Incorrect (all zero) output in compiled mode</td>
-</tr>
-
-<tr>
-<td>Synopsys VSS 97.01</td>
-
-<td>OK</td>
-</tr>
-
-<tr>
-<td>Synopsys VSS/Scirocco 2000.02</td>
-
-<td>Incorrect output in compiled mode, interpreted mode works</td>
-</tr>
-
-<tr>
-<td>Mentor quickhdl</td>
-
-<td>OK</td>
-</tr>
-
-<tr NOSAVE>
-<td NOSAVE>Modeltech modelsim</td>
-
-<td>OK</td>
-</tr>
-
-<tr>
-<td>Cadence Leapfrog</td>
-
-<td>Should work with 4.4.1
-<br>Mysterious problems have been reported - please run the test bench
-and report problems</td>
-</tr>
-</table></center>
-
-<br>&nbsp;
-<center><table BORDER COLS=2 WIDTH="80%" NOSAVE >
-<caption>PCK_FIO_1993 and various simulators/versions</caption>
-
-<tr NOSAVE>
-<th NOSAVE>Simulator</th>
-
-<th NOSAVE>PCK_FIO_1993</th>
-</tr>
-
-<tr>
-<td>Synopsys VSS/Scirocco 2000.02</td>
-
-<td>Compile errors due to improper handling of files by Synopsys</td>
-</tr>
-
-<tr>
-<td>Synopsys VSS/Scirocco 2000.06</td>
-
-<td>works fine</td>
-</tr>
-
-<tr>
-<td>Modeltech modelsim 5.4c and higher</td>
-
-<td>OK</td>
-</tr>
-</table></center>
-
-<p>Although the package name suggests file IO, it only does file output.
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-<h1>
-<a NAME="PCK_FIO_author_0"></a>Author</h1>
-<a href="mailto:jand@easics.be">Jan Decaluwe</a>
-<p>
-<hr SIZE=1 NOSHADE WIDTH="100%">
-</body>
-</html>
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold
deleted file mode 100644
index 3fcfe4c..0000000
Binary files a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold and /dev/null differ
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
deleted file mode 100644
index d4cf8e6..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd
+++ /dev/null
@@ -1,105 +0,0 @@
-----  $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-use STD.TEXTIO.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-package PCK_FIO is
-
-  -- prefix string for hex output
-  -- VHDL style:    "X"""
-  -- Verilog style: "h'"
-  -- C style:       "0x"
-  constant FIO_h_PRE:  string := "0x";
-
-  -- postfix string for hex output
-  -- VHDL style:    """"
-  constant FIO_h_POST: string := "";
-
-  -- prefix string for bit vector output
-  -- VHDL style:    "B"""
-  -- Verilog style: "b'"
-  constant FIO_bv_PRE:  string := "";
-
-  -- postfix string for bit vector output
-  -- VHDL style:    """"
-  constant FIO_bv_POST: string := "";
-
-  -- prefix string for bit output
-  -- VHDL style:    "'"
-  -- Verilog style: "b'"
-  constant FIO_b_PRE:  string := "";
-
-  -- postfix string for bit output
-  -- VHDL style:    "'"
-  constant FIO_b_POST: string := "";
-
-  -- digit width for the string representation of integers
-  constant FIO_d_WIDTH: integer := 10; 
-
-  -- bit width for the string representation of integers
-  constant FIO_b_WIDTH: integer := 32;
-
-  -- definition of the NIL string (default value for fprint arguments)
-  -- fprint stops consuming arguments at the first NIL argument 
-  constant FIO_NIL: string := "\";
-
-
-  procedure fprint 
-	     (F:       out   text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     );
-
-  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive);
-
-end PCK_FIO;
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
deleted file mode 100644
index 44e42cf..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd
+++ /dev/null
@@ -1,821 +0,0 @@
-----  $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-package body PCK_FIO is
-
-  --------------------------
-  -- FIO Warnings support --
-  --------------------------
-
-  procedure FIO_Warning_Fsbla (F:       out   text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
-        	  "Format specifier beyond last argument\n"); 
-    fprint (F, L, "**  in format string: ""%s""\n", Format); 
-    fprint (F, L, "**                     ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n"); 
-  end FIO_Warning_Fsbla;
-
-  procedure FIO_Warning_Ufs   (F:       out   text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive;
-			       Char:    in    character) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintArg: " &
-		  "Unexpected format specifier '%r'\n",
-		  fo(Char));
-    fprint (F, L, "**   in format string: ""%s""\n", Format) ; 
-    fprint (F, L, "**                      ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n**   Assuming 'q' to proceed: "); 
-  end FIO_Warning_Ufs;
-
-
-  ----------------------------------
-  -- bit conversion support --
-  ----------------------------------
-
-  type T_bit_map is array(bit) of character;  
-  
-  constant C_BIT_MAP: T_bit_map 
-             := ('0', '1');
-
-  ----------------------------------
-  -- std_logic conversion support --
-  ----------------------------------
-
-  type T_std_logic_map is array(std_ulogic) of character;  
-  
-  constant C_STD_LOGIC_MAP: T_std_logic_map 
-             := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-
-  ------------------------------
-  -- Digit conversion support --  
-  ------------------------------
-
-  -- types & constants
-
-  subtype S_digit_chars is character range '0' to '9';
-  subtype S_digits      is integer   range  0  to  9 ; 
-
-  type T_digit_chars_map is array(S_digit_chars) of S_digits; 
-
-  constant C_DIGIT_CHARS_MAP: T_digit_chars_map 
-    := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
-
-  type T_digits_map is array(S_digits) of S_digit_chars; 
-
-  constant C_DIGITS_MAP: T_digits_map  
-    := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
-
-
-  --------------------------------
-  -- Decimal conversion support --
-  --------------------------------
-
-  -- unsigned to decimal
-  
-  function U_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0;
-  begin
-    for i in Argument'range loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(-1); 
-      end case;
-    end loop;
-    return (Result);
-  end U_To_d;
-
-  -- signed to decimal
-  
-  function S_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0; 
-  begin
-    case Argument(Argument'left) is 
-      when '1' =>    Result := - 2**(Argument'left-1);   
-      when '0' =>    Result := 0;
-      when others => return (integer'low); 
-    end case;
-    for i in Argument'left-1 downto 1 loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(integer'low); 
-      end case;
-    end loop; 
-    return (Result);
-  end S_To_d;
-
-  -- string to decimal
-  
-  function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
-    constant Sign: character := Arg(1);
-    constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
-    variable Char: character;
-    variable Result: integer := 0;
-  begin
-    Result := 0;
-    for i in Value'range loop
-      Result := Result * 10;
-      Char := Value(i);
-      if (Char /= ' ') then
-        Result := Result + C_DIGIT_CHARS_MAP(Char);
-      end if;
-    end loop;
-    case Sign is when '-'    => return(-Result);
-		 when others => return(Result);
-    end case;
-  end I_To_d;
-
-  -- boolean (0,1) to decimal
-  
-  function B_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "1"    => return(1);
-                when "0"    => return(0);
-                when others => return(-1);
-    end case;
-  end B_To_d;
-
-  -- boolean (T,F) to decimal
-  
-  function L_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "T"    => return(1);
-                when others => return(0);
-    end case;
-  end L_To_d;
-
-
-
-  ----------------------------
-  -- Hex conversion support --
-  ----------------------------
-
-  -- Constants & types
-
-  constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
-
-  -- Function to return Hex index of a nibble  
-
-  function U_To_h_Index(Arg: string(4 downto 1)) return integer is
-    variable Index: integer := 0;
-  begin
-    for i in Arg'range loop
-      case Arg(i) is when '1'    => Index := 2**(i-1) + Index;   
-	             when '0'    => null;
-                     when others => return (17); 
-      end case;
-    end loop;
-    return (Index+1);
-  end U_To_h_Index;
-
-  -- Hex conversion  
-
-  function U_To_h (Arg: string) return string is
-    variable Result: string((Arg'length-1)/4 +1 downto 1);
-    variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); 
-  begin
-    ExtArg(Arg'length downto 1) := Arg;
-    for i in Result'range loop
-      Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));     
-    end loop;
-    return (FIO_h_PRE & Result & FIO_h_POST);
-  end U_To_h;
-
-
-
-  ----------------------------
-  -- Bit conversion support --
-  ----------------------------
-
-  function L_To_b (Arg: string(1 to 1)) return string is
-    variable Result: string(1 to 1); 
-  begin
-    case Arg is when "T"    => Result := "1";
-                when others => Result := "0";
-    end case;
-    return(FIO_b_PRE & Result & FIO_b_POST);
-  end L_To_b;
-
-
-  function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
-	           Justified: side;
-		   Width: integer) return string is
-
-    variable IntValue: integer := I_To_d(Arg);
-    variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-    constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
-    variable BitWidth: integer range 0 to FIO_b_WIDTH;
-    variable MsPos: integer range 1 to BitValue'length; 
-    variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); 
-
-  begin
-
-    if (IntValue < 0) then
-      Sign := '-';
-      IntValue := -IntValue;
-    end if;
-
-    for i in BitValue'reverse_range loop 
-      BitValue(i) := C_DIGITS_MAP(IntValue mod 2); 
-      IntValue := IntValue / 2;
-      exit when (IntValue = 0);
-    end loop;
-
-    BitValueExtended := BitValue & Blanks; 
-
-    if (Width = 0) or (Width > FIO_b_WIDTH+1) then
-       BitWidth := FIO_b_WIDTH;   
-    else
-       BitWidth := Width-1;   
-    end if;
-
-    if (Justified = RIGHT) then
-      return (FIO_bv_PRE & 
-	      Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & 
-	      FIO_bv_POST);    
-    else
-      for i in BitValue'range loop 
-        if BitValue(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (FIO_bv_PRE & 
- 	      Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & 
-	      FIO_bv_POST);
-    end if;
-
-  end I_To_b;
-
-
-  -----------------------------------
-  -- Reasonable conversion support --
-  -----------------------------------
-
-  function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); 
-	           Justified: side;
-		   Width: integer) return string is
-    constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
-    constant Sign: character := Arg(1);
-    constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
-    variable IntWidth: integer range 0 to FIO_d_WIDTH;
-    variable MsPos: integer range 1 to Value'length; 
-    variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; 
-  begin
-    if (Width = 0) or (Width > FIO_d_WIDTH+1) then
-       IntWidth := FIO_d_WIDTH;   
-    else
-       IntWidth := Width-1;   
-    end if;
-    if (Justified = RIGHT) then
-      return (Sign & Value(Value'length-IntWidth+1 to Value'length));    
-    else
-      for i in Value'range loop 
-        if Value(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
-    end if;
-  end I_To_r;
-
-
-  -------------------------------------------
-  -- Reasonable output conversion function --
-  -------------------------------------------
-
-  function ReasonableOutput (Arg: string;
-			     Justified: side;
-		             Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return U_To_h(Value);  
-      when "I:" =>
-	return I_To_r(Value, Justified, Width);
-      when "B:" | "L:" | "C:" =>
-        return Value;     
-      when others => 
-	return Argument;  
-    end case;
-
-  end ReasonableOutput;
-
-
-  ------------------------------------
-  -- Bit output conversion function --
-  ------------------------------------
-
-  function BitOutput (Arg: string;
-		      Justified: side;
-		      Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return (FIO_bv_PRE & Value & FIO_bv_POST);  
-      when "B:" =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-        return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);  
-      when "I:" =>
-	return I_To_b(Value, Justified, Width);
-      when "L:"  =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-	return L_To_b(Value(1 to 1));
-      when others => 
-	return Argument;  
-    end case;
-
-  end BitOutput;
-
-
-  -------------------------------------------
-  -- Decimal output conversion function --
-  -------------------------------------------
-
-  function DecimalOutput (Arg: string) return integer is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:"| "V:" =>
-	return U_To_d(Value);
-      when "S:" =>
-	return S_To_d(Value);
-      when "I:" =>
-	return I_To_d(Value);
-      when "B:" =>
-	return B_To_d(Value);
-      when "L:" =>
-	return L_To_d(Value);
-      when others => 
-	return integer'low;  
-    end case;
-
-  end DecimalOutput;
-
-
-  ----------------------------
-  -- Atomic print functions --  
-  ----------------------------
-
-  -- test for end of format string
-  
-  function FIO_EOS (Format: in string;
-		    Pointer: in integer) 
-	   return boolean is 
-  begin
-    return (Pointer > Format'length);
-  end FIO_EOS; 
-
-
-  -- Atomic value print function
-
-  procedure FIO_PrintValue (F:       out   text;
-			    L:       inout line; 
-			    Format:  in    string; 
-			    Pointer: inout integer;
-			    Last:    in    boolean := FALSE) is
-    variable Char: character;  
-  begin
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '\' =>
-	  Pointer := Pointer + 1;
-	  exit when (FIO_EOS(Format, Pointer));
-          Char := Format(Pointer);
-	  case Char is when 'n'    => writeline(F, L); 
-	               when others => write(L, Char);
-	  end case;
-	when '%' => 
-	  if Last then
-	    FIO_Warning_Fsbla(F, L, Format, Pointer);
-	  end if;
-	  Pointer := Pointer + 1; 
-	  exit;
-	when others  => 
-	  write(L, char); 
-      end case;
-      Pointer := Pointer + 1;
-    end loop;
-  end FIO_PrintValue; 
-
-
-  ---- Atomic argument print function
-
-  procedure FIO_PrintArg (F:       out   text;
-			  L:       inout line; 
-			  Format:  in    string; 
-			  Pointer: inout integer;
-			  Arg:     in    string) is
-    variable Char: character;  
-    variable Justified: side;  
-    variable Width: integer;
-  begin
-
-    FIO_PrintValue(F, L, Format, Pointer);
-
-    Justified := RIGHT;  
-    Width := 0; 
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '-' =>
-	  Justified := LEFT;  
-          Pointer := Pointer + 1;
-	when '0' to '9' =>
-	  Width := Width*10 + C_DIGIT_CHARS_MAP(Char); 
-          Pointer := Pointer + 1;
-	when 'r' => 
-	  write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'b' => 
-	  write(L, BitOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'd' => 
-	  write(L, DecimalOutput(Arg), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'q' | 's' => 
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when others  => 
-          FIO_Warning_Ufs(F, L, Format, Pointer, Char);
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-      end case;
-    end loop;
-  end FIO_PrintArg; 
-
-
-  -----------------------------------------------------
-  -- The format string iteration expansion procedure --
-  -----------------------------------------------------
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive) is
-
-    variable Pointer: positive := StartPointer;
-    variable TokenStart: positive;
-    variable IterStringStart: positive;
-    variable IterStringEnd: positive;
-    variable IterCount: natural;
-    variable OpenBrackets: natural;
-    variable L: line;
-
-  begin
-
-    FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop 
-
-      case Format(Pointer) is
-
-        -- look for format specifier
-	when '%' => 
-
-          -- initialize iteration token search 
-	  TokenStart := Pointer;
-          IterCount := 0; 
-	  Pointer := Pointer + 1;
-
-          -- start iteration token search
-	  TOKEN_READ: while not FIO_EOS(Format, Pointer) loop 
-             
-	    case Format(Pointer) is
-                
-              -- read iteration counter
-	      when '0' to '9' =>
-		IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); 
-                Pointer := Pointer + 1;
-               
-              -- expect open bracket
-	      when '{' => 
-
-		-- initialize iteration string read
-		OpenBrackets := 1;
-		IterStringStart := Pointer + 1;
-                Pointer := Pointer + 1;
-		-- quit prematurely when iteration count is 0
-		next FORMAT_SEARCH when (IterCount = 0);
-
-                -- start iteration string read
-	        ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop 
-
-	          case Format(Pointer) is
-                    -- keep track of open brackets
-		    when '{' => 
-		      OpenBrackets := OpenBrackets + 1;
-	              Pointer := Pointer + 1;
-                    -- when closing bracket is found, process iteration string      
-		    when '}' => 
-	 	      OpenBrackets := OpenBrackets - 1;
-		      if (OpenBrackets = 0) then
-			IterStringEnd := Pointer-1;
-			if (TokenStart /= 1) then
-			  write(L, Format(1 to TokenStart-1)); 
-			end if;
-			for i in 1 to IterCount loop
-			  write(L,  Format(IterStringStart to IterStringEnd));
-			end loop;
-			if (IterStringEnd /= Format'length) then
-			  write(L, Format(IterStringEnd+2 to Format'length)); 
-			end if;
-			-- call expansion procedure recursively on expanded format
-			FIO_FormatExpand(FMT, L.all, TokenStart);
-                        deallocate(L);
-                        return; 
-		      end if;
-	              Pointer := Pointer + 1;
-                    -- skip escaped characters
-	            when '\' => 
-	              Pointer := Pointer + 2;
-                    -- read iteration string  
-	            when others => 
-	              Pointer := Pointer + 1;
-
-		  end case; 
-
-		end loop ITER_STRING_READ;
-
-              -- stop iteration token search when no opening bracket found 
-	      when others => 
-                Pointer := Pointer + 1;
-		next FORMAT_SEARCH;
-
-	    end case;
-
-	  end loop TOKEN_READ;
-
-        -- skip escaped characters
-	when '\' => 
-	  Pointer := Pointer + 2;
-
-        -- read other characters
-	when others => 
-          Pointer := Pointer + 1;
-
-      end case;
-
-    end loop FORMAT_SEARCH;
-
-    write(FMT, Format);
-    deallocate(L);
-
-  end FIO_FormatExpand;
-
-
-
-  --------------------------
-  -- The fprint procedure --
-  --------------------------
-
-  procedure fprint 
-	     (F:       out   text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     ) is
-
-    variable Pointer: integer;
-    variable FMT: line;
-		    
-  begin
-
-    Pointer := 1;
-
-    FIO_FormatExpand (FMT, Format, Format'low);
-
-    if (A1  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
-    if (A2  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
-    if (A3  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
-    if (A4  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
-    if (A5  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
-    if (A6  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
-    if (A7  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
-    if (A8  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
-    if (A9  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
-    if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
-    if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
-    if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
-    if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
-    if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
-    if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
-    if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
-    if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
-    if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
-    if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
-    if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
-    if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
-    if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
-    if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
-    if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
-    if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
-    if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
-    if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
-    if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
-    if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
-    if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
-    if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
-    if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-
-    FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
-
-    deallocate(FMT);
-
-  end fprint;
-  
-
-  -------------------------------------------
-  -- Formatted output conversion functions --
-  -------------------------------------------
-
-  function fo (Arg: unsigned) return string is
-    constant Argument: unsigned(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("U:" & Result);
-  end fo;
-
-  function fo (Arg: signed) return string is
-    constant Argument: signed(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("S:" & Result);
-  end fo;
-
-  function fo (Arg: std_logic_vector) return string is
-    constant Argument: std_logic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic_vector) return string is
-    constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: bit_vector) return string is
-    constant Argument: bit_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_BIT_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: integer) return string is
-    variable Argument: integer := Arg;
-    variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-  begin
-    if (Argument < 0) and (Argument /= integer'low) then
-      Sign := '-';
-      Argument := -Argument;
-    end if;
-    for i in Result'reverse_range loop 
-      Result(i) := C_DIGITS_MAP(Argument mod 10); 
-      Argument := Argument / 10;
-      exit when (Argument = 0);
-    end loop;
-    return ("I:" & Sign & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic) return string is
-  begin
-    return ("B:" & C_STD_LOGIC_MAP(Arg));
-  end fo;
-
-  function fo (Arg: bit) return string is
-  begin
-    return ("B:" & C_BIT_MAP(Arg));
-  end fo;
-
-  function fo (Arg: boolean) return string is
-  begin
-    if (ARG = TRUE) then
-      return ("L:T");
-    else 
-      return ("L:F");
-    end if;
-  end fo;
-
-  function fo (Arg: character) return string is
-  begin
-    return ("C:" & Arg);   
-  end fo;
-
-  -- auxilary function fgets(Arg: string)
-  -- gives index until first NUL
-  -- reads string from 1 to Arg'length
-  function fgets (Arg: string) return integer is
-    variable index: integer := Arg'length;
-  begin
-      for i in 1 to Arg'length loop
-        if Arg(i) = NUL then
-          index := i - 1;
-          exit;
-         else
-           null;
-        end if;  
-      end loop;
-        return index;
-    end fgets;
-            
-  function fo (Arg: string) return string is   
-   begin  
-     return Arg(1 to fgets(Arg));
-   end fo;
-
-  function fo (Arg: time) return string is
-  begin
-    return fo (integer (Arg / 1 ns));   
-  end fo;
-
-end PCK_FIO;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
deleted file mode 100644
index 9df893e..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd
+++ /dev/null
@@ -1,108 +0,0 @@
-----  $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-use STD.TEXTIO.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-package PCK_FIO is
-
-   
-  -- prefix string for hex output
-  -- VHDL style:    "X"""
-  -- Verilog style: "h'"
-  -- C style:       "0x"
-  constant FIO_h_PRE:  string := "0x";
-
-  -- postfix string for hex output
-  -- VHDL style:    """"
-  constant FIO_h_POST: string := "";
-
-  -- prefix string for bit vector output
-  -- VHDL style:    "B"""
-  -- Verilog style: "b'"
-  constant FIO_bv_PRE:  string := "";
-
-  -- postfix string for bit vector output
-  -- VHDL style:    """"
-  constant FIO_bv_POST: string := "";
-
-  -- prefix string for bit output
-  -- VHDL style:    "'"
-  -- Verilog style: "b'"
-  constant FIO_b_PRE:  string := "";
-
-  -- postfix string for bit output
-  -- VHDL style:    "'"
-  constant FIO_b_POST: string := "";
-
-  -- digit width for the string representation of integers
-  constant FIO_d_WIDTH: integer := 10; 
-
-  -- bit width for the string representation of integers
-  constant FIO_b_WIDTH: integer := 32;
-
-  -- definition of the NIL string (default value for fprint arguments)
-  -- fprint stops consuming arguments at the first NIL argument 
-  constant FIO_NIL: string := "\";
-  
-  procedure fprint
-  	     (file F:  text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     );
-
-  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive);
-
-end PCK_FIO;
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
deleted file mode 100644
index 3d123f0..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
+++ /dev/null
@@ -1,814 +0,0 @@
-----  $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
- package body PCK_FIO is
-              
-  --------------------------
-  -- FIO Warnings support --
-  --------------------------
-
-  procedure FIO_Warning_Fsbla (file F:  text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintLastValue: " &
-        	  "Format specifier beyond last argument\n"); 
-    fprint (F, L, "**  in format string: ""%s""\n", Format); 
-    fprint (F, L, "**                     ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n"); 
-  end FIO_Warning_Fsbla;
-
-  procedure FIO_Warning_Ufs   (file F:  text;
-		               L:       inout line; 
-                               Format:  in    string;  
-			       Pointer: in    positive;
-			       Char:    in    character) is
-  begin
-    fprint (F, L, "\n** Warning: FIO_PrintArg: " &
-		  "Unexpected format specifier '%r'\n",
-		  fo(Char));
-    fprint (F, L, "**   in format string: ""%s""\n", Format) ; 
-    fprint (F, L, "**                      ");                     
-    for i in 1 to Pointer-1 loop
-      fprint (F, L, "-"); 
-    end loop;
-    fprint (F, L, "^\n**   Assuming 'q' to proceed: "); 
-  end FIO_Warning_Ufs;
-
-
-  ----------------------------------
-  -- bit conversion support --
-  ----------------------------------
-
-  type T_bit_map is array(bit) of character;  
-  
-  constant C_BIT_MAP: T_bit_map 
-             := ('0', '1');
-
-  ----------------------------------
-  -- std_logic conversion support --
-  ----------------------------------
-
-  type T_std_logic_map is array(std_ulogic) of character;  
-  
-  constant C_STD_LOGIC_MAP: T_std_logic_map 
-             := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
-
-  ------------------------------
-  -- Digit conversion support --  
-  ------------------------------
-
-  -- types & constants
-
-  subtype S_digit_chars is character range '0' to '9';
-  subtype S_digits      is integer   range  0  to  9 ; 
-
-  type T_digit_chars_map is array(S_digit_chars) of S_digits; 
-
-  constant C_DIGIT_CHARS_MAP: T_digit_chars_map 
-    := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
-
-  type T_digits_map is array(S_digits) of S_digit_chars; 
-
-  constant C_DIGITS_MAP: T_digits_map  
-    := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
-
-
-  --------------------------------
-  -- Decimal conversion support --
-  --------------------------------
-
-  -- unsigned to decimal
-  
-  function U_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0;
-  begin
-    for i in Argument'range loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(-1); 
-      end case;
-    end loop;
-    return (Result);
-  end U_To_d;
-
-  -- signed to decimal
-  
-  function S_To_d (Arg: string) return integer is
-    constant Argument: string(Arg'length downto 1) := Arg;
-    variable Result: integer := 0; 
-  begin
-    case Argument(Argument'left) is 
-      when '1' =>    Result := - 2**(Argument'left-1);   
-      when '0' =>    Result := 0;
-      when others => return (integer'low); 
-    end case;
-    for i in Argument'left-1 downto 1 loop
-      case Argument(i) is when '1'    => Result := 2**(i-1) + Result;   
-	                  when '0'    => null;
-                          when others => return(integer'low); 
-      end case;
-    end loop; 
-    return (Result);
-  end S_To_d;
-
-  -- string  to decimal
-
-  function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is
-    constant Sign: character := Arg(1);
-    constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length);
-    variable Char: character;
-    variable Result: integer := 0;
-  begin
-    Result := 0;
-    for i in Value'range loop
-      Result := Result * 10;
-      Char := Value(i);
-      if (Char /= ' ') then
-        Result := Result + C_DIGIT_CHARS_MAP(Char);
-      end if;
-    end loop;
-    case Sign is when '-'    => return(-Result);
-		 when others => return(Result);
-    end case;
-  end I_To_d;
-
-  -- boolean (0,1) to decimal
-
-  function B_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "1"    => return(1);
-                when "0"    => return(0);
-                when others => return(-1);
-    end case;
-  end B_To_d;
-
-  -- boolean (T,F) to decimal
-  
-  function L_To_d (Arg: string(1 to 1)) return integer is
-  begin
-    case Arg is when "T"    => return(1);
-                when others => return(0);
-    end case;
-  end L_To_d;
-
-
-
-  ----------------------------
-  -- Hex conversion support --
-  ----------------------------
-
-  -- Constants & types
-
-  constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?";
-
-  -- Function to return Hex index of a nibble  
-
-  function U_To_h_Index(Arg: string(4 downto 1)) return integer is
-    variable Index: integer := 0;
-  begin
-    for i in Arg'range loop
-      case Arg(i) is when '1'    => Index := 2**(i-1) + Index;   
-	             when '0'    => null;
-                     when others => return (17); 
-      end case;
-    end loop;
-    return (Index+1);
-  end U_To_h_Index;
-
-  -- Hex conversion  
-
-  function U_To_h (Arg: string) return string is
-    variable Result: string((Arg'length-1)/4 +1 downto 1);
-    variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); 
-  begin
-    ExtArg(Arg'length downto 1) := Arg;
-    for i in Result'range loop
-      Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) ));     
-    end loop;
-    return (FIO_h_PRE & Result & FIO_h_POST);
-  end U_To_h;
-
-
-
-  ----------------------------
-  -- Bit conversion support --
-  ----------------------------
-
-  function L_To_b (Arg: string(1 to 1)) return string is
-    variable Result: string(1 to 1); 
-  begin
-    case Arg is when "T"    => Result := "1";
-                when others => Result := "0";
-    end case;
-    return(FIO_b_PRE & Result & FIO_b_POST);
-  end L_To_b;
-
-
-  function I_To_b (Arg: string(1 to FIO_d_WIDTH+1);
-	           Justified: side;
-		   Width: integer) return string is
-
-    variable IntValue: integer := I_To_d(Arg);
-    variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-    constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' ');
-    variable BitWidth: integer range 0 to FIO_b_WIDTH;
-    variable MsPos: integer range 1 to BitValue'length; 
-    variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); 
-
-  begin
-
-    if (IntValue < 0) then
-      Sign := '-';
-      IntValue := -IntValue;
-    end if;
-
-    for i in BitValue'reverse_range loop 
-      BitValue(i) := C_DIGITS_MAP(IntValue mod 2); 
-      IntValue := IntValue / 2;
-      exit when (IntValue = 0);
-    end loop;
-
-    BitValueExtended := BitValue & Blanks; 
-
-    if (Width = 0) or (Width > FIO_b_WIDTH+1) then
-       BitWidth := FIO_b_WIDTH;   
-    else
-       BitWidth := Width-1;   
-    end if;
-
-    if (Justified = RIGHT) then
-      return (FIO_bv_PRE & 
-	      Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & 
-	      FIO_bv_POST);    
-    else
-      for i in BitValue'range loop 
-        if BitValue(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (FIO_bv_PRE & 
- 	      Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & 
-	      FIO_bv_POST);
-    end if;
-
-  end I_To_b;
-
-
-  -----------------------------------
-  -- Reasonable conversion support --
-  -----------------------------------
-
-  function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); 
-	           Justified: side;
-		   Width: integer) return string is
-    constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1);
-    constant Sign: character := Arg(1);
-    constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' ');
-    variable IntWidth: integer range 0 to FIO_d_WIDTH;
-    variable MsPos: integer range 1 to Value'length; 
-    variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; 
-  begin
-    if (Width = 0) or (Width > FIO_d_WIDTH+1) then
-       IntWidth := FIO_d_WIDTH;   
-    else
-       IntWidth := Width-1;   
-    end if;
-    if (Justified = RIGHT) then
-      return (Sign & Value(Value'length-IntWidth+1 to Value'length));    
-    else
-      for i in Value'range loop 
-        if Value(i) /= ' ' then
-	  MSPos := i;
-	  exit;
-	end if;
-      end loop;
-      return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1));
-    end if;
-  end I_To_r;
-
-
-  -------------------------------------------
-  -- Reasonable output conversion function --
-  -------------------------------------------
-
-  function ReasonableOutput (Arg: string;
-			     Justified: side;
-		             Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return U_To_h(Value);  
-      when "I:" =>
-	return I_To_r(Value, Justified, Width);
-      when "B:" | "L:" | "C:" =>
-        return Value;     
-      when others => 
-	return Argument;  
-    end case;
-
-  end ReasonableOutput;
-
-
-  ------------------------------------
-  -- Bit output conversion function --
-  ------------------------------------
-
-  function BitOutput (Arg: string;
-		      Justified: side;
-		      Width: integer) return string is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:" | "S:" | "V:" => 
-        return (FIO_bv_PRE & Value & FIO_bv_POST);  
-      when "B:" =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-        return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST);  
-      when "I:" =>
-	return I_To_b(Value, Justified, Width);
-      when "L:"  =>
-        -- Value(1 to 1) instead of Value for LeapFrog
-	return L_To_b(Value(1 to 1));
-      when others => 
-	return Argument;  
-    end case;
-
-  end BitOutput;
-
-
-  -------------------------------------------
-  -- Decimal output conversion function --
-  -------------------------------------------
-
-  function DecimalOutput (Arg: string) return integer is
-    constant Argument: string(1 to Arg'length) := Arg;
-    constant TypeSpec: string (1 to 2) := Argument(1 to 2);
-    constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length);
-  begin
-    case TypeSpec is
-      when "U:"| "V:" =>
-	return U_To_d(Value);
-      when "S:" =>
-	return S_To_d(Value);
-      when "I:" =>
-	return I_To_d(Value);
-      when "B:" =>
-	return B_To_d(Value);
-      when "L:" =>
-	return L_To_d(Value);
-      when others => 
-	return integer'low;  
-    end case;
-
-  end DecimalOutput;
-
-
-  ----------------------------
-  -- Atomic print functions --  
-  ----------------------------
-
-  -- test for end of format string
-  
-  function FIO_EOS (Format: in string;
-		    Pointer: in integer) 
-	   return boolean is 
-  begin
-    return (Pointer > Format'length);
-  end FIO_EOS; 
-
-
-  -- Atomic value print function
-
-  procedure FIO_PrintValue (file F:  text;
-			    L:       inout line; 
-			    Format:  in    string; 
-			    Pointer: inout integer;
-			    Last:    in    boolean := FALSE) is
-    variable Char: character;  
-  begin
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '\' =>
-	  Pointer := Pointer + 1;
-	  exit when (FIO_EOS(Format, Pointer));
-          Char := Format(Pointer);
-	  case Char is when 'n'    => writeline(F, L); 
-	               when others => write(L, Char);
-	  end case;
-	when '%' => 
-	  if Last then
-	    FIO_Warning_Fsbla(F, L, Format, Pointer);
-	  end if;
-	  Pointer := Pointer + 1; 
-	  exit;
-	when others  => 
-	  write(L, char); 
-      end case;
-      Pointer := Pointer + 1;
-    end loop;
-  end FIO_PrintValue; 
-
-
-  ---- Atomic argument print function
-
-  procedure FIO_PrintArg (file F:  text;
-			  L:       inout line; 
-			  Format:  in    string; 
-			  Pointer: inout integer;
-			  Arg:     in    string) is
-    variable Char: character;  
-    variable Justified: side;  
-    variable Width: integer;
-
-  begin
-
-    FIO_PrintValue(F, L, Format, Pointer);
-
-    Justified := RIGHT;  
-    Width := 0; 
-    while (not FIO_EOS(Format, Pointer)) loop 
-      Char := Format(Pointer);
-      case Char is
-	when '-' =>
-	  Justified := LEFT;  
-          Pointer := Pointer + 1;
-	when '0' to '9' =>
-	  Width := Width*10 + C_DIGIT_CHARS_MAP(Char);
-          Pointer := Pointer + 1;
-	when 'r' => 
-	  write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'b' => 
-	  write(L, BitOutput(Arg, Justified, Width), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'd' => 
-	  write(L, DecimalOutput(Arg), Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when 'q' | 's' => 
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-	when others  => 
-          FIO_Warning_Ufs(F, L, Format, Pointer, Char);
-	  write(L, Arg, Justified, Width);  
-          Pointer := Pointer + 1;
-	  exit;
-      end case;
-    end loop;  
-  end FIO_PrintArg; 
-
-
-  -----------------------------------------------------
-  -- The format string iteration expansion procedure --
-  -----------------------------------------------------
-
-  procedure FIO_FormatExpand (FMT:          inout line; 
-			      Format:       in    string; 
-			      StartPointer: in    positive) is
-
-    variable Pointer: positive := StartPointer;
-    variable TokenStart: positive;
-    variable IterStringStart: positive;
-    variable IterStringEnd: positive;
-    variable IterCount: natural;
-    variable OpenBrackets: natural;
-    variable L: line;
-
-  begin
-
-    FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop 
-
-      case Format(Pointer) is
-
-        -- look for format specifier
-	when '%' => 
-
-          -- initialize iteration token search 
-	  TokenStart := Pointer;
-          IterCount := 0; 
-	  Pointer := Pointer + 1;
-
-          -- start iteration token search
-	  TOKEN_READ: while not FIO_EOS(Format, Pointer) loop 
-             
-	    case Format(Pointer) is
-                
-              -- read iteration counter
-	      when '0' to '9' =>
-		IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); 
-                Pointer := Pointer + 1;
-               
-              -- expect open bracket
-	      when '{' => 
-
-		-- initialize iteration string read
-		OpenBrackets := 1;
-		IterStringStart := Pointer + 1;
-                Pointer := Pointer + 1;
-		-- quit prematurely when iteration count is 0
-		next FORMAT_SEARCH when (IterCount = 0);
-
-                -- start iteration string read
-	        ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop 
-
-	          case Format(Pointer) is
-                    -- keep track of open brackets
-		    when '{' => 
-		      OpenBrackets := OpenBrackets + 1;
-	              Pointer := Pointer + 1;
-                    -- when closing bracket is found, process iteration string      
-		    when '}' => 
-	 	      OpenBrackets := OpenBrackets - 1;
-		      if (OpenBrackets = 0) then
-			IterStringEnd := Pointer-1;
-			if (TokenStart /= 1) then
-			  write(L, Format(1 to TokenStart-1)); 
-			end if;
-			for i in 1 to IterCount loop
-			  write(L,  Format(IterStringStart to IterStringEnd));
-			end loop;
-			if (IterStringEnd /= Format'length) then
-			  write(L, Format(IterStringEnd+2 to Format'length)); 
-			end if;
-			-- call expansion procedure recursively on expanded format
-			FIO_FormatExpand(FMT, L.all, TokenStart);
-                        deallocate(L);
-                        return; 
-		      end if;
-	              Pointer := Pointer + 1;
-                    -- skip escaped characters
-	            when '\' => 
-	              Pointer := Pointer + 2;
-                    -- read iteration string  
-	            when others => 
-	              Pointer := Pointer + 1;
-
-		  end case; 
-
-		end loop ITER_STRING_READ;
-
-              -- stop iteration token search when no opening bracket found 
-	      when others => 
-                Pointer := Pointer + 1;
-		next FORMAT_SEARCH;
-
-	    end case;
-
-	  end loop TOKEN_READ;
-
-        -- skip escaped characters
-	when '\' => 
-	  Pointer := Pointer + 2;
-
-        -- read other characters
-	when others => 
-          Pointer := Pointer + 1;
-
-      end case;
-
-    end loop FORMAT_SEARCH;
-
-    write(FMT, Format);
-    deallocate(L);
-
-  end FIO_FormatExpand;
-
-
-
-  --------------------------
-  -- The fprint procedure --
-  --------------------------
-
-  procedure fprint 
-	     (file F:  text;
-	      L:       inout line; 
-	      Format:  in    string;  
-	      A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL;
-	      A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL;
-	      A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL;
-	      A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL
-	     ) is
-
-    variable Pointer: integer;
-    variable FMT: line;
-		    
-  begin
-
-    Pointer := 1;
-
-    FIO_FormatExpand (FMT, Format, Format'low);
-
-    if (A1  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 );
-    if (A2  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 );
-    if (A3  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 );
-    if (A4  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 );
-    if (A5  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 );
-    if (A6  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 );
-    if (A7  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 );
-    if (A8  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 );
-    if (A9  /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 );
-    if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10);
-    if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11);
-    if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12);
-    if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13);
-    if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14);
-    if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15);
-    if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16);
-    if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17);
-    if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18);
-    if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19);
-    if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20);
-    if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21);
-    if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22);
-    if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23);
-    if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24);
-    if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25);
-    if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26);
-    if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27);
-    if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28);
-    if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29);
-    if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30);
-    if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31);
-    if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32);
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-    end if; end if; end if; end if; end if; end if; end if; end if; 
-
-    FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE);
-
-    deallocate(FMT);
-
-  end fprint;
-  
-
-  -------------------------------------------
-  -- Formatted output conversion functions --
-  -------------------------------------------
-
-  function fo (Arg: unsigned) return string is
-    constant Argument: unsigned(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("U:" & Result);
-  end fo;
-
-  function fo (Arg: signed) return string is
-    constant Argument: signed(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("S:" & Result);
-  end fo;
-
-  function fo (Arg: std_logic_vector) return string is
-    constant Argument: std_logic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic_vector) return string is
-    constant Argument: std_ulogic_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_STD_LOGIC_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: bit_vector) return string is
-    constant Argument: bit_vector(1 to Arg'length) := Arg;
-    variable Result: string(1 to Arg'length); 
-  begin
-    for i in Argument'range loop
-      Result(i) := C_BIT_MAP(Argument(i));
-    end loop;
-    return ("V:" & Result);
-  end fo;
-
-  function fo (Arg: integer) return string is
-    variable Argument: integer := Arg;
-    variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); 
-    variable Sign: character := ' ';
-  begin
-    if (Argument < 0) and (Argument /= integer'low) then
-      Sign := '-';
-      Argument := -Argument;
-    end if;
-    for i in Result'reverse_range loop 
-      Result(i) := C_DIGITS_MAP(Argument mod 10); 
-      Argument := Argument / 10;
-      exit when (Argument = 0);
-    end loop;
-    return ("I:" & Sign & Result);
-  end fo;
-
-  function fo (Arg: std_ulogic) return string is
-  begin
-    return ("B:" & C_STD_LOGIC_MAP(Arg));
-  end fo;
-
-  function fo (Arg: bit) return string is
-  begin
-    return ("B:" & C_BIT_MAP(Arg));
-  end fo;
-
-  function fo (Arg: boolean) return string is
-  begin
-    if (ARG = TRUE) then
-      return ("L:T");
-    else 
-      return ("L:F");
-    end if;
-  end fo;
-
-  function fo (Arg: character) return string is
-  begin
-    return ("C:" & Arg);   
-  end fo;
-
-  -- auxilary function fgets(Arg :string)
-  -- returns index of first NUL in Arg or if no NUL is present just Arg'length
-  -- goes through Arg from 1 to Arg'length
-  function fgets (Arg: string) return integer is
-    variable index: integer := Arg'length;
-  begin
-      for i in 1 to Arg'length loop
-        if Arg(i) = NUL then
-          index := i - 1;
-          exit;
-         else
-           null;
-        end if;  
-      end loop;
-        return index;
-    end fgets;
-      
-   -- returns the Arg string until the first NUL was encountered
-   -- if fo is used on a string with NUL in it it will stop reading the rest
-   -- of the string, even if a larger field width has been supplied.  fo will
-   -- then just pad the remaining characters with blanco's
-   function fo (Arg: string) return string is   
-   begin
-     return Arg(1 to fgets(Arg));
-   end fo;
-
-  function fo (Arg: time) return string is
-  begin
-    return fo (integer (Arg / 1 ns));   
-  end fo;
-
-end PCK_FIO;
-
diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README
deleted file mode 100644
index b16c6c5..0000000
--- a/lib/PCK_FIO-2002.7/README
+++ /dev/null
@@ -1,88 +0,0 @@
-----  $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-Version 2002.07
-===============
-
-Contents
-========
-
-This distribution contains the following files:
-
-  PCK_FIO_1987.vhd:         VHDL-87 source of the header of the PCK_FIO package
-  PCK_FIO_1987_BODY.vhd:    VHDL-87 source of the body of the PCK_FIO package 
-  PCK_FIO_1993.vhd:         VHDL-93 source of the header of the PCK_FIO package
-  PCK_FIO_1993_BODY.vhd:    VHDL-93 source of the body of the PCK_FIO package 
-  TB_PCK_FIO_1987.vhd:      VHDL-87 source of the testbench for package PCK_FIO
-  TB_PCK_FIO_1993.vhd:      VHDL-93 source of the testbench for package PCK_FIO
-  PCK_FIO.out.gold:    	    Certified test bench output
-  PCK_FIO.html:             Manual for PCK_FIO in html format
-  README:                   This file
-
-
-Installation
-============
-
-VHDL-1987
----------
-To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
-analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library.
-
-To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library.
-
-VHDL-1993
----------
-To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and
-analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library.
-
-To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library.
-
-Numeric packages
-----------------
-If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need
-to edit the source code of the package, both header and body, and the test bench
-and replace the package use clause. PCK_FIO works with either of these packages.
-
-Documentation
--------------
-To install the documentation, put the file point PCK_FIO.html in a path of
-your choosing, point your web browser to it, and bookmark it.
-
-
-Installation check
-==================
-
-After installing the test bench, you should run it. The corresponding VHDL
-design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB).
-
-Simulating the test bench should create a file called PCK_FIO.out. This file
-should be identical to PCK_FIO.out.gold. Any difference indicates a portability
-issue or a simulator non-compliance or bug.
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
deleted file mode 100644
index 2e18ff4..0000000
--- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd
+++ /dev/null
@@ -1,531 +0,0 @@
----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
- use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
-  file RESULT:        text is out "PCK_FIO.out"; 
-  variable L:         line;
-  variable Pointer:   integer;
-  variable BoolTrue:  boolean := TRUE;
-  variable BoolFalse: boolean := FALSE;
-  variable IntPos:    integer := 5678; 
-  variable BigIntPos: integer := 12345678; 
-  variable IntNeg:    integer := -8765; 
-  variable BigIntNeg: integer := -87654321; 
-  variable Uns:       unsigned(6 downto 0) := unsigned'("1010010");
-  variable Unk:       unsigned(6 downto 0) := unsigned'("1X10Z10");
-  variable Std:       std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
-  variable SigPos:    signed(6 downto 0) := signed'("0010010");
-  variable SigNeg:    signed(6 downto 0) := signed'("1010010");
-  variable BitX:      std_logic := 'X';
-  variable Bit1:      std_logic := '1';
-  variable Bit0:      std_logic := '0';
-
-  variable parameter_1: integer := 1234;
-  variable parameter_2: integer := 2345;
-  variable parameter_3: integer := 4567;
-  
-  constant TempString: string :="ABC" & NUL & "DEF";
-begin
-
-fprint(RESULT, L,
-       "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
-       "-----------------------------------------\n\n" &
-       "This is the result of running the PCK_FIO testbench.\n" &
-       "This file should be compared with PCK_FIO.out.gold, which is\n" &
-       "the reference output. Any difference indicates a portability\n" &
-       "issue or a simulator non-compliance or bug.\n\n"
-      );
-
-  
-fprint(RESULT, L,
-       "\n--------------------\n" &
-         "-- Basic features --\n" &
-         "--------------------\n\n"
-      );
-
-fprint(RESULT, L,
-         "-- First some auxiliary declarations\n"
-      );
-
-fprint(RESULT, L,
-  "> file     RESULT:     text is out ""PCK_FIO.out"";\n" &
-  "> variable L:          line;\n" &
-  "> variable BoolTrue:   boolean := TRUE;\n" &
-  "> variable BoolFalse:  boolean := FALSE;\n" &
-  "> variable IntPos:     integer := 5678;\n" & 
-  "> variable BigIntPos:  integer := 12345678;\n" & 
-  "> variable IntNeg:     integer := -8765;\n" & 
-  "> variable BigIntNeg:  integer := -87654321;\n" & 
-  "> variable Uns:        unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
-  "> variable Unk:        unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
-  "> variable Std:        std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
-  "> variable SigPos:     signed(6 downto 0) := signed'(""0010010"");\n" &
-  "> variable SigNeg:     signed(6 downto 0) := signed'(""1010010"");\n" &
-  "> variable BitX:       std_logic := 'X';\n" &
-  "> variable Bit1:       std_logic := '1';\n" &
-  "> variable Bit0:       std_logic := '0';\n" &
-  "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
-);
-  
-   
-fprint(RESULT, L,
-       "\n\n-- fprint call with no arguments\n" &
-       "> fprint(RESULT, L, ""No arguments.\\n"");\n"
-      );
-fprint(RESULT, L, "No arguments.\n");
-  
-  
-fprint(RESULT, L,
-       "\n-- Special characters need to be escaped\n" &
-       "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
-      );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
-       "\n-- Various format specifiers interprete the same object differently\n" &
-       "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
-       ">                   fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
-                  fo(Uns), fo(Uns), fo(Uns), fo(Uns)
-      );
-
-fprint(RESULT, L,
-       "\n-- Format string can be shortened by using the iteration specifier\n" &
-       "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
-       ">                   fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
-                  fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
-      );
-fprint(RESULT, L,
-       "\n-------------------------------\n"&
-       "--Testing string manipulation--\n"&
-       "-------------------------------\n");
-fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
-                      & " & NUL & ""DEF""\n");
--- temp_string: string:="ABC"&NUL&"DEF"
--- test for detecting NUL in string
-fprint(RESULT, L, "\n--test for NUL ending in strings\n");
-fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
-fprint(RESULT, L, fo(TempString));
-
--- direct inclusion of string in fprint should give whole string
-fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
-fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
-fprint(RESULT, L, TempString & "\n");
-
--- influence of given width
-
-fprint(RESULT, L, "\n--if there are less characters in the given string then"
-                  & " in the width fo will\n"&
-               "-- pad the remaining with blanco's according to the given justification\n");
-fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
-fprint(RESULT, L, "%5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
-fprint(RESULT, L, "%-5s",fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
-fprint(RESULT, L, "%9s", TempString);
-fprint(RESULT, L, "\n\n-- if the width is smaller then the number" &
-                   " of characters in the string fprint\n" &
-                "-- will output the string with the minimum of characters needed\n");
-fprint(RESULT, L, "\n--with specified width,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
-fprint(RESULT, L, "%2s",fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
-fprint(RESULT, L, "%4s", TempString);
-
-
-fprint(RESULT, L,
-       "\n\n------------------------------------\n" &
-         "-- Support for bit-oriented types --\n" &
-         "------------------------------------\n"
-      );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
-                   "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
-                   "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
-                   "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-  
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Bitvectors with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
-       
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-
-fprint(RESULT, L, "Bitvectors with \%1r:  %4{%1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2r:  %4{%2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3r:  %4{%3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4r:  %4{%4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5r:  %4{%5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6r:  %4{%6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7r:  %4{%7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8r:  %4{%8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9r:  %4{%9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r:  %4{%-1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2r:  %4{%-2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3r:  %4{%-3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4r:  %4{%-4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5r:  %4{%-5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6r:  %4{%-6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7r:  %4{%-7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8r:  %4{%-8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9r:  %4{%-9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d:  %4{%1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2d:  %4{%2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3d:  %4{%3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4d:  %4{%4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5d:  %4{%5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6d:  %4{%6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7d:  %4{%7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8d:  %4{%8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9d:  %4{%9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d:  %4{%-1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2d:  %4{%-2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3d:  %4{%-3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4d:  %4{%-4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5d:  %4{%-5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6d:  %4{%-6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7d:  %4{%-7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8d:  %4{%-8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9d:  %4{%-9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-
-  
-  
-fprint(RESULT, L,
-       "\n-------------------------------\n" &
-         "-- Support for integer types --\n" &
-         "-------------------------------\n"
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Integers with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-       
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-  
-  
-fprint(RESULT, L, "Integers with \%5d:    %4{%5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6d:    %4{%6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7d:    %4{%7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8d:    %4{%8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9d:    %4{%9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10d:   %4{%10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d:    %4{%-5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6d:    %4{%-6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7d:    %4{%-7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8d:    %4{%-8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9d:    %4{%-9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10d:   %4{%-10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r:    %4{%5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6r:    %4{%6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7r:    %4{%7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8r:    %4{%8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9r:    %4{%9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10r:   %4{%10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r:    %4{%-5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6r:    %4{%-6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7r:    %4{%-7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8r:    %4{%-8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9r:    %4{%-9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10r:   %4{%-10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
-       "\n----------------------\n" &
-         "-- Support for time --\n" &
-         "----------------------\n"
-      );
-  
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
-                   "-- into an integer value (of nanoseconds)\n"
-       ); 
-fprint (RESULT, L, "> wait for 648 ns\n"); 
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); 
-
-wait for 648 ns;
-  
-fprint (RESULT, L, "The time is now %d ns\n", fo(now)); 
-
-  
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Erroneous calls and error messages --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
-                  "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
-      );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
- 
-fprint(RESULT, L, "\n");
-  
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
-                  "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
-                  "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
-      ); 
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Things you wouldn't expect to work --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-  
-end process USAGE;
-  
-end TB;
-
-
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
deleted file mode 100644
index 0386a11..0000000
--- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
+++ /dev/null
@@ -1,536 +0,0 @@
----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
-----  PCK_FIO: a VHDL package for C-style formatted file output
-----  Copyright (C) 1995, 2001 Easics NV 
-----
-----  This library is free software; you can redistribute it and/or
-----  modify it under the terms of the GNU Lesser General Public
-----  License as published by the Free Software Foundation; either
-----  version 2.1 of the License, or (at your option) any later version.
-----
-----  This library is distributed in the hope that it will be useful,
-----  but WITHOUT ANY WARRANTY; without even the implied warranty of
-----  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-----  Lesser General Public License for more details.
-----
-----  You should have received a copy of the GNU Lesser General Public
-----  License along with this library; if not, write to the Free Software
-----  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----- 
-----  For suggestions, bug reports, enhancement requests, and info about  
-----  our design services, you can contact us at the following address: 
-----     http://www.easics.com
-----     Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
-----     tel.: +32 16 395 600   fax : +32 16 395 619 
-----     e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
-  file RESULT:        text open write_mode is "PCK_FIO.out"; 
-  variable L:         line;
-  variable Pointer:   integer;
-  variable BoolTrue:  boolean := TRUE;
-  variable BoolFalse: boolean := FALSE;
-  variable IntPos:    integer := 5678; 
-  variable BigIntPos: integer := 12345678; 
-  variable IntNeg:    integer := -8765; 
-  variable BigIntNeg: integer := -87654321; 
-  variable Uns:       unsigned(6 downto 0) := unsigned'("1010010");
-  variable Unk:       unsigned(6 downto 0) := unsigned'("1X10Z10");
-  variable Std:       std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
-  variable SigPos:    signed(6 downto 0) := signed'("0010010");
-  variable SigNeg:    signed(6 downto 0) := signed'("1010010");
-  variable BitX:      std_logic := 'X';
-  variable Bit1:      std_logic := '1';
-  variable Bit0:      std_logic := '0';
-
-  variable parameter_1: integer := 1234;
-  variable parameter_2: integer := 2345;
-  variable parameter_3: integer := 4567;
-
-  constant TempString: string :="ABC" & NUL & "DEF";
-begin
-
-fprint(RESULT, L,
-       "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
-       "-----------------------------------------\n\n" &
-       "This is the result of running the PCK_FIO testbench.\n" &
-       "This file should be compared with PCK_FIO.out.gold, which is\n" &
-       "the reference output. Any difference indicates a portability\n" &
-       "issue or a simulator non-compliance or bug.\n\n"
-      );
-
-  
-fprint(RESULT, L,
-       "\n--------------------\n" &
-         "-- Basic features --\n" &
-         "--------------------\n\n"
-      );
-
-fprint(RESULT, L,
-         "-- First some auxiliary declarations\n"
-      );
-
-fprint(RESULT, L,
-  "> file     RESULT:     text is out ""PCK_FIO.out"";\n" &
-  "> variable L:          line;\n" &
-  "> variable BoolTrue:   boolean := TRUE;\n" &
-  "> variable BoolFalse:  boolean := FALSE;\n" &
-  "> variable IntPos:     integer := 5678;\n" & 
-  "> variable BigIntPos:  integer := 12345678;\n" & 
-  "> variable IntNeg:     integer := -8765;\n" & 
-  "> variable BigIntNeg:  integer := -87654321;\n" & 
-  "> variable Uns:        unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
-  "> variable Unk:        unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
-  "> variable Std:        std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
-  "> variable SigPos:     signed(6 downto 0) := signed'(""0010010"");\n" &
-  "> variable SigNeg:     signed(6 downto 0) := signed'(""1010010"");\n" &
-  "> variable BitX:       std_logic := 'X';\n" &
-  "> variable Bit1:       std_logic := '1';\n" &
-  "> variable Bit0:       std_logic := '0';\n" &
-  "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
-);
-  
-   
-fprint(RESULT, L,
-       "\n\n-- fprint call with no arguments\n" &
-       "> fprint(RESULT, L, ""No arguments.\\n"");\n"
-      );
-fprint(RESULT, L, "No arguments.\n");
-  
-  
-fprint(RESULT, L,
-       "\n-- Special characters need to be escaped\n" &
-       "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
-      );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
-       "\n-- Various format specifiers interprete the same object differently\n" &
-       "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
-       ">                   fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
-                  fo(Uns), fo(Uns), fo(Uns), fo(Uns)
-      );
-
-fprint(RESULT, L,
-       "\n-- Format string can be shortened by using the iteration specifier\n" &
-       "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
-       ">                   fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
-       ">       );\n"
-      );
-  
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
-                  fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
-      );
-fprint(RESULT, L,
-       "\n-------------------------------\n"&
-       "--Testing string manipulation--\n"&
-       "-------------------------------\n");
-fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
-                    & " & NUL & ""DEF""\n");
--- TempString: string:="ABC" & NUL & "DEF"
--- test for detecting NUL in string
-fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
-fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
-fprint(RESULT, L, fo(TempString));
-
--- direct inclusion of string in fprint should give whole string
-fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
-fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
-fprint(RESULT, L, TempString & "\n");
-
--- influence of given width
-
-fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
-               "-- pad the remaining with blanco's according to the given justification\n");
-fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
-fprint(RESULT, L, "%5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
-fprint(RESULT, L, "%-5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
-fprint(RESULT, L, "%9s", TempString);
-fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
-                "-- will output the string with the minimum of characters needed\n");
-fprint(RESULT, L, "\n--with specified width,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
-fprint(RESULT, L, "%2s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
-fprint(RESULT, L, "%4s", TempString);
-
-fprint(RESULT, L,
-       "\n\n------------------------------------\n" &
-         "-- Support for bit-oriented types --\n" &
-         "------------------------------------\n"
-      );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
-                   "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
-                   "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-
-  
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
-                   "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
-	           ">                   fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
-                   ">                   fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
-                   ">       );\n"
-       );
-  
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
-	          fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
-                  fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Alignment\n-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Bitvectors with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-
-fprint(RESULT, L, "Bitvectors with \%1r:  %4{%1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2r:  %4{%2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3r:  %4{%3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4r:  %4{%4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5r:  %4{%5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6r:  %4{%6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7r:  %4{%7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8r:  %4{%8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9r:  %4{%9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r:  %4{%-1r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2r:  %4{%-2r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3r:  %4{%-3r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4r:  %4{%-4r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5r:  %4{%-5r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6r:  %4{%-6r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7r:  %4{%-7r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8r:  %4{%-8r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9r:  %4{%-9r|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d:  %4{%1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%2d:  %4{%2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%3d:  %4{%3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%4d:  %4{%4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%5d:  %4{%5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%6d:  %4{%6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%7d:  %4{%7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%8d:  %4{%8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%9d:  %4{%9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d:  %4{%-1d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-2d:  %4{%-2d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-3d:  %4{%-3d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-4d:  %4{%-4d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-5d:  %4{%-5d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-6d:  %4{%-6d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-7d:  %4{%-7d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-8d:  %4{%-8d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "Bitvectors with \%-9d:  %4{%-9d|} \n",
-                   fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
-       );
-fprint(RESULT, L, "\n");
-
-  
-  
-fprint(RESULT, L,
-       "\n-------------------------------\n" &
-         "-- Support for integer types --\n" &
-         "-------------------------------\n"
-      );
-
-fprint(RESULT, L,
-       "\n\n" &
-         "-- Template of the call: (<fs> stands for the format specifier)\n"
-      );
- 
-
-fprint(RESULT, L, "\n" & 
-                 "> fprint(RESULT, L, ""Integers with <fs>:    \%4{<fs>|}\\n"",\n" &
-		 ">                  fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-       
-                 ">       );\n"
-      );
-
-fprint(RESULT, L,
-       "\n" &
-         "-- Results of the call with various format specifiers\n\n"
-      );
-  
-  
-fprint(RESULT, L, "Integers with \%5d:    %4{%5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6d:    %4{%6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7d:    %4{%7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8d:    %4{%8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9d:    %4{%9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10d:   %4{%10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d:    %4{%-5d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6d:    %4{%-6d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7d:    %4{%-7d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8d:    %4{%-8d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9d:    %4{%-9d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10d:   %4{%-10d|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r:    %4{%5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%6r:    %4{%6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%7r:    %4{%7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%8r:    %4{%8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%9r:    %4{%9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%10r:   %4{%10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r:    %4{%-5r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-6r:    %4{%-6r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-7r:    %4{%-7r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-8r:    %4{%-8r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-9r:    %4{%-9r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "Integers with \%-10r:   %4{%-10r|} \n",
-		   fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
-      );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
-       "\n----------------------\n" &
-         "-- Support for time --\n" &
-         "----------------------\n"
-      );
-  
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
-                   "-- into an integer value (of nanoseconds)\n"
-       ); 
-fprint (RESULT, L, "> wait for 648 ns\n"); 
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); 
-
-wait for 648 ns;
-  
-fprint (RESULT, L, "The time is now %d ns\n", fo(now)); 
-
-  
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Erroneous calls and error messages --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
-                  "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
-      );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
- 
-fprint(RESULT, L, "\n");
-  
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
-                  "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
-                  "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
-      ); 
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
-       "\n----------------------------------------\n" &
-         "-- Things you wouldn't expect to work --\n" &
-         "----------------------------------------\n"
-      );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-  
-end process USAGE;
-  
-end TB;
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
deleted file mode 100644
index c5a4a92..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct  4 17:33:56 CEST 2001
-
-ANALYZER    = vcom -quiet -nologo
-ANALYZER_C  = vcom -quiet -nologo
-all : \
-	bin/tbe_pck_fio/tb.dat \
-	bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) 
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO 
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
-	bin/pck_fio/body.dat \
-	bin/pck_fio/_primary.dat \
-	TB_PCK_FIO_1987.vhd 
-	${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO(<body>) 
-
-bin/pck_fio/body.dat : \
-	bin/pck_fio/_primary.dat \
-	PCK_FIO_1987_BODY.vhd 
-	${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO 
-
-bin/pck_fio/_primary.dat : \
-	PCK_FIO_1987.vhd 
-	${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
deleted file mode 100644
index 0f9a351..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct  4 17:32:23 CEST 2001
-
-ANALYZER    = vcom -quiet -nologo -93
-ANALYZER_C  = vcom -quiet -nologo -93
-all : \
-	bin/tbe_pck_fio/tb.dat \
-	bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) 
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO 
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
-	bin/pck_fio/body.dat \
-	bin/pck_fio/_primary.dat \
-	TB_PCK_FIO_1993.vhd 
-	${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO(<body>) 
-
-bin/pck_fio/body.dat : \
-	bin/pck_fio/_primary.dat \
-	PCK_FIO_1993_BODY.vhd 
-	${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO 
-
-bin/pck_fio/_primary.dat : \
-	PCK_FIO_1993.vhd 
-	${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd
-
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd b/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd
deleted file mode 100644
index 63a59d4..0000000
Binary files a/lib/SDRAM/ddr_sdr_v1_4/doc/SDRAM_CTRL.vsd and /dev/null differ
diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
deleted file mode 100644
index ba54b14..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
+++ /dev/null
@@ -1,13 +0,0 @@
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
deleted file mode 100644
index 1f30d78..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl.wdo}
-view wave
-view structure
-view signals
-run 800us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
deleted file mode 100644
index 4a9d3f1..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
+++ /dev/null
@@ -1,93 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {14963876 ps} 0}
-configure wave -namecolwidth 184
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {14733925 ps} {15711632 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
deleted file mode 100644
index 4de7283..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl_fifo.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl_fifo
-do {tb_sdr_ctrl_fifo.wdo}
-view wave
-view structure
-view signals
-run 20us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
deleted file mode 100644
index bd233a2..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
+++ /dev/null
@@ -1,68 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd
-add wave -noupdate -divider {Read FIFO}
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/was_write
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw_next
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_empty
-add wave -noupdate -divider {Write FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw_next
-add wave -noupdate -divider {Command FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_full
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {13879998 ps} {13928553 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
deleted file mode 100644
index 7d046f8..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_r_rand_w.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
deleted file mode 100644
index d3d9e2b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_w_rand_r.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
deleted file mode 100644
index 832ec1b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl_rand_addr.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 1000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
deleted file mode 100644
index eb20b08..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
+++ /dev/null
@@ -1,82 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {60573747 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {60552548 ps} {60600861 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
deleted file mode 100644
index 0e41aef..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdr_ctrl_rand_rw.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 10000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
deleted file mode 100644
index e3087e6..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
+++ /dev/null
@@ -1,84 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {16004147 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {15914249 ps} {16324366 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
deleted file mode 100644
index b3be3ab..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
+++ /dev/null
@@ -1,28 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/reset_virtex4.vhd"
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_frontend.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdram_ctrl_frontend
-do {tb_sdram_ctrl_frontend.wdo}
-view wave
-view structure
-view signals
-run 40us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
deleted file mode 100644
index 5d5538e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
+++ /dev/null
@@ -1,48 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_in
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_out
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_data_vld
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {27802417 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {27712165 ps} {27944343 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
deleted file mode 100644
index c924c8c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,240 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee, work;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clockgen is
-	generic
-	(
-		read_phaseshift : integer := 0;
-		frequency_hz : integer := 100E6
-	);
-	port 
-	(
-		-- Clocks and Reset
-		rst				: in std_logic;   -- external async reset, low active
-		clk_in			: in std_logic;   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		: in std_logic;   -- feedback clock
-		read_clk0_out	: out std_logic;  -- Clock for DDR-SDRAM data capture, dcm#1 output 0°
-		read_clk270_out	: out std_logic;  -- Clock for DDR-SDRAM data capture, dcm#1 output 270°
-		sys_clk0_out	: out std_logic;  -- System clock, dcm#0 output 0°
-		sys_clk270_out	: out std_logic;  -- System clock, dcm#0 output 270°
-		locked_out		: out std_logic;  -- DCM locked status
-		error_out		: out std_logic   -- indicates DCM Errors
-	);
-
-end;
-
-architecture tech of clockgen is
-
-	constant CLKIN_PER 				: real := real(1000E6/frequency_hz);
-
-	signal locked					: unsigned(1 downto 0);
-	signal dcm_rst					: unsigned(1 downto 0);
-	signal read_clk0				: std_logic;
-	signal read_clk270				: std_logic;
-	signal read_clk0_bufg			: std_logic;
-	signal read_clk270_bufg			: std_logic;
-	signal sys_clk0					: std_logic;
-	signal sys_clk270				: std_logic;
-	signal sys_clk0_bufg			: std_logic;
-	signal sys_clk270_bufg			: std_logic;
-	signal dcm1_locked, dcm2_locked	: unsigned(2 downto 0);
-	signal cnt_q 					: unsigned(4 downto 0);
-
-	type STATE_TYPE is (s0, s1, s2, s3, s4);
-	signal state_q : STATE_TYPE;
-
-begin 
-
-	read_clk0_out	<= read_clk0_bufg;
-	read_clk270_out	<= read_clk270_bufg;
-	sys_clk0_out	<= sys_clk0_bufg;
-	sys_clk270_out	<= sys_clk270_bufg;
-
-bufg11: bufg
-	port map
-	(
-		o  => sys_clk0_bufg,  
-		i  => sys_clk0
-	);
-
-bufg12: bufg
-	port map (
-		o  => sys_clk270_bufg,  
-		i  => sys_clk270
-	);
-
-bufg13: bufg
-	port map
-	(
-		o  => read_clk0_bufg,  
-		i  => read_clk0
-	);
-
-bufg14: bufg
-	port map (
-		o  => read_clk270_bufg,  
-		i  => read_clk270
-	);
-
-	-------------------------------------------------------------------------------------------------------
-	-- Clock generation
-	-------------------------------------------------------------------------------------------------------
-   
-inst_DCM_BASE_0 : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map (
-		CLK0 => sys_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => sys_clk270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => locked(0),     -- DCM LOCK status output
-		CLKFB => clk_fb_in,       -- DCM clock feedback
-		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(0)            -- DCM asynchronous reset input
-	);
-
-	inst_DCM_BASE_1 : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map (
-		CLK0 => read_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => read_clk270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => locked(1),     -- DCM LOCK status output
-		CLKFB => read_clk0_bufg,       -- DCM clock feedback
-		CLKIN => clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(1)            -- DCM asynchronous reset input
-	);
-
-	dcm_rst(1) <= not locked(0);
-	
-dcm_fsm:
-	process(rst, clk_in)
-	begin
-		if rst = '1' then
-			state_q <= s0;
-			dcm_rst(0) <= '0';
-			cnt_q <= "11111";
-			error_out <= '0';
-			locked_out <= '0';
-			dcm1_locked <= (others => '0');
-			dcm2_locked <= (others => '0');
-		elsif rising_edge(clk_in) then
-			case state_q is
-			when s0 =>
-				state_q <= s1;
-
-			when s1 =>
-			cnt_q <= cnt_q - 1;
-				if cnt_q = 0 then
-					dcm_rst(0) <= '1';
-					state_q <= s2;
-				end if;
-
-			when s2 =>
-				cnt_q <= cnt_q - 1;
-				if cnt_q = 0 then
-					dcm_rst(0) <= '0';
-					state_q <= s3;
-				end if;
-
-			when s3 =>
-				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
-					state_q <= s4;
-					error_out <= '0';
-				end if;
-
-			when s4 =>
-				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
-					locked_out <= '1';
-				else
-					error_out <= '1';
-				end if;
-			end case;
-
-			-- synchronize 'dcm1_locked'
-			dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
-			dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
-
-		end if;
-	end process;
-
-end architecture tech;
-
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
deleted file mode 100644
index f5ab332..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd
+++ /dev/null
@@ -1,389 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: DDR physical layer (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity ddr_phy is
-	Port (
-		sys_rst			: in  STD_LOGIC;
-		sys_clk0		: in  STD_LOGIC;
-		sys_clk270		: in  STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_rd		: out user_tag_t;
-		u_tag_wr		: out user_tag_t;
-		read_clk		: in  STD_LOGIC;
-		phy_ctrl		: in  phy_ctrl_t;
-		part_ctrl		: in  part_ctrl_t;
-		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_dm_wr_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_dm_rd_in	: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_dm_rd_out	: out unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_data_vld	: out STD_LOGIC;
-		sdr_data_req_w	: out STD_LOGIC;
-		sdr_data_req_r	: out STD_LOGIC;
-		part_clk_p		: out STD_LOGIC;
-		part_clk_n		: out STD_LOGIC;
-		part_dm			: out unsigned(DDR_DM_WIDTH-1 downto 0);
-		part_dqs		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		part_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0);
-		part_ba			: out unsigned(DDR_BANK_WIDTH-1 downto 0);
-		part_addr		: out unsigned(DDR_ADDR_WIDTH-1 downto 0);
-		part_cs_n		: out STD_LOGIC;
-		part_we_n		: out STD_LOGIC;
-		part_cas_n		: out STD_LOGIC;
-		part_ras_n		: out STD_LOGIC;
-		part_cke		: out STD_LOGIC
-	);
-end ddr_phy;
-
-architecture tech of ddr_phy is
-
-	signal dqs_drive		: std_logic;
-	signal drive			: std_logic;
-	signal dqs				: unsigned(DDR_DQS_WIDTH-1 downto 0);  
-	signal dqs_zen			: unsigned(DDR_DQS_WIDTH-1 downto 0);  
-	signal dqs_rst			: std_logic;
-	signal ddr_data_w		: unsigned(DDR_DATA_WIDTH-1 downto 0);
-	signal data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal data_reg_r		: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal drive270			: unsigned(DDR_DATA_WIDTH-1 downto 0);
-	signal part_ctrl_reg	: part_ctrl_t;
-	signal we_reg			: std_logic;
-	signal read_en			: std_logic;
-	
-	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
-	signal u_tag_pipe : u_tag_array_t;
-	
-	type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal dm_out_pipe : dm_out_array_t;
-
-begin
-
-------------------------------------------------------------------------------------------------------------------------------------------------
-utag_pipe:
-	process(sys_rst, sys_clk0)
-	begin
-		if rising_edge(sys_clk0) then
-			for i in u_tag_pipe'length-1 downto 1 loop
-				u_tag_pipe(i) <= u_tag_pipe(i-1);
-			end loop;	
-			if phy_ctrl.utag_we = '1' then
-				u_tag_pipe(0) <= u_tag_in;
-			end if;	
-		end if;
-	end process;
-
-dmout_pipe:
-	process(sys_rst, sys_clk0)
-	begin
-		if rising_edge(sys_clk0) then
-			for i in dm_out_pipe'length-1 downto 1 loop
-				dm_out_pipe(i) <= dm_out_pipe(i-1);
-			end loop;	
-			if phy_ctrl.utag_we = '1' then
-				dm_out_pipe(0) <= sdr_dm_rd_in;
-			end if;	
-		end if;
-	end process;
-
-WE_REGISTER:
-	process(sys_rst, sys_clk0)
-	begin
-		if sys_rst = '1' then
-			we_reg <= '0';
-		elsif rising_edge(sys_clk0) then
-			we_reg	<= phy_ctrl.we;
-		end if;
-	end process;
-	
-DATA_DRIVE_GEN:
-	process(sys_clk0)
-	begin
-		if falling_edge(sys_clk0) then
-			dqs_rst		<= not we_reg;
-			drive 		<= we_reg;
-		end if;
-	end process;
-
-DQS_DRIVE_GEN:
-	process(sys_clk0)
-	variable p : unsigned(1 downto 0);
-	begin
-		if rising_edge(sys_clk0) then
-			if phy_ctrl.drive_en = '1' then
-				p := (others => '1');
-			else
-				p := p(p'left-1 downto 0) & '0';
-			end if;
-		end if;
-		dqs_drive <= p(p'left);
-	end process;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- SDRAM Clock
-ODDR_clk_p : ODDR
-	generic map
-	(
-		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-		INIT => '0',						-- Initial value for Q port ('1' or '0')
-		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
-	) 										
-	port map (
-		Q	=> part_clk_p,	-- 1-bit DDR output
-		C	=> sys_clk0,	-- 1-bit clock input
-		CE	=> '1',			-- 1-bit clock enable input
-		D1	=> '1',			-- 1-bit data input (positive edge)
-		D2	=> '0',			-- 1-bit data input (negative edge)
-		R	=> '0',			-- 1-bit reset input
-		S	=> '0' 			-- 1-bit set input
-	);
-
-ODDR_clk_n : ODDR
-	generic map
-	(
-		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-		INIT => '0',						-- Initial value for Q port ('1' or '0')
-		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
-	) 										
-	port map (
-		Q	=> part_clk_n,	-- 1-bit DDR output
-		C	=> sys_clk0,	-- 1-bit clock input
-		CE	=> '1',			-- 1-bit clock enable input
-		D1	=> '0',			-- 1-bit data input (positive edge)
-		D2	=> '1',			-- 1-bit data input (negative edge)
-		R	=> '0',			-- 1-bit reset input
-		S	=> '0' 			-- 1-bit set input
-	);
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data OUT DDR-FFs
-gen_ddr_data_out:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-	begin 
-	ODDR_data : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> ddr_data_w(n),						-- 1-bit DDR output
-			C	=> sys_clk270,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_data_w(n + DDR_DATA_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_data_w(n),						-- 1-bit data input (negative edge)
-			R	=> '0',									-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_ddr_data_out;
-
--- Sample tristate on clock90
-	process (sys_clk270)
-	begin  
-		if rising_edge(sys_clk270) then
-			for n in 0 to DDR_DATA_WIDTH-1 loop
-               drive270(n) <= drive;
-			end loop;
-		end if;
-	end process;
-
--- Output mux
-out_mux_data:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-		part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
-	end generate;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data-mask OUT DDR-FFs
-gen_ddr_dm_out:
-	for n in 0 to DDR_DM_WIDTH-1 generate
-	begin 
-	ODDR_dm : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> part_dm(n),							-- 1-bit DDR output
-			C	=> sys_clk270,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_dm_wr_in(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_dm_wr_in(n),						-- 1-bit data input (negative edge)
-			R	=> '0',									-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_ddr_dm_out;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- DQS OUT DDR-FFs
-gen_dqs_out:
-	for n in 0 to DDR_DQS_WIDTH-1 generate
-	begin 
-	ODDR_dqs : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "OPPOSITE_EDGE",			-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> dqs(n),								-- 1-bit DDR output
-			C	=> sys_clk0,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D2	=> '0',									-- 1-bit data input (positive edge)
-			D1	=> '1',									-- 1-bit data input (negative edge)
-			R	=> dqs_rst,								-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_dqs_out;
-
--- Tristate-Control fuer dqs      
-	process (sys_clk0) is
-	variable zctrl : boolean; 
-	begin
-		if rising_edge(sys_clk0) then
-			if dqs_drive = '1' then
-				zctrl := false;
-			else
-				zctrl := true;
-			end if;
-			if zctrl then 
-				dqs_zen <= (others => '1');
-			else
-				dqs_zen <= (others => '0');
-			end if;	
-		end if;
-	end process;
-
--- Tristate-Buffer fuer dqs      
-gen_out_mux_dqs:
-	for n in 0 to DDR_DQS_WIDTH-1 generate
-		part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
-	end generate gen_out_mux_dqs;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
-	process (sys_rst, sys_clk0) is
-	begin  
-		if sys_rst = '1' then
-			part_ctrl_reg.cmd		<= COMMAND(SD_DESELECT); 
-			part_ctrl_reg.ba		<= (others=>'0');
-			part_ctrl_reg.addr		<= (others=>'0');
-			part_ctrl_reg.cke		<= '0';
-		elsif rising_edge(sys_clk0) then
-			part_ctrl_reg <= part_ctrl;
-		end if;
-	end process;
-
-	process (sys_clk0) is
-	begin  
-		if falling_edge(sys_clk0) then
-			part_ras_n		<= part_ctrl_reg.cmd.ras_n;
-			part_cas_n		<= part_ctrl_reg.cmd.cas_n; 
-			part_we_n 		<= part_ctrl_reg.cmd.we_n; 
-			part_cs_n 		<= part_ctrl_reg.cmd.cs_n; 
-			part_ba   		<= part_ctrl_reg.ba; 
-			part_addr    	<= part_ctrl_reg.addr;
-			part_cke  		<= part_ctrl_reg.cke;
-		end if;
-	end process;
-
------------------------------------------------------------------
--- READ DATA Processing
------------------------------------------------------------------
-gen_ddr_data_in:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-	begin 
-	IDDR_data : IDDR 
-		generic map
-		(
-			DDR_CLK_EDGE	=> "SAME_EDGE",					-- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
-			INIT_Q1			=> '0', 						-- Initial value of Q1: '0' or '1'
-			INIT_Q2			=> '0',							-- Initial value of Q2: '0' or '1'
-			SRTYPE			=> "SYNC"						-- Set/Reset type: "SYNC" or "ASYNC" 
-		)
-		port map
-		(
-			Q1				=> data_r(n),					-- 1-bit output for positive edge of clock 
-			Q2				=> data_r(n + DDR_DATA_WIDTH),	-- 1-bit output for negative edge of clock
-			C				=> read_clk, 					-- 1-bit clock input
-			CE				=> read_en,						-- 1-bit clock enable input
-			D				=> part_data(n),				-- 1-bit DDR data input
-			R				=> '0',							-- 1-bit reset
-			S				=> '0' 							-- 1-bit set
-		);
-	end generate;
-
-
-data_sample_stage:
-	process (sys_clk0)
-	begin
-		if falling_edge(sys_clk0) then
-			data_reg_r	<= data_r;
-		end if;
-	end process;
-
-misc_flags_and_data_out:
-	process (sys_rst, sys_clk0)
-	variable p : unsigned(3 downto 0);
-	begin
-		if sys_rst = '1' then
-			p				:= (others => '0');
-			read_en			<= '0';
-			sdr_data_vld	<= '0';
-			sdr_data_req_w	<= '0';
-			sdr_data_req_r	<= '0';
-		elsif rising_edge(sys_clk0) then
-			sdr_data_r		<= data_reg_r;
-			if p(3) = '1' then
-				u_tag_rd		<= u_tag_pipe(4);
-				sdr_dm_rd_out	<= dm_out_pipe(4);
-			end if;	
-			if phy_ctrl.we = '1' then
-				u_tag_wr		<= u_tag_pipe(0);
-			end if;	
-			sdr_data_req_w	<= phy_ctrl.we;
-			sdr_data_req_r	<= phy_ctrl.re;
-			sdr_data_vld	<= p(3);
-			read_en			<= p(1);
-			if phy_ctrl.re = '1' then
-				p := p(p'left-1 downto 0) & '1';
-			else
-				p := p(p'left-1 downto 0) & '0';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
deleted file mode 100644
index 02ad3a7..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd
+++ /dev/null
@@ -1,111 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.fifo_ctrl_pkg.all;
-
-entity fifo_sync is
-	Generic (
-		addr_width			: natural := 4;
-		data_width			: natural := 8;
-		almost_full_thresh	: integer := 12;
-		almost_empty_thresh	: integer := 4
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-end fifo_sync;
-
-architecture Behavioral of fifo_sync is
-	
-	signal mem_we		: STD_LOGIC;
-	signal ptr_w		: unsigned (addr_width-1 downto 0);
-	signal ptr_r		: unsigned (addr_width-1 downto 0);
-	signal full			: STD_LOGIC;
-	signal empty		: STD_LOGIC;
-	signal almost_full	: STD_LOGIC;
-	signal almost_empty	: STD_LOGIC;
-	
-begin
-
-	mem_we <= we;
-	fifo_full <= full;
-	fifo_empty <= empty;
-	fifo_afull <= almost_full;
-	fifo_aempty <= almost_empty;
-
-	inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
-	GENERIC MAP
-	(
-		addr_width			=> addr_width,
-		almost_full_thresh	=> almost_full_thresh,
-		almost_empty_thresh	=> almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst			=>	rst,
-		clk			=>	clk,
-		we			=>	we,
-		re			=>	re,
-		ptr_w		=>	ptr_w,
-		ptr_r		=>	ptr_r,
-		fifo_full	=>	full,
-		fifo_empty	=>	empty,
-		fifo_afull	=>	almost_full,
-		fifo_aempty	=>	almost_empty
-
-	);
-
-	inst_dpram_1w1r: entity work.dpram_1w1r_dist
-	GENERIC MAP (
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP(
-		clka		=> clk,
-		clkb		=> clk,
-		en_a		=> '1',
-		en_b		=> '1',
-		we_a		=> mem_we,
-		addr_a		=> ptr_w,
-		addr_b		=> ptr_r,
-		din_a		=> data_w,
-		dout_b		=> data_r
-	);
-	
-end Behavioral;
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
deleted file mode 100644
index 356bb28..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd
+++ /dev/null
@@ -1,1320 +0,0 @@
------------------------------------------------------------------------------------------
---
---     File Name: MT46V16M16.VHD
---       Version: 2.1
---          Date: January 14th, 2002
---         Model: Behavioral
---     Simulator: NCDesktop      - http://www.cadence.com
---                ModelSim PE    - http://www.model.com
---
---  Dependencies: None
---
---        Author: Son P. Huynh
---         Email: sphuynh@micron.com
---         Phone: (208) 368-3825
---       Company: Micron Technology, Inc.
---   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
---
---   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
---
---    Limitation: Doesn't model internal refresh counter
---
---          Note: 
---
---    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
---                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
---                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
---                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
---                Copyright (c) 1998 Micron Semiconductor Products, Inc.
---                All rights researved
---
---  Rev  Author                        Date        Changes
---  ---  ----------------------------  ----------  -------------------------------------
---  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
---       Micron Technology, Inc.
---
---  2.0  Son P. Huynh                  11/08/2001  - Second release
---       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
---
------------------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-    USE IEEE.STD_LOGIC_1164.ALL;
-    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-    USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY MT46V16M16 IS
-    GENERIC (                                   -- Timing for -75Z CL2
-        tCK       : TIME    :=  7.500 ns;
-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tDH       : TIME    :=  0.500 ns;
-        tDS       : TIME    :=  0.500 ns;
-        tIH       : TIME    :=  0.900 ns;
-        tIS       : TIME    :=  0.900 ns;
-        tMRD      : TIME    := 15.000 ns;
-        tRAS      : TIME    := 40.000 ns;
-        tRAP      : TIME    := 20.000 ns;
-        tRC       : TIME    := 65.000 ns;
-        tRFC      : TIME    := 75.000 ns;
-        tRCD      : TIME    := 20.000 ns;
-        tRP       : TIME    := 20.000 ns;
-        tRRD      : TIME    := 15.000 ns;
-        tWR       : TIME    := 15.000 ns;
-        addr_bits : INTEGER := 13;
-        data_bits : INTEGER := 16;
-        cols_bits : INTEGER :=  9
-    );
-    PORT (
-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
-        Clk   : IN    STD_LOGIC;
-        Clk_n : IN    STD_LOGIC;
-        Cke   : IN    STD_LOGIC;
-        Cs_n  : IN    STD_LOGIC;
-        Ras_n : IN    STD_LOGIC;
-        Cas_n : IN    STD_LOGIC;
-        We_n  : IN    STD_LOGIC;
-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
-    );
-END MT46V16M16;
-
-ARCHITECTURE behave OF MT46V16M16 IS
-    -- Array for Read pipeline
-    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Write pipeline
-    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Auto Precharge
-    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-
-    -- Array for Manual Precharge
-    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    
-    -- Array for Burst Terminate
-    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
-    -- Array for Memory Access
-    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
-    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-
-    -- Data pair
-    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
-    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-    -- Mode Register
-    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-    
-    -- Command Decode Variables
-    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
-    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-    
-    -- Burst Length Decode Variables
-    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-    
-    -- Cas Latency Decode Variables
-    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-
-    -- Internal Control Signals
-    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-
-    -- System Clock
-    SIGNAL Sys_clk : STD_LOGIC := '0';
-
-    -- Dqs buffer
-    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-
-BEGIN
-    -- Strip the strength
-    Cs_in  <= To_X01 (Cs_n);
-    Ras_in <= To_X01 (Ras_n);
-    Cas_in <= To_X01 (Cas_n);
-    We_in  <= To_X01 (We_n);
-    
-    -- Commands Decode
-    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
-    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
-    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
-    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
-    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
-    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
-    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
-    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
-
-    -- Burst Length Decode
-    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
-    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
-    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-
-    -- CAS Latency Decode
-    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
-    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
-    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-
-    -- Dqs buffer
-    Dqs <= Dqs_out;
-
-    --
-    -- System Clock
-    --
-    int_clk : PROCESS (Clk, Clk_n)
-        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
-    begin
-        IF Clk = '1' AND Clk_n = '0' THEN
-            ClkZ := '1';
-            CkeZ := Cke;
-        ELSIF Clk = '0' AND Clk_n = '1' THEN
-            ClkZ := '0';
-        END IF;
-        Sys_clk <= CkeZ AND ClkZ;
-    END PROCESS;
-
-    --
-    -- Main Process
-    --
-    state_register : PROCESS
-        -- Precharge Variables
-        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-
-        -- Activate Variables
-        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
-        -- Data IO variables
-        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-
-        -- Internal address mux variables
-        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
-        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-
-        -- DLL Reset variables
-        VARIABLE DLL_enable : STD_LOGIC := '0';
-        VARIABLE DLL_reset : STD_LOGIC := '0';
-        VARIABLE DLL_done : STD_LOGIC := '0';
-        VARIABLE DLL_count : INTEGER := 0;
-        
-        -- Timing Check
-        VARIABLE MRD_chk : TIME := 0 ns;
-        VARIABLE RFC_chk : TIME := 0 ns;
-        VARIABLE RRD_chk : TIME := 0 ns;
-        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
-        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
-        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
-        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
-        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-
-        -- Read pipeline variables
-        VARIABLE Read_cmnd : Array_Read_cmnd;
-        VARIABLE Read_bank : Array_Read_bank;
-        VARIABLE Read_cols : Array_Read_cols;
-
-        -- Write pipeline variables
-        VARIABLE Write_cmnd : Array_Write_cmnd;
-        VARIABLE Write_bank : Array_Write_bank;
-        VARIABLE Write_cols : Array_Write_cols;
-
-        -- Auto Precharge variables
-        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
-        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
-        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
-
-        -- Manual Precharge variables
-        VARIABLE A10_precharge  : Array_A10_precharge;
-        VARIABLE Bank_precharge : Array_Bank_precharge;
-        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-
-        -- Burst Terminate variable
-        VARIABLE Cmnd_bst : Array_Cmnd_bst;
-
-        -- Memory Banks
-        VARIABLE Bank0 : Array_ram_stor;
-        VARIABLE Bank1 : Array_ram_stor;
-        VARIABLE Bank2 : Array_ram_stor;
-        VARIABLE Bank3 : Array_ram_stor;
-
-        -- Burst Counter
-        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-        -- Internal Dqs initialize
-        VARIABLE Dqs_int : STD_LOGIC := '0';
-
-        -- Data buffer for DM Mask
-        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-
-        --
-        -- Initialize empty rows
-        --
-        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
-            VARIABLE i, j : INTEGER := 0;
-        BEGIN
-            IF Bank = "00" THEN
-                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
-                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank0 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "01" THEN
-                IF Bank1 (Row_index) = NULL THEN
-                    Bank1 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank1 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "10" THEN
-                IF Bank2 (Row_index) = NULL THEN
-                    Bank2 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank2 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "11" THEN
-                IF Bank3 (Row_index) = NULL THEN
-                    Bank3 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank3 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            END IF;
-        END;
-
-        --
-        -- Burst Counter
-        --
-        PROCEDURE Burst_decode IS
-            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
-        BEGIN
-            -- Advance burst counter
-            Burst_counter := Burst_counter + 1;
-
-            -- Burst Type
-            IF Mode_reg (3) = '0' THEN
-                Cols_temp := Cols_addr + 1;
-            ELSIF Mode_reg (3) = '1' THEN
-                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
-                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
-                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
-            END IF;
-
-            -- Burst Length
-            IF Burst_length_2 = '1' THEN
-                Cols_addr (0) := Cols_temp (0);
-            ELSIF Burst_length_4 = '1' THEN
-                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
-            ELSIF Burst_length_8 = '1' THEN
-                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
-            ELSE
-                Cols_addr := Cols_temp;
-            END IF;
-
-            -- Data counter
-            IF Burst_length_2 = '1' THEN
-                IF Burst_counter >= 2 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_4 = '1' THEN
-                IF Burst_counter >= 4 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_8 = '1' THEN
-                IF Burst_counter >= 8 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            END IF;
-        END;
-
-    BEGIN
-        WAIT ON Sys_clk;
-
-        --
-        -- Manual Precharge Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- A10 Precharge Pipeline
-            A10_precharge(0) := A10_precharge(1);
-            A10_precharge(1) := A10_precharge(2);
-            A10_precharge(2) := A10_precharge(3);
-            A10_precharge(3) := A10_precharge(4);
-            A10_precharge(4) := A10_precharge(5);
-            A10_precharge(5) := A10_precharge(6);
-            A10_precharge(6) := A10_precharge(7);
-            A10_precharge(7) := A10_precharge(8);
-            A10_precharge(8) := '0';
-
-            -- Bank Precharge Pipeline
-            Bank_precharge(0) := Bank_precharge(1);
-            Bank_precharge(1) := Bank_precharge(2);
-            Bank_precharge(2) := Bank_precharge(3);
-            Bank_precharge(3) := Bank_precharge(4);
-            Bank_precharge(4) := Bank_precharge(5);
-            Bank_precharge(5) := Bank_precharge(6);
-            Bank_precharge(6) := Bank_precharge(7);
-            Bank_precharge(7) := Bank_precharge(8);
-            Bank_precharge(8) := "00";
-
-            -- Command Precharge Pipeline
-            Cmnd_precharge(0) := Cmnd_precharge(1);
-            Cmnd_precharge(1) := Cmnd_precharge(2);
-            Cmnd_precharge(2) := Cmnd_precharge(3);
-            Cmnd_precharge(3) := Cmnd_precharge(4);
-            Cmnd_precharge(4) := Cmnd_precharge(5);
-            Cmnd_precharge(5) := Cmnd_precharge(6);
-            Cmnd_precharge(6) := Cmnd_precharge(7);
-            Cmnd_precharge(7) := Cmnd_precharge(8);
-            Cmnd_precharge(8) := '0';
-
-            -- Terminate Read if same bank or all banks
-            IF ((Cmnd_precharge (0) = '1') AND
-                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
-                (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Burst Terminate Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Burst Terminate pipeline
-            Cmnd_bst (0) := Cmnd_bst (1);
-            Cmnd_bst (1) := Cmnd_bst (2);
-            Cmnd_bst (2) := Cmnd_bst (3);
-            Cmnd_bst (3) := Cmnd_bst (4);
-            Cmnd_bst (4) := Cmnd_bst (5);
-            Cmnd_bst (5) := Cmnd_bst (6);
-            Cmnd_bst (6) := Cmnd_bst (7);
-            Cmnd_bst (7) := Cmnd_bst (8);
-            Cmnd_bst (8) := '0';
-
-            -- Terminate current Read
-            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Dq and Dqs Drivers
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Read Command Pipeline
-            Read_cmnd (0) := Read_cmnd (1);
-            Read_cmnd (1) := Read_cmnd (2);
-            Read_cmnd (2) := Read_cmnd (3);
-            Read_cmnd (3) := Read_cmnd (4);
-            Read_cmnd (4) := Read_cmnd (5);
-            Read_cmnd (5) := Read_cmnd (6);
-            Read_cmnd (6) := Read_cmnd (7);
-            Read_cmnd (7) := Read_cmnd (8);
-            Read_cmnd (8) := '0';
-
-            -- Read Bank Pipeline
-            Read_bank (0) := Read_bank (1);
-            Read_bank (1) := Read_bank (2);
-            Read_bank (2) := Read_bank (3);
-            Read_bank (3) := Read_bank (4);
-            Read_bank (4) := Read_bank (5);
-            Read_bank (5) := Read_bank (6);
-            Read_bank (6) := Read_bank (7);
-            Read_bank (7) := Read_bank (8);
-            Read_bank (8) := "00";
-
-            -- Read Column Pipeline
-            Read_cols (0) := Read_cols (1);
-            Read_cols (1) := Read_cols (2);
-            Read_cols (2) := Read_cols (3);
-            Read_cols (3) := Read_cols (4);
-            Read_cols (4) := Read_cols (5);
-            Read_cols (5) := Read_cols (6);
-            Read_cols (6) := Read_cols (7);
-            Read_cols (7) := Read_cols (8);
-            Read_cols (8) := (OTHERS => '0');
-
-            -- Initialize Read command
-            IF Read_cmnd (0) = '1' THEN
-                Data_out_enable := '1';
-                Bank_addr := Read_bank (0);
-                Cols_addr := Read_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Toggle Dqs during Read command
-            IF Data_out_enable = '1' THEN
-                Dqs_int := '0';
-                IF Dqs_out = "00" THEN
-                    Dqs_out <= "11";
-                ELSIF Dqs_out = "11" THEN
-                    Dqs_out <= "00";
-                ELSE
-                    Dqs_out <= "00";
-                END IF;
-            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
-                Dqs_out <= "ZZ";
-            END IF;
-
-            -- Initialize Dqs for Read command
-            IF Read_cmnd (2) = '1' THEN
-                IF Data_out_enable = '0' THEN
-                    Dqs_int := '1';
-                    Dqs_out <= "00";
-                END IF;
-            END IF;
-
-            -- Read Latch
-            IF Data_out_enable = '1' THEN
-                -- Initialize Memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Output Data
-                CASE Bank_addr IS
-                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                END CASE;
-
-                --  Increase Burst Counter
-                Burst_decode;
-            ELSE
-                Dq <= (OTHERS => 'Z');
-            END IF;
-        END IF;
-
-        --
-        -- Write FIFO and DM Mask Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Write command pipeline
-            Write_cmnd (0) := Write_cmnd (1);
-            Write_cmnd (1) := Write_cmnd (2);
-            Write_cmnd (2) := '0';
-
-            -- Write command pipeline
-            Write_bank (0) := Write_bank (1);
-            Write_bank (1) := Write_bank (2);
-            Write_bank (2) := "00";
-
-            -- Write column pipeline
-            Write_cols (0) := Write_cols (1);
-            Write_cols (1) := Write_cols (2);
-            Write_cols (2) := (OTHERS => '0');
-
-            -- Initialize Write command
-            IF Write_cmnd (0) = '1' THEN
-                Data_in_enable := '1';
-                Bank_addr := Write_bank (0);
-                Cols_addr := Write_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Write data
-            IF Data_in_enable = '1' THEN
-                -- Initialize memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Write first data
-                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (0) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
-                    END IF;
-                    IF Dm_pair (1) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-
-                --  Increase Burst Counter
-                Burst_decode;
-
-                -- Write second data
-                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (2) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
-                    END IF;
-                    IF Dm_pair (3) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-                
-                -- Increase Burst Counter
-                Burst_decode;
-
-                -- tWR start and tWTR check
-                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
-                    CASE Bank_addr IS
-                        WHEN "00"   => WR_chk0 := NOW;
-                        WHEN "01"   => WR_chk1 := NOW;
-                        WHEN "10"   => WR_chk2 := NOW;
-                        WHEN OTHERS => WR_chk3 := NOW;
-                    END CASE;
-
-                    -- tWTR check
-                    ASSERT (Read_enable = '0')
-                        REPORT "tWTR violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Auto Precharge Calculation
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Precharge counter
-            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
-                Count_precharge (0) := Count_precharge (0) + 1;
-            END IF;
-            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
-                Count_precharge (1) := Count_precharge (1) + 1;
-            END IF;
-            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
-                Count_precharge (2) := Count_precharge (2) + 1;
-            END IF;
-            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
-                Count_precharge (3) := Count_precharge (3) + 1;
-            END IF;
-
-            -- Read with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  BL/2 cycles after command
-            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW;
-                    Read_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW;
-                    Read_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW;
-                    Read_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW;
-                    Read_precharge(3) := '0';
-                END IF;
-            END IF;
-
-            -- Write with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  Two clock after last burst
-            -- Since tWR is time base, the model will compensate tRP
-            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(3) := '0';
-                END IF;
-            END IF;
-        END IF;
-        
-        --
-        -- DLL Counter
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
-                DLL_count := DLL_count + 1;
-                IF (DLL_count >= 200) THEN
-                    DLL_done := '1';
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Control Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Auto Refresh
-            IF Aref_enable = '1' THEN
-                -- Auto Refresh to Auto Refresh
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All banks must be Precharge before Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Record current tRFC time
-                RFC_chk := NOW;
-            END IF;
-
-            -- Extended Load Mode Register
-            IF Ext_mode_enable = '1' THEN
-                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
-                    IF (Addr (0) = '0') THEN
-                        DLL_enable := '1';
-                    ELSE
-                        DLL_enable := '0';
-                    END IF;
-                END IF;
-                
-                -- Precharge to EMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Extended Mode Register"
-                    SEVERITY WARNING;
-                
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Extended Load Register"
-                    SEVERITY WARNING;
-
-                -- LMR/EMR to EMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Extended Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Load Mode Register
-            IF Mode_reg_enable = '1' THEN
-                -- Register mode
-                Mode_reg <= Addr;
-                
-                -- DLL Reset
-                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
-                    DLL_reset := '1';
-                    DLL_done  := '0';
-                    DLL_count := 0;
-                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is ENABLE: DLL RESET is require"
-                        SEVERITY WARNING;
-                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge to LMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- LMR/ELMR to LMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid Burst Length
-                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
-                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
-                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
-                    REPORT "Invalid Burst Length during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid CAS Latency
-                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
-                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
-                    REPORT "Invalid CAS Latency during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Active Block (latch Bank and Row Address)
-            IF Active_enable = '1' THEN
-                -- Activate an OPEN bank can corrupt data
-                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
-                        (Ba = "01" AND Act_b1 = '0') OR
-                        (Ba = "10" AND Act_b2 = '0') OR
-                        (Ba = "11" AND Act_b3 = '0'))
-                    REPORT "Bank is already activated - data can be corrupted"
-                    SEVERITY WARNING;
-
-                -- Activate Bank 0
-                IF Ba = "00" AND Pc_b0 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk0 >= tRC)
-                        REPORT "tRC violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk0 >= tRP)
-                        REPORT "tRP violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b0 := '1';
-                    Pc_b0 := '0';
-                    B0_row_addr := Addr;
-                    RC_chk0 := NOW;
-                    RCD_chk0 := NOW;
-                    RAS_chk0 := NOW;
-                    RAP_chk0 := NOW;
-                END IF;
-
-                -- Activate Bank 1
-                IF Ba = "01" AND Pc_b1 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk1 >= tRC)
-                        REPORT "tRC violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk1 >= tRP)
-                        REPORT "tRP violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b1 := '1';
-                    Pc_b1 := '0';
-                    B1_row_addr := Addr;
-                    RC_chk1 := NOW;
-                    RCD_chk1 := NOW;
-                    RAS_chk1 := NOW;
-                    RAP_chk1 := NOW;
-                END IF;
-
-                -- Activate Bank 2
-                IF Ba = "10" AND Pc_b2 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk2 >= tRC)
-                        REPORT "tRC violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk2 >= tRP)
-                        REPORT "tRP violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b2 := '1';
-                    Pc_b2 := '0';
-                    B2_row_addr := Addr;
-                    RC_chk2 := NOW;
-                    RCD_chk2 := NOW;
-                    RAS_chk2 := NOW;
-                    RAP_chk2 := NOW;
-                END IF;
-
-                -- Activate Bank 3
-                IF Ba = "11" AND Pc_b3 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk3 >= tRC)
-                        REPORT "tRC violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk3 >= tRP)
-                        REPORT "tRP violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b3 := '1';
-                    Pc_b3 := '0';
-                    B3_row_addr := Addr;
-                    RC_chk3 := NOW;
-                    RCD_chk3 := NOW;
-                    RAS_chk3 := NOW;
-                    RAP_chk3 := NOW;
-                END IF;
-
-                -- Activate Bank A to Activate Bank B
-                IF (Prev_bank /= Ba) THEN
-                    ASSERT (NOW - RRD_chk >= tRRD)
-                        REPORT "tRRD violation during Activate"
-                        SEVERITY WARNING;
-                END IF;
-                
-                -- AutoRefresh to Activate
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Activate"
-                    SEVERITY WARNING;
-                
-                -- Record Variables for Checking Violation
-                RRD_chk := NOW;
-                Prev_bank := Ba;
-            END IF;
-
-            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
-            IF Prech_enable = '1' THEN
-                -- EMR or LMR to Precharge
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Precharge"
-                    SEVERITY WARNING;
-
-                -- Precharge Bank 0
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
-                    Act_b0 := '0';
-                    Pc_b0 := '1';
-                    RP_chk0 := NOW;
-
-                    -- Activate to Precharge bank 0
-                    ASSERT (NOW - RAS_chk0 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk0 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 1
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
-                    Act_b1 := '0';
-                    Pc_b1 := '1';
-                    RP_chk1 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk1 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk1 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 2
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
-                    Act_b2 := '0';
-                    Pc_b2 := '1';
-                    RP_chk2 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk2 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk2 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 3
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
-                    Act_b3 := '0';
-                    Pc_b3 := '1';
-                    RP_chk3 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk3 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk3 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Pipeline for READ
-                IF CAS_latency_15 = '1' THEN
-                    A10_precharge  (3) := Addr(10);
-                    Bank_precharge (3) := Ba;
-                    Cmnd_precharge (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    A10_precharge  (4) := Addr(10);
-                    Bank_precharge (4) := Ba;
-                    Cmnd_precharge (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    A10_precharge  (5) := Addr(10);
-                    Bank_precharge (5) := Ba;
-                    Cmnd_precharge (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    A10_precharge  (6) := Addr(10);
-                    Bank_precharge (6) := Ba;
-                    Cmnd_precharge (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    A10_precharge  (8) := Addr(10);
-                    Bank_precharge (8) := Ba;
-                    Cmnd_precharge (8) := '1';
-                END IF;
-            END IF;
-
-            -- Burst Terminate
-            IF Burst_term = '1' THEN
-                -- Pipeline for Read
-                IF CAS_latency_15 = '1' THEN
-                    Cmnd_bst (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    Cmnd_bst (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    Cmnd_bst (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    Cmnd_bst (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    Cmnd_bst (8) := '1';
-                END IF;
-
-                -- Terminate Write
-                ASSERT (Data_in_enable = '0')
-                    REPORT "It's illegal to Burst Terminate a Write"
-                    SEVERITY WARNING;
-
-                -- Terminate Read with Auto Precharge
-                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
-                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
-                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
-                    SEVERITY WARNING;
-            END IF;
-
-            -- Read Command
-            IF Read_enable = '1' THEN
-                -- CAS Latency Pipeline
-                IF Cas_latency_15 = '1' THEN
-                    Read_cmnd (3) := '1';
-                    Read_bank (3) := Ba;
-                    Read_cols (3) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_2 = '1' THEN
-                    Read_cmnd (4) := '1';
-                    Read_bank (4) := Ba;
-                    Read_cols (4) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_25 = '1' THEN
-                    Read_cmnd (5) := '1';
-                    Read_bank (5) := Ba;
-                    Read_cols (5) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_3 = '1' THEN
-                    Read_cmnd (6) := '1';
-                    Read_bank (6) := Ba;
-                    Read_cols (6) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_4 = '1' THEN
-                    Read_cmnd (8) := '1';
-                    Read_bank (8) := Ba;
-                    Read_cols (8) := Addr (8 DOWNTO 0);
-                END IF;
-
-                -- Write to Read: Terminate Write Immediately
-                IF Data_in_enable = '1' THEN
-                    Data_in_enable := '0';
-                END IF;
-
-                -- Interrupting a Read with Auto Precharge (same bank only)
-                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Read
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Read"
-                    SEVERITY WARNING;
-
-                -- Activate to Read without Auto Precharge
-                IF Addr (10) = '0' THEN
-                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                        REPORT "tRCD violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Activate to Read with Auto Precharge
-                IF Addr (10) = '1' THEN
-                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
-                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
-                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
-                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
-                        REPORT "tRAP violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Read_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-
-                -- DLL Check
-                IF (DLL_reset = '1') THEN
-                    ASSERT (DLL_done = '1')
-                        REPORT "DLL RESET not complete"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-
-            -- Write Command
-            IF Write_enable = '1' THEN
-                -- Pipeline for Write
-                Write_cmnd (2) := '1';
-                Write_bank (2) := Ba;
-                Write_cols (2) := Addr (8 DOWNTO 0);
-
-                -- Interrupting a Write with Auto Precharge (same bank only)
-                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Write"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                    REPORT "tRCD violation during Write"
-                    SEVERITY WARNING;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Write_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-            END IF;
-        END IF;
-    END PROCESS;
-
-    --
-    -- Dqs Receiver
-    --
-    dqs_rcvrs : PROCESS
-        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
-        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    BEGIN
-        WAIT ON Dqs;
-        -- Latch data at posedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
-            Dq_temp := Dq;
-            Dm_temp := Dm;
-        END IF;
-        -- Latch data at negedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
-            Dq_pair <= (Dq & Dq_temp);
-            Dm_pair <= (Dm & Dm_temp);
-        END IF;
-    END PROCESS;
-
-    --
-    -- Setup timing checks
-    --
-    Setup_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk;
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIS)
-                REPORT "CKE Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIS)
-                REPORT "CS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIS)
-                REPORT "CAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIS)
-                REPORT "RAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIS)
-                REPORT "WE# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIS)
-                REPORT "ADDR Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIS)
-                REPORT "BA Setup time violation -- tIS"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-    --
-    -- Hold timing checks
-    --
-    Hold_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk'DELAYED (tIH);
-        IF Sys_clk'DELAYED (tIH) = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIH)
-                REPORT "CKE Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIH)
-                REPORT "CS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIH)
-                REPORT "CAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIH)
-                REPORT "RAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIH)
-                REPORT "WE# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIH)
-                REPORT "ADDR Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIH)
-                REPORT "BA Hold time violation -- tIH"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-END behave;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd
deleted file mode 100644
index 4f799c5..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd
+++ /dev/null
@@ -1,111 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Reset generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity reset is
-	port
-	(
-		clk			: in std_logic;
-		rst_in		: in std_logic;
-		rst_out		: out std_logic
-	);
-end;
-
-architecture tech of reset is
-   
-	signal rst : std_logic;
-	signal shift_pipe : std_logic_vector(3 downto 0);
-	attribute KEEP : string;
-	attribute KEEP of shift_pipe	: signal is "TRUE";
-
-begin
-   
-	rst <= shift_pipe(0);
-
-bufg_reset: bufg
-	port map
-	(
-		o  => rst_out,  
-		i  => rst
-	);
-	
-fdp0: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map 
-	(
-		d		=> rst_in,
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(3)
-	);
-
-fdp1: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-
-		d		=> shift_pipe(3),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(2)
-	);
-
-fdp2: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-		d		=> shift_pipe(2),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(1)
-	);
-
-fdp3: fdp
-	generic map 
-	(
-		init	=> '1'
-	)
-	port map
-	(
-
-		d		=> shift_pipe(1),
-		c		=> clk,
-		pre		=> '0',
-		q		=> shift_pipe(0)
-	);
-  
-end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
deleted file mode 100644
index a50b6e8..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd
+++ /dev/null
@@ -1,269 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM command controller
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_cmd is
-	Generic (BL 		: natural := 2);
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		enable			: in  STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_out		: out user_tag_t;
-		phy_ctrl		: out phy_ctrl_t;
-		cmd				: in  sdr_cmd_t;
-		cmd_we			: in  STD_LOGIC;
-		cmd_ack			: out STD_LOGIC;
-		col_addr		: in col_addr_t;
-		mode_word		: in  mode_word_t;
-		sdr_cmd_ctrl	: out sdr_cmd_lines_t;
-		sdr_addr		: out  sdr_addr_t;
-		sdr_ba			: out  sdr_ba_t
-	);
-end sdram_cmd;
-
-architecture behaviour of sdram_cmd is
-
-	signal st_sdr, st_sdr_next : sdr_state_t;
-	
-	signal cc_preset : natural range 0 to 10;
-	signal cc_load_en : std_logic;
-	signal cycle_finished : std_logic;
-
-	signal burst_preset : natural range 0 to 3;
-	signal burst_load_en : std_logic;
-	signal burst_finished : std_logic;
-
-begin
-
-	u_tag_out <= u_tag_in;
-	
-------------------------------------------------------------------------------------------
-
-fsm_sdr_state:
-	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
-	begin
-		st_sdr_next		<= st_sdr;
-		sdr_cmd_ctrl <= COMMAND(SD_NOP);
-		
-		cc_load_en <= '0';
-		cc_preset <= TIMING(cmd);
-		burst_load_en <= '0';
-		cmd_ack	<= '0';
-		burst_preset <= BL/2-1;
-		phy_ctrl.re <= '0';
-		phy_ctrl.drive_en <= '0';
-		phy_ctrl.we <= '0';
-		phy_ctrl.utag_we <= '0';
-		sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
-		sdr_ba	 <= mode_word(mode_word_t'left downto mode_word_t'left-1);
-		
-		case st_sdr is 
-		when PWR_DOWN =>
-			sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
-			if enable = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-			
-		when PRECHARGE =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-
-		when MODE =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-
-		when IDLE =>
-			if cmd_we = '1' then
-				cmd_ack <= '1';
-				cc_load_en <= '1';
-				cc_preset <= TIMING(cmd);
-				sdr_cmd_ctrl <= COMMAND(cmd);
-				case cmd is
-					when SD_PRE =>
-						st_sdr_next <= PRECHARGE;
-						sdr_addr(BIT_PRE_ALL)	<= mode_word(BIT_PRE_ALL);
-					when SD_LMR =>
-						st_sdr_next <= MODE;
-					when SD_ACT =>
-						st_sdr_next <= ROW_ACT;
-					when SD_AR =>
-						st_sdr_next <= AUTO_REF;
-					when others	=> null;
-					end case;	
-			end if;	
-				
-		when ROW_ACT =>
-			if cycle_finished = '1' then
-				if cmd_we = '1' then
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					cc_load_en <= '1';
-					cc_preset <= TIMING(cmd);
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					case cmd is
-					when SD_PRE =>
-						st_sdr_next <= PRECHARGE;
-					when SD_READ =>
-						phy_ctrl.utag_we <= '1';
-						st_sdr_next <= READ;
-						sdr_addr(col_addr_t'range) <= col_addr;
-					when SD_WRITE =>
-						phy_ctrl.utag_we <= '1';
-						phy_ctrl.drive_en <= '1';
-						st_sdr_next <= WRITE;
-						sdr_addr(col_addr_t'range) <= col_addr;
-					when others	=> null;
-					end case;	
-				end if;	
-			end if;	
-
-		when WRITE =>
-			phy_ctrl.drive_en <= '1';
-			phy_ctrl.we <= '1';
-			if burst_finished = '1' then
-				if cmd_we = '1' and cmd = SD_WRITE then
-					sdr_addr(col_addr_t'range) <= col_addr;
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					phy_ctrl.utag_we <= '1';
-				else	
-					phy_ctrl.drive_en <= '0';
-					cc_load_en <= '1';
-					cc_preset <= TIMING(SD_WRITE)+1;
-					st_sdr_next <= ROW_ACT;
-				end if;
-			end if;	
-
-		when READ =>
-			phy_ctrl.re <= '1';
-			if burst_finished = '1' then
-				if cmd_we = '1' and cmd = SD_READ then
-					sdr_addr(col_addr_t'range) <= col_addr;
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					phy_ctrl.utag_we <= '1';
-				else
-					cc_load_en <= '1';
-					cc_preset <= TIMING(SD_READ);
-					st_sdr_next <= ROW_ACT;
-				end if;
-			end if;	
-
-		when WRITE_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when READ_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when BURST_STOP =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-			
-		when SELF_REF =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-			
-		when PRE_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when ACT_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-		
-		when AUTO_REF =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-			
-		when others =>
-			st_sdr_next <= IDLE;
-		end case;
-		
-	end process;
-	
-fsm_sdr_state_next:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			st_sdr		<= PWR_DOWN;
-		elsif rising_edge(clk) then
-			st_sdr		<= st_sdr_next;
-		end if;
-	end process;
-	
-------------------------------------------------------------------------------------------
-cycle_counter:
-	process (rst, clk)
-	variable cycle_cnt : natural range 0 to 10;
-	begin
-		if rst = '1' then
-			cycle_cnt	:= 0;
-			cycle_finished	<= '0';
-		elsif rising_edge(clk) then
-			cycle_finished	<= '0';
-			if cc_load_en = '1' then
-				cycle_cnt := cc_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt := cycle_cnt - 1;
-			else
-				cycle_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-burst_counter:
-	process (rst, clk)
-	variable burst_cnt : natural range 0 to 3;
-	begin
-		if rst = '1' then
-			burst_cnt	:= 0;
-		elsif rising_edge(clk) then
-			burst_finished	<= '0';
-			if burst_load_en = '1' then
-				burst_cnt := burst_preset;
-			elsif burst_cnt /= 0 then
-				burst_cnt := burst_cnt - 1;
-			end if;	
-			if burst_cnt = 0 then
-				burst_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
deleted file mode 100644
index b62e085..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 16;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL : real := 7.8125; -- us
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : positive  := 2;   -- precharge command period
-	constant TRAS : positive  := 4;   -- active to precharge delay 
-	constant TRFC : positive  := 8;   -- auto refresh command period
-	constant TMRD : positive  := 2;   -- load mode register command cylce time
-	constant TRCD : positive  := 2;   -- active to read or write delay !
-	constant TWR  : positive  := 2;   -- write recovery time
-
-	constant PWR_UP_WAIT : natural := 1; -- µs
-	
-	subtype user_tag_t is unsigned(3 downto 0);
-	
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
deleted file mode 100644
index dbb5b80..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd
+++ /dev/null
@@ -1,487 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM main controller and user I/F
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity sdram_ctrl is
-	Generic
-	(
-		f_sysclk 		: natural := 100E6;
-		BL 				: natural := 2
-	);
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		u_busy			: out STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_out		: out user_tag_t;
-		u_addr			: in  user_addr_t;
-		u_cmd			: in  user_cmd_t;
-		u_cmd_we		: in  STD_LOGIC;
-		col_addr		: out col_addr_t;
-		sdr_cmd_busy	: in  STD_LOGIC;
-		sdr_cmd			: out  sdr_cmd_t;
-		sdr_cmd_we		: out  STD_LOGIC;
-		sdr_mode		: out  mode_word_t;
-		sdr_cke			: out  STD_LOGIC
-	);
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
-	constant LMR_BURST_LEN		: natural := NextExpBaseTwo(BL);
-
-	type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH);
-	signal st_ctrl, st_ctrl_next : ctrl_state_t;
-	
-	constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6);
-	signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
-	signal pwr_up_cnt_rst : std_logic;
-	signal pwr_up_finished : std_logic;
-
-	signal cycle_cnt : natural range 0 to 255;
-	signal cc_preset : natural range 0 to 255;
-	signal cc_load_en : std_logic;
-	signal cycle_finished : std_logic;
-
-	signal seq_cnt : natural range 0 to 31;
-	signal seq_rst_en : std_logic;
-	signal seq_cnt_en : std_logic;
-	
-	constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6);
-	signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
-	signal refresh_request : std_logic;
-	signal refresh_cnt_rst : std_logic;
-
-	signal addr_reg_load_en : std_logic;
-
-	signal u_tag_reg : user_tag_t;
-	signal bank_addr_reg : bank_addr_t;
-	signal row_addr_reg : row_addr_t;
-	signal col_addr_reg : col_addr_t;
-
-	signal u_bank_addr : bank_addr_t;
-	signal u_row_addr : row_addr_t;
-	signal u_col_addr : col_addr_t;
-
-	signal act_request : std_logic;
-	signal act_request_set : std_logic;
-	signal act_request_clr : std_logic;
-
-	type init_seq_rom_t is array (0 to 14) of init_seq_t;
-	
-	constant init_seq_rom : init_seq_rom_t :=
-	(
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_PRE,
-			mode_word	=> "000010000000000",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
-			wait_cycle	=> 200
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_PRE,
-			mode_word	=> "000010000000000",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_AR,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_AR,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
-			wait_cycle	=> 200
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		)
-	
-	);
-		
-begin
-
-	u_row_addr		<= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
-	u_bank_addr		<= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
-	u_col_addr		<= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
-
-------------------------------------------------------------------------------------------
-fsm_ctrl_state:
-	process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request)
-	begin
-
-		u_busy 				<= '1';
-		pwr_up_cnt_rst		<= '0';
-		cc_preset			<= init_seq_rom(seq_cnt).wait_cycle;
-		cc_load_en			<= '0';
-		sdr_cmd				<= init_seq_rom(seq_cnt).cmd;
-		sdr_cmd_we			<= '0';
-		sdr_mode			<= bank_addr_reg & row_addr_reg;
-		col_addr			<= col_addr_reg;
-		sdr_cke				<= '1';
-		seq_cnt_en			<= '0';
-		seq_rst_en			<= '0';
-		addr_reg_load_en	<= '0';
-		refresh_cnt_rst		<= '0';
-		act_request_set		<= '0';
-		act_request_clr		<= '0';
-		u_tag_out			<= u_tag_reg;
-		
-		st_ctrl_next		<= st_ctrl;
-		case st_ctrl is 
-		when RESET =>
-			sdr_cke			<= '0';
-			pwr_up_cnt_rst	<= '1';
-			st_ctrl_next	<= POWER_WAIT;
-			
-		when POWER_WAIT =>
-			sdr_cke			<= '0';
-			if pwr_up_finished = '1' then
-				seq_rst_en		<= '1';
-				st_ctrl_next	<= INIT;
-			end if;	
-
-		when INIT =>
-			sdr_mode	<= init_seq_rom(seq_cnt).mode_word;
-			sdr_cmd		<= init_seq_rom(seq_cnt).cmd;
-			cc_preset	<= init_seq_rom(seq_cnt).wait_cycle;
-			if seq_cnt = init_seq_rom_t'high then
-				act_request_set	<= '1';	
-				refresh_cnt_rst	<= '1';
-				st_ctrl_next	<= USER_READY;
-			elsif sdr_cmd_busy = '0' then
-				cc_load_en		<= '1';
-				sdr_cmd_we		<= '1';
-				st_ctrl_next	<= INIT_WAIT;
-			end if;	
-				
-		when INIT_WAIT =>
-			if sdr_cmd_busy = '0' and cycle_finished = '1' then
-				seq_cnt_en		<= '1';
-				st_ctrl_next	<= INIT;
-			end if;	
-			
-		when USER_READY =>
-			if sdr_cmd_busy = '0' then
-				if refresh_request = '1' then
-					sdr_mode(BIT_PRE_ALL) <= '1';
-					sdr_cmd_we		<= '1';
-					sdr_cmd			<= SD_PRE;
-					st_ctrl_next	<= REFRESH;
-				else	
-					u_busy		<= '0';
-					if u_cmd_we = '1' then
-						case u_cmd is
-						when UCMD_NOP =>
-							sdr_cmd		<= SD_NOP;
-						when UCMD_LMR =>
-							sdr_cmd		<= SD_NOP;
-						when UCMD_WRITE =>
-							col_addr				<= u_col_addr;
-							u_tag_out				<= u_tag_in;
-							sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
-							addr_reg_load_en		<= '1';
-							act_request_clr			<= '1';	
-							sdr_cmd					<= SD_WRITE;
-							if (u_row_addr /= row_addr_reg) or act_request = '1' then
-								st_ctrl_next		<= USER_WRITE_PRE;
-							elsif (u_bank_addr /= bank_addr_reg) then
-								if ENABLE_PRE_ALL = '1' then
-									st_ctrl_next		<= USER_WRITE_ACT;
-								else	
-									st_ctrl_next		<= USER_WRITE_PRE;
-								end if;	
-							elsif sdr_cmd_busy = '0' then
-								sdr_cmd_we			<= '1';
-							else
-								st_ctrl_next		<= USER_WRITE;
-							end if;
-						when UCMD_READ =>
-							col_addr				<= u_col_addr;
-							u_tag_out				<= u_tag_in;
-							sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
-							addr_reg_load_en		<= '1';
-							act_request_clr			<= '1';	
-							sdr_cmd					<= SD_READ;
-							if (u_row_addr /= row_addr_reg) or act_request = '1' then
-								st_ctrl_next		<= USER_READ_PRE;
-							elsif (u_bank_addr /= bank_addr_reg) then
-								if ENABLE_PRE_ALL = '1' then
-									st_ctrl_next		<= USER_READ_ACT;
-								else	
-									st_ctrl_next		<= USER_READ_PRE;
-								end if;	
-							elsif sdr_cmd_busy = '0' then
-								sdr_cmd_we			<= '1';
-							else
-								st_ctrl_next		<= USER_READ;
-							end if;
-						when others => null;
-						end case;
-					end if;	
-				end if;	
-			end if;	
-
-		when USER_WRITE_PRE =>
-		sdr_cmd			<= SD_PRE;
-		sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_WRITE_ACT;
-		end if;
-
-		when USER_WRITE_ACT =>
-		sdr_cmd			<= SD_ACT;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_WRITE;
-		end if;
-
-		when USER_WRITE =>
-		sdr_cmd			<= SD_WRITE;
-		sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-		end if;
-
-		when USER_READ_PRE =>
-		sdr_cmd			<= SD_PRE;
-		sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READ_ACT;
-		end if;
-
-		when USER_READ_ACT =>
-		sdr_cmd			<= SD_ACT;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READ;
-		end if;
-
-		when USER_READ =>
-		sdr_cmd			<= SD_READ;
-		sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-		end if;
-
-		when REFRESH =>
-		sdr_cmd			<= SD_AR;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-			refresh_cnt_rst	<= '1';
-			act_request_set	<= '1';	
-		end if;
-		
-		when others =>
-			st_ctrl_next <= RESET;
-		end case;
-		
-	end process;
-	
-fsm_ctrl_state_next:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			st_ctrl		<= RESET;
-		elsif rising_edge(clk) then
-			st_ctrl		<= st_ctrl_next;
-		end if;
-	end process;
-	
-------------------------------------------------------------------------------------------
-act_request_register:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			act_request <= '1';
-		elsif rising_edge(clk) then
-			if act_request_set = '1' then
-				act_request <= '1';
-			elsif act_request_clr = '1' then	
-				act_request <= '0';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-user_addr_register:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			bank_addr_reg <= (others => '0');
-			row_addr_reg <= (others => '0');
-			col_addr_reg <= (others => '0');
-			u_tag_reg <= (others => '0');
-		elsif rising_edge(clk) then
-			if addr_reg_load_en = '1' then
-				bank_addr_reg <= u_bank_addr;
-				row_addr_reg <= u_row_addr;
-				col_addr_reg <= u_col_addr;
-				u_tag_reg <= u_tag_in;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-power_up_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			pwr_up_cnt	<= 0;
-			pwr_up_finished <= '0';
-		elsif rising_edge(clk) then
-			pwr_up_finished <= '0';
-			if pwr_up_cnt_rst = '1' then
-				pwr_up_cnt	<= PWR_UP_CLOCK_INTERVAL-1;
-			else
-				if pwr_up_cnt /= 0 then
-					pwr_up_cnt <= pwr_up_cnt - 1;
-				else
-					pwr_up_finished <= '1';
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-
-------------------------------------------------------------------------------------------
-refresh_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			refresh_cnt	<= 0;
-			refresh_request <= '0';
-		elsif rising_edge(clk) then
-			refresh_request <= '0';
-			if refresh_cnt_rst = '1' then
-				refresh_cnt	<= REFRESH_CLOCK_INTERVAL-1;
-			else
-				if refresh_cnt /= 0 then
-					refresh_cnt <= refresh_cnt - 1;
-				else
-					refresh_request <= '1';
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-cycle_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			cycle_cnt	<= 0;
-			cycle_finished	<= '0';
-		elsif rising_edge(clk) then
-			cycle_finished	<= '0';
-			if cc_load_en = '1' then
-				cycle_cnt <= cc_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt <= cycle_cnt - 1;
-			else
-				cycle_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-seq_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			seq_cnt	<= 0;
-		elsif rising_edge(clk) then
-			if seq_rst_en = '1' then
-				seq_cnt <= 0;
-			elsif seq_cnt_en = '1' then
-				if seq_cnt /= init_seq_rom_t'high then
-					seq_cnt <= seq_cnt + 1;
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
deleted file mode 100644
index 268636e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_frontend is
-	Generic
-	(
-		BL 				: natural := 2;
-		f_sysclk 		: natural := 100E6;
-		read_phaseshift : integer := 0;
-		fifo_depth		: integer := 4
-	);
-	Port
-	(
-		sys_rst_in			: in  STD_LOGIC;
-		sys_clk_in			: in  STD_LOGIC;
-		sys_rst_out			: out  STD_LOGIC;
-		sys_clk_out			: out  STD_LOGIC;
-		sys_clk_fb			: in  STD_LOGIC;
-		
-		-- User interface
-		busy				: out STD_LOGIC;
-		en					: in  STD_LOGIC;
-		r_wn				: in  STD_LOGIC;
-		be					: in unsigned(SDR_DM_WIDTH-1 downto 0);
-		addr				: in  user_addr_t;
-		din					: in unsigned(SDR_DATA_WIDTH-1 downto 0);
-		dout				: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-		dout_re				: in  STD_LOGIC;
-		dout_vld			: out STD_LOGIC;
-		
-		-- SDRAM signals
-		sd_clk_p			: out  STD_LOGIC;
-		sd_clk_n			: out  STD_LOGIC;
-		sd_cke				: out  STD_LOGIC;
-		sd_cs_n				: out  STD_LOGIC;
-		sd_cas_n			: out  STD_LOGIC;
-		sd_ras_n			: out  STD_LOGIC;
-		sd_we_n				: out  STD_LOGIC;
-		sd_addr				: out  sdr_addr_t;
-		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
-		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-		
-	);
-end sdram_ctrl_frontend;
-
-architecture struct of sdram_ctrl_frontend is
-
-	-- Number of user data words for simulation
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-
-	signal u_addr			: user_addr_t;
-	signal u_tag_in			: user_tag_t;
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t;
-	signal u_cmd_we			: std_logic;
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_dm_rd_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_dm_rd_out		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal rdy				: std_logic;
-
-	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH;
-	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_re				: std_logic;
-	signal cat_fifo_we				: std_logic;
-	signal cat_fifo_full			: std_logic;
-	signal cat_fifo_empty			: std_logic;
---	signal cat_fifo_almost_full		: std_logic;
---	signal cat_fifo_almost_empty	: std_logic;
-
-	signal write_fifo_din			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal write_fifo_dout			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal write_fifo_re			: std_logic;
-	signal write_fifo_we			: std_logic;
-	signal write_fifo_full			: std_logic;
-	signal write_fifo_empty			: std_logic;
---	signal write_fifo_almost_full	: std_logic;
---	signal write_fifo_almost_empty	: std_logic;
-
-	signal read_fifo_din			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal read_fifo_dout			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal read_fifo_re				: std_logic;
-	signal read_fifo_we				: std_logic;
-	signal read_fifo_full			: std_logic;
-	signal read_fifo_empty			: std_logic;
---	signal read_fifo_almost_full	: std_logic;
---	signal read_fifo_almost_empty	: std_logic;
-
-	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
-	alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0);
-	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH);
-	alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0);
-
-	alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH);
-	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
-	alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH);
-	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
-
-	alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH);
-	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0);
-	alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH);
-	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0);
-	
-begin 
-   
-	-- Instantiate synchronous FIFO
-	inst_cat_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> CAT_FIFO_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	cat_fifo_we,
-		re			=>	cat_fifo_re,
-		fifo_full	=>	cat_fifo_full,
-		fifo_empty	=>	cat_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cat_fifo_din,
-		data_r		=>  cat_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_write_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  write_fifo_din,
-		data_r		=>  write_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_read_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> 2*DDR_DATA_WIDTH + SDR_DM_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  read_fifo_din,
-		data_r		=>  read_fifo_dout
-	);
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BL,
-		read_phaseshift => read_phaseshift,
-		f_sysclk 		=> f_sysclk
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> sys_rst_in,
-		sys_clk_in			=> sys_clk_in,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> sys_clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> open,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm_wr_in,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> sd_clk_p,
-		sd_clk_n			=> sd_clk_n,
-		sd_cke				=> sd_cke,
-		sd_cs_n				=> sd_cs_n,
-		sd_cas_n			=> sd_cas_n,
-		sd_ras_n			=> sd_ras_n,
-		sd_we_n				=> sd_we_n,
-		sd_addr				=> sd_addr,
-		sd_ba				=> sd_ba,
-		sd_dm				=> sd_dm,
-		sd_dqs				=> sd_dqs,
-		sd_data				=> sd_data
-		
-	);
-   
-------------------------------------------------------------------------------------------
-	sys_rst_out			<= rst_out;
-	sys_clk_out			<= clk_out;
-	busy				<= not rdy;
-	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full);
-	write_fifo_we 		<= en and not r_wn and rdy;
-	write_fifo_data_in	<= din;
-	write_fifo_dm_in	<= not be;
-	cat_fifo_we			<= en and rdy;
-	cmd_fifo_in			<= UCMD_WRITE when r_wn = '0' else UCMD_READ;
-	addr_fifo_in		<= addr;
-	dm_rd_fifo_in		<= not be;
-	tag_fifo_in			<= (others=>'0');
-	dout				<= read_fifo_data_out;
-	dout_vld			<= not read_fifo_empty;
-	
-	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
-	u_cmd				<= cmd_fifo_out;
-	u_addr				<= addr_fifo_out;
-	u_dm_rd_in			<= dm_rd_fifo_out;
-	u_dm_wr_in			<= write_fifo_dm_out;
-	u_tag_in			<= tag_fifo_out;
-	
-	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
-	cat_fifo_re			<= u_cmd_we;
-	u_data_w			<= write_fifo_data_out;
-	read_fifo_re 		<= (not read_fifo_empty) and dout_re;
-	read_fifo_we		<= u_data_vld;
-	read_fifo_data_in	<= u_data_r;	
-	read_fifo_dm_in		<= u_dm_rd_out;
-
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
deleted file mode 100644
index 19768a4..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd
+++ /dev/null
@@ -1,289 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Top-level put all together
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_top is
-	Generic
-	(
-		BL 				: natural := 2;
-		f_sysclk 		: natural := 100E6;
-		read_phaseshift : integer := 0
-	);
-	Port
-	(
-		sys_rst_in			: in  STD_LOGIC;
-		sys_clk_in			: in  STD_LOGIC;
-		sys_rst_out			: out STD_LOGIC;
-		sys_clk_out			: out STD_LOGIC;
-		sys_clk_fb			: in  STD_LOGIC;
-		
-		-- User interface
-		u_data_vld			: out STD_LOGIC;
-		u_data_req_w		: out STD_LOGIC;
-		u_data_req_r		: out STD_LOGIC;
-		u_busy				: out STD_LOGIC;
-		u_tag_in			: in  user_tag_t;
-		u_tag_rd			: out user_tag_t;
-		u_tag_wr			: out user_tag_t;
-		u_addr				: in  user_addr_t;
-		u_cmd				: in  user_cmd_t;
-		u_cmd_we			: in  STD_LOGIC;
-		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		u_dm_wr_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_dm_rd_in			: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_dm_rd_out			: out unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-		
-		-- SDRAM signals
-		sd_clk_p			: out  STD_LOGIC;
-		sd_clk_n			: out  STD_LOGIC;
-		sd_cke				: out  STD_LOGIC;
-		sd_cs_n				: out  STD_LOGIC;
-		sd_cas_n			: out  STD_LOGIC;
-		sd_ras_n			: out  STD_LOGIC;
-		sd_we_n				: out  STD_LOGIC;
-		sd_addr				: out  sdr_addr_t;
-		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out  unsigned(DDR_DM_WIDTH-1 downto 0);
-		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-		
-	);
-end sdram_ctrl_top;
-
-architecture rtl of sdram_ctrl_top is
-
-	signal clk0				: std_logic;
-	signal clk270			: std_logic;
-	signal read_clk270		: std_logic;
-
-	signal phy_ctrl			: phy_ctrl_t;
-
-	signal u_tag			: user_tag_t;
-	signal sd_cmd_in		: sdr_cmd_t;
-	signal sd_cmd			: sdr_cmd_t;
-	signal sd_cmd_we		: std_logic;
-	signal cmd_ctrl			: sdr_cmd_lines_t;
-	signal cke				: std_logic;
-	signal ba				: unsigned(DDR_BANK_WIDTH-1 downto 0);
-	signal addr				: unsigned(DDR_ADDR_WIDTH-1 downto 0);
-
-	-- Clock generator
-
-	signal cg_rst			: std_logic;  
-	signal cg_read_clk0		: std_logic;  
-	signal cg_read_clk270	: std_logic;  
-	signal cg_sys_clk0		: std_logic;  
-	signal cg_sys_clk270	: std_logic;  
-	signal cg_locked		: std_logic;  
-	signal cg_error			: std_logic;  
-	signal ctrl_rst			: std_logic;  
-	signal part_ctrl		: part_ctrl_t;  
-
-	-- SD command FIFO
-
-	constant CMD_FIFO_ADDR_WIDTH	: positive := 2;
-	constant CMD_FIFO_DATA_WIDTH	: positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
-	signal cmd_fifo_din				: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
-	signal cmd_fifo_dout			: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
-	signal cmd_fifo_re				: std_logic;
-	signal cmd_fifo_we				: std_logic;
-	signal cmd_fifo_full			: std_logic;
-	signal cmd_fifo_empty			: std_logic;
-
-	alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
-	alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
-	alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
-	alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
-	alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
-	alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
-	alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
-	alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
-begin 
-      	
-	---------------------------------
-	clk0			<= cg_sys_clk0;
-	clk270			<= cg_sys_clk270;
-	read_clk270		<= cg_read_clk270;
-	cg_rst			<= not cg_locked;
-	
-	---------------------------------
-	sys_clk_out		<= cg_sys_clk0;
-	sys_rst_out		<= ctrl_rst;
-	
-	---------------------------------
-	part_ctrl.cmd	<= cmd_ctrl;
-	part_ctrl.ba	<= ba;
-	part_ctrl.addr	<= addr;
-	part_ctrl.cke	<= cke;
-
-	---------------------------------
-	sd_cmd_we		<= not cmd_fifo_empty;
-	cmd_fifo_in		<= to_unsigned(sd_cmd_in, 4);
-	sd_cmd			<= sdr_cmd_t(to_integer(cmd_fifo_out));
-
-	---------------------------------
-	inst_reset: entity work.reset
-	port map
-	(
-		clk					=> clk0,
-		rst_in				=> cg_rst,
-		rst_out				=> ctrl_rst
-	);
-	
-	inst_clockgen : entity work.clockgen
-	generic map
-	(
-		read_phaseshift => read_phaseshift,
-		frequency_hz  => f_sysclk
-	)
-	port map
-	(
-		rst					=> sys_rst_in,
-		clk_in				=> sys_clk_in,
-		clk_fb_in			=> sys_clk_fb,
-		read_clk0_out		=> cg_read_clk0,
-		read_clk270_out		=> cg_read_clk270,
-		sys_clk0_out		=> cg_sys_clk0,
-		sys_clk270_out		=> cg_sys_clk270,
-		locked_out			=> cg_locked,
-		error_out			=> cg_error
-	);
-   
-	-- Main controller
-	inst_sdram_ctrl : entity work.sdram_ctrl
-	Generic map 
-	(
-		f_sysclk	=> 100E6,
-		BL			=> BL
-	)
-	Port map 
-	(
-		rst				=> ctrl_rst,
-		clk				=> clk0,
-		u_busy			=> u_busy,
-		u_tag_in		=> u_tag_in,
-		u_tag_out		=> tag_fifo_in,
-		u_cmd			=> u_cmd,
-		u_cmd_we		=> u_cmd_we,
-		u_addr			=> u_addr,
-		sdr_cmd_busy	=> cmd_fifo_full,
-		sdr_cmd			=> sd_cmd_in,
-		sdr_cmd_we		=> cmd_fifo_we,
-		col_addr		=> col_fifo_in,
-		sdr_mode		=> mode_fifo_in,
-		sdr_cke			=> cke
-	);
-   
-	-- Instantiate synchronous FIFO
-	inst_sd_cmd_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> CMD_FIFO_ADDR_WIDTH,
-		data_width			=> CMD_FIFO_DATA_WIDTH,
-		almost_full_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1),
-		almost_empty_thresh	=> 2**(CMD_FIFO_ADDR_WIDTH-1)
-	)
-	PORT MAP
-	(
-		rst			=>	ctrl_rst,
-		clk			=>	clk0,
-		we			=>	cmd_fifo_we,
-		re			=>	cmd_fifo_re,
-		fifo_full	=>	cmd_fifo_full,
-		fifo_empty	=>	cmd_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cmd_fifo_din,
-		data_r		=>  cmd_fifo_dout
-	);
-
-	-- DDR SDRAM command fsm
-	inst_sdram_cmd : entity work.sdram_cmd
-	Generic map
-	(
-		BL				=> BL
-	)
-	Port map
-	(
-		rst				=> ctrl_rst,
-		clk				=> clk0,
-		u_tag_in		=> tag_fifo_out,
-		u_tag_out		=> u_tag,
-		phy_ctrl		=> phy_ctrl,
-		enable			=> cke,
-		cmd				=> sd_cmd,
-		cmd_we			=> sd_cmd_we,
-		cmd_ack			=> cmd_fifo_re,
-		sdr_cmd_ctrl	=> cmd_ctrl,
-		col_addr		=> col_fifo_out,
-		mode_word		=> mode_fifo_out,
-		sdr_ba			=> ba,
-		sdr_addr		=> addr
-	);
-   
-	-- DDR phy
-	inst_ddr_phy : entity work.ddr_phy
-	Port map
-	(
-		sys_rst			=> ctrl_rst,
-		sys_clk0		=> clk0,
-		sys_clk270		=> clk270,
-		u_tag_in		=> u_tag,
-		u_tag_rd		=> u_tag_rd,
-		u_tag_wr		=> u_tag_wr,
-		read_clk		=> read_clk270,
-		phy_ctrl		=> phy_ctrl,
-		part_ctrl		=> part_ctrl,
-		sdr_data_req_w	=> u_data_req_w,
-		sdr_data_req_r	=> u_data_req_r,
-		sdr_data_w		=> u_data_wr,
-		sdr_dm_wr_in	=> u_dm_wr_in,
-		sdr_dm_rd_in	=> u_dm_rd_in,
-		sdr_dm_rd_out	=> u_dm_rd_out,
-		sdr_data_r		=> u_data_rd,
-		sdr_data_vld	=> u_data_vld,
-		part_clk_p		=> sd_clk_p,
-		part_clk_n		=> sd_clk_n,
-		part_addr		=> sd_addr,
-		part_ba			=> sd_ba,
-		part_dm			=> sd_dm,
-		part_dqs		=> sd_dqs,
-		part_data		=> sd_data,
-		part_cs_n		=> sd_cs_n,
-		part_we_n		=> sd_we_n,
-		part_cas_n		=> sd_cas_n,
-		part_ras_n		=> sd_ras_n,
-		part_cke		=> sd_cke
-	);
-   
-end architecture rtl;
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
deleted file mode 100644
index d235d75..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd
+++ /dev/null
@@ -1,133 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Type definitions
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.sdram_config.all;
-
-package sdram_types is
-
-	-----------------------------------------------------------------------------------------
-	-- Table of Timing Parameters as a function of operation
-
-	-- Derived constants from sdram_config
-
-	constant DDR_DQS_WIDTH  	: positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
-	constant DDR_DM_WIDTH   	: positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
-	constant SDR_DATA_WIDTH 	: positive := 2*DDR_DATA_WIDTH;  -- 
-	constant SDR_DM_WIDTH		: positive := 2*DDR_DM_WIDTH;  -- 
-
-	subtype user_cmd_t is unsigned(1 downto 0);
-	constant UCMD_NOP			: user_cmd_t := "00";
-	constant UCMD_READ			: user_cmd_t := "01";
-	constant UCMD_WRITE			: user_cmd_t := "10";
-	constant UCMD_LMR			: user_cmd_t := "11";
-
-	subtype sdr_cmd_t is natural range 0 to 9;
-	constant SD_DESELECT		: sdr_cmd_t := 0;
-	constant SD_NOP				: sdr_cmd_t := 1;
-	constant SD_LMR				: sdr_cmd_t := 2;
-	constant SD_ACT				: sdr_cmd_t := 3;
-	constant SD_READ			: sdr_cmd_t := 4;
-	constant SD_WRITE			: sdr_cmd_t := 5;
-	constant SD_PRE				: sdr_cmd_t := 6;
-	constant SD_BST				: sdr_cmd_t := 7;
-	constant SD_AR				: sdr_cmd_t := 8;
-	constant SD_SR				: sdr_cmd_t := 9;
-	
-	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
-	subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
-	subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
-	subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
-	subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
-
-	subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
-	subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
-	subtype col_addr_t is unsigned(8 downto 0);
-	
-	subtype cycle_cnt_t is natural range 0 to 10;
-	
-	type phy_ctrl_t is
-	record
-		drive_en		: std_logic;
-		re				: std_logic;
-		we				: std_logic;
-		utag_we			: std_logic;
-	end record phy_ctrl_t;
-
-	type sdr_cmd_lines_t is
-	record
-         cs_n    : std_logic;
-         ras_n   : std_logic;
-         cas_n   : std_logic;
-         we_n    : std_logic;
-	end record sdr_cmd_lines_t;
-
-	type part_ctrl_t is
-	record
-		cmd		: sdr_cmd_lines_t;
-		ba	 	: unsigned(DDR_BANK_WIDTH-1 downto 0);
-		addr	: unsigned(DDR_ADDR_WIDTH-1 downto 0);
-		cke		: std_logic;
-	end record part_ctrl_t;
-	
-	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
-	constant COMMAND : part_cmd_array_t :=
-	--	 command                 cs_n     ras_qn      cas_qn      we_qn
-	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
-		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
-		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
-		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
-		SD_READ             =>   (   '0',      '1',        '0',        '1'),
-		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
-		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
-		SD_BST              =>   (   '0',      '1',        '1',        '0'),
-		SD_AR               =>   (   '0',      '0',        '0',        '1'),
-		SD_SR               =>   (   '0',      '0',        '0',        '1')
-	);
-
-	type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
-	constant TIMING : part_timing_array_t :=
-	--	 command                 cycle_cnt
-	(	SD_DESELECT         =>   (     0        ),
-		SD_NOP              =>   (     0        ),
-		SD_LMR              =>   (     TMRD-1   ),
-		SD_ACT              =>   (     TRCD-1   ),
-		SD_READ             =>   (     TCAS-1   ),
-		SD_WRITE            =>   (     TWR-1    ),
-		SD_PRE              =>   (     TRP-1    ),
-		SD_BST              =>   (     0        ),
-		SD_AR               =>   (     TRFC-1   ),
-		SD_SR               =>   (     TRFC-1   )
-	);
-
-	type init_seq_t is 
-	record
-		cmd			: sdr_cmd_t;
-		mode_word	: mode_word_t;
-		wait_cycle	: natural;
-	end record init_seq_t;	
-	
-end sdram_types;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
deleted file mode 100644
index 034215c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd
+++ /dev/null
@@ -1,336 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 8;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-	signal u_addr_cnt_en	: std_logic := '0';
-	signal u_addr_load		: std_logic := '0';
-	signal u_addr_preset	: user_addr_t := (others => '0');
-	signal u_addr_end		: user_addr_t := (others => '0');
-	signal ref_data			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	
-	type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
-	signal test_phase : test_phase_t := IDLE;
-	
-	type u_addr_mode_t is (MONOTONIC, RANDOM);
-	signal u_addr_mode		: u_addr_mode_t := MONOTONIC;
-	signal cycle_cnt		: natural := 1;
-	signal data_cnt			: natural := 0;
-	signal efficiency		: real := 0.0;
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_data_vld='1' then
-				if u_read_en = '1' then
-					assert (ref_data = u_data_r) report "Error on read!" severity failure;
-				end if;	
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_read_en = '0' then
-				last_data := (others => '0');
-				ref_data <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-W_DATA_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_req_wr = '1' then
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_write_en = '0' then
-				last_data := (others => '0');
-				u_data_w <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-ADDR_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_addr_load = '1' then
-				u_addr <= u_addr_preset;
-			elsif u_addr_cnt_en = '1' then
-				if u_addr_mode = MONOTONIC then
-					u_addr <= u_addr + BURST_LEN;
-				else
-					if u_addr(u_addr'left) = '1' then
-						if BURST_LEN = 2 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
-						elsif BURST_LEN = 4 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
-						elsif BURST_LEN = 8 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
-						end if;	
-					else
-						u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
-					end if;
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-performance_count:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if u_write_en = '1' or u_read_en = '1' then
-				cycle_cnt <= cycle_cnt + 1;
-				if u_req_wr = '1' or u_req_rd = '1' then
-					data_cnt <= data_cnt + 1;
-				end if;
-			else
-				cycle_cnt <= 1;
-				data_cnt <= 0;
-			end if;	
-		end if;	
-	end process;
-
-	u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
-	efficiency	<= real(data_cnt)/real(cycle_cnt);
-	u_cmd_we    <= (u_write_en or u_read_en) and (not u_busy);
-	u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-	
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	wait for 137*CLK_PERIOD;
-
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"008000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_WRITE;
-	u_write_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	wait until rising_edge(clk_out) and u_req_wr='0';
-	
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 1
-	u_addr_preset <= X"400000";
-	u_addr_end <= X"408000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_WRITE;
-	u_write_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	wait until rising_edge(clk_out) and u_req_wr='0';
-	
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"008000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_READ;
-	u_read_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 1
-	u_addr_preset <= X"400000";
-	u_addr_end <= X"408000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_READ;
-	u_read_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
deleted file mode 100644
index 51910b0..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd
+++ /dev/null
@@ -1,420 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdr_ctrl_fifo is
-end;
-
-architecture struct of tb_sdr_ctrl_fifo is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 2;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-
-	signal cmd_fifo_din				: unsigned(25 downto 0) := (others => '0');
-	signal cmd_fifo_dout			: unsigned(25 downto 0) := (others => '0');
-	signal cmd_fifo_re				: std_logic := '0';
-	signal cmd_fifo_we				: std_logic := '0';
-	signal cmd_fifo_full			: std_logic := '0';
-	signal cmd_fifo_empty			: std_logic := '0';
-	signal cmd_fifo_almost_full		: std_logic := '0';
-	signal cmd_fifo_almost_empty	: std_logic := '0';
-
-	signal write_fifo_din			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal write_fifo_dout			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal write_fifo_re			: std_logic := '0';
-	signal write_fifo_we			: std_logic := '0';
-	signal write_fifo_full			: std_logic := '0';
-	signal write_fifo_empty			: std_logic := '0';
-	signal write_fifo_almost_full	: std_logic := '0';
-	signal write_fifo_almost_empty	: std_logic := '0';
-
-	signal read_fifo_din			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal read_fifo_dout			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal read_fifo_re				: std_logic := '0';
-	signal read_fifo_we				: std_logic := '0';
-	signal read_fifo_full			: std_logic := '0';
-	signal read_fifo_empty			: std_logic := '0';
-	signal read_fifo_almost_full	: std_logic := '0';
-	signal read_fifo_almost_empty	: std_logic := '0';
-
-	signal write_start	: std_logic := '1';
-	signal read_start	: std_logic := '1';
-	
-	alias cmd_fifo_in is cmd_fifo_din(25 downto 24);
-	alias addr_fifo_in is cmd_fifo_din(23 downto 0);
-	alias cmd_fifo_out is cmd_fifo_dout(25 downto 24);
-	alias addr_fifo_out is cmd_fifo_dout(23 downto 0);
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- Instantiate synchronous FIFO
-	inst_command_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> 8,
-		data_width	=> 2+24
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	cmd_fifo_we,
-		re			=>	cmd_fifo_re,
-		fifo_full	=>	cmd_fifo_full,
-		fifo_empty	=>	cmd_fifo_empty,
-		fifo_afull	=>	cmd_fifo_almost_full,
-		fifo_aempty	=>	cmd_fifo_almost_empty,
-		data_w		=>  cmd_fifo_din,
-		data_r		=>  cmd_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_write_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> 8,
-		data_width	=> 2*DDR_DATA_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	write_fifo_almost_full,
-		fifo_aempty	=>	write_fifo_almost_empty,
-		data_w		=>  write_fifo_din,
-		data_r		=>  write_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_read_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> 8,
-		data_width	=> 2*DDR_DATA_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	rst_out,
-		clk			=>	clk_out,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	read_fifo_almost_full,
-		fifo_aempty	=>	read_fifo_almost_empty,
-		data_w		=>  read_fifo_din,
-		data_r		=>  read_fifo_dout
-	);
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-	u_cmd_we		<= (not cmd_fifo_empty) and write_start and (not u_busy);
-	u_cmd			<= cmd_fifo_out;
-	u_addr			<= addr_fifo_out;
-
-	write_fifo_re	<= u_req_wr and (not write_fifo_empty);
-	cmd_fifo_re		<= u_cmd_we;
-	u_data_w		<= write_fifo_dout;
-	read_fifo_re 	<= (not read_fifo_empty) and read_start;
-	read_fifo_we	<= u_data_vld;
-	read_fifo_din	<= u_data_r;	
-
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait for 4*CLK_PERIOD;
-	wait until rising_edge(clk_out) and rst_out='0';
-
-
	write_fifo_we <= '1';
-	cmd_fifo_we	<= '1';
-	write_fifo_din <= X"01020304";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000000";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"05060708";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000002";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"00001111";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000004";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"22223333";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000006";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"44445555";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000008";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"66667777";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"00000a";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"88889999";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"00000c";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"AAAABBBB";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"00000e";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"CCCCDDDD";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000010";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"EEEEFFFF";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000012";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '0';
-	cmd_fifo_we <= '0';
-	
---	wait until rising_edge(clk_out) and u_busy='0';
---	write_start <= '1';
---	wait until rising_edge(clk_out) and write_fifo_empty='1';
-
-	write_fifo_we <= '1';
-	cmd_fifo_we	<= '1';
-	write_fifo_din <= X"01234567";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000014";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '0';
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"000014";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"89ABCDEF";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000016";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"11223344";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000018";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '0';
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"000010";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"55667788";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"00001a";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"99990000";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"00001c";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '1';
-	write_fifo_din <= X"AAAA5555";
-	cmd_fifo_in <= UCMD_WRITE;
-	addr_fifo_in <= X"000020";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '0';
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"000000";
-
-	wait until rising_edge(clk_out);
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"000018";
-
-	wait until rising_edge(clk_out);
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"00001A";
-
-	wait until rising_edge(clk_out);
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"00001C";
-
-	wait until rising_edge(clk_out);
-	cmd_fifo_in <= UCMD_READ;
-	addr_fifo_in <= X"000020";
-
-	wait until rising_edge(clk_out);
-	write_fifo_we <= '0';
-	cmd_fifo_we <= '0';
-
-	wait for 40*CLK_PERIOD;
-	read_start <= '1';
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
deleted file mode 100644
index 961b58e..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 8;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal lin_addr			: user_addr_t := (others => '0');
-	signal rand_gen			: unsigned(7 downto 0) := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-	signal rw_null_en		: std_logic := '0';
-	signal u_addr_cnt_en	: std_logic := '0';
-	signal u_addr_load		: std_logic := '0';
-	signal u_addr_preset	: user_addr_t := (others => '0');
-	signal u_addr_end		: user_addr_t := (others => '0');
-	signal ref_data			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	
-	type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
-	signal test_phase : test_phase_t := IDLE;
-	
-	type u_addr_mode_t is (MONOTONIC, RANDOM);
-	signal u_addr_mode		: u_addr_mode_t := MONOTONIC;
-	signal cycle_cnt		: natural := 1;
-	signal data_cnt			: natural := 0;
-	signal efficiency		: real := 0.0;
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_data_vld='1' then
-				if u_read_en = '1' and u_tag_rd = "0000" then
-					assert (ref_data = u_data_r) report "Error on read!" severity failure;
-					for i in 0 to DDR_DATA_WIDTH/4-1 loop
-						ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-					end loop;
-					last_data := last_data + DDR_DATA_WIDTH/4;
-				end if;	
-			elsif u_read_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				ref_data <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-W_DATA_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_req_wr = '1' and u_tag_wr = "0000" then
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_write_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				u_data_w <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-ADDR_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_addr_load = '1' then
-				lin_addr <= u_addr_preset;
-				rand_gen <= X"80";
-			elsif u_addr_cnt_en = '1' then
-				lin_addr <= lin_addr + BURST_LEN;
-				if rand_gen(rand_gen'left) = '1' then
-					rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
-				else
-					rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-performance_count:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if u_write_en = '1' or u_read_en = '1' then
-				cycle_cnt <= cycle_cnt + 1;
-				if u_req_wr = '1' or u_req_rd = '1' then
-					data_cnt <= data_cnt + 1;
-				end if;
-			else
-				cycle_cnt <= 1;
-				data_cnt <= 0;
-			end if;	
-		end if;	
-	end process;
-
-	u_tag_in <= "000" & rw_null_en;
-
-	efficiency	<= real(data_cnt)/real(cycle_cnt);
-	u_cmd_we    <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
-	u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
-	u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	wait for 137*CLK_PERIOD;
-
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= WRITE_MULTI;
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"010000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_READ;
-	u_write_en <= '1';
-	rw_null_en <= '1';
-	while lin_addr /= u_addr_end loop
-		u_cmd <= UCMD_READ;
-		rw_null_en <= '1';
-		if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
-			if rand_gen(1) = '1' or rand_gen(7) = '1' then
-				u_cmd <= UCMD_WRITE;
-			end if;	
-			rw_null_en <= '0';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	rw_null_en <= '0';
-	wait until rising_edge(clk_out) and u_req_wr='0';
-	wait for 200*CLK_PERIOD;
-		
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= READ_MULTI;
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"010000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_WRITE;
-	u_read_en <= '1';
-	rw_null_en <= '1';
-	while lin_addr /= u_addr_end loop
-		u_cmd <= UCMD_WRITE;
-		rw_null_en <= '1';
-		if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
-			if rand_gen(1) = '1' or rand_gen(7) = '1' then
-				u_cmd <= UCMD_READ;
-			end if;	
-			rw_null_en <= '0';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	rw_null_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
deleted file mode 100644
index 286fb33..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 8;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal lin_addr			: user_addr_t := (others => '0');
-	signal rand_gen			: unsigned(7 downto 0) := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-	signal rw_null_en		: std_logic := '0';
-	signal u_addr_cnt_en	: std_logic := '0';
-	signal u_addr_load		: std_logic := '0';
-	signal u_addr_preset	: user_addr_t := (others => '0');
-	signal u_addr_end		: user_addr_t := (others => '0');
-	signal ref_data			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	
-	type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
-	signal test_phase : test_phase_t := IDLE;
-	
-	type u_addr_mode_t is (MONOTONIC, RANDOM);
-	signal u_addr_mode		: u_addr_mode_t := MONOTONIC;
-	signal cycle_cnt		: natural := 1;
-	signal data_cnt			: natural := 0;
-	signal efficiency		: real := 0.0;
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_data_vld='1' then
-				if u_read_en = '1' and u_tag_rd = "0000" then
-					assert (ref_data = u_data_r) report "Error on read!" severity failure;
-					for i in 0 to DDR_DATA_WIDTH/4-1 loop
-						ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-					end loop;
-					last_data := last_data + DDR_DATA_WIDTH/4;
-				end if;	
-			elsif u_read_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				ref_data <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-W_DATA_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_req_wr = '1' and u_tag_wr = "0000" then
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_write_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				u_data_w <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-ADDR_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_addr_load = '1' then
-				lin_addr <= u_addr_preset;
-				rand_gen <= X"80";
-			elsif u_addr_cnt_en = '1' then
-				lin_addr <= lin_addr + BURST_LEN;
-				if rand_gen(rand_gen'left) = '1' then
-					rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010";
-				else
-					rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left);
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-performance_count:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if u_write_en = '1' or u_read_en = '1' then
-				cycle_cnt <= cycle_cnt + 1;
-				if u_req_wr = '1' or u_req_rd = '1' then
-					data_cnt <= data_cnt + 1;
-				end if;
-			else
-				cycle_cnt <= 1;
-				data_cnt <= 0;
-			end if;	
-		end if;	
-	end process;
-
-	u_tag_in <= "000" & rw_null_en;
-
-	efficiency	<= real(data_cnt)/real(cycle_cnt);
-	u_cmd_we    <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
-	u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0';
-	u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0);
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	wait for 137*CLK_PERIOD;
-
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= WRITE_MULTI;
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"010000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_WRITE;
-	u_write_en <= '1';
-	while lin_addr /= u_addr_end loop
-		u_cmd <= UCMD_WRITE;
-		rw_null_en <= '0';
-		if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
-			if rand_gen(1) = '1' or rand_gen(7) = '1' then
-				u_cmd <= UCMD_READ;
-			end if;	
-			rw_null_en <= '1';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	rw_null_en <= '0';
-	wait until rising_edge(clk_out) and u_req_wr='0';
-	wait for 200*CLK_PERIOD;
-		
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= READ_MULTI;
-	u_addr_preset <= X"000000";
-	u_addr_end <= X"010000"-BURST_LEN;
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_cmd <= UCMD_READ;
-	u_read_en <= '1';
-	while lin_addr /= u_addr_end loop
-		u_cmd <= UCMD_READ;
-		rw_null_en <= '0';
-		if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then
-			if rand_gen(1) = '1' or rand_gen(7) = '1' then
-				u_cmd <= UCMD_WRITE;
-			end if;	
-			rw_null_en <= '1';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	rw_null_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
deleted file mode 100644
index 5f96aa3..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd
+++ /dev/null
@@ -1,319 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 8;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-	signal u_addr_cnt_en	: std_logic := '0';
-	signal u_addr_load		: std_logic := '0';
-	signal u_addr_preset	: user_addr_t := (others => '0');
-	signal u_addr_end		: user_addr_t := (others => '0');
-	signal ref_data			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	
-	type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
-	signal test_phase : test_phase_t := IDLE;
-	
-	type u_addr_mode_t is (MONOTONIC, RANDOM);
-	signal u_addr_mode		: u_addr_mode_t := MONOTONIC;
-	signal cycle_cnt		: natural := 1;
-	signal data_cnt			: natural := 0;
-	signal efficiency		: real := 0.0;
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_data_vld='1' then
-				if u_read_en = '1' then
-					assert (ref_data = u_data_r) report "Error on read!" severity failure;
-				end if;	
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_read_en = '0' then
-				last_data := (others => '0');
-				ref_data <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-W_DATA_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_req_wr = '1' then
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_write_en = '0' then
-				last_data := (others => '0');
-				u_data_w <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-ADDR_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_addr_load = '1' then
-				u_addr <= u_addr_preset;
-			elsif u_addr_cnt_en = '1' then
-				if u_addr_mode = MONOTONIC then
-					u_addr <= u_addr + BURST_LEN;
-				else
-					if u_addr(u_addr'left) = '1' then
-						if BURST_LEN = 2 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
-						elsif BURST_LEN = 4 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
-						elsif BURST_LEN = 8 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
-						end if;	
-					else
-						u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
-					end if;
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-performance_count:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if u_write_en = '1' or u_read_en = '1' then
-				cycle_cnt <= cycle_cnt + 1;
-				if u_req_wr = '1' or u_req_rd = '1' then
-					data_cnt <= data_cnt + 1;
-				end if;
-			else
-				cycle_cnt <= 1;
-				data_cnt <= 0;
-			end if;	
-		end if;	
-	end process;
-
-	u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
-	efficiency	<= real(data_cnt)/real(cycle_cnt);
-	u_cmd_we    <= (u_write_en or u_read_en) and (not u_busy);
-	u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-	
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	wait for 137*CLK_PERIOD;
-
-
	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= WRITE_MULTI;
-	u_addr_preset <= X"800000";
-	if BURST_LEN = 2 then
-		u_addr_end <= X"5E2330";
-	elsif BURST_LEN = 4 then
-		u_addr_end <= X"7DEDD0";
-	elsif BURST_LEN = 8 then
-		u_addr_end <= X"5666B0";
-	end if;	
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_addr_mode <= RANDOM;
-	u_cmd <= UCMD_WRITE;
-	u_write_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	wait until rising_edge(clk_out) and u_req_wr='0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= READ_MULTI;
-	u_addr_preset <= X"800000";
-	if BURST_LEN = 2 then
-		u_addr_end <= X"5E2330";
-	elsif BURST_LEN = 4 then
-		u_addr_end <= X"7DEDD0";
-	elsif BURST_LEN = 8 then
-		u_addr_end <= X"5666B0";
-	end if;	
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_addr_mode <= RANDOM;
-	u_cmd <= UCMD_READ;
-	u_read_en <= '1';
-	while u_addr /= u_addr_end loop
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
deleted file mode 100644
index c60d600..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd
+++ /dev/null
@@ -1,333 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity tb_sdr_ctrl is
-end;
-
-architecture struct of tb_sdr_ctrl is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 2;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal u_addr			: user_addr_t := (others => '0');
-	signal u_tag_in			: user_tag_t := "0000";
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t := UCMD_NOP;
-	signal u_cmd_we			: std_logic := '0';
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_dm				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_in		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_dm_rd_out		: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000";
-	signal u_data_r			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal u_req_rd			: std_logic;
-	signal u_read_en		: std_logic := '0';
-	signal u_write_en		: std_logic := '0';
-	signal rw_null_en		: std_logic := '0';
-	signal u_addr_cnt_en	: std_logic := '0';
-	signal u_addr_load		: std_logic := '0';
-	signal u_addr_preset	: user_addr_t := (others => '0');
-	signal u_addr_end		: user_addr_t := (others => '0');
-	signal ref_data			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	
-	type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED);
-	signal test_phase : test_phase_t := IDLE;
-	
-	type u_addr_mode_t is (MONOTONIC, RANDOM);
-	signal u_addr_mode		: u_addr_mode_t := MONOTONIC;
-	signal cycle_cnt		: natural := 1;
-	signal data_cnt			: natural := 0;
-	signal efficiency		: real := 0.0;
-	
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_data_req_r		=> u_req_rd,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm_wr_in			=> u_dm,
-		u_dm_rd_in			=> u_dm_rd_in,
-		u_dm_rd_out			=> u_dm_rd_out,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-------------------------------------------------------------------------------------------
-
-R_DATA_COMPARE:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_data_vld='1' then
-				if u_read_en = '1' then
-					assert (ref_data = u_data_r) report "Error on read!" severity failure;
-				end if;	
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_read_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				ref_data <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-W_DATA_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_req_wr = '1' then
-				for i in 0 to DDR_DATA_WIDTH/4-1 loop
-					u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1;
-				end loop;
-				last_data := last_data + DDR_DATA_WIDTH/4;
-			elsif u_write_en = '0' and rw_null_en = '0' then
-				last_data := (others => '0');
-				u_data_w <= (others => '0');
-			end if;	
-		end if;	
-	end process;
-
-ADDR_GEN:
-	process(clk_out)
-	variable last_data : unsigned(7 downto 0) := (others => '0');
-	begin
-		if rising_edge(clk_out) then
-			if u_addr_load = '1' then
-				u_addr <= u_addr_preset;
-			elsif u_addr_cnt_en = '1' then
-				if u_addr_mode = MONOTONIC then
-					u_addr <= u_addr + BURST_LEN;
-				else
-					if u_addr(u_addr'left) = '1' then
-						if BURST_LEN = 2 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100";
-						elsif BURST_LEN = 4 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110";
-						elsif BURST_LEN = 8 then
-							u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100";
-						end if;	
-					else
-						u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left);
-					end if;
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-performance_count:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if u_write_en = '1' or u_read_en = '1' then
-				cycle_cnt <= cycle_cnt + 1;
-				if u_req_wr = '1' or u_req_rd = '1' then
-					data_cnt <= data_cnt + 1;
-				end if;
-			else
-				cycle_cnt <= 1;
-				data_cnt <= 0;
-			end if;	
-		end if;	
-	end process;
-
-	u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000";
-
-	efficiency	<= real(data_cnt)/real(cycle_cnt);
-	u_cmd_we    <= (u_write_en or u_read_en or rw_null_en) and (not u_busy);
-	u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0';
-	
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	wait for 137*CLK_PERIOD;
-
-	-- Bank 0
-	test_phase <= WRITE_MULTI;
-	u_addr_preset <= X"800000";
-	if BURST_LEN = 2 then
-		u_addr_end <= X"646808";
-	elsif BURST_LEN = 4 then
-		u_addr_end <= X"7DEDD0";
-	elsif BURST_LEN = 8 then
-		u_addr_end <= X"5666B0";
-	end if;	
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_addr_mode <= RANDOM;
-	while u_addr /= u_addr_end loop
-		u_cmd <= UCMD_WRITE;
-		u_write_en <= '1';
-		rw_null_en <= '0';
-		if u_addr(20) = '0' then
-			u_cmd <= UCMD_READ;
-			u_write_en <= '0';
-			rw_null_en <= '1';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_write_en <= '0';
-	rw_null_en <= '0';
-	wait for 200*CLK_PERIOD;
-
-	wait until rising_edge(clk_out) and u_busy='0';
-	-- Bank 0
-	test_phase <= READ_MULTI;
-	u_addr_preset <= X"800000";
-	if BURST_LEN = 2 then
-		u_addr_end <= X"646808";
-	elsif BURST_LEN = 4 then
-		u_addr_end <= X"7DEDD0";
-	elsif BURST_LEN = 8 then
-		u_addr_end <= X"5666B0";
-	end if;	
-	u_addr_load <= '1';
-	wait until rising_edge(clk_out);
-	u_addr_load <= '0';
-	wait until rising_edge(clk_out);
-	u_addr_mode <= RANDOM;
-	while u_addr /= u_addr_end loop
-		u_cmd <= UCMD_READ;
-		u_read_en <= '1';
-		rw_null_en <= '0';
-		if u_addr(20) = '0' then
-			u_cmd <= UCMD_WRITE;
-			u_read_en <= '0';
-			rw_null_en <= '1';
-		end if;	
-		wait until rising_edge(clk_out);
-	end loop;
-	u_read_en <= '0';
-	rw_null_en <= '0';
-	wait until rising_edge(clk_out) and u_data_vld='0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
deleted file mode 100644
index 95ffa58..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd
+++ /dev/null
@@ -1,385 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdram_ctrl_frontend is
-end;
-
-architecture struct of tb_sdram_ctrl_frontend is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant BURST_LEN		: natural := 2;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '0';  
-	signal rst_out			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal addr				: user_addr_t := (others => '0');
-	signal r_wn				: std_logic := '0';
-	signal en				: std_logic := '0';
-	signal busy				: std_logic;
-	signal din				: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal be				: unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111";
-	signal dout				: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-	signal dout_vld			: std_logic;
-	signal dout_re			: std_logic;
-	signal dout_reg			: unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-begin 
-   
-	clk_fb	<= part_clk_p after 1 ns;
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend
-	Generic map
-	(
-		BL 				=> BURST_LEN,
-		read_phaseshift => 0,
-		f_sysclk 		=> 100E6,
-		fifo_depth		=> 4
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> rst,
-		sys_clk_in			=> clk,
-
-		sys_rst_out			=> rst_out,
-		sys_clk_out			=> clk_out,
-		sys_clk_fb			=> clk_fb,
-		
-		busy				=> busy,
-		en					=> en,
-		r_wn				=> r_wn,
-		be					=> be,
-		addr				=> addr,
-		din					=> din,
-		dout				=> dout,
-		dout_re				=> dout_re,
-		dout_vld			=> dout_vld,
-		
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-   i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(part_data),
-         dqs   => std_logic_vector(part_dqs),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm)
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-read_register:
-	process(clk_out)
-	begin
-		if rising_edge(clk_out) then
-			if dout_vld = '1' then
-				dout_reg	<= dout;
-			end if;
-		end if;
-	end process;
-		
-------------------------------------------------------------------------------------------
-	dout_re	<= dout_vld;
-	
-	process
-	begin
-         
-	-- Write MAX_WORDS to DDR SDRAM Controller
-	wait for 4*CLK_PERIOD;
-	rst <= '0';
-
-	wait for 4*CLK_PERIOD;
-	wait until rising_edge(clk_out) and rst_out='0';
-
-	for i in 0 to 999 loop
-
		en		<= '1';
-		r_wn	<= '0';
-		din		<= to_unsigned(i, 32);
-		addr	<= to_unsigned(2*i, 24);
-		wait until rising_edge(clk_out) and busy = '0';
-	end loop;	
-
-	for i in 0 to 999 loop
-		en		<= '1';
-		r_wn	<= '1';
-		din		<= to_unsigned(i, 32);
-		addr	<= to_unsigned(2*i, 24);
-		wait until rising_edge(clk_out) and busy = '0';
-	end loop;	
-
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"01020304";
-	addr	<= X"000000";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"05060708";
-	addr	<= X"000002";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"00001111";
-	addr	<= X"000004";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"22223333";
-	addr	<= X"000006";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"44445555";
-	addr	<= X"000008";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"66667777";
-	addr	<= X"00000a";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"88889999";
-	addr	<= X"00000c";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"AAAABBBB";
-	addr	<= X"00000e";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"CCCCDDDD";
-	addr	<= X"000010";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"EEEEFFFF";
-	addr	<= X"000012";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"FFFFFFFF";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"87CCCCCC";
-	be		<= "1000";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"CC65CCCC";
-	be		<= "0100";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"CCCC43CC";
-	be		<= "0010";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"89ABCDEF";
-	addr	<= X"000016";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"CCCCCC21";
-	be		<= "0001";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"55555555";
-	be		<= "1010";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"AAAAAAAA";
-	be		<= "0101";
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '1';
-	addr	<= X"000014";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	be		<= "1111";
-	en		<= '1';
-	r_wn	<= '0';
-	din		<= X"11223344";
-	addr	<= X"000018";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr 	<= X"000010";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din 	<= X"55667788";
-	addr	<= X"00001a";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din <= X"99990000";
-	addr <= X"00001c";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en		<= '1';
-	r_wn	<= '0';
-	din 	<= X"AAAA5555";
-	addr 	<= X"000020";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr 	<= X"000000";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr 	<= X"000018";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr 	<= X"00001A";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr	 <= X"00001C";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	r_wn	<= '1';
-	addr 	<= X"000020";
-
-	wait until rising_edge(clk_out) and busy = '0';
-	en <= '0';
-
-	wait;
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd b/lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd
deleted file mode 100644
index 92e3c51..0000000
Binary files a/lib/SDRAM/ddr_sdr_v1_5/doc/SDRAM_CTRL.vsd and /dev/null differ
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk b/lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk
deleted file mode 100644
index 7529afd..0000000
Binary files a/lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
deleted file mode 100644
index d25b108..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo
+++ /dev/null
@@ -1,30 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_frontend64_wb.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdram_ctrl_frontend64_wb
-do {tb_sdram_ctrl_frontend64_wb.wdo}
-view wave
-view structure
-view signals
-run 200us
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
deleted file mode 100644
index f576e65..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo
+++ /dev/null
@@ -1,55 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_fb
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk0_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270var_o
-add wave -noupdate -divider Part
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {38990166 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {38975716 ps} {39081070 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
deleted file mode 100644
index 4b8b1e3..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo
+++ /dev/null
@@ -1,30 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../misc/clockgen_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_frontend_wb.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdram_ctrl_frontend_wb
-do {tb_sdram_ctrl_frontend_wb.wdo}
-view wave
-view structure
-view signals
-run 200us
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
deleted file mode 100644
index 20af0f9..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo
+++ /dev/null
@@ -1,62 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
-add wave -noupdate -divider DEBUG
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_re
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_we
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270var_o
-add wave -noupdate -divider Part
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {199427964 ps} {200030108 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
deleted file mode 100644
index 11021bc..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+++ /dev/null
@@ -1,367 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: DDR physical layer (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity ddr_phy is
-	Port (
-		sys_rst			: in  STD_LOGIC;
-		sys_clk0		: in  STD_LOGIC;
-		sys_clk270		: in  STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_rd		: out user_tag_t;
-		u_tag_wr		: out user_tag_t;
-		read_clk		: in  STD_LOGIC;
-		phy_ctrl		: in  phy_ctrl_t;
-		part_ctrl		: in  part_ctrl_t;
-		sdr_data_w		: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_dm			: in unsigned(SDR_DM_WIDTH-1 downto 0);
-		sdr_data_r		: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-		sdr_data_vld	: out STD_LOGIC;
-		sdr_data_req_w	: out STD_LOGIC;
-		part_clk_p		: out STD_LOGIC;
-		part_clk_n		: out STD_LOGIC;
-		part_dm			: out unsigned(DDR_DM_WIDTH-1 downto 0);
-		part_dqs		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		part_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0);
-		part_ba			: out unsigned(DDR_BANK_WIDTH-1 downto 0);
-		part_addr		: out unsigned(DDR_ADDR_WIDTH-1 downto 0);
-		part_cs_n		: out STD_LOGIC;
-		part_we_n		: out STD_LOGIC;
-		part_cas_n		: out STD_LOGIC;
-		part_ras_n		: out STD_LOGIC;
-		part_cke		: out STD_LOGIC
-	);
-end ddr_phy;
-
-architecture tech of ddr_phy is
-
-	signal dqs_drive		: std_logic;
-	signal drive			: std_logic;
-	signal dqs				: unsigned(DDR_DQS_WIDTH-1 downto 0);  
-	signal dqs_zen			: unsigned(DDR_DQS_WIDTH-1 downto 0);  
-	signal dqs_rst			: std_logic;
-	signal ddr_data_w		: unsigned(DDR_DATA_WIDTH-1 downto 0);
-	signal data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal data_reg_r		: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal drive270			: unsigned(DDR_DATA_WIDTH-1 downto 0);
-	signal part_ctrl_reg	: part_ctrl_t;
-	signal we_reg			: std_logic;
-	signal read_en			: std_logic;
-	
-	type u_tag_array_t is array (natural range 0 to 4) of user_tag_t;
-	signal u_tag_pipe : u_tag_array_t;
-	
-begin
-
-------------------------------------------------------------------------------------------------------------------------------------------------
-utag_pipe:
-	process(sys_rst, sys_clk0)
-	begin
-		if rising_edge(sys_clk0) then
-			for i in u_tag_pipe'length-1 downto 1 loop
-				u_tag_pipe(i) <= u_tag_pipe(i-1);
-			end loop;	
-			if phy_ctrl.utag_we = '1' then
-				u_tag_pipe(0) <= u_tag_in;
-			end if;	
-		end if;
-	end process;
-
-WE_REGISTER:
-	process(sys_rst, sys_clk0)
-	begin
-		if sys_rst = '1' then
-			we_reg <= '0';
-		elsif rising_edge(sys_clk0) then
-			we_reg	<= phy_ctrl.we;
-		end if;
-	end process;
-	
-DATA_DRIVE_GEN:
-	process(sys_clk0)
-	begin
-		if falling_edge(sys_clk0) then
-			dqs_rst		<= not we_reg;
-			drive 		<= we_reg;
-		end if;
-	end process;
-
-DQS_DRIVE_GEN:
-	process(sys_clk0)
-	variable p : unsigned(1 downto 0);
-	begin
-		if rising_edge(sys_clk0) then
-			if phy_ctrl.drive_en = '1' then
-				p := (others => '1');
-			else
-				p := p(p'left-1 downto 0) & '0';
-			end if;
-		end if;
-		dqs_drive <= p(p'left);
-	end process;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- SDRAM Clock
-ODDR_clk_p : ODDR
-	generic map
-	(
-		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-		INIT => '0',						-- Initial value for Q port ('1' or '0')
-		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
-	) 										
-	port map (
-		Q	=> part_clk_p,	-- 1-bit DDR output
-		C	=> sys_clk0,	-- 1-bit clock input
-		CE	=> '1',			-- 1-bit clock enable input
-		D1	=> '1',			-- 1-bit data input (positive edge)
-		D2	=> '0',			-- 1-bit data input (negative edge)
-		R	=> '0',			-- 1-bit reset input
-		S	=> '0' 			-- 1-bit set input
-	);
-
-ODDR_clk_n : ODDR
-	generic map
-	(
-		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-		INIT => '0',						-- Initial value for Q port ('1' or '0')
-		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
-	) 										
-	port map (
-		Q	=> part_clk_n,	-- 1-bit DDR output
-		C	=> sys_clk0,	-- 1-bit clock input
-		CE	=> '1',			-- 1-bit clock enable input
-		D1	=> '0',			-- 1-bit data input (positive edge)
-		D2	=> '1',			-- 1-bit data input (negative edge)
-		R	=> '0',			-- 1-bit reset input
-		S	=> '0' 			-- 1-bit set input
-	);
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data OUT DDR-FFs
-gen_ddr_data_out:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-	begin 
-	ODDR_data : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> ddr_data_w(n),						-- 1-bit DDR output
-			C	=> sys_clk270,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_data_w(n + DDR_DATA_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_data_w(n),						-- 1-bit data input (negative edge)
-			R	=> '0',									-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_ddr_data_out;
-
--- Sample tristate on clock90
-	process (sys_clk270)
-	begin  
-		if rising_edge(sys_clk270) then
-			for n in 0 to DDR_DATA_WIDTH-1 loop
-               drive270(n) <= drive;
-			end loop;
-		end if;
-	end process;
-
--- Output mux
-out_mux_data:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-		part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z';
-	end generate;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- Data-mask OUT DDR-FFs
-gen_ddr_dm_out:
-	for n in 0 to DDR_DM_WIDTH-1 generate
-	begin 
-	ODDR_dm : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "SAME_EDGE",				-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> part_dm(n),							-- 1-bit DDR output
-			C	=> sys_clk270,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D1	=> sdr_dm(n + DDR_DM_WIDTH),		-- 1-bit data input (positive edge)
-			D2	=> sdr_dm(n),						-- 1-bit data input (negative edge)
-			R	=> '0',									-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_ddr_dm_out;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
--- DQS OUT DDR-FFs
-gen_dqs_out:
-	for n in 0 to DDR_DQS_WIDTH-1 generate
-	begin 
-	ODDR_dqs : ODDR
-		generic map
-		(
-			DDR_CLK_EDGE => "OPPOSITE_EDGE",			-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-			INIT => '0',								-- Initial value for Q port ('1' or '0')
-			SRTYPE => "SYNC"							-- Reset Type ("ASYNC" or "SYNC")
-		) 										
-		port map (
-			Q	=> dqs(n),								-- 1-bit DDR output
-			C	=> sys_clk0,							-- 1-bit clock input
-			CE	=> '1',									-- 1-bit clock enable input
-			D2	=> '0',									-- 1-bit data input (positive edge)
-			D1	=> '1',									-- 1-bit data input (negative edge)
-			R	=> dqs_rst,								-- 1-bit reset input
-			S	=> '0' 									-- 1-bit set input
-		);
-	end generate gen_dqs_out;
-
--- Tristate-Control fuer dqs      
-	process (sys_clk0) is
-	variable zctrl : boolean; 
-	begin
-		if rising_edge(sys_clk0) then
-			if dqs_drive = '1' then
-				zctrl := false;
-			else
-				zctrl := true;
-			end if;
-			if zctrl then 
-				dqs_zen <= (others => '1');
-			else
-				dqs_zen <= (others => '0');
-			end if;	
-		end if;
-	end process;
-
--- Tristate-Buffer fuer dqs      
-gen_out_mux_dqs:
-	for n in 0 to DDR_DQS_WIDTH-1 generate
-		part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n);
-	end generate gen_out_mux_dqs;
-
-------------------------------------------------------------------------------------------------------------------------------------------------
-	process (sys_rst, sys_clk0) is
-	begin  
-		if sys_rst = '1' then
-			part_ctrl_reg.cmd		<= COMMAND(SD_DESELECT); 
-			part_ctrl_reg.ba		<= (others=>'0');
-			part_ctrl_reg.addr		<= (others=>'0');
-			part_ctrl_reg.cke		<= '0';
-		elsif rising_edge(sys_clk0) then
-			part_ctrl_reg <= part_ctrl;
-		end if;
-	end process;
-
-	process (sys_clk0) is
-	begin  
-		if falling_edge(sys_clk0) then
-			part_ras_n		<= part_ctrl_reg.cmd.ras_n;
-			part_cas_n		<= part_ctrl_reg.cmd.cas_n; 
-			part_we_n 		<= part_ctrl_reg.cmd.we_n; 
-			part_cs_n 		<= part_ctrl_reg.cmd.cs_n; 
-			part_ba   		<= part_ctrl_reg.ba; 
-			part_addr    	<= part_ctrl_reg.addr;
-			part_cke  		<= part_ctrl_reg.cke;
-		end if;
-	end process;
-
------------------------------------------------------------------
--- READ DATA Processing
------------------------------------------------------------------
-gen_ddr_data_in:
-	for n in 0 to DDR_DATA_WIDTH-1 generate
-	begin 
-	IDDR_data : IDDR 
-		generic map
-		(
-			DDR_CLK_EDGE	=> "SAME_EDGE",					-- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" 
-			INIT_Q1			=> '0', 						-- Initial value of Q1: '0' or '1'
-			INIT_Q2			=> '0',							-- Initial value of Q2: '0' or '1'
-			SRTYPE			=> "SYNC"						-- Set/Reset type: "SYNC" or "ASYNC" 
-		)
-		port map
-		(
-			Q1				=> data_r(n),					-- 1-bit output for positive edge of clock 
-			Q2				=> data_r(n + DDR_DATA_WIDTH),	-- 1-bit output for negative edge of clock
-			C				=> read_clk, 					-- 1-bit clock input
-			CE				=> read_en,						-- 1-bit clock enable input
-			D				=> part_data(n),				-- 1-bit DDR data input
-			R				=> '0',							-- 1-bit reset
-			S				=> '0' 							-- 1-bit set
-		);
-	end generate;
-
-
-data_sample_stage:
-	process (sys_clk0)
-	begin
-		if falling_edge(sys_clk0) then
-			data_reg_r	<= data_r;
-		end if;
-	end process;
-
-misc_flags_and_data_out:
-	process (sys_rst, sys_clk0)
-	variable p : unsigned(3 downto 0);
-	begin
-		if sys_rst = '1' then
-			p				:= (others => '0');
-			read_en			<= '0';
-			sdr_data_vld	<= '0';
-			sdr_data_req_w	<= '0';
-		elsif rising_edge(sys_clk0) then
-			sdr_data_r		<= data_reg_r;
-			if p(3) = '1' then
-				u_tag_rd		<= u_tag_pipe(4);
-			end if;	
-			if phy_ctrl.we = '1' then
-				u_tag_wr		<= u_tag_pipe(0);
-			end if;	
-			sdr_data_req_w	<= phy_ctrl.we;
-			sdr_data_vld	<= p(3);
-			read_en			<= p(1);
-			if phy_ctrl.re = '1' then
-				p := p(p'left-1 downto 0) & '1';
-			else
-				p := p(p'left-1 downto 0) & '0';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end tech;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd
deleted file mode 100644
index 356bb28..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd
+++ /dev/null
@@ -1,1320 +0,0 @@
------------------------------------------------------------------------------------------
---
---     File Name: MT46V16M16.VHD
---       Version: 2.1
---          Date: January 14th, 2002
---         Model: Behavioral
---     Simulator: NCDesktop      - http://www.cadence.com
---                ModelSim PE    - http://www.model.com
---
---  Dependencies: None
---
---        Author: Son P. Huynh
---         Email: sphuynh@micron.com
---         Phone: (208) 368-3825
---       Company: Micron Technology, Inc.
---   Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
---
---   Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
---
---    Limitation: Doesn't model internal refresh counter
---
---          Note: 
---
---    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
---                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
---                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
---                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
---                Copyright (c) 1998 Micron Semiconductor Products, Inc.
---                All rights researved
---
---  Rev  Author                        Date        Changes
---  ---  ----------------------------  ----------  -------------------------------------
---  2.1  Son P. Huynh                  01/14/2002  - Fix Burst_counter
---       Micron Technology, Inc.
---
---  2.0  Son P. Huynh                  11/08/2001  - Second release
---       Micron Technology, Inc.                   - Rewrote and remove SHARED VARIABLE
---
------------------------------------------------------------------------------------------
-
-LIBRARY IEEE;
-    USE IEEE.STD_LOGIC_1164.ALL;
-    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-    USE IEEE.STD_LOGIC_ARITH.ALL;
-
-ENTITY MT46V16M16 IS
-    GENERIC (                                   -- Timing for -75Z CL2
-        tCK       : TIME    :=  7.500 ns;
-        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
-        tDH       : TIME    :=  0.500 ns;
-        tDS       : TIME    :=  0.500 ns;
-        tIH       : TIME    :=  0.900 ns;
-        tIS       : TIME    :=  0.900 ns;
-        tMRD      : TIME    := 15.000 ns;
-        tRAS      : TIME    := 40.000 ns;
-        tRAP      : TIME    := 20.000 ns;
-        tRC       : TIME    := 65.000 ns;
-        tRFC      : TIME    := 75.000 ns;
-        tRCD      : TIME    := 20.000 ns;
-        tRP       : TIME    := 20.000 ns;
-        tRRD      : TIME    := 15.000 ns;
-        tWR       : TIME    := 15.000 ns;
-        addr_bits : INTEGER := 13;
-        data_bits : INTEGER := 16;
-        cols_bits : INTEGER :=  9
-    );
-    PORT (
-        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
-        Clk   : IN    STD_LOGIC;
-        Clk_n : IN    STD_LOGIC;
-        Cke   : IN    STD_LOGIC;
-        Cs_n  : IN    STD_LOGIC;
-        Ras_n : IN    STD_LOGIC;
-        Cas_n : IN    STD_LOGIC;
-        We_n  : IN    STD_LOGIC;
-        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
-    );
-END MT46V16M16;
-
-ARCHITECTURE behave OF MT46V16M16 IS
-    -- Array for Read pipeline
-    TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Write pipeline
-    TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-    -- Array for Auto Precharge
-    TYPE Array_Read_precharge  IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-
-    -- Array for Manual Precharge
-    TYPE Array_A10_precharge  IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
-    TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-    
-    -- Array for Burst Terminate
-    TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-
-    -- Array for Memory Access
-    TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    TYPE Array_ram_pntr IS ACCESS Array_ram_type;
-    TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-
-    -- Data pair
-    SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
-    SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-
-    -- Mode Register
-    SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-    
-    -- Command Decode Variables
-    SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
-    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-    
-    -- Burst Length Decode Variables
-    SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-    
-    -- Cas Latency Decode Variables
-    SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-
-    -- Internal Control Signals
-    SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-
-    -- System Clock
-    SIGNAL Sys_clk : STD_LOGIC := '0';
-
-    -- Dqs buffer
-    SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-
-BEGIN
-    -- Strip the strength
-    Cs_in  <= To_X01 (Cs_n);
-    Ras_in <= To_X01 (Ras_n);
-    Cas_in <= To_X01 (Cas_n);
-    We_in  <= To_X01 (We_n);
-    
-    -- Commands Decode
-    Active_enable   <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND     We_in;
-    Aref_enable     <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND     We_in;
-    Burst_term      <= NOT(Cs_in) AND     Ras_in  AND     Cas_in  AND NOT(We_in);
-    Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND     Ba(0)  AND NOT(Ba(1));
-    Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
-    Prech_enable    <= NOT(Cs_in) AND NOT(Ras_in) AND     Cas_in  AND NOT(We_in);
-    Read_enable     <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND     We_in;
-    Write_enable    <= NOT(Cs_in) AND     Ras_in  AND NOT(Cas_in) AND NOT(We_in);
-
-    -- Burst Length Decode
-    Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);
-    Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));
-    Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-    Burst_length_f  <=    (Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);
-
-    -- CAS Latency Decode
-    Cas_latency_15  <=     Mode_reg(6)  AND NOT(Mode_reg(5)) AND    (Mode_reg(4));
-    Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_25  <=     Mode_reg(6)  AND     Mode_reg(5)  AND NOT(Mode_reg(4));
-    Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);
-    Cas_latency_4   <=    (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-
-    -- Dqs buffer
-    Dqs <= Dqs_out;
-
-    --
-    -- System Clock
-    --
-    int_clk : PROCESS (Clk, Clk_n)
-        VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
-    begin
-        IF Clk = '1' AND Clk_n = '0' THEN
-            ClkZ := '1';
-            CkeZ := Cke;
-        ELSIF Clk = '0' AND Clk_n = '1' THEN
-            ClkZ := '0';
-        END IF;
-        Sys_clk <= CkeZ AND ClkZ;
-    END PROCESS;
-
-    --
-    -- Main Process
-    --
-    state_register : PROCESS
-        -- Precharge Variables
-        VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-
-        -- Activate Variables
-        VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-
-        -- Data IO variables
-        VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-
-        -- Internal address mux variables
-        VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
-        VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-        VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-        VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-
-        -- DLL Reset variables
-        VARIABLE DLL_enable : STD_LOGIC := '0';
-        VARIABLE DLL_reset : STD_LOGIC := '0';
-        VARIABLE DLL_done : STD_LOGIC := '0';
-        VARIABLE DLL_count : INTEGER := 0;
-        
-        -- Timing Check
-        VARIABLE MRD_chk : TIME := 0 ns;
-        VARIABLE RFC_chk : TIME := 0 ns;
-        VARIABLE RRD_chk : TIME := 0 ns;
-        VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
-        VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
-        VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
-        VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
-        VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-        VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-
-        -- Read pipeline variables
-        VARIABLE Read_cmnd : Array_Read_cmnd;
-        VARIABLE Read_bank : Array_Read_bank;
-        VARIABLE Read_cols : Array_Read_cols;
-
-        -- Write pipeline variables
-        VARIABLE Write_cmnd : Array_Write_cmnd;
-        VARIABLE Write_bank : Array_Write_bank;
-        VARIABLE Write_cols : Array_Write_cols;
-
-        -- Auto Precharge variables
-        VARIABLE Read_precharge  : Array_Read_precharge  := ('0' & '0' & '0' & '0');
-        VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
-        VARIABLE Count_precharge : Array_Count_precharge := ( 0  &  0  &  0  &  0 );
-
-        -- Manual Precharge variables
-        VARIABLE A10_precharge  : Array_A10_precharge;
-        VARIABLE Bank_precharge : Array_Bank_precharge;
-        VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-
-        -- Burst Terminate variable
-        VARIABLE Cmnd_bst : Array_Cmnd_bst;
-
-        -- Memory Banks
-        VARIABLE Bank0 : Array_ram_stor;
-        VARIABLE Bank1 : Array_ram_stor;
-        VARIABLE Bank2 : Array_ram_stor;
-        VARIABLE Bank3 : Array_ram_stor;
-
-        -- Burst Counter
-        VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-
-        -- Internal Dqs initialize
-        VARIABLE Dqs_int : STD_LOGIC := '0';
-
-        -- Data buffer for DM Mask
-        VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
-
-        --
-        -- Initialize empty rows
-        --
-        PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
-            VARIABLE i, j : INTEGER := 0;
-        BEGIN
-            IF Bank = "00" THEN
-                IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty
-                    Bank0 (Row_index) := NEW Array_ram_type;            -- Open new row for access
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP           -- Filled row with zeros
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank0 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "01" THEN
-                IF Bank1 (Row_index) = NULL THEN
-                    Bank1 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank1 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "10" THEN
-                IF Bank2 (Row_index) = NULL THEN
-                    Bank2 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank2 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            ELSIF Bank = "11" THEN
-                IF Bank3 (Row_index) = NULL THEN
-                    Bank3 (Row_index) := NEW Array_ram_type;
-                    FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
-                        FOR j IN (data_bits - 1) DOWNTO 0 LOOP
-                            Bank3 (Row_index) (i) (j) := '0';
-                        END LOOP;
-                    END LOOP;
-                END IF;
-            END IF;
-        END;
-
-        --
-        -- Burst Counter
-        --
-        PROCEDURE Burst_decode IS
-            VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
-        BEGIN
-            -- Advance burst counter
-            Burst_counter := Burst_counter + 1;
-
-            -- Burst Type
-            IF Mode_reg (3) = '0' THEN
-                Cols_temp := Cols_addr + 1;
-            ELSIF Mode_reg (3) = '1' THEN
-                Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
-                Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
-                Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
-            END IF;
-
-            -- Burst Length
-            IF Burst_length_2 = '1' THEN
-                Cols_addr (0) := Cols_temp (0);
-            ELSIF Burst_length_4 = '1' THEN
-                Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
-            ELSIF Burst_length_8 = '1' THEN
-                Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
-            ELSE
-                Cols_addr := Cols_temp;
-            END IF;
-
-            -- Data counter
-            IF Burst_length_2 = '1' THEN
-                IF Burst_counter >= 2 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_4 = '1' THEN
-                IF Burst_counter >= 4 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            ELSIF Burst_length_8 = '1' THEN
-                IF Burst_counter >= 8 THEN
-                    IF Data_in_enable = '1' THEN
-                        Data_in_enable := '0';
-                    ELSIF Data_out_enable = '1' THEN
-                        Data_out_enable := '0';
-                    END IF;
-                END IF;
-            END IF;
-        END;
-
-    BEGIN
-        WAIT ON Sys_clk;
-
-        --
-        -- Manual Precharge Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- A10 Precharge Pipeline
-            A10_precharge(0) := A10_precharge(1);
-            A10_precharge(1) := A10_precharge(2);
-            A10_precharge(2) := A10_precharge(3);
-            A10_precharge(3) := A10_precharge(4);
-            A10_precharge(4) := A10_precharge(5);
-            A10_precharge(5) := A10_precharge(6);
-            A10_precharge(6) := A10_precharge(7);
-            A10_precharge(7) := A10_precharge(8);
-            A10_precharge(8) := '0';
-
-            -- Bank Precharge Pipeline
-            Bank_precharge(0) := Bank_precharge(1);
-            Bank_precharge(1) := Bank_precharge(2);
-            Bank_precharge(2) := Bank_precharge(3);
-            Bank_precharge(3) := Bank_precharge(4);
-            Bank_precharge(4) := Bank_precharge(5);
-            Bank_precharge(5) := Bank_precharge(6);
-            Bank_precharge(6) := Bank_precharge(7);
-            Bank_precharge(7) := Bank_precharge(8);
-            Bank_precharge(8) := "00";
-
-            -- Command Precharge Pipeline
-            Cmnd_precharge(0) := Cmnd_precharge(1);
-            Cmnd_precharge(1) := Cmnd_precharge(2);
-            Cmnd_precharge(2) := Cmnd_precharge(3);
-            Cmnd_precharge(3) := Cmnd_precharge(4);
-            Cmnd_precharge(4) := Cmnd_precharge(5);
-            Cmnd_precharge(5) := Cmnd_precharge(6);
-            Cmnd_precharge(6) := Cmnd_precharge(7);
-            Cmnd_precharge(7) := Cmnd_precharge(8);
-            Cmnd_precharge(8) := '0';
-
-            -- Terminate Read if same bank or all banks
-            IF ((Cmnd_precharge (0) = '1') AND
-                (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
-                (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Burst Terminate Pipeline
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Burst Terminate pipeline
-            Cmnd_bst (0) := Cmnd_bst (1);
-            Cmnd_bst (1) := Cmnd_bst (2);
-            Cmnd_bst (2) := Cmnd_bst (3);
-            Cmnd_bst (3) := Cmnd_bst (4);
-            Cmnd_bst (4) := Cmnd_bst (5);
-            Cmnd_bst (5) := Cmnd_bst (6);
-            Cmnd_bst (6) := Cmnd_bst (7);
-            Cmnd_bst (7) := Cmnd_bst (8);
-            Cmnd_bst (8) := '0';
-
-            -- Terminate current Read
-            IF ((Cmnd_bst  (0) = '1') AND (Data_out_enable = '1')) THEN
-                Data_out_enable := '0';
-            END IF;
-        END IF;
-
-        --
-        -- Dq and Dqs Drivers
-        --
-        IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
-            -- Read Command Pipeline
-            Read_cmnd (0) := Read_cmnd (1);
-            Read_cmnd (1) := Read_cmnd (2);
-            Read_cmnd (2) := Read_cmnd (3);
-            Read_cmnd (3) := Read_cmnd (4);
-            Read_cmnd (4) := Read_cmnd (5);
-            Read_cmnd (5) := Read_cmnd (6);
-            Read_cmnd (6) := Read_cmnd (7);
-            Read_cmnd (7) := Read_cmnd (8);
-            Read_cmnd (8) := '0';
-
-            -- Read Bank Pipeline
-            Read_bank (0) := Read_bank (1);
-            Read_bank (1) := Read_bank (2);
-            Read_bank (2) := Read_bank (3);
-            Read_bank (3) := Read_bank (4);
-            Read_bank (4) := Read_bank (5);
-            Read_bank (5) := Read_bank (6);
-            Read_bank (6) := Read_bank (7);
-            Read_bank (7) := Read_bank (8);
-            Read_bank (8) := "00";
-
-            -- Read Column Pipeline
-            Read_cols (0) := Read_cols (1);
-            Read_cols (1) := Read_cols (2);
-            Read_cols (2) := Read_cols (3);
-            Read_cols (3) := Read_cols (4);
-            Read_cols (4) := Read_cols (5);
-            Read_cols (5) := Read_cols (6);
-            Read_cols (6) := Read_cols (7);
-            Read_cols (7) := Read_cols (8);
-            Read_cols (8) := (OTHERS => '0');
-
-            -- Initialize Read command
-            IF Read_cmnd (0) = '1' THEN
-                Data_out_enable := '1';
-                Bank_addr := Read_bank (0);
-                Cols_addr := Read_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Toggle Dqs during Read command
-            IF Data_out_enable = '1' THEN
-                Dqs_int := '0';
-                IF Dqs_out = "00" THEN
-                    Dqs_out <= "11";
-                ELSIF Dqs_out = "11" THEN
-                    Dqs_out <= "00";
-                ELSE
-                    Dqs_out <= "00";
-                END IF;
-            ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
-                Dqs_out <= "ZZ";
-            END IF;
-
-            -- Initialize Dqs for Read command
-            IF Read_cmnd (2) = '1' THEN
-                IF Data_out_enable = '0' THEN
-                    Dqs_int := '1';
-                    Dqs_out <= "00";
-                END IF;
-            END IF;
-
-            -- Read Latch
-            IF Data_out_enable = '1' THEN
-                -- Initialize Memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Output Data
-                CASE Bank_addr IS
-                    WHEN "00"   => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "01"   => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN "10"   => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                END CASE;
-
-                --  Increase Burst Counter
-                Burst_decode;
-            ELSE
-                Dq <= (OTHERS => 'Z');
-            END IF;
-        END IF;
-
-        --
-        -- Write FIFO and DM Mask Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Write command pipeline
-            Write_cmnd (0) := Write_cmnd (1);
-            Write_cmnd (1) := Write_cmnd (2);
-            Write_cmnd (2) := '0';
-
-            -- Write command pipeline
-            Write_bank (0) := Write_bank (1);
-            Write_bank (1) := Write_bank (2);
-            Write_bank (2) := "00";
-
-            -- Write column pipeline
-            Write_cols (0) := Write_cols (1);
-            Write_cols (1) := Write_cols (2);
-            Write_cols (2) := (OTHERS => '0');
-
-            -- Initialize Write command
-            IF Write_cmnd (0) = '1' THEN
-                Data_in_enable := '1';
-                Bank_addr := Write_bank (0);
-                Cols_addr := Write_cols (0);
-                Cols_brst := Cols_addr (2 DOWNTO 0);
-                Burst_counter := (OTHERS => '0');
-
-                -- Row address mux
-                CASE Bank_addr IS
-                    WHEN "00"   => Rows_addr := B0_row_addr;
-                    WHEN "01"   => Rows_addr := B1_row_addr;
-                    WHEN "10"   => Rows_addr := B2_row_addr;
-                    WHEN OTHERS => Rows_addr := B3_row_addr;
-                END CASE;
-            END IF;
-
-            -- Write data
-            IF Data_in_enable = '1' THEN
-                -- Initialize memory
-                Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
-                
-                -- Write first data
-                IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (0) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
-                    END IF;
-                    IF Dm_pair (1) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-
-                --  Increase Burst Counter
-                Burst_decode;
-
-                -- Write second data
-                IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
-                    -- Data Buffer
-                    CASE Bank_addr IS
-                        WHEN "00"   => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "01"   => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN "10"   => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                        WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
-                    END CASE;
-
-                    -- Perform DM Mask
-                    IF Dm_pair (2) = '0' THEN
-                        Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
-                    END IF;
-                    IF Dm_pair (3) = '0' THEN
-                        Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
-                    END IF;
-
-                    -- Write Data
-                    CASE Bank_addr IS
-                        WHEN "00"   => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "01"   => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN "10"   => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                        WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
-                    END CASE;
-                END IF;
-                
-                -- Increase Burst Counter
-                Burst_decode;
-
-                -- tWR start and tWTR check
-                IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
-                    CASE Bank_addr IS
-                        WHEN "00"   => WR_chk0 := NOW;
-                        WHEN "01"   => WR_chk1 := NOW;
-                        WHEN "10"   => WR_chk2 := NOW;
-                        WHEN OTHERS => WR_chk3 := NOW;
-                    END CASE;
-
-                    -- tWTR check
-                    ASSERT (Read_enable = '0')
-                        REPORT "tWTR violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Auto Precharge Calculation
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Precharge counter
-            IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
-                Count_precharge (0) := Count_precharge (0) + 1;
-            END IF;
-            IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
-                Count_precharge (1) := Count_precharge (1) + 1;
-            END IF;
-            IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
-                Count_precharge (2) := Count_precharge (2) + 1;
-            END IF;
-            IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
-                Count_precharge (3) := Count_precharge (3) + 1;
-            END IF;
-
-            -- Read with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  BL/2 cycles after command
-            IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(0) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW;
-                    Read_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(1) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW;
-                    Read_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(2) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW;
-                    Read_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1)  OR
-                    (Burst_length_4 = '1' AND Count_precharge(3) >= 2)  OR
-                    (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW;
-                    Read_precharge(3) := '0';
-                END IF;
-            END IF;
-
-            -- Write with AutoPrecharge Calculation
-            --      The device start internal precharge when:
-            --          1.  Meet tRAS requirement
-            --          2.  Two clock after last burst
-            -- Since tWR is time base, the model will compensate tRP
-            IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
-                    Pc_b0 := '1';
-                    Act_b0 := '0';
-                    RP_chk0 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(0) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
-                    Pc_b1 := '1';
-                    Act_b1 := '0';
-                    RP_chk1 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(1) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
-                    Pc_b2 := '1';
-                    Act_b2 := '0';
-                    RP_chk2 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(2) := '0';
-                END IF;
-            END IF;
-            IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
-                IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
-                    (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
-                    (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
-                    Pc_b3 := '1';
-                    Act_b3 := '0';
-                    RP_chk3 := NOW - ((2 * tCK) - tWR);
-                    Write_precharge(3) := '0';
-                END IF;
-            END IF;
-        END IF;
-        
-        --
-        -- DLL Counter
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            IF (DLL_Reset = '1' AND DLL_done = '0') THEN
-                DLL_count := DLL_count + 1;
-                IF (DLL_count >= 200) THEN
-                    DLL_done := '1';
-                END IF;
-            END IF;
-        END IF;
-
-        --
-        -- Control Logic
-        --
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            -- Auto Refresh
-            IF Aref_enable = '1' THEN
-                -- Auto Refresh to Auto Refresh
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Precharge to Auto Refresh
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All banks must be Precharge before Auto Refresh"
-                    SEVERITY WARNING;
-
-                -- Record current tRFC time
-                RFC_chk := NOW;
-            END IF;
-
-            -- Extended Load Mode Register
-            IF Ext_mode_enable = '1' THEN
-                IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
-                    IF (Addr (0) = '0') THEN
-                        DLL_enable := '1';
-                    ELSE
-                        DLL_enable := '0';
-                    END IF;
-                END IF;
-                
-                -- Precharge to EMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Extended Mode Register"
-                    SEVERITY WARNING;
-                
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Extended Load Register"
-                    SEVERITY WARNING;
-
-                -- LMR/EMR to EMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Extended Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Load Mode Register
-            IF Mode_reg_enable = '1' THEN
-                -- Register mode
-                Mode_reg <= Addr;
-                
-                -- DLL Reset
-                IF (DLL_enable = '1' AND Addr (8) = '1') THEN
-                    DLL_reset := '1';
-                    DLL_done  := '0';
-                    DLL_count := 0;
-                ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is ENABLE: DLL RESET is require"
-                        SEVERITY WARNING;
-                ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
-                    ASSERT (FALSE)
-                        REPORT "DLL is DISABLE: DLL RESET will be ignored"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge to LMR
-                ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
-                    REPORT "All bank must be Precharged before Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Precharge to EMR
-                ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
-                        (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
-                    REPORT "tRP violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- LMR/ELMR to LMR
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid Burst Length
-                ASSERT ((Addr (2 DOWNTO 0) = "001") OR      -- BL = 2
-                        (Addr (2 DOWNTO 0) = "010") OR      -- BL = 4
-                        (Addr (2 DOWNTO 0) = "011"))        -- BL = 8
-                    REPORT "Invalid Burst Length during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Check for invalid CAS Latency
-                ASSERT ((Addr (6 DOWNTO 4) = "010") OR      -- CL = 2.0
-                        (Addr (6 DOWNTO 4) = "110"))        -- CL = 2.5
-                    REPORT "Invalid CAS Latency during Load Mode Register"
-                    SEVERITY WARNING;
-
-                -- Record current tMRD time
-                MRD_chk := NOW;
-            END IF;
-
-            -- Active Block (latch Bank and Row Address)
-            IF Active_enable = '1' THEN
-                -- Activate an OPEN bank can corrupt data
-                ASSERT ((Ba = "00" AND Act_b0 = '0') OR
-                        (Ba = "01" AND Act_b1 = '0') OR
-                        (Ba = "10" AND Act_b2 = '0') OR
-                        (Ba = "11" AND Act_b3 = '0'))
-                    REPORT "Bank is already activated - data can be corrupted"
-                    SEVERITY WARNING;
-
-                -- Activate Bank 0
-                IF Ba = "00" AND Pc_b0 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk0 >= tRC)
-                        REPORT "tRC violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk0 >= tRP)
-                        REPORT "tRP violation during Activate Bank 0"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b0 := '1';
-                    Pc_b0 := '0';
-                    B0_row_addr := Addr;
-                    RC_chk0 := NOW;
-                    RCD_chk0 := NOW;
-                    RAS_chk0 := NOW;
-                    RAP_chk0 := NOW;
-                END IF;
-
-                -- Activate Bank 1
-                IF Ba = "01" AND Pc_b1 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk1 >= tRC)
-                        REPORT "tRC violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk1 >= tRP)
-                        REPORT "tRP violation during Activate Bank 1"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b1 := '1';
-                    Pc_b1 := '0';
-                    B1_row_addr := Addr;
-                    RC_chk1 := NOW;
-                    RCD_chk1 := NOW;
-                    RAS_chk1 := NOW;
-                    RAP_chk1 := NOW;
-                END IF;
-
-                -- Activate Bank 2
-                IF Ba = "10" AND Pc_b2 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk2 >= tRC)
-                        REPORT "tRC violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk2 >= tRP)
-                        REPORT "tRP violation during Activate Bank 2"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b2 := '1';
-                    Pc_b2 := '0';
-                    B2_row_addr := Addr;
-                    RC_chk2 := NOW;
-                    RCD_chk2 := NOW;
-                    RAS_chk2 := NOW;
-                    RAP_chk2 := NOW;
-                END IF;
-
-                -- Activate Bank 3
-                IF Ba = "11" AND Pc_b3 = '1' THEN
-                    -- Activate to Activate (same bank)
-                    ASSERT (NOW - RC_chk3 >= tRC)
-                        REPORT "tRC violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Precharge to Active
-                    ASSERT (NOW - RP_chk3 >= tRP)
-                        REPORT "tRP violation during Activate Bank 3"
-                        SEVERITY WARNING;
-
-                    -- Record Variables for checking violation
-                    Act_b3 := '1';
-                    Pc_b3 := '0';
-                    B3_row_addr := Addr;
-                    RC_chk3 := NOW;
-                    RCD_chk3 := NOW;
-                    RAS_chk3 := NOW;
-                    RAP_chk3 := NOW;
-                END IF;
-
-                -- Activate Bank A to Activate Bank B
-                IF (Prev_bank /= Ba) THEN
-                    ASSERT (NOW - RRD_chk >= tRRD)
-                        REPORT "tRRD violation during Activate"
-                        SEVERITY WARNING;
-                END IF;
-                
-                -- AutoRefresh to Activate
-                ASSERT (NOW - RFC_chk >= tRFC)
-                    REPORT "tRFC violation during Activate"
-                    SEVERITY WARNING;
-                
-                -- Record Variables for Checking Violation
-                RRD_chk := NOW;
-                Prev_bank := Ba;
-            END IF;
-
-            -- Precharge Block - Consider NOP if bank already precharged or in process of precharging
-            IF Prech_enable = '1' THEN
-                -- EMR or LMR to Precharge
-                ASSERT (NOW - MRD_chk >= tMRD)
-                    REPORT "tMRD violation during Precharge"
-                    SEVERITY WARNING;
-
-                -- Precharge Bank 0
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
-                    Act_b0 := '0';
-                    Pc_b0 := '1';
-                    RP_chk0 := NOW;
-
-                    -- Activate to Precharge bank 0
-                    ASSERT (NOW - RAS_chk0 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk0 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 1
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
-                    Act_b1 := '0';
-                    Pc_b1 := '1';
-                    RP_chk1 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk1 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk1 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 2
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
-                    Act_b2 := '0';
-                    Pc_b2 := '1';
-                    RP_chk2 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk2 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk2 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Precharge Bank 3
-                IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
-                    Act_b3 := '0';
-                    Pc_b3 := '1';
-                    RP_chk3 := NOW;
-
-                    -- Activate to Precharge
-                    ASSERT (NOW - RAS_chk3 >= tRAS)
-                        REPORT "tRAS violation during Precharge"
-                        SEVERITY WARNING;
-
-                    -- tWR violation check for Write
-                    ASSERT (NOW - WR_chk3 >= tWR)
-                        REPORT "tWR violation during Precharge"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Pipeline for READ
-                IF CAS_latency_15 = '1' THEN
-                    A10_precharge  (3) := Addr(10);
-                    Bank_precharge (3) := Ba;
-                    Cmnd_precharge (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    A10_precharge  (4) := Addr(10);
-                    Bank_precharge (4) := Ba;
-                    Cmnd_precharge (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    A10_precharge  (5) := Addr(10);
-                    Bank_precharge (5) := Ba;
-                    Cmnd_precharge (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    A10_precharge  (6) := Addr(10);
-                    Bank_precharge (6) := Ba;
-                    Cmnd_precharge (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    A10_precharge  (8) := Addr(10);
-                    Bank_precharge (8) := Ba;
-                    Cmnd_precharge (8) := '1';
-                END IF;
-            END IF;
-
-            -- Burst Terminate
-            IF Burst_term = '1' THEN
-                -- Pipeline for Read
-                IF CAS_latency_15 = '1' THEN
-                    Cmnd_bst (3) := '1';
-                ELSIF CAS_latency_2 = '1' THEN
-                    Cmnd_bst (4) := '1';
-                ELSIF CAS_latency_25 = '1' THEN
-                    Cmnd_bst (5) := '1';
-                ELSIF CAS_latency_3 = '1' THEN
-                    Cmnd_bst (6) := '1';
-                ELSIF CAS_latency_4 = '1' THEN
-                    Cmnd_bst (8) := '1';
-                END IF;
-
-                -- Terminate Write
-                ASSERT (Data_in_enable = '0')
-                    REPORT "It's illegal to Burst Terminate a Write"
-                    SEVERITY WARNING;
-
-                -- Terminate Read with Auto Precharge
-                ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
-                        Read_precharge (2) = '0' AND Read_precharge (3) = '0')
-                    REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
-                    SEVERITY WARNING;
-            END IF;
-
-            -- Read Command
-            IF Read_enable = '1' THEN
-                -- CAS Latency Pipeline
-                IF Cas_latency_15 = '1' THEN
-                    Read_cmnd (3) := '1';
-                    Read_bank (3) := Ba;
-                    Read_cols (3) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_2 = '1' THEN
-                    Read_cmnd (4) := '1';
-                    Read_bank (4) := Ba;
-                    Read_cols (4) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_25 = '1' THEN
-                    Read_cmnd (5) := '1';
-                    Read_bank (5) := Ba;
-                    Read_cols (5) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_3 = '1' THEN
-                    Read_cmnd (6) := '1';
-                    Read_bank (6) := Ba;
-                    Read_cols (6) := Addr (8 DOWNTO 0);
-                ELSIF Cas_latency_4 = '1' THEN
-                    Read_cmnd (8) := '1';
-                    Read_bank (8) := Ba;
-                    Read_cols (8) := Addr (8 DOWNTO 0);
-                END IF;
-
-                -- Write to Read: Terminate Write Immediately
-                IF Data_in_enable = '1' THEN
-                    Data_in_enable := '0';
-                END IF;
-
-                -- Interrupting a Read with Auto Precharge (same bank only)
-                ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Read with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Read
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Read"
-                    SEVERITY WARNING;
-
-                -- Activate to Read without Auto Precharge
-                IF Addr (10) = '0' THEN
-                    ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                            (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                            (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                            (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                        REPORT "tRCD violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Activate to Read with Auto Precharge
-                IF Addr (10) = '1' THEN
-                    ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
-                            (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
-                            (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
-                            (Ba = "11" AND NOW - RAP_chk3 >= tRAP))
-                        REPORT "tRAP violation during Read"
-                        SEVERITY WARNING;
-                END IF;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Read_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-
-                -- DLL Check
-                IF (DLL_reset = '1') THEN
-                    ASSERT (DLL_done = '1')
-                        REPORT "DLL RESET not complete"
-                        SEVERITY WARNING;
-                END IF;
-            END IF;
-
-            -- Write Command
-            IF Write_enable = '1' THEN
-                -- Pipeline for Write
-                Write_cmnd (2) := '1';
-                Write_bank (2) := Ba;
-                Write_cols (2) := Addr (8 DOWNTO 0);
-
-                -- Interrupting a Write with Auto Precharge (same bank only)
-                ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
-                    REPORT "It's illegal to interrupt a Write with Auto Precharge"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND Act_b0 = '1') OR
-                        (Ba = "01" AND Act_b1 = '1') OR
-                        (Ba = "10" AND Act_b2 = '1') OR
-                        (Ba = "11" AND Act_b3 = '1'))
-                    REPORT "Bank is not Activated for Write"
-                    SEVERITY WARNING;
-
-                -- Activate to Write
-                ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
-                        (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
-                        (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
-                        (Ba = "11" AND NOW - RCD_chk3 >= tRCD))
-                    REPORT "tRCD violation during Write"
-                    SEVERITY WARNING;
-
-                -- Auto precharge
-                IF Addr (10) = '1' THEN
-                    Write_precharge (Conv_INTEGER(Ba)) := '1';
-                    Count_precharge (Conv_INTEGER(Ba)) := 0;
-                END IF;
-            END IF;
-        END IF;
-    END PROCESS;
-
-    --
-    -- Dqs Receiver
-    --
-    dqs_rcvrs : PROCESS
-        VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
-        VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
-    BEGIN
-        WAIT ON Dqs;
-        -- Latch data at posedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
-            Dq_temp := Dq;
-            Dm_temp := Dm;
-        END IF;
-        -- Latch data at negedge Dqs
-        IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
-            Dq_pair <= (Dq & Dq_temp);
-            Dm_pair <= (Dm & Dm_temp);
-        END IF;
-    END PROCESS;
-
-    --
-    -- Setup timing checks
-    --
-    Setup_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk;
-        IF Sys_clk'EVENT AND Sys_clk = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIS)
-                REPORT "CKE Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIS)
-                REPORT "CS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIS)
-                REPORT "CAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIS)
-                REPORT "RAS# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIS)
-                REPORT "WE# Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIS)
-                REPORT "ADDR Setup time violation -- tIS"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIS)
-                REPORT "BA Setup time violation -- tIS"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-    --
-    -- Hold timing checks
-    --
-    Hold_check : PROCESS
-    BEGIN
-        WAIT ON Sys_clk'DELAYED (tIH);
-        IF Sys_clk'DELAYED (tIH) = '1' THEN
-            ASSERT(Cke'LAST_EVENT >= tIH)
-                REPORT "CKE Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cs_n'LAST_EVENT >= tIH)
-                REPORT "CS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Cas_n'LAST_EVENT >= tIH)
-                REPORT "CAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ras_n'LAST_EVENT >= tIH)
-                REPORT "RAS# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(We_n'LAST_EVENT >= tIH)
-                REPORT "WE# Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Addr'LAST_EVENT >= tIH)
-                REPORT "ADDR Hold time violation -- tIH"
-                SEVERITY WARNING;
-            ASSERT(Ba'LAST_EVENT >= tIH)
-                REPORT "BA Hold time violation -- tIH"
-                SEVERITY WARNING;
-        END IF;   
-    END PROCESS;
-
-END behave;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
deleted file mode 100644
index ae38d48..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+++ /dev/null
@@ -1,290 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM command controller
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_cmd is
-	Generic 
-	(
-		f_sdrclk		: real		:= 100.0;
-		BL 				: natural	:= 2
-	);
-	Port
-	(
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		enable			: in  STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_out		: out user_tag_t;
-		phy_ctrl		: out phy_ctrl_t;
-		cmd				: in  sdr_cmd_t;
-		cmd_we			: in  STD_LOGIC;
-		cmd_ack			: out STD_LOGIC;
-		col_addr		: in col_addr_t;
-		mode_word		: in  mode_word_t;
-		sdr_cmd_ctrl	: out sdr_cmd_lines_t;
-		sdr_addr		: out  sdr_addr_t;
-		sdr_ba			: out  sdr_ba_t
-	);
-end sdram_cmd;
-
-architecture behaviour of sdram_cmd is
-
-	signal st_sdr, st_sdr_next : sdr_state_t;
-	
-	signal cc_preset : natural range 0 to 15;
-	signal cc_load_en : std_logic;
-	signal cycle_finished : std_logic;
-
-	signal burst_preset : natural range 0 to 3;
-	signal burst_load_en : std_logic;
-	signal burst_finished : std_logic;
-
-	subtype cycle_cnt_t is natural range 0 to 15;
-
-	type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
-	constant TIMING : part_timing_array_t :=
-	--	 command                 cycle_cnt
-	(	SD_DESELECT         =>   (0        ),
-		SD_NOP              =>   (0        ),
-		SD_LMR              =>   (TMRD-1   ),
-		SD_ACT              =>   (to_cycles(TRCD, f_sdrclk)-1),
-		SD_READ             =>   (TCAS-1   ),
-		SD_WRITE            =>   (to_cycles(TWR, f_sdrclk)-1),
-		SD_PRE              =>   (to_cycles(TRP, f_sdrclk)-1),
-		SD_BST              =>   (0        ),
-		SD_AR               =>   (to_cycles(TRFC, f_sdrclk)-1),
-		SD_SR               =>   (to_cycles(TRFC, f_sdrclk)-1)
-	);
-
-begin
-
-	u_tag_out <= u_tag_in;
-	
-------------------------------------------------------------------------------------------
-
-fsm_sdr_state:
-	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
-	begin
-		st_sdr_next		<= st_sdr;
-		sdr_cmd_ctrl <= COMMAND(SD_NOP);
-		
-		cc_load_en <= '0';
-		cc_preset <= TIMING(cmd);
-		burst_load_en <= '0';
-		cmd_ack	<= '0';
-		burst_preset <= BL/2-1;
-		phy_ctrl.re <= '0';
-		phy_ctrl.drive_en <= '0';
-		phy_ctrl.we <= '0';
-		phy_ctrl.utag_we <= '0';
-		sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
-		sdr_ba	 <= mode_word(mode_word_t'left downto mode_word_t'left-1);
-		
-		case st_sdr is 
-		when PWR_DOWN =>
-			sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
-			if enable = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-			
-		when PRECHARGE =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-
-		when MODE =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-
-		when IDLE =>
-			if cmd_we = '1' then
-				cmd_ack <= '1';
-				cc_load_en <= '1';
-				cc_preset <= TIMING(cmd);
-				sdr_cmd_ctrl <= COMMAND(cmd);
-				case cmd is
-					when SD_PRE =>
-						st_sdr_next <= PRECHARGE;
-					when SD_LMR =>
-						st_sdr_next <= MODE;
-					when SD_ACT =>
-						st_sdr_next <= ROW_ACT;
-					when SD_AR =>
-						st_sdr_next <= AUTO_REF;
-					when others	=> null;
-					end case;	
-			end if;	
-				
-		when ROW_ACT =>
-			if cycle_finished = '1' then
-				if cmd_we = '1' then
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					cc_load_en <= '1';
-					cc_preset <= TIMING(cmd);
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					case cmd is
-					when SD_PRE =>
-						st_sdr_next <= PRECHARGE;
-					when SD_READ =>
-						phy_ctrl.utag_we <= '1';
-						st_sdr_next <= READ;
-						sdr_addr(col_addr_t'range) <= col_addr;
-					when SD_WRITE =>
-						phy_ctrl.utag_we <= '1';
-						phy_ctrl.drive_en <= '1';
-						st_sdr_next <= WRITE;
-						sdr_addr(col_addr_t'range) <= col_addr;
-					when others	=> null;
-					end case;	
-				end if;	
-			end if;	
-
-		when WRITE =>
-			phy_ctrl.drive_en <= '1';
-			phy_ctrl.we <= '1';
-			if burst_finished = '1' then
-				if cmd_we = '1' and cmd = SD_WRITE then
-					sdr_addr(col_addr_t'range) <= col_addr;
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					phy_ctrl.utag_we <= '1';
-				else	
-					phy_ctrl.drive_en <= '0';
-					cc_load_en <= '1';
-					cc_preset <= TIMING(SD_WRITE)+1;
-					st_sdr_next <= ROW_ACT;
-				end if;
-			end if;	
-
-		when READ =>
-			phy_ctrl.re <= '1';
-			if burst_finished = '1' then
-				if cmd_we = '1' and cmd = SD_READ then
-					sdr_addr(col_addr_t'range) <= col_addr;
-					cmd_ack <= '1';
-					burst_load_en <= '1';
-					sdr_cmd_ctrl <= COMMAND(cmd);
-					phy_ctrl.utag_we <= '1';
-				else
-					cc_load_en <= '1';
-					cc_preset <= TIMING(SD_READ);
-					st_sdr_next <= ROW_ACT;
-				end if;
-			end if;	
-
-		when WRITE_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when READ_A =>			-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when BURST_STOP =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-			
-		when SELF_REF =>		-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-			
-		when PRE_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-
-		when ACT_PWR_DOWN =>	-- not implemented yet
-			cmd_ack <= '1';
-			st_sdr_next <= IDLE;
-		
-		when AUTO_REF =>
-			if cycle_finished = '1' then
-				st_sdr_next <= IDLE;
-			end if;	
-			
-		when others =>
-			st_sdr_next <= IDLE;
-		end case;
-		
-	end process;
-	
-fsm_sdr_state_next:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			st_sdr		<= PWR_DOWN;
-		elsif rising_edge(clk) then
-			st_sdr		<= st_sdr_next;
-		end if;
-	end process;
-	
-------------------------------------------------------------------------------------------
-cycle_counter:
-	process (rst, clk)
-	variable cycle_cnt : natural range 0 to 15;
-	begin
-		if rst = '1' then
-			cycle_cnt	:= 0;
-			cycle_finished	<= '0';
-		elsif rising_edge(clk) then
-			cycle_finished	<= '0';
-			if cc_load_en = '1' then
-				cycle_cnt := cc_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt := cycle_cnt - 1;
-			else
-				cycle_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-burst_counter:
-	process (rst, clk)
-	variable burst_cnt : natural range 0 to 3;
-	begin
-		if rst = '1' then
-			burst_cnt	:= 0;
-		elsif rising_edge(clk) then
-			burst_finished	<= '0';
-			if burst_load_en = '1' then
-				burst_cnt := burst_preset;
-			elsif burst_cnt /= 0 then
-				burst_cnt := burst_cnt - 1;
-			end if;	
-			if burst_cnt = 0 then
-				burst_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
deleted file mode 100644
index 534232b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive	:= 2;			-- CAS latency [clocks]
-	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
-	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
-	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
-	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
-	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
-
-	constant PWR_UP_WAIT		: real := 1.0E3; -- [ns]
-	
-	subtype user_tag_t is unsigned(3 downto 0);
-	
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
deleted file mode 100644
index d812b1c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+++ /dev/null
@@ -1,491 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: SDRAM main controller and user I/F
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.utils_pkg.all;
-
-entity sdram_ctrl is
-	Generic
-	(
-		f_sysclk		: real		:= 100.0;
-		BL 				: natural	:= 2
-	);
-	Port (
-		rst				: in  STD_LOGIC;
-		clk				: in  STD_LOGIC;
-		u_busy			: out STD_LOGIC;
-		u_tag_in		: in  user_tag_t;
-		u_tag_out		: out user_tag_t;
-		u_addr			: in  user_addr_t;
-		u_cmd			: in  user_cmd_t;
-		u_cmd_we		: in  STD_LOGIC;
-		col_addr		: out col_addr_t;
-		sdr_cmd_busy	: in  STD_LOGIC;
-		sdr_cmd			: out  sdr_cmd_t;
-		sdr_cmd_we		: out  STD_LOGIC;
-		sdr_mode		: out  mode_word_t;
-		sdr_cke			: out  STD_LOGIC
-	);
-end sdram_ctrl;
-
-architecture behaviour of sdram_ctrl is
-
-	constant LMR_BURST_LEN		: natural := NextExpBaseTwo(BL);
-
-	type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH);
-	signal st_ctrl, st_ctrl_next : ctrl_state_t;
-	
-	constant PWR_UP_CLOCK_INTERVAL : natural := to_cycles(PWR_UP_WAIT, f_sysclk);
-	signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1;
-	signal pwr_up_cnt_rst : std_logic;
-	signal pwr_up_finished : std_logic;
-
-	signal cycle_cnt : natural range 0 to 255;
-	signal cc_preset : natural range 0 to 255;
-	signal cc_load_en : std_logic;
-	signal cycle_finished : std_logic;
-
-	signal seq_cnt : natural range 0 to 31;
-	signal seq_rst_en : std_logic;
-	signal seq_cnt_en : std_logic;
-	
-	constant REFRESH_CLOCK_INTERVAL : natural := to_cycles(REFRESH_INTERVAL, f_sysclk);
-	signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1;
-	signal refresh_request : std_logic;
-	signal refresh_cnt_rst : std_logic;
-
-	signal addr_reg_load_en : std_logic;
-
-	signal u_tag_reg : user_tag_t;
-	signal bank_addr_reg : bank_addr_t;
-	signal row_addr_reg : row_addr_t;
-	signal col_addr_reg : col_addr_t;
-	signal bank_addr_last : bank_addr_t;
-	signal row_addr_last : row_addr_t;
-	signal col_addr_last : col_addr_t;
-
-	signal u_bank_addr : bank_addr_t;
-	signal u_row_addr : row_addr_t;
-	signal u_col_addr : col_addr_t;
-
-	signal bank_active_reg : unsigned(0 to 3);
-	signal bank_is_active : std_logic;
-	signal bank_activate : std_logic;
-	signal bank_clr : std_logic;
-
-	type init_seq_rom_t is array (0 to 14) of init_seq_t;
-	
-	constant init_seq_rom : init_seq_rom_t :=
-	(
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_PRE,
-			mode_word	=> "000010000000000",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
-			wait_cycle	=> 200
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_PRE,
-			mode_word	=> "000010000000000",
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_AR,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_AR,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		),
-		(
-			cmd			=> SD_LMR,
-			mode_word	=> to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3),
-			wait_cycle	=> 200
-		),
-		(
-			cmd			=> SD_NOP,
-			mode_word	=> (others => '0'),
-			wait_cycle	=> 0
-		)
-	
-	);
-		
-begin
-
-	u_row_addr		<= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1);
-	u_bank_addr		<= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1);
-	u_col_addr		<= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0);
-	bank_is_active	<= bank_active_reg(to_integer(u_bank_addr));
-
-------------------------------------------------------------------------------------------
-fsm_ctrl_state:
-	process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, bank_addr_last, row_addr_last, refresh_request, bank_is_active)
-	begin
-
-		u_busy 				<= '1';
-		pwr_up_cnt_rst		<= '0';
-		cc_preset			<= init_seq_rom(seq_cnt).wait_cycle;
-		cc_load_en			<= '0';
-		sdr_cmd				<= init_seq_rom(seq_cnt).cmd;
-		sdr_cmd_we			<= '0';
-		sdr_mode			<= bank_addr_reg & row_addr_reg;
-		col_addr			<= col_addr_reg;
-		sdr_cke				<= '1';
-		seq_cnt_en			<= '0';
-		seq_rst_en			<= '0';
-		addr_reg_load_en	<= '0';
-		refresh_cnt_rst		<= '0';
-		bank_activate		<= '0';
-		bank_clr			<= '0';
-		u_tag_out			<= u_tag_reg;
-		
-		st_ctrl_next		<= st_ctrl;
-		case st_ctrl is 
-		when RESET =>
-			sdr_cke			<= '0';
-			pwr_up_cnt_rst	<= '1';
-			st_ctrl_next	<= POWER_WAIT;
-			
-		when POWER_WAIT =>
-			sdr_cke			<= '0';
-			if pwr_up_finished = '1' then
-				seq_rst_en		<= '1';
-				st_ctrl_next	<= INIT;
-			end if;	
-
-		when INIT =>
-			sdr_mode	<= init_seq_rom(seq_cnt).mode_word;
-			sdr_cmd		<= init_seq_rom(seq_cnt).cmd;
-			cc_preset	<= init_seq_rom(seq_cnt).wait_cycle;
-			if seq_cnt = init_seq_rom_t'high then
-				bank_clr		<= '1';
-				refresh_cnt_rst	<= '1';
-				st_ctrl_next	<= USER_READY;
-			elsif sdr_cmd_busy = '0' then
-				cc_load_en		<= '1';
-				sdr_cmd_we		<= '1';
-				st_ctrl_next	<= INIT_WAIT;
-			end if;	
-				
-		when INIT_WAIT =>
-			if sdr_cmd_busy = '0' and cycle_finished = '1' then
-				seq_cnt_en		<= '1';
-				st_ctrl_next	<= INIT;
-			end if;	
-			
-		when USER_READY =>
-			if refresh_request = '1' then
-				st_ctrl_next	<= REFRESH_PRE;
-			else	
-				u_busy		<= '0';
-				col_addr				<= u_col_addr;
-				u_tag_out				<= u_tag_in;
-				sdr_mode				<= u_bank_addr & u_row_addr;
-				sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
-				if u_cmd_we = '1' then
-					addr_reg_load_en		<= '1';
-					case u_cmd is
-					when UCMD_NOP =>
-						sdr_cmd		<= SD_NOP;
-					when UCMD_LMR =>
-						sdr_cmd		<= SD_NOP;
-					when UCMD_WRITE =>
-						sdr_cmd					<= SD_WRITE;
-						if (u_row_addr /= row_addr_reg) then
-							st_ctrl_next		<= USER_WRITE_PRE;
-						elsif bank_is_active = '0' then
-							st_ctrl_next		<= USER_WRITE_ACT;
-						elsif sdr_cmd_busy = '1' then
-							st_ctrl_next		<= USER_WRITE;
-						else
-							sdr_cmd_we			<= '1';
-						end if;
-					when UCMD_READ =>
-						sdr_cmd					<= SD_READ;
-						if (u_row_addr /= row_addr_reg) then
-							st_ctrl_next		<= USER_READ_PRE;
-						elsif bank_is_active = '0' then
-							st_ctrl_next		<= USER_READ_ACT;
-						elsif sdr_cmd_busy = '1' then
-							st_ctrl_next		<= USER_READ;
-						else
-							sdr_cmd_we			<= '1';
-						end if;
-					when others => null;
-					end case;
-				end if;	
-			end if;	
-
-		when USER_WRITE_PRE =>
-		bank_clr		<= '1';
-		sdr_cmd					<= SD_PRE;
-		sdr_mode				<= bank_addr_last & row_addr_last;
-		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_WRITE_ACT;
-		end if;
-
-		when USER_WRITE_ACT =>
-		bank_activate	<= '1';
-		sdr_cmd				<= SD_ACT;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_WRITE;
-		end if;
-
-		when USER_WRITE =>
-		sdr_cmd					<= SD_WRITE;
-		sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-		end if;
-
-		when USER_READ_PRE =>
-		bank_clr		<= '1';
-		sdr_cmd			<= SD_PRE;
-		sdr_mode				<= bank_addr_last & row_addr_last;
-		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READ_ACT;
-		end if;
-
-		when USER_READ_ACT =>
-		bank_activate	<= '1';
-		sdr_cmd					<= SD_ACT;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READ;
-		end if;
-
-		when USER_READ =>
-		sdr_cmd					<= SD_READ;
-		sdr_mode(BIT_AUTO_PRE)	<= ENABLE_AUTO_PRE;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-		end if;
-
-		when REFRESH_PRE =>
-		bank_clr		<= '1';
-		sdr_cmd					<= SD_PRE;
---		sdr_mode				<= bank_addr_last & row_addr_last;
-		sdr_mode(BIT_PRE_ALL)	<= ENABLE_PRE_ALL;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= REFRESH;
-		end if;
-
-		when REFRESH =>
-		sdr_cmd			<= SD_AR;
-		if sdr_cmd_busy = '0' then
-			sdr_cmd_we		<= '1';
-			st_ctrl_next	<= USER_READY;
-			refresh_cnt_rst	<= '1';
-		end if;
-		
-		when others =>
-			st_ctrl_next <= RESET;
-		end case;
-		
-	end process;
-	
-fsm_ctrl_state_next:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			st_ctrl		<= RESET;
-		elsif rising_edge(clk) then
-			st_ctrl		<= st_ctrl_next;
-		end if;
-	end process;
-	
-------------------------------------------------------------------------------------------
-bank_active_register:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			if bank_clr = '1' then
-				bank_active_reg <= (others => '0');		-- assumes PRE_ALL !!!!!!!!!!!!!
-			elsif bank_activate = '1' then	
-				bank_active_reg(to_integer(bank_addr_reg)) <= '1';
-			end if;	
-		end if;
-	end process;
-
-
-------------------------------------------------------------------------------------------
-user_addr_register:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			bank_addr_reg <= (others => '0');
-			row_addr_reg <= (others => '0');
-			col_addr_reg <= (others => '0');
-			u_tag_reg <= (others => '0');
-		elsif rising_edge(clk) then
-			if addr_reg_load_en = '1' then
-				bank_addr_last <= bank_addr_reg;
-				row_addr_last <= row_addr_reg;
-				col_addr_last <= col_addr_reg;
-				bank_addr_reg <= u_bank_addr;
-				row_addr_reg <= u_row_addr;
-				col_addr_reg <= u_col_addr;
-				u_tag_reg <= u_tag_in;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-power_up_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			pwr_up_cnt	<= 0;
-			pwr_up_finished <= '0';
-		elsif rising_edge(clk) then
-			pwr_up_finished <= '0';
-			if pwr_up_cnt_rst = '1' then
-				pwr_up_cnt	<= PWR_UP_CLOCK_INTERVAL-1;
-			else
-				if pwr_up_cnt /= 0 then
-					pwr_up_cnt <= pwr_up_cnt - 1;
-				else
-					pwr_up_finished <= '1';
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-
-------------------------------------------------------------------------------------------
-refresh_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			refresh_cnt	<= 0;
-			refresh_request <= '0';
-		elsif rising_edge(clk) then
-			refresh_request <= '0';
-			if refresh_cnt_rst = '1' then
-				refresh_cnt	<= REFRESH_CLOCK_INTERVAL-1;
-			else
-				if refresh_cnt /= 0 then
-					refresh_cnt <= refresh_cnt - 1;
-				else
-					refresh_request <= '1';
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-cycle_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			cycle_cnt	<= 0;
-			cycle_finished	<= '0';
-		elsif rising_edge(clk) then
-			cycle_finished	<= '0';
-			if cc_load_en = '1' then
-				cycle_cnt <= cc_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt <= cycle_cnt - 1;
-			else
-				cycle_finished	<= '1';
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-seq_counter:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			seq_cnt	<= 0;
-		elsif rising_edge(clk) then
-			if seq_rst_en = '1' then
-				seq_cnt <= 0;
-			elsif seq_cnt_en = '1' then
-				if seq_cnt /= init_seq_rom_t'high then
-					seq_cnt <= seq_cnt + 1;
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------------------------------------
-end behaviour;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
deleted file mode 100644
index 5d997c3..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_frontend64_wb is
-	Generic
-	(
-		BL 				: natural	:= 2;
-		f_sysclk		: real		:= 100.0;
-		f_sdrclk	 	: real		:= 100.0;
-		fifo_depth		: integer	:= 4
-	);
-	Port
-	(
-		RST_I				: in  STD_LOGIC;
-		CLK_I				: in  STD_LOGIC;
-		SDRAM_CLK0_I		: in  STD_LOGIC;
-		SDRAM_CLK270_I		: in  STD_LOGIC;
-		SDRAM_CLK270VAR_I	: in  STD_LOGIC;
-		
-		CYC_I				: in  STD_LOGIC;
-		STB_I				: in  STD_LOGIC;
-		SEL_I				: in  unsigned(SDR_DM_WIDTH-1 downto 0);
-		WE_I				: in  STD_LOGIC;
-		ACK_O				: out STD_LOGIC;
-		MRDY_I				: in  STD_LOGIC;
-		SRDY_O				: out STD_LOGIC;
-		ADDR_I				: in  unsigned(31 downto 0);
-		DAT_I				: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		DAT_O				: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-
-		-- SDRAM signals
-		sd_clk_p			: out  STD_LOGIC;
-		sd_clk_n			: out  STD_LOGIC;
-		sd_cke				: out  STD_LOGIC;
-		sd_cs_n				: out  STD_LOGIC;
-		sd_cas_n			: out  STD_LOGIC;
-		sd_ras_n			: out  STD_LOGIC;
-		sd_we_n				: out  STD_LOGIC;
-		sd_addr				: out  sdr_addr_t;
-		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
-		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-		
-	);
-end sdram_ctrl_frontend64_wb;
-
-architecture struct of sdram_ctrl_frontend64_wb is
-
-	-- Number of user data words for simulation
-	signal u_addr			: user_addr_t;
-	signal u_tag_in			: user_tag_t;
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t;
-	signal u_cmd_we			: std_logic;
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal rdy				: std_logic;
-
-	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
-	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_re				: std_logic;
-	signal cat_fifo_we				: std_logic;
-	signal cat_fifo_full			: std_logic;
-	signal cat_fifo_empty			: std_logic;
---	signal cat_fifo_almost_full		: std_logic;
---	signal cat_fifo_almost_empty	: std_logic;
-
-	signal write_fifo_din			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal write_fifo_dout			: unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0);
-	signal write_fifo_re			: std_logic;
-	signal write_fifo_we			: std_logic;
-	signal write_fifo_full			: std_logic;
-	signal write_fifo_empty			: std_logic;
---	signal write_fifo_almost_full	: std_logic;
---	signal write_fifo_almost_empty	: std_logic;
-
-	signal read_fifo_din			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal read_fifo_dout			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal read_fifo_re				: std_logic;
-	signal read_fifo_we				: std_logic;
-	signal read_fifo_full			: std_logic;
-	signal read_fifo_empty			: std_logic;
---	signal read_fifo_almost_full	: std_logic;
---	signal read_fifo_almost_empty	: std_logic;
-
-	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
-	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
-
-	alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
-	alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0);
-	alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
-	alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
-
-	alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0);
-	alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0);
-	
-begin 
-   
-	-- Instantiate synchronous FIFO
-	inst_cat_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> CAT_FIFO_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	cat_fifo_we,
-		re			=>	cat_fifo_re,
-		fifo_full	=>	cat_fifo_full,
-		fifo_empty	=>	cat_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cat_fifo_din,
-		data_r		=>  cat_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_write_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> write_fifo_din'length
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	CLK_I,
-		clk_r		=>	SDRAM_CLK0_I,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  write_fifo_din,
-		data_r		=>  write_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_read_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> read_fifo_din'length
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	SDRAM_CLK0_I,
-		clk_r		=>	CLK_I,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  read_fifo_din,
-		data_r		=>  read_fifo_dout
-	);
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BL,
-		f_sysclk 		=> f_sysclk,
-		f_sdrclk		=> f_sdrclk,
-		fifo_depth		=> fifo_depth
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> RST_I,
-		sys_clk_in			=> CLK_I,
-
-		sdram_clk0_in		=> SDRAM_CLK0_I,
-		sdram_clk270_in		=> SDRAM_CLK270_I,
-		sdram_clk270_rd_in	=> SDRAM_CLK270VAR_I,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm_wr_in,
-		
-		-- SDRAM signals
-		sd_clk_p			=> sd_clk_p,
-		sd_clk_n			=> sd_clk_n,
-		sd_cke				=> sd_cke,
-		sd_cs_n				=> sd_cs_n,
-		sd_cas_n			=> sd_cas_n,
-		sd_ras_n			=> sd_ras_n,
-		sd_we_n				=> sd_we_n,
-		sd_addr				=> sd_addr,
-		sd_ba				=> sd_ba,
-		sd_dm				=> sd_dm,
-		sd_dqs				=> sd_dqs,
-		sd_data				=> sd_data
-		
-	);
-
-------------------------------------------------------------------------------------------
-	SRDY_O				<= rdy;
-	ACK_O				<= not (read_fifo_empty);
-	DAT_O				<= read_fifo_data_out;
-	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
-	write_fifo_we 		<= STB_I and WE_I and rdy;
-	write_fifo_data_in	<= DAT_I;
-	write_fifo_dm_in	<= not SEL_I;
-	cat_fifo_we			<= STB_I and rdy;
-	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
-	addr_fifo_in		<= ADDR_I(25 downto 3) & "0";
-	tag_fifo_in			<= "000" & ADDR_I(2);
-	
-	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
-	u_cmd				<= cmd_fifo_out;
-	u_addr				<= addr_fifo_out;
-	u_dm_wr_in			<= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH);
-	u_tag_in			<= tag_fifo_out;
-	u_data_w			<= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
-	
-	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
-	cat_fifo_re			<= u_cmd_we;
-	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
-	read_fifo_we		<= u_data_vld;
-	read_fifo_data_in	<= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0);	
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
deleted file mode 100644
index 57002b9..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+++ /dev/null
@@ -1,278 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_frontend_wb is
-	Generic
-	(
-		BL 				: natural	:= 2;
-		f_sysclk 		: real		:= 100.0;
-		f_sdrclk 		: real		:= 100.0;
-		fifo_depth		: integer := 4
-	);
-	Port
-	(
-		RST_I				: in  STD_LOGIC;
-		CLK_I				: in  STD_LOGIC;
-		SDRAM_CLK0_I		: in  STD_LOGIC;
-		SDRAM_CLK270_I		: in  STD_LOGIC;
-		SDRAM_CLK270VAR_I	: in  STD_LOGIC;
-		
-		CYC_I				: in  STD_LOGIC;
-		STB_I				: in  STD_LOGIC;
-		SEL_I				: in  unsigned(3 downto 0);
-		WE_I				: in  STD_LOGIC;
-		ACK_O				: out STD_LOGIC;
-		MRDY_I				: in  STD_LOGIC;
-		SRDY_O				: out STD_LOGIC;
-		ADDR_I				: in  unsigned(31 downto 0);
-		DAT_I				: in  unsigned(31 downto 0);
-		DAT_O				: out unsigned(31 downto 0);
-
-		-- SDRAM signals
-		sd_clk_p			: out  STD_LOGIC;
-		sd_clk_n			: out  STD_LOGIC;
-		sd_cke				: out  STD_LOGIC;
-		sd_cs_n				: out  STD_LOGIC;
-		sd_cas_n			: out  STD_LOGIC;
-		sd_ras_n			: out  STD_LOGIC;
-		sd_we_n				: out  STD_LOGIC;
-		sd_addr				: out  sdr_addr_t;
-		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out unsigned(DDR_DM_WIDTH-1 downto 0);
-		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-		
-	);
-end sdram_ctrl_frontend_wb;
-
-architecture struct of sdram_ctrl_frontend_wb is
-
-	-- Number of user data words for simulation
-	signal u_addr			: user_addr_t;
-	signal u_tag_in			: user_tag_t;
-	signal u_tag_rd			: user_tag_t;
-	signal u_tag_wr			: user_tag_t;
-	signal u_cmd			: user_cmd_t;
-	signal u_cmd_we			: std_logic;
-	signal u_busy			: std_logic;
-	signal u_data_w			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_dm_wr_in		: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal u_data_r			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal u_data_vld		: std_logic;
-	signal u_req_wr			: std_logic;
-	signal rdy				: std_logic;
-
-	constant CAT_FIFO_WIDTH			: integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH;
-	signal cat_fifo_din				: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_dout			: unsigned(CAT_FIFO_WIDTH-1 downto 0);
-	signal cat_fifo_re				: std_logic;
-	signal cat_fifo_we				: std_logic;
-	signal cat_fifo_full			: std_logic;
-	signal cat_fifo_empty			: std_logic;
---	signal cat_fifo_almost_full		: std_logic;
---	signal cat_fifo_almost_empty	: std_logic;
-
-	signal write_fifo_din			: unsigned(35 downto 0);
-	signal write_fifo_dout			: unsigned(35 downto 0);
-	signal write_fifo_re			: std_logic;
-	signal write_fifo_we			: std_logic;
-	signal write_fifo_full			: std_logic;
-	signal write_fifo_empty			: std_logic;
---	signal write_fifo_almost_full	: std_logic;
---	signal write_fifo_almost_empty	: std_logic;
-
-	signal read_fifo_din			: unsigned(31 downto 0);
-	signal read_fifo_dout			: unsigned(31 downto 0);
-	signal read_fifo_re				: std_logic;
-	signal read_fifo_we				: std_logic;
-	signal read_fifo_full			: std_logic;
-	signal read_fifo_empty			: std_logic;
---	signal read_fifo_almost_full	: std_logic;
---	signal read_fifo_almost_empty	: std_logic;
-
-	alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
-	alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length);
-	alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length);
-	alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0);
-
-	alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4);
-	alias write_fifo_dm_in is write_fifo_din(3 downto 0);
-	alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4);
-	alias write_fifo_dm_out is write_fifo_dout(3 downto 0);
-
-	alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0);
-	alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0);
-	
-begin 
-   
-	-- Instantiate synchronous FIFO
-	inst_cat_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> CAT_FIFO_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	cat_fifo_we,
-		re			=>	cat_fifo_re,
-		fifo_full	=>	cat_fifo_full,
-		fifo_empty	=>	cat_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cat_fifo_din,
-		data_r		=>  cat_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_write_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> write_fifo_din'length
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	CLK_I,
-		clk_r		=>	SDRAM_CLK0_I,
-		we			=>	write_fifo_we,
-		re			=>	write_fifo_re,
-		fifo_full	=>	write_fifo_full,
-		fifo_empty	=>	write_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  write_fifo_din,
-		data_r		=>  write_fifo_dout
-	);
-
-	-- Instantiate synchronous FIFO
-	inst_read_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width	=> fifo_depth,
-		data_width	=> read_fifo_din'length
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk_w		=>	SDRAM_CLK0_I,
-		clk_r		=>	CLK_I,
-		we			=>	read_fifo_we,
-		re			=>	read_fifo_re,
-		fifo_full	=>	read_fifo_full,
-		fifo_empty	=>	read_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  read_fifo_din,
-		data_r		=>  read_fifo_dout
-	);
-
-	-- DDR SDRAM Controller Core
-	inst_sdram_ctrl : entity work.sdram_ctrl_top
-	Generic map
-	(
-		BL 				=> BL,
-		f_sysclk 		=> f_sysclk,
-		f_sdrclk		=> f_sdrclk,
-		fifo_depth		=> fifo_depth
-	)
-	Port map
-	(
-	
-		sys_rst_in			=> RST_I,
-		sys_clk_in			=> CLK_I,
-
-		sdram_clk0_in		=> SDRAM_CLK0_I,
-		sdram_clk270_in		=> SDRAM_CLK270_I,
-		sdram_clk270_rd_in	=> SDRAM_CLK270VAR_I,
-		
-		-- User interface
-		u_data_vld			=> u_data_vld,
-		u_data_req_w		=> u_req_wr,
-		u_tag_in			=> u_tag_in,
-		u_tag_rd			=> u_tag_rd,
-		u_tag_wr			=> u_tag_wr,
-		u_busy				=> u_busy,
-		u_addr				=> u_addr,
-		u_cmd				=> u_cmd,
-		u_cmd_we			=> u_cmd_we,
-		u_data_wr			=> u_data_w,
-		u_data_rd			=> u_data_r,
-		u_dm				=> u_dm_wr_in,
-		
-		-- SDRAM signals
-		sd_clk_p			=> sd_clk_p,
-		sd_clk_n			=> sd_clk_n,
-		sd_cke				=> sd_cke,
-		sd_cs_n				=> sd_cs_n,
-		sd_cas_n			=> sd_cas_n,
-		sd_ras_n			=> sd_ras_n,
-		sd_we_n				=> sd_we_n,
-		sd_addr				=> sd_addr,
-		sd_ba				=> sd_ba,
-		sd_dm				=> sd_dm,
-		sd_dqs				=> sd_dqs,
-		sd_data				=> sd_data
-		
-	);
-
-------------------------------------------------------------------------------------------
-	SRDY_O				<= rdy;
-	ACK_O				<= not (read_fifo_empty);
-	DAT_O				<= read_fifo_data_out;
-	rdy					<= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I;
-	write_fifo_we 		<= STB_I and WE_I and rdy;
-	write_fifo_data_in	<= DAT_I;
-	write_fifo_dm_in	<= not SEL_I;
-	cat_fifo_we			<= STB_I and rdy;
-	cmd_fifo_in			<= UCMD_WRITE when WE_I = '1' else UCMD_READ;
-	addr_fifo_in		<= ADDR_I(24 downto 2) & "0";
-	tag_fifo_in			<= "000" & ADDR_I(25);
-	
-	u_cmd_we			<= (not cat_fifo_empty) and (not u_busy);
-	u_cmd				<= cmd_fifo_out;
-	u_addr				<= addr_fifo_out;
-	u_dm_wr_in			<= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111");
-	u_tag_in			<= tag_fifo_out;
-	u_data_w			<= write_fifo_data_out & write_fifo_data_out;
-	
-	write_fifo_re		<= u_req_wr and (not write_fifo_empty);
-	cat_fifo_re			<= u_cmd_we;
-	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
-	read_fifo_we		<= u_data_vld;
-	read_fifo_data_in	<= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32);	
-
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
deleted file mode 100644
index 8d4a9a4..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+++ /dev/null
@@ -1,237 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Top-level put all together
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity sdram_ctrl_top is
-	Generic
-	(
-		BL 				: natural	:= 2;
-		f_sysclk		: real		:= 100.0;
-		f_sdrclk		: real		:= 100.0;
-		fifo_depth		: natural := 3
-	);
-	Port
-	(
-		sys_rst_in			: in  STD_LOGIC;
-		sys_clk_in			: in  STD_LOGIC;
-		
-		sdram_clk0_in		: in  STD_LOGIC;
-		sdram_clk270_in		: in  STD_LOGIC;
-		sdram_clk270_rd_in	: in  STD_LOGIC;
-		
-		-- User interface
-		u_data_vld			: out STD_LOGIC;
-		u_data_req_w		: out STD_LOGIC;
-		u_busy				: out STD_LOGIC;
-		u_tag_in			: in  user_tag_t;
-		u_tag_rd			: out user_tag_t;
-		u_tag_wr			: out user_tag_t;
-		u_addr				: in  user_addr_t;
-		u_cmd				: in  user_cmd_t;
-		u_cmd_we			: in  STD_LOGIC;
-		u_data_wr			: in  unsigned(SDR_DATA_WIDTH-1 downto 0);
-		u_dm				: in unsigned(SDR_DM_WIDTH-1 downto 0);
-		u_data_rd			: out unsigned(SDR_DATA_WIDTH-1 downto 0);
-		
-		-- SDRAM signals
-		sd_clk_p			: out  STD_LOGIC;
-		sd_clk_n			: out  STD_LOGIC;
-		sd_cke				: out  STD_LOGIC;
-		sd_cs_n				: out  STD_LOGIC;
-		sd_cas_n			: out  STD_LOGIC;
-		sd_ras_n			: out  STD_LOGIC;
-		sd_we_n				: out  STD_LOGIC;
-		sd_addr				: out  sdr_addr_t;
-		sd_ba				: out  sdr_ba_t;
-		sd_dm				: out  unsigned(DDR_DM_WIDTH-1 downto 0);
-		sd_dqs				: inout unsigned(DDR_DQS_WIDTH-1 downto 0);
-		sd_data				: inout unsigned(DDR_DATA_WIDTH-1 downto 0)
-		
-	);
-end sdram_ctrl_top;
-
-architecture rtl of sdram_ctrl_top is
-
-
-	signal phy_ctrl			: phy_ctrl_t;
-
-	signal u_tag			: user_tag_t;
-	signal sd_cmd_in		: sdr_cmd_t;
-	signal sd_cmd			: sdr_cmd_t;
-	signal sd_cmd_we		: std_logic;
-	signal cmd_ctrl			: sdr_cmd_lines_t;
-	signal cke				: std_logic;
-	signal ba				: unsigned(DDR_BANK_WIDTH-1 downto 0);
-	signal addr				: unsigned(DDR_ADDR_WIDTH-1 downto 0);
-
-	-- Clock generator
-
-	signal part_ctrl		: part_ctrl_t;  
-
-	-- SD command FIFO
-
-	constant CMD_FIFO_DATA_WIDTH	: positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
-	signal cmd_fifo_din				: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
-	signal cmd_fifo_dout			: unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
-	signal cmd_fifo_re				: std_logic;
-	signal cmd_fifo_we				: std_logic;
-	signal cmd_fifo_full			: std_logic;
-	signal cmd_fifo_empty			: std_logic;
-
-	alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
-	alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
-	alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
-	alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
-	alias sd_tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
-	alias sd_cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
-	alias sd_mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
-	alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
-
-begin 
-      	
-	---------------------------------
-	part_ctrl.cmd	<= cmd_ctrl;
-	part_ctrl.ba	<= ba;
-	part_ctrl.addr	<= addr;
-	part_ctrl.cke	<= cke;
-
-	---------------------------------
-	sd_cmd_we		<= not cmd_fifo_empty;
-	cmd_fifo_in		<= to_unsigned(sd_cmd_in, 4);
-	sd_cmd			<= sdr_cmd_t(to_integer(sd_cmd_fifo_out));
-
-	---------------------------------
-
-	-- Main controller
-	inst_sdram_ctrl : entity work.sdram_ctrl
-	Generic map 
-	(
-		f_sysclk		=> f_sysclk,
-		BL				=> BL
-	)
-	Port map 
-	(
-		rst				=> sys_rst_in,
-		clk				=> sys_clk_in,
-		u_busy			=> u_busy,
-		u_tag_in		=> u_tag_in,
-		u_tag_out		=> tag_fifo_in,
-		u_cmd			=> u_cmd,
-		u_cmd_we		=> u_cmd_we,
-		u_addr			=> u_addr,
-		sdr_cmd_busy	=> cmd_fifo_full,
-		sdr_cmd			=> sd_cmd_in,
-		sdr_cmd_we		=> cmd_fifo_we,
-		col_addr		=> col_fifo_in,
-		sdr_mode		=> mode_fifo_in,
-		sdr_cke			=> cke
-	);
-   
-	-- Instantiate synchronous FIFO
-	inst_sd_cmd_fifo: entity work.fifo_async
-	GENERIC MAP
-	(
-		addr_width			=> fifo_depth,
-		data_width			=> CMD_FIFO_DATA_WIDTH
-	)
-	PORT MAP
-	(
-		rst			=>	sys_rst_in,
-		clk_w		=>	sys_clk_in,
-		clk_r		=>	sdram_clk0_in,
-		we			=>	cmd_fifo_we,
-		re			=>	cmd_fifo_re,
-		fifo_full	=>	cmd_fifo_full,
-		fifo_empty	=>	cmd_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  cmd_fifo_din,
-		data_r		=>  cmd_fifo_dout
-	);
-
-	-- DDR SDRAM command fsm
-	inst_sdram_cmd : entity work.sdram_cmd
-	Generic map
-	(
-		f_sdrclk		=> f_sdrclk,
-		BL				=> BL
-	)
-	Port map
-	(
-		rst				=> sys_rst_in,
-		clk				=> sdram_clk0_in,
-		u_tag_in		=> sd_tag_fifo_out,
-		u_tag_out		=> u_tag,
-		phy_ctrl		=> phy_ctrl,
-		enable			=> cke,
-		cmd				=> sd_cmd,
-		cmd_we			=> sd_cmd_we,
-		cmd_ack			=> cmd_fifo_re,
-		sdr_cmd_ctrl	=> cmd_ctrl,
-		col_addr		=> sd_col_fifo_out,
-		mode_word		=> sd_mode_fifo_out,
-		sdr_ba			=> ba,
-		sdr_addr		=> addr
-	);
-   
-	-- DDR phy
-	inst_ddr_phy : entity work.ddr_phy
-	Port map
-	(
-		sys_rst			=> sys_rst_in,
-		sys_clk0		=> sdram_clk0_in,
-		sys_clk270		=> sdram_clk270_in,
-		u_tag_in		=> u_tag,
-		u_tag_rd		=> u_tag_rd,
-		u_tag_wr		=> u_tag_wr,
-		read_clk		=> sdram_clk270_rd_in,
-		phy_ctrl		=> phy_ctrl,
-		part_ctrl		=> part_ctrl,
-		sdr_data_req_w	=> u_data_req_w,
-		sdr_data_w		=> u_data_wr,
-		sdr_dm			=> u_dm,
-		sdr_data_r		=> u_data_rd,
-		sdr_data_vld	=> u_data_vld,
-		part_clk_p		=> sd_clk_p,
-		part_clk_n		=> sd_clk_n,
-		part_addr		=> sd_addr,
-		part_ba			=> sd_ba,
-		part_dm			=> sd_dm,
-		part_dqs		=> sd_dqs,
-		part_data		=> sd_data,
-		part_cs_n		=> sd_cs_n,
-		part_we_n		=> sd_we_n,
-		part_cas_n		=> sd_cas_n,
-		part_ras_n		=> sd_ras_n,
-		part_cke		=> sd_cke
-	);
-   
-end architecture rtl;
-
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
deleted file mode 100644
index 5520b28..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+++ /dev/null
@@ -1,130 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Type definitions
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
-
-use work.sdram_config.all;
-
-package sdram_types is
-
-	-----------------------------------------------------------------------------------------
-	-- Table of Timing Parameters as a function of operation
-
-	-- Derived constants from sdram_config
-
-	constant DDR_DQS_WIDTH  	: positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines
-	constant DDR_DM_WIDTH   	: positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines
-	constant SDR_DATA_WIDTH 	: positive := 2*DDR_DATA_WIDTH;  -- 
-	constant SDR_DM_WIDTH		: positive := 2*DDR_DM_WIDTH;  -- 
-
-	subtype user_cmd_t is unsigned(1 downto 0);
-	constant UCMD_NOP			: user_cmd_t := "00";
-	constant UCMD_READ			: user_cmd_t := "01";
-	constant UCMD_WRITE			: user_cmd_t := "10";
-	constant UCMD_LMR			: user_cmd_t := "11";
-
-	subtype sdr_cmd_t is natural range 0 to 9;
-	constant SD_DESELECT		: sdr_cmd_t := 0;
-	constant SD_NOP				: sdr_cmd_t := 1;
-	constant SD_LMR				: sdr_cmd_t := 2;
-	constant SD_ACT				: sdr_cmd_t := 3;
-	constant SD_READ			: sdr_cmd_t := 4;
-	constant SD_WRITE			: sdr_cmd_t := 5;
-	constant SD_PRE				: sdr_cmd_t := 6;
-	constant SD_BST				: sdr_cmd_t := 7;
-	constant SD_AR				: sdr_cmd_t := 8;
-	constant SD_SR				: sdr_cmd_t := 9;
-	
-	type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN);
-	subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0);
-	subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
-	subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
-	subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0);
-
-	subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0);
-	subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0);
-	subtype col_addr_t is unsigned(8 downto 0);
-	
-	type phy_ctrl_t is
-	record
-		drive_en		: std_logic;
-		re				: std_logic;
-		we				: std_logic;
-		utag_we			: std_logic;
-	end record phy_ctrl_t;
-
-	type sdr_cmd_lines_t is
-	record
-         cs_n    : std_logic;
-         ras_n   : std_logic;
-         cas_n   : std_logic;
-         we_n    : std_logic;
-	end record sdr_cmd_lines_t;
-
-	type part_ctrl_t is
-	record
-		cmd		: sdr_cmd_lines_t;
-		ba	 	: unsigned(DDR_BANK_WIDTH-1 downto 0);
-		addr	: unsigned(DDR_ADDR_WIDTH-1 downto 0);
-		cke		: std_logic;
-	end record part_ctrl_t;
-	
-	type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t;
-	constant COMMAND : part_cmd_array_t :=
-	--	 command                 cs_n     ras_qn      cas_qn      we_qn
-	(	SD_DESELECT         =>   (   '1',      '1',        '1',        '1'),
-		SD_NOP              =>   (   '0',      '1',        '1',        '1'),
-		SD_LMR              =>   (   '0',      '0',        '0',        '0'),
-		SD_ACT              =>   (   '0',      '0',        '1',        '1'),
-		SD_READ             =>   (   '0',      '1',        '0',        '1'),
-		SD_WRITE            =>   (   '0',      '1',        '0',        '0'),
-		SD_PRE              =>   (   '0',      '0',        '1',        '0'),
-		SD_BST              =>   (   '0',      '1',        '1',        '0'),
-		SD_AR               =>   (   '0',      '0',        '0',        '1'),
-		SD_SR               =>   (   '0',      '0',        '0',        '1')
-	);
-
-	type init_seq_t is 
-	record
-		cmd			: sdr_cmd_t;
-		mode_word	: mode_word_t;
-		wait_cycle	: natural;
-	end record init_seq_t;	
-	
-	function to_cycles(T_ns : real; f_Mhz : real) return natural;
-	
-end sdram_types;
-
-package body sdram_types is
-
-	function to_cycles(T_ns : real; f_Mhz : real) return natural is
-	begin
-		
-		return natural(ceil(1.0E-3*T_ns*f_Mhz));
-
-	end to_cycles;	
-
-end sdram_types;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
deleted file mode 100644
index fdfd07d..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+++ /dev/null
@@ -1,871 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdram_ctrl_frontend64_wb is
-end;
-
-architecture struct of tb_sdram_ctrl_frontend64_wb is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant SDCLK_PERIOD	: time := 7.5 ns;
-	constant BURST_LEN		: natural := 2;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '1';  
-	signal sdclk			: std_logic := '1';  
-	signal locked			: std_logic;  
-	signal error			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal CLK_O			: std_logic;
-	signal CLK0_O			: std_logic;
-	signal CLK270_O			: std_logic;
-	signal CLK270VAR_O		: std_logic;
-	signal RST_O			: std_logic;
-	signal CYC_O			: std_logic := '0';
-	signal STB_O			: std_logic := '0';
-	signal WE_O				: std_logic := '0';
-	signal SEL_O			: unsigned(SDR_DM_WIDTH-1 downto 0);
-	signal ACK_I			: std_logic;
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic;
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-	signal DAT_O			: unsigned(SDR_DATA_WIDTH-1 downto 0);
-
-	signal dout_rst			: std_logic := '0';
-	signal dout_reg			: unsigned(31 downto 0);
-	signal dout_cnt			: natural range 0 to 255;
-
-	signal sddat			: unsigned(31 downto 0) := (others => '-');
-	signal sdsel			: unsigned(3 downto 0) := (others => '1');
-
-	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
-	signal sd_cmd : sd_cmd_t;
-	
-begin 
-   
-	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
-	variable cmd : unsigned (2 downto 0);
-
-	begin
-		cmd := part_ras_n & part_cas_n & part_we_n;
-		sd_cmd <= nop;
-		if part_cs_n = '0' then
-			case cmd is
-				when "000" =>
-					sd_cmd <= lmr;
-				when "001" =>
-					sd_cmd <= ar;
-				when "010" =>
-					sd_cmd <= pre;
-				when "011" =>
-					sd_cmd <= act;
-				when "100" =>
-					sd_cmd <= write;
-				when "101" =>
-					sd_cmd <= read;
-				when "110" =>
-					sd_cmd <= bst;
-				when "111" =>
-					sd_cmd <= nop;
-				
-				when others =>
-					sd_cmd <= nop;
-
-			end case;
-		end if;
-	end process;
-	
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		clk_in_freq			=> 100.0,
-		clk0_out_phaseshift	=> 0,
-		clk1_out_phaseshift	=> 0
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst				=> rst,   -- external async reset, low active
-		clk_in			=> sdclk,   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		=> clk_fb,   -- feedback clock
-		clk0_0_out		=> CLK0_O,  -- System clock #0, dcm#0 output 0°
-		clk0_270_out	=> CLK270_O,  -- System clock #0, dcm#0 output 270°
-		clk1_0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		clk1_270_out	=> CLK270VAR_O,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		locked_out		=> locked,  -- DCM locked status
-		error_out		=> error
-	);
-
-	clk_fb	<= part_clk_p after 1 ns;
-	CLK_O	<= clk;
-	RST_O	<= not locked;
-	DAT_O	<= X"DEADBEEF" & sddat;
-	SEL_O	<= "0000" & sdsel;
-	
-	-- DDR SDRAM Controller Core
-	sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
-	GENERIC MAP
-	(
-		BL 				=> BURST_LEN,
-		f_sysclk	 	=> 100.000,
-		f_sdrclk	 	=> 133.333,
-		fifo_depth		=> 4
-	)
-	PORT MAP
-	(
-		RST_I				=> RST_O,
-		CLK_I				=> CLK_O,
-		SDRAM_CLK0_I		=> CLK0_O,
-		SDRAM_CLK270_I		=> CLK270_O,
-		SDRAM_CLK270VAR_I	=> CLK270VAR_O,
-		CYC_I				=> CYC_O,
-		STB_I				=> STB_O,
-		SEL_I				=> SEL_O,
-		WE_I				=> WE_O,
-		ACK_O				=> ACK_I,
-		SRDY_O				=> SRDY_I,
-		MRDY_I				=> MRDY_O,
-		ADDR_I				=> ADDR_O,
-		DAT_I				=> DAT_O,
-		DAT_O				=> DAT_I,
-
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map
-      (
-         dq    => std_logic_vector(part_data(15 downto 0)),
-         dqs   => std_logic_vector(part_dqs(1 downto 0)),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm(1 downto 0))
-	);
-
-   -- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_1 : entity work.mt46v16m16 
-      port map
-      (
-         dq    => std_logic_vector(part_data(31 downto 16)),
-         dqs   => std_logic_vector(part_dqs(3 downto 2)),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm(3 downto 2))
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-SDCLK_GEN: process
-	begin
-		wait for SDCLK_PERIOD/2;
-		sdclk <= not sdclk;
-	end process;
-
-read_register:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if dout_rst = '1' then
-				dout_cnt <= 0;
-			elsif ACK_I = '1' and WE_O = '0' then
-				dout_reg	<= DAT_I(31 downto 0);
-				dout_cnt 	<= dout_cnt + 1;
-			end if;
-		end if;
-	end process;
-		
-------------------------------------------------------------------------------------------
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		
-		wait until RST_O = '0';
-		-- 8 single cycles
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		sddat	<= X"1234_0000";
-		ADDR_O	<= X"0000_0000";
-		
-		for i in 0 to 8192 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			sddat	<= sddat + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-	
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		sdsel	<= "0011";
-		ADDR_O	<= X"0000_0080";
-		sddat	<= X"DEADBEEF";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0080";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-		for k in 0 to 3 loop
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-		for k in 0 to 3 loop
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"1111_0000";
-			ADDR_O	<= X"0000_0000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"2222_0000";
-			ADDR_O	<= X"0000_0400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"3333_0000";
-			ADDR_O	<= X"0000_0800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"4444_0000";
-			ADDR_O	<= X"0000_0C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"1111_0000";
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"2222_0000";
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"3333_0000";
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			sdsel	<= "1111";
-			sddat	<= X"4444_0000";
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				sddat	<= sddat + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		wait; 
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
deleted file mode 100644
index 9673d37..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+++ /dev/null
@@ -1,867 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-use work.fifo_ctrl_pkg.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-
-entity tb_sdram_ctrl_frontend_wb is
-end;
-
-architecture struct of tb_sdram_ctrl_frontend_wb is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-	constant SDCLK_PERIOD	: time := 8 ns;
-	constant BURST_LEN		: natural := 2;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '1';  
-	signal sdclk			: std_logic := '1';  
-	signal locked			: std_logic;  
-	signal error			: std_logic;  
-	signal clk_out			: std_logic;  
-	signal clk_fb			: std_logic;  
-	signal part_clk_p		: std_logic;  
-	signal part_clk_n		: std_logic;  
-	signal part_cke			: std_logic;  
-	signal part_cs_n		: std_logic;  
-	signal part_we_n		: std_logic;  
-	signal part_ras_n		: std_logic;  
-	signal part_cas_n		: std_logic;  
-	signal part_ba			: unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0');
-	signal part_dm			: unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0');
-	signal part_dqs			: unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0');
-	signal part_addr		: unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0');
-	signal part_data		: unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
-
-	signal CLK_O			: std_logic;
-	signal CLK0_O			: std_logic;
-	signal CLK270_O			: std_logic;
-	signal CLK270VAR_O		: std_logic;
-	signal RST_O			: std_logic;
-	signal CYC_O			: std_logic := '0';
-	signal STB_O			: std_logic := '0';
-	signal WE_O				: std_logic := '0';
-	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I			: std_logic;
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic;
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I			: unsigned(31 downto 0);
-	signal DAT_O			: unsigned(31 downto 0) := (others => '-');
-
-	signal dout_rst			: std_logic := '0';
-	signal dout_reg			: unsigned(31 downto 0);
-	signal dout_cnt			: natural range 0 to 255;
-
-	type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst);
-	signal sd_cmd : sd_cmd_t;
-	
-begin 
-   
-	process(part_cs_n, part_ras_n, part_cas_n, part_we_n)
-	variable cmd : unsigned (2 downto 0);
-
-	begin
-		cmd := part_ras_n & part_cas_n & part_we_n;
-		sd_cmd <= nop;
-		if part_cs_n = '0' then
-			case cmd is
-				when "000" =>
-					sd_cmd <= lmr;
-				when "001" =>
-					sd_cmd <= ar;
-				when "010" =>
-					sd_cmd <= pre;
-				when "011" =>
-					sd_cmd <= act;
-				when "100" =>
-					sd_cmd <= write;
-				when "101" =>
-					sd_cmd <= read;
-				when "110" =>
-					sd_cmd <= bst;
-				when "111" =>
-					sd_cmd <= nop;
-				
-				when others =>
-					sd_cmd <= nop;
-
-			end case;
-		end if;
-	end process;
-	
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		clk_in_freq			=> 100.0,
-		clk0_out_phaseshift	=> 0,
-		clk1_out_phaseshift	=> 0
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst				=> rst,   -- external async reset, low active
-		clk_in			=> sdclk,   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		=> clk_fb,   -- feedback clock
-		clk0_0_out		=> CLK0_O,  -- System clock #0, dcm#0 output 0°
-		clk0_270_out	=> CLK270_O,  -- System clock #0, dcm#0 output 270°
-		clk1_0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		clk1_270_out	=> CLK270VAR_O,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		locked_out		=> locked,  -- DCM locked status
-		error_out		=> error
-	);
-
-	clk_fb	<= part_clk_p after 1 ns;
-	RST_O	<= not locked;
-	CLK_O	<= clk;
-	
-	-- DDR SDRAM Controller Core
-	sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
-	GENERIC MAP
-	(
-		BL 				=> BURST_LEN,
-		f_sysclk		=> 100.0,
-		f_sdrclk		=> 100.0,
-		fifo_depth		=> 4
-	)
-	PORT MAP
-	(
-		RST_I				=> RST_O,
-		CLK_I				=> CLK_O,
-		SDRAM_CLK0_I		=> CLK0_O,
-		SDRAM_CLK270_I		=> CLK270_O,
-		SDRAM_CLK270VAR_I	=> CLK270VAR_O,
-		
-		CYC_I				=> CYC_O,
-		STB_I				=> STB_O,
-		SEL_I				=> SEL_O,
-		WE_I				=> WE_O,
-		ACK_O				=> ACK_I,
-		SRDY_O				=> SRDY_I,
-		MRDY_I				=> MRDY_O,
-		ADDR_I				=> ADDR_O,
-		DAT_I				=> DAT_O,
-		DAT_O				=> DAT_I,
-
-		-- SDRAM signals
-		sd_clk_p			=> part_clk_p,
-		sd_clk_n			=> part_clk_n,
-		sd_cke				=> part_cke,
-		sd_cs_n				=> part_cs_n,
-		sd_cas_n			=> part_cas_n,
-		sd_ras_n			=> part_ras_n,
-		sd_we_n				=> part_we_n,
-		sd_addr				=> part_addr,
-		sd_ba				=> part_ba,
-		sd_dm				=> part_dm,
-		sd_dqs				=> part_dqs,
-		sd_data				=> part_data
-		
-	);
-   
-   -- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map
-      (
-         dq    => std_logic_vector(part_data(15 downto 0)),
-         dqs   => std_logic_vector(part_dqs(1 downto 0)),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm(1 downto 0))
-	);
-
-   -- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_1 : entity work.mt46v16m16 
-      port map
-      (
-         dq    => std_logic_vector(part_data(31 downto 16)),
-         dqs   => std_logic_vector(part_dqs(3 downto 2)),
-         addr  => std_logic_vector(part_addr),
-         ba    => std_logic_vector(part_ba),
-         clk   => part_clk_p,
-         clk_n => part_clk_n,
-         cke   => part_cke,
-         cs_n  => part_cs_n,
-         ras_n => part_ras_n,
-         cas_n => part_cas_n,
-         we_n  => part_we_n,
-         dm    => std_logic_vector(part_dm(3 downto 2))
-	);
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-SDCLK_GEN: process
-	begin
-		wait for SDCLK_PERIOD/2;
-		sdclk <= not sdclk;
-	end process;
-
-read_register:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if dout_rst = '1' then
-				dout_cnt <= 0;
-			elsif ACK_I = '1' and WE_O = '0' then
-				dout_reg	<= DAT_I;
-				dout_cnt 	<= dout_cnt + 1;
-			end if;
-		end if;
-	end process;
-		
-------------------------------------------------------------------------------------------
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		
-		wait until RST_O = '0';
-		-- 8 single cycles
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		DAT_O	<= X"1234_0000";
-		ADDR_O	<= X"0000_0000";
-		
-		for i in 0 to 8192 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-	
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "0011";
-		ADDR_O	<= X"0000_0080";
-		DAT_O	<= X"DEADBEEF";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0080";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-		for k in 0 to 3 loop
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_0C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-		for k in 0 to 3 loop
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"1111_0000";
-			ADDR_O	<= X"0000_0000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"2222_0000";
-			ADDR_O	<= X"0000_0400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"3333_0000";
-			ADDR_O	<= X"0000_0800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"4444_0000";
-			ADDR_O	<= X"0000_0C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"1111_0000";
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"2222_0000";
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"3333_0000";
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '1';
-			SEL_O	<= "1111";
-			DAT_O	<= X"4444_0000";
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				DAT_O	<= DAT_O + 1;
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O);
-			CYC_O	<= '0';
-		
-		end loop;
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		for k in 0 to 3 loop
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1000";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1400";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1800";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-
-			------------------------------------------------------------
---			wait for 3*CLK_PERIOD;
-			------------------------------------------------------------
-
-			-- 8-word burst cycle
-			dout_rst	<= '1';
-			wait until rising_edge(CLK_O);
-			dout_rst	<= '0';
-
-			CYC_O	<= '1';
-			STB_O	<= '1';
-			WE_O	<= '0';
-			ADDR_O	<= X"0000_1C00";
-
-			for i in 0 to 7 loop
-				wait until rising_edge(CLK_O) and SRDY_I = '1';
-				ADDR_O	<= ADDR_O + 4;
-			end loop;
-
-			STB_O	<= '0';
-			wait until rising_edge(CLK_O) and dout_cnt = 7;
-			CYC_O	<= '0';
-		
-		end loop;
-
-		wait; 
-	
-	end process;
-	
-end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/todo.txt b/lib/SDRAM/ddr_sdr_v1_5/todo.txt
deleted file mode 100644
index 62fe90a..0000000
--- a/lib/SDRAM/ddr_sdr_v1_5/todo.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-2009-11-04
-- several async. resets recognized. Sync. resets better?
-
-2009-11-11
-- utag-stuff from ddr_phy to sdram_ctrl_top
-- connect ddr_phy on top level to sdram_ctrl_frontend*
-- u_data_req_r not nessecary (removed 2009-11-15)
diff --git a/lib/SSRAM/sim/ModelSim SE .lnk b/lib/SSRAM/sim/ModelSim SE .lnk
deleted file mode 100644
index 935209c..0000000
Binary files a/lib/SSRAM/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo
deleted file mode 100644
index 9aafbb0..0000000
--- a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit  -93 "../src/package_utility.vhd"
-vcom -explicit  -93 "../src/CY7C1354B.vhd"
-vcom -explicit  -93 "../src/ssram_frontend_wb.vhd"
-vcom -explicit  -93 "../src/tb_ssram_frontend_wb.vhd"
-
-vsim -t 1ps   -lib work tb_ssram_frontend_wb
-do {tb_ssram_frontend_wb.wdo}
-view wave
-view structure
-view signals
-run 6us
-			 
\ No newline at end of file
diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo
deleted file mode 100644
index 71718ed..0000000
--- a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo
+++ /dev/null
@@ -1,47 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz
-add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg
-add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt
-add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb
-add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {6300 ns}
diff --git a/lib/SSRAM/src/CY7C1354B.vhd b/lib/SSRAM/src/CY7C1354B.vhd
deleted file mode 100644
index d652656..0000000
--- a/lib/SSRAM/src/CY7C1354B.vhd
+++ /dev/null
@@ -1,388 +0,0 @@
------------------------------------------------------------------------------------------
---
---     File Name:  CY7C1354B.VHD
---       Version:  2.0
---          Date:  Nov 22nd, 2004
---         Model:  BUS Functional
---     
--- 
---        Author:  RKF 
---       Company:  Cypress Semiconductor
---         Model:  CY7C1354B (256k x 36)
---          Mode:  Pipelined
---
---   Description:  NoBL SRAM VHDL Model
---
---    Limitation:  None
---
---          Note:  - BSDL Model available separately
---                 - Set simulator resolution to "ps" timescale
---
---    Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
---                 WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
---                 IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
---                 A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
---
---                 Copyright (c) 2004 Cypress Semiconductor 
---                 All rights reserved
---
---     Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
---
---  Rev  Author          Date        Changes
---  ---  --------       -------     ----------  
---  2.0  RKF 		11/22/2004  - Second Release
---				    - Fully Tested with New Test Bench and Test Vectors	
------------------------------------------------------------------------------------------
-
-LIBRARY ieee,work;
-	USE ieee.std_logic_1164.all;
-	USE ieee.std_logic_unsigned.all;
-	Use IEEE.Std_Logic_Arith.all;
---	Use work.all;   
-	USE work.package_utility.all;   
-
-ENTITY cy7c1354 IS
-
-    GENERIC (
-
-        -- Constant parameters
-	addr_bits : INTEGER := 18;
-	data_bits : INTEGER := 32;
-	par_bits : INTEGER := 4;
-
-        -- Timing parameters for -5 (225 Mhz)
---         tCYC	: TIME    := 4.4 ns;
---         tCH	: TIME    :=  1.8 ns;
---         tCL	: TIME    :=  1.8 ns;
---         tCO	: TIME    :=  2.8 ns;
---         tAS	: TIME    :=  1.4 ns;
---         tCENS	: TIME    :=  1.4 ns;
---         tWES	: TIME    :=  1.4 ns;
---         tDS	: TIME    :=  1.4 ns;
---         tAH	: TIME    :=  0.4 ns;
---         tCENH	: TIME    :=  0.4 ns;
---         tWEH	: TIME    :=  0.4 ns;
---         tDH	: TIME    :=  0.4 ns
-
-
-     
-        -- Timing parameters for -6 (200 Mhz)
-        --tCYC	: TIME    := 5.0 ns;
-        --tCH	: TIME    :=  2.0 ns;
-        --tCL	: TIME    :=  2.0 ns;
-        --tCO	: TIME    :=  3.2 ns;
-        --tAS	: TIME    :=  1.5 ns;
-        --tCENS	: TIME    :=  1.5 ns;
-        --tWES	: TIME    :=  1.5 ns;
-        --tDS	: TIME    :=  1.5 ns;
-        --tAH	: TIME    :=  0.5 ns;
-        --tCENH	: TIME    :=  0.5 ns;
-        --tWEH	: TIME    :=  0.5 ns;
-        --tDH	: TIME    :=  0.5 ns
-         
-
-        -- Timing parameters for -7 (166 Mhz)
-        tCYC	: TIME    := 6.0 ns;
-        tCH	: TIME    :=  2.4 ns;
-        tCL	: TIME    :=  2.4 ns;
-        tCO	: TIME    :=  3.5 ns;
-        tAS	: TIME    :=  1.5 ns;
-        tCENS	: TIME    :=  1.5 ns;
-        tWES	: TIME    :=  1.5 ns;
-        tDS	: TIME    :=  1.5 ns;
-        tAH	: TIME    :=  0.5 ns;
-        tCENH	: TIME    :=  0.5 ns;
-        tWEH	: TIME    :=  0.5 ns;
-        tDH	: TIME    :=  0.5 ns
-
-       
-
-         );
-
-    -- Port Declarations
-    PORT (
-	Dq	: INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0);   	-- Data I/O
-	Dpq	: INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0);   	-- Data parity I/O
-	Addr	: IN	STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0);   	-- Address
-	Mode	: IN	STD_LOGIC	:= '1'; 			-- Burst Mode
-	Clk	: IN	STD_LOGIC;                                   -- Clk
-	CEN_n	: IN	STD_LOGIC;                                   -- CEN#
-	AdvLd_n	: IN	STD_LOGIC;                                   -- Adv/Ld#
-	Bwa_n	: IN	STD_LOGIC;                                   -- Bwa#
-	Bwb_n	: IN	STD_LOGIC;                                   -- BWb#
-	Bwc_n	: IN	STD_LOGIC;                                   -- Bwc#
-	Bwd_n	: IN	STD_LOGIC;                                   -- BWd#
-	Rw_n	: IN	STD_LOGIC;                                   -- RW#
-	Oe_n	: IN	STD_LOGIC;                                   -- OE#
-	Ce1_n	: IN	STD_LOGIC;                                   -- CE1#
-	Ce2	: IN	STD_LOGIC;                                   -- CE2
-	Ce3_n	: IN	STD_LOGIC;                                   -- CE3#
-	Zz	: IN	STD_LOGIC                                    -- Snooze Mode
-    );
-END cy7c1354;
-
-ARCHITECTURE behave OF cy7c1354 IS
-    SIGNAL ce : STD_LOGIC := '0';
-    SIGNAL doe : STD_LOGIC := '0';
-    SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
-    SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
-    SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
-
-BEGIN
-
-
-    ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
-
-    doe <= NOT(Oe_n) AND NOT(Zz);
-
-    -- Output Buffers
-    WITH doe SELECT
-        Dq <= TRANSPORT dout            AFTER (tCO) WHEN '1',
-                        (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-    
-    WITH doe SELECT
-        Dpq <= TRANSPORT dout_p            AFTER (tCO) WHEN '1',
-                        (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
-                           
- 
-    -- Check for Clock Timing Violation
-    clk_check : PROCESS
-        VARIABLE clk_high, clk_low : TIME := 0 ns;
-    BEGIN
-        WAIT ON Clk;
-            IF Clk = '1' AND NOW >= tCYC THEN
-                ASSERT (NOW - clk_low >= tCH)
-                    REPORT "Clk width low - tCH violation"
-                    SEVERITY ERROR;
-                ASSERT (NOW - clk_high >= tCYC)
-                    REPORT "Clk period high - tCYC violation"
-                    SEVERITY ERROR;
-                clk_high := NOW;
-            ELSIF Clk = '0' AND NOW /= 0 ns THEN
-                ASSERT (NOW - clk_high >= tCL)
-                    REPORT "Clk width high - tCL violation"
-                    SEVERITY ERROR;
-                ASSERT (NOW - clk_low >= tCYC)
-                    REPORT "Clk period low - tCYC violation"
-                    SEVERITY ERROR;
-                clk_low := NOW;
-            END IF;
-    END PROCESS;
-
-    -- Check for Setup Timing Violation
-    setup_check : PROCESS
-    BEGIN
-        WAIT ON Clk;
-        IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN
-           	ASSERT (Addr'LAST_EVENT >= tAS)
-           	    REPORT "Addr - tAS violation"
-           	    SEVERITY ERROR;
-            ASSERT (CEN_n'LAST_EVENT >= tCENS)
-                REPORT "CKE# - tCENS violation"
-                SEVERITY ERROR;
-            ASSERT (Ce1_n'LAST_EVENT >= tWES)
-                REPORT "CE1# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Ce2'LAST_EVENT >= tWES)
-                REPORT "CE2 - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Ce3_n'LAST_EVENT >= tWES)
-                REPORT "CE3# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (AdvLd_n'LAST_EVENT >= tWES)
-                REPORT "ADV/LD# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Rw_n'LAST_EVENT >= tWES)
-                REPORT "RW# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Bwa_n'LAST_EVENT >= tWES)
-                REPORT "BWa# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Bwb_n'LAST_EVENT >= tWES)
-                REPORT "BWb# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Bwc_n'LAST_EVENT >= tWES)
-                REPORT "BWc# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Bwd_n'LAST_EVENT >= tWES)
-                REPORT "BWd# - tWES violation"
-                SEVERITY ERROR;
-            ASSERT (Dq'LAST_EVENT >= tDS)
-                REPORT "Dq - tDS violation"
-                SEVERITY ERROR;
-        END IF;
-    END PROCESS;
-
-    -- Check for Hold Timing Violation
-    hold_check : PROCESS
-    BEGIN
-        WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
-        IF Clk'DELAYED(tAH) = '1' THEN
-            ASSERT (Addr'LAST_EVENT > tAH)
-                REPORT "Addr - tAH violation"
-                SEVERITY ERROR;
-        END IF;
-        IF Clk'DELAYED(tCENH) = '1' THEN
-            ASSERT (CEN_n'LAST_EVENT > tCENH)
-                REPORT "CKE# - tCENH violation"
-                SEVERITY ERROR;
-        END IF;
-        IF Clk'DELAYED(tDH) = '1' THEN
-            ASSERT (Dq'LAST_EVENT > tDH)
-                REPORT "Dq - tDH violation"
-                SEVERITY ERROR;
-        END IF;
-        IF Clk'DELAYED(tWEH) = '1' THEN
-            ASSERT (Ce1_n'LAST_EVENT > tWEH)
-                REPORT "CE1# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Ce2'LAST_EVENT > tWEH)
-                REPORT "CE2 - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Ce3_n'LAST_EVENT > tWEH)
-                REPORT "CE3 - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (AdvLd_n'LAST_EVENT > tWEH)
-                REPORT "ADV/LD# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Rw_n'LAST_EVENT > tWEH)
-                        REPORT "RW# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Bwa_n'LAST_EVENT > tWEH)
-                REPORT "BWa# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Bwb_n'LAST_EVENT > tWEH)
-                REPORT "BWb# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Bwc_n'LAST_EVENT > tWEH)
-                REPORT "BWc# - tWEH violation"
-                SEVERITY ERROR;
-            ASSERT (Bwd_n'LAST_EVENT > tWEH)
-                REPORT "BWd# - tWEH violation"
-                SEVERITY ERROR;
-        END IF;
-        
-    END PROCESS;
-
-   -- Main Program
-    main : PROCESS 
-
-    TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0);
-       
-        VARIABLE Addr_in 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
-        VARIABLE first_Addr 	: STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
-        VARIABLE Addr_read 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
-        VARIABLE Addr_write 	: STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
-        VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
-        VARIABLE bank0 		: memory_array;
-        VARIABLE bank1 		: memory_array;
-        VARIABLE bank2 		: memory_array;
-        VARIABLE bank3 		: memory_array;
-
-        VARIABLE ce_in 		: STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-        VARIABLE rw_in 		: STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
-        VARIABLE bwa_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
-        VARIABLE bwb_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
-        VARIABLE bwc_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
-        VARIABLE bwd_in 	: STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
-        VARIABLE bcnt 		: STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
-
-    BEGIN
-        WAIT ON Clk;
-        IF Clk'EVENT AND Clk = '1' THEN
-            IF CEN_n = '0' AND Zz = '0' THEN
-                -- Write Address Register
-                Addr_write := Addr_read;
-
-                -- Read Address Register
-                Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
-
-                -- Address Register
-                IF AdvLd_n = '0' and ce = '1' THEN
-                  Addr_in := Addr;
-                  first_Addr := Addr(1 DOWNTO 0);
-                  bcnt := Addr(1 DOWNTO 0);
-              END IF;
-
-
-                -- Burst Logic
-              IF Mode = '0' AND AdvLd_n = '1' THEN
-                  bcnt := bcnt + 1;
-              ELSIF Mode = '1' AND AdvLd_n = '1' THEN
-			IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
-                  		bcnt := bcnt + 1;
-			ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
-                  		bcnt := bcnt - 1;
-              		END IF;
-              END IF;
-				
-
-                  bAddr1 := bcnt (1);
-                  bAddr0 := bcnt (0);
-
-                -- Read Logic
-                ce_in (0) := ce_in (1);
-
-                IF AdvLd_n = '0' THEN
-                    ce_in (1) := ce;
-                END IF;
-
-                rw_in (0) := rw_in (1);
-                rw_in (1) := rw_in (2);
-
-                IF AdvLd_n = '0' THEN
-                    rw_in (2) := NOT(ce AND NOT(Rw_n));
-                END IF;
-
-                -- Write Registry and Data Coherency Control Logic
-                bwa_in (0) := bwa_in (1);
-                bwb_in (0) := bwb_in (1);
-                bwc_in (0) := bwc_in (1);
-                bwd_in (0) := bwd_in (1);
-                bwa_in (1) := bwa_in (2);
-                bwb_in (1) := bwb_in (2);
-                bwc_in (1) := bwc_in (2);
-                bwd_in (1) := bwd_in (2);
-                bwa_in (2) := Bwa_n;
-                bwb_in (2) := Bwb_n;
-                bwc_in (2) := Bwc_n;
-                bwd_in (2) := Bwd_n;
-
-                -- Write Data to Memory
-                IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
-                    bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO  0);
-                END IF;
-                IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
-                    bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO  (data_bits / 4));
-                END IF;
-                IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
-                    bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO  (data_bits / 2));
-                END IF;
-                IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
-                    bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO  (3 * (data_bits / 4)));
-                END IF;
-            END IF;
-
-		Addr_read_sig	<= Addr_read;
-
-            -- Read Data from Memory Array
-            IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
-                dout ((data_bits / 4) - 1 DOWNTO  0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
-                dout ((data_bits / 2 - 1) DOWNTO  (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
-                dout ((3 * (data_bits / 4)) - 1 DOWNTO  (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
-                dout (data_bits - 1 DOWNTO  (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO  0);
-                dout_p(0)	<= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
-                dout_p(1)	<= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
-                dout_p(2)	<= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
-                dout_p(3)	<= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4);
-            ELSE
-                dout <= (OTHERS => 'Z');
-                dout_p <= (OTHERS => 'Z');
-            END IF;
-       END IF;
-    END PROCESS;
-
-END behave;
-
-
-
diff --git a/lib/SSRAM/src/package_utility.vhd b/lib/SSRAM/src/package_utility.vhd
deleted file mode 100644
index 9fb543f..0000000
--- a/lib/SSRAM/src/package_utility.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
---****************************************************************
---**    MODEL   :     package_utility                           **
---**    COMPANY :     Cypress Semiconductor			**
---**    REVISION:     1.0 Created new package utility model     **
---**                                                            **
---****************************************************************
-Library ieee,work; 
-   Use ieee.std_logic_1164.all;
-   Use IEEE.Std_Logic_Arith.all;
-   Use IEEE.std_logic_TextIO.all;
-   --- Use work.package_timing.all;
-
-Library Std;
-   Use STD.TextIO.all;
-
-Package package_utility is
-
-FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR;
-FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER;
-
-End; -- package package_utility
-
-Package body package_utility is  
-
-
-------------------------------------------------------------------------------------------------
---Converts string into std_logic_vector 
-------------------------------------------------------------------------------------------------
-
-FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS
-	VARIABLE result : STD_LOGIC_VECTOR(S'RANGE);
-		BEGIN
-			FOR i	IN S'RANGE LOOP
-				IF 	S(i) = '0' THEN
-					result(i) := '0'; 
-				ELSIF S(i) = '1' THEN 
-					result(i) := '1';
-				ELSIF S(i) = 'X' THEN
-					result(i) := 'X';
-				ELSE
-					result(i) := 'Z';
-				END IF;
-			END LOOP;
-		RETURN result;
-END convert_string;
-
-------------------------------------------------------------------------------------------------
---Converts std_logic_vector into integer
-------------------------------------------------------------------------------------------------
-
-FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS
-		VARIABLE result : INTEGER := 0;
-		BEGIN
-			FOR i IN S'RANGE LOOP
-				IF S(i) = '1' THEN
-					result := result + (2**i);
-				ELSIF S(i) = '0' THEN
-					result := result;
-				ELSE
-					result := 0;
-				END IF;
-			END LOOP;
-			RETURN result;
-		END CONV_INTEGER1;	
-
-
-
-
-end package_utility;   
-
-
-
-
diff --git a/lib/SSRAM/src/ssram_frontend_wb.vhd b/lib/SSRAM/src/ssram_frontend_wb.vhd
deleted file mode 100644
index 056b328..0000000
--- a/lib/SSRAM/src/ssram_frontend_wb.vhd
+++ /dev/null
@@ -1,181 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-ENTITY ssram_frontend_wb IS
-	Generic
-	(
-		latency			: natural := 2;		-- clock cycles
-		addr_width		: natural := 20;
-		data_width		: natural := 32;
-		parity_width	: natural := 4
-	);
-	Port
-	(
-		-- J-Bus domain
-		CLK_I			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		WE_I			: in  STD_LOGIC;
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		
-		-- Sync SRAM domain
-		ssram_clk_o		: out std_logic;
-		ssram_clk_fb	: in  std_logic;
-		ssram_cke_n		: out std_logic;
-		ssram_ce_n		: out std_logic;
-		ssram_oe_n		: out std_logic;
-		ssram_we_n		: out std_logic;
-		ssram_adv		: out std_logic;
-		ssram_mode		: out std_logic;
-		ssram_zz		: out std_logic;
-		ssram_a			: out unsigned(addr_width-1 downto 0);
-		ssram_d			: inout unsigned(data_width-1 downto 0);
-		ssram_dp		: inout unsigned(parity_width-1 downto 0);
-		ssram_bw_n		: out unsigned(3 downto 0)
-	);
-END ssram_frontend_wb;
-
-ARCHITECTURE behavior OF ssram_frontend_wb IS
-
-	constant topad	: time := 3 ns;
-	subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0);
-	type data_pipe_t is array (latency downto 0) of ssram_d_t;
-
-	signal ssram_clk	: std_logic;
-	signal dcm_locked	: std_logic;
-	signal dcm_clk0		: std_logic;
-	signal dcm_clk1		: std_logic;
-	signal data_en		: std_logic;
-	signal drive		: std_logic;
-	signal vld_pipe		: unsigned(latency downto 0);
-	signal drive_pipe	: unsigned(latency downto 0);
-	signal data_pipe	: data_pipe_t;
-	signal ssram_dout	: ssram_d_t;
-	
-begin
-
-	SRDY_O							<= CYC_I and dcm_locked;
-	ACK_O							<= vld_pipe(vld_pipe'left);
-	DAT_O(data_width-1 downto 0)	<= ssram_d;
-
-	data_en							<= CYC_I and STB_I;
-	ssram_dout						<= "0000" & DAT_I(data_width-1 downto 0);
-	drive							<= drive_pipe(drive_pipe'left);
-	
-	ssram_clk_o						<= ssram_clk after topad;
-	ssram_cke_n						<= not dcm_locked after topad;
-	ssram_oe_n						<= not vld_pipe(vld_pipe'left-1) after topad;
-	
-inst_clock_out : ODDR
-	generic map
-	(
-		DDR_CLK_EDGE => "OPPOSITE_EDGE",	-- "OPPOSITE_EDGE" or "SAME_EDGE" 
-		INIT => '0',						-- Initial value for Q port ('1' or '0')
-		SRTYPE => "SYNC"					-- Reset Type ("ASYNC" or "SYNC")
-	) 										
-	port map (
-		Q	=> ssram_clk,	-- 1-bit DDR output
-		C	=> dcm_clk1,	-- 1-bit clock input
-		CE	=> '1',			-- 1-bit clock enable input
-		D1	=> '1',			-- 1-bit data input (positive edge)
-		D2	=> '0',			-- 1-bit data input (negative edge)
-		R	=> '0',			-- 1-bit reset input
-		S	=> '0' 			-- 1-bit set input
-	);
-
-ssram_bufg: bufg
-	port map
-	(
-		o  => dcm_clk1,  
-		i  => dcm_clk0
-	);
-
-inst_DCM_BASE_0 : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map (
-		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => open,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => dcm_locked,     -- DCM LOCK status output
-		CLKFB => ssram_clk_fb,       -- DCM clock feedback
-		CLKIN => CLK_I,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => RST_I            -- DCM asynchronous reset input
-	);
-
-
-data_valid_pipeline:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				vld_pipe	<= (others => '0');
-			else
-				vld_pipe	<= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I);
-			end if;
-		end if;
-	end process;
-
-data_out_pipeline:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				ssram_ce_n	<= '1' after topad;
-				ssram_we_n	<= '1' after topad;
-				ssram_adv	<= '0' after topad;
-				ssram_mode	<= '0' after topad;
-				ssram_zz	<= '1' after topad;
-				drive_pipe	<= (others => '0');
-			elsif dcm_locked = '1' then
-				ssram_ce_n	<= not data_en after topad;
-				ssram_we_n	<= not (WE_I and data_en) after topad;
-				ssram_adv	<= '0' after topad;
-				ssram_mode	<= '0' after topad;
-				ssram_zz	<= '0' after topad;
-				ssram_a		<= ADDR_I(addr_width-1 downto 0) after topad;
-				ssram_bw_n	<= not SEL_I after topad;		
-				drive_pipe	<= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I);
-				data_pipe	<= data_pipe(data_pipe'left-1 downto 0) & ssram_dout;
-			end if;	
-		end if;
-	end process;
-	
-	ssram_d		<= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad;
-	ssram_dp	<= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad;
-	
-end behavior;
diff --git a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd
deleted file mode 100644
index 86f1411..0000000
--- a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd
+++ /dev/null
@@ -1,457 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-USE work.package_utility.all;   
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-ENTITY tb_ssram_frontend_wb IS
-END tb_ssram_frontend_wb;
-
-ARCHITECTURE behavior OF tb_ssram_frontend_wb IS 
-
-	constant CLK_PERIOD : time := 10 ns;
-	signal CLK_O	: std_logic := '1';
-	signal RST_O	: std_logic := '1';
-	signal CYC_O	: std_logic := '0';
-	signal STB_O	: std_logic := '0';
-	signal WE_O		: std_logic := '0';
-	signal SEL_O	: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I	: std_logic;
-	signal MRDY_O	: std_logic := '1';
-	signal SRDY_I	: std_logic;
-	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I	: unsigned(31 downto 0);
-	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
-
-    SIGNAL ssram_d		: unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z');
-    SIGNAL ssram_dp		: unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z');
-    SIGNAL ssram_a		: unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0');
-    SIGNAL ssram_clk	: STD_LOGIC := '0';
-    SIGNAL ssram_cke_n	: STD_LOGIC;
-    SIGNAL ssram_adv	: STD_LOGIC;
-    SIGNAL ssram_mode	: STD_LOGIC;
-    SIGNAL ssram_bw_n	: unsigned(3 downto 0);
-    SIGNAL ssram_we_n	: STD_LOGIC;
-    SIGNAL ssram_oe_n	: STD_LOGIC;
-    SIGNAL ssram_ce_n	: STD_LOGIC;
-    SIGNAL ssram_zz		: STD_LOGIC;
-
-    SIGNAL ssram_clk_fb	: STD_LOGIC;
-
-	signal dout_rst		: std_logic := '0';
-	signal dout_reg		: unsigned(31 downto 0);
-	signal dout_cnt		: natural range 0 to 255;
-
-BEGIN
-
-	ssram_clk_fb	<= ssram_clk after 0.5 ns;
-
-inst_ssram_frontend_wb : entity work.ssram_frontend_wb
-	GENERIC MAP
-	(
-		addr_width		=> 20,
-		data_width		=> 32,
-		parity_width	=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		RST_I		=> RST_O,
-		CLK_I		=> CLK_O,
-		CYC_I		=> CYC_O,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_I,
-		SRDY_O		=> SRDY_I,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I,
-		
-		-- Sync SRAM domain
-		ssram_clk_o		=> ssram_clk,
-		ssram_clk_fb	=> ssram_clk_fb,
-		ssram_cke_n		=> ssram_cke_n,
-		ssram_ce_n		=> ssram_ce_n,
-		ssram_oe_n		=> ssram_oe_n,
-		ssram_we_n		=> ssram_we_n,
-		ssram_adv		=> ssram_adv,
-		ssram_mode		=> ssram_mode,
-		ssram_zz		=> ssram_zz,
-		ssram_a			=> ssram_a,
-		ssram_d			=> ssram_d,
-		ssram_dp		=> ssram_dp,
-		ssram_bw_n		=> ssram_bw_n
-	);
-	
-inst_ssram : entity work.cy7c1354
-    -- PORT MAP Declarations
-    PORT MAP 
-    (
-		Dq		=> STD_LOGIC_VECTOR(ssram_d),   	-- Data I/O
-		Dpq		=> STD_LOGIC_VECTOR(ssram_dp),   	-- Data I/O
-		Addr	=> STD_LOGIC_VECTOR(ssram_a(19 downto 2)),   	-- Address
-		Mode	=> ssram_mode, 	-- Burst Mode
-		Clk		=> ssram_clk,      -- Clk
-		CEN_n	=> ssram_cke_n,                                   -- CEN#
-		AdvLd_n	=> ssram_adv,                                   -- Adv/Ld#
-		Bwa_n	=> ssram_bw_n(0),                                   -- Bwa#
-		Bwb_n	=> ssram_bw_n(1),                                   -- BWb#
-		Bwc_n	=> ssram_bw_n(2),                                   -- Bwc#
-		Bwd_n	=> ssram_bw_n(3),                                   -- BWd#
-		Rw_n	=> ssram_we_n,                                   -- RW#
-		Oe_n	=> ssram_oe_n,                                   -- OE#
-		Ce1_n	=> ssram_ce_n,                                   -- CE1#
-		Ce2		=> '1',                                   -- CE2
-		Ce3_n	=> '0',                                   -- CE3#
-		Zz		=> ssram_zz
-    );
-
-read_register:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if dout_rst = '1' then
-				dout_cnt <= 0;
-			elsif ACK_I = '1' and WE_O = '0' then
-				dout_reg	<= DAT_I;
-				dout_cnt 	<= dout_cnt + 1;
-			end if;
-		end if;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 5*CLK_PERIOD;
-		RST_O <= '0';
-		
-		wait until rising_edge(CLK_O);
-		-- 8 single cycles
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		DAT_O	<= X"1234_0000";
-		ADDR_O	<= X"0000_0000";
-		
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-	
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "0011";
-		ADDR_O	<= X"0000_0010";
-		DAT_O	<= X"DEADBEEF";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0010";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 3*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 31 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-		
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "1111";
-		DAT_O	<= X"1111_0000";
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "1111";
-		DAT_O	<= X"2222_0000";
-		ADDR_O	<= X"0000_0400";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0400";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "1111";
-		DAT_O	<= X"3333_0000";
-		ADDR_O	<= X"0000_0800";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0800";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "1111";
-		DAT_O	<= X"4444_0000";
-		ADDR_O	<= X"0000_0C00";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			DAT_O	<= DAT_O + 1;
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0C00";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-		------------------------------------------------------------
-		wait for 10*CLK_PERIOD;
-		------------------------------------------------------------
-		
-		-- 8-word burst cycle
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		ADDR_O	<= X"0000_0400";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-
-		ADDR_O	<= X"0000_0800";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-
-		ADDR_O	<= X"0000_0C00";
-
-		for i in 0 to 7 loop
-			wait until rising_edge(CLK_O) and SRDY_I = '1';
-			ADDR_O	<= ADDR_O + 4;
-		end loop;
-
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and dout_cnt = 31;
-		CYC_O	<= '0';
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/VGA_ctrl/sim/ModelSim SE .lnk b/lib/VGA_ctrl/sim/ModelSim SE .lnk
deleted file mode 100644
index 0a32950..0000000
Binary files a/lib/VGA_ctrl/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
deleted file mode 100644
index 3108918..0000000
--- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
+++ /dev/null
@@ -1,26 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
-vcom -explicit  -93 "../src/vga_types.vhd"
-vcom -explicit  -93 "../src/char_gen.vhd"
-vcom -explicit  -93 "../src/vga_sync.vhd"
-vcom -explicit  -93 "../src/vga_timing.vhd"
-vcom -explicit  -93 "../src/vga_backend.vhd"
-vcom -explicit  -93 "../src/vga_frontend.vhd"
-vcom -explicit  -93 "../src/tb_vga_frontend.vhd"
-vsim -t 1ps   -lib work tb_vga_frontend
-view wave
-do {tb_vga_frontend.wdo}
-view structure
-view signals
-
-run 20ms
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend.wdo
deleted file mode 100644
index 227b8b3..0000000
--- a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo
+++ /dev/null
@@ -1,79 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_vga_frontend/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend/rst_o
-add wave -noupdate -divider Master
-add wave -noupdate -format Logic /tb_vga_frontend/cyc_o
-add wave -noupdate -format Logic /tb_vga_frontend/stb_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_o
-add wave -noupdate -format Literal /tb_vga_frontend/sel_o
-add wave -noupdate -format Logic /tb_vga_frontend/we_o
-add wave -noupdate -format Logic /tb_vga_frontend/ack_i
-add wave -noupdate -format Logic /tb_vga_frontend/mrdy_o
-add wave -noupdate -format Logic /tb_vga_frontend/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/mdat_o
-add wave -noupdate -divider Slave
-add wave -noupdate -format Logic /tb_vga_frontend/cyc_i
-add wave -noupdate -format Logic /tb_vga_frontend/stb_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_i
-add wave -noupdate -format Literal /tb_vga_frontend/sel_i
-add wave -noupdate -format Logic /tb_vga_frontend/we_i
-add wave -noupdate -format Logic /tb_vga_frontend/ack_o
-add wave -noupdate -format Logic /tb_vga_frontend/mrdy_i
-add wave -noupdate -format Logic /tb_vga_frontend/srdy_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/sdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/sdat_o
-add wave -noupdate -divider VGA
-add wave -noupdate -format Logic /tb_vga_frontend/vga_clk
-add wave -noupdate -format Logic /tb_vga_frontend/vga_blank_n
-add wave -noupdate -format Logic /tb_vga_frontend/vga_sync_n
-add wave -noupdate -format Logic /tb_vga_frontend/vga_hsync
-add wave -noupdate -format Logic /tb_vga_frontend/vga_vsync
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_red
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_green
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_blue
-add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/s
-add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/request_cnt
-add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/read_cnt
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/vga_master_en
-add wave -noupdate -divider FIFO
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_full
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_almost_empty
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_almost_full
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_color_re
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/fifo_color_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/inst_vga_frontend/fifo_color_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/inst_vga_frontend/fifo_color_in
-add wave -noupdate -divider Backend
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/ctrl_scan_en
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/sys_rst
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_vga_rdy
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_scan
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/scan_enable
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/is_scan
-add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_hpos
-add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_vpos
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/rst
-add wave -noupdate -format Logic /tb_vga_frontend/vga_en
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_draw
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_en
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/hready
-add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/vready
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {9915333000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {9915291469 ps} {9915942555 ps}
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
deleted file mode 100644
index 1d8256e..0000000
--- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
+++ /dev/null
@@ -1,28 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006
-##
-vlib work
-vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/fonts/char_rom_c64.vhd"
-vcom -explicit  -93 "../src/vga_types.vhd"
-vcom -explicit  -93 "../src/char_gen.vhd"
-vcom -explicit  -93 "../src/vga_sync.vhd"
-vcom -explicit  -93 "../src/vga_timing.vhd"
-vcom -explicit  -93 "../src/vga_backend.vhd"
-vcom -explicit  -93 "../src/vga_frontend64.vhd"
-vcom -explicit  -93 "../src/tb_vga_frontend64.vhd"
-vsim -t 1ps   -lib work tb_vga_frontend64
-view wave
-do {tb_vga_frontend64.wdo}
-view structure
-view signals
-
-run 2ms
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo
deleted file mode 100644
index ddbe21f..0000000
--- a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo
+++ /dev/null
@@ -1,240 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/rst_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/read_reg
-add wave -noupdate -divider Master
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cyc_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/srdy_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/stb_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/sdat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/sel_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/we_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/sdat_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/mrdy_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/ack_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_o
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider Slave
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/int_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cyc_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/stb_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/sdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/sdat_o
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/sel_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/we_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/ack_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/mrdy_i
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/srdy_o
-add wave -noupdate -format Logic /tb_vga_frontend64/rdy
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request
-add wave -noupdate -divider {Bus Output FIFO}
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_dout
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_re
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_we
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_full
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busout_fifo_rdy
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider {Bus Input FIFO}
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_dout
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_re
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_we
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_full
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_rdy
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/busin_fifo_dout_vld
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider VGA
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_dma_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_dma_en2
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_rdy
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue
-add wave -noupdate -format Literal -radix unsigned /tb_vga_frontend64/inst_vga_frontend64/request_cnt
-add wave -noupdate -format Literal -radix unsigned /tb_vga_frontend64/inst_vga_frontend64/read_cnt
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/bus_read_fin
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/vga_fb_back
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/vga_fb_front
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/host_fb_front
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/host_fb_back
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider FIFO
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_full
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_almost_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_almost_full
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_color_re
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/fifo_color_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/fifo_color_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/fifo_color_in
-add wave -noupdate -divider {Blitter REGS}
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_reset
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_fill_finish
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request_set
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_finish_strobe
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int_ack
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_complete_int_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int_ack
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_empty_int_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_dimx_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_cc
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_func
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_const_color_en
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_request_set
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_finish_strobe
-add wave -noupdate -divider {Blitter CMD}
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_re
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_we
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_bsy
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_avail
-add wave -noupdate -divider {Blitter SRC}
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/src_dbg
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_x
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_cnt_y
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_src_offset
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/mdat_i
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_cnt
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_full
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_src
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_src_0
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider BLIT-FIFO
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/fill_dbg
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_write_en
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_din
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_full
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_read_en
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_1
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty_read
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_vld
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_src_finish
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_fill_finish
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_x
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_cnt_y
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_offset
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_fill_addr
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider {Blitter DST}
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -expand /tb_vga_frontend64/inst_vga_frontend64/dst_dbg
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_cc
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_const_color_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/request_cnt_rst
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/request_en
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/request_cnt
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/read_cnt
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_cnt
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_chunk_full
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_x
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_cnt_y
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_offset
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_finish
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_addr_next
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/addr_o_blit_dst
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_nx
-add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blit_cmd_addr_dst
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blit_dst_be
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blitfifo_read_en
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_dout_1
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/blitfifo_empty
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/blit_dst_suspend
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s
-add wave -noupdate -divider RAM
-add wave -noupdate -format Literal /tb_vga_frontend64/state
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/ram_src
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_vga_frontend64/ram_dst
-add wave -noupdate -divider Backend
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/vga_scan_rdy
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos
-add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst
-add wave -noupdate -format Logic /tb_vga_frontend64/vga_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready
-add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready
-add wave -noupdate -format Logic /tb_vga_frontend64/clk_o
-add wave -noupdate -format Logic /tb_vga_frontend64/rst_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/read_reg
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {604745488 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 118
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {2100 us}
diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd
deleted file mode 100644
index f0cb6b8..0000000
--- a/lib/VGA_ctrl/src/char_gen.vhd
+++ /dev/null
@@ -1,547 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    char_gen - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.vga_types.all;
-
-entity char_gen is
-	Generic
-	(
-		tsvga					: vga_timespec_t := ts_vga_800_600_72;
-
-		-- User supplied parameters
-		CHARACTER_SCALE			: natural := 1;
-		CHAR_ROM_SIZE_X			: natural := 8;		-- Pixels
-		CHAR_ROM_SIZE_Y			: natural := 16;	-- Pixels
-		CHAR_ROM_DEPTH			: natural := 256;	-- Chars
-		MAX_CHAR_PER_LINE		: natural := 32;	-- Chars
-		MAX_LINE_PER_FRAME		: natural := 16;	-- Chars
-		CHAR_SPACING_X			: natural := 0; 	-- Pixels
-		CHAR_SPACING_Y			: natural := 0;		-- Pixels
-		SCREEN_OFFSET_X			: natural := 16;	-- Pixels
-		SCREEN_OFFSET_Y			: natural := 16		-- Pixels
-	);
-	Port
-	(
-		-- System signals
-		rst					: in std_logic;
-		vga_clk				: in std_logic;
-		sys_clk				: in std_logic;
-		ce					: in std_logic;
-		frame_pulse			: in std_logic;
-
-		
-		-- Host Signals
-		clr_screen			: in std_logic;
-		clr_line			: in std_logic;
-		din					: in unsigned(7 downto 0);
-		dout				: out unsigned(7 downto 0);
-		ascii_we			: in std_logic;
-		posy_we				: in std_logic;
-		posx_we				: in std_logic;
-		ready				: out std_logic;
-		
-		-- Control signals
-		scan_pos_x_in		: in natural range 0 to tsvga.ts_h.ncyc_scan-1;
-		scan_pos_y_in		: in natural range 0 to tsvga.ts_v.ncyc_scan-1;
-		
-		-- Status signals
-		csr_pos_x_out		: out natural range 0 to MAX_CHAR_PER_LINE-1;
-		csr_pos_y_out		: out natural range 0 to MAX_LINE_PER_FRAME-1;
-
-		-- Output 
-		char_draw_en		: out std_logic
-		
-	);
-end char_gen;
-
-architecture Behavioral of char_gen is
-
-	constant A_RAM_ADDR_WIDTH 		: integer := 12;
-	constant A_RAM_DATA_WIDTH 		: integer := 8;
-
-	type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
-
-	
-
-	function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is
-	variable result : offset_rom_t;
-
-	variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0');
-	begin
-		for i in 0 to num_lines-1 loop
-			result(i) := offset;
-			offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1);
-		end loop;
-		return result;
-	end gen_offset_rom;
-	
-	constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME);
-		
-	-- Calculated parameters
-	type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen);
-	signal s, sn : cg_state_t;
-	
-	constant CELL_SIZE_X			: natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE;
-	constant CELL_SIZE_Y			: natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE;
-	constant CHAR_SIZE_X			: natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE;
-	constant CHAR_SIZE_Y			: natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE;
-	
-	signal line_offset				: natural range 0 to MAX_LINE_PER_FRAME-1;
-	signal cell_x_cnt				: natural range 0 to MAX_CHAR_PER_LINE-1;
-	signal cell_y_cnt				: natural range 0 to MAX_LINE_PER_FRAME-1;
-	signal char_x_cnt				: natural range 0 to CELL_SIZE_X-1;
-	signal char_y_cnt				: natural range 0 to CELL_SIZE_Y-1;
-	signal char_rom_row				: unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0);
-	signal char_rom_addr			: unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0);
-	signal char_rom_data			: unsigned(CHAR_ROM_SIZE_X-1 downto 0);
-	signal char_reg					: unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0);
-	
-	signal a_addr_rd				: unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
-	signal a_addr_wr				: unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
-	signal a_data_rd				: unsigned(A_RAM_DATA_WIDTH-1 downto 0);
-	signal a_data_wr				: unsigned(A_RAM_DATA_WIDTH-1 downto 0);
-	signal a_ram_we					: std_logic;
-	signal a_cnt					: natural range 0 to 2**A_RAM_ADDR_WIDTH-1;
-	signal a_cnt_rst				: std_logic;
-	signal a_cnt_en					: std_logic;
-	signal csr_posx_reg				: natural range 0 to MAX_CHAR_PER_LINE-1;
-	signal csr_posy_reg				: natural range 0 to MAX_LINE_PER_FRAME-1;
-	signal a_data_reg				: unsigned(A_RAM_DATA_WIDTH-1 downto 0);
-	signal a_data_we				: std_logic;
-	signal csr_posx_overflow		: std_logic;
-	signal csr_posx_cnt_din			: natural range 0 to MAX_CHAR_PER_LINE-1;
-	signal csr_posx_cnt_set			: std_logic;
-	signal csr_posx_cnt_en			: std_logic;
-	signal csr_posy_overflow		: std_logic;
-	signal csr_posy_cnt_din			: natural range 0 to MAX_LINE_PER_FRAME-1;
-	signal csr_posy_cnt_set			: std_logic;
-	signal csr_posy_cnt_en			: std_logic;
-
-	signal line_addr				: unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
-	signal char_addr				: unsigned(A_RAM_ADDR_WIDTH-1 downto 0);
-	
-	-- Visible Cursor
-	constant CURSOR_BLINK_INTERVAL	: natural := tsvga.nfps/2;
-
-	type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0);
-	constant cursor_rom				: cursor_rom_t :=
-	(
-		-- Cursor off
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"00000000",
-		"11111111",
-		"11111111",
-		"11111111",
-		
-		-- Cursor on
-		"00000000",
-		"00000000",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"11111111",
-		"00000000",
-		"00000000",
-		"00000000"
-
-	);
-	signal cursor_rom_addr			: unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0);
-	signal cursor_rom_data			: unsigned(CHAR_ROM_SIZE_X-1 downto 0);
-	signal cursor_visible			: std_logic;
-	signal cursor_cnt				: natural range 0 to CURSOR_BLINK_INTERVAL-1;
-	signal csr_posx_synced			: natural range 0 to MAX_CHAR_PER_LINE-1;
-	signal csr_posy_synced			: natural range 0 to MAX_LINE_PER_FRAME-1;
-		
-	-- Scrolling
-	signal scroll_offset			: natural range 0 to MAX_LINE_PER_FRAME-1;
-	signal scroll_active			: std_logic;
-
-
-begin
-
-	a_addr_rd 		<= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset);
-	line_addr		<= offset_rom(csr_posy_reg);
-	char_addr		<= to_unsigned(csr_posx_reg, char_addr'length);
-	char_rom_addr	<= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
-	cursor_rom_addr	<= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1));
-	csr_pos_x_out	<= csr_posx_reg;
-	csr_pos_y_out	<= csr_posy_reg;
-	
-	inst_char_rom : entity work.char_rom
-	PORT MAP
-	(
-	    CLK         => vga_clk,
-	    ADDR        => char_rom_addr,
-	    DATA        => char_rom_data
-    );
-
-	inst_ascii_ram: entity work.dpram_1w1r2c_ro
-	GENERIC MAP (
-		addr_width	=> A_RAM_ADDR_WIDTH,
-		data_width	=> A_RAM_DATA_WIDTH
-	)
-	PORT MAP(
-		clk_a		=> sys_clk,
-		clk_b		=> vga_clk,
-		en_a		=> '1',
-		en_b		=> '1',
-		we_a		=> a_ram_we,
-		addr_a		=> a_addr_wr,
-		addr_b		=> a_addr_rd,
-		din_a		=> a_data_wr,
-		dout_b		=> a_data_rd
-	);
-
-	---------------------------------------------------------------------------------------------
-	--- ASCII RAM control
-	---------------------------------------------------------------------------------------------
-	asci_ram_fsm: 
-	process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr)
-	begin
-		sn			<= s;
-		a_cnt_rst	<= '0';
-		a_cnt_en	<= '0';
-		a_ram_we 	<= '0';
-		a_data_wr 	<= a_data_reg;
-		a_addr_wr	<= char_addr + line_addr;
-		ready 		<= '0';
-		
-		case s is
-		
-		when cg_init =>
-			sn <= cg_clr_screen;
-			a_cnt_rst <= '1';
-		when cg_ready =>
-			ready		<= '1';
-			a_ram_we	<= a_data_we;
-			if clr_screen = '1' then
-				a_cnt_rst <= '1';
-				sn <= cg_clr_screen;
-			elsif clr_line = '1' then
-				a_cnt_rst <= '1';
-				sn <= cg_clr_line;
-			end if;	
-		when cg_clr_line =>
-			a_ram_we <= '1';
-			a_cnt_en <= '1';
-			a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
-			a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH);
-			if a_cnt = MAX_CHAR_PER_LINE-1 then
-				sn <= cg_ready;
-			end if;	
-		when cg_clr_screen =>
-			a_ram_we <= '1';
-			a_cnt_en <= '1';
-			a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH);
-			a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH);
-			if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then
-				sn <= cg_ready;
-			end if;	
-				
-		when others =>
-			sn <= cg_ready;
-		
-		end case;
-	end process;
-		
-	asci_ram_fsm_next: process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			if rst = '1' then
-				s <= cg_init;
-			else	
-				s <= sn;
-			end if;	
-		end if;	
-	end process;
-
-	---------------------------------------------------------------------------------------------
-	asci_ram_cnt: process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			if a_cnt_rst = '1' then
-				a_cnt <= 0;
-			elsif a_cnt_en = '1' then
-				if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then
-					a_cnt <= a_cnt + 1;
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
-	---------------------------------------------------------------------------------------------
-	asci_addr_reg: process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			a_data_we <= '0';
-			csr_posx_cnt_en <= '0';
-			csr_posx_cnt_set <= '0';
-			csr_posy_cnt_en <= '0';
-			csr_posy_cnt_set <= '0';
-			if rst = '1' then
-				a_data_reg <= (others => '0');
-			elsif posy_we = '1' then
-				csr_posy_cnt_din <= to_integer(din);
-				csr_posy_cnt_set <= '1';
-			elsif posx_we = '1' then
-				csr_posx_cnt_din <= to_integer(din);
-				csr_posx_cnt_set <= '1';
-			elsif ascii_we = '1' then
-				dout <= din;	-- written char is simply echoed back to dout
-				if din < X"20" then
-					if din = X"0D" then
-						csr_posx_cnt_din <= 0;
-						csr_posx_cnt_set <= '1';
-					elsif din = X"0A" then	
-						csr_posy_cnt_en <= '1';
-					end if;	
-				else
-					a_data_reg <= din - X"20";
-					a_data_we <= '1';
-					csr_posx_cnt_en <= '1';
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
-	asci_csr_posx_counter:
-	process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			csr_posx_overflow <= '0';
-			if rst = '1' then
-				csr_posx_reg <= 0;
-			elsif csr_posx_cnt_set = '1' then
-				csr_posx_reg <= csr_posx_cnt_din;
-			elsif csr_posx_cnt_en = '1' then	
-				if csr_posx_reg < MAX_CHAR_PER_LINE-1 then
-					csr_posx_reg <= csr_posx_reg + 1;
-				else	
-					csr_posx_reg <= 0;
-					csr_posx_overflow <= '1';
-				end if;	
-			end if;
-		end if;
-	end process;
-	
-	asci_csr_posy_counter:
-	process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			csr_posy_overflow <= '0';
-			if rst = '1' then
-				csr_posy_reg <= 0;
-			elsif csr_posy_cnt_set = '1' then
-				csr_posy_reg <= csr_posy_cnt_din;
-			elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then	
-				if csr_posy_reg < MAX_LINE_PER_FRAME-1 then
-					csr_posy_reg <= csr_posy_reg + 1;
-				else	
-					csr_posy_reg <= 0;
-					csr_posy_overflow <= '1';
-				end if;	
-			end if;
-		end if;
-	end process;
-	
-	scroll_gen: process (sys_clk)
-	begin
-		if rising_edge(sys_clk) then
-			if rst = '1' or clr_screen = '1' then
-				scroll_offset <= 0;
-				scroll_active <= '0';
-			elsif csr_posy_cnt_set = '1' then
-				scroll_active <= '0';
-			elsif csr_posy_overflow = '1' then
-				scroll_active <= '1';
-				scroll_offset <= 1;
-			end if;
-			if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then
-				scroll_offset <= scroll_offset + 1;
-			end if;	
-		end if;	
-	end process;
-
-	---------------------------------------------------------------------------------------------
-	--- Cursor generator
-	---------------------------------------------------------------------------------------------
-	proc_sync_csr_posx:
-	process(vga_clk)
-	variable p1, p2	: natural range 0 to MAX_CHAR_PER_LINE-1;
-	begin
-		if rising_edge(vga_clk) then
-			csr_posx_synced <= p2;
-			p2 := p1;
-			p1 := csr_posx_reg;
-		end if;
-	end process;
-
-	proc_sync_csr_posy:
-	process(vga_clk)
-	variable p1, p2	: natural range 0 to MAX_LINE_PER_FRAME-1;
-	begin
-		if rising_edge(vga_clk) then
-			csr_posy_synced <= p2;
-			p2 := p1;
-			p1 := csr_posy_reg;
-		end if;
-	end process;
-
-	csr_blink_cnt: process (rst, vga_clk)
-	begin
-		if rst = '1' then
-			cursor_cnt <= 0;
-			cursor_visible <= '0';
-		elsif rising_edge(vga_clk) then
-			if frame_pulse = '1' then
-				if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then
-					cursor_cnt <= cursor_cnt + 1;
-				else
-					cursor_cnt <= 0;
-					cursor_visible <= not cursor_visible;
-				end if;
-			end if;	
-		end if;	
-	end process;
-
-	cursor_rom_read: process (vga_clk)
-	begin
-		if rising_edge(vga_clk) then
-			cursor_rom_data <= (others => '0');
-			if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then
-				cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr));
-			end if;	
-		end if;
-	end process;
-		
-	---------------------------------------------------------------------------------------------
-	--- Character generator
-	---------------------------------------------------------------------------------------------
-	char_rom_ctrl: process (vga_clk)
-	begin
-		if rising_edge(vga_clk) then
-			char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length);
-		end if;	
-	end process;
-
-	---------------------------------------------------------------------------------------------
-	char_reg_ctrl: process (vga_clk)
-	begin
-		if rising_edge(vga_clk) and ce = '1' then
-			if char_x_cnt = 2 then	-- +2 delay for ASCII-RAM access and CHAR-ROM access
-				for i in 0 to CHAR_ROM_SIZE_X-1 loop
-					for j in 0 to CHARACTER_SCALE-1 loop
-						char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i);
-					end loop;
-				end loop;	
-			else
-				char_reg <= char_reg(char_reg'left-1 downto 0) & '0';
-			end if;	
-		end if;
-	end process;
-	
-	---------------------------------------------------------------------------------------------
-	cg_ctrl: process (rst, vga_clk)
-	variable enable_x : std_logic;
-	variable enable_y : std_logic;
-	variable char_en : std_logic;
-	variable char_en2 : std_logic;
-	begin
-		
-		if (rst = '1') then
-			enable_x		:= '0';
-			enable_y		:= '0';
-			line_offset		<= 0;
-			cell_x_cnt		<= 0;
-			cell_y_cnt		<= 0;
-			char_x_cnt		<= 0;
-			char_y_cnt		<= 0;
-			char_en			:= '0';
-		elsif rising_edge(vga_clk) and ce = '1' then
-			char_draw_en	<= char_en2 and char_reg(char_reg'left);
-			char_en2		:= char_en;
-			char_en			:= '0';
-			if scan_pos_y_in = SCREEN_OFFSET_Y then
-				enable_y 	:= '1';
-				cell_y_cnt	<= 0;
-				char_x_cnt	<= 0;
-				line_offset	<= scroll_offset;
-			end if;	
-			if scan_pos_x_in = SCREEN_OFFSET_X and enable_y = '1' then
-				enable_x 	:= '1';
-				cell_x_cnt	<= 0;
-				char_x_cnt	<= 0;
-			elsif enable_x = '1' and enable_y = '1' then
-				if char_x_cnt < CELL_SIZE_X-1 then
-					char_x_cnt <= char_x_cnt + 1;
-				else	
-					char_x_cnt		<= 0;
-					if cell_x_cnt < MAX_CHAR_PER_LINE-1 then
-						cell_x_cnt <= cell_x_cnt + 1;
-					else	
-						enable_x	:= '0';
-						if char_y_cnt < CELL_SIZE_Y-1 then
-							char_y_cnt <= char_y_cnt + 1;
-						else
-							char_y_cnt		<= 0;
-							if cell_y_cnt < MAX_LINE_PER_FRAME-1 then
-								cell_y_cnt <= cell_y_cnt + 1;
-							else
-								enable_y	:= '0';
-							end if;	
-							if line_offset < MAX_LINE_PER_FRAME-1 then
-								line_offset <= line_offset + 1;
-							else
-								line_offset	<= 0;
-							end if;	
-						end if;	
-					end if;	
-				end if;	
-				if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then
-					char_en :=  '1';
-				end if;
-			end if;	
-		end if;
-	end process;
-
-	---------------------------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd
deleted file mode 100644
index 0a08d0c..0000000
--- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd
+++ /dev/null
@@ -1,106 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    vga_ctrl_core - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-library work;
-use work.utils_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clkgen is
-	Generic
-	(
-		clk_in_freq			: real	:= 100.0;
-		clk_out_freq		: real	:= 100.0
-	);
-	Port
-	(
-		rst			: in std_logic;
-		clk_in		: in std_logic;
-		clk_out		: out std_logic;
-		locked		: out std_logic
-	);
-end clkgen;
-
-architecture tech of clkgen is
-
-	signal dcm_clk0               : std_logic;
-	signal dcm_clk_fb             : std_logic;
-	signal clk_out0	              : std_logic;
-
-	begin
-	
-	-- Compnent instantiation
-	DCM_VGA_CLK_inst : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, clk_out_freq),   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, clk_out_freq), -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-											 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map
-	(
-		CLK0 => dcm_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => open,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => clk_out0,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => locked,     -- DCM LOCK status output
-		CLKFB => dcm_clk_fb,       -- DCM clock feedback
-		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => rst            -- DCM asynchronous reset input
-	);
-
-	BUFG_dcm_clk_fb : BUFG
-	port map
-	(
-		O => dcm_clk_fb,     -- Clock buffer output
-		I => dcm_clk0        -- Clock buffer input
-	);
-
-	BUFG_clk_out : BUFG
-	port map
-	(
-		O => clk_out,     -- Clock buffer output
-		I => clk_out0     -- Clock buffer input
-	);
-
-end tech;
diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff
deleted file mode 100644
index a1d2353..0000000
Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff and /dev/null differ
diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff
deleted file mode 100644
index b5c16cc..0000000
Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff and /dev/null differ
diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff
deleted file mode 100644
index 158e99f..0000000
Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff and /dev/null differ
diff --git a/lib/VGA_ctrl/src/fonts/System_16x16.bff b/lib/VGA_ctrl/src/fonts/System_16x16.bff
deleted file mode 100644
index 4ca2523..0000000
Binary files a/lib/VGA_ctrl/src/fonts/System_16x16.bff and /dev/null differ
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd
deleted file mode 100644
index 5a544d0..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd
+++ /dev/null
@@ -1,540 +0,0 @@
--- generated with romgen v3.0 by MikeJ
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-  port (
-    CLK         : in    std_logic;
-    ADDR        : in    unsigned(11 downto 0);
-    DATA        : out   unsigned(7 downto 0)
-    );
-end;
-
-architecture RTL of char_rom is
-
-
-  type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000
-    x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008
-    x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010
-    x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018
-    x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020
-    x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
-    x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030
-    x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038
-    x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040
-    x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
-    x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050
-    x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058
-    x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
-    x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068
-    x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070
-    x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
-    x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080
-    x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088
-    x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090
-    x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098
-    x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
-    x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8
-    x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
-    x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8
-    x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0
-    x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
-    x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0
-    x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
-    x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0
-    x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
-    x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
-    x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
-    x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108
-    x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110
-    x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118
-    x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120
-    x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128
-    x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
-    x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138
-    x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
-    x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
-    x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150
-    x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
-    x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
-    x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
-    x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180
-    x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
-    x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190
-    x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
-    x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0
-    x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
-    x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
-    x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8
-    x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
-    x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8
-    x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
-    x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
-    x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
-    x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
-    x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
-    x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8
-    x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
-    x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208
-    x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210
-    x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218
-    x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220
-    x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228
-    x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230
-    x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238
-    x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240
-    x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248
-    x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250
-    x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260
-    x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268
-    x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270
-    x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278
-    x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280
-    x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
-    x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290
-    x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298
-    x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0
-    x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8
-    x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0
-    x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8
-    x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0
-    x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8
-    x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0
-    x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8
-    x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0
-    x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8
-    x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0
-    x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
-    x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
-    x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
-    x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328
-    x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338
-    x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340
-    x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
-    x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358
-    x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
-    x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368
-    x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370
-    x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
-    x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380
-    x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388
-    x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390
-    x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
-    x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
-    x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
-    x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
-    x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
-    x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8
-    x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
-    x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
-    x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400
-    x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408
-    x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410
-    x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418
-    x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420
-    x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
-    x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
-    x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438
-    x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440
-    x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448
-    x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450
-    x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458
-    x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
-    x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468
-    x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470
-    x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478
-    x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480
-    x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488
-    x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490
-    x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498
-    x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
-    x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8
-    x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0
-    x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8
-    x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0
-    x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
-    x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0
-    x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
-    x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0
-    x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
-    x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0
-    x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
-    x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508
-    x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510
-    x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518
-    x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520
-    x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528
-    x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530
-    x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538
-    x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540
-    x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548
-    x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550
-    x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560
-    x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
-    x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578
-    x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580
-    x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588
-    x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590
-    x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598
-    x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0
-    x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8
-    x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0
-    x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
-    x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0
-    x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8
-    x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0
-    x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8
-    x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
-    x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8
-    x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
-    x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8
-    x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600
-    x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608
-    x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610
-    x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618
-    x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620
-    x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
-    x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630
-    x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638
-    x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640
-    x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648
-    x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650
-    x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660
-    x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668
-    x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670
-    x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678
-    x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680
-    x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690
-    x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698
-    x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0
-    x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8
-    x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0
-    x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8
-    x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0
-    x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8
-    x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0
-    x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8
-    x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0
-    x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8
-    x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0
-    x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
-    x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
-    x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
-    x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728
-    x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738
-    x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740
-    x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
-    x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758
-    x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
-    x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768
-    x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
-    x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780
-    x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788
-    x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790
-    x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
-    x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
-    x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0
-    x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
-    x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
-    x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8
-    x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
-    x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8
-    x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800
-    x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808
-    x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810
-    x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818
-    x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820
-    x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828
-    x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830
-    x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838
-    x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840
-    x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848
-    x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850
-    x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858
-    x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860
-    x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868
-    x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870
-    x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878
-    x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880
-    x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888
-    x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890
-    x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898
-    x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0
-    x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8
-    x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0
-    x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8
-    x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0
-    x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8
-    x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0
-    x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8
-    x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0
-    x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8
-    x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0
-    x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
-    x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908
-    x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910
-    x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918
-    x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920
-    x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928
-    x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930
-    x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938
-    x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940
-    x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948
-    x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950
-    x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960
-    x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970
-    x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978
-    x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980
-    x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988
-    x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990
-    x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998
-    x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0
-    x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8
-    x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0
-    x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8
-    x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0
-    x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8
-    x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0
-    x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8
-    x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0
-    x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8
-    x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0
-    x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8
-    x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00
-    x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08
-    x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10
-    x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18
-    x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20
-    x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28
-    x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30
-    x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38
-    x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40
-    x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48
-    x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50
-    x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58
-    x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60
-    x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68
-    x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70
-    x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78
-    x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80
-    x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88
-    x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90
-    x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98
-    x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0
-    x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8
-    x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0
-    x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8
-    x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0
-    x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8
-    x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0
-    x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8
-    x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0
-    x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8
-    x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0
-    x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
-    x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08
-    x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10
-    x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28
-    x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38
-    x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40
-    x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50
-    x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58
-    x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60
-    x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68
-    x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78
-    x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80
-    x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88
-    x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90
-    x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0
-    x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0
-    x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
-    x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
-    x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8
-    x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0
-    x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8
-    x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0
-    x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8
-    x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0
-    x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8
-    x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00
-    x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08
-    x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10
-    x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18
-    x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20
-    x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28
-    x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30
-    x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38
-    x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40
-    x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48
-    x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50
-    x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58
-    x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60
-    x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68
-    x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70
-    x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78
-    x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80
-    x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88
-    x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90
-    x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98
-    x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0
-    x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8
-    x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0
-    x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8
-    x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0
-    x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8
-    x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0
-    x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8
-    x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0
-    x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8
-    x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0
-    x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00
-    x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08
-    x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10
-    x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18
-    x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20
-    x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28
-    x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30
-    x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38
-    x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40
-    x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48
-    x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50
-    x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60
-    x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70
-    x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78
-    x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80
-    x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88
-    x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90
-    x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98
-    x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0
-    x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8
-    x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0
-    x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8
-    x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0
-    x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8
-    x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0
-    x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8
-    x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0
-    x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8
-    x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0
-    x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8
-    x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00
-    x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08
-    x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10
-    x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18
-    x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20
-    x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28
-    x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30
-    x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38
-    x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40
-    x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48
-    x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50
-    x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58
-    x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60
-    x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68
-    x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70
-    x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78
-    x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80
-    x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88
-    x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90
-    x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98
-    x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0
-    x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8
-    x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0
-    x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8
-    x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0
-    x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8
-    x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0
-    x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8
-    x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0
-    x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8
-    x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0
-    x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00
-    x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08
-    x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10
-    x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28
-    x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38
-    x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40
-    x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50
-    x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58
-    x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60
-    x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68
-    x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78
-    x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80
-    x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88
-    x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90
-    x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0
-    x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8
-    x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8
-    x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0
-    x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8
-    x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0
-    x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8
-    x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0
-    x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-     DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd
deleted file mode 100644
index c52e7f7..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd
+++ /dev/null
@@ -1,539 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-  port (
-    CLK         : in    std_logic;
-    ADDR        : in    unsigned(11 downto 0);
-    DATA        : out   unsigned(7 downto 0)
-    );
-end;
-
-architecture RTL of char_rom is
-
-
-  type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000
-    x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008
-    x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010
-    x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018
-    x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020
-    x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028
-    x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030
-    x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038
-    x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040
-    x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048
-    x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050
-    x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058
-    x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060
-    x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068
-    x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070
-    x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078
-    x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080
-    x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088
-    x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090
-    x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098
-    x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0
-    x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8
-    x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0
-    x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8
-    x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0
-    x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8
-    x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0
-    x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8
-    x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0
-    x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8
-    x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0
-    x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
-    x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108
-    x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110
-    x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118
-    x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120
-    x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128
-    x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130
-    x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138
-    x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140
-    x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148
-    x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150
-    x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158
-    x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160
-    x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
-    x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178
-    x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180
-    x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188
-    x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190
-    x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198
-    x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0
-    x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8
-    x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0
-    x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8
-    x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0
-    x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8
-    x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0
-    x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8
-    x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
-    x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8
-    x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
-    x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8
-    x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200
-    x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208
-    x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210
-    x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218
-    x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220
-    x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228
-    x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230
-    x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238
-    x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240
-    x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248
-    x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250
-    x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258
-    x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260
-    x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268
-    x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270
-    x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278
-    x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280
-    x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288
-    x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290
-    x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298
-    x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0
-    x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8
-    x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0
-    x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8
-    x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0
-    x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8
-    x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0
-    x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8
-    x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0
-    x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8
-    x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0
-    x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
-    x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308
-    x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310
-    x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320
-    x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328
-    x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330
-    x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338
-    x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340
-    x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350
-    x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358
-    x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360
-    x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368
-    x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370
-    x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378
-    x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380
-    x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388
-    x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390
-    x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0
-    x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0
-    x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8
-    x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8
-    x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0
-    x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8
-    x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0
-    x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8
-    x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400
-    x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408
-    x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410
-    x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418
-    x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420
-    x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428
-    x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430
-    x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438
-    x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440
-    x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448
-    x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450
-    x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458
-    x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460
-    x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468
-    x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470
-    x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478
-    x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480
-    x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488
-    x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490
-    x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498
-    x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0
-    x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8
-    x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0
-    x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8
-    x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0
-    x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8
-    x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0
-    x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8
-    x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0
-    x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8
-    x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0
-    x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500
-    x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508
-    x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510
-    x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518
-    x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520
-    x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528
-    x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530
-    x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538
-    x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540
-    x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548
-    x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550
-    x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558
-    x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560
-    x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570
-    x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578
-    x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580
-    x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588
-    x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590
-    x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598
-    x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0
-    x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8
-    x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0
-    x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8
-    x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0
-    x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8
-    x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0
-    x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8
-    x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0
-    x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8
-    x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0
-    x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8
-    x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600
-    x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608
-    x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610
-    x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618
-    x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620
-    x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630
-    x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638
-    x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640
-    x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648
-    x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650
-    x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660
-    x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668
-    x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670
-    x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678
-    x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680
-    x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690
-    x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698
-    x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0
-    x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8
-    x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0
-    x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8
-    x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0
-    x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8
-    x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0
-    x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8
-    x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0
-    x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8
-    x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0
-    x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700
-    x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708
-    x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710
-    x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728
-    x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730
-    x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738
-    x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740
-    x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750
-    x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758
-    x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760
-    x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768
-    x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778
-    x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780
-    x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788
-    x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790
-    x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0
-    x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8
-    x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8
-    x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0
-    x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8
-    x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0
-    x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8
-    x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0
-    x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-     DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd
deleted file mode 100644
index 95a9bd1..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd
+++ /dev/null
@@ -1,539 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-  port (
-    CLK         : in    std_logic;
-    ADDR        : in    unsigned(11 downto 0);
-    DATA        : out   unsigned(7 downto 0)
-    );
-end;
-
-architecture RTL of char_rom is
-
-
-  type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000
-    x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008
-    x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010
-    x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018
-    x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020
-    x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028
-    x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030
-    x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038
-    x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040
-    x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048
-    x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050
-    x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058
-    x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060
-    x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068
-    x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070
-    x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078
-    x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080
-    x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088
-    x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090
-    x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098
-    x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0
-    x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8
-    x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0
-    x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8
-    x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0
-    x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8
-    x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
-    x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108
-    x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110
-    x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118
-    x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120
-    x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128
-    x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130
-    x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138
-    x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140
-    x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148
-    x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150
-    x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
-    x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
-    x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178
-    x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180
-    x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188
-    x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190
-    x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198
-    x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0
-    x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8
-    x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0
-    x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8
-    x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0
-    x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8
-    x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0
-    x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8
-    x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0
-    x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
-    x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0
-    x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8
-    x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200
-    x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208
-    x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210
-    x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218
-    x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220
-    x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228
-    x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230
-    x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238
-    x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240
-    x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248
-    x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250
-    x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260
-    x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268
-    x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270
-    x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278
-    x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280
-    x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288
-    x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290
-    x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298
-    x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0
-    x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8
-    x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0
-    x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8
-    x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0
-    x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8
-    x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0
-    x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8
-    x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0
-    x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8
-    x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0
-    x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
-    x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370
-    x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
-    x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408
-    x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410
-    x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418
-    x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420
-    x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430
-    x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438
-    x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440
-    x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448
-    x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450
-    x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458
-    x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460
-    x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468
-    x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470
-    x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488
-    x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490
-    x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498
-    x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508
-    x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510
-    x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518
-    x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520
-    x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530
-    x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538
-    x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540
-    x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548
-    x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550
-    x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558
-    x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560
-    x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568
-    x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570
-    x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578
-    x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588
-    x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590
-    x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598
-    x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0
-    x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8
-    x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
-    x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608
-    x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610
-    x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618
-    x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620
-    x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630
-    x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638
-    x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640
-    x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648
-    x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650
-    x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658
-    x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660
-    x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668
-    x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670
-    x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678
-    x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688
-    x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690
-    x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698
-    x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0
-    x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8
-    x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0
-    x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
-    x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708
-    x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710
-    x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
-    x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
-    x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
-    x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
-    x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
-    x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740
-    x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748
-    x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750
-    x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758
-    x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
-    x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
-    x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
-    x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
-    x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
-    x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
-    x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
-    x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
-    x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
-    x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
-    x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
-    x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-     DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd
deleted file mode 100644
index ce977b6..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd
+++ /dev/null
@@ -1,539 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-  port (
-    CLK         : in    std_logic;
-    ADDR        : in    unsigned(11 downto 0);
-    DATA        : out   unsigned(7 downto 0)
-    );
-end;
-
-architecture RTL of char_rom is
-
-
-  type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000
-    x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008
-    x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010
-    x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018
-    x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020
-    x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028
-    x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030
-    x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038
-    x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040
-    x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048
-    x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050
-    x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058
-    x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060
-    x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068
-    x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070
-    x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078
-    x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080
-    x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088
-    x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090
-    x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098
-    x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0
-    x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8
-    x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0
-    x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8
-    x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0
-    x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8
-    x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0
-    x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8
-    x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0
-    x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8
-    x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0
-    x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100
-    x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108
-    x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110
-    x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118
-    x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120
-    x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128
-    x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130
-    x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138
-    x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140
-    x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148
-    x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150
-    x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160
-    x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168
-    x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170
-    x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178
-    x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180
-    x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188
-    x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190
-    x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198
-    x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0
-    x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8
-    x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0
-    x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8
-    x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0
-    x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8
-    x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0
-    x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8
-    x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0
-    x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8
-    x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0
-    x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8
-    x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200
-    x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208
-    x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210
-    x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218
-    x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220
-    x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228
-    x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230
-    x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238
-    x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240
-    x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248
-    x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250
-    x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258
-    x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260
-    x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268
-    x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270
-    x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278
-    x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280
-    x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288
-    x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290
-    x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298
-    x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0
-    x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8
-    x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0
-    x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-     DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd
deleted file mode 100644
index 3b60051..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd
+++ /dev/null
@@ -1,4383 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-	port
-	(
-	CLK			: in  std_logic;
-	ADDR		: in  unsigned(11 downto 0);
-	DATA		: out unsigned(7 downto 0)
-	);
-end;
-
-architecture RTL of char_rom is
-
-
-	type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-	constant ROM : ROM_ARRAY :=
-	(
-		-- ASCII 032 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 033 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"00111100", -- |  ####  | 05
-		"00111100", -- |  ####  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 034 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 035 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110110", -- |  ## ## | 03
-		"00110110", -- |  ## ## | 04
-		"01111111", -- | #######| 05
-		"00110110", -- |  ## ## | 06
-		"00110110", -- |  ## ## | 07
-		"00110110", -- |  ## ## | 08
-		"01111111", -- | #######| 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 036 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00011000", -- |   ##   | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00001100", -- |    ##  | 08
-		"00000110", -- |     ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		-- ASCII 037 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01110000", -- | ###    | 02
-		"11011000", -- |## ##   | 03
-		"11011010", -- |## ## # | 04
-		"01110110", -- | ### ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110000", -- |  ##    | 08
-		"01101110", -- | ## ### | 09
-		"01011011", -- | # ## ##| 10
-		"00011011", -- |   ## ##| 11
-		"00001110", -- |    ### | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 038 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"11111111", -- |########| 13
-		"00000000", -- |        | 14
-		-- ASCII 039 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 040 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00000000", -- |        | 14
-		-- ASCII 041 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00110000", -- |  ##    | 13
-		"00000000", -- |        | 14
-		-- ASCII 042 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00110110", -- |  ## ## | 05
-		"00011100", -- |   ###  | 06
-		"01111111", -- | #######| 07
-		"00011100", -- |   ###  | 08
-		"00110110", -- |  ## ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 043 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 044 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		-- ASCII 045 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 046 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 047 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"01100000", -- | ##     | 11
-		"01100000", -- | ##     | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 048 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011110", -- |   #### | 03
-		"00110011", -- |  ##  ##| 04
-		"00110111", -- |  ## ###| 05
-		"00110111", -- |  ## ###| 06
-		"00110011", -- |  ##  ##| 07
-		"00111011", -- |  ### ##| 08
-		"00111011", -- |  ### ##| 09
-		"00110011", -- |  ##  ##| 10
-		"00011110", -- |   #### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 049 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011100", -- |   ###  | 04
-		"01111100", -- | #####  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 050 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000110", -- |     ## | 06
-		"00001100", -- |    ##  | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 051 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000110", -- |     ## | 06
-		"00011100", -- |   ###  | 07
-		"00000110", -- |     ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 052 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00110000", -- |  ##    | 04
-		"00110110", -- |  ## ## | 05
-		"00110110", -- |  ## ## | 06
-		"00110110", -- |  ## ## | 07
-		"01100110", -- | ##  ## | 08
-		"01111111", -- | #######| 09
-		"00000110", -- |     ## | 10
-		"00000110", -- |     ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 053 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"00000110", -- |     ## | 08
-		"00000110", -- |     ## | 09
-		"00001100", -- |    ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 054 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011100", -- |   ###  | 03
-		"00011000", -- |   ##   | 04
-		"00110000", -- |  ##    | 05
-		"01111100", -- | #####  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 055 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00000110", -- |     ## | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 056 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01110110", -- | ### ## | 06
-		"00111100", -- |  ####  | 07
-		"01101110", -- | ## ### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 057 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"00111110", -- |  ##### | 08
-		"00001100", -- |    ##  | 09
-		"00011000", -- |   ##   | 10
-		"00111000", -- |  ###   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 058 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 059 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		-- ASCII 060 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"01100000", -- | ##     | 07
-		"00110000", -- |  ##    | 08
-		"00011000", -- |   ##   | 09
-		"00001100", -- |    ##  | 10
-		"00000110", -- |     ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 061 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"01111110", -- | ###### | 06
-		"00000000", -- |        | 07
-		"01111110", -- | ###### | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 062 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"00110000", -- |  ##    | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00000110", -- |     ## | 07
-		"00001100", -- |    ##  | 08
-		"00011000", -- |   ##   | 09
-		"00110000", -- |  ##    | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 063 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 064 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"11000011", -- |##    ##| 05
-		"11001111", -- |##  ####| 06
-		"11011011", -- |## ## ##| 07
-		"11011011", -- |## ## ##| 08
-		"11001111", -- |##  ####| 09
-		"11000000", -- |##      | 10
-		"01111111", -- | #######| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 065 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 066 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 067 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 068 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"01101100", -- | ## ##  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01101100", -- | ## ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 069 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 070 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 071 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01101110", -- | ## ### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 072 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111110", -- | ###### | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 073 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 074 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00000110", -- |     ## | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00000110", -- |     ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 075 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01101100", -- | ## ##  | 05
-		"01101100", -- | ## ##  | 06
-		"01111000", -- | ####   | 07
-		"01101100", -- | ## ##  | 08
-		"01101100", -- | ## ##  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 076 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 077 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110111", -- | ### ###| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 078 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110011", -- | ###  ##| 05
-		"01111011", -- | #### ##| 06
-		"01101111", -- | ## ####| 07
-		"01100111", -- | ##  ###| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 079 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 080 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 081 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00000110", -- |     ## | 13
-		"00000000", -- |        | 14
-		-- ASCII 082 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01101100", -- | ## ##  | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 083 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00001100", -- |    ##  | 08
-		"00000110", -- |     ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 084 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 085 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 086 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 087 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01100011", -- | ##   ##| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"00110110", -- |  ## ## | 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 088 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"00110100", -- |  ## #  | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00101100", -- |  # ##  | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 089 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 090 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00000110", -- |     ## | 04
-		"00000110", -- |     ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110000", -- |  ##    | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 091 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00110000", -- |  ##    | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00110000", -- |  ##    | 12
-		"00110000", -- |  ##    | 13
-		"00111100", -- |  ####  | 14
-		-- ASCII 092 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00000110", -- |     ## | 11
-		"00000110", -- |     ## | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 093 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00001100", -- |    ##  | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00001100", -- |    ##  | 12
-		"00001100", -- |    ##  | 13
-		"00111100", -- |  ####  | 14
-		-- ASCII 094 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 095 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"11111111", -- |########| 14
-		-- ASCII 096 ---------------
-		"00000000", -- |        | 00
-		"00111000", -- |  ###   | 01
-		"00011000", -- |   ##   | 02
-		"00001100", -- |    ##  | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 097 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 098 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 099 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 100 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 101 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 102 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011110", -- |   #### | 03
-		"00110000", -- |  ##    | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"01111110", -- | ###### | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 103 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"01111100", -- | #####  | 14
-		-- ASCII 104 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 105 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00011000", -- |   ##   | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 106 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00001100", -- |    ##  | 02
-		"00001100", -- |    ##  | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00001100", -- |    ##  | 12
-		"00001100", -- |    ##  | 13
-		"01111000", -- | ####   | 14
-		-- ASCII 107 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01101100", -- | ## ##  | 07
-		"01111000", -- | ####   | 08
-		"01101100", -- | ## ##  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 108 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 109 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111110", -- | ###### | 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01101011", -- | ## # ##| 09
-		"01101011", -- | ## # ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 110 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 111 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 112 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"01100000", -- | ##     | 14
-		-- ASCII 113 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"00000110", -- |     ## | 14
-		-- ASCII 114 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01101110", -- | ## ### | 06
-		"01110000", -- | ###    | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 115 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"00111100", -- |  ####  | 08
-		"00000110", -- |     ## | 09
-		"00000110", -- |     ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 116 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00110000", -- |  ##    | 04
-		"01111110", -- | ###### | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00011110", -- |   #### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 117 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 118 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 119 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100011", -- | ##   ##| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01101011", -- | ## # ##| 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 120 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00111100", -- |  ####  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 121 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		-- ASCII 122 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111110", -- | ###### | 05
-		"00000110", -- |     ## | 06
-		"00001100", -- |    ##  | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 123 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00110000", -- |  ##    | 07
-		"01100000", -- | ##     | 08
-		"00110000", -- |  ##    | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00000000", -- |        | 14
-		-- ASCII 124 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00011000", -- |   ##   | 14
-		-- ASCII 125 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00001100", -- |    ##  | 07
-		"00000110", -- |     ## | 08
-		"00001100", -- |    ##  | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00110000", -- |  ##    | 13
-		"00000000", -- |        | 14
-		-- ASCII 126 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01110001", -- | ###   #| 03
-		"11011011", -- |## ## ##| 04
-		"10001110", -- |#   ### | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 127 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 128 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 129 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 130 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 131 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 132 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 133 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 134 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 135 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 136 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 137 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 138 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 139 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 140 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 141 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 142 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 143 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 144 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 145 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 146 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011100", -- |   ###  | 03
-		"00011100", -- |   ###  | 04
-		"00001100", -- |    ##  | 05
-		"00011000", -- |   ##   | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 147 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 148 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 149 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 150 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 151 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 152 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 153 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 154 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 155 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 156 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 157 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 158 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 159 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 160 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 161 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00111100", -- |  ####  | 12
-		"00111100", -- |  ####  | 13
-		"00011000", -- |   ##   | 14
-		-- ASCII 162 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 163 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"11111100", -- |######  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"11000000", -- |##      | 10
-		"11111110", -- |####### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 164 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"01100110", -- | ##  ## | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"00111100", -- |  ####  | 08
-		"01100110", -- | ##  ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 165 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00111100", -- |  ####  | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"01111110", -- | ###### | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 166 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00011000", -- |   ##   | 14
-		-- ASCII 167 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00111000", -- |  ###   | 06
-		"00111100", -- |  ####  | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011100", -- |   ###  | 11
-		"00000110", -- |     ## | 12
-		"01100110", -- | ##  ## | 13
-		"00111100", -- |  ####  | 14
-		-- ASCII 168 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 169 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"10011001", -- |#  ##  #| 05
-		"10100101", -- |# #  # #| 06
-		"10100001", -- |# #    #| 07
-		"10100101", -- |# #  # #| 08
-		"10011001", -- |#  ##  #| 09
-		"11000011", -- |##    ##| 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 170 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00000110", -- |     ## | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"00111110", -- |  ##### | 07
-		"00000000", -- |        | 08
-		"01111110", -- | ###### | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 171 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00110011", -- |  ##  ##| 07
-		"01100110", -- | ##  ## | 08
-		"11001100", -- |##  ##  | 09
-		"01100110", -- | ##  ## | 10
-		"00110011", -- |  ##  ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 172 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000110", -- |     ## | 08
-		"00000110", -- |     ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 173 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 174 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"10111001", -- |# ###  #| 05
-		"10100101", -- |# #  # #| 06
-		"10100101", -- |# #  # #| 07
-		"10111001", -- |# ###  #| 08
-		"10100101", -- |# #  # #| 09
-		"11000011", -- |##    ##| 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 175 ---------------
-		"11111111", -- |########| 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 176 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"00111100", -- |  ####  | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 177 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00000000", -- |        | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 178 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"00111100", -- |  ####  | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 179 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00111000", -- |  ###   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 180 ---------------
-		"00000000", -- |        | 00
-		"00011100", -- |   ###  | 01
-		"00011000", -- |   ##   | 02
-		"00110000", -- |  ##    | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 181 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111011", -- | #### ##| 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"11000000", -- |##      | 14
-		-- ASCII 182 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011111", -- |   #####| 03
-		"00111110", -- |  ##### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"00111110", -- |  ##### | 08
-		"00011110", -- |   #### | 09
-		"00000110", -- |     ## | 10
-		"00000110", -- |     ## | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"00000110", -- |     ## | 14
-		-- ASCII 183 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011100", -- |   ###  | 06
-		"00011100", -- |   ###  | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 184 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		-- ASCII 185 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111000", -- |  ###   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 186 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00000000", -- |        | 08
-		"01111110", -- | ###### | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 187 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"11001100", -- |##  ##  | 07
-		"01100110", -- | ##  ## | 08
-		"00110011", -- |  ##  ##| 09
-		"01100110", -- | ##  ## | 10
-		"11001100", -- |##  ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 188 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100000", -- | ##     | 02
-		"11100000", -- |###     | 03
-		"01100011", -- | ##   ##| 04
-		"01100110", -- | ##  ## | 05
-		"01101100", -- | ## ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110111", -- |  ## ###| 08
-		"01101111", -- | ## ####| 09
-		"11011011", -- |## ## ##| 10
-		"00011111", -- |   #####| 11
-		"00000011", -- |      ##| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 189 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100000", -- | ##     | 02
-		"11100000", -- |###     | 03
-		"01100011", -- | ##   ##| 04
-		"01100110", -- | ##  ## | 05
-		"01101100", -- | ## ##  | 06
-		"00011000", -- |   ##   | 07
-		"00111110", -- |  ##### | 08
-		"01100011", -- | ##   ##| 09
-		"11000110", -- |##   ## | 10
-		"00001100", -- |    ##  | 11
-		"00001111", -- |    ####| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 190 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"11100000", -- |###     | 02
-		"00110000", -- |  ##    | 03
-		"01100011", -- | ##   ##| 04
-		"00110110", -- |  ## ## | 05
-		"11101100", -- |### ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110111", -- |  ## ###| 08
-		"01101111", -- | ## ####| 09
-		"11011011", -- |## ## ##| 10
-		"00011111", -- |   #####| 11
-		"00000011", -- |      ##| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 191 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00110000", -- |  ##    | 11
-		"01100110", -- | ##  ## | 12
-		"01100110", -- | ##  ## | 13
-		"00111100", -- |  ####  | 14
-		-- ASCII 192 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 193 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 194 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 195 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 196 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 197 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00111100", -- |  ####  | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 198 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001111", -- |    ####| 03
-		"00011100", -- |   ###  | 04
-		"00111100", -- |  ####  | 05
-		"01101100", -- | ## ##  | 06
-		"01101111", -- | ## ####| 07
-		"01111100", -- | #####  | 08
-		"01101100", -- | ## ##  | 09
-		"01101100", -- | ## ##  | 10
-		"01101111", -- | ## ####| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 199 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		-- ASCII 200 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 201 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 202 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 203 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 204 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 205 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 206 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 207 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 208 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"01101100", -- | ## ##  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"11110110", -- |#### ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01101100", -- | ## ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 209 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110011", -- | ###  ##| 05
-		"01111011", -- | #### ##| 06
-		"01101111", -- | ## ####| 07
-		"01100111", -- | ##  ###| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 210 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 211 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 212 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 213 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 214 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 215 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"01000010", -- | #    # | 04
-		"01100110", -- | ##  ## | 05
-		"00111100", -- |  ####  | 06
-		"00011000", -- |   ##   | 07
-		"00111100", -- |  ####  | 08
-		"01100110", -- | ##  ## | 09
-		"01000010", -- | #    # | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 216 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111110", -- |  ##### | 03
-		"01100110", -- | ##  ## | 04
-		"01101110", -- | ## ### | 05
-		"01101110", -- | ## ### | 06
-		"01111110", -- | ###### | 07
-		"01110110", -- | ### ## | 08
-		"01110110", -- | ### ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 217 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 218 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 219 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 220 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 221 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 222 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01111100", -- | #####  | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 223 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"01101100", -- | ## ##  | 04
-		"01101100", -- | ## ##  | 05
-		"01101100", -- | ## ##  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01101100", -- | ## ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 224 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 225 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 226 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 227 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 228 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 229 ---------------
-		"00000000", -- |        | 00
-		"00111100", -- |  ####  | 01
-		"01100110", -- | ##  ## | 02
-		"00111100", -- |  ####  | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 230 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01101110", -- | ## ### | 05
-		"00011011", -- |   ## ##| 06
-		"00011011", -- |   ## ##| 07
-		"01111111", -- | #######| 08
-		"11011000", -- |## ##   | 09
-		"11011000", -- |## ##   | 10
-		"01110111", -- | ### ###| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 231 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		-- ASCII 232 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 233 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 234 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 235 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 236 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 237 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 238 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 239 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 240 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110110", -- |  ## ## | 03
-		"00011000", -- |   ##   | 04
-		"01101100", -- | ## ##  | 05
-		"00011110", -- |   #### | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 241 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 242 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 243 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 244 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 245 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 246 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 247 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 248 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01101110", -- | ## ### | 07
-		"01111110", -- | ###### | 08
-		"01110110", -- | ### ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 249 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 250 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 251 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 252 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 253 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		-- ASCII 254 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01111100", -- | #####  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"01100000", -- | ##     | 14
-		-- ASCII 255 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		-- ASCII 256 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 257 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 258 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 259 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 260 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 261 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 262 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 263 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 264 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 265 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 266 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 267 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 268 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 269 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 270 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 271 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 272 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 273 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 274 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 275 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 276 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 277 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 278 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 279 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 280 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 281 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 282 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 283 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 284 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 285 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 286 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- ASCII 287 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		-- Padding ---------------
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000", -- Padded
-		"00000000" -- Padded
-	);
-begin
-
-	p_rom : process
-	begin
-		wait until rising_edge(CLK);
-		DATA <= ROM(to_integer(unsigned(ADDR)));
-	end process;
-
-end RTL;
-
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd
deleted file mode 100644
index e46151c..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd
+++ /dev/null
@@ -1,4382 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-	port
-	(
-	CLK			: in  std_logic;
-	ADDR		: in  unsigned(11 downto 0);
-	DATA		: out unsigned(7 downto 0)
-	);
-end;
-
-architecture RTL of char_rom is
-
-
-	type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-	constant ROM : ROM_ARRAY :=
-	(
-		-- ASCII 032 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 033 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"00111100", -- |  ####  | 05
-		"00111100", -- |  ####  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 034 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 035 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110110", -- |  ## ## | 03
-		"00110110", -- |  ## ## | 04
-		"01111111", -- | #######| 05
-		"00110110", -- |  ## ## | 06
-		"00110110", -- |  ## ## | 07
-		"00110110", -- |  ## ## | 08
-		"01111111", -- | #######| 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 036 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00011000", -- |   ##   | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00001100", -- |    ##  | 08
-		"00000110", -- |     ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 037 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01110000", -- | ###    | 02
-		"11011000", -- |## ##   | 03
-		"11011010", -- |## ## # | 04
-		"01110110", -- | ### ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110000", -- |  ##    | 08
-		"01101110", -- | ## ### | 09
-		"01011011", -- | # ## ##| 10
-		"00011011", -- |   ## ##| 11
-		"00001110", -- |    ### | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 038 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"11111111", -- |########| 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 039 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 040 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 041 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00110000", -- |  ##    | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 042 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00110110", -- |  ## ## | 05
-		"00011100", -- |   ###  | 06
-		"01111111", -- | #######| 07
-		"00011100", -- |   ###  | 08
-		"00110110", -- |  ## ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 043 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 044 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 045 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 046 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 047 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"01100000", -- | ##     | 11
-		"01100000", -- | ##     | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 048 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011110", -- |   #### | 03
-		"00110011", -- |  ##  ##| 04
-		"00110111", -- |  ## ###| 05
-		"00110111", -- |  ## ###| 06
-		"00110011", -- |  ##  ##| 07
-		"00111011", -- |  ### ##| 08
-		"00111011", -- |  ### ##| 09
-		"00110011", -- |  ##  ##| 10
-		"00011110", -- |   #### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 049 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011100", -- |   ###  | 04
-		"01111100", -- | #####  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 050 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000110", -- |     ## | 06
-		"00001100", -- |    ##  | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 051 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00000110", -- |     ## | 06
-		"00011100", -- |   ###  | 07
-		"00000110", -- |     ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 052 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00110000", -- |  ##    | 04
-		"00110110", -- |  ## ## | 05
-		"00110110", -- |  ## ## | 06
-		"00110110", -- |  ## ## | 07
-		"01100110", -- | ##  ## | 08
-		"01111111", -- | #######| 09
-		"00000110", -- |     ## | 10
-		"00000110", -- |     ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 053 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"00000110", -- |     ## | 08
-		"00000110", -- |     ## | 09
-		"00001100", -- |    ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 054 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011100", -- |   ###  | 03
-		"00011000", -- |   ##   | 04
-		"00110000", -- |  ##    | 05
-		"01111100", -- | #####  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 055 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00000110", -- |     ## | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 056 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01110110", -- | ### ## | 06
-		"00111100", -- |  ####  | 07
-		"01101110", -- | ## ### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 057 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"00111110", -- |  ##### | 08
-		"00001100", -- |    ##  | 09
-		"00011000", -- |   ##   | 10
-		"00111000", -- |  ###   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 058 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 059 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011100", -- |   ###  | 10
-		"00011100", -- |   ###  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 060 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"01100000", -- | ##     | 07
-		"00110000", -- |  ##    | 08
-		"00011000", -- |   ##   | 09
-		"00001100", -- |    ##  | 10
-		"00000110", -- |     ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 061 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"01111110", -- | ###### | 06
-		"00000000", -- |        | 07
-		"01111110", -- | ###### | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 062 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"00110000", -- |  ##    | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00000110", -- |     ## | 07
-		"00001100", -- |    ##  | 08
-		"00011000", -- |   ##   | 09
-		"00110000", -- |  ##    | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 063 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 064 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"11000011", -- |##    ##| 05
-		"11001111", -- |##  ####| 06
-		"11011011", -- |## ## ##| 07
-		"11011011", -- |## ## ##| 08
-		"11001111", -- |##  ####| 09
-		"11000000", -- |##      | 10
-		"01111111", -- | #######| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 065 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 066 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 067 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 068 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"01101100", -- | ## ##  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01101100", -- | ## ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 069 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 070 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 071 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01101110", -- | ## ### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 072 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111110", -- | ###### | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 073 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 074 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00000110", -- |     ## | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00000110", -- |     ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 075 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01101100", -- | ## ##  | 05
-		"01101100", -- | ## ##  | 06
-		"01111000", -- | ####   | 07
-		"01101100", -- | ## ##  | 08
-		"01101100", -- | ## ##  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 076 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 077 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110111", -- | ### ###| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 078 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110011", -- | ###  ##| 05
-		"01111011", -- | #### ##| 06
-		"01101111", -- | ## ####| 07
-		"01100111", -- | ##  ###| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 079 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 080 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 081 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00000110", -- |     ## | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 082 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111100", -- | #####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01111100", -- | #####  | 07
-		"01101100", -- | ## ##  | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 083 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00001100", -- |    ##  | 08
-		"00000110", -- |     ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 084 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 085 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 086 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 087 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01100011", -- | ##   ##| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"00110110", -- |  ## ## | 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 088 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"00110100", -- |  ## #  | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00101100", -- |  # ##  | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 089 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 090 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"00000110", -- |     ## | 04
-		"00000110", -- |     ## | 05
-		"00001100", -- |    ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110000", -- |  ##    | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 091 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00110000", -- |  ##    | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00110000", -- |  ##    | 12
-		"00110000", -- |  ##    | 13
-		"00111100", -- |  ####  | 14
-		"00000000", -- |        | 15
-		-- ASCII 092 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00000110", -- |     ## | 11
-		"00000110", -- |     ## | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 093 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00001100", -- |    ##  | 04
-		"00001100", -- |    ##  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00001100", -- |    ##  | 12
-		"00001100", -- |    ##  | 13
-		"00111100", -- |  ####  | 14
-		"00000000", -- |        | 15
-		-- ASCII 094 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 095 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"11111111", -- |########| 14
-		"00000000", -- |        | 15
-		-- ASCII 096 ---------------
-		"00000000", -- |        | 00
-		"00111000", -- |  ###   | 01
-		"00011000", -- |   ##   | 02
-		"00001100", -- |    ##  | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 097 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 098 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 099 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 100 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000110", -- |     ## | 03
-		"00000110", -- |     ## | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 101 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 102 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011110", -- |   #### | 03
-		"00110000", -- |  ##    | 04
-		"00110000", -- |  ##    | 05
-		"00110000", -- |  ##    | 06
-		"01111110", -- | ###### | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00110000", -- |  ##    | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 103 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"01111100", -- | #####  | 14
-		"00000000", -- |        | 15
-		-- ASCII 104 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 105 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00011000", -- |   ##   | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 106 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00001100", -- |    ##  | 02
-		"00001100", -- |    ##  | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00001100", -- |    ##  | 06
-		"00001100", -- |    ##  | 07
-		"00001100", -- |    ##  | 08
-		"00001100", -- |    ##  | 09
-		"00001100", -- |    ##  | 10
-		"00001100", -- |    ##  | 11
-		"00001100", -- |    ##  | 12
-		"00001100", -- |    ##  | 13
-		"01111000", -- | ####   | 14
-		"00000000", -- |        | 15
-		-- ASCII 107 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01101100", -- | ## ##  | 07
-		"01111000", -- | ####   | 08
-		"01101100", -- | ## ##  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 108 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 109 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111110", -- | ###### | 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01101011", -- | ## # ##| 09
-		"01101011", -- | ## # ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 110 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 111 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 112 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"01100000", -- | ##     | 14
-		"00000000", -- |        | 15
-		-- ASCII 113 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"00000110", -- |     ## | 14
-		"00000000", -- |        | 15
-		-- ASCII 114 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01101110", -- | ## ### | 06
-		"01110000", -- | ###    | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 115 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"00111100", -- |  ####  | 08
-		"00000110", -- |     ## | 09
-		"00000110", -- |     ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 116 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00110000", -- |  ##    | 04
-		"01111110", -- | ###### | 05
-		"00110000", -- |  ##    | 06
-		"00110000", -- |  ##    | 07
-		"00110000", -- |  ##    | 08
-		"00110000", -- |  ##    | 09
-		"00110000", -- |  ##    | 10
-		"00011110", -- |   #### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 117 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 118 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 119 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100011", -- | ##   ##| 05
-		"01101011", -- | ## # ##| 06
-		"01101011", -- | ## # ##| 07
-		"01101011", -- | ## # ##| 08
-		"01101011", -- | ## # ##| 09
-		"00110110", -- |  ## ## | 10
-		"00110110", -- |  ## ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 120 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00111100", -- |  ####  | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 121 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		"00000000", -- |        | 15
-		-- ASCII 122 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01111110", -- | ###### | 05
-		"00000110", -- |     ## | 06
-		"00001100", -- |    ##  | 07
-		"00011000", -- |   ##   | 08
-		"00110000", -- |  ##    | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 123 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00110000", -- |  ##    | 07
-		"01100000", -- | ##     | 08
-		"00110000", -- |  ##    | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 124 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00011000", -- |   ##   | 14
-		"00000000", -- |        | 15
-		-- ASCII 125 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110000", -- |  ##    | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00001100", -- |    ##  | 07
-		"00000110", -- |     ## | 08
-		"00001100", -- |    ##  | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00110000", -- |  ##    | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 126 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01110001", -- | ###   #| 03
-		"11011011", -- |## ## ##| 04
-		"10001110", -- |#   ### | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 127 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 128 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 129 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 130 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 131 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 132 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 133 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 134 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 135 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 136 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 137 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 138 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 139 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 140 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 141 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 142 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 143 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 144 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 145 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001100", -- |    ##  | 03
-		"00011000", -- |   ##   | 04
-		"00011100", -- |   ###  | 05
-		"00011100", -- |   ###  | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 146 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011100", -- |   ###  | 03
-		"00011100", -- |   ###  | 04
-		"00001100", -- |    ##  | 05
-		"00011000", -- |   ##   | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 147 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 148 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 149 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 150 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 151 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 152 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 153 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 154 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 155 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 156 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 157 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 158 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 159 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01111110", -- | ###### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"01111110", -- | ###### | 08
-		"01111110", -- | ###### | 09
-		"01111110", -- | ###### | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 160 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 161 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00111100", -- |  ####  | 12
-		"00111100", -- |  ####  | 13
-		"00011000", -- |   ##   | 14
-		"00000000", -- |        | 15
-		-- ASCII 162 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 163 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"11111100", -- |######  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"11000000", -- |##      | 10
-		"11111110", -- |####### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 164 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"01100110", -- | ##  ## | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"00111100", -- |  ####  | 08
-		"01100110", -- | ##  ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 165 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"00111100", -- |  ####  | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"01111110", -- | ###### | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 166 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00011000", -- |   ##   | 12
-		"00011000", -- |   ##   | 13
-		"00011000", -- |   ##   | 14
-		"00000000", -- |        | 15
-		-- ASCII 167 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100000", -- | ##     | 05
-		"00111000", -- |  ###   | 06
-		"00111100", -- |  ####  | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"00111100", -- |  ####  | 10
-		"00011100", -- |   ###  | 11
-		"00000110", -- |     ## | 12
-		"01100110", -- | ##  ## | 13
-		"00111100", -- |  ####  | 14
-		"00000000", -- |        | 15
-		-- ASCII 168 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 169 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"10011001", -- |#  ##  #| 05
-		"10100101", -- |# #  # #| 06
-		"10100001", -- |# #    #| 07
-		"10100101", -- |# #  # #| 08
-		"10011001", -- |#  ##  #| 09
-		"11000011", -- |##    ##| 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 170 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00000110", -- |     ## | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"00111110", -- |  ##### | 07
-		"00000000", -- |        | 08
-		"01111110", -- | ###### | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 171 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00110011", -- |  ##  ##| 07
-		"01100110", -- | ##  ## | 08
-		"11001100", -- |##  ##  | 09
-		"01100110", -- | ##  ## | 10
-		"00110011", -- |  ##  ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 172 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000110", -- |     ## | 08
-		"00000110", -- |     ## | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 173 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 174 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"11000011", -- |##    ##| 04
-		"10111001", -- |# ###  #| 05
-		"10100101", -- |# #  # #| 06
-		"10100101", -- |# #  # #| 07
-		"10111001", -- |# ###  #| 08
-		"10100101", -- |# #  # #| 09
-		"11000011", -- |##    ##| 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 175 ---------------
-		"11111111", -- |########| 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 176 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"00111100", -- |  ####  | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 177 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"01111110", -- | ###### | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00000000", -- |        | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 178 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00110000", -- |  ##    | 06
-		"00111100", -- |  ####  | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 179 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"00001100", -- |    ##  | 04
-		"00011000", -- |   ##   | 05
-		"00001100", -- |    ##  | 06
-		"00111000", -- |  ###   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 180 ---------------
-		"00000000", -- |        | 00
-		"00011100", -- |   ###  | 01
-		"00011000", -- |   ##   | 02
-		"00110000", -- |  ##    | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 181 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111011", -- | #### ##| 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"11000000", -- |##      | 14
-		"00000000", -- |        | 15
-		-- ASCII 182 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011111", -- |   #####| 03
-		"00111110", -- |  ##### | 04
-		"01111110", -- | ###### | 05
-		"01111110", -- | ###### | 06
-		"01111110", -- | ###### | 07
-		"00111110", -- |  ##### | 08
-		"00011110", -- |   #### | 09
-		"00000110", -- |     ## | 10
-		"00000110", -- |     ## | 11
-		"00000110", -- |     ## | 12
-		"00000110", -- |     ## | 13
-		"00000110", -- |     ## | 14
-		"00000000", -- |        | 15
-		-- ASCII 183 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011100", -- |   ###  | 06
-		"00011100", -- |   ###  | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 184 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		"00000000", -- |        | 15
-		-- ASCII 185 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111000", -- |  ###   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 186 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00000000", -- |        | 08
-		"01111110", -- | ###### | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 187 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"11001100", -- |##  ##  | 07
-		"01100110", -- | ##  ## | 08
-		"00110011", -- |  ##  ##| 09
-		"01100110", -- | ##  ## | 10
-		"11001100", -- |##  ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 188 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100000", -- | ##     | 02
-		"11100000", -- |###     | 03
-		"01100011", -- | ##   ##| 04
-		"01100110", -- | ##  ## | 05
-		"01101100", -- | ## ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110111", -- |  ## ###| 08
-		"01101111", -- | ## ####| 09
-		"11011011", -- |## ## ##| 10
-		"00011111", -- |   #####| 11
-		"00000011", -- |      ##| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 189 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100000", -- | ##     | 02
-		"11100000", -- |###     | 03
-		"01100011", -- | ##   ##| 04
-		"01100110", -- | ##  ## | 05
-		"01101100", -- | ## ##  | 06
-		"00011000", -- |   ##   | 07
-		"00111110", -- |  ##### | 08
-		"01100011", -- | ##   ##| 09
-		"11000110", -- |##   ## | 10
-		"00001100", -- |    ##  | 11
-		"00001111", -- |    ####| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 190 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"11100000", -- |###     | 02
-		"00110000", -- |  ##    | 03
-		"01100011", -- | ##   ##| 04
-		"00110110", -- |  ## ## | 05
-		"11101100", -- |### ##  | 06
-		"00011000", -- |   ##   | 07
-		"00110111", -- |  ## ###| 08
-		"01101111", -- | ## ####| 09
-		"11011011", -- |## ## ##| 10
-		"00011111", -- |   #####| 11
-		"00000011", -- |      ##| 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 191 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00110000", -- |  ##    | 11
-		"01100110", -- | ##  ## | 12
-		"01100110", -- | ##  ## | 13
-		"00111100", -- |  ####  | 14
-		"00000000", -- |        | 15
-		-- ASCII 192 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 193 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 194 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 195 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 196 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 197 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00111100", -- |  ####  | 02
-		"00011000", -- |   ##   | 03
-		"00111100", -- |  ####  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 198 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00001111", -- |    ####| 03
-		"00011100", -- |   ###  | 04
-		"00111100", -- |  ####  | 05
-		"01101100", -- | ## ##  | 06
-		"01101111", -- | ## ####| 07
-		"01111100", -- | #####  | 08
-		"01101100", -- | ## ##  | 09
-		"01101100", -- | ## ##  | 10
-		"01101111", -- | ## ####| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 199 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100000", -- | ##     | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		"00000000", -- |        | 15
-		-- ASCII 200 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 201 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 202 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 203 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01111110", -- | ###### | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01100000", -- | ##     | 06
-		"01111100", -- | #####  | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 204 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 205 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 206 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 207 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 208 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01111000", -- | ####   | 03
-		"01101100", -- | ## ##  | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"11110110", -- |#### ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01101100", -- | ## ##  | 10
-		"01111000", -- | ####   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 209 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"01100011", -- | ##   ##| 03
-		"01100011", -- | ##   ##| 04
-		"01110011", -- | ###  ##| 05
-		"01111011", -- | #### ##| 06
-		"01101111", -- | ## ####| 07
-		"01100111", -- | ##  ###| 08
-		"01100011", -- | ##   ##| 09
-		"01100011", -- | ##   ##| 10
-		"01100011", -- | ##   ##| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 210 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 211 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 212 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 213 ---------------
-		"00111011", -- |  ### ##| 00
-		"01101110", -- | ## ### | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 214 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"00111100", -- |  ####  | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 215 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"01000010", -- | #    # | 04
-		"01100110", -- | ##  ## | 05
-		"00111100", -- |  ####  | 06
-		"00011000", -- |   ##   | 07
-		"00111100", -- |  ####  | 08
-		"01100110", -- | ##  ## | 09
-		"01000010", -- | #    # | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 216 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111110", -- |  ##### | 03
-		"01100110", -- | ##  ## | 04
-		"01101110", -- | ## ### | 05
-		"01101110", -- | ## ### | 06
-		"01111110", -- | ###### | 07
-		"01110110", -- | ### ## | 08
-		"01110110", -- | ### ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 217 ---------------
-		"00110000", -- |  ##    | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 218 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 219 ---------------
-		"00111100", -- |  ####  | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 220 ---------------
-		"01100110", -- | ##  ## | 00
-		"01100110", -- | ##  ## | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 221 ---------------
-		"00001100", -- |    ##  | 00
-		"00011000", -- |   ##   | 01
-		"00000000", -- |        | 02
-		"01100110", -- | ##  ## | 03
-		"01100110", -- | ##  ## | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"00111100", -- |  ####  | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00011000", -- |   ##   | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 222 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01111100", -- | #####  | 09
-		"01100000", -- | ##     | 10
-		"01100000", -- | ##     | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 223 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00111000", -- |  ###   | 03
-		"01101100", -- | ## ##  | 04
-		"01101100", -- | ## ##  | 05
-		"01101100", -- | ## ##  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01101100", -- | ## ##  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 224 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 225 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 226 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 227 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 228 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 229 ---------------
-		"00000000", -- |        | 00
-		"00111100", -- |  ####  | 01
-		"01100110", -- | ##  ## | 02
-		"00111100", -- |  ####  | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"00000110", -- |     ## | 06
-		"00000110", -- |     ## | 07
-		"00111110", -- |  ##### | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 230 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"01101110", -- | ## ### | 05
-		"00011011", -- |   ## ##| 06
-		"00011011", -- |   ## ##| 07
-		"01111111", -- | #######| 08
-		"11011000", -- |## ##   | 09
-		"11011000", -- |## ##   | 10
-		"01110111", -- | ### ###| 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 231 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100000", -- | ##     | 07
-		"01100000", -- | ##     | 08
-		"01100000", -- | ##     | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00011000", -- |   ##   | 12
-		"00001100", -- |    ##  | 13
-		"00111000", -- |  ###   | 14
-		"00000000", -- |        | 15
-		-- ASCII 232 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 233 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 234 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 235 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01111110", -- | ###### | 08
-		"01100000", -- | ##     | 09
-		"01100000", -- | ##     | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 236 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 237 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 238 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 239 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01111000", -- | ####   | 05
-		"00011000", -- |   ##   | 06
-		"00011000", -- |   ##   | 07
-		"00011000", -- |   ##   | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"01111110", -- | ###### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 240 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00110110", -- |  ## ## | 03
-		"00011000", -- |   ##   | 04
-		"01101100", -- | ## ##  | 05
-		"00011110", -- |   #### | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 241 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"01111100", -- | #####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01100110", -- | ##  ## | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 242 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 243 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 244 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 245 ---------------
-		"00000000", -- |        | 00
-		"01110001", -- | ###   #| 01
-		"11011011", -- |## ## ##| 02
-		"10001110", -- |#   ### | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 246 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"00111100", -- |  ####  | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 247 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00011000", -- |   ##   | 04
-		"00011000", -- |   ##   | 05
-		"00000000", -- |        | 06
-		"01111110", -- | ###### | 07
-		"00000000", -- |        | 08
-		"00011000", -- |   ##   | 09
-		"00011000", -- |   ##   | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 248 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00111110", -- |  ##### | 05
-		"01100110", -- | ##  ## | 06
-		"01101110", -- | ## ### | 07
-		"01111110", -- | ###### | 08
-		"01110110", -- | ### ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 249 ---------------
-		"00000000", -- |        | 00
-		"01110000", -- | ###    | 01
-		"00110000", -- |  ##    | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 250 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 251 ---------------
-		"00000000", -- |        | 00
-		"00011000", -- |   ##   | 01
-		"00111100", -- |  ####  | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 252 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111110", -- |  ##### | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 253 ---------------
-		"00000000", -- |        | 00
-		"00001110", -- |    ### | 01
-		"00001100", -- |    ##  | 02
-		"00011000", -- |   ##   | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		"00000000", -- |        | 15
-		-- ASCII 254 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"01100000", -- | ##     | 03
-		"01100000", -- | ##     | 04
-		"01100000", -- | ##     | 05
-		"01111100", -- | #####  | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"01111100", -- | #####  | 11
-		"01100000", -- | ##     | 12
-		"01100000", -- | ##     | 13
-		"01100000", -- | ##     | 14
-		"00000000", -- |        | 15
-		-- ASCII 255 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"01100110", -- | ##  ## | 02
-		"01100110", -- | ##  ## | 03
-		"00000000", -- |        | 04
-		"01100110", -- | ##  ## | 05
-		"01100110", -- | ##  ## | 06
-		"01100110", -- | ##  ## | 07
-		"01100110", -- | ##  ## | 08
-		"01100110", -- | ##  ## | 09
-		"01100110", -- | ##  ## | 10
-		"00111100", -- |  ####  | 11
-		"00001100", -- |    ##  | 12
-		"00011000", -- |   ##   | 13
-		"11110000", -- |####    | 14
-		"00000000", -- |        | 15
-		-- ASCII 256 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 257 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 258 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 259 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 260 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 261 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 262 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 263 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 264 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 265 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 266 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 267 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 268 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 269 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 270 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 271 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 272 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 273 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 274 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 275 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 276 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 277 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 278 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 279 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 280 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 281 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 282 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 283 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 284 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 285 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 286 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"00000000", -- |        | 12
-		"00000000", -- |        | 13
-		"00000000", -- |        | 14
-		"00000000", -- |        | 15
-		-- ASCII 287 ---------------
-		"00000000", -- |        | 00
-		"00000000", -- |        | 01
-		"00000000", -- |        | 02
-		"00000000", -- |        | 03
-		"00000000", -- |        | 04
-		"00000000", -- |        | 05
-		"00000000", -- |        | 06
-		"00000000", -- |        | 07
-		"00000000", -- |        | 08
-		"00000000", -- |        | 09
-		"00000000", -- |        | 10
-		"00000000", -- |        | 11
-		"11111111", -- |########| 12
-		"11111111", -- |########| 13
-		"11111111", -- |########| 14
-		"00000000"  -- |        | 15
-	);
-begin
-
-	p_rom : process
-	begin
-		wait until rising_edge(CLK);
-		DATA <= ROM(to_integer(unsigned(ADDR)));
-	end process;
-
-end RTL;
-
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd
deleted file mode 100644
index 9b32d16..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd
+++ /dev/null
@@ -1,4351 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-	port
-	(
-	CLK			: in  std_logic;
-	ADDR		: in  unsigned(11 downto 0);
-	DATA		: out unsigned(8 downto 0)
-	);
-end;
-
-architecture RTL of char_rom is
-
-
-	type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0);
-	constant ROM : ROM_ARRAY :=
-	(
-		-- ASCII 032 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 033 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"001111000", -- |  ####   | 05
-		"001111000", -- |  ####   | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000000000", -- |         | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 034 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 035 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001101100", -- |  ## ##  | 03
-		"001101100", -- |  ## ##  | 04
-		"011111110", -- | ####### | 05
-		"001101100", -- |  ## ##  | 06
-		"001101100", -- |  ## ##  | 07
-		"001101100", -- |  ## ##  | 08
-		"011111110", -- | ####### | 09
-		"001101100", -- |  ## ##  | 10
-		"001101100", -- |  ## ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 036 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"000110000", -- |   ##    | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011000000", -- | ##      | 05
-		"001100000", -- |  ##     | 06
-		"000110000", -- |   ##    | 07
-		"000011000", -- |    ##   | 08
-		"000001100", -- |     ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000110000", -- |   ##    | 12
-		"000110000", -- |   ##    | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 037 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011100000", -- | ###     | 02
-		"110110000", -- |## ##    | 03
-		"110110100", -- |## ## #  | 04
-		"011101100", -- | ### ##  | 05
-		"000011000", -- |    ##   | 06
-		"000110000", -- |   ##    | 07
-		"001100000", -- |  ##     | 08
-		"011011100", -- | ## ###  | 09
-		"010110110", -- | # ## ## | 10
-		"000110110", -- |   ## ## | 11
-		"000011100", -- |    ###  | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 038 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"111111110", -- |######## | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 039 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 040 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000011000", -- |    ##   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"001100000", -- |  ##     | 06
-		"001100000", -- |  ##     | 07
-		"001100000", -- |  ##     | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"000011000", -- |    ##   | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 041 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001100000", -- |  ##     | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000011000", -- |    ##   | 06
-		"000011000", -- |    ##   | 07
-		"000011000", -- |    ##   | 08
-		"000011000", -- |    ##   | 09
-		"000011000", -- |    ##   | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"001100000", -- |  ##     | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 042 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001101100", -- |  ## ##  | 05
-		"000111000", -- |   ###   | 06
-		"011111110", -- | ####### | 07
-		"000111000", -- |   ###   | 08
-		"001101100", -- |  ## ##  | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 043 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"011111100", -- | ######  | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 044 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000111000", -- |   ###   | 10
-		"000111000", -- |   ###   | 11
-		"000011000", -- |    ##   | 12
-		"000110000", -- |   ##    | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 045 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"011111100", -- | ######  | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 046 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000111000", -- |   ###   | 10
-		"000111000", -- |   ###   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 047 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000001100", -- |     ##  | 03
-		"000001100", -- |     ##  | 04
-		"000011000", -- |    ##   | 05
-		"000011000", -- |    ##   | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"011000000", -- | ##      | 11
-		"011000000", -- | ##      | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 048 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000111100", -- |   ####  | 03
-		"001100110", -- |  ##  ## | 04
-		"001101110", -- |  ## ### | 05
-		"001101110", -- |  ## ### | 06
-		"001100110", -- |  ##  ## | 07
-		"001110110", -- |  ### ## | 08
-		"001110110", -- |  ### ## | 09
-		"001100110", -- |  ##  ## | 10
-		"000111100", -- |   ####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 049 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000011000", -- |    ##   | 03
-		"000111000", -- |   ###   | 04
-		"011111000", -- | #####   | 05
-		"000011000", -- |    ##   | 06
-		"000011000", -- |    ##   | 07
-		"000011000", -- |    ##   | 08
-		"000011000", -- |    ##   | 09
-		"000011000", -- |    ##   | 10
-		"000011000", -- |    ##   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 050 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"000001100", -- |     ##  | 06
-		"000011000", -- |    ##   | 07
-		"000110000", -- |   ##    | 08
-		"001100000", -- |  ##     | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 051 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"000001100", -- |     ##  | 06
-		"000111000", -- |   ###   | 07
-		"000001100", -- |     ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 052 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001100000", -- |  ##     | 03
-		"001100000", -- |  ##     | 04
-		"001101100", -- |  ## ##  | 05
-		"001101100", -- |  ## ##  | 06
-		"001101100", -- |  ## ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011111110", -- | ####### | 09
-		"000001100", -- |     ##  | 10
-		"000001100", -- |     ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 053 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"000001100", -- |     ##  | 08
-		"000001100", -- |     ##  | 09
-		"000011000", -- |    ##   | 10
-		"011110000", -- | ####    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 054 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000111000", -- |   ###   | 03
-		"000110000", -- |   ##    | 04
-		"001100000", -- |  ##     | 05
-		"011111000", -- | #####   | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 055 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"000001100", -- |     ##  | 04
-		"000011000", -- |    ##   | 05
-		"000011000", -- |    ##   | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"001100000", -- |  ##     | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 056 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011101100", -- | ### ##  | 06
-		"001111000", -- |  ####   | 07
-		"011011100", -- | ## ###  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 057 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"001111100", -- |  #####  | 08
-		"000011000", -- |    ##   | 09
-		"000110000", -- |   ##    | 10
-		"001110000", -- |  ###    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 058 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000111000", -- |   ###   | 05
-		"000111000", -- |   ###   | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000111000", -- |   ###   | 10
-		"000111000", -- |   ###   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 059 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000111000", -- |   ###   | 05
-		"000111000", -- |   ###   | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000111000", -- |   ###   | 10
-		"000111000", -- |   ###   | 11
-		"000011000", -- |    ##   | 12
-		"000110000", -- |   ##    | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 060 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000001100", -- |     ##  | 03
-		"000011000", -- |    ##   | 04
-		"000110000", -- |   ##    | 05
-		"001100000", -- |  ##     | 06
-		"011000000", -- | ##      | 07
-		"001100000", -- |  ##     | 08
-		"000110000", -- |   ##    | 09
-		"000011000", -- |    ##   | 10
-		"000001100", -- |     ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 061 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"011111100", -- | ######  | 06
-		"000000000", -- |         | 07
-		"011111100", -- | ######  | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 062 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"001100000", -- |  ##     | 04
-		"000110000", -- |   ##    | 05
-		"000011000", -- |    ##   | 06
-		"000001100", -- |     ##  | 07
-		"000011000", -- |    ##   | 08
-		"000110000", -- |   ##    | 09
-		"001100000", -- |  ##     | 10
-		"011000000", -- | ##      | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 063 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"000011000", -- |    ##   | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000000000", -- |         | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 064 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"110000110", -- |##    ## | 04
-		"110000110", -- |##    ## | 05
-		"110011110", -- |##  #### | 06
-		"110110110", -- |## ## ## | 07
-		"110110110", -- |## ## ## | 08
-		"110011110", -- |##  #### | 09
-		"110000000", -- |##       | 10
-		"011111110", -- | ####### | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 065 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 066 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111000", -- | #####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011111000", -- | #####   | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 067 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011000000", -- | ##      | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 068 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011110000", -- | ####    | 03
-		"011011000", -- | ## ##   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011011000", -- | ## ##   | 10
-		"011110000", -- | ####    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 069 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 070 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011000000", -- | ##      | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 071 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011000000", -- | ##      | 06
-		"011000000", -- | ##      | 07
-		"011011100", -- | ## ###  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 072 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011111100", -- | ######  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 073 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 074 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000001100", -- |     ##  | 03
-		"000001100", -- |     ##  | 04
-		"000001100", -- |     ##  | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"000001100", -- |     ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 075 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011011000", -- | ## ##   | 05
-		"011011000", -- | ## ##   | 06
-		"011110000", -- | ####    | 07
-		"011011000", -- | ## ##   | 08
-		"011011000", -- | ## ##   | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 076 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 077 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000110", -- | ##   ## | 03
-		"011000110", -- | ##   ## | 04
-		"011101110", -- | ### ### | 05
-		"011010110", -- | ## # ## | 06
-		"011010110", -- | ## # ## | 07
-		"011010110", -- | ## # ## | 08
-		"011000110", -- | ##   ## | 09
-		"011000110", -- | ##   ## | 10
-		"011000110", -- | ##   ## | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 078 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000110", -- | ##   ## | 03
-		"011000110", -- | ##   ## | 04
-		"011100110", -- | ###  ## | 05
-		"011110110", -- | #### ## | 06
-		"011011110", -- | ## #### | 07
-		"011001110", -- | ##  ### | 08
-		"011000110", -- | ##   ## | 09
-		"011000110", -- | ##   ## | 10
-		"011000110", -- | ##   ## | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 079 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 080 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111000", -- | #####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011000000", -- | ##      | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 081 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000011000", -- |    ##   | 12
-		"000001100", -- |     ##  | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 082 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111000", -- | #####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011111000", -- | #####   | 07
-		"011011000", -- | ## ##   | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 083 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011000000", -- | ##      | 05
-		"001100000", -- |  ##     | 06
-		"000110000", -- |   ##    | 07
-		"000011000", -- |    ##   | 08
-		"000001100", -- |     ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 084 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 085 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 086 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"001111000", -- |  ####   | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 087 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000110", -- | ##   ## | 03
-		"011000110", -- | ##   ## | 04
-		"011000110", -- | ##   ## | 05
-		"011010110", -- | ## # ## | 06
-		"011010110", -- | ## # ## | 07
-		"011010110", -- | ## # ## | 08
-		"001101100", -- |  ## ##  | 09
-		"001101100", -- |  ## ##  | 10
-		"001101100", -- |  ## ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 088 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"001101000", -- |  ## #   | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"001011000", -- |  # ##   | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 089 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"001111000", -- |  ####   | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 090 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"000001100", -- |     ##  | 04
-		"000001100", -- |     ##  | 05
-		"000011000", -- |    ##   | 06
-		"000110000", -- |   ##    | 07
-		"001100000", -- |  ##     | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 091 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"001100000", -- |  ##     | 04
-		"001100000", -- |  ##     | 05
-		"001100000", -- |  ##     | 06
-		"001100000", -- |  ##     | 07
-		"001100000", -- |  ##     | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"001100000", -- |  ##     | 11
-		"001100000", -- |  ##     | 12
-		"001100000", -- |  ##     | 13
-		"001111000", -- |  ####   | 14
-		"000000000", -- |         | 15
-		-- ASCII 092 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"001100000", -- |  ##     | 05
-		"001100000", -- |  ##     | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000011000", -- |    ##   | 09
-		"000011000", -- |    ##   | 10
-		"000001100", -- |     ##  | 11
-		"000001100", -- |     ##  | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 093 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000011000", -- |    ##   | 04
-		"000011000", -- |    ##   | 05
-		"000011000", -- |    ##   | 06
-		"000011000", -- |    ##   | 07
-		"000011000", -- |    ##   | 08
-		"000011000", -- |    ##   | 09
-		"000011000", -- |    ##   | 10
-		"000011000", -- |    ##   | 11
-		"000011000", -- |    ##   | 12
-		"000011000", -- |    ##   | 13
-		"001111000", -- |  ####   | 14
-		"000000000", -- |         | 15
-		-- ASCII 094 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 095 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"111111110", -- |######## | 14
-		"000000000", -- |         | 15
-		-- ASCII 096 ---------------
-		"000000000", -- |         | 00
-		"001110000", -- |  ###    | 01
-		"000110000", -- |   ##    | 02
-		"000011000", -- |    ##   | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 097 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 098 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 099 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 100 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000001100", -- |     ##  | 03
-		"000001100", -- |     ##  | 04
-		"001111100", -- |  #####  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 101 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 102 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000111100", -- |   ####  | 03
-		"001100000", -- |  ##     | 04
-		"001100000", -- |  ##     | 05
-		"001100000", -- |  ##     | 06
-		"011111100", -- | ######  | 07
-		"001100000", -- |  ##     | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"001100000", -- |  ##     | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 103 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111100", -- |  #####  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000001100", -- |     ##  | 12
-		"000001100", -- |     ##  | 13
-		"011111000", -- | #####   | 14
-		"000000000", -- |         | 15
-		-- ASCII 104 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 105 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000110000", -- |   ##    | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011110000", -- | ####    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 106 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000011000", -- |    ##   | 02
-		"000011000", -- |    ##   | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000011000", -- |    ##   | 06
-		"000011000", -- |    ##   | 07
-		"000011000", -- |    ##   | 08
-		"000011000", -- |    ##   | 09
-		"000011000", -- |    ##   | 10
-		"000011000", -- |    ##   | 11
-		"000011000", -- |    ##   | 12
-		"000011000", -- |    ##   | 13
-		"011110000", -- | ####    | 14
-		"000000000", -- |         | 15
-		-- ASCII 107 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011011000", -- | ## ##   | 07
-		"011110000", -- | ####    | 08
-		"011011000", -- | ## ##   | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 108 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011110000", -- | ####    | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 109 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011111100", -- | ######  | 05
-		"011010110", -- | ## # ## | 06
-		"011010110", -- | ## # ## | 07
-		"011010110", -- | ## # ## | 08
-		"011010110", -- | ## # ## | 09
-		"011010110", -- | ## # ## | 10
-		"011000110", -- | ##   ## | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 110 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 111 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 112 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"011000000", -- | ##      | 12
-		"011000000", -- | ##      | 13
-		"011000000", -- | ##      | 14
-		"000000000", -- |         | 15
-		-- ASCII 113 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111100", -- |  #####  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000001100", -- |     ##  | 12
-		"000001100", -- |     ##  | 13
-		"000001100", -- |     ##  | 14
-		"000000000", -- |         | 15
-		-- ASCII 114 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011011100", -- | ## ###  | 06
-		"011100000", -- | ###     | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011000000", -- | ##      | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 115 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111100", -- |  #####  | 05
-		"011000000", -- | ##      | 06
-		"011000000", -- | ##      | 07
-		"001111000", -- |  ####   | 08
-		"000001100", -- |     ##  | 09
-		"000001100", -- |     ##  | 10
-		"011111000", -- | #####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 116 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001100000", -- |  ##     | 03
-		"001100000", -- |  ##     | 04
-		"011111100", -- | ######  | 05
-		"001100000", -- |  ##     | 06
-		"001100000", -- |  ##     | 07
-		"001100000", -- |  ##     | 08
-		"001100000", -- |  ##     | 09
-		"001100000", -- |  ##     | 10
-		"000111100", -- |   ####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 117 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 118 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"001111000", -- |  ####   | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 119 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011000110", -- | ##   ## | 05
-		"011010110", -- | ## # ## | 06
-		"011010110", -- | ## # ## | 07
-		"011010110", -- | ## # ## | 08
-		"011010110", -- | ## # ## | 09
-		"001101100", -- |  ## ##  | 10
-		"001101100", -- |  ## ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 120 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"001111000", -- |  ####   | 07
-		"000110000", -- |   ##    | 08
-		"001111000", -- |  ####   | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 121 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000011000", -- |    ##   | 12
-		"000110000", -- |   ##    | 13
-		"111100000", -- |####     | 14
-		"000000000", -- |         | 15
-		-- ASCII 122 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011111100", -- | ######  | 05
-		"000001100", -- |     ##  | 06
-		"000011000", -- |    ##   | 07
-		"000110000", -- |   ##    | 08
-		"001100000", -- |  ##     | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 123 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000011000", -- |    ##   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"001100000", -- |  ##     | 07
-		"011000000", -- | ##      | 08
-		"001100000", -- |  ##     | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"000011000", -- |    ##   | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 124 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"000110000", -- |   ##    | 13
-		"000110000", -- |   ##    | 14
-		"000000000", -- |         | 15
-		-- ASCII 125 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001100000", -- |  ##     | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000011000", -- |    ##   | 07
-		"000001100", -- |     ##  | 08
-		"000011000", -- |    ##   | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"001100000", -- |  ##     | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 126 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011100010", -- | ###   # | 03
-		"110110110", -- |## ## ## | 04
-		"100011100", -- |#   ###  | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 127 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 128 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 129 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 130 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 131 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 132 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 133 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 134 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 135 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 136 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 137 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 138 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 139 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 140 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 141 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 142 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 143 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 144 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 145 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000011000", -- |    ##   | 03
-		"000110000", -- |   ##    | 04
-		"000111000", -- |   ###   | 05
-		"000111000", -- |   ###   | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 146 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000111000", -- |   ###   | 03
-		"000111000", -- |   ###   | 04
-		"000011000", -- |    ##   | 05
-		"000110000", -- |   ##    | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 147 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 148 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 149 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 150 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 151 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 152 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 153 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 154 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 155 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 156 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 157 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 158 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 159 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011111100", -- | ######  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"011111100", -- | ######  | 08
-		"011111100", -- | ######  | 09
-		"011111100", -- | ######  | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 160 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 161 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000000000", -- |         | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"001111000", -- |  ####   | 12
-		"001111000", -- |  ####   | 13
-		"000110000", -- |   ##    | 14
-		"000000000", -- |         | 15
-		-- ASCII 162 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"000110000", -- |   ##    | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011001100", -- | ##  ##  | 09
-		"001111000", -- |  ####   | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 163 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"111111000", -- |######   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"110000000", -- |##       | 10
-		"111111100", -- |#######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 164 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"011001100", -- | ##  ##  | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"001111000", -- |  ####   | 08
-		"011001100", -- | ##  ##  | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 165 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"001111000", -- |  ####   | 06
-		"011111100", -- | ######  | 07
-		"000110000", -- |   ##    | 08
-		"011111100", -- | ######  | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 166 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000110000", -- |   ##    | 12
-		"000110000", -- |   ##    | 13
-		"000110000", -- |   ##    | 14
-		"000000000", -- |         | 15
-		-- ASCII 167 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011000000", -- | ##      | 05
-		"001110000", -- |  ###    | 06
-		"001111000", -- |  ####   | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"001111000", -- |  ####   | 10
-		"000111000", -- |   ###   | 11
-		"000001100", -- |     ##  | 12
-		"011001100", -- | ##  ##  | 13
-		"001111000", -- |  ####   | 14
-		"000000000", -- |         | 15
-		-- ASCII 168 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 169 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"110000110", -- |##    ## | 04
-		"100110010", -- |#  ##  # | 05
-		"101001010", -- |# #  # # | 06
-		"101000010", -- |# #    # | 07
-		"101001010", -- |# #  # # | 08
-		"100110010", -- |#  ##  # | 09
-		"110000110", -- |##    ## | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 170 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000001100", -- |     ##  | 04
-		"001111100", -- |  #####  | 05
-		"011001100", -- | ##  ##  | 06
-		"001111100", -- |  #####  | 07
-		"000000000", -- |         | 08
-		"011111100", -- | ######  | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 171 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"001100110", -- |  ##  ## | 07
-		"011001100", -- | ##  ##  | 08
-		"110011000", -- |##  ##   | 09
-		"011001100", -- | ##  ##  | 10
-		"001100110", -- |  ##  ## | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 172 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"011111100", -- | ######  | 07
-		"000001100", -- |     ##  | 08
-		"000001100", -- |     ##  | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 173 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"011111100", -- | ######  | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 174 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"110000110", -- |##    ## | 04
-		"101110010", -- |# ###  # | 05
-		"101001010", -- |# #  # # | 06
-		"101001010", -- |# #  # # | 07
-		"101110010", -- |# ###  # | 08
-		"101001010", -- |# #  # # | 09
-		"110000110", -- |##    ## | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 175 ---------------
-		"111111110", -- |######## | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 176 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"001111000", -- |  ####   | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 177 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"011111100", -- | ######  | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000000000", -- |         | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 178 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001110000", -- |  ###    | 03
-		"000011000", -- |    ##   | 04
-		"000110000", -- |   ##    | 05
-		"001100000", -- |  ##     | 06
-		"001111000", -- |  ####   | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 179 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001110000", -- |  ###    | 03
-		"000011000", -- |    ##   | 04
-		"000110000", -- |   ##    | 05
-		"000011000", -- |    ##   | 06
-		"001110000", -- |  ###    | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 180 ---------------
-		"000000000", -- |         | 00
-		"000111000", -- |   ###   | 01
-		"000110000", -- |   ##    | 02
-		"001100000", -- |  ##     | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 181 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011110110", -- | #### ## | 11
-		"011000000", -- | ##      | 12
-		"011000000", -- | ##      | 13
-		"110000000", -- |##       | 14
-		"000000000", -- |         | 15
-		-- ASCII 182 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000111110", -- |   ##### | 03
-		"001111100", -- |  #####  | 04
-		"011111100", -- | ######  | 05
-		"011111100", -- | ######  | 06
-		"011111100", -- | ######  | 07
-		"001111100", -- |  #####  | 08
-		"000111100", -- |   ####  | 09
-		"000001100", -- |     ##  | 10
-		"000001100", -- |     ##  | 11
-		"000001100", -- |     ##  | 12
-		"000001100", -- |     ##  | 13
-		"000001100", -- |     ##  | 14
-		"000000000", -- |         | 15
-		-- ASCII 183 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000111000", -- |   ###   | 06
-		"000111000", -- |   ###   | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 184 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"000000000", -- |         | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000110000", -- |   ##    | 12
-		"000011000", -- |    ##   | 13
-		"001110000", -- |  ###    | 14
-		"000000000", -- |         | 15
-		-- ASCII 185 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001110000", -- |  ###    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000000000", -- |         | 08
-		"000000000", -- |         | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 186 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"001111000", -- |  ####   | 07
-		"000000000", -- |         | 08
-		"011111100", -- | ######  | 09
-		"000000000", -- |         | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 187 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000000000", -- |         | 06
-		"110011000", -- |##  ##   | 07
-		"011001100", -- | ##  ##  | 08
-		"001100110", -- |  ##  ## | 09
-		"011001100", -- | ##  ##  | 10
-		"110011000", -- |##  ##   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 188 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011000000", -- | ##      | 02
-		"111000000", -- |###      | 03
-		"011000110", -- | ##   ## | 04
-		"011001100", -- | ##  ##  | 05
-		"011011000", -- | ## ##   | 06
-		"000110000", -- |   ##    | 07
-		"001101110", -- |  ## ### | 08
-		"011011110", -- | ## #### | 09
-		"110110110", -- |## ## ## | 10
-		"000111110", -- |   ##### | 11
-		"000000110", -- |      ## | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 189 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011000000", -- | ##      | 02
-		"111000000", -- |###      | 03
-		"011000110", -- | ##   ## | 04
-		"011001100", -- | ##  ##  | 05
-		"011011000", -- | ## ##   | 06
-		"000110000", -- |   ##    | 07
-		"001111100", -- |  #####  | 08
-		"011000110", -- | ##   ## | 09
-		"110001100", -- |##   ##  | 10
-		"000011000", -- |    ##   | 11
-		"000011110", -- |    #### | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 190 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"111000000", -- |###      | 02
-		"001100000", -- |  ##     | 03
-		"011000110", -- | ##   ## | 04
-		"001101100", -- |  ## ##  | 05
-		"111011000", -- |### ##   | 06
-		"000110000", -- |   ##    | 07
-		"001101110", -- |  ## ### | 08
-		"011011110", -- | ## #### | 09
-		"110110110", -- |## ## ## | 10
-		"000111110", -- |   ##### | 11
-		"000000110", -- |      ## | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 191 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"000000000", -- |         | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000000000", -- |         | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001100000", -- |  ##     | 11
-		"011001100", -- | ##  ##  | 12
-		"011001100", -- | ##  ##  | 13
-		"001111000", -- |  ####   | 14
-		"000000000", -- |         | 15
-		-- ASCII 192 ---------------
-		"001100000", -- |  ##     | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 193 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 194 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 195 ---------------
-		"001110110", -- |  ### ## | 00
-		"011011100", -- | ## ###  | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 196 ---------------
-		"011001100", -- | ##  ##  | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 197 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"001111000", -- |  ####   | 02
-		"000110000", -- |   ##    | 03
-		"001111000", -- |  ####   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 198 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000011110", -- |    #### | 03
-		"000111000", -- |   ###   | 04
-		"001111000", -- |  ####   | 05
-		"011011000", -- | ## ##   | 06
-		"011011110", -- | ## #### | 07
-		"011111000", -- | #####   | 08
-		"011011000", -- | ## ##   | 09
-		"011011000", -- | ## ##   | 10
-		"011011110", -- | ## #### | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 199 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011000000", -- | ##      | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000110000", -- |   ##    | 12
-		"000011000", -- |    ##   | 13
-		"001110000", -- |  ###    | 14
-		"000000000", -- |         | 15
-		-- ASCII 200 ---------------
-		"001100000", -- |  ##     | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 201 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 202 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 203 ---------------
-		"011001100", -- | ##  ##  | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"011111100", -- | ######  | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011000000", -- | ##      | 06
-		"011111000", -- | #####   | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 204 ---------------
-		"001100000", -- |  ##     | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 205 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 206 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 207 ---------------
-		"011001100", -- | ##  ##  | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 208 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011110000", -- | ####    | 03
-		"011011000", -- | ## ##   | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"111101100", -- |#### ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011011000", -- | ## ##   | 10
-		"011110000", -- | ####    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 209 ---------------
-		"001110110", -- |  ### ## | 00
-		"011011100", -- | ## ###  | 01
-		"000000000", -- |         | 02
-		"011000110", -- | ##   ## | 03
-		"011000110", -- | ##   ## | 04
-		"011100110", -- | ###  ## | 05
-		"011110110", -- | #### ## | 06
-		"011011110", -- | ## #### | 07
-		"011001110", -- | ##  ### | 08
-		"011000110", -- | ##   ## | 09
-		"011000110", -- | ##   ## | 10
-		"011000110", -- | ##   ## | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 210 ---------------
-		"001100000", -- |  ##     | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 211 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 212 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 213 ---------------
-		"001110110", -- |  ### ## | 00
-		"011011100", -- | ## ###  | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 214 ---------------
-		"011001100", -- | ##  ##  | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"001111000", -- |  ####   | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 215 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"010000100", -- | #    #  | 04
-		"011001100", -- | ##  ##  | 05
-		"001111000", -- |  ####   | 06
-		"000110000", -- |   ##    | 07
-		"001111000", -- |  ####   | 08
-		"011001100", -- | ##  ##  | 09
-		"010000100", -- | #    #  | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 216 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001111100", -- |  #####  | 03
-		"011001100", -- | ##  ##  | 04
-		"011011100", -- | ## ###  | 05
-		"011011100", -- | ## ###  | 06
-		"011111100", -- | ######  | 07
-		"011101100", -- | ### ##  | 08
-		"011101100", -- | ### ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 217 ---------------
-		"001100000", -- |  ##     | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 218 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 219 ---------------
-		"001111000", -- |  ####   | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 220 ---------------
-		"011001100", -- | ##  ##  | 00
-		"011001100", -- | ##  ##  | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 221 ---------------
-		"000011000", -- |    ##   | 00
-		"000110000", -- |   ##    | 01
-		"000000000", -- |         | 02
-		"011001100", -- | ##  ##  | 03
-		"011001100", -- | ##  ##  | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"001111000", -- |  ####   | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"000110000", -- |   ##    | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 222 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011111000", -- | #####   | 09
-		"011000000", -- | ##      | 10
-		"011000000", -- | ##      | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 223 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001110000", -- |  ###    | 03
-		"011011000", -- | ## ##   | 04
-		"011011000", -- | ## ##   | 05
-		"011011000", -- | ## ##   | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011011000", -- | ## ##   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 224 ---------------
-		"000000000", -- |         | 00
-		"011100000", -- | ###     | 01
-		"001100000", -- |  ##     | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 225 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 226 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 227 ---------------
-		"000000000", -- |         | 00
-		"011100010", -- | ###   # | 01
-		"110110110", -- |## ## ## | 02
-		"100011100", -- |#   ###  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 228 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 229 ---------------
-		"000000000", -- |         | 00
-		"001111000", -- |  ####   | 01
-		"011001100", -- | ##  ##  | 02
-		"001111000", -- |  ####   | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"000001100", -- |     ##  | 06
-		"000001100", -- |     ##  | 07
-		"001111100", -- |  #####  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 230 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"011011100", -- | ## ###  | 05
-		"000110110", -- |   ## ## | 06
-		"000110110", -- |   ## ## | 07
-		"011111110", -- | ####### | 08
-		"110110000", -- |## ##    | 09
-		"110110000", -- |## ##    | 10
-		"011101110", -- | ### ### | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 231 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011000000", -- | ##      | 07
-		"011000000", -- | ##      | 08
-		"011000000", -- | ##      | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000110000", -- |   ##    | 12
-		"000011000", -- |    ##   | 13
-		"001110000", -- |  ###    | 14
-		"000000000", -- |         | 15
-		-- ASCII 232 ---------------
-		"000000000", -- |         | 00
-		"011100000", -- | ###     | 01
-		"001100000", -- |  ##     | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 233 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 234 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 235 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011111100", -- | ######  | 08
-		"011000000", -- | ##      | 09
-		"011000000", -- | ##      | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 236 ---------------
-		"000000000", -- |         | 00
-		"011100000", -- | ###     | 01
-		"001100000", -- |  ##     | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011110000", -- | ####    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 237 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011110000", -- | ####    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 238 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"011110000", -- | ####    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 239 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"011110000", -- | ####    | 05
-		"000110000", -- |   ##    | 06
-		"000110000", -- |   ##    | 07
-		"000110000", -- |   ##    | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"011111100", -- | ######  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 240 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"001101100", -- |  ## ##  | 03
-		"000110000", -- |   ##    | 04
-		"011011000", -- | ## ##   | 05
-		"000111100", -- |   ####  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 241 ---------------
-		"000000000", -- |         | 00
-		"011100010", -- | ###   # | 01
-		"110110110", -- |## ## ## | 02
-		"100011100", -- |#   ###  | 03
-		"000000000", -- |         | 04
-		"011111000", -- | #####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011001100", -- | ##  ##  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 242 ---------------
-		"000000000", -- |         | 00
-		"011100000", -- | ###     | 01
-		"001100000", -- |  ##     | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 243 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 244 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 245 ---------------
-		"000000000", -- |         | 00
-		"011100010", -- | ###   # | 01
-		"110110110", -- |## ## ## | 02
-		"100011100", -- |#   ###  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 246 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"001111000", -- |  ####   | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 247 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000110000", -- |   ##    | 04
-		"000110000", -- |   ##    | 05
-		"000000000", -- |         | 06
-		"011111100", -- | ######  | 07
-		"000000000", -- |         | 08
-		"000110000", -- |   ##    | 09
-		"000110000", -- |   ##    | 10
-		"000000000", -- |         | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 248 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"000000000", -- |         | 03
-		"000000000", -- |         | 04
-		"001111100", -- |  #####  | 05
-		"011001100", -- | ##  ##  | 06
-		"011011100", -- | ## ###  | 07
-		"011111100", -- | ######  | 08
-		"011101100", -- | ### ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 249 ---------------
-		"000000000", -- |         | 00
-		"011100000", -- | ###     | 01
-		"001100000", -- |  ##     | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 250 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 251 ---------------
-		"000000000", -- |         | 00
-		"000110000", -- |   ##    | 01
-		"001111000", -- |  ####   | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 252 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111100", -- |  #####  | 11
-		"000000000", -- |         | 12
-		"000000000", -- |         | 13
-		"000000000", -- |         | 14
-		"000000000", -- |         | 15
-		-- ASCII 253 ---------------
-		"000000000", -- |         | 00
-		"000011100", -- |    ###  | 01
-		"000011000", -- |    ##   | 02
-		"000110000", -- |   ##    | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000011000", -- |    ##   | 12
-		"000110000", -- |   ##    | 13
-		"111100000", -- |####     | 14
-		"000000000", -- |         | 15
-		-- ASCII 254 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"000000000", -- |         | 02
-		"011000000", -- | ##      | 03
-		"011000000", -- | ##      | 04
-		"011000000", -- | ##      | 05
-		"011111000", -- | #####   | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"011111000", -- | #####   | 11
-		"011000000", -- | ##      | 12
-		"011000000", -- | ##      | 13
-		"011000000", -- | ##      | 14
-		"000000000", -- |         | 15
-		-- ASCII 255 ---------------
-		"000000000", -- |         | 00
-		"000000000", -- |         | 01
-		"011001100", -- | ##  ##  | 02
-		"011001100", -- | ##  ##  | 03
-		"000000000", -- |         | 04
-		"011001100", -- | ##  ##  | 05
-		"011001100", -- | ##  ##  | 06
-		"011001100", -- | ##  ##  | 07
-		"011001100", -- | ##  ##  | 08
-		"011001100", -- | ##  ##  | 09
-		"011001100", -- | ##  ##  | 10
-		"001111000", -- |  ####   | 11
-		"000011000", -- |    ##   | 12
-		"000110000", -- |   ##    | 13
-		"111100000", -- |####     | 14
-		"000000000", -- |         | 15
-		-- Padding ---------------
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000", -- Padded
-		"000000000" -- Padded
-	);
-begin
-
-	p_rom : process
-	begin
-		wait until rising_edge(CLK);
-		DATA <= ROM(to_integer(unsigned(ADDR)));
-	end process;
-
-end RTL;
-
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd
deleted file mode 100644
index d50d36f..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd
+++ /dev/null
@@ -1,4382 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-	port
-	(
-	CLK			: in  std_logic;
-	ADDR		: in  unsigned(11 downto 0);
-	DATA		: out unsigned(15 downto 0)
-	);
-end;
-
-architecture RTL of char_rom is
-
-
-	type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0);
-	constant ROM : ROM_ARRAY :=
-	(
-		-- ASCII 032 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 033 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0000000000000000", -- |                | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 034 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100110000000000", -- |##  ##          | 03
-		"1100110000000000", -- |##  ##          | 04
-		"1100110000000000", -- |##  ##          | 05
-		"1100110000000000", -- |##  ##          | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 035 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011011000000000", -- |  ## ##         | 03
-		"0011011000000000", -- |  ## ##         | 04
-		"0111111100000000", -- | #######        | 05
-		"0011011000000000", -- |  ## ##         | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0110110000000000", -- | ## ##          | 08
-		"0110110000000000", -- | ## ##          | 09
-		"1111111000000000", -- |#######         | 10
-		"0110110000000000", -- | ## ##          | 11
-		"0110110000000000", -- | ## ##          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 036 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011110000000000", -- |  ####          | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110000000000000", -- | ##             | 07
-		"0011110000000000", -- |  ####          | 08
-		"0000011000000000", -- |     ##         | 09
-		"0000011000000000", -- |     ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0001100000000000", -- |   ##           | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 037 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111000001100000", -- | ###     ##     | 03
-		"1101100011000000", -- |## ##   ##      | 04
-		"1101100110000000", -- |## ##  ##       | 05
-		"1101101100000000", -- |## ## ##        | 06
-		"0111011000000000", -- | ### ##         | 07
-		"0000110111000000", -- |    ## ###      | 08
-		"0001101101100000", -- |   ## ## ##     | 09
-		"0011001101100000", -- |  ##  ## ##     | 10
-		"0110001101100000", -- | ##   ## ##     | 11
-		"1100000111000000", -- |##     ###      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 038 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"1111000000000000", -- |####            | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 039 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 040 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000000000000", -- |  ##            | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0011000000000000", -- |  ##            | 15
-		-- ASCII 041 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100000000000000", -- |##              | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"1100000000000000", -- |##              | 15
-		-- ASCII 042 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000000000000", -- |  ##            | 03
-		"1111110000000000", -- |######          | 04
-		"0011000000000000", -- |  ##            | 05
-		"0111100000000000", -- | ####           | 06
-		"0100100000000000", -- | #  #           | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 043 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0001100000000000", -- |   ##           | 05
-		"0001100000000000", -- |   ##           | 06
-		"0001100000000000", -- |   ##           | 07
-		"0111111000000000", -- | ######         | 08
-		"0001100000000000", -- |   ##           | 09
-		"0001100000000000", -- |   ##           | 10
-		"0001100000000000", -- |   ##           | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 044 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"1100000000000000", -- |##              | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 045 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"1111000000000000", -- |####            | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 046 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 047 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000000000000", -- |  ##            | 03
-		"0011000000000000", -- |  ##            | 04
-		"0011000000000000", -- |  ##            | 05
-		"0011000000000000", -- |  ##            | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"1100000000000000", -- |##              | 11
-		"1100000000000000", -- |##              | 12
-		"1100000000000000", -- |##              | 13
-		"1100000000000000", -- |##              | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 048 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 049 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0111100000000000", -- | ####           | 04
-		"0001100000000000", -- |   ##           | 05
-		"0001100000000000", -- |   ##           | 06
-		"0001100000000000", -- |   ##           | 07
-		"0001100000000000", -- |   ##           | 08
-		"0001100000000000", -- |   ##           | 09
-		"0001100000000000", -- |   ##           | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 050 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0000011000000000", -- |     ##         | 06
-		"0000110000000000", -- |    ##          | 07
-		"0001100000000000", -- |   ##           | 08
-		"0011000000000000", -- |  ##            | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 051 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000011000000000", -- |     ##         | 05
-		"0000011000000000", -- |     ##         | 06
-		"0001110000000000", -- |   ###          | 07
-		"0000011000000000", -- |     ##         | 08
-		"0000011000000000", -- |     ##         | 09
-		"0000011000000000", -- |     ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 052 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000011000000000", -- |     ##         | 03
-		"0000111000000000", -- |    ###         | 04
-		"0001111000000000", -- |   ####         | 05
-		"0001111000000000", -- |   ####         | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0011011000000000", -- |  ## ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"0000011000000000", -- |     ##         | 11
-		"0000011000000000", -- |     ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 053 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111000000000", -- | ######         | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111110000000000", -- | #####          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0000011000000000", -- |     ##         | 09
-		"0000011000000000", -- |     ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 054 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111110000000000", -- | #####          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 055 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111000000000", -- | ######         | 03
-		"0000011000000000", -- |     ##         | 04
-		"0000110000000000", -- |    ##          | 05
-		"0000110000000000", -- |    ##          | 06
-		"0001100000000000", -- |   ##           | 07
-		"0001100000000000", -- |   ##           | 08
-		"0001100000000000", -- |   ##           | 09
-		"0011000000000000", -- |  ##            | 10
-		"0011000000000000", -- |  ##            | 11
-		"0011000000000000", -- |  ##            | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 056 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0011110000000000", -- |  ####          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 057 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0011111000000000", -- |  #####         | 08
-		"0000011000000000", -- |     ##         | 09
-		"0000011000000000", -- |     ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 058 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 059 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"1100000000000000", -- |##              | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 060 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000011000000000", -- |     ##         | 04
-		"0000110000000000", -- |    ##          | 05
-		"0001100000000000", -- |   ##           | 06
-		"0011000000000000", -- |  ##            | 07
-		"0110000000000000", -- | ##             | 08
-		"0011000000000000", -- |  ##            | 09
-		"0001100000000000", -- |   ##           | 10
-		"0000110000000000", -- |    ##          | 11
-		"0000011000000000", -- |     ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 061 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111111000000000", -- | ######         | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0111111000000000", -- | ######         | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 062 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0011000000000000", -- |  ##            | 05
-		"0001100000000000", -- |   ##           | 06
-		"0000110000000000", -- |    ##          | 07
-		"0000011000000000", -- |     ##         | 08
-		"0000110000000000", -- |    ##          | 09
-		"0001100000000000", -- |   ##           | 10
-		"0011000000000000", -- |  ##            | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 063 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0000011000000000", -- |     ##         | 06
-		"0000110000000000", -- |    ##          | 07
-		"0001100000000000", -- |   ##           | 08
-		"0001100000000000", -- |   ##           | 09
-		"0000000000000000", -- |                | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 064 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000011110000000", -- |     ####       | 02
-		"0001110011100000", -- |   ###  ###     | 03
-		"0011000000110000", -- |  ##      ##    | 04
-		"0011001110110000", -- |  ##  ### ##    | 05
-		"0110011011011000", -- | ##  ## ## ##   | 06
-		"0110011011011000", -- | ##  ## ## ##   | 07
-		"0110110011011000", -- | ## ##  ## ##   | 08
-		"0110110110011000", -- | ## ## ##  ##   | 09
-		"0110110110011000", -- | ## ## ##  ##   | 10
-		"0011011011110000", -- |  ## ## ####    | 11
-		"0011000000000000", -- |  ##            | 12
-		"0001110001110000", -- |   ###   ###    | 13
-		"0000011111000000", -- |     #####      | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 065 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 066 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0111111100000000", -- | #######        | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 067 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000100000000", -- | ##    #        | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000100000000", -- | ##    #        | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 068 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111000000000", -- | ######         | 03
-		"0110001100000000", -- | ##   ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0110001100000000", -- | ##   ##        | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 069 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 070 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 071 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111100000000", -- |   #####        | 03
-		"0011000110000000", -- |  ##   ##       | 04
-		"0110000010000000", -- | ##     #       | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110011110000000", -- | ##  ####       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011000110000000", -- |  ##   ##       | 11
-		"0001111010000000", -- |   #### #       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 072 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0111111110000000", -- | ########       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"0110000110000000", -- | ##    ##       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 073 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 074 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000110000000000", -- |    ##          | 03
-		"0000110000000000", -- |    ##          | 04
-		"0000110000000000", -- |    ##          | 05
-		"0000110000000000", -- |    ##          | 06
-		"0000110000000000", -- |    ##          | 07
-		"0000110000000000", -- |    ##          | 08
-		"0000110000000000", -- |    ##          | 09
-		"1100110000000000", -- |##  ##          | 10
-		"1100110000000000", -- |##  ##          | 11
-		"0111100000000000", -- | ####           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 075 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110001100000000", -- | ##   ##        | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110110000000000", -- | ## ##          | 05
-		"0111100000000000", -- | ####           | 06
-		"0111000000000000", -- | ###            | 07
-		"0111100000000000", -- | ####           | 08
-		"0110110000000000", -- | ## ##          | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110001100000000", -- | ##   ##        | 11
-		"0110000110000000", -- | ##    ##       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 076 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 077 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000001100000", -- | ##      ##     | 03
-		"0110000001100000", -- | ##      ##     | 04
-		"0111000011100000", -- | ###    ###     | 05
-		"0111000011100000", -- | ###    ###     | 06
-		"0111100111100000", -- | ####  ####     | 07
-		"0111100111100000", -- | ####  ####     | 08
-		"0110111101100000", -- | ## #### ##     | 09
-		"0110111101100000", -- | ## #### ##     | 10
-		"0110011001100000", -- | ##  ##  ##     | 11
-		"0110011001100000", -- | ##  ##  ##     | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 078 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0111000110000000", -- | ###   ##       | 04
-		"0111100110000000", -- | ####  ##       | 05
-		"0111100110000000", -- | ####  ##       | 06
-		"0110110110000000", -- | ## ## ##       | 07
-		"0110110110000000", -- | ## ## ##       | 08
-		"0110011110000000", -- | ##  ####       | 09
-		"0110011110000000", -- | ##  ####       | 10
-		"0110001110000000", -- | ##   ###       | 11
-		"0110000110000000", -- | ##    ##       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 079 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 080 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0111111100000000", -- | #######        | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 081 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110011110000000", -- | ##  ####       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111110000000", -- |   ######       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 082 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0111111100000000", -- | #######        | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"0110000011000000", -- | ##     ##      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 083 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011111000000000", -- |  #####         | 03
-		"0110001100000000", -- | ##   ##        | 04
-		"0110001100000000", -- | ##   ##        | 05
-		"0110000000000000", -- | ##             | 06
-		"0011100000000000", -- |  ###           | 07
-		"0000111000000000", -- |    ###         | 08
-		"0000001100000000", -- |      ##        | 09
-		"0110001100000000", -- | ##   ##        | 10
-		"0110001100000000", -- | ##   ##        | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 084 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1111111100000000", -- |########        | 03
-		"0001100000000000", -- |   ##           | 04
-		"0001100000000000", -- |   ##           | 05
-		"0001100000000000", -- |   ##           | 06
-		"0001100000000000", -- |   ##           | 07
-		"0001100000000000", -- |   ##           | 08
-		"0001100000000000", -- |   ##           | 09
-		"0001100000000000", -- |   ##           | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 085 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 086 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100001100000000", -- |##    ##        | 03
-		"1100001100000000", -- |##    ##        | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0010010000000000", -- |  #  #          | 08
-		"0011110000000000", -- |  ####          | 09
-		"0011110000000000", -- |  ####          | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 087 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100001100001100", -- |##    ##    ##  | 03
-		"1100001100001100", -- |##    ##    ##  | 04
-		"1100001100001100", -- |##    ##    ##  | 05
-		"0110011110011000", -- | ##  ####  ##   | 06
-		"0110011110011000", -- | ##  ####  ##   | 07
-		"0011010010110000", -- |  ## #  # ##    | 08
-		"0011110011110000", -- |  ####  ####    | 09
-		"0001100001100000", -- |   ##    ##     | 10
-		"0001100001100000", -- |   ##    ##     | 11
-		"0001100001100000", -- |   ##    ##     | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 088 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100000110000000", -- |##     ##       | 03
-		"1100000110000000", -- |##     ##       | 04
-		"0110001100000000", -- | ##   ##        | 05
-		"0011011000000000", -- |  ## ##         | 06
-		"0001110000000000", -- |   ###          | 07
-		"0001110000000000", -- |   ###          | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110001100000000", -- | ##   ##        | 10
-		"1100000110000000", -- |##     ##       | 11
-		"1100000110000000", -- |##     ##       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 089 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100000011000000", -- |##      ##      | 03
-		"1100000011000000", -- |##      ##      | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0011001100000000", -- |  ##  ##        | 06
-		"0001111000000000", -- |   ####         | 07
-		"0000110000000000", -- |    ##          | 08
-		"0000110000000000", -- |    ##          | 09
-		"0000110000000000", -- |    ##          | 10
-		"0000110000000000", -- |    ##          | 11
-		"0000110000000000", -- |    ##          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 090 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1111111110000000", -- |#########       | 03
-		"0000000110000000", -- |       ##       | 04
-		"0000001100000000", -- |      ##        | 05
-		"0000011000000000", -- |     ##         | 06
-		"0000110000000000", -- |    ##          | 07
-		"0001100000000000", -- |   ##           | 08
-		"0011000000000000", -- |  ##            | 09
-		"0110000000000000", -- | ##             | 10
-		"1100000000000000", -- |##              | 11
-		"1111111110000000", -- |#########       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 091 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111000000000000", -- | ###            | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0111000000000000", -- | ###            | 15
-		-- ASCII 092 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100000000000000", -- |##              | 03
-		"1100000000000000", -- |##              | 04
-		"1100000000000000", -- |##              | 05
-		"1100000000000000", -- |##              | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0011000000000000", -- |  ##            | 11
-		"0011000000000000", -- |  ##            | 12
-		"0011000000000000", -- |  ##            | 13
-		"0011000000000000", -- |  ##            | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 093 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1110000000000000", -- |###             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"1110000000000000", -- |###             | 15
-		-- ASCII 094 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0010000000000000", -- |  #             | 03
-		"0111000000000000", -- | ###            | 04
-		"1101100000000000", -- |## ##           | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 095 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"1111111100000000", -- |########        | 15
-		-- ASCII 096 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0111000000000000", -- | ###            | 02
-		"0011000000000000", -- |  ##            | 03
-		"0001100000000000", -- |   ##           | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 097 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 098 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0111110000000000", -- | #####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 099 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 100 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000011000000000", -- |     ##         | 03
-		"0000011000000000", -- |     ##         | 04
-		"0000011000000000", -- |     ##         | 05
-		"0011111000000000", -- |  #####         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 101 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0111111000000000", -- | ######         | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 102 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000000000000", -- |  ##            | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"1111000000000000", -- |####            | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 103 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011111000000000", -- |  #####         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000011000000000", -- |     ##         | 13
-		"0110011000000000", -- | ##  ##         | 14
-		"0011110000000000", -- |  ####          | 15
-		-- ASCII 104 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0110011000000000", -- | ##  ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 105 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 106 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"1100000000000000", -- |##              | 15
-		-- ASCII 107 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110110000000000", -- | ## ##          | 07
-		"0111100000000000", -- | ####           | 08
-		"0111000000000000", -- | ###            | 09
-		"0111100000000000", -- | ####           | 10
-		"0110110000000000", -- | ## ##          | 11
-		"0110011000000000", -- | ##  ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 108 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 109 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111111111000000", -- | #########      | 06
-		"0110011001100000", -- | ##  ##  ##     | 07
-		"0110011001100000", -- | ##  ##  ##     | 08
-		"0110011001100000", -- | ##  ##  ##     | 09
-		"0110011001100000", -- | ##  ##  ##     | 10
-		"0110011001100000", -- | ##  ##  ##     | 11
-		"0110011001100000", -- | ##  ##  ##     | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 110 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0110011000000000", -- | ##  ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 111 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 112 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0111110000000000", -- | #####          | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 113 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011111000000000", -- |  #####         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000011000000000", -- |     ##         | 13
-		"0000011000000000", -- |     ##         | 14
-		"0000011000000000", -- |     ##         | 15
-		-- ASCII 114 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111100000000000", -- | ####           | 06
-		"0111000000000000", -- | ###            | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 115 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110000000000000", -- | ##             | 08
-		"0011110000000000", -- |  ####          | 09
-		"0000011000000000", -- |     ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 116 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"1111000000000000", -- |####            | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0011000000000000", -- |  ##            | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 117 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 118 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"1100001100000000", -- |##    ##        | 06
-		"1100001100000000", -- |##    ##        | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0011110000000000", -- |  ####          | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 119 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"1100000011000000", -- |##      ##      | 06
-		"1100110011000000", -- |##  ##  ##      | 07
-		"0110110110000000", -- | ## ## ##       | 08
-		"0110110110000000", -- | ## ## ##       | 09
-		"0111111110000000", -- | ########       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0011001100000000", -- |  ##  ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 120 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"1100001100000000", -- |##    ##        | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0011110000000000", -- |  ####          | 08
-		"0001100000000000", -- |   ##           | 09
-		"0011110000000000", -- |  ####          | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 121 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"1100001100000000", -- |##    ##        | 06
-		"1100001100000000", -- |##    ##        | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0011110000000000", -- |  ####          | 10
-		"0011110000000000", -- |  ####          | 11
-		"0001100000000000", -- |   ##           | 12
-		"0001100000000000", -- |   ##           | 13
-		"0011000000000000", -- |  ##            | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 122 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0111111000000000", -- | ######         | 06
-		"0000011000000000", -- |     ##         | 07
-		"0000110000000000", -- |    ##          | 08
-		"0001100000000000", -- |   ##           | 09
-		"0011000000000000", -- |  ##            | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 123 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0011000000000000", -- |  ##            | 05
-		"0011000000000000", -- |  ##            | 06
-		"0011000000000000", -- |  ##            | 07
-		"0011000000000000", -- |  ##            | 08
-		"0110000000000000", -- | ##             | 09
-		"0011000000000000", -- |  ##            | 10
-		"0011000000000000", -- |  ##            | 11
-		"0011000000000000", -- |  ##            | 12
-		"0011000000000000", -- |  ##            | 13
-		"0011000000000000", -- |  ##            | 14
-		"0001100000000000", -- |   ##           | 15
-		-- ASCII 124 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 125 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100000000000000", -- |##              | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0011000000000000", -- |  ##            | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"1100000000000000", -- |##              | 15
-		-- ASCII 126 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1110100000000000", -- |### #           | 03
-		"1011100000000000", -- |# ###           | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 127 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 128 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 129 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 130 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 131 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 132 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 133 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 134 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 135 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 136 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 137 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 138 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 139 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 140 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 141 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 142 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 143 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 144 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 145 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011000000000000", -- |  ##            | 02
-		"0110000000000000", -- | ##             | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 146 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0110000000000000", -- | ##             | 02
-		"1100000000000000", -- |##              | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 147 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 148 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 149 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 150 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 151 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 152 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 153 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 154 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 155 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 156 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 157 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 158 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 159 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 160 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 161 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 162 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000110000000000", -- |    ##          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110111000000000", -- | ## ###         | 07
-		"0110100000000000", -- | ## #           | 08
-		"0110100000000000", -- | ## #           | 09
-		"0111000000000000", -- | ###            | 10
-		"0111011000000000", -- | ### ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0011000000000000", -- |  ##            | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 163 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011100000000000", -- |  ###           | 03
-		"0110110000000000", -- | ## ##          | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0011000000000000", -- |  ##            | 07
-		"0111100000000000", -- | ####           | 08
-		"0011000000000000", -- |  ##            | 09
-		"0011000000000000", -- |  ##            | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0111110000000000", -- | #####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 164 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0011110000000000", -- |  ####          | 04
-		"0010010000000000", -- |  #  #          | 05
-		"0010010000000000", -- |  #  #          | 06
-		"0011110000000000", -- |  ####          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 165 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1100001100000000", -- |##    ##        | 03
-		"1100001100000000", -- |##    ##        | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"1111111100000000", -- |########        | 07
-		"0001100000000000", -- |   ##           | 08
-		"1111111100000000", -- |########        | 09
-		"0001100000000000", -- |   ##           | 10
-		"0001100000000000", -- |   ##           | 11
-		"0001100000000000", -- |   ##           | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 166 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0000000000000000", -- |                | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 167 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0011100000000000", -- |  ###           | 05
-		"0011100000000000", -- |  ###           | 06
-		"0110110000000000", -- | ## ##          | 07
-		"0011011000000000", -- |  ## ##         | 08
-		"0001110000000000", -- |   ###          | 09
-		"0001110000000000", -- |   ###          | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 168 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1101100000000000", -- |## ##           | 03
-		"1101100000000000", -- |## ##           | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 169 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011111100000000", -- |  ######        | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"1100110011000000", -- |##  ##  ##      | 05
-		"1101001011000000", -- |## #  # ##      | 06
-		"1101000011000000", -- |## #    ##      | 07
-		"1101000011000000", -- |## #    ##      | 08
-		"1101001011000000", -- |## #  # ##      | 09
-		"1100110011000000", -- |##  ##  ##      | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"0011111100000000", -- |  ######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 170 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0010000000000000", -- |  #             | 03
-		"0001000000000000", -- |   #            | 04
-		"0011000000000000", -- |  ##            | 05
-		"0101000000000000", -- | # #            | 06
-		"0011000000000000", -- |  ##            | 07
-		"0000000000000000", -- |                | 08
-		"0111000000000000", -- | ###            | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 171 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0110110000000000", -- | ## ##          | 08
-		"1101100000000000", -- |## ##           | 09
-		"0110110000000000", -- | ## ##          | 10
-		"0011011000000000", -- |  ## ##         | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 172 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0111111000000000", -- | ######         | 07
-		"0000011000000000", -- |     ##         | 08
-		"0000011000000000", -- |     ##         | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 173 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"1111000000000000", -- |####            | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 174 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011111100000000", -- |  ######        | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"1101110011000000", -- |## ###  ##      | 05
-		"1101001011000000", -- |## #  # ##      | 06
-		"1101001011000000", -- |## #  # ##      | 07
-		"1101110011000000", -- |## ###  ##      | 08
-		"1101010011000000", -- |## # #  ##      | 09
-		"1101001011000000", -- |## #  # ##      | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"0011111100000000", -- |  ######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 175 ---------------
-		"0000000000000000", -- |                | 00
-		"1111111100000000", -- |########        | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 176 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111000000000000", -- | ###            | 03
-		"0101000000000000", -- | # #            | 04
-		"0101000000000000", -- | # #            | 05
-		"0111000000000000", -- | ###            | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 177 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0001100000000000", -- |   ##           | 06
-		"0001100000000000", -- |   ##           | 07
-		"0111111000000000", -- | ######         | 08
-		"0001100000000000", -- |   ##           | 09
-		"0001100000000000", -- |   ##           | 10
-		"0000000000000000", -- |                | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 178 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"1011000000000000", -- |# ##            | 04
-		"0011000000000000", -- |  ##            | 05
-		"0110000000000000", -- | ##             | 06
-		"1111000000000000", -- |####            | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 179 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"1011000000000000", -- |# ##            | 04
-		"0110000000000000", -- | ##             | 05
-		"1011000000000000", -- |# ##            | 06
-		"0110000000000000", -- | ##             | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 180 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011100000000000", -- |  ###           | 02
-		"0011000000000000", -- |  ##            | 03
-		"0110000000000000", -- | ##             | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 181 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0111111100000000", -- | #######        | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 182 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0111110000000000", -- | #####          | 04
-		"0111110000000000", -- | #####          | 05
-		"0111110000000000", -- | #####          | 06
-		"0111110000000000", -- | #####          | 07
-		"0011110000000000", -- |  ####          | 08
-		"0000110000000000", -- |    ##          | 09
-		"0000110000000000", -- |    ##          | 10
-		"0000110000000000", -- |    ##          | 11
-		"0000110000000000", -- |    ##          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 183 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 184 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0011000000000000", -- |  ##            | 13
-		"0001100000000000", -- |   ##           | 14
-		"0111000000000000", -- | ###            | 15
-		-- ASCII 185 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"1110000000000000", -- |###             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 186 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111000000000000", -- | ###            | 03
-		"0101000000000000", -- | # #            | 04
-		"0101000000000000", -- | # #            | 05
-		"0101000000000000", -- | # #            | 06
-		"0111000000000000", -- | ###            | 07
-		"0000000000000000", -- |                | 08
-		"0111000000000000", -- | ###            | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 187 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"1101100000000000", -- |## ##           | 07
-		"0110110000000000", -- | ## ##          | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110110000000000", -- | ## ##          | 10
-		"1101100000000000", -- |## ##           | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 188 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000001100000", -- |  ##     ##     | 03
-		"0111000011000000", -- | ###    ##      | 04
-		"0011000110000000", -- |  ##   ##       | 05
-		"0011001100000000", -- |  ##  ##        | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0000110011000000", -- |    ##  ##      | 08
-		"0001100111000000", -- |   ##  ###      | 09
-		"0011001101000000", -- |  ##  ## #      | 10
-		"0110001111000000", -- | ##   ####      | 11
-		"1100000011000000", -- |##      ##      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 189 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000001100000", -- |  ##     ##     | 03
-		"0111000011000000", -- | ###    ##      | 04
-		"0011000110000000", -- |  ##   ##       | 05
-		"0011001100000000", -- |  ##  ##        | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0000110110000000", -- |    ## ##       | 08
-		"0001101011000000", -- |   ## # ##      | 09
-		"0011000011000000", -- |  ##    ##      | 10
-		"0110000110000000", -- | ##    ##       | 11
-		"1100001111000000", -- |##    ####      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 190 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011000001100000", -- |  ##     ##     | 03
-		"0101100011000000", -- | # ##   ##      | 04
-		"0011000110000000", -- |  ##   ##       | 05
-		"0101101100000000", -- | # ## ##        | 06
-		"0011011000000000", -- |  ## ##         | 07
-		"0000110011000000", -- |    ##  ##      | 08
-		"0001100111000000", -- |   ##  ###      | 09
-		"0011001101000000", -- |  ##  ## #      | 10
-		"0110001111000000", -- | ##   ####      | 11
-		"1100000011000000", -- |##      ##      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 191 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0000000000000000", -- |                | 05
-		"0001100000000000", -- |   ##           | 06
-		"0001100000000000", -- |   ##           | 07
-		"0011000000000000", -- |  ##            | 08
-		"0110000000000000", -- | ##             | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 192 ---------------
-		"0011100000000000", -- |  ###           | 00
-		"0001100000000000", -- |   ##           | 01
-		"0000110000000000", -- |    ##          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 193 ---------------
-		"0001110000000000", -- |   ###          | 00
-		"0001100000000000", -- |   ##           | 01
-		"0011000000000000", -- |  ##            | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 194 ---------------
-		"0001100000000000", -- |   ##           | 00
-		"0011110000000000", -- |  ####          | 01
-		"0110011000000000", -- | ##  ##         | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 195 ---------------
-		"0111101000000000", -- | #### #         | 00
-		"0101111000000000", -- | # ####         | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 196 ---------------
-		"0110011000000000", -- | ##  ##         | 00
-		"0110011000000000", -- | ##  ##         | 01
-		"0000000000000000", -- |                | 02
-		"0001100000000000", -- |   ##           | 03
-		"0001100000000000", -- |   ##           | 04
-		"0011110000000000", -- |  ####          | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 197 ---------------
-		"0001100000000000", -- |   ##           | 00
-		"0011110000000000", -- |  ####          | 01
-		"0001100000000000", -- |   ##           | 02
-		"0000000000000000", -- |                | 03
-		"0001100000000000", -- |   ##           | 04
-		"0001100000000000", -- |   ##           | 05
-		"0011110000000000", -- |  ####          | 06
-		"0010010000000000", -- |  #  #          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100001100000000", -- |##    ##        | 11
-		"1100001100000000", -- |##    ##        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 198 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111111110000", -- |   #########    | 03
-		"0001111000000000", -- |   ####         | 04
-		"0011011000000000", -- |  ## ##         | 05
-		"0011011000000000", -- |  ## ##         | 06
-		"0011011111100000", -- |  ## ######     | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111111000000000", -- | ######         | 10
-		"1100011000000000", -- |##   ##         | 11
-		"1100011111110000", -- |##   #######    | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 199 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000100000000", -- | ##    #        | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000100000000", -- | ##    #        | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000110000000000", -- |    ##          | 13
-		"0000011000000000", -- |     ##         | 14
-		"0001110000000000", -- |   ###          | 15
-		-- ASCII 200 ---------------
-		"0001110000000000", -- |   ###          | 00
-		"0000110000000000", -- |    ##          | 01
-		"0000011000000000", -- |     ##         | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 201 ---------------
-		"0000111000000000", -- |    ###         | 00
-		"0000110000000000", -- |    ##          | 01
-		"0001100000000000", -- |   ##           | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 202 ---------------
-		"0000110000000000", -- |    ##          | 00
-		"0001111000000000", -- |   ####         | 01
-		"0011001100000000", -- |  ##  ##        | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 203 ---------------
-		"0011001100000000", -- |  ##  ##        | 00
-		"0011001100000000", -- |  ##  ##        | 01
-		"0000000000000000", -- |                | 02
-		"0111111100000000", -- | #######        | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0111111000000000", -- | ######         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0111111100000000", -- | #######        | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 204 ---------------
-		"1100000000000000", -- |##              | 00
-		"0110000000000000", -- | ##             | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 205 ---------------
-		"0011000000000000", -- |  ##            | 00
-		"0110000000000000", -- | ##             | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 206 ---------------
-		"0110000000000000", -- | ##             | 00
-		"1001000000000000", -- |#  #            | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 207 ---------------
-		"1001000000000000", -- |#  #            | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 208 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111111000000000", -- | ######         | 03
-		"0110001100000000", -- | ##   ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"1111100110000000", -- |#####  ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0110001100000000", -- | ##   ##        | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 209 ---------------
-		"0011110100000000", -- |  #### #        | 00
-		"0010111100000000", -- |  # ####        | 01
-		"0000000000000000", -- |                | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0111000110000000", -- | ###   ##       | 04
-		"0111100110000000", -- | ####  ##       | 05
-		"0111100110000000", -- | ####  ##       | 06
-		"0110110110000000", -- | ## ## ##       | 07
-		"0110110110000000", -- | ## ## ##       | 08
-		"0110011110000000", -- | ##  ####       | 09
-		"0110011110000000", -- | ##  ####       | 10
-		"0110001110000000", -- | ##   ###       | 11
-		"0110000110000000", -- | ##    ##       | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 210 ---------------
-		"0001110000000000", -- |   ###          | 00
-		"0000110000000000", -- |    ##          | 01
-		"0000011000000000", -- |     ##         | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 211 ---------------
-		"0000111000000000", -- |    ###         | 00
-		"0000110000000000", -- |    ##          | 01
-		"0001100000000000", -- |   ##           | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 212 ---------------
-		"0000110000000000", -- |    ##          | 00
-		"0001111000000000", -- |   ####         | 01
-		"0011001100000000", -- |  ##  ##        | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 213 ---------------
-		"0011110100000000", -- |  #### #        | 00
-		"0010111100000000", -- |  # ####        | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 214 ---------------
-		"0011001100000000", -- |  ##  ##        | 00
-		"0011001100000000", -- |  ##  ##        | 01
-		"0000000000000000", -- |                | 02
-		"0001111000000000", -- |   ####         | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 215 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0011110000000000", -- |  ####          | 08
-		"0001100000000000", -- |   ##           | 09
-		"0011110000000000", -- |  ####          | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 216 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0001111110000000", -- |   ######       | 03
-		"0011001100000000", -- |  ##  ##        | 04
-		"0110001110000000", -- | ##   ###       | 05
-		"0110011110000000", -- | ##  ####       | 06
-		"0110110110000000", -- | ## ## ##       | 07
-		"0110110110000000", -- | ## ## ##       | 08
-		"0111100110000000", -- | ####  ##       | 09
-		"0111000110000000", -- | ###   ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0111111000000000", -- | ######         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 217 ---------------
-		"0001110000000000", -- |   ###          | 00
-		"0000110000000000", -- |    ##          | 01
-		"0000011000000000", -- |     ##         | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 218 ---------------
-		"0000111000000000", -- |    ###         | 00
-		"0000110000000000", -- |    ##          | 01
-		"0001100000000000", -- |   ##           | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 219 ---------------
-		"0000110000000000", -- |    ##          | 00
-		"0001111000000000", -- |   ####         | 01
-		"0011001100000000", -- |  ##  ##        | 02
-		"0000000000000000", -- |                | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 220 ---------------
-		"0011001100000000", -- |  ##  ##        | 00
-		"0011001100000000", -- |  ##  ##        | 01
-		"0000000000000000", -- |                | 02
-		"0110000110000000", -- | ##    ##       | 03
-		"0110000110000000", -- | ##    ##       | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0110000110000000", -- | ##    ##       | 06
-		"0110000110000000", -- | ##    ##       | 07
-		"0110000110000000", -- | ##    ##       | 08
-		"0110000110000000", -- | ##    ##       | 09
-		"0110000110000000", -- | ##    ##       | 10
-		"0011001100000000", -- |  ##  ##        | 11
-		"0001111000000000", -- |   ####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 221 ---------------
-		"0000111000000000", -- |    ###         | 00
-		"0000110000000000", -- |    ##          | 01
-		"0001100000000000", -- |   ##           | 02
-		"1100000011000000", -- |##      ##      | 03
-		"1100000011000000", -- |##      ##      | 04
-		"0110000110000000", -- | ##    ##       | 05
-		"0011001100000000", -- |  ##  ##        | 06
-		"0001111000000000", -- |   ####         | 07
-		"0000110000000000", -- |    ##          | 08
-		"0000110000000000", -- |    ##          | 09
-		"0000110000000000", -- |    ##          | 10
-		"0000110000000000", -- |    ##          | 11
-		"0000110000000000", -- |    ##          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 222 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0111111000000000", -- | ######         | 05
-		"0110001100000000", -- | ##   ##        | 06
-		"0110001100000000", -- | ##   ##        | 07
-		"0110001100000000", -- | ##   ##        | 08
-		"0110001100000000", -- | ##   ##        | 09
-		"0111111000000000", -- | ######         | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 223 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0110011000000000", -- | ##  ##         | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110110000000000", -- | ## ##          | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0110110000000000", -- | ## ##          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 224 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011100000000000", -- |  ###           | 02
-		"0001100000000000", -- |   ##           | 03
-		"0000110000000000", -- |    ##          | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 225 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001110000000000", -- |   ###          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 226 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001100000000000", -- |   ##           | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 227 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111101000000000", -- | #### #         | 03
-		"0101111000000000", -- | # ####         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 228 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 229 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001100000000000", -- |   ##           | 02
-		"0011110000000000", -- |  ####          | 03
-		"0001100000000000", -- |   ##           | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0001111000000000", -- |   ####         | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 230 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011111111000000", -- |  ########      | 06
-		"0110011001100000", -- | ##  ##  ##     | 07
-		"0001111111100000", -- |   ########     | 08
-		"0011011000000000", -- |  ## ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011001100000", -- | ##  ##  ##     | 11
-		"0011111111000000", -- |  ########      | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 231 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0001100000000000", -- |   ##           | 13
-		"0000110000000000", -- |    ##          | 14
-		"0011100000000000", -- |  ###           | 15
-		-- ASCII 232 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011100000000000", -- |  ###           | 02
-		"0001100000000000", -- |   ##           | 03
-		"0000110000000000", -- |    ##          | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0111111000000000", -- | ######         | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 233 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001110000000000", -- |   ###          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0111111000000000", -- | ######         | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 234 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001100000000000", -- |   ##           | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0111111000000000", -- | ######         | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 235 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0111111000000000", -- | ######         | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 236 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"1110000000000000", -- |###             | 02
-		"0110000000000000", -- | ##             | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 237 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0111000000000000", -- | ###            | 02
-		"0110000000000000", -- | ##             | 03
-		"1100000000000000", -- |##              | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 238 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0110000000000000", -- | ##             | 02
-		"1111000000000000", -- |####            | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 239 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"1001000000000000", -- |#  #            | 03
-		"1001000000000000", -- |#  #            | 04
-		"0000000000000000", -- |                | 05
-		"0110000000000000", -- | ##             | 06
-		"0110000000000000", -- | ##             | 07
-		"0110000000000000", -- | ##             | 08
-		"0110000000000000", -- | ##             | 09
-		"0110000000000000", -- | ##             | 10
-		"0110000000000000", -- | ##             | 11
-		"0110000000000000", -- | ##             | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 240 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111011000000000", -- | ### ##         | 03
-		"0001100000000000", -- |   ##           | 04
-		"0110110000000000", -- | ## ##          | 05
-		"0000110000000000", -- |    ##          | 06
-		"0011111000000000", -- |  #####         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 241 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111101000000000", -- | #### #         | 03
-		"0101111000000000", -- | # ####         | 04
-		"0000000000000000", -- |                | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0110011000000000", -- | ##  ##         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 242 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011100000000000", -- |  ###           | 02
-		"0001100000000000", -- |   ##           | 03
-		"0000110000000000", -- |    ##          | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 243 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001110000000000", -- |   ###          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 244 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001100000000000", -- |   ##           | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 245 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0111101000000000", -- | #### #         | 03
-		"0101111000000000", -- | # ####         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 246 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0011110000000000", -- |  ####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011110000000000", -- |  ####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 247 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0011000000000000", -- |  ##            | 05
-		"0011000000000000", -- |  ##            | 06
-		"0000000000000000", -- |                | 07
-		"0111100000000000", -- | ####           | 08
-		"0000000000000000", -- |                | 09
-		"0011000000000000", -- |  ##            | 10
-		"0011000000000000", -- |  ##            | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 248 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0011111000000000", -- |  #####         | 06
-		"0110111000000000", -- | ## ###         | 07
-		"0110111000000000", -- | ## ###         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0111011000000000", -- | ### ##         | 10
-		"0111011000000000", -- | ### ##         | 11
-		"0111110000000000", -- | #####          | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 249 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0011100000000000", -- |  ###           | 02
-		"0001100000000000", -- |   ##           | 03
-		"0000110000000000", -- |    ##          | 04
-		"0000000000000000", -- |                | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 250 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001110000000000", -- |   ###          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 251 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001100000000000", -- |   ##           | 02
-		"0011110000000000", -- |  ####          | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 252 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"0110011000000000", -- | ##  ##         | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0011111000000000", -- |  #####         | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 253 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0001110000000000", -- |   ###          | 02
-		"0001100000000000", -- |   ##           | 03
-		"0011000000000000", -- |  ##            | 04
-		"0000000000000000", -- |                | 05
-		"1100001100000000", -- |##    ##        | 06
-		"1100001100000000", -- |##    ##        | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0011110000000000", -- |  ####          | 10
-		"0011110000000000", -- |  ####          | 11
-		"0001100000000000", -- |   ##           | 12
-		"0001100000000000", -- |   ##           | 13
-		"0011000000000000", -- |  ##            | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 254 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110000000000000", -- | ##             | 03
-		"0110000000000000", -- | ##             | 04
-		"0110000000000000", -- | ##             | 05
-		"0111110000000000", -- | #####          | 06
-		"0110011000000000", -- | ##  ##         | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0110011000000000", -- | ##  ##         | 10
-		"0110011000000000", -- | ##  ##         | 11
-		"0111110000000000", -- | #####          | 12
-		"0110000000000000", -- | ##             | 13
-		"0110000000000000", -- | ##             | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 255 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0110011000000000", -- | ##  ##         | 03
-		"0110011000000000", -- | ##  ##         | 04
-		"0000000000000000", -- |                | 05
-		"1100001100000000", -- |##    ##        | 06
-		"1100001100000000", -- |##    ##        | 07
-		"0110011000000000", -- | ##  ##         | 08
-		"0110011000000000", -- | ##  ##         | 09
-		"0011110000000000", -- |  ####          | 10
-		"0011110000000000", -- |  ####          | 11
-		"0001100000000000", -- |   ##           | 12
-		"0001100000000000", -- |   ##           | 13
-		"0011000000000000", -- |  ##            | 14
-		"0110000000000000", -- | ##             | 15
-		-- ASCII 256 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 257 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 258 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 259 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 260 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 261 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 262 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 263 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 264 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 265 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 266 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 267 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 268 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 269 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 270 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 271 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 272 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 273 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 274 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 275 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 276 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 277 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 278 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 279 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 280 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 281 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 282 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 283 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 284 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 285 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 286 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000", -- |                | 15
-		-- ASCII 287 ---------------
-		"0000000000000000", -- |                | 00
-		"0000000000000000", -- |                | 01
-		"0000000000000000", -- |                | 02
-		"0000000000000000", -- |                | 03
-		"0000000000000000", -- |                | 04
-		"0000000000000000", -- |                | 05
-		"0000000000000000", -- |                | 06
-		"0000000000000000", -- |                | 07
-		"0000000000000000", -- |                | 08
-		"0000000000000000", -- |                | 09
-		"0000000000000000", -- |                | 10
-		"0000000000000000", -- |                | 11
-		"0000000000000000", -- |                | 12
-		"0000000000000000", -- |                | 13
-		"0000000000000000", -- |                | 14
-		"0000000000000000" -- |                | 15
-	);
-begin
-
-	p_rom : process
-	begin
-		wait until rising_edge(CLK);
-		DATA <= ROM(to_integer(unsigned(ADDR)));
-	end process;
-
-end RTL;
-
diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd
deleted file mode 100644
index f5bbcc5..0000000
--- a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd
+++ /dev/null
@@ -1,539 +0,0 @@
-library ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity char_rom is
-  port (
-    CLK         : in    std_logic;
-    ADDR        : in    unsigned(11 downto 0);
-    DATA        : out   unsigned(7 downto 0)
-    );
-end;
-
-architecture RTL of char_rom is
-
-
-  type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008
-    x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010
-    x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020
-    x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028
-    x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038
-    x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040
-    x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048
-    x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050
-    x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058
-    x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060
-    x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070
-    x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078
-    x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080
-    x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088
-    x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090
-    x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098
-    x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0
-    x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8
-    x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8
-    x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100
-    x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108
-    x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118
-    x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128
-    x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138
-    x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148
-    x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150
-    x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158
-    x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168
-    x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170
-    x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178
-    x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180
-    x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188
-    x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190
-    x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198
-    x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0
-    x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8
-    x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8
-    x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200
-    x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208
-    x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218
-    x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228
-    x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230
-    x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238
-    x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240
-    x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250
-    x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268
-    x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270
-    x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278
-    x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280
-    x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288
-    x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300
-    x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308
-    x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310
-    x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318
-    x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330
-    x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338
-    x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348
-    x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350
-    x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358
-    x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360
-    x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368
-    x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370
-    x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378
-    x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380
-    x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388
-    x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390
-    x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-     DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat
deleted file mode 100644
index 9cfa61b..0000000
--- a/lib/VGA_ctrl/src/fonts/make_rom.bat
+++ /dev/null
@@ -1,6 +0,0 @@
-@echo off
-
-bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd
-bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd
-bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd
-bff2rom System_16x16.bff y >char_rom_system_16x16.vhd
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
deleted file mode 100644
index a89f7a4..0000000
--- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-use work.vga_types.all;
-
-ENTITY tb_vga_frontend IS
-END tb_vga_frontend;
-
-ARCHITECTURE behavior OF tb_vga_frontend IS 
-
-	constant tsvga			: vga_timespec_t := ts_vga_testbench;
-	constant CLK_PERIOD		: time := 10 ns;
-	constant VGA_CLK_PERIOD	: time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;
-	signal CLK_O			: std_logic := '1';
-	signal RST_O			: std_logic := '1';
-
-	-- Master
-	signal CYC_O			: std_logic;
-	signal STB_O			: std_logic;
-	signal WE_O				: std_logic;
-	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I			: std_logic := '0';
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
-
-	-- Slave
-	signal CYC_I			: std_logic := '0';
-	signal STB_I			: std_logic := '0';
-	signal WE_I				: std_logic := '0';
-	signal SEL_I			: unsigned(3 downto 0);
-	signal ACK_O			: std_logic;
-	signal MRDY_I			: std_logic;
-	signal SRDY_O			: std_logic;
-	signal ADDR_I			: unsigned(31 downto 0) := (others => '-');
-	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
-
-	-- VGA signals
-	signal vga_clk			: std_logic := '1';
-	signal vga_red			: unsigned(7 downto 0);
-	signal vga_green		: unsigned(7 downto 0);
-	signal vga_blue			: unsigned(7 downto 0);
-	signal vga_blank_n		: std_logic;
-	signal vga_sync_n		: std_logic;
-	signal vga_hsync		: std_logic;
-	signal vga_vsync		: std_logic;
-	signal vga_en			: std_logic;
-
-
-BEGIN
-
-inst_vga_frontend : entity work.vga_frontend
-	GENERIC MAP
-	(
-		fifo_depth					=> 256,
-		fifo_almost_full_thresh		=> 240,
-		fifo_almost_empty_thresh	=> 16,
-		tsvga						=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_I,
-		STB_O			=> STB_I,
-		WE_O			=> WE_I,
-		SEL_O			=> SEL_I,
-		ACK_I			=> ACK_O,
-		SRDY_I			=> SRDY_O,
-		MRDY_O			=> MRDY_I,
-		ADDR_O			=> ADDR_I,
-		MDAT_I			=> MDAT_O,
-		MDAT_O			=> MDAT_I,
-
-		-- JBUS Slave signals
-		CYC_I			=> CYC_O,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O,
-		ACK_O			=> ACK_I,
-		SRDY_O			=> SRDY_I,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> SDAT_O,
-		SDAT_O			=> SDAT_I,
-		
-		-- VGA signals
-		vga_clk_in		=> vga_clk,
-		vga_clk_ce		=> vga_en,
-		vga_red			=> vga_red,
-		vga_green		=> vga_green,
-		vga_blue		=> vga_blue,
-		vga_blank_n		=> vga_blank_n,
-		vga_sync_n		=> vga_sync_n,
-		vga_hsync		=> vga_hsync,
-		vga_vsync		=> vga_vsync
-	);
-
-	vga_en		<= not RST_O;
-	
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-VGA_CLK_GEN: process
-	begin
-		wait for VGA_CLK_PERIOD/2;
-		vga_clk <= not vga_clk after 3 ns;
-	end process;
-
--- Slave
-	SRDY_O	<= CYC_I;
-	
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				MDAT_O	<= X"00000000";
-			elsif (CYC_I and STB_I) = '1' then
-				MDAT_O	<= MDAT_O + 1;
-				ACK_O	<= '1';
-			else
-				ACK_O	<= '0';
-			end if;
-		end if;
-	end process;
-
--- Master
-STIMULUS: process
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		RST_O <= '0';
-		wait for 60*CLK_PERIOD;
-
-		-- Enable master
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0002";
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read status
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read resolution X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0018";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read resolution Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_001C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Write char 1
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0035";
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read char 1
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Write char 2
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0045";
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read char 2
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Set Cursor X
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0012";
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Set Cursor Y
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0014";
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		
-
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
deleted file mode 100644
index cdcb8bb..0000000
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ /dev/null
@@ -1,969 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-use work.vga_types.all;
-
-ENTITY tb_vga_frontend64 IS
-END tb_vga_frontend64;
-
-ARCHITECTURE behavior OF tb_vga_frontend64 IS 
-
-	constant tsvga			: vga_timespec_t := ts_vga_testbench;
-	constant CLK_PERIOD		: time := 10 ns;
-	constant VGA_CLK_PERIOD	: time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;
-	signal CLK_O			: std_logic := '1';
-	signal RST_O			: std_logic := '1';
-
-	-- Master
-	signal INT_O			: std_logic;
-	signal CYC_O			: std_logic;
-	signal STB_O			: std_logic;
-	signal WE_O				: std_logic;
-	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I			: std_logic := '0';
-	signal MRDY_O			: std_logic := '1';
-	signal SRDY_I			: std_logic := '0';
-	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
-	signal MDAT_I			: unsigned(63 downto 0) := (others => '-');
-	signal MDAT_O			: unsigned(63 downto 0) := (others => '-');
-
-	-- Slave
-	signal CYC_I			: std_logic := '0';
-	signal STB_I			: std_logic := '0';
-	signal WE_I				: std_logic := '0';
-	signal SEL_I			: unsigned(7 downto 0);
-	signal ACK_O			: std_logic;
-	signal MRDY_I			: std_logic;
-	signal SRDY_O			: std_logic;
-	signal ADDR_I			: unsigned(31 downto 0) := (others => '0');
-	signal SDAT_I			: unsigned(31 downto 0) := (others => '-');
-	signal SDAT_O			: unsigned(31 downto 0) := (others => '-');
-	signal rdy				: std_logic := '0';
-
-	signal read_reg			: unsigned(31 downto 0) := (others => '-');
-	signal const_color		: unsigned(31 downto 0) := X"0000_0000";
-
-	-- VGA signals
-	signal vga_clk			: std_logic := '1';
-	signal vga_red			: unsigned(7 downto 0);
-	signal vga_green		: unsigned(7 downto 0);
-	signal vga_blue			: unsigned(7 downto 0);
-	signal vga_blank_n		: std_logic;
-	signal vga_sync_n		: std_logic;
-	signal vga_hsync		: std_logic;
-	signal vga_vsync		: std_logic;
-	signal vga_en			: std_logic;
-
-	type blit_size_array_t	is array (0 to 9) of natural;
-	
-	constant blit_size_x : blit_size_array_t := (8, 1, 2, 7, 8, 7, 1, 8, 8, 0);
-	constant blit_size_y : blit_size_array_t := (8, 1, 2, 8, 7, 7, 8, 1, 0, 8);
-	signal blit_count_rst	: std_logic := '0';
-	type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU);
-	signal state : state_t := IDLE;
-	
-	type ram_t  is array (0 to 127) of unsigned(63 downto 0);
-	
-	signal ram_src		: ram_t := 
-	(
-		X"B000_0000_A000_0000",
-		X"B000_0001_A000_0001",
-		X"B000_0002_A000_0002",
-		X"B000_0003_A000_0003",
-		X"B000_0004_A000_0004",
-		X"B000_0005_A000_0005",
-		X"B000_0006_A000_0006",
-		X"B000_0007_A000_0007",
-		X"B000_0008_A000_0008",
-		X"B000_0009_A000_0009",
-		X"B000_000A_A000_000A",
-		X"B000_000B_A000_000B",
-		X"B000_000C_A000_000C",
-		X"B000_000D_A000_000D",
-		X"B000_000E_A000_000E",
-		X"B000_000F_A000_000F",
-
-		X"B000_0010_A000_0010",
-		X"B000_0011_A000_0011",
-		X"B000_0012_A000_0012",
-		X"B000_0013_A000_0013",
-		X"B000_0014_A000_0014",
-		X"B000_0015_A000_0015",
-		X"B000_0016_A000_0016",
-		X"B000_0017_A000_0017",
-		X"B000_0018_A000_0018",
-		X"B000_0019_A000_0019",
-		X"B000_001A_A000_001A",
-		X"B000_001B_A000_001B",
-		X"B000_001C_A000_001C",
-		X"B000_001D_A000_001D",
-		X"B000_001E_A000_001E",
-		X"B000_001F_A000_001F",
-		
-		X"B000_0020_A000_0020",
-		X"B000_0021_A000_0021",
-		X"B000_0022_A000_0022",
-		X"B000_0023_A000_0023",
-		X"B000_0024_A000_0024",
-		X"B000_0025_A000_0025",
-		X"B000_0026_A000_0026",
-		X"B000_0027_A000_0027",
-		X"B000_0028_A000_0028",
-		X"B000_0029_A000_0029",
-		X"B000_002A_A000_002A",
-		X"B000_002B_A000_002B",
-		X"B000_002C_A000_002C",
-		X"B000_002D_A000_002D",
-		X"B000_002E_A000_002E",
-		X"B000_002F_A000_002F",
-
-		X"B000_0030_A000_0030",
-		X"B000_0031_A000_0031",
-		X"B000_0032_A000_0032",
-		X"B000_0033_A000_0033",
-		X"B000_0034_A000_0034",
-		X"B000_0035_A000_0035",
-		X"B000_0036_A000_0036",
-		X"B000_0037_A000_0037",
-		X"B000_0038_A000_0038",
-		X"B000_0039_A000_0039",
-		X"B000_003A_A000_003A",
-		X"B000_003B_A000_003B",
-		X"B000_003C_A000_003C",
-		X"B000_003D_A000_003D",
-		X"B000_003E_A000_003E",
-		X"B000_003F_A000_003F",
-
-		X"B000_0040_A000_0040",
-		X"B000_0041_A000_0041",
-		X"B000_0042_A000_0042",
-		X"B000_0043_A000_0043",
-		X"B000_0044_A000_0044",
-		X"B000_0045_A000_0045",
-		X"B000_0046_A000_0046",
-		X"B000_0047_A000_0047",
-		X"B000_0048_A000_0048",
-		X"B000_0049_A000_0049",
-		X"B000_004A_A000_004A",
-		X"B000_004B_A000_004B",
-		X"B000_004C_A000_004C",
-		X"B000_004D_A000_004D",
-		X"B000_004E_A000_004E",
-		X"B000_004F_A000_004F",
-
-		X"B000_0050_A000_0050",
-		X"B000_0051_A000_0051",
-		X"B000_0052_A000_0052",
-		X"B000_0053_A000_0053",
-		X"B000_0054_A000_0054",
-		X"B000_0055_A000_0055",
-		X"B000_0056_A000_0056",
-		X"B000_0057_A000_0057",
-		X"B000_0058_A000_0058",
-		X"B000_0059_A000_0059",
-		X"B000_005A_A000_005A",
-		X"B000_005B_A000_005B",
-		X"B000_005C_A000_005C",
-		X"B000_005D_A000_005D",
-		X"B000_005E_A000_005E",
-		X"B000_005F_A000_005F",
-		
-		X"B000_0060_A000_0060",
-		X"B000_0061_A000_0061",
-		X"B000_0062_A000_0062",
-		X"B000_0063_A000_0063",
-		X"B000_0064_A000_0064",
-		X"B000_0065_A000_0065",
-		X"B000_0066_A000_0066",
-		X"B000_0067_A000_0067",
-		X"B000_0068_A000_0068",
-		X"B000_0069_A000_0069",
-		X"B000_006A_A000_006A",
-		X"B000_006B_A000_006B",
-		X"B000_006C_A000_006C",
-		X"B000_006D_A000_006D",
-		X"B000_006E_A000_006E",
-		X"B000_006F_A000_006F",
-
-		X"B000_0070_A000_0070",
-		X"B000_0071_A000_0071",
-		X"B000_0072_A000_0072",
-		X"B000_0073_A000_0073",
-		X"B000_0074_A000_0074",
-		X"B000_0075_A000_0075",
-		X"B000_0076_A000_0076",
-		X"B000_0077_A000_0077",
-		X"B000_0078_A000_0078",
-		X"B000_0079_A000_0079",
-		X"B000_007A_A000_007A",
-		X"B000_007B_A000_007B",
-		X"B000_007C_A000_007C",
-		X"B000_007D_A000_007D",
-		X"B000_007E_A000_007E",
-		X"B000_007F_A000_007F"
-	);
-
-	signal ram_dst		: ram_t := 
-	(
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000",
-		X"0000_0000_0000_0000"
-		
-	);
-
-BEGIN
-
-inst_vga_frontend64 : entity work.vga_frontend64
-	GENERIC MAP
-	(
-		fifo_depth					=> 64,
-		fifo_almost_full_thresh		=> 48,
-		fifo_almost_empty_thresh	=> 16,
-		BLIT_CHUNK_SIZE				=> 16,
-		tsvga						=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_I,
-		STB_O			=> STB_I,
-		WE_O			=> WE_I,
-		SEL_O			=> SEL_I,
-		ACK_I			=> ACK_O,
-		SRDY_I			=> SRDY_O,
-		MRDY_O			=> MRDY_I,
-		ADDR_O			=> ADDR_I,
-		MDAT_I			=> MDAT_O,
-		MDAT_O			=> MDAT_I,
-
-		-- JBUS Slave signals
-		INT_O			=> INT_O,
-		CYC_I			=> CYC_O,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O,
-		ACK_O			=> ACK_I,
-		SRDY_O			=> SRDY_I,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> SDAT_O,
-		SDAT_O			=> SDAT_I,
-		
-		-- VGA signals
-		vga_clk_in		=> vga_clk,
-		vga_clk_ce		=> vga_en,
-		vga_red			=> vga_red,
-		vga_green		=> vga_green,
-		vga_blue		=> vga_blue,
-		vga_blank_n		=> vga_blank_n,
-		vga_sync_n		=> vga_sync_n,
-		vga_hsync		=> vga_hsync,
-		vga_vsync		=> vga_vsync
-	);
-
-	vga_en		<= not RST_O;
-
-rdy_GEN: process
-	begin
-		wait for 3*CLK_PERIOD/2;
-		wait until rising_edge(CLK_O);
-		rdy <= not rdy;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-VGA_CLK_GEN: process
-	begin
-		wait for VGA_CLK_PERIOD/2;
-		vga_clk <= not vga_clk after 3 ns;
-	end process;
-
--- Slave
-	SRDY_O	<= CYC_I and rdy;
-	
-	process(CLK_O)
-	variable ack_v : unsigned(11 downto 0);
-	type arr64_t is array (11 downto 0) of unsigned(63 downto 0);
-	variable dat_v : arr64_t;
-	variable res: unsigned(63 downto 0);
-	variable scan_count: unsigned(31 downto 0);
-	variable ram_data : unsigned(63 downto 0);
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				scan_count	:= X"00000000";
-				for i in 0 to 11 loop
-					dat_v(i)	:= X"FFFFFFFF_FFFFFFFF";
-					ack_v(i)	:= '0';
-				end loop;
-			else
-				if (CYC_I and STB_I) = '1' and rdy = '1' then
-					if WE_I = '0' then
-						if ADDR_I(30) = '1' then
-							if ADDR_I(2) = '0' then
-								res			:= ADDR_I & scan_count;
-							else
-								res			:= scan_count & ADDR_I;
-							end if;
-							scan_count 	:= scan_count + 8;
-						else
-							ram_data := ram_src(to_integer(ADDR_I(31 downto 3)));
-							if ADDR_I(2) = '0' then
-								res			:= ram_data;
-							else
-								res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
-							end if;
-						end if;
-						dat_v		:= dat_v(10 downto 0) & res;
-						ack_v		:= ack_v(10 downto 0) & '1';
-					else -- WE=1
-						ram_data := ram_dst(to_integer(ADDR_I(31 downto 3)));
-						ram_data := (others => '-');
-						if ADDR_I(2) = '0' then
-							if SEL_I = "11111111" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I;
-							elsif SEL_I = "00001111" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(31 downto 0);
-							elsif SEL_I = "11110000" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(63 downto 32) & ram_data(31 downto 0);
-							end if;
-						else
-							if SEL_I = "11111111" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & MDAT_I(63 downto 32);
-							elsif SEL_I = "00001111" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & ram_data(31 downto 0);
-							elsif SEL_I = "11110000" then
-								ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(63 downto 32);
-							end if;
-						end if;
-					end if;
-				else
-					dat_v	:= dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF";
-					ack_v	:= ack_v(10 downto 0) & '0';
-				end if;
-				
-				MDAT_O	<= dat_v(dat_v'left);
-				ACK_O	<= ack_v(ack_v'left);
-			end if;
-		end if;
-	end process;
-
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				read_reg	<= X"00000000";
-			elsif ACK_I = '1' then
-				read_reg	<= SDAT_I;
-			end if;
-		end if;
-	end process;
-
--- Master
-STIMULUS: process
-
-	variable result : unsigned(31 downto 0);
-
-	procedure reg_write(reg, val : unsigned) is
-	begin
-	
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		WE_O	<= '1';
-		ADDR_O	<= reg;
-		SDAT_O	<= val;
-		STB_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		CYC_O	<= '0';
-
-	end procedure reg_write;
-
-	procedure reg_read(reg : unsigned) is
-	begin
-	
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		WE_O	<= '0';
-		ADDR_O	<= reg;
-		STB_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		result	:= SDAT_I;
-		CYC_O	<= '0';
-
-	end procedure reg_read;
-
-	begin
-
-		wait for 6*CLK_PERIOD;
-		RST_O <= '0';
-		wait for 60*CLK_PERIOD;
-
-		reg_write(X"0000_0018", X"4000_0000");	-- set frontbuffer address
-		reg_write(X"0000_001C", X"4000_0000");	-- set backbuffer address
-		reg_write(X"0000_0020", X"0000_0000");	-- set BLIT source address 0
-		reg_write(X"0000_0024", X"0000_0000");	-- set BLIT source dimension 0
-		reg_write(X"0000_0030", X"0000_0000");	-- set BLIT source address 1
-		reg_write(X"0000_0034", X"0000_0000");	-- set BLIT source dimension 1
-		reg_write(X"0000_0040", X"0000_0000");	-- set BLIT destination address
-		reg_write(X"0000_0044", X"0000_0000");	-- set BLIT destination dimension
-
-		-- Enable master
-		reg_write(X"0000_0000", X"0000_0002");
-
-		-- Read status
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read resolution
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0014";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Write char 1
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0035";
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read char 1
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Write char 2
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0045";
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read char 2
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0004";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Set Cursor X
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0012";
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Set Cursor Y
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0014";
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		-- Read Cursor X
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0008";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		-- Read Cursor Y
-		CYC_O	<= '1';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_000C";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		wait for 60000*CLK_PERIOD;
-
-		for i in 0 to blit_size_array_t'length-1 loop
-		
---			wait for 600*CLK_PERIOD;
-
-			-------------------------------------------------
-			-- BLIT aligned => aligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			state <= LA_SA;
-			
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0000");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0000");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
---			wait for 600*CLK_PERIOD;
-			-------------------------------------------------
-			-- BLIT unaligned => aligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-			state <= LU_SA;
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0004");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0000");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
---			wait for 600*CLK_PERIOD;
-			
-			-------------------------------------------------
-			-- BLIT aligned => unaligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-			state <= LA_SU;
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0000");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0004");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
---			wait for 600*CLK_PERIOD;
-			-------------------------------------------------
-			-- BLIT unaligned => unaligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-			state <= LU_SU;
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0004");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0004");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-
---			wait for 600*CLK_PERIOD;
-			-------------------------------------------------
-			-- BLIT const => aligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-			state <= CC_SA;
-
-			const_color	<= const_color + X"1111_1111";
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0000");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0000");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", result or X"0001_0100");
-
---			wait for 600*CLK_PERIOD;
-			-------------------------------------------------
-			-- BLIT const => unaligned test
-			-------------------------------------------------
-			while(true) loop
-				reg_read(X"0000_0000");
-				if result(8) = '0' then
-					exit;
-				end if;
-			end loop;
-			blit_count_rst <= '1';
-			wait until rising_edge(CLK_O);
-			blit_count_rst <= '0';
-			state <= CC_SU;
-
-			const_color	<= const_color + X"1111_1111";
-
-			-- set source start address
-			reg_write(X"0000_0020", X"0000_0000");
-
-			-- set src dim-x
-			reg_write(X"0000_0024", to_unsigned(32, 32));
-
-			-- set destination start address
-			reg_write(X"0000_0040", X"0000_0004");
-
-			-- set constant color
-			reg_write(X"0000_0058", const_color);
-
-			-- set dst dim-x
-			reg_write(X"0000_0044", to_unsigned(32, 32));
-
-			-- set nx
-			reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32));
-
-			-- set ny
-			reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32));
-
-			-- set blit request
-			reg_read(X"0000_0000");
-			reg_write(X"0000_0000", result or X"0001_0100");
-
---			wait for 600*CLK_PERIOD;
-		
-		end loop;
-		state <= IDLE;
-		
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd
deleted file mode 100644
index ed741ec..0000000
--- a/lib/VGA_ctrl/src/vga_backend.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    vga_backend - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.vga_types.all;
-
-entity vga_backend is
-	Generic
-	(
-		tsvga				: vga_timespec_t	:= ts_vga_800_600_72
-	);
-	Port
-	(
-		-- System signals
-		sys_rst				: in std_logic;
-		sys_clk				: in std_logic;
-		
-		-- Color channels
-		color_in			: in color_array_t;
-		color_op			: in color_op_t;
-		color_en			: unsigned (VGA_NUM_CH-1 downto 0);
-
-		-- Control signals
-		ctrl_scan_en		: in std_logic;
-
-		-- Status signals
-		stat_vga_rdy		: out std_logic;
-		stat_scan			: out std_logic;
-		stat_hsync			: out std_logic;
-		stat_vsync			: out std_logic;
-		stat_hready			: out std_logic;
-		stat_vready			: out std_logic;
-		stat_hscan			: out std_logic;
-		stat_vscan			: out std_logic;
-		stat_hpos			: out natural range 0 to tsvga.ts_h.ncyc_scan-1;
-		stat_vpos			: out natural range 0 to tsvga.ts_v.ncyc_scan-1;
-		
-		-- VGA domain signals
-		vga_clk_in			: in  std_logic;
-		vga_clk_ce			: in  std_logic;
-		vga_red				: out unsigned(7 downto 0);
-		vga_green			: out unsigned(7 downto 0);
-		vga_blue			: out unsigned(7 downto 0);
-		vga_blank_n			: out std_logic;
-		vga_sync_n			: out std_logic;
-		vga_hsync			: out std_logic;
-		vga_vsync			: out std_logic
-	);
-end vga_backend;
-
-architecture Behavioral of vga_backend is
-
-	signal scan_enable			: std_logic;
-	signal is_scan				: std_logic;
-	signal is_hscan				: std_logic;
-	signal is_vscan				: std_logic;
-	signal hsync				: std_logic;
-	signal vsync				: std_logic;
-	signal hready				: std_logic;
-	signal vready				: std_logic;
-	signal rst					: std_logic;
-
-begin
-
-inst_vga_timing: entity work.vga_timing 
-	GENERIC MAP
-	(
-		tsvga => tsvga
-	)		
-	PORT MAP
-	(
-		sys_rst		=> sys_rst,
-		vga_clk		=> vga_clk_in,
-		vga_ce		=> vga_clk_ce,
-		sync_h		=> hsync,
-		sync_v		=> vsync,
-		scan_pos_h	=> stat_hpos,
-		scan_pos_v	=> stat_vpos,
-		is_scan_h	=> is_hscan,
-		is_scan_v	=> is_vscan,
-		scan_rdy_h	=> hready,
-		scan_rdy_v	=> vready
-	);
-
-	---------------------------------------------------------------------------------------------
-	rst					<= not vga_clk_ce;
-	stat_vga_rdy		<= vga_clk_ce;
-	stat_hsync			<= hsync;
-	stat_vsync			<= vsync;
-	stat_hscan			<= is_hscan;
-	stat_vscan			<= is_vscan;
-	stat_hready			<= hready;
-	stat_vready			<= vready;
-	stat_scan			<= is_scan;
-	
-	vga_blank_n			<= '1';
-	vga_sync_n			<= '0';
-	is_scan				<= is_hscan and is_vscan and scan_enable;
-	
-	---------------------------------------------------------------------------------------------
-	proc_vga_start:
-	process (rst, vga_clk_in)
-	begin
-		if rst = '1' then
-			scan_enable <= '0';
-		elsif rising_edge(vga_clk_in) then
-			if vsync = '1' then
-				if ctrl_scan_en = '1' then
-					scan_enable <= '1';
-				else
-					scan_enable <= '0';
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-	proc_vga_color_out:
-	process (vga_clk_in)
-	variable do_scan : std_logic;
-	variable color : color_t;
-	begin
-		if rising_edge(vga_clk_in) then
-			vga_red		<= X"00";
-			vga_green	<= X"00";
-			vga_blue	<= X"00";
-			if is_scan = '1' then
-				for i in 0 to VGA_NUM_CH-1 loop
-					color := 	color_in(i);		
-					if color_en(i) = '1' then
-						vga_red		<= color(r);	-- ToDo: color_op over channels
-						vga_green	<= color(g);	-- ToDo: color_op over channels
-						vga_blue	<= color(b);	-- ToDo: color_op over channels
-					end if;
-				end loop;
-			end if;
-		end if;
-	end process;
-		
-	---------------------------------------------------------------------------------------------
-	proc_vga_sync_out:
-	process (rst, vga_clk_in)
-	variable hsync_r : std_logic;
-	variable vsync_r : std_logic;
-	begin
-		if rst = '1' then
-			vga_hsync	<= tsvga.ts_h.sync_polarity;
-			vga_vsync	<= tsvga.ts_v.sync_polarity;
-			hsync_r		:= tsvga.ts_h.sync_polarity;
-			vsync_r		:= tsvga.ts_v.sync_polarity;
-		elsif rising_edge(vga_clk_in) then
-			vga_hsync	<= hsync_r;
-			vga_vsync	<= vsync_r;
-			hsync_r		:= hsync xor (not tsvga.ts_h.sync_polarity);
-			vsync_r		:= vsync xor (not tsvga.ts_v.sync_polarity);
-		end if;
-	end process;
-
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_frontend.vhd b/lib/VGA_ctrl/src/vga_frontend.vhd
deleted file mode 100644
index 8e1f6a6..0000000
--- a/lib/VGA_ctrl/src/vga_frontend.vhd
+++ /dev/null
@@ -1,495 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    vga_backend - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.vga_types.all;
-
-entity vga_frontend is
-	Generic
-	(
-		fifo_depth					: integer    		:= 2048;
-		fifo_almost_full_thresh		: natural 			:= 2000;
-		fifo_almost_empty_thresh	: natural 			:= 48;
-		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
-	);
-	Port
-	(
-		-- System signals
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-
-		-- JBUS Master signals
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(3 downto 0);
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		MDAT_I			: in  unsigned(31 downto 0);
-		MDAT_O			: out unsigned(31 downto 0);
-		
-		-- JBUS Slave signals
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		SDAT_I			: in  unsigned(31 downto 0);
-		SDAT_O			: out unsigned(31 downto 0);
-		
-		-- VGA signals
-		vga_clk_in		: in  std_logic;
-		vga_clk_ce		: in  std_logic;
-		vga_red			: out unsigned(7 downto 0);
-		vga_green		: out unsigned(7 downto 0);
-		vga_blue		: out unsigned(7 downto 0);
-		vga_blank_n		: out std_logic;
-		vga_sync_n		: out std_logic;
-		vga_hsync		: out std_logic;
-		vga_vsync		: out std_logic
-	);
-end vga_frontend;
-
-architecture Behavioral of vga_frontend is
-
-	signal vga_clk				: std_logic;
-
-	-- Color FIFO signals
-	signal fifo_full			: std_logic;
-	signal fifo_empty			: std_logic;
-	signal fifo_almost_empty	: std_logic;
-	signal fifo_almost_full		: std_logic;
-	signal fifo_color_re		: std_logic;
-	signal fifo_color_we		: std_logic;
-	signal fifo_color_out		: unsigned(31 downto 0);
-	signal fifo_color_in		: unsigned(31 downto 0);
-
-	--	Backend signals
-	signal scan_rdy				: std_logic;
-	signal ctrl_scan_en			: std_logic;
-	signal color_in				: color_array_t;
-	signal color_op				: color_op_t;
-	signal color_en				: unsigned (VGA_NUM_CH-1 downto 0);
-
-	signal stat_vga_rdy			: std_logic;
-	signal stat_hready			: std_logic;
-	signal stat_vready			: std_logic;
-	signal stat_scan			: std_logic;
-	signal stat_hscan			: std_logic;
-	signal stat_vscan			: std_logic;
-	signal stat_hsync			: std_logic;
-	signal stat_vsync			: std_logic;
-	signal stat_hpos			: natural range 0 to tsvga.ts_h.ncyc_scan-1;
-	signal stat_vpos			: natural range 0 to tsvga.ts_v.ncyc_scan-1;
-
-	--	CG signals
-	signal cg_en				: std_logic;
-	signal cg_rdy				: std_logic;
-	signal cg_draw				: std_logic;
-	signal cg_clr_screen		: std_logic;
-	signal cg_clr_line			: std_logic;
-	signal cg_din				: unsigned(7 downto 0);
-	signal cg_dout				: unsigned(7 downto 0);
-	signal cg_ascii_we			: std_logic;
-	signal cg_posy_we			: std_logic;
-	signal cg_posx_we			: std_logic;
-	signal cg_color				: color_t;
-	signal cg_csr_pos_x			: natural range 0 to 80-1;
-	signal cg_csr_pos_y			: natural range 0 to 32-1;
-
-	-- Bus master signals
-	constant MAX_REQUEST_CNT	: natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
-
-	signal vga_mem_offset		: unsigned(31 downto 0);
-	signal vga_scan_rdy			: std_logic;
-	signal vga_master_en		: std_logic;
-	signal request_cnt_rst		: std_logic;
-	signal request_cnt_en		: std_logic;
-	signal pixel_cnt_rst		: std_logic;
-	signal read_bus_en			: std_logic;
-	signal request_cnt			: natural range 0 to MAX_REQUEST_CNT-1;
-	signal read_cnt				: natural range 0 to MAX_REQUEST_CNT-1;
-
-	type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data);
-	signal s, sn : vm_state_t;
-
-begin
-
-inst_vga_backend : entity work.vga_backend
-	GENERIC MAP
-	(
-		tsvga						=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		sys_rst			=> RST_I,
-		sys_clk			=> CLK_I,
-		
-		-- Color channels
-		color_in		=> color_in,
-		color_op		=> color_op,
-		color_en		=> color_en,
-
-		-- Control signals
-		ctrl_scan_en	=> ctrl_scan_en,
-
-		-- Status signals
-		stat_vga_rdy	=> stat_vga_rdy,
-		stat_scan		=> stat_scan,
-		stat_hsync		=> stat_hsync,
-		stat_vsync		=> stat_vsync,
-		stat_hready		=> stat_hready,
-		stat_vready		=> stat_vready,
-		stat_hscan		=> stat_hscan,
-		stat_vscan		=> stat_vscan,
-		stat_hpos		=> stat_hpos,
-		stat_vpos		=> stat_vpos,
-		
-		-- VGA domain signals
-		vga_clk_in		=> vga_clk_in,
-		vga_clk_ce		=> vga_clk_ce,
-		vga_red			=> vga_red,
-		vga_green		=> vga_green,
-		vga_blue		=> vga_blue,
-		vga_blank_n		=> vga_blank_n,
-		vga_sync_n		=> vga_sync_n,
-		vga_hsync		=> vga_hsync,
-		vga_vsync		=> vga_vsync
-	);
-
-	ctrl_scan_en	<= '1';
-	color_en(0)		<= not fifo_empty;
-	color_en(1)		<= cg_draw;
-	color_in(0)		<= to_color_t(fifo_color_out);
-	color_in(1)		<= cg_color; --(X"FF", X"FF", X"FF", X"FF");	-- white opaque
-	color_op		<= op_over;
-	vga_scan_rdy	<= stat_hready and stat_vready;
-	
-inst_linefifo: entity work.fifo_async
-	GENERIC MAP 
-	(
-		addr_width			=> NextExpBaseTwo(fifo_depth),
-		data_width			=> 32,
-		almost_full_thresh	=> fifo_almost_full_thresh,
-		almost_empty_thresh	=> fifo_almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=> RST_I,
-		clk_w			=> CLK_I,
-		clk_r			=> vga_clk_in,
-		we				=> fifo_color_we,
-		re				=> fifo_color_re,
-		data_w			=> fifo_color_in,
-		data_r			=> fifo_color_out,
-		fifo_full		=> fifo_full,
-		fifo_empty		=> fifo_empty,
-		fifo_afull		=> fifo_almost_full,
-		fifo_aempty		=> fifo_almost_empty
-		
-	);
-
-	fifo_color_in		<= MDAT_I;
-	fifo_color_re		<= stat_scan;
-	fifo_color_we		<= ACK_I and read_bus_en;		-- TODO:
-	MRDY_O				<= not fifo_full;
-	SEL_O				<= (others => '0');
-	WE_O				<= '0';
-	
-vga_master_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s	<= init;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-
-vga_master:
-	process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
-	begin
-	
-	CYC_O			<= '0';
-	STB_O			<= '0';
-	pixel_cnt_rst	<= '0';
-	request_cnt_rst	<= '0';
-	request_cnt_en	<= '0';
-	read_bus_en		<= '0';
-	sn				<= s;
-	
-	case s is
-		when init =>
-		if stat_vga_rdy = '1' then
-			sn	<= idle;
-		end if;
-		
-		when idle =>
-		pixel_cnt_rst	<= '1';
-		if vga_master_en = '1' and vga_scan_rdy = '1' then
-			sn	<= rdy;
-		end if;
-		
-		when rdy =>
---		pixel_cnt_rst	<= '1';
-		if fifo_almost_empty = '1' then
-			sn	<= bus_request;
-		end if;
-		
-		when bus_request =>
-			CYC_O			<= '1';
-			request_cnt_rst	<= '1';
-			if SRDY_I = '1' then
-				sn	<= bus_access;
-			end if;
-			
-		when bus_access =>
-			CYC_O			<= '1';
-			STB_O			<= '1';
-			request_cnt_en	<= '1';
-			read_bus_en		<= '1';
-			if fifo_almost_full = '1' then
-				sn <= bus_data;
-			end if;	
-		when bus_data =>
-			CYC_O		<= '1';
-			read_bus_en	<= '1';
-			if read_cnt = request_cnt then
-				sn	<= rdy;
-				if vga_master_en = '0' then
-					sn	<= idle;
-				end if;	
-			end if;	
-		when others =>
-			sn	<= idle;
-		
-		end case;
-	end process;
-	
-request_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_cnt_rst = '1' then
-				request_cnt	<= 0;
-			elsif request_cnt_en = '1' and SRDY_I = '1' then
-				if request_cnt /= MAX_REQUEST_CNT-1 then
-					request_cnt <= request_cnt + 1;
-				end if;
-			end if;	
-		end if;
-	end process;	
-		
-read_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_cnt_rst = '1' then
-				read_cnt	<= 0;
-			elsif read_bus_en = '1' and ACK_I = '1' then
-				if read_cnt /= MAX_REQUEST_CNT-1 then
-					read_cnt <= read_cnt + 1;
-				end if;
-			end if;	
-		end if;
-	end process;	
-
-pixel_counter:
-	process(CLK_I)
-	variable pixel_cnt	: natural range 0 to MAX_REQUEST_CNT-1;
-	begin
-		if rising_edge(CLK_I) then
-			if pixel_cnt_rst = '1' then
-				pixel_cnt	:= 0;
-			elsif request_cnt_en = '1' and SRDY_I = '1' then
-				if pixel_cnt /= MAX_REQUEST_CNT-1 then
-					pixel_cnt 	:= pixel_cnt + 1;
-				else
-					pixel_cnt	:= 0;
-				end if;	
- 			end if;	
- 			ADDR_O	<= vga_mem_offset + (to_unsigned(pixel_cnt, 30) & "00");
-		end if;
-	end process;	
-	
-inst_char_gen : entity work.char_gen
-	GENERIC MAP
-	(
-		tsvga				=> tsvga,
-		CHARACTER_SCALE		=> 1,
-		CHAR_ROM_SIZE_X		=> 8,	-- Pixels
-		CHAR_ROM_SIZE_Y		=> 16,	-- Pixels
-		CHAR_ROM_DEPTH		=> 256,	-- Chars
-		MAX_CHAR_PER_LINE	=> 80,	-- Chars
-		MAX_LINE_PER_FRAME	=> 32,	-- Chars
-		CHAR_SPACING_X		=> 0, 	-- Pixels
-		CHAR_SPACING_Y		=> 0,	-- Pixels
-		SCREEN_OFFSET_X		=> 16,	-- Pixels
-		SCREEN_OFFSET_Y		=> 16	-- Pixels
-	)		
-	PORT MAP
-	(
-	    rst				=> RST_I,
-	    sys_clk			=> CLK_I,
-	    vga_clk			=> vga_clk_in,
-	    ce				=> cg_en,
-	    frame_pulse		=> scan_rdy,
-	    clr_screen		=> cg_clr_screen,
-	    clr_line		=> cg_clr_line,
-	    din				=> cg_din,
-	    dout			=> cg_dout,
-	    ascii_we		=> cg_ascii_we,
-	    posy_we			=> cg_posy_we,
-	    posx_we			=> cg_posx_we,
-	    ready			=> cg_rdy,
-	    scan_pos_x_in	=> stat_hpos,
-	    scan_pos_y_in	=> stat_vpos,
-	   	csr_pos_x_out	=> cg_csr_pos_x,
-	   	csr_pos_y_out	=> cg_csr_pos_y,
-	    char_draw_en	=> cg_draw
-    );
-	SRDY_O				<= CYC_I; -- and cg_rdy;
---	SDAT_O				<= X"0000000" & "000" & cg_rdy;
-	MDAT_O				<= (others => '-');
-	scan_rdy			<= stat_hready and stat_vready;
-	cg_en				<= stat_scan;
-	
-
-registers_read: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			ACK_O			<= '0';
-			if (STB_I and CYC_I) = '1' then
-				ACK_O		<= not WE_I;
-				SDAT_O		<= (others => '0');
-				case ADDR_I(5 downto 2) is
-
-				-- sys_vga_ctrl		0
-				when "0000" =>
-					SDAT_O(0)			<= cg_rdy;
-					SDAT_O(1)			<= vga_master_en;
-					
-				-- sys_vga_ascii	4
-				when "0001" =>
-					SDAT_O(7 downto 0)	<= cg_dout;
-					
-				-- sys_vga_posx		8
-				when "0010" =>
-					SDAT_O(7 downto 0)	<= to_unsigned(cg_csr_pos_x, 8);
-
-				-- sys_vga_posy		12
-				when "0011" =>
-					SDAT_O(7 downto 0)	<= to_unsigned(cg_csr_pos_y, 8);
-
-				-- sys_vga_cgcol	16
-				when "0100" =>
-					SDAT_O				<= to_unsigned(cg_color);
-
-				-- sys_vga_moffs	20
-				when "0101" =>
-					SDAT_O				<= vga_mem_offset;
-
-				-- sys_vga_resx		24
-				when "0110" =>
-					SDAT_O(15 downto 0)	<= to_unsigned(tsvga.ts_h.ncyc_scan, 16);
-
-				-- sys_vga_resy		28
-				when "0111" =>
-					SDAT_O(15 downto 0)	<= to_unsigned(tsvga.ts_v.ncyc_scan, 16);
-
-				-- sys_vga_fps		32
-				when "1000" =>
-					SDAT_O(15 downto 0)	<= to_unsigned(tsvga.nfps, 16);
-
-				when others => null;
-				end case;
-			end if;
-		end if;	
-	end process;
-
-
-registers_write:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			cg_ascii_we	<= '0';
-			cg_posy_we	<= '0';
-			cg_posx_we	<= '0';
-			cg_clr_screen		<= '0';
-			cg_clr_line			<= '0';
-			if RST_I = '1' then
-				cg_din			<= (others => '0');
-				vga_master_en	<= '0';
-				vga_mem_offset	<= X"40000000";
-				cg_color		<= (X"FF", X"FF", X"FF", X"FF");
-			elsif (STB_I and CYC_I and WE_I) = '1' then
-				case ADDR_I(5 downto 2) is
-				
-				-- sys_vga_ctrl		0
-				when "0000" =>
-					vga_master_en	<= SDAT_I(1);
-					cg_clr_screen	<= SDAT_I(4);
-					cg_clr_line		<= SDAT_I(5);
-					
-				-- sys_vga_ascii	4
-				when "0001" =>
-					cg_ascii_we		<= '1';
-					cg_din			<= SDAT_I(7 downto 0);
-					
-				-- sys_vga_posx		8
-				when "0010" =>
-					cg_posx_we		<= '1';
-					cg_din			<= SDAT_I(7 downto 0);
-
-				-- sys_vga_posy		12
-				when "0011" =>
-					cg_posy_we		<= '1';
-					cg_din			<= SDAT_I(7 downto 0);
-
-				-- sys_vga_cgcol	16
-				when "0100" =>
-					cg_color		<= to_color_t(SDAT_I(31 downto 0));
-
-				-- sys_vga_moffs	20
-				when "0101" =>
-					vga_mem_offset	<= SDAT_I(31 downto 2) & "00";
-					
-				when others => null;
-				end case;
-
-			end if;
-		end if;
-	end process;
-	
-	---------------------------------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd
deleted file mode 100644
index 60c1a6c..0000000
--- a/lib/VGA_ctrl/src/vga_frontend64.vhd
+++ /dev/null
@@ -1,1329 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    vga_backend - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.utils_pkg.all;
-use work.vga_types.all;
-
-entity vga_frontend64 is
-	Generic
-	(
-		fifo_depth					: integer    		:= 4096;
-		fifo_almost_full_thresh		: natural 			:= 4000;
-		fifo_almost_empty_thresh	: natural 			:= 800;
-		BLIT_CHUNK_SIZE				: natural 			:= 512;
-		BLIT_CMD_FIFO_DEPTH			: natural 			:= 256;
-		tsvga						: vga_timespec_t	:= ts_vga_800_600_72
-	);
-	Port
-	(
-		-- System signals
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-
-		-- JBUS Master signals
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(7 downto 0);
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		MDAT_I			: in  unsigned(63 downto 0);
-		MDAT_O			: out unsigned(63 downto 0);
-		
-		-- JBUS Slave signals
-		INT_O			: out STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		SDAT_I			: in  unsigned(31 downto 0);
-		SDAT_O			: out unsigned(31 downto 0);
-		
-		-- VGA signals
-		vga_clk_in		: in  std_logic;
-		vga_clk_ce		: in  std_logic;
-		vga_red			: out unsigned(7 downto 0);
-		vga_green		: out unsigned(7 downto 0);
-		vga_blue		: out unsigned(7 downto 0);
-		vga_blank_n		: out std_logic;
-		vga_sync_n		: out std_logic;
-		vga_hsync		: out std_logic;
-		vga_vsync		: out std_logic
-	);
-end vga_frontend64;
-
-architecture Behavioral of vga_frontend64 is
-
-	-- Color FIFO signals
-	signal fifo_full					: std_logic;
-	signal fifo_empty					: std_logic;
-	signal fifo_almost_empty			: std_logic;
-	signal fifo_almost_full				: std_logic;
-	signal fifo_color_re				: std_logic;
-	signal fifo_color_we				: std_logic;
-	signal fifo_color_out				: unsigned(63 downto 0);
-	signal fifo_color_in				: unsigned(63 downto 0);
-
-	--	Backend signals
-	signal scan_rdy						: std_logic;
-	signal ctrl_scan_en					: std_logic;
-	signal color_in						: color_array_t;
-	signal color_op						: color_op_t;
-	signal color_en						: unsigned (VGA_NUM_CH-1 downto 0);
-
-	signal stat_vga_rdy					: std_logic;
-	signal stat_hready					: std_logic;
-	signal stat_vready					: std_logic;
-	signal stat_scan					: std_logic;
-	signal stat_hscan					: std_logic;
-	signal stat_vscan					: std_logic;
-	signal stat_hsync					: std_logic;
-	signal stat_vsync					: std_logic;
-	signal stat_hpos					: natural range 0 to tsvga.ts_h.ncyc_scan-1;
-	signal stat_vpos					: natural range 0 to tsvga.ts_v.ncyc_scan-1;
-
-	--	CG signals
-	signal cg_en						: std_logic;
-	signal cg_rdy						: std_logic;
-	signal cg_draw						: std_logic;
-	signal cg_clr_screen				: std_logic;
-	signal cg_clr_line					: std_logic;
-	signal cg_din						: unsigned(7 downto 0);
-	signal cg_dout						: unsigned(7 downto 0);
-	signal cg_ascii_we					: std_logic;
-	signal cg_posy_we					: std_logic;
-	signal cg_posx_we					: std_logic;
-	signal cg_color						: color_t;
-	signal cg_csr_pos_x					: natural range 0 to 80-1;
-	signal cg_csr_pos_y					: natural range 0 to 32-1;
-
-	-- Bus master signals
-	constant MAX_REQUEST_CNT			: natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan;
-
-	signal reg_read_vld					: std_logic;
-	signal bufchg						: std_logic;
-	signal bufchg_irq_en				: std_logic;
-	signal bufchg_flag					: std_logic;
-	signal bufchg_flag_ack				: std_logic;
-	signal vga_fb_back					: unsigned(31 downto 0);
-	signal vga_fb_front					: unsigned(31 downto 0);
-	signal host_fb_front				: unsigned(31 downto 0);
-	signal host_fb_back					: unsigned(31 downto 0);
-	signal blit_reg_addr_src_0			: unsigned(31 downto 0);
-	signal blit_reg_addr_src_1			: unsigned(31 downto 0);
-	signal blit_reg_addr_dst			: unsigned(31 downto 0);
-	signal blit_reg_dimx_src_0			: unsigned(31 downto 0);
-	signal blit_reg_dimx_src_1			: unsigned(31 downto 0);
-	signal blit_reg_dimx_dst			: unsigned(31 downto 0);
-	signal blit_reg_nx					: unsigned(31 downto 0);
-	signal blit_reg_ny					: unsigned(31 downto 0);
-	signal blit_reg_const_color			: unsigned(31 downto 0);
-	signal blit_reg_func				: unsigned(7 downto 0);
-	signal vga_scan_rdy					: std_logic;
-	signal vga_scan_dma_en				: std_logic;
-	signal vga_scan_dma_en2				: std_logic;
-	signal request_cnt_rst				: std_logic;
-	signal request_en					: std_logic;
-	signal bus_read_en					: std_logic;
-	signal request_cnt					: unsigned(28 downto 0);
-	signal read_cnt						: unsigned(28 downto 0);
-	signal bus_read_fin					: std_logic;
-	signal bus_cycle_en					: std_logic;
-
-	signal CYC_O_scan					: std_logic;
-	signal STB_O_scan					: std_logic;
-	signal ADDR_O_scan					: unsigned(31 downto 0);
-	signal pixel_cnt					: natural range 0 to MAX_REQUEST_CNT/2-1;
-	signal front						: unsigned(31 downto 0);
-	signal back							: unsigned(31 downto 0);
-
-
-	-- Blitter vars
-	signal blit_reset					: std_logic;
-	signal blit_request					: std_logic;
-	signal blit_const_color_en			: std_logic;
-	signal blit_request_set				: std_logic;
-	signal blit_finish_strobe			: unsigned(2 downto 0);
-	signal blit_complete_int			: std_logic;
-	signal blit_complete_int_ack		: std_logic;
-	signal blit_complete_int_en			: std_logic;
-	signal blit_cmd_empty_int			: std_logic;
-	signal blit_cmd_empty_int_ack		: std_logic;
-	signal blit_cmd_empty_int_en		: std_logic;
-	
-	-- BLIT command FIFO
-	constant BLIT_CMD_FIFO_WIDTH	: natural := 320;
-	signal blit_cmd_din				: unsigned(BLIT_CMD_FIFO_WIDTH-1 downto 0);
-	signal blit_cmd_dout			: unsigned(BLIT_CMD_FIFO_WIDTH-1 downto 0);
-	signal blit_cmd_re				: std_logic;
-	signal blit_cmd_we				: std_logic;
-	signal blit_cmd_empty			: std_logic;
-	signal blit_cmd_full			: std_logic;
-	signal blit_cmd_bsy				: std_logic;
-	signal blit_cmd_avail			: std_logic;
-	
-	signal blit_cmd_addr_src_0		: unsigned(31 downto 0);
-	signal blit_cmd_addr_src_1		: unsigned(31 downto 0);
-	signal blit_cmd_addr_dst		: unsigned(31 downto 0);
-	signal blit_cmd_dimx_src_0		: unsigned(31 downto 0);
-	signal blit_cmd_dimx_src_1		: unsigned(31 downto 0);
-	signal blit_cmd_dimx_dst		: unsigned(31 downto 0);
-	signal blit_cmd_nx				: unsigned(31 downto 0);
-	signal blit_cmd_ny				: unsigned(31 downto 0);
-	signal blit_cmd_CC				: unsigned(31 downto 0);
-	signal blit_cmd_func			: unsigned(31 downto 0);
-
-	signal blit_chunk_cnt			: natural range 0 to BLIT_CHUNK_SIZE-1;
-	signal blit_chunk_full			: std_logic;
-	
-	-- Blitter FIFO signals
-	signal blitfifo_dout_vld	: std_logic;
-	signal blitfifo_write_en	: std_logic;
-	signal blitfifo_read_en		: std_logic;
-	signal blitfifo_full		: unsigned(1 downto 0);
-	signal blitfifo_empty		: unsigned(1 downto 0);
-	signal blitfifo_we			: unsigned(1 downto 0);
-	signal blitfifo_re			: unsigned(1 downto 0);
-	signal blitfifo_din			: unsigned(63 downto 0);
-	signal blitfifo_dout_0		: unsigned(31 downto 0);
-	signal blitfifo_dout_1		: unsigned(31 downto 0);
-	
-
-	-- BLIT Source register
-	signal blit_src_cnt_x_next	: unsigned(32 downto 0);
-	signal blit_src_cnt_y_next	: unsigned(32 downto 0);
-	signal blit_src_cnt_x		: unsigned(31 downto 0);
-	signal blit_src_cnt_y		: unsigned(31 downto 0);
-	signal blit_src_offset		: unsigned(31 downto 0);
-	signal blit_src_addr_next	: unsigned(31 downto 0);
-	signal blit_src_finish		: std_logic;
-	signal blit_src_START_U		: std_logic;
-	signal blit_src_START_A		: std_logic;
-	signal blit_src_STOP_U		: std_logic;
-	signal blit_src_STOP_A		: std_logic;
-
-	signal CYC_O_blit_src		: std_logic;
-	signal STB_O_blit_src		: std_logic;
-	signal ADDR_O_blit_src		: unsigned(31 downto 0);
-	
-	-- BLIT Destination register
-	signal blit_dst_cnt_x_next	: unsigned(32 downto 0);
-	signal blit_dst_cnt_y_next	: unsigned(32 downto 0);
-	signal blit_dst_cnt_x		: unsigned(31 downto 0);
-	signal blit_dst_cnt_y		: unsigned(31 downto 0);
-	signal blit_dst_offset		: unsigned(31 downto 0);
-	signal blit_dst_addr_next	: unsigned(31 downto 0);
-	signal blit_dst_finish		: std_logic;
-	signal blitfifo_empty_read	: std_logic;
-	signal blit_dst_suspend		: std_logic;
-	signal blit_dst_be			: unsigned(7 downto 0);
-	
-	-- BLIT Source Tracker
-	signal blit_fill_cnt_x_next	: unsigned(32 downto 0);
-	signal blit_fill_cnt_y_next	: unsigned(32 downto 0);
-	signal blit_fill_cnt_x		: unsigned(31 downto 0);
-	signal blit_fill_cnt_y		: unsigned(31 downto 0);
-	signal blit_fill_offset		: unsigned(2 downto 0);
-	signal blit_fill_finish		: std_logic;
-	signal blit_fill_addr		: unsigned(2 downto 0);
-	
-	signal CYC_O_blit_dst		: std_logic;
-	signal STB_O_blit_dst		: std_logic;
-	signal ADDR_O_blit_dst		: unsigned(31 downto 0);
-
-	signal odd_pixel			: unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
-
-	
-	-- Bus output FIFO
-	signal busout_fifo_din		: unsigned(104 downto 0);
-	signal busout_fifo_dout		: unsigned(104 downto 0);
-	signal busout_fifo_re		: std_logic;
-	signal busout_fifo_we		: std_logic;
-	signal busout_fifo_full		: std_logic;
-	signal busout_fifo_empty	: std_logic;
-	signal busout_fifo_rdy		: std_logic;
-
-	alias busout_fifo_addr_in is busout_fifo_din(31 downto 0);
-	alias busout_fifo_data_in is busout_fifo_din(95 downto 32);
-	alias busout_fifo_sel_in is busout_fifo_din(103 downto 96);
-	alias busout_fifo_we_in is busout_fifo_din(104);
-	
-	alias busout_fifo_addr_out is busout_fifo_dout(31 downto 0);
-	alias busout_fifo_data_out is busout_fifo_dout(95 downto 32);
-	alias busout_fifo_sel_out is busout_fifo_dout(103 downto 96);
-	alias busout_fifo_we_out is busout_fifo_dout(104);
-	
-	-- Bus input FIFO
-	signal busin_fifo_din		: unsigned(63 downto 0);
-	signal busin_fifo_dout		: unsigned(63 downto 0);
-	signal busin_fifo_re		: std_logic;
-	signal busin_fifo_we		: std_logic;
-	signal busin_fifo_full		: std_logic;
-	signal busin_fifo_empty		: std_logic;
-	signal busin_fifo_rdy		: std_logic;
-	signal busin_fifo_dout_vld	: std_logic;
-
-	type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, const_dst_bus_request, bus_fin);
-	signal s, sn : vm_state_t;
-
-	type debug_t is 
-	record
-		FIRST		: std_logic;
-		LAST		: std_logic;
-		UNALIGNED	: std_logic;
-		PARTIAL		: std_logic;
-	end record debug_t;
-	
-	signal src_dbg	: debug_t;
-	signal fill_dbg	: debug_t;
-	signal dst_dbg	: debug_t;
-	
---------------------------------------------------------------------------
-begin
-
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-1 downto BLIT_CMD_FIFO_WIDTH-32)		 <= blit_reg_addr_src_0;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-32-1 downto BLIT_CMD_FIFO_WIDTH-64)	 <= blit_reg_dimx_src_0;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-64-1 downto BLIT_CMD_FIFO_WIDTH-96)	 <= blit_reg_addr_src_1;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-96-1 downto BLIT_CMD_FIFO_WIDTH-128)	 <= blit_reg_dimx_src_1;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-128-1 downto BLIT_CMD_FIFO_WIDTH-160)	 <= blit_reg_addr_dst;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-160-1 downto BLIT_CMD_FIFO_WIDTH-192)	 <= blit_reg_dimx_dst;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-192-1 downto BLIT_CMD_FIFO_WIDTH-224)	 <= blit_reg_nx;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-224-1 downto BLIT_CMD_FIFO_WIDTH-256)	 <= blit_reg_ny;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-256-1 downto BLIT_CMD_FIFO_WIDTH-288)	 <= blit_reg_const_color;
-	blit_cmd_din(BLIT_CMD_FIFO_WIDTH-288-1 downto BLIT_CMD_FIFO_WIDTH-320)	 <= (31 downto 8 => '0') & blit_reg_func;
-
-	blit_cmd_addr_src_0			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-1 downto BLIT_CMD_FIFO_WIDTH-32);
-	blit_cmd_dimx_src_0			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-32-1 downto BLIT_CMD_FIFO_WIDTH-64);
-	blit_cmd_addr_src_1			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-64-1 downto BLIT_CMD_FIFO_WIDTH-96);
-	blit_cmd_dimx_src_1			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-96-1 downto BLIT_CMD_FIFO_WIDTH-128);
-	blit_cmd_addr_dst 			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-128-1 downto BLIT_CMD_FIFO_WIDTH-160);
-	blit_cmd_dimx_dst			<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-160-1 downto BLIT_CMD_FIFO_WIDTH-192);
-	blit_cmd_nx					<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-192-1 downto BLIT_CMD_FIFO_WIDTH-224);
-	blit_cmd_ny					<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-224-1 downto BLIT_CMD_FIFO_WIDTH-256);
-	blit_cmd_CC					<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-256-1 downto BLIT_CMD_FIFO_WIDTH-288);
-	blit_cmd_func				<= blit_cmd_dout(BLIT_CMD_FIFO_WIDTH-288-1 downto BLIT_CMD_FIFO_WIDTH-320);
-
-	blit_cmd_avail 				<= not blit_cmd_empty;
-	blit_cmd_bsy				<= blit_cmd_full;
-	blit_cmd_re					<= blit_finish_strobe(0);
-	blit_cmd_we 				<= blit_request_set;
-
--- Command FIFO
-inst_blit_cmd_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width	=> NextExpBaseTwo(BLIT_CMD_FIFO_DEPTH),
-		data_width	=> BLIT_CMD_FIFO_WIDTH,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	blit_cmd_we,
-		re			=>	blit_cmd_re,
-		fifo_full	=>	blit_cmd_full,
-		fifo_empty	=>	blit_cmd_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  blit_cmd_din,
-		data_r		=>  blit_cmd_dout
-	);
-
-proc_synced_vga_scan_en:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				vga_scan_dma_en2 <= '0';
-			elsif vga_scan_rdy = '1' then
-				vga_scan_dma_en2 <= vga_scan_dma_en;
-			end if;				
-		end if;
-	end process;	
-
-	ADDR_O_scan			<= front + (to_unsigned(pixel_cnt, 29) & "000");
-
-proc_scan_addr:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			bufchg			<= '0';
-			if vga_scan_dma_en2 = '0' then
-				pixel_cnt	<= 0;
-				front		<= host_fb_front;
-			elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
-				if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
-					pixel_cnt 	<= pixel_cnt + 1;
-				else
-					pixel_cnt	<= 0;
-					front		<= host_fb_back;
-					bufchg		<= '1';
-				end if;	
- 			end if;	
-			vga_fb_front	<= front;
- 			vga_fb_back		<= back;
-		end if;
-	end process;	
-	
----------------------------------------------------------------------------------
-inst_vga_backend : entity work.vga_backend
-	GENERIC MAP
-	(
-		tsvga			=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		sys_rst			=> RST_I,
-		sys_clk			=> CLK_I,
-		
-		-- Color channels
-		color_in		=> color_in,
-		color_op		=> color_op,
-		color_en		=> color_en,
-
-		-- Control signals
-		ctrl_scan_en	=> ctrl_scan_en,
-
-		-- Status signals
-		stat_vga_rdy	=> stat_vga_rdy,
-		stat_scan		=> stat_scan,
-		stat_hsync		=> stat_hsync,
-		stat_vsync		=> stat_vsync,
-		stat_hready		=> stat_hready,
-		stat_vready		=> stat_vready,
-		stat_hscan		=> stat_hscan,
-		stat_vscan		=> stat_vscan,
-		stat_hpos		=> stat_hpos,
-		stat_vpos		=> stat_vpos,
-		
-		-- VGA domain signals
-		vga_clk_in		=> vga_clk_in,
-		vga_clk_ce		=> vga_clk_ce,
-		vga_red			=> vga_red,
-		vga_green		=> vga_green,
-		vga_blue		=> vga_blue,
-		vga_blank_n		=> vga_blank_n,
-		vga_sync_n		=> vga_sync_n,
-		vga_hsync		=> vga_hsync,
-		vga_vsync		=> vga_vsync
-	);
-	
-	SRDY_O			<= CYC_I; -- and cg_rdy;
-	MRDY_O			<= busin_fifo_rdy; --not fifo_full;
-	STB_O			<= not busout_fifo_empty;
-	ADDR_O			<= busout_fifo_addr_out;
-	MDAT_O			<= busout_fifo_data_out;
-	SEL_O			<= busout_fifo_sel_out;
-	WE_O			<= busout_fifo_we_out;
-
-	odd_pixel		<= to_unsigned(stat_hpos, odd_pixel'length);
-	ctrl_scan_en	<= '1';
-	color_en(0)		<= not fifo_empty;
-	color_en(1)		<= cg_draw;
-	color_in(0)		<= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32));
-	color_in(1)		<= cg_color; --(X"FF", X"FF", X"FF", X"FF");	-- white opaque
-	color_op		<= op_over;
-	vga_scan_rdy	<= stat_hready and stat_vready;
-	
--- SCAN line FIFO
-inst_linefifo: entity work.fifo_async
-	GENERIC MAP 
-	(
-		addr_width			=> NextExpBaseTwo(fifo_depth),
-		data_width			=> 64,
-		almost_full_thresh	=> fifo_almost_full_thresh,
-		almost_empty_thresh	=> fifo_almost_empty_thresh
-	)
-	PORT MAP
-	(
-		rst				=> RST_I,
-		clk_w			=> CLK_I,
-		clk_r			=> vga_clk_in,
-		we				=> fifo_color_we,
-		re				=> fifo_color_re,
-		data_w			=> fifo_color_in,
-		data_r			=> fifo_color_out,
-		fifo_full		=> fifo_full,
-		fifo_empty		=> fifo_empty,
-		fifo_afull		=> fifo_almost_full,
-		fifo_aempty		=> fifo_almost_empty
-		
-	);
-
-	fifo_color_in		<= busin_fifo_dout;
-	fifo_color_re		<= stat_scan and odd_pixel(0);
-	fifo_color_we		<= busin_fifo_dout_vld and CYC_O_scan;		-- TODO:
-
-
--- Bus input FIFO
-inst_busin_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> 2,
-		data_width			=> busin_fifo_din'length,
-		do_last_read_update	=> true
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	busin_fifo_we,
-		re			=>	busin_fifo_re,
-		fifo_full	=>	busin_fifo_full,
-		fifo_empty	=>	busin_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  busin_fifo_din,
-		data_r		=>  busin_fifo_dout
-	);
-	busin_fifo_rdy		<= not busin_fifo_full;
-	busin_fifo_din		<= MDAT_I;
-	busin_fifo_we		<= ACK_I and bus_cycle_en and bus_read_en;
-	busin_fifo_dout_vld	<= not busin_fifo_empty;
-	busin_fifo_re		<= not fifo_full when CYC_O_scan = '1' else CYC_O_blit_src;
-	
--- Bus output FIFO
-inst_busout_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> 2,
-		data_width			=> busout_fifo_din'length,
-		do_last_read_update	=> false
-	)
-	PORT MAP
-	(
-		rst			=>	RST_I,
-		clk			=>	CLK_I,
-		we			=>	busout_fifo_we,
-		re			=>	busout_fifo_re,
-		fifo_full	=>	busout_fifo_full,
-		fifo_empty	=>	busout_fifo_empty,
-		fifo_afull	=>	open,
-		fifo_aempty	=>	open,
-		data_w		=>  busout_fifo_din,
-		data_r		=>  busout_fifo_dout
-	);
-
-	blit_const_color_en	<= blit_cmd_func(0);
-
-	busout_fifo_rdy		<= not busout_fifo_full;
-	busout_fifo_re		<= not busout_fifo_empty and SRDY_I;
-	busout_fifo_we		<= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
-	busout_fifo_data_in	<= (blitfifo_dout_1 & blitfifo_dout_0) when blit_const_color_en = '0' else (blit_cmd_CC & blit_cmd_CC);
-	busout_fifo_addr_in	<= 	ADDR_O_blit_src when CYC_O_blit_src = '1' else
-							ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
-							ADDR_O_scan;
-	busout_fifo_sel_in	<= blit_dst_be;
-	busout_fifo_we_in	<= CYC_O_blit_dst;
-	request_en			<= bus_cycle_en and busout_fifo_we and busout_fifo_rdy;
-	CYC_O				<= bus_cycle_en;
-	
-------------------------------------------------------------------------------------
--- Bus request counter
-------------------------------------------------------------------------------------
-proc_bus_request_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_cnt_rst = '1' then
-				request_cnt	<= (others => '0');
-			elsif request_en = '1' then
-				request_cnt <= request_cnt + 1;
-			end if;	
-		end if;
-	end process;	
-		
-proc_bus_read_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_cnt_rst = '1' then
-				read_cnt	<= (others => '0');
-			elsif busin_fifo_dout_vld = '1' then
-				read_cnt <= read_cnt + 1;
-			end if;	
-		end if;
-	end process;	
-
-proc_bus_read_finish:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			bus_read_fin <= '0';
-			if read_cnt = request_cnt then
-				bus_read_fin <= '1';
-			end if;
-		end if;
-	end process;	
-
-------------------------------------------------------------------------------------
--- VGA master FSM	
-------------------------------------------------------------------------------------
-vga_master_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s	<= init;
-			else
-				s	<= sn;
-			end if;
-		end if;
-	end process;	
-
-vga_master:
-	process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_empty, blit_request, blit_dst_suspend, blit_chunk_full, blitfifo_dout_vld, blit_src_finish, blitfifo_empty_read, blit_dst_finish, blit_const_color_en)
-	begin
-	
-	CYC_O_scan		<= '0';
-	STB_O_scan		<= '0';
-	CYC_O_blit_src	<= '0';
-	STB_O_blit_src	<= '0';
-	CYC_O_blit_dst	<= '0';
-	STB_O_blit_dst	<= '0';
-	request_cnt_rst	<= '0';
-	bus_read_en		<= '0';
-	bus_cycle_en	<= '0';
-	
-	sn				<= s;
-	case s is
-		when init =>
-		if stat_vga_rdy = '1' then
-			sn	<= rdy;
-		end if;
-		
-		when rdy =>
-		request_cnt_rst	<= '1';
-		if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
-			sn				<= scan_bus_request;
-		elsif blit_request = '1' then	-- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
-			sn	<= blit_dst_bus_request;
-			if blitfifo_dout_vld = '0' or blit_dst_suspend = '1' then
-				sn	<= blit_src_bus_request;
-				if blit_const_color_en = '1' then
-					sn	<= const_dst_bus_request;
-				end if;
-			end if;
-		end if;
-		
-		when scan_bus_request =>
-			bus_cycle_en	<= '1';
-			CYC_O_scan		<= '1';
-			STB_O_scan		<= '1';
-			bus_read_en		<= '1';
-			if fifo_almost_full = '1' then
-				sn <= scan_bus_read;
-			end if;	
-			
-		when scan_bus_read =>
-			bus_cycle_en	<= '1';
-			CYC_O_scan		<= '1';
-			bus_read_en		<= '1';
-			if bus_read_fin = '1' then
-				sn	<= rdy;
-			end if;	
-
-		when blit_src_bus_request =>
-			bus_cycle_en	<= '1';
-			bus_read_en		<= '1';
-			CYC_O_blit_src	<= '1';
-			STB_O_blit_src	<= '1';
-			if blit_chunk_full = '1' or blit_src_finish = '1' then
-				STB_O_blit_src	<= '0';
-				sn 				<= blit_src_bus_read;
-			end if;	
-
-		when blit_src_bus_read =>
-			bus_cycle_en	<= '1';
-			bus_read_en		<= '1';
-			CYC_O_blit_src	<= '1';
-			if bus_read_fin = '1' then
-				sn	<= rdy;
-			end if;	
-
-		when blit_dst_bus_request =>
-			bus_cycle_en	<= '1';
-			CYC_O_blit_dst	<= '1';
-			STB_O_blit_dst	<= '1';
-			if blitfifo_empty_read = '1' or blitfifo_dout_vld = '0' or blit_dst_finish = '1' then
-				STB_O_blit_dst	<= '0';
-				sn				<= bus_fin;
-			end if;	
-
-		when const_dst_bus_request =>
-			bus_cycle_en	<= '1';
-			CYC_O_blit_dst	<= '1';
-			STB_O_blit_dst	<= '1';
-			if blit_chunk_full = '1' or blit_dst_finish = '1' then
-				STB_O_blit_dst	<= '0';
-				sn 				<= bus_fin;
-			end if;	
-
-		when bus_fin =>
-			bus_cycle_en	<= '1';
-			if busout_fifo_empty = '1' then
-				sn	<= rdy;
-			end if;	
-
-		when others =>
-			sn	<= rdy;
-		
-		end case;
-	end process;
-	
----------------------------------------------------------------------------------
--- BLITTER
----------------------------------------------------------------------------------
-proc_blit_complete_int_flag:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or (blit_complete_int = '1' and blit_complete_int_ack = '1') then
-				blit_complete_int	<= '0';
-			elsif blit_finish_strobe(2) = '1' or (blit_complete_int = '0' and blit_complete_int_ack = '1') then
-				blit_complete_int	<= '1';
-			end if;
-		end if;
-	end process;	
-
-proc_blit_cmd_empty_int_flag:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or (blit_cmd_empty_int = '1' and blit_cmd_empty_int_ack = '1') then
-				blit_cmd_empty_int	<= '0';
-			elsif (blit_finish_strobe(2) = '1' and blit_cmd_avail = '0') or (blit_cmd_empty_int = '0' and blit_cmd_empty_int_ack = '1') then
-				blit_cmd_empty_int	<= '1';
-			end if;
-		end if;
-	end process;	
-
-proc_irq:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if vga_scan_dma_en2 = '0' or bufchg_flag_ack = '1' then
-				bufchg_flag	<= '0';
-			elsif bufchg = '1' then
-				bufchg_flag	<= '1';
-			end if;
-			INT_O		<= (bufchg_flag and bufchg_irq_en)
-						or (blit_complete_int and blit_complete_int_en)
-						or (blit_cmd_empty_int and blit_cmd_empty_int_en);
-		end if;
-	end process;	
-
-proc_blit_reset:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				blit_reset		<= '1';
-				blit_request	<= '0';
-			else
-				blit_reset		<= (blit_cmd_avail and not blit_request) or (blit_request and blit_finish_strobe(0));
-				blit_request	<= blit_cmd_avail;
-			end if;
-		end if;
-	end process;	
-
-proc_blit_chunk_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if request_cnt_rst = '1' then
-				blit_chunk_full <= '0';
-				blit_chunk_cnt	<= BLIT_CHUNK_SIZE-2;
-			elsif request_en = '1' then
-				if blit_chunk_cnt = 0 then
-					blit_chunk_full <= '1';
-				else
-					blit_chunk_cnt 		<= blit_chunk_cnt - 1;
-				end if;
-			end if;
-		end if;
-	end process;	
-
--- BLIT buffer low
-inst_blitfifo_src0: entity work.fifo_sync
-	GENERIC MAP 
-	(
-		addr_width			=> NextExpBaseTwo(BLIT_CHUNK_SIZE),
-		data_width			=> 32,
-		
-		do_last_read_update	=> false
-
-	)
-	PORT MAP
-	(
-		rst				=> blit_reset,
-		clk				=> CLK_I,
-		we				=> blitfifo_we(0),
-		re				=> blitfifo_re(0),
-		data_w			=> blitfifo_din(31 downto 0),
-		data_r			=> blitfifo_dout_0,
-		fifo_full		=> blitfifo_full(0),
-		fifo_empty		=> blitfifo_empty(0),
-		fifo_afull		=> open,
-		fifo_aempty		=> open
-		
-	);
-
--- BLIT buffer high
-inst_blitfifo_src1: entity work.fifo_sync
-	GENERIC MAP 
-	(
-		addr_width			=> NextExpBaseTwo(BLIT_CHUNK_SIZE),
-		data_width			=> 32,
-		
-		do_last_read_update	=> false
-
-	)
-	PORT MAP
-	(
-		rst				=> blit_reset,
-		clk				=> CLK_I,
-		we				=> blitfifo_we(1),
-		re				=> blitfifo_re(1),
-		data_w			=> blitfifo_din(63 downto 32),
-		data_r			=> blitfifo_dout_1,
-		fifo_full		=> blitfifo_full(1),
-		fifo_empty		=> blitfifo_empty(1),
-		fifo_afull		=> open,
-		fifo_aempty		=> open
-		
-	);
-
-	blitfifo_din		<= busin_fifo_dout;
-	blitfifo_write_en	<= busin_fifo_dout_vld and CYC_O_blit_src;
-	blitfifo_read_en	<= busout_fifo_rdy and CYC_O_blit_dst;
-	blitfifo_dout_vld	<= not (blitfifo_empty(0) and blitfifo_empty(1));
-	
----------------------------------------------------------------------------------
-blit_dst_be_gen:
-	process(dst_dbg)
-	begin
-		blit_dst_be <= "11111111";
-		if dst_dbg.UNALIGNED = '1' then
-			if dst_dbg.FIRST = '1' then
-				blit_dst_be <= "00001111";
-			elsif dst_dbg.LAST = '1' then
-				if dst_dbg.PARTIAL = '1' then
-					blit_dst_be <= "11110000";
-				end if;
-			end if;
-		elsif dst_dbg.LAST = '1' then
-			if dst_dbg.PARTIAL = '1' then
-				blit_dst_be <= "00001111";
-			end if;
-		end if;
-	end process;
-
-blitfifo_we_gen:
-	process(fill_dbg, blitfifo_write_en)
-	begin
-		blitfifo_we <= (blitfifo_write_en & blitfifo_write_en);
-		if fill_dbg.UNALIGNED = '1' then
-			if fill_dbg.FIRST = '1' then
-				blitfifo_we <= ('0' & blitfifo_write_en);
-			elsif fill_dbg.LAST = '1' then
-				if fill_dbg.PARTIAL = '1' then
-					blitfifo_we <= (blitfifo_write_en & '0');
-				end if;
-			end if;
-		elsif fill_dbg.LAST = '1' then
-			if fill_dbg.PARTIAL = '1' then
-				blitfifo_we <= ('0' & blitfifo_write_en);
-			end if;
-		end if;
-	end process;
-	
-blitfifo_re_gen:
-	process(dst_dbg, blitfifo_empty, blitfifo_read_en)
-	variable fifo_re : unsigned(1 downto 0);
-	variable empty_read : std_logic;
-	begin
-		fifo_re := (blitfifo_read_en & blitfifo_read_en);
-		if dst_dbg.UNALIGNED = '1' then
-			if dst_dbg.FIRST = '1' then
-				fifo_re := ('0' & blitfifo_read_en);
-			elsif dst_dbg.LAST = '1' then
-				if dst_dbg.PARTIAL = '1' then
-					fifo_re := (blitfifo_read_en & '0');
-				end if;
-			end if;
-		elsif dst_dbg.LAST = '1' then
-			if dst_dbg.PARTIAL = '1' then
-				fifo_re := ('0' & blitfifo_read_en);
-			end if;
-		end if;
-		empty_read			:= (blitfifo_empty(0) and fifo_re(0)) or (blitfifo_empty(1) and fifo_re(1));
-		blitfifo_re			<= fifo_re and not (empty_read & empty_read);
-		blitfifo_empty_read	<= empty_read;
-	end process;
-
-blit_dst_suspend_gen:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or blit_dst_finish = '1' or CYC_O_blit_src = '1' then
-				blit_dst_suspend <= '0';
-			elsif blitfifo_read_en = '1' and blitfifo_empty_read = '1' then
-				blit_dst_suspend <= not (blitfifo_empty(0) and blitfifo_empty(1));
-			end if;
-		end if;
-	end process;	
-
-	fill_dbg.LAST		<= '1' when blit_fill_cnt_x_next = '0' & X"0000_0000" or blit_fill_cnt_x_next(32) = '1' else '0';
-	fill_dbg.PARTIAL	<= blit_fill_cnt_x_next(32);
-
-	blit_fill_cnt_x_next	<= ('0' & blit_fill_cnt_x - 1) when fill_dbg.FIRST = '1' and fill_dbg.UNALIGNED = '1' else ('0' & blit_fill_cnt_x - 2);
-	blit_fill_cnt_y_next	<= ('0' & blit_fill_cnt_y) - 1;
-
--- BLIT Buffer fill address generator
-blitfifo_fill_src_0:
-	process(CLK_I)
-	variable addr_next : unsigned(31 downto 0);
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or blit_reset = '1' then
-				blit_fill_addr		<= blit_cmd_addr_src_0(2) & "00";
-				blit_fill_cnt_x		<= blit_cmd_nx;
-				blit_fill_cnt_y		<= blit_cmd_ny;
-				blit_fill_offset	<= blit_cmd_dimx_src_0(2 downto 0);
-				blit_fill_finish	<= '0';
-				fill_dbg.FIRST		<= '1';
-				fill_dbg.UNALIGNED	<= blit_cmd_addr_src_0(2);
-			elsif blit_request = '1' and blit_fill_finish = '0' and blit_const_color_en = '0' and blitfifo_write_en = '1' then
-				fill_dbg.FIRST		<= '0';
-				if fill_dbg.LAST = '1' then
-					if blit_fill_cnt_y_next = ('0' & X"0000_0000") or blit_fill_cnt_y_next(32) = '1' then
-						blit_fill_finish	<= '1';
-					else
-						addr_next			:= (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_fill_offset;
-						blit_fill_addr		<= addr_next(2 downto 0);
-						blit_fill_offset	<= blit_fill_offset + blit_cmd_dimx_src_0(2 downto 0);
-						blit_fill_cnt_x		<= blit_cmd_nx;
-						blit_fill_cnt_y 	<= blit_fill_cnt_y_next(31 downto 0);
-						fill_dbg.FIRST		<= '1';
-						fill_dbg.UNALIGNED	<= addr_next(2);
-					end if;
-				else
-					blit_fill_cnt_x		<= blit_fill_cnt_x_next(31 downto 0);
-					blit_fill_addr 		<= (others => '0');
-				end if;
-			end if;
-		end if;
-	end process;	
-
-	src_dbg.LAST		<= '1' when blit_src_cnt_x_next = '0' & X"0000_0000" or blit_src_cnt_x_next(32) = '1' else '0';
-	src_dbg.PARTIAL		<= blit_src_cnt_x_next(32);
-	
-	blit_src_addr_next	<= ADDR_O_blit_src + 8;
-	blit_src_cnt_x_next	<= ('0' & blit_src_cnt_x - 1) when src_dbg.FIRST = '1' and src_dbg.UNALIGNED = '1' else ('0' & blit_src_cnt_x - 2);
-	blit_src_cnt_y_next	<= ('0' & blit_src_cnt_y) - 1;
-
--- BLIT Source address generator
-blit_request_addr_src:
-	process(CLK_I)
-	variable addr_next : unsigned(31 downto 0);
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or blit_reset = '1' then
-				ADDR_O_blit_src		<= blit_cmd_addr_src_0(31 downto 2) & "00";
-				blit_src_cnt_x		<= blit_cmd_nx;
-				blit_src_cnt_y		<= blit_cmd_ny;
-				blit_src_offset		<= blit_cmd_dimx_src_0;
-				blit_src_finish		<= '0';
-				src_dbg.FIRST		<= '1';
-				src_dbg.UNALIGNED	<= blit_cmd_addr_src_0(2);
-			elsif blit_request = '1' and blit_src_finish = '0' and blit_const_color_en = '0' and (STB_O_blit_src = '1' and busout_fifo_rdy = '1') then
-				src_dbg.FIRST		<= '0';
-				if src_dbg.LAST = '1' then
-					if blit_src_cnt_y_next = ('0' & X"0000_0000") or blit_src_cnt_y_next(32) = '1' then
-						blit_src_finish	<= '1';
-					else
-						addr_next			:= (blit_cmd_addr_src_0(31 downto 2) & "00") + blit_src_offset;
-						ADDR_O_blit_src		<= addr_next;
-						blit_src_offset		<= blit_src_offset + blit_cmd_dimx_src_0;
-						blit_src_cnt_x		<= blit_cmd_nx;
-						blit_src_cnt_y 		<= blit_src_cnt_y_next(31 downto 0);
-						src_dbg.FIRST		<= '1';
-						src_dbg.UNALIGNED	<= addr_next(2);
-					end if;
-				else
-					ADDR_O_blit_src 	<= blit_src_addr_next;
-					blit_src_cnt_x 		<= blit_src_cnt_x_next(31 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;	
-
-
-	dst_dbg.LAST		<= '1' when blit_dst_cnt_x_next = '0' & X"0000_0000" or blit_dst_cnt_x_next(32) = '1' else '0';
-	dst_dbg.PARTIAL		<= blit_dst_cnt_x_next(32);
-
-	blit_dst_addr_next	<= ADDR_O_blit_dst + 8;
-	blit_dst_cnt_x_next	<= ('0' & blit_dst_cnt_x - 1) when dst_dbg.FIRST = '1' and dst_dbg.UNALIGNED = '1' else ('0' & blit_dst_cnt_x - 2);
-	blit_dst_cnt_y_next	<= ('0' & blit_dst_cnt_y) - 1;
-	
--- BLIT Destination address generator
-blit_request_addr_dst:
-	process(CLK_I)
-	variable addr_next : unsigned(31 downto 0);
-	begin
-		if rising_edge(CLK_I) then
-			blit_finish_strobe	<= blit_finish_strobe(blit_finish_strobe'left-1 downto 0) & '0';
-			if RST_I = '1' then
-				blit_finish_strobe	<= (others =>'0');
-			elsif blit_reset = '1' then
-				ADDR_O_blit_dst		<= blit_cmd_addr_dst(31 downto 2) & "00";
-				blit_dst_cnt_x		<= blit_cmd_nx;
-				blit_dst_cnt_y		<= blit_cmd_ny;
-				blit_dst_offset		<= blit_cmd_dimx_dst;
-				blit_dst_finish		<= '0';
-				dst_dbg.FIRST		<= '1';
-				dst_dbg.UNALIGNED	<= blit_cmd_addr_dst(2);
-			elsif blit_request = '1' and blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
-				dst_dbg.FIRST		<= '0';
-				if dst_dbg.LAST = '1' then
-					if blit_dst_cnt_y_next = ('0' & X"0000_0000") or blit_dst_cnt_y_next(32) = '1' then
-						blit_dst_finish			<= '1';
-						blit_finish_strobe(0)	<= '1';
-					else
-						addr_next			:= (blit_cmd_addr_dst(31 downto 2) & "00") + blit_dst_offset;
-						ADDR_O_blit_dst		<= addr_next;
-						blit_dst_offset		<= blit_dst_offset + blit_cmd_dimx_dst;
-						blit_dst_cnt_x		<= blit_cmd_nx;
-						blit_dst_cnt_y 		<= blit_dst_cnt_y_next(31 downto 0);
-						dst_dbg.FIRST		<= '1';
-						dst_dbg.UNALIGNED		<= addr_next(2);
-					end if;
-				else
-					ADDR_O_blit_dst 	<= blit_dst_addr_next;
-					blit_dst_cnt_x 		<= blit_dst_cnt_x_next(31 downto 0);
-				end if;
-			end if;
-		end if;
-	end process;	
-
----------------------------------------------------------------------------------
--- Character generator
----------------------------------------------------------------------------------
-inst_char_gen : entity work.char_gen
-	GENERIC MAP
-	(
-		tsvga				=> tsvga,
-		CHARACTER_SCALE		=> 1,
-		CHAR_ROM_SIZE_X		=> 8,	-- Pixels
-		CHAR_ROM_SIZE_Y		=> 16,	-- Pixels
-		CHAR_ROM_DEPTH		=> 256,	-- Chars
-		MAX_CHAR_PER_LINE	=> 80,	-- Chars
-		MAX_LINE_PER_FRAME	=> 32,	-- Chars
-		CHAR_SPACING_X		=> 0, 	-- Pixels
-		CHAR_SPACING_Y		=> 0,	-- Pixels
-		SCREEN_OFFSET_X		=> 16,	-- Pixels
-		SCREEN_OFFSET_Y		=> 16	-- Pixels
-	)		
-	PORT MAP
-	(
-	    rst				=> RST_I,
-	    sys_clk			=> CLK_I,
-	    vga_clk			=> vga_clk_in,
-	    ce				=> cg_en,
-	    frame_pulse		=> scan_rdy,
-	    clr_screen		=> cg_clr_screen,
-	    clr_line		=> cg_clr_line,
-	    din				=> cg_din,
-	    dout			=> cg_dout,
-	    ascii_we		=> cg_ascii_we,
-	    posy_we			=> cg_posy_we,
-	    posx_we			=> cg_posx_we,
-	    ready			=> cg_rdy,
-	    scan_pos_x_in	=> stat_hpos,
-	    scan_pos_y_in	=> stat_vpos,
-	   	csr_pos_x_out	=> cg_csr_pos_x,
-	   	csr_pos_y_out	=> cg_csr_pos_y,
-	    char_draw_en	=> cg_draw
-    );
-	scan_rdy			<= stat_hready and stat_vready;
-	cg_en				<= stat_scan;
-
----------------------------------------------------------------------------------
--- JBUS registers
----------------------------------------------------------------------------------
-registers_read: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			ACK_O			<= '0';
-			reg_read_vld	<= '0';
-			if CYC_I = '1' and WE_I = '0' then
-				ACK_O			<= reg_read_vld;
-				reg_read_vld	<= STB_I;
-				
-				SDAT_O		<= (others => '0');
-				case ADDR_I(6 downto 2) is
-
-				-- sys_vga_ctrl
-				-- 0x00
-				when "00000" =>
-					SDAT_O(0)				<= cg_rdy;
-					SDAT_O(1)				<= vga_scan_dma_en;
-					SDAT_O(2)				<= bufchg_irq_en;
-					SDAT_O(3)				<= bufchg_flag;
-					SDAT_O(8)				<= blit_cmd_bsy;
-					SDAT_O(9)				<= blit_complete_int;
-					SDAT_O(10)				<= blit_complete_int_en;
-					SDAT_O(11)				<= blit_cmd_empty_int;
-					SDAT_O(12)				<= blit_cmd_empty_int_en;
-					SDAT_O(23 downto 16)	<= blit_reg_func(7 downto 0);
-					SDAT_O(31)				<= blit_request;				-- RO: Blitter is active. Blit jobs avaliable in CMD-FIFO
-					
-				-- sys_vga_ascii
-				-- 0x04
-				when "00001" =>
-					SDAT_O(7 downto 0)	<= cg_dout;
-					
-				-- sys_vga_posx
-				-- 0x08
-				when "00010" =>
-					SDAT_O(7 downto 0)	<= to_unsigned(cg_csr_pos_x, 8);
-
-				-- sys_vga_posy
-				-- 0x0C
-				when "00011" =>
-					SDAT_O(7 downto 0)	<= to_unsigned(cg_csr_pos_y, 8);
-
-				-- sys_vga_cgcol
-				-- 0x10
-				when "00100" =>
-					SDAT_O				<= to_unsigned(cg_color);
-
-				-- sys_vga_res
-				-- 0x14
-				when "00101" =>
-					SDAT_O				<= to_unsigned(tsvga.nfps, 8) & to_unsigned(tsvga.ts_v.ncyc_scan, 12) & to_unsigned(tsvga.ts_h.ncyc_scan, 12);
-
-				-- sys_vga_fb_front
-				-- 0x18
-				when "00110" =>
-					SDAT_O				<= vga_fb_front;
-
-				-- sys_vga_fb_back
-				-- 0x1C
-				when "00111" =>
-					SDAT_O				<= vga_fb_back;
-
-				-- sys_blit_descr_src_0
-				-- 0x20
-				when "01000" =>
-					SDAT_O				<= blit_reg_addr_src_0;
-
-				-- 0x24
-				when "01001" =>
-					SDAT_O				<= blit_reg_dimx_src_0;
-
-				-- sys_blit_descr_src_1
-				-- 0x30
-				when "01100" =>
-					SDAT_O				<= blit_reg_addr_src_1;
-
-				-- 0x34
-				when "01101" =>
-					SDAT_O				<= blit_reg_dimx_src_1;
-
-				-- sys_blit_descr_dst
-				-- 0x40
-				when "10000" =>
-					SDAT_O				<= blit_reg_addr_dst;
-
-				-- 0x44
-				when "10001" =>
-					SDAT_O				<= blit_reg_dimx_dst;
-
-				-- sys_blit_reg_nx
-				-- 0x50
-				when "10100" =>
-					SDAT_O				<= blit_reg_nx;
-
-				-- sys_blit_reg_ny
-				-- 0x54
-				when "10101" =>
-					SDAT_O				<= blit_reg_ny;
-
-				-- sys_blit_color
-				-- 0x58
-				when "10110" =>
-					SDAT_O				<= blit_reg_const_color;
-
-				when others => null;
-				end case;
-			end if;
-		end if;	
-	end process;
-
-	
-registers_write:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			cg_ascii_we				<= '0';
-			cg_posy_we				<= '0';
-			cg_posx_we				<= '0';
-			cg_clr_screen			<= '0';
-			cg_clr_line				<= '0';
-			bufchg_flag_ack			<= '0';
-			blit_request_set		<= '0';
-			blit_complete_int_ack	<= '0';
-			blit_cmd_empty_int_ack	<= '0';
-			if RST_I = '1' then
-				cg_din					<= (others => '0');
-				vga_scan_dma_en			<= '0';
-				bufchg_irq_en			<= '0';
-				blit_complete_int_en	<= '0';
-				blit_cmd_empty_int_en	<= '0';
-				blit_reg_func			<= (others => '0');
-				blit_reg_addr_src_0		<= (others => '0');
-				blit_reg_addr_src_1		<= (others => '0');
-				blit_reg_dimx_src_0		<= (others => '0');
-				blit_reg_dimx_src_1		<= (others => '0');
-				blit_reg_addr_dst		<= (others => '0');
-				blit_reg_dimx_dst		<= (others => '0');
-				blit_reg_nx				<= (others => '0');
-				blit_reg_ny				<= (others => '0');
-				host_fb_front			<= (others => '0');
-				host_fb_back			<= (others => '0');
-				cg_color				<= (X"FF", X"FF", X"FF", X"FF");
-			elsif (STB_I and CYC_I and WE_I) = '1' then
-				case ADDR_I(6 downto 2) is
-				
-				-- sys_vga_ctrl
-				-- 0x00
-				when "00000" =>
-					vga_scan_dma_en			<= SDAT_I(1);
-					bufchg_irq_en			<= SDAT_I(2);
-					bufchg_flag_ack			<= SDAT_I(3);
-					cg_clr_screen			<= SDAT_I(4);
-					cg_clr_line				<= SDAT_I(5);
-					blit_request_set		<= SDAT_I(8);
-					blit_complete_int_ack	<= SDAT_I(9);
-					blit_complete_int_en	<= SDAT_I(10);
-					blit_cmd_empty_int_ack	<= SDAT_I(11);
-					blit_cmd_empty_int_en	<= SDAT_I(12);
-					blit_reg_func			<= SDAT_I(23 downto 16);
-					
-				-- sys_vga_ascii
-				-- 0x04
-				when "00001" =>
-					cg_ascii_we		<= '1';
-					cg_din					<= SDAT_I(7 downto 0);
-					
-				-- sys_vga_posx
-				-- 0x08
-				when "00010" =>
-					cg_posx_we				<= '1';
-					cg_din					<= SDAT_I(7 downto 0);
-
-				-- sys_vga_posy
-				-- 0x0C
-				when "00011" =>
-					cg_posy_we				<= '1';
-					cg_din					<= SDAT_I(7 downto 0);
-
-				-- sys_vga_cgcol
-				-- 0x10
-				when "00100" =>
-					cg_color				<= to_color_t(SDAT_I(31 downto 0));
-
-				-- sys_vga_fb_front
-				-- 0x18
-				when "00110" =>
-					host_fb_front			<= SDAT_I(31 downto 3) & "000";
-					
-				-- sys_vga_fb_back
-				-- 0x1C
-				when "00111" =>
-					bufchg_flag_ack	<= '1';
-					host_fb_back			<= SDAT_I(31 downto 3) & "000";
-					
-				-- sys_blit_descr_src_0
-				-- 0x20
-				when "01000" =>
-					blit_reg_addr_src_0		<= SDAT_I(31 downto 0);
-
-				-- 0x24
-				when "01001" =>
-					blit_reg_dimx_src_0		<= SDAT_I(29 downto 0) & "00";
-
-				-- sys_blit_descr_src_1
-				-- 0x30
-				when "01100" =>
-					blit_reg_addr_src_1		<= SDAT_I(31 downto 0);
-
-				-- 0x34
-				when "01101" =>
-					blit_reg_dimx_src_1		<= SDAT_I(29 downto 0) & "00";
-
-				-- sys_blit_descr_dst
-				-- 0x40
-				when "10000" =>
-					blit_reg_addr_dst		<= SDAT_I(31 downto 0);
-					
-				-- 0x44
-				when "10001" =>
-					blit_reg_dimx_dst		<= SDAT_I(29 downto 0) & "00";
-
-				-- sys_blit_reg_nx
-				-- 0x50
-				when "10100" =>
-					blit_reg_nx				<= SDAT_I;
-
-				-- sys_blit_reg_ny
-				-- 0x54
-				when "10101" =>
-					blit_reg_ny				<= SDAT_I;
-									
-				-- sys_blit_color
-				-- 0x58
-				when "10110" =>
-					blit_reg_const_color	<= SDAT_I;
-
-				when others => null;
-				end case;
-
-			end if;
-		end if;
-	end process;
-
-	---------------------------------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd
deleted file mode 100644
index 56e4384..0000000
--- a/lib/VGA_ctrl/src/vga_sync.vhd
+++ /dev/null
@@ -1,127 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:15:39 10/21/05
--- Design Name:    
--- Module Name:    fsm_scan - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.vga_types.all;
-
-entity vga_sync is
-	Generic
-	(
-		ts	: scan_timespec_t := (4,2,1,3,'0')
-	);
-	Port
-	(
-		rst			: in std_logic;
-		clk			: in std_logic;
-		ce			: in std_logic;
-		pos			: out natural range 0 to ts.ncyc_scan-1;
-		sync		: out std_logic;
-		is_scan		: out std_logic;
-		rdy_scan	: out std_logic
-	);
-	end vga_sync;
-
-architecture Behavioral of vga_sync is
-
-	type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back); 
-
-	-- Counter
-	signal state, next_state	: timing_state_t;
-	signal count_srst			: std_logic;
-	signal count				: natural range 0 to ts.ncyc_scan-1;
-
-begin
-
-	pos	<= count;
-	
----------------------------------------------------------------------------------------------
-counter:
-	process (clk)
-	begin
-		if rising_edge(clk) then
-			if ce = '1' then
-				if count_srst = '1' then
-					count <= 0;
-				else	
-					count <= count + 1;
-				end if;
-			end if;	
-		end if;
-	end process;	
-
----------------------------------------------------------------------------------------------
-SYNC_TIMING:
-process (state, count)
-	begin
-		count_srst	<= '0';
-		rdy_scan	<= '0';
-		is_scan		<= '0';
-		sync		<= '0';
-
-		next_state <= state;  --default is to stay in current state
-
-		case (state) is
-		
-		when st_init =>
-			count_srst	<= '1';
-			next_state	<= st_front;
-		when st_front =>
-			if count = ts.ncyc_porch_front - 1 then
-				count_srst	<= '1';
-				next_state <= st_sync;
-			end if;
-		when st_sync =>
-			sync	<= '1';
-			if count = ts.ncyc_sync_pulse - 1 then
-				count_srst	<= '1';
-				next_state	<= st_back;
-			end if;
-		when st_back =>
-			if count = ts.ncyc_porch_back - 1 then
-				count_srst	<= '1';
-				next_state	<= st_scan;
-            end if;
-         when st_scan =>
-			is_scan  <= '1';
-			if count = ts.ncyc_scan - 1 then
-				count_srst	<= '1';
-				rdy_scan	<= '1';
-				next_state	<= st_front;
-			end if;
-		when others =>	
-			next_state <= st_init;
-			
-		end case;      
-	end process;
-
-SYNC_TIMING_NEXT:
-	process (rst, clk)
-	begin
-		if rst = '1' then
-			state <= st_init;
-		elsif rising_edge(clk) and ce = '1' then
-			state <= next_state;
-		end if;
-	end process;
-
----------------------------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd
deleted file mode 100644
index c110652..0000000
--- a/lib/VGA_ctrl/src/vga_timing.vhd
+++ /dev/null
@@ -1,102 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:25:45 10/15/05
--- Design Name:    
--- Module Name:    vga_ctrl_core - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-use work.vga_types.all;
-
-entity vga_timing is
-	Generic
-	(
-		tsvga		: vga_timespec_t	:= ts_vga_800_600_72
-	);
-	Port
-	(
-		sys_rst			: in std_logic;
-		vga_clk			: in std_logic;
-		vga_ce			: in std_logic;
-		sync_h			: out std_logic;
-		sync_v			: out std_logic;
-		scan_pos_h		: out natural range 0 to tsvga.ts_h.ncyc_scan-1;
-		scan_pos_v		: out natural range 0 to tsvga.ts_v.ncyc_scan-1;
-		is_scan_h		: out std_logic;
-		is_scan_v		: out std_logic;
-		scan_rdy_h		: out std_logic;
-		scan_rdy_v		: out std_logic
-	);
-end vga_timing;
-
-architecture Behavioral of vga_timing is
-
-	---------------------------------------------------------------------------------------------
-	signal is_scan_h_i		: std_logic;
-	signal is_scan_v_i		: std_logic;
-	signal scan_rdy_h_i		: std_logic;
-	signal scan_rdy_v_i		: std_logic;
-	signal sync_h_i			: std_logic;
-	signal sync_v_i			: std_logic;
-	
-	---------------------------------------------------------------------------------------------
-begin
-
-	is_scan_h	<= is_scan_h_i;
-	is_scan_v	<= is_scan_v_i;
-	scan_rdy_h	<= scan_rdy_h_i;
-	scan_rdy_v	<= scan_rdy_v_i;
-	sync_h		<= sync_h_i;
-	sync_v		<= sync_v_i;
-	
-	---------------------------------------------------------------------------------------------
-	inst_vga_sync_h: entity work.vga_sync 
-	GENERIC MAP
-	(
-		ts => tsvga.ts_h
-	)		
-	PORT MAP
-	(
-		rst			=> sys_rst,
-		clk			=> vga_clk,
-		ce			=> vga_ce,
-		pos			=> scan_pos_h,
-		sync		=> sync_h_i,
-		is_scan		=> is_scan_h_i,
-		rdy_scan	=> scan_rdy_h_i
-	);
-
-	inst_vga_sync_v: entity work.vga_sync 
-	GENERIC MAP 
-	(
-		ts => tsvga.ts_v
-	)
-	PORT MAP
-	(
-		rst			=> sys_rst,
-		clk			=> vga_clk,
-		ce			=> scan_rdy_h_i,
-		pos			=> scan_pos_v,
-		sync		=> sync_v_i,
-		is_scan		=> is_scan_v_i,
-		rdy_scan	=> scan_rdy_v_i
-	);
-
----------------------------------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd
deleted file mode 100644
index e8fa93e..0000000
--- a/lib/VGA_ctrl/src/vga_types.vhd
+++ /dev/null
@@ -1,158 +0,0 @@
---	Package File Template
---
---	Purpose: This package defines supplemental types, subtypes, 
---		 constants, and functions 
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package vga_types is
-	
-	-- Constants
-	constant	VGA_NUM_CH		: natural := 2;
-	
-	-- Types
-	type color_range_t is (r, g, b, a);
-	type color_t is array (color_range_t) of unsigned(7 downto 0);
-	type color_array_t is array (0 to VGA_NUM_CH-1) of color_t;
-
-	type color_op_t is (op_over, op_xor, op_alpha);
-	
-	type scan_timespec_t is
-	record
-		ncyc_scan				: integer;
-		ncyc_porch_front		: integer;
-		ncyc_sync_pulse			: integer;
-		ncyc_porch_back			: integer;
-		sync_polarity			: std_logic;
-	end record;
-
-	type vga_timespec_t is
-	record
-		f_pxl_clk              : integer;
-		nfps                   : integer;
-		ts_h                   : scan_timespec_t;
-		ts_v                   : scan_timespec_t;
-	end record;
-
-	-----------------------------------------------------------------------
-	-- Common timimg specifications
-	-----------------------------------------------------------------------
-	-- For test bench (not for H/W use)
-	constant ts_vga_testbench : vga_timespec_t :=
-	(
-		f_pxl_clk              => 40E6,
-		nfps                   => 6,
-		ts_h                   => (80,5,2,3,'0'),
-		ts_v                   => (60,4,2,3,'0')
-	);
-
-	-- 640 x 480 @ 60 Hz (not recommended)
-	constant ts_vga_640_480_60 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 25175000,
-		nfps                   => 60,
-		ts_h                   => (640,16,96,48,'0'),
-		ts_v                   => (480,11,2,31,'0')
-	);
-
-	-- 640 x 480 @ 72 Hz (not recommended)
-	constant ts_vga_640_480_72 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 31500000,
-		nfps                   => 72,
-		ts_h                   => (640,24,40,128,'0'),
-		ts_v                   => (480,9,3,28,'0')
-	);
- 
-	-- 800 x 600 @ 60 Hz (OK)
-	constant ts_vga_800_600_60 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 40000000,
-		nfps                   => 60,
-		ts_h                   => (800,40,128,88,'0'),
-		ts_v                   => (600,1,4,23,'0')
-	);
-	
-	-- 800 x 600 @ 72 Hz (OK)
-	constant ts_vga_800_600_72 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 50000000,
-		nfps                   => 72,
-		ts_h                   => (800,56,120,64,'0'),
-		ts_v                   => (600,37,6,23,'0')
-	);
-
-	-- 1024 x 768 @ 60 Hz (Noisy)
-	constant ts_vga_1024_768_60 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 65000000,
-		nfps                   => 60,
-		ts_h                   => (1024,24,136,160,'0'),
-		ts_v                   => (768,3,6,29,'0')
-	);
-
-	-- 1024 x 768 @ 70 Hz (OK)
-	constant ts_vga_1024_768_70 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 75000000,
-		nfps                   => 70,
-		ts_h                   => (1024,24,136,144,'0'),
-		ts_v                   => (768,3,6,29,'0')
-	);
-
-	-- 1280 x 1024 @ 70 Hz (Noisy)
-	constant ts_vga_1280_1024_70 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 125000000,
-		nfps                   => 70,
-		ts_h                   => (1280,16,176,192,'0'),
-		ts_v                   => (1024,3,3,42,'0')
-	);
-
-	-- 1280 x 1024 @ 72 Hz (OK)
-	constant ts_vga_1280_1024_72 : vga_timespec_t :=
-	(
-		f_pxl_clk              => 130000000,
-		nfps                   => 72,
-		ts_h                   => (1280,32,160,224,'0'),
-		ts_v                   => (1024,2,2,33,'0')
-	);
-
-	-- Functions
-	function to_color_t(x : unsigned) return color_t;
-	function to_unsigned(x : color_t) return unsigned;
-	
-end vga_types;
-
-
-package body vga_types is
-
-	function to_color_t(x : unsigned) return color_t is
-	variable result : color_t;
-	begin
-		result(r)	:= x(x'right+7 downto x'right+0);
-		result(g)	:= x(x'right+15 downto x'right+8);
-		result(b)	:= x(x'right+23 downto x'right+16);
-		result(a)	:= x(x'right+31 downto x'right+24);
-		
-		return result;
-	end to_color_t;
-	
-	function to_unsigned(x : color_t) return unsigned is
-	variable result : unsigned(31 downto 0);
-	begin
-		result(7 downto 0)		:= x(r);
-		result(15 downto 8)		:= x(g);
-		result(23 downto 16)	:= x(b);
-		result(31 downto 24)	:= x(a);
-
-		return result;
-	end to_unsigned;
-
-end vga_types;
-
-
diff --git a/lib/VGA_ctrl/todo.txt b/lib/VGA_ctrl/todo.txt
deleted file mode 100644
index e20e96d..0000000
--- a/lib/VGA_ctrl/todo.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-2009-11-04
-- char_gen.vhdl: add csr_posx_out, csr_posy_out to port. Make it register readable (done 2009-11-04)
-- several async. resets recognized. Sync. resets better?
-- Make screen width, screen height and FPS register readable (done 2009-11-04)
-
-2009-11-08
-- Double-buffering to reduce artifacts on buffer write by host and buffer read by VGA master.
-  currently double-buffer can only be updatetd if msten = 0. Buffer updates should be always possible
-  for large screen change, which need more time than one frame. (done 2009-11-08)
-- VGA-INT every n-th buffer change?
-
-2009-11-11
-- adding a blitter for blockcopy of whole frame or box region. (done 2009-11-22)
-- Adding blitter capability to read from three sources (image 1, image 2 and mask), manipulate and store back of whole frame or box region
-
-2009-11-25
-- Adding blitter capability to read/write single 32-Bit words (and even bytes)
-- Adding blitter capability to blit constant color
-- Increase BLIT_CHUNKSIZE to LINEFIFO_DEPTH/2 for more performance (needs modification to FSM)
-
-
diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo b/lib/ac97_ctrl/sim/tb_ac97_wb.fdo
deleted file mode 100644
index bbdc249..0000000
--- a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo
+++ /dev/null
@@ -1,20 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../misc/dpram_1w1r_dist.vhd"
-vcom -explicit  -93 "../../FIFO/src/fifo_sync_dist.vhd"
-vcom -explicit  -93 "../../misc/singleshot.vhd"
-vcom -explicit  -93 "../src/core/ac_out.vhd"
-vcom -explicit  -93 "../src/core/ac_in.vhd"
-vcom -explicit  -93 "../src/core/ac_io.vhd"
-vcom -explicit  -93 "../src/core/ac97_wb.vhd"
-vcom -explicit  -93 "../src/tb_ac97_wb.vhd"
-vsim -t 1ps   -lib work tb_ac97_wb
-do {tb_ac97_wb.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo b/lib/ac97_ctrl/sim/tb_ac97_wb.wdo
deleted file mode 100644
index f7e1885..0000000
--- a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo
+++ /dev/null
@@ -1,77 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Logic /tb_ac97_wb/rst_o
-add wave -noupdate -format Logic /tb_ac97_wb/int_i
-add wave -noupdate -format Logic /tb_ac97_wb/cyc_o
-add wave -noupdate -format Logic /tb_ac97_wb/stb_o
-add wave -noupdate -format Logic /tb_ac97_wb/we_o
-add wave -noupdate -format Logic /tb_ac97_wb/ack_i
-add wave -noupdate -format Logic /tb_ac97_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ac97_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_o
-add wave -noupdate -format Logic /tb_ac97_wb/dout_rst
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dout_reg
-add wave -noupdate -format Literal /tb_ac97_wb/dout_cnt
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_bit_clk
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_reset_n
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_out
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_ssync
-add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_in
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_reg_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_pending
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_addr
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_cmd_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_tx_pcm_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/stat_reg
-add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_reg_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_pending
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_tx_pcm_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_rx_pcm_addr
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_sync_strobe
-add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_slot_valid
-add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_ready
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_data_start
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_status
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_frame
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_frame_valid
-add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_tx
-add wave -noupdate -format Literal /tb_ac97_wb/uut/request
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_dout
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_full
-add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_empty
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_data_start
-add wave -noupdate -format Logic /tb_ac97_wb/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_dout
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_re
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_we
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_full
-add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac97_stat
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {200000401 ps} 0} {{Cursor 2} {699514236 ps} 0} {{Cursor 4} {4999959266 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {699260742 ps} {700038909 ps}
diff --git a/lib/ac97_ctrl/sim/tb_ac_in.fdo b/lib/ac97_ctrl/sim/tb_ac_in.fdo
deleted file mode 100644
index fd7fb1f..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_in.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit  -93 "../../../lib/src/misc/singleshot.vhd"
-vcom -explicit  -93 "../src/core/ac_out.vhd"
-vcom -explicit  -93 "../src/core/ac_in.vhd"
-vcom -explicit  -93 "../src/tb_ac_in.vhd"
-vsim -t 1ps   -lib work tb_ac_in
-do {tb_ac_in.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac_in.wdo b/lib/ac97_ctrl/sim/tb_ac_in.wdo
deleted file mode 100644
index a7d0e35..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_in.wdo
+++ /dev/null
@@ -1,43 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_in/uut/rst
-add wave -noupdate -format Logic /tb_ac_in/uut/clk
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_status
-add wave -noupdate -divider {AC97 lines}
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in
-add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data
-add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag
-add wave -noupdate -format Literal /tb_ac_in/uut/sac
-add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt
-add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg
-add wave -noupdate -format Logic /tb_ac_in/uut/stat_read
-add wave -noupdate -format Logic /tb_ac_in/uut/host_update
-add wave -noupdate -format Logic /tb_ac_in/uut/slot_end
-add wave -noupdate -format Logic /tb_ac_in/uut/sync_end
-add wave -noupdate -format Logic /tb_ac_in/uut/last_slot
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {52190046 ps} {56168939 ps}
diff --git a/lib/ac97_ctrl/sim/tb_ac_io.fdo b/lib/ac97_ctrl/sim/tb_ac_io.fdo
deleted file mode 100644
index 4b0180f..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_io.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit  -93 "../../../lib/misc/singleshot.vhd"
-vcom -explicit  -93 "../src/core/ac_out.vhd"
-vcom -explicit  -93 "../src/core/ac_in.vhd"
-vcom -explicit  -93 "../src/core/ac_io.vhd"
-vcom -explicit  -93 "../src/tb_ac_io.vhd"
-vsim -t 1ps   -lib work tb_ac_io
-do {tb_ac_io.wdo}
-view wave
-view structure
-view signals
-run 700us
diff --git a/lib/ac97_ctrl/sim/tb_ac_io.wdo b/lib/ac97_ctrl/sim/tb_ac_io.wdo
deleted file mode 100644
index b445bdb..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_io.wdo
+++ /dev/null
@@ -1,51 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_io/uut/rst
-add wave -noupdate -format Logic /tb_ac_io/uut/clk
-add wave -noupdate -format Logic /tb_ac_io/uut/ready
-add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid
-add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data
-add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data
-add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data
-add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we
-add wave -noupdate -divider {AC97 lines}
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out
-add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt
-add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync
-add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0}
-configure wave -namecolwidth 173
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {735 us}
diff --git a/lib/ac97_ctrl/sim/tb_ac_out.fdo b/lib/ac97_ctrl/sim/tb_ac_out.fdo
deleted file mode 100644
index ac9d3c4..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_out.fdo
+++ /dev/null
@@ -1,13 +0,0 @@
-## NOTE:  Do not edit this file.
-## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007
-##
-vlib work
-vcom -explicit  -93 "../../../lib/src/misc/singleshot.vhd"
-vcom -explicit  -93 "../src/core/ac_out.vhd"
-vcom -explicit  -93 "../src/tb_ac_out.vhd"
-vsim -t 1ps   -lib work tb_ac_out
-do {tb_ac_out.wdo}
-view wave
-view structure
-view signals
-run 600us
diff --git a/lib/ac97_ctrl/sim/tb_ac_out.wdo b/lib/ac97_ctrl/sim/tb_ac_out.wdo
deleted file mode 100644
index b9d9a25..0000000
--- a/lib/ac97_ctrl/sim/tb_ac_out.wdo
+++ /dev/null
@@ -1,41 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ac_out/rst
-add wave -noupdate -format Logic /tb_ac_out/clk
-add wave -noupdate -format Logic /tb_ac_out/ce
-add wave -noupdate -divider {Host hand shake}
-add wave -noupdate -format Logic /tb_ac_out/sync_tx
-add wave -noupdate -divider {Command I/F}
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data
-add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we
-add wave -noupdate -divider {PCM I/F}
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data
-add wave -noupdate -format Logic /tb_ac_out/pcm_in_we
-add wave -noupdate -divider {AC97 I/F}
-add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk
-add wave -noupdate -format Logic /tb_ac_out/ac_reset
-add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out
-add wave -noupdate -format Logic /tb_ac_out/ac_ssync
-add wave -noupdate -divider Debug
-add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg
-add wave -noupdate -format Literal /tb_ac_out/uut/sac
-add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt
-add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {544839100 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {532851785 ps} {556826415 ps}
diff --git a/lib/ac97_ctrl/src/core/ac97_wb.vhd b/lib/ac97_ctrl/src/core/ac97_wb.vhd
deleted file mode 100644
index 1b4fb57..0000000
--- a/lib/ac97_ctrl/src/core/ac97_wb.vhd
+++ /dev/null
@@ -1,330 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY ac97_wb IS
-	Generic
-	(
-		fifo_depth		: natural := 8
-	);
-	Port
-	(
-		-- J-Bus domain
-		CLK_I			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		INT_O			: out STD_LOGIC;
-		
-		-- AC97 domain
-		ac97_sdata_in	: in std_logic;
-		ac97_bit_clk	: in  std_logic;          
-		ac97_reset_n	: out std_logic;
-		ac97_sdata_out	: out std_logic;
-		ac97_ssync		: out std_logic
-	);
-END ac97_wb;
-
-ARCHITECTURE behavior OF ac97_wb IS
-
-	constant ac_data_width			: natural := 20;
-	constant pcm_data_width			: natural := 18;
-	constant stat_data_width		: natural := 16;
-	signal cmd_reg_we				: std_logic;
-	signal cmd_pending				: std_logic;
-	signal ac_cmd_data				: unsigned(ac_data_width-1 downto 0);
-	signal ac_cmd_addr				: unsigned(ac_data_width-1 downto 0);
-	signal ac_cmd_we				: std_logic;
-	signal ac_tx_pcm_we				: std_logic;
-
-	signal stat_reg					: unsigned(stat_data_width-1 downto 0);
-	signal stat_reg_re				: std_logic;
-	signal stat_valid				: std_logic;
-	signal stat_pending				: std_logic;
-	signal ac_stat_data				: unsigned(ac_data_width-1 downto 0);
-	signal ac_stat_addr				: unsigned(ac_data_width-1 downto 0);
-	signal ac_stat_read				: std_logic;
-	signal ac_stat_valid			: std_logic;
-
-	signal ac_tx_pcm_data			: unsigned(ac_data_width-1 downto 0);
-	signal ac_tx_pcm_addr			: unsigned (3 downto 0);
-	signal ac_rx_pcm_data			: unsigned(ac_data_width-1 downto 0);
-	signal ac_rx_pcm_addr			: unsigned (3 downto 0);
-	signal ac_sync_strobe			: unsigned(0 to 2);
-	signal ac_slot_valid			: unsigned(0 to 12);
-	signal ac_ready					: std_logic;
-	signal rx_frame_valid			: std_logic;
-	signal sync_frame				: std_logic;
-	signal sync_tx					: std_logic;
-	signal sync_status				: std_logic;
-	signal request					: unsigned(3 to 12);
-
-	signal tx_data_start			: std_logic;
-	signal tx_fifo_din				: unsigned(pcm_data_width-1 downto 0);
-	signal tx_fifo_dout				: unsigned(pcm_data_width-1 downto 0);
-	signal tx_fifo_re				: std_logic;
-	signal tx_fifo_we				: std_logic;
-	signal tx_fifo_full				: std_logic;
-	signal tx_fifo_empty			: std_logic;
-	signal tx_fifo_almost_full		: std_logic;
-	signal tx_fifo_almost_empty		: std_logic;
-
-	signal rx_data_irq				: std_logic;
-	signal rx_data_ack				: std_logic;
-
-	signal ac97_stat				: unsigned(31 downto 0);
-	signal addr_reg					: unsigned(31 downto 0);
-	signal data_reg					: unsigned(31 downto 0);
-	signal int_en_frame_sync		: std_logic;
-	signal int_en_rx				: std_logic;
-	signal int_en_tx				: std_logic;
-	signal rx_en					: std_logic;
-	signal tx_en					: std_logic;
-	signal rx_fifo_rst				: std_logic;
-	signal tx_fifo_rst				: std_logic;
-
-	function GetRequest(slot1 : unsigned) return unsigned is
-	variable res : unsigned(3 to 12);
-	begin
-		res := (others => '0');
-		for i in res'range loop
-			res(i) := not slot1(14-i);
-		end loop;
-		return res;	
-
-	end GetRequest;
-
-	type ac_state_t is (reset, idle, pcm_3, pcm_4);
-	signal rx_state, rx_state_n : ac_state_t;
-
-begin
-
-	SRDY_O			<= CYC_I;
-	INT_O			<= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ;
-	
-	rx_frame_valid	<= ac_slot_valid(0);
-	sync_frame		<= ac_sync_strobe(0);
-	sync_status		<= ac_sync_strobe(1);
-	sync_tx			<= ac_sync_strobe(2);
-	request			<= GetRequest(ac_stat_addr);
-	
-	ac_stat_read	<= not addr_reg(9);
-	ac_stat_valid	<= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0';
-	ac97_stat		<= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending;
-	
-command_logic:
-	process (CLK_I)
-	begin
-	
-		if rising_edge(CLK_I) then
-			ac_cmd_we	<= '0';
-			if RST_I = '1' then
-				cmd_pending		<= '0';
-			elsif cmd_reg_we = '1' and cmd_pending = '0' then
-				cmd_pending		<= '1';
-			elsif (rx_frame_valid and sync_tx) = '1' and cmd_pending = '1' then
-				ac_cmd_we		<= '1';
-				cmd_pending		<= '0';
-			end if;	
-		end if;	
-	end process;
-
-status_logic:
-	process (CLK_I)
-	begin
-	
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				stat_pending	<= '0';
-			elsif cmd_reg_we = '1' and cmd_pending = '0' then
-				stat_pending	<= ac_stat_read;
-			elsif ac_stat_valid = '1' then
-				stat_pending	<= '0';
-			end if;	
-		end if;	
-	end process;
-
-command_register:
-	process (CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if cmd_reg_we = '1' and cmd_pending = '0' then
-				ac_cmd_addr		<= ac_stat_read & addr_reg(8 downto 2) & X"000";
-				ac_cmd_data		<= data_reg(stat_data_width-1 downto 0) & X"0";
-			end if;	
-		end if;	
-	end process;
-
-status_register:
-	process (CLK_I)
-	begin
-	
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				stat_valid		<= '0';
-			elsif stat_pending = '1' and ac_stat_valid = '1' then
-				stat_reg		<= ac_stat_data(ac_data_width-1 downto ac_data_width-stat_data_width);
-				stat_valid		<= '1';
-			elsif stat_reg_re = '1' then
-				stat_valid		<= '0';
-			end if;	
-		end if;	
-	end process;
-
-	-- Instantiate synchronous FIFO
-inst_tx_fifo: entity work.fifo_sync
-	GENERIC MAP
-	(
-		addr_width			=> fifo_depth,
-		data_width			=> pcm_data_width,
-		almost_full_thresh	=> 90*(2**fifo_depth)/100,
-		almost_empty_thresh	=> 10*(2**fifo_depth)/100
-	)
-	PORT MAP
-	(
-		rst			=>	tx_fifo_rst,
-		clk			=>	CLK_I,
-		we			=>	tx_fifo_we,
-		re			=>	tx_fifo_re,
-		fifo_full	=>	tx_fifo_full,
-		fifo_empty	=>	tx_fifo_empty,
-		fifo_afull	=>	tx_fifo_almost_full,
-		fifo_aempty	=>	tx_fifo_almost_empty,
-		data_w		=>  tx_fifo_din,
-		data_r		=>  tx_fifo_dout
-	);
-	tx_fifo_rst		<= not tx_en or RST_I;
-	
-tx_logic:
-	process (CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' or tx_en = '0' then
-				ac_tx_pcm_addr 	<= "0011";
-				tx_data_start	<= '0';
-			elsif sync_tx = '1' and (request(3) and request(4)) = '1' then
-				ac_tx_pcm_addr 	<= "0011";
-				tx_data_start	<= '1';
-			elsif ac_tx_pcm_addr /= "0100" then
-				ac_tx_pcm_addr	<= ac_tx_pcm_addr + 1;
-			else
-				tx_data_start	<= '0';
-			end if;	
-		end if;	
-	end process;
-
-	ac_tx_pcm_we	<= not tx_fifo_empty and tx_data_start;
-	tx_fifo_re		<= ac_tx_pcm_we;
-	
-	tx_fifo_din		<= data_reg(pcm_data_width-1 downto 0);
-	
-	ac_rx_pcm_addr	<= addr_reg(5 downto 2);
-
-rx_logic:
-	process (CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				rx_data_irq	<= '0';
-			elsif rx_frame_valid = '1' and sync_frame = '1' then 
-				if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then
-					rx_data_irq	<= rx_en;
-				end if;
-			elsif rx_data_ack = '1' then
-				rx_data_irq	<= '0';
-			end if;
-		end if;
-	end process;	
-
-inst_ac_io : entity work.ac_io
-    PORT MAP
-    (
-		rst				=> RST_I,
-		clk				=> CLK_I,
-		ready			=> ac_ready,
-		sync_strobe		=> ac_sync_strobe,
-		slot_valid		=> ac_slot_valid,
-		stat_addr		=> ac_stat_addr,
-		stat_data		=> ac_stat_data,
-		rx_pcm_addr		=> ac_rx_pcm_addr,
-		rx_pcm_data		=> ac_rx_pcm_data,
-		cmd_addr		=> ac_cmd_addr,
-		cmd_data		=> ac_cmd_data,
-		cmd_we			=> ac_cmd_we,
-		tx_pcm_addr		=> ac_tx_pcm_addr,
-		tx_pcm_data		=> ac_tx_pcm_data,
-		tx_pcm_we		=> ac_tx_pcm_we,
-		ac_sdata_in		=> ac97_sdata_in,
-		ac_bit_clk		=> ac97_bit_clk,          
-		ac_reset_n		=> ac97_reset_n,
-		ac_sdata_out	=> ac97_sdata_out,
-		ac_ssync		=> ac97_ssync
-	);
-
-	ac_tx_pcm_data		<= tx_fifo_dout & (ac_data_width-pcm_data_width-1 downto 0 => '0');
-
-slave_data_out:
-	process	(CLK_I)
-	begin
-		
-		if rising_edge(CLK_I) then
-			tx_fifo_we		<= '0';
-			stat_reg_re		<= '0';
-			cmd_reg_we		<= '0';
-			rx_data_ack		<= '0';
-			ACK_O			<= '0';
-			if RST_I = '1' then
-				addr_reg			<= (others => '0');
-				int_en_frame_sync	<= '0';
-				int_en_rx			<= '0';
-				int_en_tx			<= '0';
-				tx_en				<= '0';
-				rx_en				<= '0';
-			else
---				DAT_O			<= (others => '-');
-
-				if (STB_I and CYC_I) = '1' then
-					ACK_O		<= not WE_I;
-
-					case ADDR_I(11 downto 10) is 
-
-					when "00" =>
-						DAT_O				<= ac97_stat;
-						if WE_I = '1' then
-							int_en_frame_sync	<= DAT_I(0);
-							int_en_tx			<= DAT_I(1);
-							int_en_rx			<= DAT_I(2);
-							tx_en				<= DAT_I(4);
-							rx_en				<= DAT_I(5);
-						end if;
-					when "01" =>
-						addr_reg			<= ADDR_I;
-						data_reg			<= DAT_I;
-						stat_reg_re			<= not WE_I;
-						cmd_reg_we			<= WE_I;
-						DAT_O				<= (31 downto stat_data_width => '0') & stat_reg;
-
-					when "10" =>
-						rx_data_ack			<= not WE_I;
-						addr_reg			<= ADDR_I;
-						data_reg			<= DAT_I;
-						tx_fifo_we			<= WE_I;
-						DAT_O				<= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width);
-
-					when others => null;
-
-					end case;
-				end if;
-			end if;
-		end if;
-		
-	end process;
-	
-end behavior;
diff --git a/lib/ac97_ctrl/src/core/ac_in.vhd b/lib/ac97_ctrl/src/core/ac_in.vhd
deleted file mode 100644
index a072a9b..0000000
--- a/lib/ac97_ctrl/src/core/ac_in.vhd
+++ /dev/null
@@ -1,309 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    08:27:43 08/26/2006 
--- Design Name: 
--- Module Name:    ac_out - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_in is
-    Port (
-		rst 			: in  std_logic;
-		clk 			: in  std_logic;
-		sync_frame	 	: out std_logic;
-		sync_status	 	: out std_logic;
-		slot_valid		: out unsigned(0 to 12);
-		stat_addr		: out unsigned (19 downto 0);
-		stat_data		: out unsigned (19 downto 0);
-		pcm_out_addr	: in  unsigned (3 downto 0);
-		pcm_out_data	: out unsigned (19 downto 0);
-		ac_reset		: in  std_logic; 
-		ac_bit_clk		: in  std_logic;
-		ac_sdata_in		: in  std_logic;
-		ac_ssync		: in  std_logic
-		);
-end ac_in;
-
-architecture Behavioral of ac_in is
-	
-------------------------------------------------------------------
-COMPONENT singleshot
-GENERIC (mode : integer);
-PORT(
-	rst : IN std_logic;
-	clk : IN std_logic;
-	input : IN std_logic;          
-	output : OUT std_logic
-	);
-END COMPONENT;
-
-------------------------------------------------------------------
-type sac_t is (ac_idle, ac_tag, ac_data);
-subtype bitcnt_t is integer range 0 to 19;
-subtype slotcnt_t is integer range 0 to 12;
-subtype slot_valid_t is UNSIGNED(0 to 12);
-subtype tag_t is UNSIGNED(15 downto 0);
-subtype slot_t is UNSIGNED(19 downto 0);
-type slot_array_t is array (natural range <>) of slot_t;
-
-signal data_array : slot_array_t (1 to 12);
-signal tag : tag_t;
- 
-signal sac, snac : sac_t;
-signal bitcnt : bitcnt_t;
-signal bitcnt_rst, bitcnt_en : STD_LOGIC;
-signal slotcnt : slotcnt_t;
-signal slotcnt_rst, slotcnt_en : STD_LOGIC;
-
-signal rx_reg : slot_t;
-signal stat_read, host_update : STD_LOGIC; 
-signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC; 
-
-------------------------------------------------------------------
-function GetSlotValid(data : tag_t) return slot_valid_t is
-variable res : slot_valid_t := (others => '0');
-begin
-	res := (others => '0');
-	for i in slot_valid_t'range loop
-		res(i) := data(data'left-i);
-	end loop;
-	return res;	
-	
-end GetSlotValid;
-
-------------------------------------------------------------------
-begin
-
--------------------------------------------------------------
--- proc_status_flags
--------------------------------------------------------------
-proc_status_flags:
-process (rst, clk, host_update, tag, data_array)
-begin
-	if rising_edge(clk) then
-		sync_status <= '0';
-		if rst = '1' then
-			slot_valid <= (others => '0');
-			stat_addr <= (others => '0');
-			stat_data <= (others => '0');
-		elsif host_update = '1' then
-			sync_status <= '1';
-			slot_valid <= GetSlotValid(tag);
-			stat_addr <= data_array(1);
-			stat_data <= data_array(2);
-		end if;
-	end if;	
-end process;	
-
--------------------------------------------------------------
--- proc_pcm_data
--------------------------------------------------------------
-proc_pcm_data:
-process (clk, pcm_out_addr, data_array)
-variable slot_id : integer range 0 to 12;
-begin
-	pcm_out_data <= (others => '-');
-	slot_id := to_integer(pcm_out_addr);
-	if (slot_id > 2) then
-		pcm_out_data <= data_array(slot_id);
-	end if;	
-end process;			
-	
--------------------------------------------------------------
--- proc_read_data
--------------------------------------------------------------
-proc_read_data : 
-process (ac_reset, ac_bit_clk, slot_end, slotcnt)
-begin
-
-	if ac_reset = '1' then
-		stat_read <= '0';
-	elsif rising_edge(ac_bit_clk) then
-		stat_read <= '0';
-		if slot_end = '1' and slotcnt /= 0 then
-			data_array(slotcnt) <= rx_reg;
-			if slotcnt = 2 then
-				stat_read <= '1';
-			end if;
-		end if;	
-	end if;	
-end process;
-
--------------------------------------------------------------
--- proc_read_stat
--------------------------------------------------------------
-proc_read_tag : 
-process (ac_reset, ac_bit_clk, sync_end)
-begin
-
-	if ac_reset = '1' then
-		tag <= (others => '0');
-	elsif rising_edge(ac_bit_clk) then
-		if sync_end = '1' then
-			tag <= rx_reg(15 downto 0);
-		end if;	
-	end if;	
-
-end process;
-
--------------------------------------------------------------
--- proc_slot_count
--------------------------------------------------------------
-proc_slot_count:
-process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
-begin
-	if rising_edge(ac_bit_clk) then
-		if slotcnt_rst = '1' then
-			slotcnt <= slotcnt_t'low;
-		elsif slotcnt_en = '1' then
-			if slotcnt /= slotcnt_t'high then
-				slotcnt <= slotcnt + 1;
-			else
-				slotcnt <= slotcnt_t'low;
-			end if;
-		end if;
-	end if;
-end process;	
-
--------------------------------------------------------------
--- proc_bit_count
--------------------------------------------------------------
-proc_bit_count:
-process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
-begin
-	if rising_edge(ac_bit_clk) then
-		if bitcnt_rst = '1' then
-			bitcnt <= bitcnt_t'low;
-		elsif bitcnt_en = '1' then
-			if bitcnt /= bitcnt_t'high then
-				bitcnt <= bitcnt + 1;
-			else
-				bitcnt <= bitcnt_t'low;
-			end if;
-		end if;
-	end if;
-end process;	
-
-------------------------------------------------------------------
-proc_ac_fsm:
-process (bitcnt, slotcnt, sac, ac_ssync)
-begin
-	snac <= sac;
-	bitcnt_rst <= '0';
-	bitcnt_en <= '1';
-	slotcnt_rst <= '0';
-	slotcnt_en <= '0';
-	slot_end <= '0';
-	sync_end <= '0';
-	last_slot <= '0';
-	start_of_frame <= '0';
-	
-	if bitcnt = 19 then 
-		slot_end <= '1';
-	end if;	
-	if slotcnt = 12 and bitcnt = 19 then
-		last_slot <= '1';
-	end if;	
-	
-	case sac is
-	
-		when ac_idle => 
-			bitcnt_rst <= '1';
-			slotcnt_rst <= '1';
-			if (ac_ssync = '1') then
-				snac <= ac_tag;
-			end if;	
-
-		when ac_tag =>
-			if (bitcnt = 0) then
-				start_of_frame <= '1';
-			elsif (bitcnt = 15) then
-				slotcnt_en <= '1';
-				bitcnt_rst <= '1';
-				sync_end <= '1';
-				if (ac_ssync = '0') then
-					snac <= ac_data;
-				else	
-					snac <= ac_idle;
-				end if;	
-			end if;	
-
-		when ac_data =>
-			if bitcnt = 19 then 
-				slotcnt_en <= '1';
-				if slotcnt = 12 then
-					slotcnt_rst <= '1';
-					snac <= ac_tag;
-				end if;	
-			end if;	
-		when others => null;
-	end case;	
-end process;
-
-proc_ac_fsm_next:
-process (ac_reset, ac_bit_clk, snac)
-begin
-	if ac_reset = '1' then
-		sac <= ac_idle;
-	elsif rising_edge(ac_bit_clk) then
-		sac <= snac;
-	end if;
-end process;	
-
--------------------------------------------------------------
--- Receive Shift Register
--------------------------------------------------------------
-process (ac_reset, ac_bit_clk, ac_sdata_in)
-begin
-	if ac_reset = '1' then
-		rx_reg <= (others => '0');
-	elsif falling_edge(ac_bit_clk) then  
-		rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in;
-	end if;	
-end process;
-
-------------------------------------------------------------------
-singleshot_inst1: singleshot 
-GENERIC MAP (
-	mode => 0)		
-PORT MAP(
-	rst => rst,
-	clk => clk,
-	input => stat_read,
-	output => host_update
-);
-
-singleshot_inst2: singleshot 
-GENERIC MAP (
-	mode => 1)		
-PORT MAP(
-	rst => rst,
-	clk => clk,
-	input => start_of_frame,
-	output => sync_frame
-);
-
--------------------------------------------------------------
-
-end Behavioral;
-
diff --git a/lib/ac97_ctrl/src/core/ac_io.vhd b/lib/ac97_ctrl/src/core/ac_io.vhd
deleted file mode 100644
index 211a5ef..0000000
--- a/lib/ac97_ctrl/src/core/ac_io.vhd
+++ /dev/null
@@ -1,189 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    18:29:55 08/26/2006 
--- Design Name: 
--- Module Name:    ac_io - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_io is
-    Port
-    (
-		rst				: in  std_logic;
-		clk				: in  std_logic;
-		ready			: out std_logic;
-		sync_strobe		: out unsigned(0 to 2);
-		slot_valid 		: out unsigned(0 to 12);
-		stat_addr		: out unsigned (19 downto 0);
-		stat_data		: out unsigned (19 downto 0);
-		rx_pcm_addr		: in  unsigned (3 downto 0);
-		rx_pcm_data		: out unsigned (19 downto 0);
-		cmd_addr 		: in  unsigned(19 downto 0);
-		cmd_data		: in  unsigned(19 downto 0);
-		cmd_we			: in  std_logic;
-		tx_pcm_addr		: in  unsigned(3 downto 0);
-		tx_pcm_data		: in  unsigned(19 downto 0);
-		tx_pcm_we		: in  std_logic;
-		ac_sdata_in		: in std_logic;
-		ac_bit_clk		: in  std_logic;          
-		ac_reset_n		: out std_logic;
-		ac_sdata_out	: out std_logic;
-		ac_ssync		: out std_logic
-	);
-end ac_io;
-
-architecture Behavioral of ac_io is
-
-	COMPONENT ac_in
-    Port
-    (
-		rst 			: in  std_logic;
-		clk 			: in  std_logic;
-		sync_frame	 	: out std_logic;
-		sync_status	 	: out std_logic;
-		slot_valid 		: out unsigned(0 to 12);
-		stat_addr		: out unsigned (19 downto 0);
-		stat_data		: out unsigned (19 downto 0);
-		pcm_out_addr	: in  unsigned (3 downto 0);
-		pcm_out_data	: out unsigned (19 downto 0);
-		ac_reset		: in std_logic; 
-		ac_bit_clk		: in  std_logic;
-		ac_sdata_in		: in std_logic;
-		ac_ssync		: in std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT ac_out
-	PORT
-	(
-		rst				: in  std_logic;
-		clk				: in  std_logic;
-		sync_tx		 	: out std_logic;
-		cmd_addr 		: in  unsigned(19 downto 0);
-		cmd_data		: in  unsigned(19 downto 0);
-		cmd_we			: in  std_logic;
-		pcm_in_addr		: in  unsigned(3 downto 0);
-		pcm_in_data		: in  unsigned(19 downto 0);
-		pcm_in_we		: in  std_logic;
-		ac_bit_clk		: in  std_logic;          
-		ac_reset		: in  std_logic;
-		ac_sdata_out	: out std_logic;
-		ac_ssync		: out std_logic
-	);
-	END COMPONENT;
-
-	SIGNAL ac_reset :  std_logic;
-	SIGNAL ssync_rx :  std_logic;
-	SIGNAL ssync_tx :  std_logic;
-	SIGNAL sync_frame :  std_logic;
-	SIGNAL sync_status :  std_logic;
-	SIGNAL sync_tx :  std_logic;
-
-begin
-
-inst_ac_in: ac_in
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		sync_frame => sync_frame,
-		sync_status => sync_status,
-		slot_valid => slot_valid,
-		stat_addr => stat_addr,
-		stat_data => stat_data,
-		pcm_out_addr => rx_pcm_addr,
-		pcm_out_data => rx_pcm_data,
-		ac_reset => ac_reset,
-		ac_bit_clk => ac_bit_clk,
-		ac_sdata_in => ac_sdata_in,
-		ac_ssync => ssync_rx
-	);
-	
-inst_ac_out: ac_out
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		sync_tx => sync_tx,
-		cmd_addr => cmd_addr,
-		cmd_data => cmd_data,
-		cmd_we => cmd_we,
-		pcm_in_addr => tx_pcm_addr,
-		pcm_in_data => tx_pcm_data,
-		pcm_in_we => tx_pcm_we,
-		ac_reset => ac_reset,
-		ac_bit_clk => ac_bit_clk,
-		ac_sdata_out => ac_sdata_out,
-		ac_ssync => ssync_tx
-	);
-
-	------------------------------------------------------------------
-	ready <= not ac_reset;
-	ac_ssync <= ssync_tx;
-	ssync_rx <= ssync_tx;
-	sync_strobe <= sync_frame & sync_status & sync_tx;
-	
-	------------------------------------------------------------------
-	proc_reset_gen:
-	process (rst, clk, ac_bit_clk)
-	type rstate_t is (s0, s1);
-	variable rstate, rstaten : rstate_t;
-	subtype cnt_t is integer range 0 to 999;
-	variable cnt : cnt_t;
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				rstate := s0;
-				cnt := cnt_t'high;
-				ac_reset <= '1';
-				ac_reset_n <= '0';
-			else
-				rstaten := rstate;
-				case rstate is
-					when s0 =>
-					if cnt /= 0 then
-						cnt := cnt - 1;
-					else
-						ac_reset_n <= '1';
-						if ac_bit_clk = '1' then
-							rstaten := s1;
-							cnt := cnt_t'high;
-						end if;	
-					end if;
-					
-					when s1 =>
-					if cnt /= 0 then
-						cnt := cnt - 1;
-					else
-						ac_reset <= '0';
-					end if;
-				end case;
-				rstate := rstaten;
-			end if;
-		end if;
-	end process;	
-	
-	------------------------------------------------------------------
-	
-end Behavioral;
-
diff --git a/lib/ac97_ctrl/src/core/ac_out.vhd b/lib/ac97_ctrl/src/core/ac_out.vhd
deleted file mode 100644
index a770495..0000000
--- a/lib/ac97_ctrl/src/core/ac_out.vhd
+++ /dev/null
@@ -1,276 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    15:41:12 06/05/2007 
--- Design Name: 
--- Module Name:    ac_out - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ac_out is
-    Port (
-		rst				: in  std_logic;
-		clk				: in  std_logic;
-		sync_tx		 	: out std_logic;
-		cmd_addr 		: in  unsigned (19 downto 0);
-		cmd_data		: in  unsigned (19 downto 0);
-		cmd_we			: in  std_logic;
-		pcm_in_addr		: in  unsigned (3 downto 0);
-		pcm_in_data		: in  unsigned (19 downto 0);
-		pcm_in_we		: in  std_logic;
-		ac_reset		: in  std_logic; 
-		ac_bit_clk		: in  std_logic;
-		ac_sdata_out	: out std_logic;
-		ac_ssync		: out std_logic
-	);
-end ac_out;
-
-architecture Behavioral of ac_out is
-
-------------------------------------------------------------------
-COMPONENT singleshot
-GENERIC (mode : integer);
-PORT(
-	rst : IN std_logic;
-	clk : IN std_logic;
-	input : IN std_logic;          
-	output : OUT std_logic
-	);
-END COMPONENT;
-
-------------------------------------------------------------------
-subtype tag_t is UNSIGNED(15 downto 0);
-subtype slot_valid_t is UNSIGNED(1 to 12);
-signal slot_valid : slot_valid_t;
-subtype slot_t is UNSIGNED(19 downto 0);
-type slot_array_t is array (natural range <>) of slot_t;
-signal data_array : slot_array_t (1 to 12);
-
signal tx_reg : UNSIGNED(19 downto 0);
-signal last_slot, ssync : STD_LOGIC;
-
-type sac_t is (ac_idle, ac_tag, ac_data);
-signal sac, snac : sac_t;
- 
-subtype bitcnt_t is integer range 0 to 19;
-subtype slotcnt_t is integer range 0 to 12;
-
-signal bitcnt : bitcnt_t;
-signal bitcnt_rst, bitcnt_en : STD_LOGIC;
-signal slotcnt : slotcnt_t;
-signal slotcnt_rst, slotcnt_en : STD_LOGIC;
-
-signal slot_start : STD_LOGIC; 
-
-------------------------------------------------------------------
-function CreateTag(slot_valid : slot_valid_t) return tag_t is
-variable tag : tag_t := (others => '0');
-begin
-
	tag := (others => '0');
-	for i in slot_valid_t'range loop
-		tag(15-i) := slot_valid(i);
-		if slot_valid(i) = '1' then
-			tag(15) := '1';
-		end if;	
-	end loop;
-	tag(0) := '0';	-- ID0 
-	tag(1) := '0';	-- ID1
-	tag(2) := '0';	-- Reserved
---	tag(15) := '1';	-- Frame is valid
-	return tag;	
-	
-end CreateTag;
-
-begin
-
-------------------------------------------------------------------
-proc_slot_reg:
-process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
-variable slot_id : integer range 0 to 12;
-begin
-	slot_id := to_integer(pcm_in_addr);
-	if rising_edge(clk) then
-		if rst = '1' then
-			for i in data_array'range(1) loop
-				data_array(i) <= (others => '0');
-			end loop;
-			slot_valid <= (others => '0');
-		elsif last_slot = '1' then
-			slot_valid <= (others => '0');
-		else
-			if cmd_we = '1' then
-				slot_valid(1) <= '1';
-				slot_valid(2) <= '1';
-				data_array(1) <= cmd_addr;
-				data_array(2) <= cmd_data;
-			end if;
-			if pcm_in_we = '1' then
-				if (slot_id > 2) then
-					data_array(slot_id) <= pcm_in_data;
-					slot_valid(slot_id) <= '1';
-				end if;	
-			end if;
-		end if;
-	end if;	
-end process;			
-
--------------------------------------------------------------
--- proc_slot_count
--------------------------------------------------------------
-proc_slot_count:
-process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
-begin
-	if rising_edge(ac_bit_clk) then
-		if slotcnt_rst = '1' then
-			slotcnt <= slotcnt_t'low;
-		elsif slotcnt_en = '1' then
-			if slotcnt /= slotcnt_t'high then
-				slotcnt <= slotcnt + 1;
-			else
-				slotcnt <= slotcnt_t'low;
-			end if;
-		end if;
-	end if;
-end process;	
-
-------------------------------------------------------------------
--- proc_bit_count
-------------------------------------------------------------------
-proc_bit_count:
-process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
-begin
-	if rising_edge(ac_bit_clk) then
-		if bitcnt_rst = '1' then
-			bitcnt <= bitcnt_t'low;
-		elsif bitcnt_en = '1' then
-			if bitcnt /= bitcnt_t'high then
-				bitcnt <= bitcnt + 1;
-			else
-				bitcnt <= bitcnt_t'low;
-			end if;
-		end if;
-	end if;
-end process;	
-
-------------------------------------------------------------------
-proc_ac_fsm:
-process (bitcnt, slotcnt, sac)
-begin
-	snac <= sac;
-	bitcnt_rst <= '0';
-	bitcnt_en <= '1';
-	slotcnt_rst <= '0';
-	slotcnt_en <= '0';
-	slot_start <= '0';
-	ssync <= '0';
-	
-	if bitcnt = 0 then 
-		slot_start <= '1';
-	end if;	
-	
-	case sac is
-	
-		when ac_idle => 
-			bitcnt_rst <= '1';
-			slotcnt_rst <= '1';
-			snac <= ac_tag;
-
-		when ac_tag =>
-			ssync <= '1';
-			if (bitcnt = 15) then
-				slotcnt_en <= '1';
-				bitcnt_rst <= '1';
-				snac <= ac_data;
-			end if;	
-
-		when ac_data =>
-			if bitcnt = 19 then 
-				slotcnt_en <= '1';
-				if slotcnt = 12 then
-					slotcnt_rst <= '1';
-					snac <= ac_tag;
-				end if;	
-			end if;	
-		when others => null;
-	end case;	
-end process;
-
-proc_ac_fsm_next:
-process (ac_reset, ac_bit_clk, snac)
-begin
-	if ac_reset = '1' then
-		sac <= ac_idle;
-	elsif rising_edge(ac_bit_clk) then
-		sac <= snac;
-	end if;
-end process;	
-
-------------------------------------------------------------------
-proc_tx_shift_reg:
-process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
-begin
-
-	if ac_reset = '1' then
-		tx_reg <= (others => '0');
-	elsif rising_edge(ac_bit_clk) then
-		last_slot <= '0';
-		if slot_start = '1' then
-			if ssync = '1' then
-				tx_reg <= CreateTag(slot_valid) & "0000";
-			else	
-				if slotcnt /= 0 then
-					tx_reg <= data_array(slotcnt);
-					if slotcnt = 12 then
-						last_slot <= '1';
-					end if;	
-				end if;	
-			end if;	
-		else	
-			tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
-		end if;
-	end if;	
-end process;
-
-------------------------------------------------------------------
-proc_ac_sync_out:
-process (ac_reset, ac_bit_clk, ssync, tx_reg)
-begin
-	if ac_reset = '1' then
-		ac_ssync <= '0';
-		ac_sdata_out <= '0';
-	elsif rising_edge(ac_bit_clk) then
-		ac_ssync <= ssync;
-		ac_sdata_out <= tx_reg(tx_reg'left);
-	end if;
-end process;	
-
-------------------------------------------------------------------
-singleshot_inst1: singleshot 
-GENERIC MAP (
-	mode => 0)		
-PORT MAP(
-	rst => rst,
-	clk => clk,
-	input => last_slot,
-	output => sync_tx
-);
-
-end Behavioral;
diff --git a/lib/ac97_ctrl/src/tb_ac97_wb.vhd b/lib/ac97_ctrl/src/tb_ac97_wb.vhd
deleted file mode 100644
index 7ab47a4..0000000
--- a/lib/ac97_ctrl/src/tb_ac97_wb.vhd
+++ /dev/null
@@ -1,152 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:33:47 06/05/2007
--- Design Name:   eval_ac
--- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name:  ac_out
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac97_wb IS
-END tb_ac97_wb;
-
-ARCHITECTURE behavior OF tb_ac97_wb IS 
-
-	constant SYS_CLK_PERIOD : time := 10 ns;
-	CONSTANT BIT_CLK_PERIOD : time := 100 ns;
---	constant BIT_CLK_PERIOD : time := 81.38 ns;
-	
-	signal CLK_O	: std_logic := '1';
-	signal RST_O	: std_logic := '1';
-	signal CYC_O	: std_logic := '0';
-	signal STB_O	: std_logic := '0';
-	signal WE_O		: std_logic := '0';
-	signal ACK_I	: std_logic;
-	signal MRDY_O	: std_logic := '1';
-	signal SRDY_I	: std_logic;
-	signal INT_I	: std_logic;
-	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I	: unsigned(31 downto 0);
-	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
-
-	signal dout_rst			: std_logic := '0';
-	signal dout_reg			: unsigned(31 downto 0);
-	signal dout_cnt			: natural range 0 to 255;
-
-	SIGNAL ac97_bit_clk		:  std_logic := '0';
-	SIGNAL ac97_reset_n		:  std_logic;
-	SIGNAL ac97_sdata_out	:  std_logic;
-	SIGNAL ac97_ssync		:  std_logic;
-	SIGNAL ac97_sdata_in	:  std_logic;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-uut : entity work.ac97_wb
-	GENERIC MAP
-	(
-		fifo_depth		=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_O,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_I,
-		SRDY_O			=> SRDY_I,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> DAT_O,
-		DAT_O			=> DAT_I,
-		INT_O			=> INT_I,
-
-		-- AC97 domain
-		ac97_sdata_in	=> ac97_sdata_in,
-		ac97_bit_clk	=> ac97_bit_clk,          
-		ac97_reset_n	=> ac97_reset_n,
-		ac97_sdata_out	=> ac97_sdata_out,
-		ac97_ssync		=> ac97_ssync		
-	);
-
-	
-	ac97_sdata_in <= ac97_sdata_out;
-	
-CLK_GEN: process
-	begin
-		wait for SYS_CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-	bit_clk_gen : PROCESS
-	begin
-		if (ac97_reset_n = '0') then
-			ac97_bit_clk <= '0';
-			wait until ac97_reset_n = '1';
-			wait for 150 us;
-		end if;	
-		wait for BIT_CLK_PERIOD/2;
-		ac97_bit_clk <= not ac97_bit_clk;
-	END PROCESS;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*SYS_CLK_PERIOD;
-		RST_O <= '0';
-
-		wait for 200 us;
-		wait until rising_edge(CLK_O);
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		DAT_O	<= X"0000_0000";
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O);
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O) and ACK_I = '1';
-		CYC_O	<= '0';
-
-		wait until rising_edge(CLK_O);
-
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		DAT_O	<= X"5555_1000";
-		ADDR_O	<= X"0000_0800";
-		wait until rising_edge(CLK_O);
-		DAT_O	<= X"5555_1001";
-		wait until rising_edge(CLK_O);
-		STB_O	<= '0';
-		CYC_O	<= '0';
-
-		WAIT;
-	END PROCESS;
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_in.vhd b/lib/ac97_ctrl/src/tb_ac_in.vhd
deleted file mode 100644
index 359e79b..0000000
--- a/lib/ac97_ctrl/src/tb_ac_in.vhd
+++ /dev/null
@@ -1,203 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:33:47 06/05/2007
--- Design Name:   eval_ac
--- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name:  ac_out
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_in IS
-END tb_ac_in;
-
-ARCHITECTURE behavior OF tb_ac_in IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT ac_in
-    Port (
-		rst 			: in  std_logic;
-		clk 			: in  std_logic;
-		sync_frame	 	: out std_logic;
-		sync_status	 	: out std_logic;
-		slot_valid 		: out unsigned(0 to 12);
-		stat_addr		: out unsigned (19 downto 0);
-		stat_data		: out unsigned (19 downto 0);
-		pcm_out_addr	: in  unsigned (3 downto 0);
-		pcm_out_data	: out unsigned (19 downto 0);
-		ac_reset		: in std_logic; 
-		ac_bit_clk		: in  std_logic;
-		ac_sdata_in		: in std_logic;
-		ac_ssync		: in std_logic
-		);
-	END COMPONENT;
-
-	COMPONENT ac_out
-	PORT(
-		rst				: in  std_logic;
-		clk				: in  std_logic;
-		sync_tx		 	: out std_logic;
-		cmd_addr 		: in  unsigned(19 downto 0);
-		cmd_data		: in  unsigned(19 downto 0);
-		cmd_we			: in  std_logic;
-		pcm_in_addr		: in  unsigned(3 downto 0);
-		pcm_in_data		: in  unsigned(19 downto 0);
-		pcm_in_we		: in  std_logic;
-		ac_bit_clk		: in  std_logic;          
-		ac_reset		: in  std_logic;
-		ac_sdata_out	: out std_logic;
-		ac_ssync		: out std_logic
-		);
-	END COMPONENT;
-
-	constant SYS_CLK_PERIOD : time := 10 ns;
-	constant BIT_CLK_PERIOD : time := 81.38 ns;
-	
-	--Inputs
-	SIGNAL rst :  std_logic := '1';
-	SIGNAL clk :  std_logic := '0';
-	SIGNAL cmd_we :  std_logic := '0';
-	SIGNAL pcm_in_we :  std_logic := '0';
-	SIGNAL ac_bit_clk :  std_logic := '0';
-	SIGNAL cmd_addr :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL cmd_data :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL pcm_in_addr :  unsigned(3 downto 0) := "0011";
-	SIGNAL pcm_in_data :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL ac_sdata_in :  std_logic;
-	SIGNAL pcm_out_addr :  unsigned(3 downto 0) := "0101";
-	SIGNAL ac_reset :  std_logic := '1';
-
-	--Outputs
-	SIGNAL sync_frame :  std_logic;
-	SIGNAL sync_status :  std_logic;
-	SIGNAL sync_tx :  std_logic;
-	SIGNAL ac_sdata_out :  std_logic;
-	SIGNAL ac_ssync :  std_logic;
-	SIGNAL stat_addr : unsigned(19 downto 0);
-	SIGNAL stat_data : unsigned(19 downto 0);
-	SIGNAL stat_valid : std_logic;
-	SIGNAL pcm_out_data :  unsigned(19 downto 0);
-	SIGNAL pcm_out_valid :  std_logic;
-	SIGNAL pcm_out_avail :  std_logic;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: ac_in PORT MAP(
-		rst => rst,
-		clk => clk,
-		sync_frame => sync_frame,
-		sync_status => sync_status,
-		stat_addr => stat_addr,
-		stat_data => stat_data,
-		pcm_out_addr => pcm_out_addr,
-		pcm_out_data => pcm_out_data,
-		ac_reset => ac_reset,
-		ac_bit_clk => ac_bit_clk,
-		ac_sdata_in => ac_sdata_in,
-		ac_ssync => ac_ssync
-	);
-	
-	inst_ac_out: ac_out PORT MAP(
-		rst => rst,
-		clk => clk,
-		sync_tx => sync_tx,
-		cmd_addr => cmd_addr,
-		cmd_data => cmd_data,
-		cmd_we => cmd_we,
-		pcm_in_addr => pcm_in_addr,
-		pcm_in_data => pcm_in_data,
-		pcm_in_we => pcm_in_we,
-		ac_reset => ac_reset,
-		ac_bit_clk => ac_bit_clk,
-		ac_sdata_out => ac_sdata_out,
-		ac_ssync => ac_ssync
-	);
-
-	ac_sdata_in <= ac_sdata_out;
-	
-	sys_clk_gen :
-	PROCESS
-	BEGIN
-		wait for SYS_CLK_PERIOD;
-		clk <= not clk;
-	END PROCESS;
-
-	bit_clk_gen :
-	PROCESS
-	BEGIN
-		wait for BIT_CLK_PERIOD;
-		ac_bit_clk <= not ac_bit_clk;
-	END PROCESS;
-
-	tb_out : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 100*SYS_CLK_PERIOD;
-		rst <= '0';
-		
-		wait for 100*SYS_CLK_PERIOD;
-		ac_reset <= '0';
-		
-		wait until rising_edge(clk) and sync_tx = '1';
-		wait for 100*SYS_CLK_PERIOD;
-		cmd_data <= X"12340";
-		cmd_addr <= X"8B930";
-
-		wait until rising_edge(clk);
-		cmd_we <= '1';
-		wait until rising_edge(clk);
-		cmd_we <= '0';
-
-		for k in 1 to 10 loop
-			pcm_in_we <= '0';
-			wait until rising_edge(clk) and sync_tx = '1';
-			wait for 100*SYS_CLK_PERIOD;
-			for i in 3 to 12 loop
-				pcm_in_addr <= to_unsigned(i, 4);
-				pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
-				pcm_in_we <= '1';
-				wait until rising_edge(clk);
-			end loop;
-		end loop;
-		pcm_in_we <= '0';
-
-		-- Place stimulus here
-
-		wait; -- will wait forever
-	END PROCESS;
-
-	tb_in : PROCESS(clk, pcm_out_addr, sync_status)
-	BEGIN
-		if rising_edge(clk) then
-			if sync_status = '1' then
-				pcm_out_addr <= "0011";
-			elsif pcm_out_addr /= "1100" then
-				pcm_out_addr <= pcm_out_addr + 1;
-			end if;	
-		end if;
-	END PROCESS;
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_io.vhd b/lib/ac97_ctrl/src/tb_ac_io.vhd
deleted file mode 100644
index 6f25c1d..0000000
--- a/lib/ac97_ctrl/src/tb_ac_io.vhd
+++ /dev/null
@@ -1,186 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:33:47 06/05/2007
--- Design Name:   eval_ac
--- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name:  ac_out
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_io IS
-END tb_ac_io;
-
-ARCHITECTURE behavior OF tb_ac_io IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT ac_io
-    Port (
-			rst				: in  std_logic;
-			clk				: in  std_logic;
-			ready			: out std_logic;
-			sync_strobe		: out unsigned(0 to 2);
-			slot_valid		: out unsigned(0 to 12);
-			stat_addr		: out unsigned (19 downto 0);
-			stat_data		: out unsigned (19 downto 0);
-			rx_pcm_addr		: in  unsigned (3 downto 0);
-			rx_pcm_data		: out unsigned (19 downto 0);
-			cmd_addr 		: in  unsigned(19 downto 0);
-			cmd_data		: in  unsigned(19 downto 0);
-			cmd_we			: in  std_logic;
-			tx_pcm_addr		: in  unsigned(3 downto 0);
-			tx_pcm_data		: in  unsigned(19 downto 0);
-			tx_pcm_we		: in  std_logic;
-			ac_sdata_in		: in std_logic;
-			ac_bit_clk		: in  std_logic;          
-			ac_reset_n		: out std_logic;
-			ac_sdata_out	: out std_logic;
-			ac_ssync		: out std_logic
-			);
-	END COMPONENT;
-
-	constant SYS_CLK_PERIOD : time := 10 ns;
-	CONSTANT BIT_CLK_PERIOD : time := 100 ns;
---	constant BIT_CLK_PERIOD : time := 81.38 ns;
-	
-	--Inputs
-	SIGNAL rst : std_logic := '1';
-	SIGNAL clk : std_logic := '0';
-	SIGNAL acio_ready  : std_logic;
-	SIGNAL cmd_we   :  std_logic := '0';
-	SIGNAL tx_pcm_we   :  std_logic := '0';
-	SIGNAL ac_bit_clk  :  std_logic := '0';
-	SIGNAL cmd_addr :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL cmd_data :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL tx_pcm_addr :  unsigned(3 downto 0) := "0011";
-	SIGNAL tx_pcm_data :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL ac_sdata_in :  std_logic;
-	SIGNAL rx_pcm_addr :  unsigned(3 downto 0) := "0101";
-
-	--Outputs
-	SIGNAL slot_valid :  unsigned(0 to 12);
-	SIGNAL sync_strobe :  unsigned(0 to 2);
-	SIGNAL ac_reset_n :  std_logic;
-	SIGNAL ac_sdata_out :  std_logic;
-	SIGNAL ac_ssync :  std_logic;
-	SIGNAL stat_addr :  unsigned(19 downto 0);
-	SIGNAL stat_data :  unsigned(19 downto 0);
-	SIGNAL rx_pcm_data :  unsigned(19 downto 0);
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: ac_io PORT MAP(
-		rst				=> rst,				
-		clk				=> clk,				
-		ready			=> acio_ready,				
-		sync_strobe		=> sync_strobe,	
-		slot_valid		=> slot_valid,	
-		stat_addr		=> stat_addr,			
-		stat_data		=> stat_data,			
-		rx_pcm_addr		=> rx_pcm_addr,		
-		rx_pcm_data		=> rx_pcm_data,		
-		cmd_addr 		=> cmd_addr, 	
-		cmd_data		=> cmd_data,		
-		cmd_we			=> cmd_we,	
-		tx_pcm_addr		=> tx_pcm_addr,		
-		tx_pcm_data		=> tx_pcm_data,		
-		tx_pcm_we		=> tx_pcm_we,	
-		ac_sdata_in		=> ac_sdata_in,		
-		ac_bit_clk		=> ac_bit_clk,		
-		ac_reset_n		=> ac_reset_n,		
-		ac_sdata_out	=> ac_sdata_out,	
-		ac_ssync		=> ac_ssync		
-	);
-	
-	ac_sdata_in <= ac_sdata_out;
-	
-	sys_clk_gen :
-	PROCESS
-	BEGIN
-		wait for SYS_CLK_PERIOD;
-		clk <= not clk;
-	END PROCESS;
-
-	bit_clk_gen : PROCESS
-	begin
-		if (ac_reset_n = '0') then
-			ac_bit_clk <= '0';
-			wait until ac_reset_n = '1';
-			wait for 150 us;
-		end if;	
-		wait for BIT_CLK_PERIOD/2;
-		ac_bit_clk <= not ac_bit_clk;
-	END PROCESS;
-
-	tb_out : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 100*SYS_CLK_PERIOD;
-		rst <= '0';
-		
-		wait until (ac_reset_n = '1');
-		
-		wait until rising_edge(clk) and sync_strobe(2) = '1';
-		wait for 100*SYS_CLK_PERIOD;
-		cmd_data <= X"12340";
-		cmd_addr <= X"8B930";
-
-		wait until rising_edge(clk);
-		cmd_we <= '1';
-		wait until rising_edge(clk);
-		cmd_we <= '0';
-
-		for k in 1 to 10 loop
-			tx_pcm_we <= '0';
-			wait until rising_edge(clk) and sync_strobe(2) = '1';
-			wait for 10*BIT_CLK_PERIOD;
-			for i in 3 to 12 loop
-				tx_pcm_addr <= to_unsigned(i, 4);
-				tx_pcm_data <= to_unsigned(2048*k + integer(i), 20);
-				tx_pcm_we <= '1';
-				wait until rising_edge(clk);
-			end loop;
-		end loop;
-		tx_pcm_we <= '0';
-
-		-- Place stimulus here
-
-		wait; -- will wait forever
-	END PROCESS;
-
-	tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe)
-	BEGIN
-		if rising_edge(clk) then
-			if sync_strobe(1) = '1' then
-				rx_pcm_addr <= "0011";
-			elsif rx_pcm_addr /= "1100" then
-				rx_pcm_addr <= rx_pcm_addr + 1;
-			end if;	
-		end if;
-	END PROCESS;
-
-END;
diff --git a/lib/ac97_ctrl/src/tb_ac_out.vhd b/lib/ac97_ctrl/src/tb_ac_out.vhd
deleted file mode 100644
index 6f6cb42..0000000
--- a/lib/ac97_ctrl/src/tb_ac_out.vhd
+++ /dev/null
@@ -1,149 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:33:47 06/05/2007
--- Design Name:   eval_ac
--- Module Name:   E:/work/VHDL/eval_ac/tb_eval_ac.vhd
--- Project Name:  ac_out
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: ac_out
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-ENTITY tb_ac_out IS
-END tb_ac_out;
-
-ARCHITECTURE behavior OF tb_ac_out IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT ac_out
-	PORT(
-		rst				: IN  std_logic;
-		clk				: IN  std_logic;
-		sync_tx			: OUT std_logic;
-		cmd_addr 		: IN  unsigned(19 downto 0);
-		cmd_data		: IN  unsigned(19 downto 0);
-		cmd_we			: IN  std_logic;
-		pcm_in_addr		: IN  unsigned(3 downto 0);
-		pcm_in_data		: IN  unsigned(19 downto 0);
-		pcm_in_we		: IN  std_logic;
-		ac_bit_clk		: IN  std_logic;          
-		ac_reset		: in std_logic;
-		ac_sdata_out	: OUT std_logic;
-		ac_ssync		: OUT std_logic
-		);
-	END COMPONENT;
-
-	constant SYS_CLK_PERIOD : time := 10 ns;
-	constant BIT_CLK_PERIOD : time := 81.38 ns;
-	
-	--Inputs
-	SIGNAL rst :  std_logic := '1';
-	SIGNAL clk :  std_logic := '0';
-	SIGNAL ce :  std_logic := '0';
-	SIGNAL cmd_we :  std_logic := '0';
-	SIGNAL pcm_in_we :  std_logic := '0';
-	SIGNAL ac_bit_clk :  std_logic := '0';
-	SIGNAL cmd_addr :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL cmd_data :  unsigned(19 downto 0) := (others=>'0');
-	SIGNAL pcm_in_addr :  unsigned(3 downto 0) := (others=>'0');
-	SIGNAL pcm_in_data :  unsigned(19 downto 0) := (others=>'0');
-
-	--Outputs
-	SIGNAL sync_tx :  std_logic;
-	SIGNAL ac_reset :  std_logic;
-	SIGNAL ac_sdata_out :  std_logic;
-	SIGNAL ac_ssync :  std_logic;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: ac_out PORT MAP(
-		rst => rst,
-		clk => clk,
-		sync_tx => sync_tx,
-		cmd_addr => cmd_addr,
-		cmd_data => cmd_data,
-		cmd_we => cmd_we,
-		pcm_in_addr => pcm_in_addr,
-		pcm_in_data => pcm_in_data,
-		pcm_in_we => pcm_in_we,
-		ac_reset => ac_reset,
-		ac_bit_clk => ac_bit_clk,
-		ac_sdata_out => ac_sdata_out,
-		ac_ssync => ac_ssync
-	);
-
-	sys_clk_gen :
-	PROCESS
-	BEGIN
-		wait for SYS_CLK_PERIOD;
-		clk <= not clk;
-	END PROCESS;
-
-	bit_clk_gen :
-	PROCESS
-	BEGIN
-		wait for BIT_CLK_PERIOD;
-		ac_bit_clk <= not ac_bit_clk;
-	END PROCESS;
-
-	tb : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 100*SYS_CLK_PERIOD;
-		rst <= '0';
-		
-		wait for 100*SYS_CLK_PERIOD;
-		ac_reset <= '0';
-		
-		wait until rising_edge(clk) and sync_tx = '1';
-		wait for 100*SYS_CLK_PERIOD;
-		cmd_data <= X"aaaa0";
-		cmd_addr <= X"1DFC0";
-
-		wait until rising_edge(clk);
-		cmd_we <= '1';
-		wait until rising_edge(clk);
-		cmd_we <= '0';
-
-		for k in 1 to 10 loop
-			pcm_in_we <= '0';
-			wait until rising_edge(clk) and sync_tx = '1';
-			wait for 100*SYS_CLK_PERIOD;
-			for i in 3 to 12 loop
-				pcm_in_addr <= to_unsigned(i, 4);
-				pcm_in_data <= to_unsigned(2048*k + integer(i), 20);
-				pcm_in_we <= '1';
-				wait until rising_edge(clk);
-			end loop;
-		end loop;
-		pcm_in_we <= '0';
-
-		-- Place stimulus here
-
-		wait; -- will wait forever
-	END PROCESS;
-
-END;
diff --git a/lib/ac97_ctrl/todo.txt b/lib/ac97_ctrl/todo.txt
deleted file mode 100644
index 7abc706..0000000
--- a/lib/ac97_ctrl/todo.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-2010-07-08
-- RX FIFO
diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m
deleted file mode 100644
index ccac021..0000000
--- a/lib/filter/sim/eval_lowpass.m
+++ /dev/null
@@ -1,37 +0,0 @@
-function eval_filter(N)
-omega_lp = 0.15
-omega_hp = 0.05
-
-omega_bp_m = 0.02;
-bw2_bp = 0.02;
-
-lp = lowpass(N, omega_lp, 1.0);
-coef_lp = hann(N)'.*lp./sum(lp.^2);
-
-hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1));
-coef_hp = hp./sum(hp.^2).*hann(N)';
-
-bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1));
-coef_bp = bp./sum(bp.^2).*hann(N)';
-
-abs_lp = 20*log10(abs(fft(coef_lp)));
-abs_hp = 20*log10(abs(fft(coef_hp)));
-abs_bp = 20*log10(abs(fft(coef_bp)));
-
-close all;
-plot((0:N/2)/N, abs_lp(1:N/2+1));grid;
-figure
-plot((0:N/2)/N, abs_hp(1:N/2+1));grid;
-figure
-plot((0:N/2)/N, abs_bp(1:N/2+1));grid;
-
-figure
-plot((0:N-1), coef_lp);grid;
-figure
-plot((0:N-1), coef_hp);grid;
-figure
-plot((0:N-1), coef_bp);grid;
-
-mean_lp = mean(coef_lp-mean(coef_lp))
-mean_hp = mean(coef_hp)
-mean_bp = mean(coef_bp)
diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m
deleted file mode 100644
index 292964d..0000000
--- a/lib/filter/sim/lowpass.m
+++ /dev/null
@@ -1,20 +0,0 @@
-function coef = lowpass(N, omega, scale)
-
-phi = 0;
-dphi = 2*omega;
-if (mod(N, 2) == 0)
-	M = N/2;
-	for i=0:M-1,
-		phi = phi + dphi;
-		coef(M+i+1) = scale*sinc(phi);
-		coef(M-i-1+1) = coef(M+i+1);
-	end;
-else
-	M = (N-1)/2;
-	for i=1:M,
-		phi = phi + dphi;
-		coef(M+i+1) = scale*sinc(phi);
-		coef(M-i+1) = coef(M+i+1);
-	end;
-	coef(M+1) = scale*Sinc(0.0);
-end;
diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo
deleted file mode 100644
index 5260669..0000000
--- a/lib/filter/sim/tb_fir_iterative.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage.vhd"
-vcom -explicit  -93 "../src/fir_iterative.vhd"
-vcom -explicit  -93 "../src/tb_fir_iterative.vhd"
-vsim -t 1ps   -lib work tb_fir_iterative
-do {tb_fir_iterative.wdo}
-view wave
-view structure
-view signals
-run 20us
diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo
deleted file mode 100644
index cb193af..0000000
--- a/lib/filter/sim/tb_fir_iterative.wdo
+++ /dev/null
@@ -1,144 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Literal /tb_fir_iterative/xi
-add wave -noupdate -format Literal /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
-add wave -noupdate -divider {Xmem Dual}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Logic /tb_fir_iterative/y_valid
-add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -divider {FIR Stage}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Literal /tb_fir_iterative/xi
-add wave -noupdate -format Literal /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem
-add wave -noupdate -divider {Xmem Dual}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo
-add wave -noupdate -format Literal /tb_fir_iterative/coeffs
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid
-add wave -noupdate -format Logic /tb_fir_iterative/y_valid
-add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem
-add wave -noupdate -divider {FIR Stage}
-add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out
-add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {5100000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel
deleted file mode 100644
index f784c1a..0000000
Binary files a/lib/filter/sim/tb_fir_parallel and /dev/null differ
diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo
deleted file mode 100644
index 6bee97f..0000000
--- a/lib/filter/sim/tb_fir_parallel.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage.vhd"
-vcom -explicit  -93 "../src/fir_parallel.vhd"
-vcom -explicit  -93 "../src/tb_fir_parallel.vhd"
-vsim -t 1ps   -lib work tb_fir_parallel
-do {tb_fir_parallel.wdo}
-view wave
-view structure
-view signals
-run 1000us
diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo
deleted file mode 100644
index f0e20ce..0000000
--- a/lib/filter/sim/tb_fir_parallel.wdo
+++ /dev/null
@@ -1,29 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_parallel/clk
-add wave -noupdate -format Logic /tb_fir_parallel/srst
-add wave -noupdate -format Logic /tb_fir_parallel/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out
-add wave -noupdate -format Logic /tb_fir_parallel/out_valid
-add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable
-add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi
-add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {19450000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {25152750 ps}
diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m
deleted file mode 100644
index 75a542c..0000000
--- a/lib/filter/sim/tb_fir_results.m
+++ /dev/null
@@ -1,10 +0,0 @@
-% Read data
-function tb_fir_results()
-fir = TEXTREAD('fir.txt')';
-
-N= length(fir);
-
-% Output
-close all;
-plot(0:N-1, fir); grid;
-
diff --git a/lib/filter/sim/tb_fir_semi_parallel.fdo b/lib/filter/sim/tb_fir_semi_parallel.fdo
deleted file mode 100644
index 63079c8..0000000
--- a/lib/filter/sim/tb_fir_semi_parallel.fdo
+++ /dev/null
@@ -1,20 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_sys.vhd"
-vcom -explicit  -93 "../src/delay_line.vhd"
-vcom -explicit  -93 "../src/fir_semi_parallel.vhd"
-vcom -explicit  -93 "../src/tb_fir_semi_parallel.vhd"
-vsim -t 1ps   -lib work tb_fir_semi_parallel
-do {tb_fir_semi_parallel.wdo}
-view wave
-view structure
-view signals
-run 50us
diff --git a/lib/filter/sim/tb_fir_semi_parallel.wdo b/lib/filter/sim/tb_fir_semi_parallel.wdo
deleted file mode 100644
index aba8fb1..0000000
--- a/lib/filter/sim/tb_fir_semi_parallel.wdo
+++ /dev/null
@@ -1,57 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/rst
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/clk
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/h_in
-add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out
-add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy
-add wave -noupdate -divider {Real out}
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/yo
-add wave -noupdate -divider -height 50 <NULL>
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/count0
-add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/start
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/count_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/en_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/ce_array
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/x
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/accu_load
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y
-add wave -noupdate -divider {stage 1}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram
-add wave -noupdate -divider {stage 2}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {52500 ns}
diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo
deleted file mode 100644
index e9fefb8..0000000
--- a/lib/filter/sim/tb_fir_stage.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage.vhd"
-vcom -explicit  -93 "../src/tb_fir_stage.vhd"
-vsim -t 1ps   -lib work tb_fir_stage
-do {tb_fir_stage.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo
deleted file mode 100644
index 916de83..0000000
--- a/lib/filter/sim/tb_fir_stage.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage/clk
-add wave -noupdate -format Logic /tb_fir_stage/srst
-add wave -noupdate -divider Input
-add wave -noupdate -format Logic /tb_fir_stage/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in
-add wave -noupdate -format Literal /tb_fir_stage/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Logic /tb_fir_stage/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1655000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {2100 ns}
diff --git a/lib/filter/sim/tb_fir_stage_sys.fdo b/lib/filter/sim/tb_fir_stage_sys.fdo
deleted file mode 100644
index b2417c3..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/filter_pkg.vhd"
-vcom -explicit  -93 "../src/fir_pkg.vhd"
-vcom -explicit  -93 "../src/fir_stage_sys.vhd"
-vcom -explicit  -93 "../src/tb_fir_stage_sys.vhd"
-vsim -t 1ps   -lib work tb_fir_stage_sys
-do {tb_fir_stage_sys.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage_sys.wdo b/lib/filter/sim/tb_fir_stage_sys.wdo
deleted file mode 100644
index 21e822e..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.wdo
+++ /dev/null
@@ -1,28 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage_sys/clk
-add wave -noupdate -divider Input
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in
-add wave -noupdate -format Literal /tb_fir_stage_sys/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1060000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {706931 ps} {1268317 ps}
diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
deleted file mode 100644
index a05e317..0000000
--- a/lib/filter/src/delay_line.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_parallel - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-
-entity delay_line is
-Generic
-(
-	nbits				: integer := 12;
-	nbits_frac			: integer := 11;
-	ntaps				: integer := 4;
-	delay_fix			: integer := 1
-);
-Port
-(
-	rst			: in std_logic;
-	clk			: in std_logic;
-	shift_en	: in std_logic;
-	delay		: in natural range 0 to ntaps-1;
-	din			: in sfixed;
-	dout		: out sfixed
-);
-end delay_line;
-
-architecture ram_based of delay_line is
-
-	-------------------------------------------------------------------------------
-	signal count : natural range 0 to ntaps-1;
-	signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
-	signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
-	signal ram_w : unsigned(nbits-1 downto 0);
-	signal ram_r : unsigned(nbits-1 downto 0);
-
-	-------------------------------------------------------------------------------
-begin
-
-	addr_w	<= to_unsigned(count, addr_w'length);
-	addr_r	<= addr_w + not to_unsigned(delay, addr_w'length);
-	
-	ram_w	<= unsigned(din);
-	dout	<= sfixed(ram_r);
-
-counter:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				count <= 0;
-			elsif shift_en = '1' then
-				if count /= ntaps-1 then
-					count <= count + 1;
-				else
-					count <= 0;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	inst_dpram_1w1r: entity work.dpram_1w1r
-	GENERIC MAP
-	(
-		addr_width	=> NextExpBaseTwo(ntaps),
-		data_width	=> nbits
-	)
-	PORT MAP (
-		clka	=> clk,
-		clkb	=> clk,
-		en_a	=> '1',
-		en_b	=> '1',
-		we_a	=> shift_en,
-		addr_a	=> addr_w,
-		addr_b	=> addr_r,
-		din_a	=> ram_w,
-		dout_b	=> ram_r
-	);
-	
-end ram_based;
-
-architecture reg_based of delay_line is
-
-	-------------------------------------------------------------------------------
-	subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
-	type delay_pipe_t is array (ntaps-1 downto 0) of word_t;
-	type delay_fix_pipe_t is array (delay_fix downto 0) of word_t;
-	
-	-------------------------------------------------------------------------------
-begin
-
-shift_register:
-	process(clk)
-	variable delay_pipe	: delay_pipe_t;
-	begin
-		if rising_edge(clk) then
-			dout			<= delay_pipe(delay);
-			if shift_en = '1' then
-				delay_pipe		:= delay_pipe(delay_pipe'left-1 downto 0) & din;
-			end if;
-		end if;
-	end process;
-
-end reg_based;
-
diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd
deleted file mode 100644
index 1359d25..0000000
--- a/lib/filter/src/filter_pkg.vhd
+++ /dev/null
@@ -1,219 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use IEEE.MATH_REAL.ALL;
-
-library work;
-use work.fixed_util_pkg.all;
-
--------------------------------------------------------------------------------
-package filter_pkg is
-
-	function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t;
-	function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t;
-	function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t;
-	function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t;
-	function Window_Hamming (x : real_array_t) return real_array_t;
-	function Window_VonHann (x : real_array_t) return real_array_t;
-	function Window_Blackman (x : real_array_t) return real_array_t;
-	function Sinc (x : real) return real;
-	function FilterEnergy (x : real_array_t) return real;
-	function FilterMean (x : real_array_t) return real;
-	function FilterScale (x : real_array_t; scale : real) return real_array_t;
-	function FilterTestCoef (N : positive) return real_array_t;
-	
-end; -- package filter_pkg;
-
--------------------------------------------------------------------------------
-package body filter_pkg is
-	
-	function Prototype_Lowpass (N : positive; omega : real) return real_array_t is
-	variable res : real_array_t(0 to N-1);
-	variable M : positive;
-	variable phi : real := 0.0;
-	variable dphi : real := pi*omega;
-	begin
-		if (N mod 2) = 0 then
-			M := N/2;
-			for i in 0 to M-1 loop
-				phi := phi + dphi;
-				res(M+i) := Sinc(phi);
-				res(M-i-1) := res(M+i);
-			end loop;
-		else
-			M := (N-1)/2;
-			for i in 1 to M loop
-				phi := phi + dphi;
-				res(M+i) := Sinc(phi);
-				res(M-i) := res(M+i);
-			end loop;
-			res(M) := Sinc(0.0);
-		end if;
-		return res;
-		
-	end Prototype_Lowpass;
-
-	-------------------------------------------------------------------------------
-	function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t is
-	variable lp : real_array_t(0 to N-1);
-	begin
-		lp := Prototype_Lowpass(N, omega);
-
-		return Window_VonHann(FilterScale(lp, gain/FilterEnergy(lp)));
-		
-	end FilterCoef_Lowpass;
-
-	-------------------------------------------------------------------------------
-	function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t is
-	variable lp, res : real_array_t(0 to N-1);
-	variable phi : real := 0.0;
-	variable dphi : real := pi;
-	begin
-		lp := Prototype_Lowpass(N, 0.5-omega);
-
-		for i in 0 to N-1 loop
-			res(i) := lp(i) * cos(phi);	
-			phi := phi + dphi;
-		end loop;	
-		
-		return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-			
-	end FilterCoef_Highpass;
-
-	-------------------------------------------------------------------------------
-	function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t is
-	variable lp, res, mean, sum : real_array_t(0 to N-1);
-	variable phi : real := 0.0;
-	variable dphi : real := 2.0*pi*omega_m;
-	begin
-		lp := Prototype_Lowpass(N, bw2/2.0);
-		
-		for i in 0 to N-1 loop
-			res(i) := lp(i) * cos(phi);	
-			phi := phi + dphi;
-		end loop;	
-
-		return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-
-	end FilterCoef_Bandpass;
-
-	-------------------------------------------------------------------------------
-	function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t is
-	variable res : real_array_t(0 to N-1);
-	begin
-			for i in 0 to N-1 loop
-				res(i) := 0.0;
-			end loop;
-			res(delay) := gain;
-			
-		return res;
-		
-	end FilterCoef_Delta;
-	
-	-------------------------------------------------------------------------------
-	function FilterTestCoef (N : positive) return real_array_t is
-	variable phi : real := 0.0;
-	variable dphi : real := 1.0/real(N);
-	variable res : real_array_t(0 to N-1);
-	begin
-			for i in 0 to N-1 loop
-				res(i) := phi;
-				phi := phi + dphi;
-			end loop;
-		return res;
-		
-	end FilterTestCoef;
-	
-	-------------------------------------------------------------------------------
-	function Window_Hamming (x : real_array_t) return real_array_t is
-	variable res : real_array_t(x'range);
-	variable phi : real := 0.0;
-	variable dphi : real := 2.0*pi/real(x'length-1);
-	begin
-		for i in x'range loop
-			res(i) := x(i) * (0.54 - 0.46*(cos(phi)));
-			phi := phi + dphi;
-		end loop;
-		return res;
-		
-	end Window_Hamming;
-	
-	-------------------------------------------------------------------------------
-	function Window_VonHann (x : real_array_t) return real_array_t is
-	variable res : real_array_t(x'range);
-	variable phi : real := 0.0;
-	variable dphi : real := 2.0*pi/real(x'length-1);
-	begin
-		for i in x'range loop
-			res(i) := 0.5 * x(i) * (1.0 - (cos(phi)));
-			phi := phi + dphi;
-		end loop;
-		return res;
-		
-	end Window_VonHann;
-	
-	-------------------------------------------------------------------------------
-	function Window_Blackman (x : real_array_t) return real_array_t is
-	variable res : real_array_t(0 to x'length-1);
-	variable phi : real := 0.0;
-	variable dphi : real := 2.0*pi/real(x'length-1);
-	begin
-		for i in x'range loop
-			res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi));
-			phi := phi + dphi;
-		end loop;
-		return res;
-		
-	end Window_Blackman;
-	
-	-------------------------------------------------------------------------------
-	function Sinc (x : real) return real is
-	variable res : real := 1.0;
-	begin
-		if x /= 0.0 then
-			res := sin(x)/x;
-		end if;
-		
-		return res;
-		
-	end Sinc;
-	
-	-------------------------------------------------------------------------------
-	function FilterScale (x : real_array_t; scale : real) return real_array_t is
-	variable res : real_array_t(x'range);
-	begin
-		for i in x'range loop
-			res(i) := scale * x(i);
-		end loop;
-		
-		return res;
-		
-	end FilterScale;
-	
-	-------------------------------------------------------------------------------
-	function FilterEnergy (x : real_array_t) return real is
-	variable res : real := 0.0;
-	begin
-		for i in x'range loop
-			res := res + x(i)*x(i);
-		end loop;
-		
-		return res;
-		
-	end FilterEnergy;
-	
-	-------------------------------------------------------------------------------
-	function FilterMean (x : real_array_t) return real is
-	variable res : real := 0.0;
-	begin
-		for i in x'range loop
-			res := res + x(i);
-		end loop;
-		
-		return res/real(x'length);
-	
-	end FilterMean;
-	
--------------------------------------------------------------------------------
-end; -- package filter_pkg;
diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd
deleted file mode 100644
index bc1dba5..0000000
--- a/lib/filter/src/fir_iterative.vhd
+++ /dev/null
@@ -1,323 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_parallel - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_iterative is
-Generic
-(
-	ntaps				: integer := 33;
-	nbits_in			: integer := 12;
-	nbits_in_frac		: integer := 11;
-	nbits_stages		: integer := 13;
-	nbits_stages_frac	: integer := 11;
-	nbits_out			: integer := 12;
-	nbits_out_frac		: integer := 11;
-	fir_mode			: fir_iterative_mode_t := normal;
-	rounding			: boolean := true;
-	saturating			: boolean := true
-);
-Port
-(
-	srst			: in std_logic;
-	clk				: in std_logic;
-	h_din			: in sfixed;
-	h_addr_out		: out natural;
-	ready			: out std_logic;
-	x_valid			: in std_logic;
-	x_din			: in sfixed;
-	y_dout_valid	: out std_logic;
-	y_dout			: out sfixed
-);
-end fir_iterative;
-
-architecture Behavioral of fir_iterative is
-
--------------------------------------------------------------------------------
-	constant fir_stage_mode : fir_stage_mode_t := transposed;
-	constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
-	constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode);
-	
-	subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	
-	type state_t is (init, idle, start, proc, p1, p2, output);
-	signal s, sn : state_t;
-	signal x_stage, xo, y_stage : stage_t;
-	signal stage_en, cnt_en, new_round : std_logic;
-	
-	subtype tap_cnt_t is natural range 0 to ntaps-1;
-	signal htap_cnt : tap_cnt_t;
-	signal xtap_cnt_w : tap_cnt_t;
-	signal xtap_cnt_r : tap_cnt_t;
-	signal stage_valid, clr_xmem, valid, fir_stage_clr,  fir_stage_en, cnt_reset : std_logic;
-	subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1;
-	signal h_addr : tap_range_t;
-	signal xmem_din, xmem_dout : in_t;
-	signal xmem_we, y_valid : std_logic;
-
-	type xmem_t is array (0 to ntaps-1) of in_t;
-	signal xmem : xmem_t;
-	signal y_out_reg : out_t;
-	signal y_reg_valid : std_logic;
-	
-	-------------------------------------------------------------------------------
-begin
-	
-	h_addr_out <= h_addr;
-	x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate);
-	
-	----------------------------------------
-	process (clk)
-	begin
-	if rising_edge(clk) then
-		y_reg_valid <= '0';
-		if srst = '1' then
-			y_out_reg <= to_sfixed(0, y_out_reg);
-		elsif y_valid = '1' then
-			y_out_reg <=  resize(y_stage, y_out_reg);
-			y_reg_valid <= '1';
-		end if;
-	end if;
-	end process;
-
-	process (clk)
-	begin
-	if rising_edge(clk) then
-		y_dout_valid <= '0';
-		if srst = '1' then
-			y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
-		elsif y_reg_valid = '1' then
-			y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-			y_dout_valid <= '1';
-		end if;
-	end if;
-	end process;
-
-	----------------------------------------
-	proc_xmem_rw: process (clk)
-	begin
-	if rising_edge(clk) then
-		if xmem_we = '1' then
-			xmem(xtap_cnt_w) <= xmem_din;
-		end if;
-		xmem_dout <= xmem(xtap_cnt_r);
-	end if;
-	end process;
-
-	----------------------------------------
-	proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout)
-	begin
-		xmem_din <= to_sfixed(0, xmem_din);
-		if new_round = '1' and clr_xmem = '0' then
-			xmem_din <= sfixed(x_din);
-		end if;
-	end process;
-
-	----------------------------------------
-	proc_xmem_pointer: process(clk, new_round ,clr_xmem)
-	begin
-		xmem_we <= clr_xmem or new_round;
-		if rising_edge(clk) then
-			if srst = '1' then
-				xtap_cnt_w <= tap_cnt_t'high; 
-			elsif xmem_we = '1' then
-				if xtap_cnt_w /= tap_cnt_t'low then
-					xtap_cnt_w <= xtap_cnt_w - 1;
-				else
-					xtap_cnt_w <= tap_cnt_t'high;
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
-	----------------------------------------
-	proc_h_addr: process(htap_cnt)
-	begin
-		if fir_mode = symmetric then
-			if ntaps_is_even then 
-				if htap_cnt > ntaps/2-1 then
-					h_addr <= ntaps - htap_cnt - 1;
-				else
-					h_addr <= htap_cnt;
-				end if;
-			else	
-				if htap_cnt > (ntaps-1)/2 then
-					h_addr <= ntaps - htap_cnt - 1;
-				else
-					h_addr <= htap_cnt;
-				end if;
-			end if;	
-		else	
-			h_addr <= htap_cnt;
-		end if;	
-	end process;
-
-	----------------------------------------
-	proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en)
-	begin
-		if rising_edge(clk) then
-			if cnt_reset = '1' then
-				htap_cnt <= tap_cnt_t'low; 
-				xtap_cnt_r <= xtap_cnt_w; 
-			elsif cnt_en = '1' then
-				if htap_cnt /= tap_cnt_t'high then
-					htap_cnt <= htap_cnt + 1;
-				else
-					htap_cnt <= tap_cnt_t'low; 
-				end if;	
-				if xtap_cnt_r /= tap_cnt_t'high then
-					xtap_cnt_r <= xtap_cnt_r + 1;
-				else
-					xtap_cnt_r <= tap_cnt_t'low; 
-				end if;	
-			end if;	
-		end if;	
-	end process;
-
-	----------------------------------------
-	proc_valid_out: process(srst, clk, valid, new_round)
-	variable val_pipe : unsigned(4 downto 0);
-	variable ctrl_pipe : unsigned(2 downto 0);
-
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				ctrl_pipe := (others => '0');
-				fir_stage_en <= '0';
-				fir_stage_clr <= '0';
-			else	
-				ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round;
-				fir_stage_en <= stage_en;
-				fir_stage_clr <= ctrl_pipe(2);
-			end if;	
-		end if;
-		cnt_reset <= new_round;
-	end process;
-
-	----------------------------------------
-	proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w)
-	begin
-		clr_xmem <= '0';
-		new_round <= '0';
-		cnt_en <= '0';
-		ready <= '0';
-		valid <= '0';
-		sn <= s;
-		stage_en <= '0';
-		y_valid <= '0';
-		
-		case s is
-			when init =>
-			clr_xmem <= '1';
-			if xtap_cnt_w = tap_cnt_t'low then
-				sn <= idle;
-			end if;
-			
-			when idle =>
-			ready <= '1';
-			if x_valid = '1' then
-				sn <= start;
-			end if;	
-			
-			when start =>
-				new_round <= '1';
-				sn <= proc;
-
-			when proc =>
-				stage_en <= '1';
-				cnt_en <= '1';
-				if htap_cnt = tap_cnt_t'high then
-					sn <= p1;
-				end if;
-
-			when p1 =>
-				sn <= p2;
-				
-			when p2 =>
-				sn <= output;
-				ready <= '1';
-
-			when output =>
-				sn <= idle;
-				y_valid <= '1';
-				ready <= '1';
-				if x_valid = '1' then
-					sn <= start;
-				end if;	
-
-			when others => null;
-		end case;
-	end process;	
-
-	proc_fsm_next: process(srst, clk, sn)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				s <= init;
-			else
-				s <= sn;
-			end if;
-		end if;
-	end process;	
-	
-	----------------------------------------
-		inst_fir_stage: entity work.fir_stage_sys
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			input_latency	=> 1,
-			coef_latency	=> 1,
-			pipe_latency	=> 3
-		)
-		PORT MAP
-		(
-			rst			=> fir_stage_clr,
-			clk			=> clk,
-			x_in		=> x_stage,
-			y_in		=> y_stage,
-			h_in		=> h_din,
-			x_out		=> xo,
-			y_out		=> y_stage
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	
-end Behavioral;
diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd
deleted file mode 100644
index af8bb68..0000000
--- a/lib/filter/src/fir_iterative_pkg.vhd
+++ /dev/null
@@ -1,52 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_iterative_pkg is
-	
-	type fir_iterative_mode_t is (normal, symmetric);
-
-	function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-	function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-	
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
-package body fir_iterative_pkg is
-
-	function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
-	variable res : integer;
-	begin
-		res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
-		return res;
-	end taps_nbits;	
-	
-	function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
-	constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
-	variable res : integer := ntaps;
-	begin
-		if mode = symmetric then
-			if ntaps_is_even then
-				res := ntaps/2;
-			else
-				res := (ntaps-1)/2 + 1;
-			end if;	
-		end if;	
-		return res;
-	end ntaps_addr;	
-
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd
deleted file mode 100644
index 2561848..0000000
--- a/lib/filter/src/fir_parallel.vhd
+++ /dev/null
@@ -1,218 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_parallel - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_parallel is
-Generic
-(
-	ntaps				: integer := 33;
-	nbits_in			: integer := 12;
-	nbits_in_frac		: integer := 11;
-	nbits_stages		: integer := 13;
-	nbits_stages_frac	: integer := 11;
-	nbits_out			: integer := 12;
-	nbits_out_frac		: integer := 11;
-	has_in_reg			: boolean := false;
-	has_pipe_reg		: boolean := false;
-	has_out_reg			: boolean := false;
-	fir_mode			: fir_parallel_mode_t := transposed;
-	rounding			: boolean := true;
-	saturating			: boolean := true
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	h_in		: in sfixed_array_t;
-	in_valid	: in std_logic;
-	d_in		: in sfixed;
-	out_valid	: out std_logic;
-	d_out		: out sfixed
-);
-end fir_parallel;
-
-architecture Behavioral of fir_parallel is
-
--------------------------------------------------------------------------------
-	-- Component Declaration for FIR stage
-	COMPONENT fir_stage
-	GENERIC
-	(
-		nbits_in		: integer;
-		nbits_in_frac	: integer;
-		nbits_out		: integer;
-		nbits_out_frac	: integer;
-		has_in_reg		: boolean;
-		has_pipe_reg	: boolean;
-		has_out_reg		: boolean;
-		fir_mode		: fir_stage_mode_t;
-		rounding		: boolean;
-		saturating		: boolean
-	);
-	PORT
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		in_valid	: in std_logic;
-		x_in		: in sfixed;
-		y_in		: in sfixed;
-		h_in		: in sfixed;
-		out_valid	: out std_logic;
-		x_out		: out sfixed;
-		y_out		: out sfixed;
-		y_out_clr	: in std_logic
-	);
-	END COMPONENT;
-
-	-------------------------------------------------------------------------------
-	type coeff_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	type stages_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
-	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-	constant fir_stage_mode : fir_stage_mode_t := transposed;
-
-	SIGNAL x_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-	SIGNAL x    	   : stages_array_t(0 to ntaps-2);
-	SIGNAL y           : stages_array_t(0 to ntaps-2);
-	SIGNAL h           : coeff_array_t(0 to ntaps-1);
-	
-	-------------------------------------------------------------------------------
-begin
-
-	-- Assign coefficients
-    assign_coeffs:
-	for i in 0 to ntaps-1 generate
-		h(i) <= to_sfixed(h_in, i);
-	end generate;	
-
-	----------------------------------------
-	-- Instantiate the FIR stages
-	----------------------------------------
-		uut_first_stage: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_in,
-			nbits_in_frac	=> nbits_in_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_stage_mode,
-			rounding		=> false,
-			saturating		=> false
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> d_in,
-			y_in		=> zero_in,
-			h_in		=> h(ntaps-1),
-			out_valid	=> out_valid,
-			x_out		=> x(0),
-			y_out		=> y(0),
-			y_out_clr	=> '0'
-		);
-
-	----------------------------------------
-    gen_stages:
-	for i in 1 to ntaps-2 generate
-		uut_stages: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_stage_mode,
-			rounding		=> false,
-			saturating		=> false
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> x(i-1),
-			y_in		=> y(i-1),
-			h_in		=> h(ntaps-i-1),
-			out_valid	=> open,
-			x_out		=> x(i),
-			y_out		=> y(i),
-			y_out_clr	=> '0'
-		);
-	end generate;
-	
-	----------------------------------------
-		uut_last_stage: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_out,
-			nbits_out_frac	=> nbits_out_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_stage_mode,
-			rounding		=> rounding,
-			saturating		=> saturating
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> x(ntaps-2),
-			y_in		=> y(ntaps-2),
-			h_in		=> h(0),
-			out_valid	=> open,
-			x_out		=> x_out,
-			y_out		=> d_out,
-			y_out_clr	=> '0'
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	
-end Behavioral;
diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd
deleted file mode 100644
index 9243d8c..0000000
--- a/lib/filter/src/fir_parallel_pkg.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_stage_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_parallel_pkg is
-	
-	type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
-package body fir_parallel_pkg is
-
-	
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_pkg.vhd b/lib/filter/src/fir_pkg.vhd
deleted file mode 100644
index 9e904b5..0000000
--- a/lib/filter/src/fir_pkg.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_pkg is
-	
-	type fir_stage_mode_t is (transposed, systolic);
-	type fir_iterative_mode_t is (normal, symmetric);
-	type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
-	function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-	function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-	
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
-package body fir_pkg is
-
-	function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
-	variable res : integer;
-	begin
-		res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
-		return res;
-	end taps_nbits;	
-	
-	function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
-	constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
-	variable res : integer := ntaps;
-	begin
-		if mode = symmetric then
-			if ntaps_is_even then
-				res := ntaps/2;
-			else
-				res := (ntaps-1)/2 + 1;
-			end if;	
-		end if;	
-		return res;
-	end ntaps_addr;	
-
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
deleted file mode 100644
index 68493c1..0000000
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ /dev/null
@@ -1,300 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_parallel - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_semi_parallel is
-Generic
-(
-	ntaps_per_stage		: integer := 32;
-	nstages				: integer := 2;
-	pipe_latency		: integer := 4;
-	nbits_in			: integer := 12;
-	nbits_in_frac		: integer := 11;
-	nbits_stages		: integer := 13;
-	nbits_stages_frac	: integer := 11;
-	nbits_out			: integer := 12;
-	nbits_out_frac		: integer := 11
-);
-Port
-(
-	rst			: in std_logic;
-	clk			: in std_logic;
-	h_addr		: in natural range 0 to nstages*ntaps_per_stage-1;
-	h_we		: in std_logic;
-	h_in		: in sfixed;
-	din_vld		: in std_logic;
-	din			: in sfixed;
-	dout_vld	: out std_logic;
-	start		: in  std_logic;
-	rdy			: out std_logic;
-	dout		: out sfixed
-);
-end fir_semi_parallel;
-
-architecture Behavioral of fir_semi_parallel is
-
-	-------------------------------------------------------------------------------
-	constant coef_addr_nbits	: natural := NextExpBaseTwo(ntaps_per_stage) + NextExpBaseTwo(nstages);
-	
-	subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	subtype count_t is natural range 0 to ntaps_per_stage-1;
-	type count_array_t is array (nstages-1 downto 0) of count_t;
-		
-	subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	type stage_array_t is array (0 to nstages) of stage_t;
-
-	signal count_array			: count_array_t;
-	signal count0				: count_t;
-	signal ce_array				: unsigned(nstages downto 0);
-	signal en_array				: unsigned(nstages downto 0);
-	signal coef_addr			: unsigned(coef_addr_nbits-1 downto 0);
-	
-	SIGNAL x			: stage_array_t;
-	SIGNAL xo			: stage_array_t;
-	SIGNAL y			: stage_array_t;
-	SIGNAL accu			: sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
-	SIGNAL act			: std_logic := '0';
-	SIGNAL start_r		: std_logic := '0';
-	signal accu_load	: std_logic;
-	signal accu_ld_pipe	: unsigned(nstages+pipe_latency-1 downto 0);
-	
-	signal din_r 		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	signal coef_we 		: unsigned(nstages-1 downto 0);
-	
-	type coef_array_t is array (0 to nstages-1) of unsigned(nbits_stages-1 downto 0);
-	signal coef_din		: unsigned(nbits_stages-1 downto 0);
-	signal coef_dout	: coef_array_t;
-
-	-------------------------------------------------------------------------------
-begin
-
-	assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure;
-	assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure;
-
-	x(0)		<= resize(din_r, x(0));
-	y(0)		<= to_sfixed(0.0, y(0));
-
-	accu_load	<= accu_ld_pipe(accu_ld_pipe'left);
-	start_r		<= act and ce_array(ce_array'left) and not ce_array(ce_array'left-1);
-	
-din_register:	
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if din_vld = '1' then
-				din_r <= din;
-			end if;
-		end if;
-	end process;
-
-accu_load_pipe:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				accu_ld_pipe <= (others => '0');
-			else
-				accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & start_r;
-			end if;	
-		end if;
-	end process;
-
-coef_we_gen:
-	process(clk)
-	variable i : natural range 0 to nstages-1;
-	variable caddr	: unsigned(coef_addr_nbits-1 downto 0);
-	variable saddr	: unsigned(NextExpBaseTwo(nstages)-1 downto 0);
-	begin
-		if rising_edge(clk) then
-			caddr		:= to_unsigned(h_addr, coef_addr_nbits);
-			saddr		:= caddr(caddr'left downto NextExpBaseTwo(ntaps_per_stage));
-			i 			:= to_integer(saddr);
-			coef_we		<= (others => '0');
-			coef_we(i)	<= '1';
-			coef_din	<= unsigned(h_in);
-			coef_addr	<= caddr;
-		end if;	
-	end process;
-
-rdy_logic:	
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				rdy	<= '1';
-				act	<= '0';
-			elsif start = '1' then
-				rdy	<= '0';
-				act	<= '1';
-			elsif count0 = count_t'high-2 then
-				rdy	<= '1';
-				act	<= '0';
-			end if;
-		end if;
-	end process;
-
-counter:	
-	process(clk)
-	variable cnt	: count_t;
-	variable enable	: std_logic;
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cnt := count_t'high;
-			elsif cnt /= count_t'high then
-				cnt := cnt + 1;
-			else
-				enable	:= '0';
-				if start_r = '1' then
-					enable	:= '1';
-					cnt := 0;
-				end if;
-			end if;
-			count0	<= cnt;
-			count_array	<= count_array(count_array'left-1 downto 0) & cnt;
-			en_array	<= en_array(en_array'left-1 downto 0) & enable;
-		end if;
-	end process;
-
-ce_pipe:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				ce_array <= (others => '0');
-			else
-				ce_array <= ce_array(ce_array'left-1 downto 0) & din_vld;
-			end if;
-		end if;
-	end process;
-
-gen_coef_ram:
-	for i in 0 to nstages-1 generate
-	signal addr_a : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
-	signal addr_b : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
-	begin
-		addr_a	<= coef_addr(addr_a'length-1 downto 0);
-		addr_b <= to_unsigned(count_array(i), addr_b'length);
-		inst_coef_ram: entity work.dpram_1w1r
-		GENERIC MAP 
-		(
-			addr_width	=> NextExpBaseTwo(ntaps_per_stage),
-			data_width	=> nbits_stages
-		)
-		PORT MAP (
-			clka	=> clk,
-			clkb	=> clk,
-			en_a	=> '1',
-			en_b	=> '1',
-			we_a	=> coef_we(i),
-			addr_a	=> addr_a,
-			addr_b	=> addr_b,
-			din_a	=> coef_din,
-			dout_b	=> coef_dout(i)
-		);
-	end generate;
-		
-
-gen_stages:
-	for i in 0 to nstages-1 generate
-	signal h_in : coef_t;
-	begin
-		h_in <= sfixed(coef_dout(i));
-		inst_fir_stage: entity work.fir_stage_sys
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			pipe_latency	=> pipe_latency
-		)
-		PORT MAP
-		(
-			clk			=> clk,
-			ce			=> en_array(i),
-			x_in		=> x(i+1),
-			y_in		=> y(i),
-			h_in		=> h_in,
-			x_out		=> xo(i+1),
-			y_out		=> y(i+1)
-		);
-	end generate;
-					
-
-gen_delays:
-	for i in 0 to nstages-1 generate
-	begin
-		inst_delay_line : entity work.delay_line(ram_based)
-		GENERIC MAP
-		(
-			nbits		=> nbits_stages,
-			nbits_frac	=> nbits_stages_frac,
-			ntaps		=> ntaps_per_stage,
-			delay_fix	=> 0
-		)
-		PORT MAP
-		(
-			rst			=> rst,
-			clk			=> clk,
-			shift_en	=> ce_array(i),
-			delay		=> count_array(i),
-			din			=> x(i),
-			dout		=> x(i+1)
-		);
-	end generate;
-	
-acumulator:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			dout_vld	<= accu_load;
-			if rst = '1' then
-				dout_vld	<= '0';
-			elsif en_array(en_array'left) = '1' then
-				if accu_load = '1' then
-					dout	<= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
-					accu 	<= y(nstages);
-				else
-					accu	<= resize(accu + y(nstages), accu);
-				end if;
-			end if;
-		end if;
-	end process;
-	
-	
-end Behavioral;
diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd
deleted file mode 100644
index a519cf4..0000000
--- a/lib/filter/src/fir_stage.vhd
+++ /dev/null
@@ -1,157 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage is
-Generic
-(
-	nbits_in		: integer := 12;
-	nbits_in_frac	: integer := 12;
-	nbits_out		: integer := 12;
-	nbits_out_frac	: integer := 12;
-	has_in_reg		: boolean := false;
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false;
-	fir_mode		: fir_stage_mode_t := transposed;
-	rounding		: boolean := true;
-	saturating		: boolean := true
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	in_valid	: in std_logic;
-	x_in		: in sfixed;
-	y_in		: in sfixed;
-	h_in		: in sfixed;
-	out_valid	: out std_logic;
-	x_out		: out sfixed;
-	y_out		: out sfixed;
-	y_out_clr	: in std_logic
-);
-end fir_stage;
-
-architecture Behavioral of fir_stage is
-
-signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
-	proc_in_reg_y: process(clk)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' or y_out_clr = '1' then
-				yin <= to_sfixed(0, yin);
-			else	
-				yin <= resize(y_in, yin);
-			end if;	
-		end	if;
-	end process;
-
-------------------------------------------------------------
-	proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in)
-	variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	begin
-		if has_in_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					xin <= to_sfixed(0, xin);
-					hin <= to_sfixed(0, hin);
-					valid <= '0';
-				else
-					valid <= in_valid;
-					if in_valid = '1' then
-						xin <= resize(x_in, xin);
-						hin <= resize(h_in, hin);
-					end if;
-				end if;
-			end if;
-		else
-			xin <= resize(x_in, xin);
-			hin <= resize(h_in, hin);
-			valid <= in_valid;
-		end if;
-		x_out <= resize(x_in, p);
-		
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(srst, clk, valid, xin, hin)
-	variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	begin
-		p := resize(xin * hin, p);
-		if has_pipe_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					prod  <= to_sfixed(0, prod);
-					p_valid <= '0';
-				else
-					prod  <= p;
-					p_valid <= valid;
-				end if;	
-			end if;	
-		else	
-			prod  <= p;
-			p_valid <= valid;
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-	proc_out_reg: process(srst, clk, p_valid, prod, yin)
-	variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	begin
-		yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
---		if rising_edge(clk) then
---			if srst = '1' or y_out_clr = '1' then
---				y_out <= to_sfixed(0, yout);
---				out_valid <= '0';
---			else	
---				y_out <= yout;
---				out_valid <= p_valid;
---			end if;	
---		end	if;
-		out_valid <= p_valid;
-		y_out <= yout;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd
deleted file mode 100644
index c6408b8..0000000
--- a/lib/filter/src/fir_stage_pkg.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fir_stage_pkg is
-
-type fir_stage_mode_t is (transposed, systolic);
-
-end; -- package fir_stage_pkg;
-
-package body fir_stage_pkg is
-
-end; -- package fir_stage_pkg;
diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
deleted file mode 100644
index af0f74a..0000000
--- a/lib/filter/src/fir_stage_sys.vhd
+++ /dev/null
@@ -1,109 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    fir_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage_sys is
-Generic
-(
-	nbits_in		: integer := 12;
-	nbits_in_frac	: integer := 12;
-	nbits_out		: integer := 12;
-	nbits_out_frac	: integer := 12;
-	pipe_latency	: integer := 4
-);
-Port
-(
-	clk			: in std_logic;
-	ce			: in std_logic;
-	x_in		: in sfixed;
-	y_in		: in sfixed;
-	h_in		: in sfixed;
-	x_out		: out sfixed;
-	y_out		: out sfixed
-);
-end fir_stage_sys;
-
-architecture Behavioral of fir_stage_sys is
-
-constant min_pipe_lat	: integer := 4;
-
-subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-type input_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-
-signal yin	: in_t;
-signal prod	: out_t;
-
-------------------------------------------------------------
-begin
-
-	assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure;
-
-	yin			<= resize(y_in, yin);
-
-------------------------------------------------------------
-	proc_pipe_reg: process(clk)
-	variable h_pipe	: coef_pipe_t;
-	variable x_pipe	: input_pipe_t;
-	begin
-		if rising_edge(clk) then
-			if ce = '1' then
-				x_pipe	:= x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0));
-				h_pipe	:= h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0));
-				prod	<= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate);
-			end if;	
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-	proc_out_reg: process(clk)
-	variable yout : out_t;
-	variable xout : in_t;
-	begin
-		if rising_edge(clk) then
-			if ce = '1' then
-				yout	:= resize(yin + prod, yout, fixed_wrap, fixed_truncate);
-				y_out	<= yout;
-				xout	:= resize(x_in, xout, fixed_wrap, fixed_truncate);
-				x_out	<= xout;
-			end if;	
-		end	if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd
deleted file mode 100644
index 76b6024..0000000
--- a/lib/filter/src/tb_fir_iterative.vhd
+++ /dev/null
@@ -1,234 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_fir_stage
--- Module Name:   tb_fir_stage.vhd
--- Project Name:  fir_stage
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_iterative IS
-	Generic (
-		ntaps				: integer := 11;
-		nbits_in			: integer := 15;
-		nbits_in_frac		: integer := 15;
-		nbits_stages		: integer := 15;
-		nbits_stages_frac	: integer := 15;
-		nbits_out			: integer := 15;
-		nbits_out_frac		: integer := 15;
-		fir_mode			: fir_iterative_mode_t := symmetric;
-		rounding			: boolean := true;
-		saturating			: boolean := true
-	        );
-END tb_fir_iterative;
-
-ARCHITECTURE behavior OF tb_fir_iterative IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT fir_iterative
-	GENERIC
-	(
-		ntaps				: integer;
-		nbits_in			: integer;
-		nbits_in_frac		: integer;
-		nbits_stages		: integer;
-		nbits_stages_frac	: integer;
-		nbits_out			: integer;
-		nbits_out_frac		: integer;
-		fir_mode			: fir_iterative_mode_t;
-		rounding			: boolean;
-		saturating			: boolean
-	);
-	PORT
-	(
-		srst			: in std_logic;
-		clk				: in std_logic;
-		h_din			: in sfixed;
-		h_addr_out		: out natural;
-		ready			: out std_logic;
-		x_valid			: in std_logic;
-		x_din			: in sfixed;
-		y_dout_valid	: out std_logic;
-		y_dout			: out sfixed
-	);
-	END COMPONENT;
-
-	-------------------------------------------------------------------------------
-	--Constants
-	constant nsamples : integer := 32;
-	
-	constant PERIOD : time := 10 ns;
-	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL x_valid    : std_logic := '0';
-	SIGNAL h_din        : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	SIGNAL x_din        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
-	--Outputs
-	SIGNAL y_dout       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL y_valid   : std_logic;
-	SIGNAL ready   : std_logic;
-
-	SIGNAL fileout_enable   : std_logic := '1';
-	
-	-- Test coefficients
---	SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1);
-	SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1);
---	SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps);
-	signal x_input : real_array_t(0 to nsamples-1) :=
-	(
-		0.0,	
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.9999,
-		-0.0000,	
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0
-		
-	);
-	type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	signal ymem : ymem_t;
-	
-	signal y_cnt : integer ;
-	SIGNAL xi, yo : real := 0.0;
-	SIGNAL h_addr : natural;
-	
-	-- file I/O
-	subtype sample_t is integer range -32768 to 32767;
-	type file_t is file of sample_t;
-	
-	-------------------------------------------------------------------------------
-BEGIN
-
-	xi <= to_real(x_din);
-	yo <= to_real(y_dout);
-	
-	----------------------------------------
-	-- Instantiate the Unit Under Test (UUT)
-	----------------------------------------
-		uut_fir_iterative: fir_iterative
-		GENERIC MAP
-		(
-			ntaps				=> ntaps,
-			nbits_in			=> nbits_in,
-			nbits_in_frac		=> nbits_in_frac,
-			nbits_out			=> nbits_out,
-			nbits_out_frac		=> nbits_out_frac,
-			nbits_stages		=> nbits_stages,
-			nbits_stages_frac	=> nbits_stages_frac,
-			fir_mode			=> fir_mode,
-			rounding			=> rounding,
-			saturating			=> saturating
-		)
-		PORT MAP
-		(
-			srst			=> srst,
-			clk				=> clk,
-			h_din			=> h_din,
-			h_addr_out		=> h_addr,
-			ready			=> ready,
-			x_valid			=> x_valid,
-			x_din			=> x_din,
-			y_dout_valid	=> y_valid,
-			y_dout			=> y_dout
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		
-		for i in 0 to nsamples-1 loop
-			if i = nsamples/2 then
-				wait for 43*PERIOD;
-			end if;					
-			------------------------------------------
-			wait until rising_edge(clk) and ready = '1';
-			x_din <= to_sfixed(x_input(i), x_din);
-			x_valid <= '1';
-			------------------------------------------
-			wait until rising_edge(clk);
-			x_valid <= '0';
-		end loop;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	process(srst, clk, y_valid)
-	begin
-		if rising_edge(clk) then
-			h_din <= to_sfixed(coeffs(h_addr), h_din);
-			if srst = '1' then
-				y_cnt <= 0;
-				
-			elsif y_valid = '1' then
-				ymem(y_cnt) <= y_dout;
-				y_cnt <= y_cnt + 1;
-			end if;
-		end if;	
-	end process;	
-
-END;
diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd
deleted file mode 100644
index e1ff939..0000000
--- a/lib/filter/src/tb_fir_parallel.vhd
+++ /dev/null
@@ -1,193 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_fir_stage
--- Module Name:   tb_fir_stage.vhd
--- Project Name:  fir_stage
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_parallel IS
-	Generic (
-		ntaps				: integer := 33;
-		nbits_in			: integer := 16;
-		nbits_in_frac		: integer := 16;
-		nbits_stages		: integer := 16;
-		nbits_stages_frac	: integer := 15;
-		nbits_out			: integer := 16;
-		nbits_out_frac		: integer := 16;
-		has_in_reg			: boolean := false;
-		has_pipe_reg		: boolean := true;
-		has_out_reg			: boolean := false;
-		fir_mode			: fir_parallel_mode_t := transposed;
-		rounding			: boolean := true;
-		saturating			: boolean := true
-	        );
-END tb_fir_parallel;
-
-ARCHITECTURE behavior OF tb_fir_parallel IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT fir_parallel
-	GENERIC
-	(
-		ntaps				: integer;
-		nbits_in			: integer;
-		nbits_in_frac		: integer;
-		nbits_stages		: integer;
-		nbits_stages_frac	: integer;
-		nbits_out			: integer;
-		nbits_out_frac		: integer;
-		has_in_reg			: boolean;
-		has_pipe_reg		: boolean;
-		has_out_reg			: boolean;
-		fir_mode			: fir_parallel_mode_t;
-		rounding			: boolean;
-		saturating			: boolean
-	);
-	PORT
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		h_in		: in sfixed_array_t;
-		in_valid	: in std_logic;
-		d_in		: in sfixed;
-		out_valid	: out std_logic;
-		d_out		: out sfixed
-	);
-	END COMPONENT;
-
-	-------------------------------------------------------------------------------
-	--Constants
-	constant PERIOD : time := 10 ns;
-	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_in        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
-	--Outputs
-	SIGNAL y_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL out_valid   : std_logic := '0';
-
-	SIGNAL fileout_enable   : std_logic := '1';
-	
-	-- Test coefficients
-	SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
-	
-	SIGNAL xi, yo : real := 0.0;
-	
-	-- file I/O
-	subtype sample_t is integer range -32768 to 32767;
-	type file_t is file of sample_t;
-	
-	-------------------------------------------------------------------------------
-BEGIN
-
-	xi <= to_real(x_in);
-	yo <= to_real(y_out);
-	
-	----------------------------------------
-	-- Instantiate the Unit Under Test (UUT)
-	----------------------------------------
-		uut_fir_parallel: fir_parallel
-		GENERIC MAP
-		(
-			ntaps				=> ntaps,
-			nbits_in			=> nbits_in,
-			nbits_in_frac		=> nbits_in_frac,
-			nbits_out			=> nbits_out,
-			nbits_out_frac		=> nbits_out_frac,
-			nbits_stages		=> nbits_stages,
-			nbits_stages_frac	=> nbits_stages_frac,
-			has_in_reg			=> has_in_reg,
-			has_pipe_reg		=> has_pipe_reg,
-			has_out_reg			=> has_out_reg,
-			fir_mode			=> fir_mode,
-			rounding			=> rounding,
-			saturating			=> saturating
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			clk			=> clk,
-			h_in		=> coeff_in,
-			in_valid	=> in_valid,
-			d_in		=> x_in,
-			out_valid	=> out_valid,
-			d_out		=> y_out
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	file fi : file_t open read_mode is "wav_in.dat";
-	variable si : sample_t;
-	
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		
-		while not endfile(fi) loop
-			read(fi, si);
-			x_in <= to_sfixed(to_signed(si, x_in'length));
-			in_valid <= '1';
-			wait for PERIOD;
-			wait until rising_edge(clk);
-		end loop;	
-		------------------------------------------
-		in_valid <= '0';
-		
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk, fileout_enable, out_valid)
-	file fo : file_t open write_mode is "wav_out.dat";
-	variable so : sample_t;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
-			so := to_integer(y_out);
-			write(fo, so);
-		end if;
-
-	END PROCESS;
-	
-END;
diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd
deleted file mode 100644
index 33da80f..0000000
--- a/lib/filter/src/tb_fir_semi_parallel.vhd
+++ /dev/null
@@ -1,289 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_fir_stage
--- Module Name:   tb_fir_stage.vhd
--- Project Name:  fir_stage
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_semi_parallel IS
-	Generic
-	(
-		ntaps_per_stage		: integer := 32;
-		nstages				: integer := 2;
-		nbits_in			: integer := 32;
-		nbits_in_frac		: integer := 30;
-		nbits_stages		: integer := 32;
-		nbits_stages_frac	: integer := 30;
-		nbits_out			: integer := 32;
-		nbits_out_frac		: integer := 30
-	);
-END tb_fir_semi_parallel;
-
-ARCHITECTURE behavior OF tb_fir_semi_parallel IS 
-
-	-------------------------------------------------------------------------------
-	--Constants
-	constant PERIOD : time := 10 ns;
-	constant nsamples : integer := 32;
-	constant M		 : integer := 1;
-
-	--Inputs
-	SIGNAL clk			: std_logic := '0';
-	SIGNAL rst			: std_logic := '1';
-	SIGNAL din_vld		: std_logic := '0';
-	SIGNAL d_in			: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	signal h_addr		: natural := 0;
-	SIGNAL h_we			: std_logic := '0';
-	SIGNAL h_in			: sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-	SIGNAL start		: std_logic := '0';
-
-	--Outputs
-	SIGNAL d_out		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL dout_vld		: std_logic;
-	SIGNAL rdy			: std_logic;
-
-	SIGNAL fileout_enable   : std_logic := '1';
-	
-	
-	SIGNAL xi, yo : real := 0.0;
-
-	CONSTANT ntaps	: natural := nstages*ntaps_per_stage;
-	type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
-	function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
-	variable res : h_mem_t;
-	begin
-		for i in 0 to ntaps-1 loop
-			res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
-		end loop;
-		
-		return res;
-	end to_h_mem;	
-	
-	CONSTANT coeffs : real_array_t(0 to ntaps-1) := FilterCoef_Lowpass(ntaps, 0.1, 4.0);
-	CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps, h_in);
-	
-	-- file I/O
-	subtype sample_t is integer range -32768 to 32767;
-	type file_t is file of sample_t;
-
-	signal x_input : real_array_t(0 to nsamples-1) :=
-	(
-		0.0,	
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		1.0,
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0,		
-		0.0
-		
-	);
-	
-	-------------------------------------------------------------------------------
-BEGIN
-
-	xi <= to_real(d_in);
-	yo <= to_real(d_out);
-	
-	----------------------------------------
-	-- Instantiate the Unit Under Test (UUT)
-	----------------------------------------
-	uut : entity work.fir_semi_parallel
-	GENERIC MAP
-	(
-		ntaps_per_stage		=> ntaps_per_stage,
-		nstages				=> nstages,
-		pipe_latency		=> 5,
-		nbits_in			=> nbits_in,
-		nbits_in_frac		=> nbits_in_frac,
-		nbits_stages		=> nbits_stages,
-		nbits_stages_frac	=> nbits_stages_frac,
-		nbits_out			=> nbits_out,
-		nbits_out_frac		=> nbits_out_frac
-	)
-	PORT MAP
-	(
-		rst			=> rst,
-		clk			=> clk,
-		h_addr		=> h_addr,
-		h_we		=> h_we,
-		h_in		=> h_in,
-		din_vld		=> din_vld,
-		din			=> d_in,
-		dout_vld	=> dout_vld,
-		rdy			=> rdy,
-		start		=> start,
-		dout		=> d_out
-	);
-	
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	file fi : file_t open read_mode is "wav_in.dat";
-	variable si : sample_t;
-	variable remain : integer;
-	variable j : integer;
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		rst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		
-		-- write coeffs
-		for i in 0 to ntaps-1 loop
-			wait until rising_edge(clk);
-			h_addr	<= i;
-			h_in 	<= h_mem(i);
-			h_we	<= '1';
-		end loop;
-		wait until rising_edge(clk);
---		h_addr	<= 0;
---		h_in 	<= to_sfixed(0.25, h_in);
---		h_we	<= '1';
---		wait until rising_edge(clk);
-		h_we	<= '0';
-
-		-- Write zeros
-		remain := ntaps_per_stage*nstages;
-		j := 0;
-		while remain /= 0 loop
-			wait until rising_edge(clk) and rdy = '1';
-			for i in 0 to M-1 loop
-				d_in <= to_sfixed(0.0, d_in);
-				din_vld <= '1';
-				j := j + 1;
-				remain := remain - 1;
-				wait until rising_edge(clk);
-			end loop;
-			din_vld <= '0';
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
-			start <= '1';
-			wait until rising_edge(clk);
-			start <= '0';
-		end loop;
-
-		------------------------------------------
-		-- Write data
-		remain := nsamples;
-		j := 0;
-		while remain /= 0 loop
-			wait until rising_edge(clk) and rdy = '1';
-			for i in 0 to M-1 loop
-				d_in <= to_sfixed(x_input(j), d_in);
-				din_vld <= '1';
-				j := j + 1;
-				remain := remain - 1;
-				wait until rising_edge(clk);
-			end loop;
-			din_vld <= '0';
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
-			start <= '1';
-			wait until rising_edge(clk);
-			start <= '0';
-		end loop;
-
-		-- Write zeros
-		remain := 100;
-		j := 0;
-		while remain /= 0 loop
-			wait until rising_edge(clk) and rdy = '1';
-			for i in 0 to M-1 loop
-				d_in <= to_sfixed(0.0, d_in);
-				din_vld <= '1';
-				j := j + 1;
-				remain := remain - 1;
-				wait until rising_edge(clk);
-			end loop;
-			din_vld <= '0';
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
---			wait until rising_edge(clk);
-			start <= '1';
-			wait until rising_edge(clk);
-			start <= '0';
-		end loop;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk, fileout_enable)
-	file fo : file_t open write_mode is "wav_out.dat";
-	variable so : sample_t;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' then
-			if dout_vld = '1' then
-				so := to_integer(d_out);
-				write(fo, so);
-			end if;	
-		end if;
-
-	END PROCESS;
-	
-END;
diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd
deleted file mode 100644
index 04bb03f..0000000
--- a/lib/filter/src/tb_fir_stage.vhd
+++ /dev/null
@@ -1,276 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_fir_stage
--- Module Name:   tb_fir_stage.vhd
--- Project Name:  fir_stage
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage IS
-	Generic (
-		ntaps				: integer := 33;
-		nbits_in			: integer := 24;
-		nbits_in_frac		: integer := 23;
-		nbits_stages		: integer := 25;
-		nbits_stages_frac	: integer := 23;
-		nbits_out			: integer := 24;
-		nbits_out_frac		: integer := 22;
-		has_in_reg			: boolean := true;
-		has_pipe_reg		: boolean := true;
-		has_out_reg			: boolean := false;
-		fir_mode			: fir_stage_mode_t := transposed;
-		rounding			: boolean := true;
-		saturating			: boolean := true
-	        );
-END tb_fir_stage;
-
-ARCHITECTURE behavior OF tb_fir_stage IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT fir_stage
-	GENERIC
-	(
-		nbits_in		: integer;
-		nbits_in_frac	: integer;
-		nbits_out		: integer;
-		nbits_out_frac	: integer;
-		has_in_reg		: boolean;
-		has_pipe_reg	: boolean;
-		has_out_reg		: boolean;
-		fir_mode		: fir_stage_mode_t;
-		rounding		: boolean;
-		saturating		: boolean
-	);
-	PORT
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		in_valid	: in std_logic;
-		x_in		: in sfixed;
-		y_in		: in sfixed;
-		h_in		: in sfixed;
-		out_valid	: out std_logic;
-		x_out		: out sfixed;
-		y_out		: out sfixed;
-		y_out_clr	: in std_logic
-	);
-	END COMPONENT;
-
-	type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); 
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_in        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
-	--Outputs
-	SIGNAL x_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL y_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL out_valid   : std_logic := '0';
-
-	SIGNAL x    	   : stages_t(0 to ntaps-2);
-	SIGNAL y           : stages_t(0 to ntaps-2);
-	
-	SIGNAL fileout_enable   : std_logic := '1';
-	
-	-- Test coefficients
-	function to_sfixed(x_real : real_array_t) return stages_t is
-	variable res : stages_t(x_real'range); 
-	begin
-		for i in x_real'range loop
-			res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
-		end loop;
-		
-		return res;
-	end to_sfixed;
-	
-	constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-	
-	SIGNAL xi, yo : real := 0.0;
-	
-BEGIN
-
-	xi <= to_real(x_in);
-	yo <= to_real(y_out);
-	
-	----------------------------------------
-	-- Instantiate the Unit Under Test (UUT)
-	----------------------------------------
-		uut_first_stage: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_in,
-			nbits_in_frac	=> nbits_in_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_mode,
-			rounding		=> false,
-			saturating		=> false
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			y_out_clr	=> '0',
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> x_in,
-			y_in		=> zero_in,
-			h_in		=> h(ntaps-1),
-			out_valid	=> out_valid,
-			x_out		=> x(0),
-			y_out		=> y(0)
-		);
-
-	----------------------------------------
-    gen_stages:
-	for i in 1 to ntaps-2 generate
-		uut_stages: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_mode,
-			rounding		=> false,
-			saturating		=> false
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			y_out_clr	=> '0',
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> x(i-1),
-			y_in		=> y(i-1),
-			h_in		=> h(ntaps-i-1),
-			out_valid	=> open,
-			x_out		=> x(i),
-			y_out		=> y(i)
-		);
-	end generate;
-	
-	----------------------------------------
-		uut_last_stage: fir_stage 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_out,
-			nbits_out_frac	=> nbits_out_frac,
-			has_in_reg		=> has_in_reg,
-			has_pipe_reg	=> has_pipe_reg,
-			has_out_reg		=> has_out_reg,
-			fir_mode		=> fir_mode,
-			rounding		=> rounding,
-			saturating		=> saturating
-		)
-		PORT MAP
-		(
-			srst		=> srst,
-			y_out_clr	=> '0',
-			clk			=> clk,
-			in_valid	=> in_valid,
-			x_in		=> x(ntaps-2),
-			y_in		=> y(ntaps-2),
-			h_in		=> h(0),
-			out_valid	=> open,
-			x_out		=> x_out,
-			y_out		=> y_out
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		
-		x_in <= to_sfixed(0.0, x_in);
-
-		wait until rising_edge(clk);
-		in_valid <= '1';
-
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(1.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-
-		wait for 150*PERIOD;
-		
-		wait until rising_edge(clk);
-		in_valid <= '0';
-		
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk, fileout_enable, out_valid)
-	file RESULT_FIR:      text open write_mode is "fir.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
-			fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
-		end if;
-
-	END PROCESS;
-	
-END;
diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd
deleted file mode 100644
index b0afe32..0000000
--- a/lib/filter/src/tb_fir_stage_sys.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_fir_stage
--- Module Name:   tb_fir_stage.vhd
--- Project Name:  fir_stage
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage_sys IS
-	Generic
-	(
-		ntaps				: integer := 33;
-		nbits_in			: integer := 24;
-		nbits_in_frac		: integer := 23;
-		nbits_stages		: integer := 25;
-		nbits_stages_frac	: integer := 23;
-		nbits_out			: integer := 24;
-		nbits_out_frac		: integer := 22
-        );
-END tb_fir_stage_sys;
-
-ARCHITECTURE behavior OF tb_fir_stage_sys IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT fir_stage_sys
-	GENERIC
-	(
-		nbits_in		: integer;
-		nbits_in_frac	: integer;
-		nbits_out		: integer;
-		nbits_out_frac	: integer;
-		input_latency	: integer;
-		coef_latency	: integer;
-		pipe_latency	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		ce			: in std_logic;
-		x_in		: in sfixed;
-		y_in		: in sfixed;
-		h_in		: in sfixed;
-		x_out		: out sfixed;
-		y_out		: out sfixed
-	);
-	END COMPONENT;
-
-	type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); 
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
-	--Inputs
-	SIGNAL ce         : std_logic := '1';
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL x_in        : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
-	--Outputs
-	SIGNAL x_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL y_out       : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-	SIGNAL x    	   : stages_t(0 to ntaps-2);
-	SIGNAL y           : stages_t(0 to ntaps-2);
-	
-	SIGNAL fileout_enable   : std_logic := '1';
-	
-	-- Test coefficients
-	function to_sfixed(x_real : real_array_t) return stages_t is
-	variable res : stages_t(x_real'range); 
-	begin
-		for i in x_real'range loop
-			res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
-		end loop;
-		
-		return res;
-	end to_sfixed;
-	
-	constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-	
-	SIGNAL xi, yo : real := 0.0;
-	
-BEGIN
-
-	xi <= to_real(x_in);
-	yo <= to_real(y_out);
-	
-	----------------------------------------
-	-- Instantiate the Unit Under Test (UUT)
-	----------------------------------------
-		uut_first_stage_sys: fir_stage_sys 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_in,
-			nbits_in_frac	=> nbits_in_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			input_latency	=> 1,
-			coef_latency	=> 1,
-			pipe_latency	=> 2
-		)
-		PORT MAP
-		(
-			clk			=> clk,
-			ce			=> ce,
-			x_in		=> x_in,
-			y_in		=> zero_in,
-			h_in		=> h(ntaps-1),
-			x_out		=> x(0),
-			y_out		=> y(0)
-		);
-
-	----------------------------------------
-    gen_stages:
-	for i in 1 to ntaps-2 generate
-		uut_stages: fir_stage_sys 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_stages,
-			nbits_out_frac	=> nbits_stages_frac,
-			input_latency	=> 2,
-			coef_latency	=> 1,
-			pipe_latency	=> 2
-		)
-		PORT MAP
-		(
-			clk			=> clk,
-			ce			=> ce,
-			x_in		=> x(i-1),
-			y_in		=> y(i-1),
-			h_in		=> h(ntaps-i-1),
-			x_out		=> x(i),
-			y_out		=> y(i)
-		);
-	end generate;
-	
-	----------------------------------------
-		uut_last_stage: fir_stage_sys 
-		GENERIC MAP
-		(
-			nbits_in		=> nbits_stages,
-			nbits_in_frac	=> nbits_stages_frac,
-			nbits_out		=> nbits_out,
-			nbits_out_frac	=> nbits_out_frac,
-			input_latency	=> 2,
-			coef_latency	=> 1,
-			pipe_latency	=> 2
-		)
-		PORT MAP
-		(
-			clk			=> clk,
-			ce			=> ce,
-			x_in		=> x(ntaps-2),
-			y_in		=> y(ntaps-2),
-			h_in		=> h(0),
-			x_out		=> x_out,
-			y_out		=> y_out
-		);
-
-	----------------------------------------
-	-- Finished instantiation
-	----------------------------------------
-	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		x_in <= to_sfixed(0.0, x_in);
-
-		wait for 40*PERIOD;
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(1.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-		wait until rising_edge(clk);
-		x_in <= to_sfixed(0.0, x_in);
-
-		wait for 150*PERIOD;
-		
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk, fileout_enable)
-	file RESULT_FIR:      text open write_mode is "fir.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' then
-			fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
-		end if;
-
-	END PROCESS;
-	
-END;
diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd
deleted file mode 100644
index 6397ebc..0000000
--- a/lib/fix_std/fix_std.vhd
+++ /dev/null
@@ -1,1007 +0,0 @@
----------------------------------------------------------------------
--- 
--- Package fix_std
--- Fixed point arithmetic based on numeric_std
--- 
----------------------------------------------------------------------
--- 
--- This document describes a VHDL package of definitions and subprograms 
--- intended to support the use of fixed-point arithmetic in test benches 
--- and synthesisable designs.  This document and the package it describes 
--- are made freely available to the HDL design community without warranty 
--- of any kind.  You are welcome to make use of this information for your 
--- own private study and in your own designs.  If you make use of the 
--- package, you accept sole responsibility for its fitness for purpose 
--- and its suitability in your application.  You are free to modify the 
--- package in any way, and to record your contribution to it, but this 
--- notice must appear in a prominent place in any modified or derived 
--- version of the package or its supporting documentation.
--- 
--- The author wishes to thank his employer Doulos Ltd for making 
--- available the facilities used to develop, test and distribute this 
--- package.  However, Doulos Ltd accepts no responsibility for the 
--- package's contents and cannot support it in any way.
--- 
----------------------------------------------------------------------
--- Revision information:
--- 
--- Version 0.1  06-May-2003
---   Alpha version, for review
---   No division operators are provided, pending detailed
---   consultation on their functionality.
---   Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2 11-Jun-2003
---   Fixes aiming to make the package portable across all synthesis tools:
---   * Removed deferred constants, made them package constants
---   * Removed all variable initialisations in procedures, made them
---     procedural initialisations in the code
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package fix_std is
-
-  --------------------------------------------------------------------
-
-  -- Integer subtype specifying legal values for a bit index.
-  -- At present it's restricted to 'natural' to conform with
-  -- the behaviour of mainstream synthesis tools.  For simulation,
-  -- or in the future when synthesis tools are able to cope, it
-  -- would be possible to change this subtype to be the full
-  -- integer range, thus allowing negative subscripts for
-  -- fraction bits.
-  --
-  subtype Fix_Subscr is natural;
-  
-  -- Fixed-point offset, the bit number (subscript) used for
-  -- the bit in a UFix or SFix vector having binary weight 2^0
-  -- (the units bit).
-  --
-  constant FixP: Fix_Subscr := 100;
-
-  -- Type declarations for the basic unsigned and signed fixed point
-  -- data types:
-  --
-  type UFix is array (Fix_Subscr range <>) of std_logic;
-  type SFix is array (Fix_Subscr range <>) of std_logic;
-
-  -- Type declarations for control of rounding and overflow modes:
-  --
-  type Fix_Rounding_Mode is (
-    clip_LS,      -- Throw away unwanted least significant bits
-    towards_zero, -- Round towards zero - same as clip_LS for UFix
-    to_nearest    -- Round to nearest.  Exact halves round up.
-  );
-  type Fix_Overflow_Mode is (
-    clip_MS,      -- Throw away unwanted most significant bits
-    saturate      -- Saturate overflow to nearest representable value
-  );
-
-  -- Defaults for these modes:
-  --
-  constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
-  constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
-  --------------------------------------------------------------------
-
-  ---------------------------
-  -- E.  Extraction functions
-  ---------------------------
-
-  -- E.1.  Return the integral part of a UFix value
-  function Int(U: UFix) return UFix;
-
-  -- E.2.  Return the fractional part of a UFix value
-  function Frac(U: UFix) return UFix;
-
-  -- E.3.  Return the integral part of a SFix value
-  function Int(S: SFix) return SFix;
-
-  -- E.4.  Return the fractional part of a SFix value
-  function Frac(S: SFix) return UFix;
-
-  -- E.5.  Widen a SFix value if necessary so that
-  --       its range adjoins or spans the binary point
-  function Span(S: SFix) return SFix;
-
-  -- E.6.  Widen a UFix value if necessary so that
-  --       its range adjoins or spans the binary point
-  function Span(U: UFix) return UFix;
-  
-  ---------------------------
-  -- T.  Conversion functions
-  ---------------------------
-
-  -- T.1 to T.8: Unsigned conversions
-  --
-  -- T.1.  Resizing an existing UFix.  Provide number of 
-  --       integer bits and number of fraction bits.
-  --
-  function to_UFix(
-    N         : UFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix;
-
-  -- T.2.  Resizing an existing SFix.  Provide number of 
-  --       integer bits and number of fraction bits.
-  --
-  function to_UFix(
-    N         : SFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix;
-
-  -- T.3.  Conversion from integer to UFix.  Provide number of 
-  --       integer bits and number of fraction bits.  Note that 
-  --       negative input is tolerated!
-  --
-  function to_UFix(
-    N         : integer;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix;
-
-  -- T.4.  Conversion from unsigned to UFix.  Provide subscripts of 
-  --       MS and (optionally) LS bit of the resulting UFix.
-  --
-  function to_UFix(
-    N         : unsigned;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix;
-
-  -- T.5.  Conversion from  unsigned to UFix.  Automatically set the
-  --       range of the resulting UFix to match the unsigned value,
-  --       as an integral UFix value with no fraction bits.
-  --
-  function to_UFix( N : unsigned ) return UFix;
-
-  -- T.6.  Conversion from UFix to unsigned.  All integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_unsigned(
-    N        : UFix;
-    rounding : Fix_Rounding_Mode   := Fix_Default_Rounding
-  ) return unsigned;
-
-  -- T.7.  Conversion from UFix to unsigned.  Caller specifies
-  --       required number of bits in unsigned result.
-  --
-  function to_unsigned(
-    N        : UFix;
-    bits     : positive;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return unsigned;
-
-  -- T.8.  Conversion from UFix to integer. Up to 31 integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_integer(
-    N        : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return integer;
-
-
-  -- T.9 to T.16: Signed conversions
-  --
-  -- T.9.  Resizing an existing UFix.  Provide number of 
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : UFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix;
-
-  -- T.10. Resizing an existing SFix.  Provide number of 
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : SFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix;
-
-  -- T.11. Conversion from integer to SFix.  Provide number of 
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : integer;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix;
-
-  -- T.12. Conversion from signed to SFix.  Provide subscripts of 
-  --       MS and (optionally) LS bit of the resulting SFix.
-  --
-  function to_SFix(
-    N         : signed;
-    MSB_index : Fix_Subscr;      
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix;
-
-  -- T.13. Conversion from signed to SFix.  Automatically set the
-  --       range of the resulting SFix to match the signed value,
-  --       as an integral SFix value with no fraction bits.
-  --
-  function to_SFix( N : signed ) return SFix;
-
-  -- T.14. Conversion from SFix to signed.  All integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_signed(
-    N        : SFix;
-    rounding : Fix_Rounding_Mode   := Fix_Default_Rounding
-  ) return signed;
-
-  -- T.15. Conversion from SFix to signed.  Caller specifies
-  --       required number of bits in signed result.
-  --
-  function to_signed(
-    N        : SFix;
-    bits     : positive;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return signed;
-
-  -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_integer(
-    N        : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return integer;
-  
-  -- T.17. Conversion from UFix to SFix.  This simply adds
-  --       an extra more significant bit, set to zero.
-  --
-  function  to_SFix(U: UFix) return SFix;
-
-  ----------------------------------
-  -- V.  Copy-to-variable procedures
-  ----------------------------------
-
-  -- Range-aware copying of an expression into a variable.  The
-  -- ranges of destination variable and source expression are 
-  -- used to determine correct rounding, overflow and scaling
-  -- behaviour.
-
-  -- V.1 to V.5: Copy an expression into a UFix variable
-  --
-
-  -- V.1. Copy UFix to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-  --
-  -- V.2. Copy SFix to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.3. Copy UNSIGNED to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : unsigned;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.4. Copy SIGNED to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : signed;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.5. Copy integer to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : integer;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.6 to V.10: Copy an expression into a SFix variable
-  --
-
-  -- V.6. Copy UFix to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.7. Copy SFix to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.8. Copy UNSIGNED to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : unsigned;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.9. Copy SIGNED to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : signed;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- V.10. Copy integer to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : integer;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-
-  --------------------------------
-  -- S.  Copy-to-signal procedures
-  --------------------------------
-  --
-  -- Range-aware copying of an expression into a signal.  The
-  -- ranges of destination signal and source expression are 
-  -- used to determine correct rounding, overflow and scaling
-  -- behaviour.
-
-  -- S.1 to S.5: Copy an expression into a UFix signal
-  --
-
-  -- S.1. Copy UFix to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : UFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.1. Copy SFix to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : SFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.3. Copy UNSIGNED to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : unsigned;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.4. Copy SIGNED to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : signed;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.5. Copy integer to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : integer;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.6 to S.10: Copy an expression into a SFix signal
-  --
-
-  -- S.6. Copy UFix to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : UFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.7. Copy SFix to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : SFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.8. Copy UNSIGNED to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : unsigned;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.9. Copy SIGNED to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : signed;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-  -- S.10. Copy integer to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : integer;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  );
-
-
-  ------------------------------------------------------------------
-  -- A.  Arithmetic operations involving UFix, SFix and other 
-  --     numeric types.
-  --     The operators are overloaded for most of the sensible
-  --     combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
-  --
-  -- IMPORTANT NOTE:
-  --   Arithmetic operators return a result that is wide enough
-  --   and precise enough so that no information is lost.  THIS IS
-  --   SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
-  --   In the detailed description that follow, "scaling" means
-  --   the numerical value (weight) of the least significant bit
-  --   in a fixed-point value.
-  --
-  -- ADDITION returns a result whose least significant bit
-  -- is the same as the least significant bit in either operand,
-  -- and whose most significant bit is one position higher than
-  -- the most significant bit in either operand.  Addition of 
-  -- two operands having the same bounds therefore results in
-  -- a growth of one bit at the most significant end.
-  --
-  -- SUBTRACTION where one or both operands are signed behaves 
-  -- in the same way as addition.  Subtraction where both operands
-  -- are unsigned returns a result whose most significant bit
-  -- position is the same as the most significant bit in either
-  -- operand, and whose least significant bit is the same as the
-  -- least significant bit in either operand.
-  --
-  -- MULTIPLICATION returns a result whose width is the sum of
-  -- the widths of its two operands, and whose scaling is the 
-  -- product of its two operands' scalings.
-  --
-  -- UNARY NEGATION always gives a result having one more 
-  -- significant bit than the operand.
-  --
-  -- ABSOLUTE VALUE always gives a result having exactly the
-  -- same subtype as its operand.
-  --
-  -- In binary operations where one operand is a fixed-point type
-  -- and the other is an integer numeric type, the integer operand
-  -- is first converted to a fixed-point type of the same subtype
-  -- as the other operand using Copy_V with default rounding and 
-  -- overflow modes.  The operation is then performed between two 
-  -- fixed-point operands in the normal way.
-  --
-  ------------------------------------------------------------------
-
-
-  ------------------------------------
-  -- A.1.  Unary "-" negation operator
-  ------------------------------------
-
-  -- A.1.1.  SFix := - UFix
-  function "-" (R: UFix) return SFix;
-
-  -- A.1.2.  SFix := - SFix
-  function "-" (R: SFix) return SFix;
-
-
-  --------------------------------------------
-  -- A.2.  Unary "abs" absolute-value operator
-  --------------------------------------------
-
-  -- A.2.1.  SFix := abs SFix
-  function "abs" (R: SFix) return SFix;
-
-
-  -------------------------------------
-  -- A.3.  Binary "+" addition operator
-  -------------------------------------
-
-  -- A.3.1.  UFix := UFix + UFix
-  function "+" (L: UFix; R: UFix) return UFix;
-
-  -- A.3.2.  UFix := UFix + unsigned
-  function "+" (L: UFix; R: unsigned) return UFix;
-
-  -- A.3.3.  UFix := unsigned + UFix
-  function "+" (L: unsigned; R: UFix) return UFix;
-
-  -- A.3.4.  UFix := UFix + natural
-  function "+" (L: UFix; R: natural) return UFix;
-
-  -- A.3.5.  UFix := natural + UFix
-  function "+" (L: natural; R: UFix) return UFix;
-
-  -- A.3.6.  SFix := SFix + SFix
-  function "+" (L: SFix; R: SFix) return SFix;
-
-  -- A.3.7.  SFix := SFix + UFix
-  function "+" (L: SFix; R: UFix) return SFix;
-
-  -- A.3.8.  SFix := UFix + SFix
-  function "+" (L: UFix; R: SFix) return SFix;
-
-  -- A.3.9.  SFix := SFix + signed
-  function "+" (L: SFix; R: signed) return SFix;
-
-  -- A.3.10. SFix := signed + SFix
-  function "+" (L: signed; R: SFix) return SFix;
-
-  -- A.3.11. SFix := SFix + integer
-  function "+" (L: SFix; R: integer) return SFix;
-
-  -- A.3.12. SFix := integer + SFix
-  function "+" (L: integer; R: SFix) return SFix;
-
-
-  ----------------------------------------
-  -- A.4.  Binary "-" subtraction operator
-  ----------------------------------------
-  --
-  -- NOTE: There is a special problem with subtraction 
-  -- operators that return a UFix result if that result
-  -- goes negative.  Our arbitrary decision is that we
-  -- truncate most-significant bits in this case.  If you
-  -- wish to avoid the risk of this arbitrarily-defined
-  -- truncation behaviour, change one or more of your 
-  -- operands to SFix and get a SFix result using this
-  -- idiom:
-  --   SFix := UFix + (-UFix)
-  -- or copy one of the UFix operands into a SFix that's
-  -- one bit wider, before performing the operation.
-  --
-  -- Subtractions returning a UFix result take unsigned
-  -- operands and do not exhibit bit growth.
-  -- Subtractions returning a SFix result take signed or
-  -- unsigned operands and exhibit one-bit growth like addition.
-
-  -- A.4.1.  UFix := UFix - UFix
-  function "-" (L: UFix; R: UFix) return UFix;
-
-  -- A.4.2.  UFix := UFix - unsigned
-  function "-" (L: UFix; R: unsigned) return UFix;
-
-  -- A.4.3.  UFix := unsigned - UFix
-  function "-" (L: unsigned; R: UFix) return UFix;
-
-  -- A.4.4.  UFix := UFix - natural
-  function "-" (L: UFix; R: natural) return UFix;
-
-  -- A.4.5.  UFix := natural - UFix
-  function "-" (L: natural; R: UFix) return UFix;
-
-  -- A.4.6.  SFix := SFix - SFix
-  function "-" (L: SFix; R: SFix) return SFix;
-
-  -- A.4.7.  SFix := SFix - UFix
-  function "-" (L: SFix; R: UFix) return SFix;
-
-  -- A.4.8.  SFix := UFix - SFix
-  function "-" (L: UFix; R: SFix) return SFix;
-
-  -- A.4.9.  SFix := SFix - signed
-  function "-" (L: SFix; R: signed) return SFix;
-
-  -- A.4.10. SFix := signed - SFix
-  function "-" (L: signed; R: SFix) return SFix;
-
-  -- A.4.11. SFix := SFix - integer
-  function "-" (L: SFix; R: integer) return SFix;
-
-  -- A.4.12. SFix := integer - SFix
-  function "-" (L: integer; R: SFix) return SFix;
-
-
-  -------------------------------------------
-  -- A.5.  Binary "*" multiplication operator
-  -------------------------------------------
-
-  -- A.5.1.  UFix := UFix * UFix
-  function "*" (L: UFix; R: UFix) return UFix;
-
-  -- A.5.2.  UFix := UFix * unsigned
-  function "*" (L: UFix; R: unsigned) return UFix;
-
-  -- A.5.3.  UFix := unsigned * UFix
-  function "*" (L: unsigned; R: UFix) return UFix;
-
-  -- A.5.4.  UFix := UFix * natural
-  function "*" (L: UFix; R: natural) return UFix;
-
-  -- A.5.5.  UFix := natural * UFix
-  function "*" (L: natural; R: UFix) return UFix;
-
-  -- A.5.6.  SFix := SFix * SFix
-  function "*" (L: SFix; R: SFix) return SFix;
-
-  -- A.5.7.  SFix := SFix * UFix
-  function "*" (L: SFix; R: UFix) return SFix;
-
-  -- A.5.8.  SFix := UFix * SFix
-  function "*" (L: UFix; R: SFix) return SFix;
-
-  -- A.5.9.  SFix := SFix * signed
-  function "*" (L: SFix; R: signed) return SFix;
-
-  -- A.5.10. SFix := signed * SFix
-  function "*" (L: signed; R: SFix) return SFix;
-
-  -- A.5.11. SFix := SFix * integer
-  function "*" (L: SFix; R: integer) return SFix;
-
-  -- A.5.12. SFix := integer * SFix
-  function "*" (L: integer; R: SFix) return SFix;
-
-
-  ------------------------------------------------------------------
-  -- R.  Relational operators - arithmetic comparisons involving  
-  --     UFix, SFix and other numeric types.
-  --     The operators are overloaded for most of the sensible
-  --     combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
-  --     Note that in all cases comparisons are exact;  if one 
-  --     operand has more fraction bits than the other, the less 
-  --     precise operand will have its LSBs zero-extended, and 
-  --     these zero bits will take part in comparison with whatever 
-  --     LSBs exist in the more precise operand.
-  ------------------------------------------------------------------
-
-  -------------------------------------
-  -- R.1.  Binary "=" equality operator
-  -------------------------------------
-
-  -- R.1.1.   UFix = UFix
-  function "=" (L: UFix; R: UFix) return boolean;
-
-  -- R.1.2.   UFix = unsigned
-  function "=" (L: UFix; R: unsigned) return boolean;
-
-  -- R.1.3.   unsigned = UFix
-  function "=" (L: unsigned; R: UFix) return boolean;
-
-  -- R.1.4.   UFix = integer
-  function "=" (L: UFix; R: integer) return boolean;
-
-  -- R.1.5.   integer = UFix
-  function "=" (L: integer; R: UFix) return boolean;
-
-  -- R.1.6.   SFix = SFix
-  function "=" (L: SFix; R: SFix) return boolean;
-
-  -- R.1.7.   SFix = UFix
-  function "=" (L: SFix; R: UFix) return boolean;
-
-  -- R.1.8.   UFix = SFix
-  function "=" (L: UFix; R: SFix) return boolean;
-
-  -- R.1.9.   SFix = signed
-  function "=" (L: SFix; R: signed) return boolean;
-
-  -- R.1.10.  signed = SFix
-  function "=" (L: signed; R: SFix) return boolean;
-
-  -- R.1.11.  SFix = integer
-  function "=" (L: SFix; R: integer) return boolean;
-
-  -- R.1.12.  integer = SFix
-  function "=" (L: integer; R: SFix) return boolean;
-
-
-  --------------------------------------
-  -- R.2.  Binary "<" less-than operator
-  --------------------------------------
-
-  -- R.2.1.   UFix < UFix
-  function "<" (L: UFix; R: UFix) return boolean;
-
-  -- R.2.2.   UFix < unsigned
-  function "<" (L: UFix; R: unsigned) return boolean;
-
-  -- R.2.3.   unsigned < UFix
-  function "<" (L: unsigned; R: UFix) return boolean;
-
-  -- R.2.4.   UFix < integer
-  function "<" (L: UFix; R: integer) return boolean;
-
-  -- R.2.5.   integer < UFix
-  function "<" (L: integer; R: UFix) return boolean;
-
-  -- R.2.6.   SFix < SFix
-  function "<" (L: SFix; R: SFix) return boolean;
-
-  -- R.2.7.   SFix < UFix
-  function "<" (L: SFix; R: UFix) return boolean;
-
-  -- R.2.8.   UFix < SFix
-  function "<" (L: UFix; R: SFix) return boolean;
-
-  -- R.2.9.   SFix < signed
-  function "<" (L: SFix; R: signed) return boolean;
-
-  -- R.2.10.  signed < SFix
-  function "<" (L: signed; R: SFix) return boolean;
-
-  -- R.2.11.  SFix < integer
-  function "<" (L: SFix; R: integer) return boolean;
-
-  -- R.2.12.  integer < SFix
-  function "<" (L: integer; R: SFix) return boolean;
-
-
-  ----------------------------------------
-  -- R.3.  Binary "/=" inequality operator
-  ----------------------------------------
-
-  -- R.3.1.   UFix /= UFix
-  function "/=" (L: UFix; R: UFix) return boolean;
-
-  -- R.3.2.   UFix /= unsigned
-  function "/=" (L: UFix; R: unsigned) return boolean;
-
-  -- R.3.3.   unsigned /= UFix
-  function "/=" (L: unsigned; R: UFix) return boolean;
-
-  -- R.3.4.   UFix /= integer
-  function "/=" (L: UFix; R: integer) return boolean;
-
-  -- R.3.5.   integer /= UFix
-  function "/=" (L: integer; R: UFix) return boolean;
-
-  -- R.3.6.   SFix /= SFix
-  function "/=" (L: SFix; R: SFix) return boolean;
-
-  -- R.3.7.   SFix /= UFix
-  function "/=" (L: SFix; R: UFix) return boolean;
-
-  -- R.3.8.   UFix /= SFix
-  function "/=" (L: UFix; R: SFix) return boolean;
-
-  -- R.3.9.   SFix /= signed
-  function "/=" (L: SFix; R: signed) return boolean;
-
-  -- R.3.10.  signed /= SFix
-  function "/=" (L: signed; R: SFix) return boolean;
-
-  -- R.3.11.  SFix /= integer
-  function "/=" (L: SFix; R: integer) return boolean;
-
-  -- R.3.12.  integer /= SFix
-  function "/=" (L: integer; R: SFix) return boolean;
-
-
-  -----------------------------------------
-  -- R.4.  Binary ">" greater-than operator
-  -----------------------------------------
-
-  -- R.4.1.   UFix > UFix
-  function ">" (L: UFix; R: UFix) return boolean;
-
-  -- R.4.2.   UFix > unsigned
-  function ">" (L: UFix; R: unsigned) return boolean;
-
-  -- R.4.3.   unsigned > UFix
-  function ">" (L: unsigned; R: UFix) return boolean;
-
-  -- R.4.4.   UFix > integer
-  function ">" (L: UFix; R: integer) return boolean;
-
-  -- R.4.5.   integer > UFix
-  function ">" (L: integer; R: UFix) return boolean;
-
-  -- R.4.6.   SFix > SFix
-  function ">" (L: SFix; R: SFix) return boolean;
-
-  -- R.4.7.   SFix > UFix
-  function ">" (L: SFix; R: UFix) return boolean;
-
-  -- R.4.8.   UFix > SFix
-  function ">" (L: UFix; R: SFix) return boolean;
-
-  -- R.4.9.   SFix > signed
-  function ">" (L: SFix; R: signed) return boolean;
-
-  -- R.4.10.  signed > SFix
-  function ">" (L: signed; R: SFix) return boolean;
-
-  -- R.4.11.  SFix > integer
-  function ">" (L: SFix; R: integer) return boolean;
-
-  -- R.4.12.  integer > SFix
-  function ">" (L: integer; R: SFix) return boolean;
-
-
-  ----------------------------------------------
-  -- R.5.  Binary ">=" greater-or-equal operator
-  ----------------------------------------------
-
-  -- R.5.1.   UFix >= UFix
-  function ">=" (L: UFix; R: UFix) return boolean;
-
-  -- R.5.2.   UFix >= unsigned
-  function ">=" (L: UFix; R: unsigned) return boolean;
-
-  -- R.5.3.   unsigned >= UFix
-  function ">=" (L: unsigned; R: UFix) return boolean;
-
-  -- R.5.4.   UFix >= integer
-  function ">=" (L: UFix; R: integer) return boolean;
-
-  -- R.5.5.   integer >= UFix
-  function ">=" (L: integer; R: UFix) return boolean;
-
-  -- R.5.6.   SFix >= SFix
-  function ">=" (L: SFix; R: SFix) return boolean;
-
-  -- R.5.7.   SFix >= UFix
-  function ">=" (L: SFix; R: UFix) return boolean;
-
-  -- R.5.8.   UFix >= SFix
-  function ">=" (L: UFix; R: SFix) return boolean;
-
-  -- R.5.9.   SFix >= signed
-  function ">=" (L: SFix; R: signed) return boolean;
-
-  -- R.5.10.  signed >= SFix
-  function ">=" (L: signed; R: SFix) return boolean;
-
-  -- R.5.11.  SFix >= integer
-  function ">=" (L: SFix; R: integer) return boolean;
-
-  -- R.5.12.  integer >= SFix
-  function ">=" (L: integer; R: SFix) return boolean;
-
-
-  -------------------------------------------
-  -- R.6.  Binary "<=" less-or-equal operator
-  -------------------------------------------
-
-  -- R.6.1.   UFix <= UFix
-  function "<=" (L: UFix; R: UFix) return boolean;
-
-  -- R.6.2.   UFix <= unsigned
-  function "<=" (L: UFix; R: unsigned) return boolean;
-
-  -- R.6.3.   unsigned <= UFix
-  function "<=" (L: unsigned; R: UFix) return boolean;
-
-  -- R.6.4.   UFix <= integer
-  function "<=" (L: UFix; R: integer) return boolean;
-
-  -- R.6.5.   integer <= UFix
-  function "<=" (L: integer; R: UFix) return boolean;
-
-  -- R.6.6.   SFix <= SFix
-  function "<=" (L: SFix; R: SFix) return boolean;
-
-  -- R.6.7.   SFix <= UFix
-  function "<=" (L: SFix; R: UFix) return boolean;
-
-  -- R.6.8.   UFix <= SFix
-  function "<=" (L: UFix; R: SFix) return boolean;
-
-  -- R.6.9.   SFix <= signed
-  function "<=" (L: SFix; R: signed) return boolean;
-
-  -- R.6.10.  signed <= SFix
-  function "<=" (L: signed; R: SFix) return boolean;
-
-  -- R.6.11.  SFix <= integer
-  function "<=" (L: SFix; R: integer) return boolean;
-
-  -- R.6.12.  integer <= SFix
-  function "<=" (L: integer; R: SFix) return boolean;
-
-
-  ------------------------------------------------------------------
-  -- C.  Concatenation operators between fixed-point operands, and
-  --     between fixed-point operands and other reasonable types.
-  --     Unlike the implicitly defined "&" operator, they preserve
-  --     place value and return an appropriately aligned subtype.
-  --     Preservation of place value means that some concatenation
-  --     operations are illegal.  In particular, operations
-  --     [SFix & SFix] and [UFix & SFix] are illegal, and 
-  --     the place values of operands in [SFix & UFix] and 
-  --     [UFix & UFix] must match up - the rightmost subscript of
-  --     the left operand must be one higher than the leftmost
-  --     subscript of the right operand.
-  --     Single bits of type std_ulogic may be concatenated with
-  --     fixed-point types where there is no risk of losing 
-  --     sign-extension information.
-  --     Because of the way VHDL defines implicit concatenation,
-  --     it is impossible to detect all these errors at compile time.
-  --     Instead they are detected by assertion statements at run time.
-  --     Tool vendors may choose to implement compile-time checks
-  --     so that the run-time checking overhead can be avoided.
-  ------------------------------------------------------------------
-
-  -- C.1.1.   UFix := UFix & UFix
-  function "&" (L: UFix; R: UFix) return UFix;
-  
-  -- No need to define "&"[UFix, SFix] explicitly,  because
-  -- the types are incompatible and so there's no default
-
-  -- C.1.2.   UFix := UFix & std_ulogic
-  function "&" (L: UFix; R: std_ulogic) return UFix;
-
-  -- C.1.3.   UFix := std_ulogic & UFix
-  function "&" (L: std_ulogic; R: UFix) return UFix;
-
-
-  -- C.2.1.   SFix := SFix & UFix
-  function "&" (L: SFix; R: UFix) return SFix;
-
-  -- C.2.2.   SFix := SFix & SFix -- ILLEGAL
-  function "&" (L: SFix; R: SFix) return SFix;
-
-  -- C.2.3.   SFix := SFix & std_ulogic
-  function "&" (L: SFix; R: std_ulogic) return SFix;
-
-  -- C.2.4.   SFix := std_ulogic & SFix
-  function "&" (L: std_ulogic; R: SFix) return SFix;
-
-
-end; -- package fix_std;
diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd
deleted file mode 100644
index 695cd11..0000000
--- a/lib/fix_std/fix_stdb.vhd
+++ /dev/null
@@ -1,1910 +0,0 @@
----------------------------------------------------------------------
---
--- Package body fix_std
--- Fixed point arithmetic based on numeric_std
--- Compile using VHDL-93 (required to support 'ASCENDING
--- array attribute).
---
----------------------------------------------------------------------
---
--- This document describes a VHDL package of definitions and subprograms
--- intended to support the use of fixed-point arithmetic in test benches
--- and synthesisable designs.  This document and the package it describes
--- are made freely available to the HDL design community without warranty
--- of any kind.  You are welcome to make use of this information for your
--- own private study and in your own designs.  If you make use of the
--- package, you accept sole responsibility for its fitness for purpose
--- and its suitability in your application.  You are free to modify the
--- package in any way, and to record your contribution to it, but this
--- notice must appear in a prominent place in any modified or derived
--- version of the package or its supporting documentation.
---
--- The author wishes to thank his employer Doulos Ltd for making
--- available the facilities used to develop, test and distribute this
--- package.  However, Doulos Ltd accepts no responsibility for the
--- package's contents and cannot support it in any way.
---
----------------------------------------------------------------------
--- Revision information:
---
--- Version 0.1  06-May-2003
---   Alpha version, for review
---   No division operators are provided, pending detailed
---   consultation on their functionality.
---   Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2  11-Jun-2003
---   Fixes aiming to make the package portable across all synthesis tools:
---   * Removed deferred constants, made them package constants
---   * Removed all variable initialisations in procedures, made them
---     procedural initialisations in the code
---   * Fixed definition of extract functions to return just one bit
---     if their results would otherwise be null
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package body fix_std is
-
-  --------------------------------------------------------------------
-  -- DEFERRED CONSTANTS
-  --------------------------------------------------------------------
-  -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
-  -- IMPLEMENTATIONS OR APPLICATIONS.
-  --------------------------------------------------------------------
-
-  -- Fixed-point offset, the bit number (subscript) used for
-  -- the bit in a UFix or SFix vector having binary weight 2^0
-  -- (the units bit).
-  --
-  -- constant FixP : Fix_Subscr := 100;
-
-  -- Default values for overflow and rounding modes:
-  --
-  -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
-  -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
-  --------------------------------------------------------------------
-  -- END OF DEFERRED CONSTANTS
-  --------------------------------------------------------------------
-
-  --------------------------------------------------------------------
-  -- IMPLEMENTATION CONSTANTS
-  --------------------------------------------------------------------
-  -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
-  -- IMPLEMENTATIONS OR APPLICATIONS.
-  --------------------------------------------------------------------
-
-  -- Severity levels for various errors
-
-  -- Concatenation errors - bad sign extension, discontiguous range etc
-  -- These are only warnings - they just give the wrong answer.
-  --
-  constant concat_severity    : severity_level := WARNING;
-
-  -- Subtype direction errors - the present implementation can't
-  -- handle fixed-point objects with ascending ranges.  These messages
-  -- are intended to give early warning of problems that would
-  -- definitely cause other fatal errors at elaboration or run time.
-  --
-  constant direction_severity : severity_level := FAILURE;
-
-  -- Assertion error message constants
-
-  constant bad_direction_msg : string :=
-           " has ascending range";
-
-  constant concat_range_msg  : string :=
-           "Concatenation bounds should have contiguous ranges";
-
-  constant concat_sxt_msg    : string :=
-           "Concatenation corrupts sign of result";
-
-  constant concat_signLS_msg : string :=
-           "RHS of concatenation should be unsigned";
-
-  constant compare_meta_msg  : string :=
-           "Metavalue detected in FIX_STD comparison, returning FALSE";
-
-  --------------------------------------------------------------------
-  -- END OF IMPLEMENTATION CONSTANTS
-  --------------------------------------------------------------------
-
-  --------------------------------------------------------------------
-  -- DO NOT MODIFY ANY CODE BELOW THIS POINT.
-  --------------------------------------------------------------------
-
-  -- Assumed bit width of INTEGER type in VHDL
-  --
-  constant INT_WIDTH : positive := 32;
-
-  -- Single-bit zero values
-  subtype Izero_UFixT is UFix(FixP downto FixP);
-  subtype Izero_SFixT is SFix(FixP downto FixP);
-  subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1);
-  constant Izero_UFix: Izero_UFixT := "0";
-  constant Izero_SFix: Izero_SFixT := "0";
-  constant Fzero_UFix: Fzero_UFixT := "0";
-
-  --------------------------------------------------------------------
-  -- LOCAL PRIVATE SUBPROGRAMS
-  --------------------------------------------------------------------
-
-  -- Min, Max: Find minimum and maximum of two integers.
-  -- Useful for determining appropriate range for operation results.
-  --
-  function Max(L, R: Fix_Subscr) return Fix_Subscr is
-  begin
-    if L>R then
-      return L;
-    else
-      return R;
-    end if;
-  end;
-  --
-  function Min(L, R: Fix_Subscr) return Fix_Subscr is
-  begin
-    if L<R then
-      return L;
-    else
-      return R;
-    end if;
-  end;
-
-  -- concat:
-  --
-  -- This helper function automates the calculation of return
-  -- subtype range in concatenation operators "&".
-  --
-  function concat(L, R: std_logic_vector) return std_logic_vector is
-    variable F: std_logic_vector(L'LEFT downto R'RIGHT);
-  begin
-    if L'LENGTH = 0 then
-      return R;
-    elsif R'LENGTH = 0 then
-      return L;
-    else
-      assert L'RIGHT = R'LEFT+1
-        report concat_range_msg
-        severity concat_severity;
-      F := L & R;
-      return F;
-    end if;
-  end;
-  --
-  function concat(L: std_logic; R: std_logic_vector)
-  return std_logic_vector is
-    variable F: std_logic_vector(R'LEFT+1 downto R'RIGHT);
-  begin
-    F := L & R;
-    return F;
-  end;
-  --
-  function concat(L: std_logic_vector; R: std_ulogic)
-  return std_logic_vector is
-    variable F: std_logic_vector(L'LEFT downto L'RIGHT-1);
-  begin
-    F := L & R;
-    return F;
-  end;
-
-  --------------------------------------------------------------------
-  -- IMPLEMENTATIONS OF PUBLIC SUBPROGRAMS
-  --------------------------------------------------------------------
-
-  ---------------------------
-  -- E.  Extraction functions
-  ---------------------------
-
-  -- E.1.  Return the integral part of a UFix value
-  function Int(U: UFix) return UFix is
-  begin
-    if U'LEFT < FixP then
-      return Izero_UFix;
-    elsif U'RIGHT > FixP then
-      return Span(U);
-    else
-      return U(U'LEFT downto FixP);
-    end if;
-  end;
-
-  -- E.2.  Return the fractional part of a UFix value
-  function Frac(U: UFix) return UFix is
-  begin
-    if U'LEFT < FixP-1 then
-      return Span(U);
-    elsif U'RIGHT >= FixP then
-      return Fzero_UFix;
-    else
-      return U(FixP-1 downto U'RIGHT);
-    end if;
-  end;
-
-  -- E.3.  Return the integral part of a SFix value
-  function Int(S: SFix) return SFix is
-  begin
-    if S'LENGTH = 0 then
-      return Izero_SFix;
-    elsif S'LEFT <= FixP then
-      return SFix'(FixP => S(S'LEFT));
-    elsif S'RIGHT > FixP then
-      return Span(S);
-    else
-      return S(S'LEFT downto FixP);
-    end if;
-  end;
-
-  -- E.4.  Return the fractional part of a SFix value
-  function Frac(S: SFix) return UFix is
-    variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
-  begin
-    if S'LEFT < FixP then
-      for I in FixP-1 downto S'LEFT+1 loop
-        P(I) := S(S'LEFT);
-      end loop;
-      P(S'RANGE) := S;
-      return UFix(S(FixP-1 downto S'RIGHT));
-    elsif S'RIGHT >= FixP then
-      return Fzero_UFix;
-    else
-      return UFix(S(FixP-1 downto S'RIGHT));
-    end if;
-  end;
-
-  -- E.5.  Widen a SFix value if necessary so that
-  --       its range adjoins or spans the binary point
-  function Span(S: SFix) return SFix is
-    variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
-  begin
-    F(S'RANGE) := S;
-    for I in F'LEFT downto S'LEFT+1 loop
-      F(I) := S(S'LEFT);
-    end loop;
-    for I in S'RIGHT-1 downto F'RIGHT loop
-      F(I) := '0';
-    end loop;
-    return F;
-  end;
-
-  -- E.6.  Widen a UFix value if necessary so that
-  --       its range adjoins or spans the binary point
-  function Span(U: UFix) return UFix is
-    variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP));
-  begin
-    F(U'RANGE) := U;
-    for I in F'LEFT downto U'LEFT+1 loop
-      F(I) := '0';
-    end loop;
-    for I in U'RIGHT-1 downto F'RIGHT loop
-      F(I) := '0';
-    end loop;
-    return F;
-  end;
-
-  ---------------------------
-  -- T.  Conversion functions
-  ---------------------------
-
-  -- T.1 to T.8: Unsigned conversions
-
-  -- T.1.  Resizing an existing UFix.  Provide number of
-  --       integer bits and number of fraction bits.
-  --
-  function to_UFix(
-    N         : UFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix is
-    variable F: UFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.2.  Resizing an existing SFix.  Provide number of
-  --       integer bits and number of fraction bits.
-  --
-  function to_UFix(
-    N         : SFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix is
-    variable F: UFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.3.  Conversion from integer to UFix.  Provide number of
-  --       integer bits and number of fraction bits.  Note that
-  --       negative input is tolerated!
-  --
-  function to_UFix(
-    N         : integer;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix is
-    variable F: UFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.4.  Conversion from unsigned to UFix.  Provide subscripts of
-  --       MS and (optionally) LS bit of the resulting UFix.
-  --
-  function to_UFix(
-    N         : unsigned;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return UFix is
-    variable F: UFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.5.  Conversion from  unsigned to UFix.  Automatically set the
-  --       range of the resulting UFix to match the unsigned value,
-  --       as an integral UFix value with no fraction bits.
-  --
-  function to_UFix( N : unsigned ) return UFix is
-    variable F: UFix(FixP+N'LENGTH-1 downto FixP);
-  begin
-    F := UFix(N);
-    return F;
-  end;
-
-  -- T.6.  Conversion from UFix to unsigned.  All integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_unsigned(
-    N        : UFix;
-    rounding : Fix_Rounding_Mode   := Fix_Default_Rounding
-  ) return unsigned is
-    variable F_UFix: UFix(N'LEFT downto FixP);
-    variable F: unsigned(F_UFix'LENGTH-1 downto 0);
-  begin
-    Copy_V(F_UFix, N, rounding=>rounding);
-    F := unsigned(F_UFix);
-    return F;
-  end;
-
-  -- T.7.  Conversion from UFix to unsigned.  Caller specifies
-  --       required number of bits in unsigned result.
-  --
-  function to_unsigned(
-    N        : UFix;
-    bits     : positive;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return unsigned is
-    variable F_UFix: UFix(FixP+bits-1 downto FixP);
-    variable F: unsigned(F_UFix'LENGTH-1 downto 0);
-  begin
-    Copy_V(F_UFix, N, overflow, rounding);
-    F := unsigned(F_UFix);
-    return F;
-  end;
-
-  -- T.8.  Conversion from UFix to integer. Up to 31 integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_integer(
-    N        : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return integer is
-    variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP);
-  begin
-    Copy_V(F_UFix, N, overflow, rounding);
-    return to_integer(unsigned(F_UFix));
-  end;
-
-  -- T.9 to T.16: Signed conversions
-
-  -- T.9.  Resizing an existing UFix.  Provide number of
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : UFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix is
-    variable F: SFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.10. Resizing an existing SFix.  Provide number of
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : SFix;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix is
-    variable F: SFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.11. Conversion from integer to SFix.  Provide number of
-  --       integer bits and number of fraction bits.
-  --
-  function to_SFix(
-    N         : integer;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix is
-    variable F: SFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.12. Conversion from signed to SFix.  Provide subscripts of
-  --       MS and (optionally) LS bit of the resulting SFix.
-  --
-  function to_SFix(
-    N         : signed;
-    MSB_index : Fix_Subscr;
-    LSB_index : Fix_Subscr        := FixP;
-    overflow  : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding  : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return SFix is
-    variable F: SFix(MSB_index downto LSB_index);
-  begin
-    Copy_V(F, N, overflow, rounding);
-    return F;
-  end;
-
-  -- T.13. Conversion from signed to SFix.  Automatically set the
-  --       range of the resulting SFix to match the signed value,
-  --       as an integral SFix value with no fraction bits.
-  --
-  function to_SFix( N : signed ) return SFix is
-    variable F: SFix(FixP+N'LENGTH-1 downto FixP);
-  begin
-    F := SFix(N);
-    return F;
-  end;
-
-  -- T.14. Conversion from SFix to signed.  All integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_signed(
-    N        : SFix;
-    rounding : Fix_Rounding_Mode   := Fix_Default_Rounding
-  ) return signed is
-    variable F_SFix: SFix(N'LEFT downto FixP);
-    variable F: signed(F_SFix'LENGTH-1 downto 0);
-  begin
-    Copy_V(F_SFix, N, rounding=>rounding);
-    F := signed(F_SFix);
-    return F;
-  end;
-
-  -- T.15. Conversion from SFix to signed.  Caller specifies
-  --       required number of bits in signed result.
-  --
-  function to_signed(
-    N        : SFix;
-    bits     : positive;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return signed is
-    variable F_SFix: UFix(FixP+bits-1 downto FixP);
-    variable F: signed(F_SFix'LENGTH-1 downto 0);
-  begin
-    Copy_V(F_SFix, N, overflow, rounding);
-    F := signed(F_SFix);
-    return F;
-  end;
-
-  -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
-  --       preserved (including adding LS scale bits if necessary).
-  --
-  function to_integer(
-    N        : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) return integer is
-    variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP);
-  begin
-    Copy_V(F_SFix, N, overflow, rounding);
-    return to_integer(signed(F_SFix));
-  end;
-
-  -- T.17. Conversion from UFix to SFix.  This simply adds
-  --       an extra more significant bit, set to zero.
-  --
-  function  to_SFix(U: UFix) return SFix is
-    variable F: SFix(U'LEFT+1 downto U'RIGHT);
-  begin
-    F := SFix('0' & U);
-    return F;
-  end;
-
-
-  ----------------------------------
-  -- V.  Copy-to-variable procedures
-  ----------------------------------
-
-  -- Range-aware copying of an expression into a variable.  The
-  -- ranges of destination variable and source expression are
-  -- used to determine correct rounding, overflow and scaling
-  -- behaviour.
-
-  -- V.1 to V.5: Copy an expression into a UFix variable
-
-  -- V.1. Copy UFix to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    subtype target_T is UFix(target'RANGE);
-    variable W: UFix(Max(target'LEFT, source'LEFT+1) downto
-                     Min(target'RIGHT, source'RIGHT));
-    constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0');
-  begin
-    assert not target'ASCENDING
-      report "target" & bad_direction_msg
-      severity direction_severity;
-    assert not source'ASCENDING
-      report "source" & bad_direction_msg
-      severity direction_severity;
-    W := (others => '0');
-    W(source'RANGE) := source;
-    if target'RIGHT > source'RIGHT then
-      case rounding is
-        when clip_LS | towards_zero =>
-          null;
-        when to_nearest =>
-          W(W'LEFT downto target'RIGHT-1) := UFix(
-            unsigned(W(W'LEFT downto target'RIGHT-1)) + 1
-          );
-      end case;
-    end if;
-    target := W(target'RANGE);
-    if HighZero'LENGTH > 0 then
-      if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then
-        case overflow is
-          when clip_MS =>
-            null;
-          when saturate =>
-            target := target_T'(others => '1');
-        end case;
-      end if;
-    end if;
-  end;
-
-  -- V.2. Copy SFix to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT);
-    constant target_zero: UFix(target'RANGE) := (others => '0');
-  begin
-    assert not target'ASCENDING
-      report "target" & bad_direction_msg
-      severity direction_severity;
-    assert not source'ASCENDING
-      report "source" & bad_direction_msg
-      severity direction_severity;
-    W := (others => '0');
-    -- Rounding & sign-extend
-    Copy_V(W, source, clip_MS, rounding);
-    -- Saturation?
-    if W < 0 and overflow = saturate then
-      target := target_zero;
-    else
-      Copy_V(target, UFix(W), overflow, clip_LS);
-    end if;
-  end;
-
-  -- V.3. Copy UNSIGNED to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : unsigned;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source);
-  begin
-    Copy_V(target, U, overflow, rounding);
-  end;
-
-  -- V.4. Copy SIGNED to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : signed;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
-  begin
-    Copy_V(target, S, overflow, rounding);
-  end;
-
-  -- V.5. Copy integer to UFix
-  --
-  procedure Copy_V(
-    target   : out UFix;
-    source   : integer;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant N: signed(FixP+INT_WIDTH-1 downto FixP)
-              := to_signed(source, INT_WIDTH);
-  begin
-    -- Cop-out, this is very inefficient, but will do for now.
-    Copy_V(target, N, overflow, rounding);
-  end;
-
-  -- V.6 to V.10: Copy an expression into a SFix variable
-
-  -- V.6. Copy UFix to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : UFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source);
-  begin
-    Copy_V(target, S, overflow, rounding);
-  end;
-
-  -- V.7. Copy SFix to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : SFix;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    subtype target_T is SFix(target'RANGE);
-    variable W: SFix(Max(target'LEFT, source'LEFT+1) downto
-                     Min(target'RIGHT, source'RIGHT));
-    variable HighSX: SFix(W'LEFT downto target'LEFT+1);
-  begin
-    for i in HighSX'RANGE loop
-      HighSX(i) := source(source'LEFT);
-    end loop;
-    assert not target'ASCENDING
-      report "target" & bad_direction_msg
-      severity direction_severity;
-    assert not source'ASCENDING
-      report "source" & bad_direction_msg
-      severity direction_severity;
-    -- Make W a copy of source, duly extended at both ends
-    W := (others => '0');
-    W(source'RANGE) := source;
-    W(HighSX'RANGE) := HighSX;
-    -- Do any rounding required
-    if target'RIGHT > source'RIGHT then
-      case rounding is
-        when clip_LS =>
-          null;
-        when towards_zero =>
-          if
-            (to_UX01(W(W'LEFT)) = '1')   -- it's negative?
-          and
-            (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up?
-          then
-            W(W'LEFT downto target'RIGHT) := SFix(
-              signed(W(W'LEFT downto target'RIGHT)) + 1
-            );
-          end if;
-        when to_nearest =>
-          W(W'LEFT downto target'RIGHT-1) := SFix(
-            signed(W(W'LEFT downto target'RIGHT-1)) + 1
-          );
-      end case;
-    end if;
-    -- Do any overflow required
-    target := W(target'RANGE);
-    if HighSX'LENGTH > 0 then
-      if signed(W(HighSX'RANGE)) /= signed(HighSX) then
-        case overflow is
-          when clip_MS =>
-            null;
-          when saturate =>
-            target := Target_T'(others => not W(W'LEFT));
-            target(target'LEFT) := W(W'LEFT);
-        end case;
-      end if;
-    end if;
-  end;
-
-  -- V.8. Copy UNSIGNED to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : unsigned;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source);
-  begin
-    Copy_V(target, S, overflow, rounding);
-  end;
-
-  -- V.9. Copy SIGNED to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : signed;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
-  begin
-    Copy_V(target, S, overflow, rounding);
-  end;
-
-  -- V.10. Copy integer to SFix
-  --
-  procedure Copy_V(
-    target   : out SFix;
-    source   : integer;
-    overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-    rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    constant N: signed(FixP+INT_WIDTH-1 downto FixP)
-              := to_signed(source, INT_WIDTH);
-  begin
-    -- Cop-out, this is very inefficient, but will do for now.
-    Copy_V(target, N, overflow, rounding);
-  end;
-
-
-  --------------------------------
-  -- S.  Copy-to-signal procedures
-  --------------------------------
-  --
-  -- Range-aware copying of an expression into a signal.  The
-  -- ranges of destination signal and source expression are
-  -- used to determine correct rounding, overflow and scaling
-  -- behaviour.
-
-  -- S.1 to S.5: Copy an expression into a UFix signal
-  --
-
-  -- S.1. Copy UFix to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : UFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: UFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.1. Copy SFix to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : SFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: UFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.3. Copy UNSIGNED to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : unsigned;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: UFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.4. Copy SIGNED to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : signed;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: UFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.5. Copy integer to UFix
-  --
-  procedure Copy_S(
-    signal target   : out UFix;
-           source   : integer;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: UFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.6 to S.10: Copy an expression into a SFix signal
-  --
-
-  -- S.6. Copy UFix to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : UFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: SFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.7. Copy SFix to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : SFix;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: SFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.8. Copy UNSIGNED to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : unsigned;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: SFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.9. Copy SIGNED to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : signed;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: SFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-  -- S.10. Copy integer to SFix
-  --
-  procedure Copy_S(
-    signal target   : out SFix;
-           source   : integer;
-           overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
-           rounding : Fix_Rounding_Mode := Fix_Default_Rounding
-  ) is
-    variable V: SFix(target'RANGE);
-  begin
-    Copy_V(V, source, overflow, rounding);
-    target <= V;
-  end;
-
-
-  ------------------------------------------------------------------
-  -- A.  Arithmetic operations involving UFix, SFix and other
-  --     numeric types.
-  --     The operators are overloaded for most of the sensible
-  --     combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
-  --
-  -- IMPORTANT NOTE:
-  --   Arithmetic operators return a result that is wide enough
-  --   and precise enough so that no information is lost.  THIS IS
-  --   SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
-  --   In the detailed description that follow, "scaling" means
-  --   the numerical value (weight) of the least significant bit
-  --   in a fixed-point value.
-  --
-  -- ADDITION returns a result whose least significant bit
-  -- is the same as the least significant bit in either operand,
-  -- and whose most significant bit is one position higher than
-  -- the most significant bit in either operand.  Addition of
-  -- two operands having the same bounds therefore results in
-  -- a growth of one bit at the most significant end.  Addition
-  -- of an integer to a UFix or SFix is accomplished by first
-  -- converting the integer to the same subtype as the other
-  -- operand, thereby giving rise to one-bit growth;  default
-  -- truncation and rounding modes are used for the conversion.
-  --
-  -- SUBTRACTION where one or both operands are signed behaves
-  -- in the same way as addition.  Subtraction where both operands
-  -- are unsigned returns a result whose most significant bit
-  -- position is the same as the most significant bit in either
-  -- operand, and whose least significant bit is the same as the
-  -- least significant bit in either operand.
-  --
-  -- MULTIPLICATION returns a result whose width is the sum of
-  -- the widths of its two operands, and whose scaling is the
-  -- product of its two operands' scalings.
-  --
-  -- UNARY NEGATION always gives a result having one more
-  -- significant bit than the operand.
-  --
-  -- ABSOLUTE VALUE always gives a result having exactly the
-  -- same subtype as its operand.
-  --
-  -- In binary operations where one operand is a fixed-point type
-  -- and the other is an integer numeric type, the integer operand
-  -- is first converted to a fixed-point type of the same subtype
-  -- as the other operand using Copy_V with default rounding and
-  -- overflow modes.  The operation is then performed between two
-  -- fixed-point operands in the normal way.
-  --
-  ------------------------------------------------------------------
-
-
-  ------------------------------------
-  -- A.1.  Unary "-" negation operator
-  ------------------------------------
-
-  -- A.1.1.  SFix := - UFix
-  function "-" (R: UFix) return SFix is
-    variable F: SFix(R'LEFT+1 downto R'RIGHT);
-  begin
-    F := SFix(-(signed('0' & R)));
-    return F;
-  end;
-
-  -- A.1.2.  SFix := - SFix
-  function "-" (R: SFix) return SFix is
-    variable F: SFix(R'LEFT+1 downto R'RIGHT);
-  begin
-    F := SFix(-(signed(R(R'LEFT) & R)));
-    return F;
-  end;
-
-
-  --------------------------------------------
-  -- A.2.  Unary "abs" absolute-value operator
-  --------------------------------------------
-
-  -- A.2.1.  SFix := abs SFix
-  function "abs" (R: SFix) return SFix is
-    variable F: SFix(R'RANGE);
-  begin
-    F := R;
-    if to_X01(R(R'LEFT)) = '1' then
-      F := SFix(-(signed(R)));
-    end if;
-    return F;
-  end;
-
-
-  -------------------------------------
-  -- A.3.  Binary "+" addition operator
-  -------------------------------------
-
-  -- A.3.1.  UFix := UFix + UFix
-  function "+" (L: UFix; R: UFix) return UFix is
-    variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
-    variable LU, RU: unsigned(F'RANGE);
-  begin
-    LU := (others => '0');
-    RU := (others => '0');
-    LU(L'RANGE) := unsigned(L);
-    RU(R'RANGE) := unsigned(R);
-    F := UFix(LU + RU);
-    return F;
-  end;
-
-  -- A.3.2.  UFix := UFix + unsigned
-  function "+" (L: UFix; R: unsigned) return UFix is
-  begin
-    return L + to_UFix(R);
-  end;
-
-  -- A.3.3.  UFix := unsigned + UFix
-  function "+" (L: unsigned; R: UFix) return UFix is
-  begin
-    return R+L;
-  end;
-
-  -- A.3.4.  UFix := UFix + natural
-  function "+" (L: UFix; R: natural) return UFix is
-    variable R_fp: UFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L + R_fp;
-  end;
-
-  -- A.3.5.  UFix := natural + UFix
-  function "+" (L: natural; R: UFix) return UFix is
-  begin
-    return R+L;
-  end;
-
-  -- A.3.6.  SFix := SFix + SFix
-  function "+" (L: SFix; R: SFix) return SFix is
-    variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
-    variable LS, RS: signed(F'RANGE);
-  begin
-    LS := (others => '0');
-    RS := (others => '0');
-    LS(L'RANGE) := signed(L);
-    RS(R'RANGE) := signed(R);
-    for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop;
-    for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop;
-    F := SFix(LS + RS);
-    return F;
-  end;
-
-  -- A.3.7.  SFix := SFix + UFix
-  function "+" (L: SFix; R: UFix) return SFix is
-  begin
-    return L + SFix('0' & R);
-  end;
-
-  -- A.3.8.  SFix := UFix + SFix
-  function "+" (L: UFix; R: SFix) return SFix is
-  begin
-    return SFix('0' & L) + R;
-  end;
-
-  -- A.3.9.  SFix := SFix + signed
-  function "+" (L: SFix; R: signed) return SFix is
-  begin
-    return L + to_SFix(R);
-  end;
-
-  -- A.3.10. SFix := signed + SFix
-  function "+" (L: signed; R: SFix) return SFix is
-  begin
-    return to_SFix(L) + R;
-  end;
-
-  -- A.3.11. SFix := SFix + integer
-  function "+" (L: SFix; R: integer) return SFix is
-    variable R_fp: SFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L + R_fp;
-  end;
-
-  -- A.3.12. SFix := integer + SFix
-  function "+" (L: integer; R: SFix) return SFix is
-  begin
-    return R + L;
-  end;
-
-
-  ----------------------------------------
-  -- A.4.  Binary "-" subtraction operator
-  ----------------------------------------
-  --
-  -- NOTE: There is a special problem with subtraction
-  -- operators that return a UFix result if that result
-  -- goes negative.  Our arbitrary decision is that we
-  -- truncate most-significant bits in this case.  If you
-  -- wish to avoid the risk of this arbitrarily-defined
-  -- truncation behaviour, change one or more of your
-  -- operands to SFix and get a SFix result using this
-  -- idiom:
-  --   SFix := UFix + (-UFix)
-  -- or copy one of the UFix operands into a SFix that's
-  -- one bit wider, before performing the operation.
-  --
-  -- Subtractions returning a UFix result take unsigned
-  -- operands and do not exhibit bit growth.
-  -- Subtractions returning a SFix result take signed or
-  -- unsigned operands and exhibit one-bit growth like addition.
-
-  -- A.4.1.  UFix := UFix - UFix
-  function "-" (L: UFix; R: UFix) return UFix is
-    variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto
-                             Min(L'RIGHT, R'RIGHT));
-  begin
-    LW := (others => '0');
-    RW := (others => '0');
-    LW(L'RANGE) := L;
-    RW(R'RANGE) := R;
-    F := UFix(unsigned(LW) - unsigned(RW));
-    return F;
-  end;
-
-  -- A.4.2.  UFix := UFix - unsigned
-  function "-" (L: UFix; R: unsigned) return UFix is
-  begin
-    return L - to_UFix(R);
-  end;
-
-  -- A.4.3.  UFix := unsigned - UFix
-  function "-" (L: unsigned; R: UFix) return UFix is
-  begin
-    return to_UFix(L) - R;
-  end;
-
-  -- A.4.4.  UFix := UFix - integer
-  function "-" (L: UFix; R: natural) return UFix is
-    variable R_fp: UFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L - R_fp;
-  end;
-
-  -- A.4.5.  UFix := natural - UFix
-  function "-" (L: natural; R: UFix) return UFix is
-    variable L_fp: UFix(R'RANGE);
-  begin
-    Copy_V(L_fp, L);
-    return L_fp - R;
-  end;
-
-  -- A.4.6.  SFix := SFix - SFix
-  function "-" (L: SFix; R: SFix) return SFix is
-  begin
-    return L + (-R);
-  end;
-
-  -- A.4.7.  SFix := SFix - UFix
-  function "-" (L: SFix; R: UFix) return SFix is
-  begin
-    return L + (-R);
-  end;
-
-  -- A.4.8.  SFix := UFix - SFix
-  function "-" (L: UFix; R: SFix) return SFix is
-  begin
-    return To_SFix(L) - R;
-  end;
-
-  -- A.4.9.  SFix := SFix - signed
-  function "-" (L: SFix; R: signed) return SFix is
-  begin
-    return L - to_SFix(R);
-  end;
-
-  -- A.4.10. SFix := signed - SFix
-  function "-" (L: signed; R: SFix) return SFix is
-  begin
-    return to_SFix(L) - R;
-  end;
-
-  -- A.4.11. SFix := SFix - integer
-  function "-" (L: SFix; R: integer) return SFix is
-    variable R_fp: SFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L - R_fp;
-  end;
-
-  -- A.4.12. SFix := integer - SFix
-  function "-" (L: integer; R: SFix) return SFix is
-    variable L_fp: SFix(R'RANGE);
-  begin
-    Copy_V(L_fp, L);
-    return L_fp - R;
-  end;
-
-
-  -------------------------------------------
-  -- A.5.  Binary "*" multiplication operator
-  -------------------------------------------
-
-  -- A.5.1.  UFix := UFix * UFix
-  function "*" (L: UFix; R: UFix) return UFix is
-    variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
-  begin
-    F := UFix(unsigned(L) * unsigned(R));
-    return F;
-  end;
-
-  -- A.5.2.  UFix := UFix * unsigned
-  function "*" (L: UFix; R: unsigned) return UFix is
-  begin
-    return L * to_UFix(R);
-  end;
-
-  -- A.5.3.  UFix := unsigned * UFix
-  function "*" (L: unsigned; R: UFix) return UFix is
-  begin
-    return to_UFix(L) * R;
-  end;
-
-  -- A.5.4.  UFix := UFix * natural
-  function "*" (L: UFix; R: natural) return UFix is
-    variable R_fp: UFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L * R_fp;
-  end;
-
-  -- A.5.5.  UFix := natural * UFix
-  function "*" (L: natural; R: UFix) return UFix is
-  begin
-    return R * L;
-  end;
-
-  -- A.5.6.  SFix := SFix * SFix
-  function "*" (L: SFix; R: SFix) return SFix is
-    variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
-  begin
-    F := SFix(signed(L) * signed(R));
-    return F;
-  end;
-
-  -- A.5.7.  SFix := SFix * UFix
-  function "*" (L: SFix; R: UFix) return SFix is
-    constant RS: SFix := SFix('0' & R);
-    variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
-    variable FW: SFix(F'LEFT+1 downto F'RIGHT);
-  begin
-    FW := SFix(signed(L) * signed(RS));
-    Copy_V(F, FW);  -- never overflows
-    return F;
-  end;
-
-  -- A.5.8.  SFix := UFix * SFix
-  function "*" (L: UFix; R: SFix) return SFix is
-  begin
-    return R * L;
-  end;
-
-  -- A.5.9.  SFix := SFix * signed
-  function "*" (L: SFix; R: signed) return SFix is
-  begin
-    return L * to_SFix(R);
-  end;
-
-  -- A.5.10. SFix := signed * SFix
-  function "*" (L: signed; R: SFix) return SFix is
-  begin
-    return to_SFix(L) * R;
-  end;
-
-  -- A.5.11. SFix := SFix * integer
-  function "*" (L: SFix; R: integer) return SFix is
-    variable R_fp: SFix(L'RANGE);
-  begin
-    Copy_V(R_fp, R);
-    return L * R_fp;
-  end;
-
-  -- A.5.12. SFix := integer * SFix
-  function "*" (L: integer; R: SFix) return SFix is
-  begin
-    return R * L;
-  end;
-
-
-  ------------------------------------------------------------------
-  -- R.  Relational operators - arithmetic comparisons involving
-  --     UFix, SFix and other numeric types.
-  --     The operators are overloaded for most of the sensible
-  --     combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
-  --     Note that in all cases comparisons are exact;  if one
-  --     operand has more fraction bits than the other, the less
-  --     precise operand will have its LSBs zero-extended, and
-  --     these zero bits will take part in comparison with whatever
-  --     LSBs exist in the more precise operand.
-  --
-  -- Our implementation is based on only two operators, "=" and "<".
-  -- All other operators are derived from these two, either by
-  -- logical inversion of the result or by swapping operands.
-  ------------------------------------------------------------------
-
-  -------------------------------------
-  -- R.1.  Binary "=" equality operator
-  -------------------------------------
-
-  -- R.1.1.   UFix = UFix
-  function "=" (L: UFix; R: UFix) return boolean is
-    variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
-  begin
-    LW := (others => '0');
-    RW := (others => '0');
-    LW(L'RANGE) := L;
-    RW(R'RANGE) := R;
-    return unsigned(LW) = unsigned(RW);
-  end;
-
-  -- R.1.2.   UFix = unsigned
-  function "=" (L: UFix; R: unsigned) return boolean is
-  begin
-    return L = to_UFix(R);
-  end;
-
-  -- R.1.3.   unsigned = UFix
-  function "=" (L: unsigned; R: UFix) return boolean is
-  begin
-    return to_UFix(L) = R;
-  end;
-
-  -- R.1.4.   UFix = integer
-  function "=" (L: UFix; R: integer) return boolean is
-    variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(RS, R, clip_MS, clip_LS);
-    return To_SFix(L) = RS;
-  end;
-
-  -- R.1.5.   integer = UFix
-  function "=" (L: integer; R: UFix) return boolean is
-  begin
-    return R = L;
-  end;
-
-  -- R.1.6.   SFix = SFix
-  function "=" (L: SFix; R: SFix) return boolean is
-    variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
-  begin
-    -- clip modes are OK because we aren't losing any bits
-    Copy_V(LW, L, clip_MS, clip_LS);
-    Copy_V(RW, R, clip_MS, clip_LS);
-    return signed(LW) = signed(RW);
-  end;
-
-  -- R.1.7.   SFix = UFix
-  function "=" (L: SFix; R: UFix) return boolean is
-  begin
-    return L = To_SFix(R);
-  end;
-
-  -- R.1.8.   UFix = SFix
-  function "=" (L: UFix; R: SFix) return boolean is
-  begin
-    return R = L;
-  end;
-
-  -- R.1.9.   SFix = signed
-  function "=" (L: SFix; R: signed) return boolean is
-  begin
-    return L = to_SFix(R);
-  end;
-
-  -- R.1.10.  signed = SFix
-  function "=" (L: signed; R: SFix) return boolean is
-  begin
-    return to_SFix(L) = R;
-  end;
-
-  -- R.1.11.  SFix = integer
-  function "=" (L: SFix; R: integer) return boolean is
-    variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(RS, R, clip_MS, clip_LS);
-    return L = RS;
-  end;
-
-  -- R.1.12.  integer = SFix
-  function "=" (L: integer; R: SFix) return boolean is
-  begin
-    return R = L;
-  end;
-
-
-  --------------------------------------
-  -- R.2.  Binary "<" less-than operator
-  --------------------------------------
-
-  -- R.2.1.   UFix < UFix
-  function "<" (L: UFix; R: UFix) return boolean is
-    variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto
-                              Min(L'RIGHT, R'RIGHT));
-  begin
-    LW := (others => '0');
-    RW := (others => '0');
-    LW(L'RANGE) := unsigned(L);
-    RW(R'RANGE) := unsigned(R);
-    return unsigned(LW) < unsigned(RW);
-  end;
-
-  -- R.2.2.   UFix < unsigned
-  function "<" (L: UFix; R: unsigned) return boolean is
-  begin
-    return L < To_UFix(R);
-  end;
-
-  -- R.2.3.   unsigned < UFix
-  function "<" (L: unsigned; R: UFix) return boolean is
-  begin
-    return To_UFix(L) < R;
-  end;
-
-  -- R.2.4.   UFix < integer
-  function "<" (L: UFix; R: integer) return boolean is
-    variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(S, R, clip_MS, clip_LS);
-    return L < S;
-  end;
-
-  -- R.2.5.   integer < UFix
-  function "<" (L: integer; R: UFix) return boolean is
-    variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(S, L, clip_MS, clip_LS);
-    return S < R;
-  end;
-
-  -- R.2.6.   SFix < SFix
-  function "<" (L: SFix; R: SFix) return boolean is
-    variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto
-                          Min(L'RIGHT, R'RIGHT));
-  begin
-    Copy_V(LW, L, clip_MS, clip_LS);
-    Copy_V(RW, R, clip_MS, clip_LS);
-    return signed(LW) < signed(RW);
-  end;
-
-  -- R.2.7.   SFix < UFix
-  function "<" (L: SFix; R: UFix) return boolean is
-  begin
-    return L < To_SFix(R);
-  end;
-
-  -- R.2.8.   UFix < SFix
-  function "<" (L: UFix; R: SFix) return boolean is
-  begin
-    return To_SFix(L) < R;
-  end;
-
-  -- R.2.9.   SFix < signed
-  function "<" (L: SFix; R: signed) return boolean is
-  begin
-    return L < To_SFix(R);
-  end;
-
-  -- R.2.10.  signed < SFix
-  function "<" (L: signed; R: SFix) return boolean is
-  begin
-    return To_SFix(L) < R;
-  end;
-
-  -- R.2.11.  SFix < integer
-  function "<" (L: SFix; R: integer) return boolean is
-    variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(S, R, clip_MS, clip_LS);
-    return L < S;
-  end;
-
-  -- R.2.12.  integer < SFix
-  function "<" (L: integer; R: SFix) return boolean is
-    variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
-  begin
-    Copy_V(S, L, clip_MS, clip_LS);
-    return S < R;
-  end;
-
-
-  ----------------------------------------
-  -- R.3.  Binary "/=" inequality operator
-  ----------------------------------------
-
-  -- R.3.1.   UFix /= UFix
-  function "/=" (L: UFix; R: UFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.2.   UFix /= unsigned
-  function "/=" (L: UFix; R: unsigned) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.3.   unsigned /= UFix
-  function "/=" (L: unsigned; R: UFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.4.   UFix /= integer
-  function "/=" (L: UFix; R: integer) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.5.   integer /= UFix
-  function "/=" (L: integer; R: UFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.6.   SFix /= SFix
-  function "/=" (L: SFix; R: SFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.7.   SFix /= UFix
-  function "/=" (L: SFix; R: UFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.8.   UFix /= SFix
-  function "/=" (L: UFix; R: SFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.9.   SFix /= signed
-  function "/=" (L: SFix; R: signed) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.10.  signed /= SFix
-  function "/=" (L: signed; R: SFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.11.  SFix /= integer
-  function "/=" (L: SFix; R: integer) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-  -- R.3.12.  integer /= SFix
-  function "/=" (L: integer; R: SFix) return boolean is
-  begin
-    return not (L = R);
-  end;
-
-
-  -----------------------------------------
-  -- R.4.  Binary ">" greater-than operator
-  -----------------------------------------
-
-  -- R.4.1.   UFix > UFix
-  function ">" (L: UFix; R: UFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.2.   UFix > unsigned
-  function ">" (L: UFix; R: unsigned) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.3.   unsigned > UFix
-  function ">" (L: unsigned; R: UFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.4.   UFix > integer
-  function ">" (L: UFix; R: integer) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.5.   integer > UFix
-  function ">" (L: integer; R: UFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.6.   SFix > SFix
-  function ">" (L: SFix; R: SFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.7.   SFix > UFix
-  function ">" (L: SFix; R: UFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.8.   UFix > SFix
-  function ">" (L: UFix; R: SFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.9.   SFix > signed
-  function ">" (L: SFix; R: signed) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.10.  signed > SFix
-  function ">" (L: signed; R: SFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.11.  SFix > integer
-  function ">" (L: SFix; R: integer) return boolean is
-  begin
-    return R < L;
-  end;
-
-  -- R.4.12.  integer > SFix
-  function ">" (L: integer; R: SFix) return boolean is
-  begin
-    return R < L;
-  end;
-
-
-  ----------------------------------------------
-  -- R.5.  Binary ">=" greater-or-equal operator
-  ----------------------------------------------
-
-  -- R.5.1.   UFix >= UFix
-  function ">=" (L: UFix; R: UFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.2.   UFix >= unsigned
-  function ">=" (L: UFix; R: unsigned) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.3.   unsigned >= UFix
-  function ">=" (L: unsigned; R: UFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.4.   UFix >= integer
-  function ">=" (L: UFix; R: integer) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.5.   integer >= UFix
-  function ">=" (L: integer; R: UFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.6.   SFix >= SFix
-  function ">=" (L: SFix; R: SFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.7.   SFix >= UFix
-  function ">=" (L: SFix; R: UFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.8.   UFix >= SFix
-  function ">=" (L: UFix; R: SFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.9.   SFix >= signed
-  function ">=" (L: SFix; R: signed) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.10.  signed >= SFix
-  function ">=" (L: signed; R: SFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.11.  SFix >= integer
-  function ">=" (L: SFix; R: integer) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-  -- R.5.12.  integer >= SFix
-  function ">=" (L: integer; R: SFix) return boolean is
-  begin
-    return not (L < R);
-  end;
-
-
-  -------------------------------------------
-  -- R.6.  Binary "<=" less-or-equal operator
-  -------------------------------------------
-
-  -- R.6.1.   UFix <= UFix
-  function "<=" (L: UFix; R: UFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.2.   UFix <= unsigned
-  function "<=" (L: UFix; R: unsigned) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.3.   unsigned <= UFix
-  function "<=" (L: unsigned; R: UFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.4.   UFix <= integer
-  function "<=" (L: UFix; R: integer) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.5.   integer <= UFix
-  function "<=" (L: integer; R: UFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.6.   SFix <= SFix
-  function "<=" (L: SFix; R: SFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.7.   SFix <= UFix
-  function "<=" (L: SFix; R: UFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.8.   UFix <= SFix
-  function "<=" (L: UFix; R: SFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.9.   SFix <= signed
-  function "<=" (L: SFix; R: signed) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.10.  signed <= SFix
-  function "<=" (L: signed; R: SFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.11.  SFix <= integer
-  function "<=" (L: SFix; R: integer) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  -- R.6.12.  integer <= SFix
-  function "<=" (L: integer; R: SFix) return boolean is
-  begin
-    return not (R < L);
-  end;
-
-  ------------------------------------------------------------------
-  -- C.  Concatenation operators between fixed-point operands, and
-  --     between fixed-point operands and other reasonable types.
-  --     Unlike the implicitly defined "&" operator, they preserve
-  --     place value and return an appropriately aligned subtype.
-  --     Preservation of place value means that some concatenation
-  --     operations are illegal.  In particular, operations
-  --     [SFix & SFix] and [UFix & SFix] are illegal, and
-  --     the place values of operands in [SFix & UFix] and
-  --     [UFix & UFix] must match up - the rightmost subscript of
-  --     the left operand must be one higher than the leftmost
-  --     subscript of the right operand.
-  --     Single bits of type std_ulogic may be concatenated with
-  --     fixed-point types where there is no risk of losing
-  --     sign-extension information.
-  --     Because of the way VHDL defines implicit concatenation,
-  --     it is impossible to detect all these errors at compile time.
-  --     Instead they are detected by assertion statements at run time.
-  --     Tool vendors may choose to implement compile-time checks
-  --     so that the run-time checking overhead can be avoided.
-  ------------------------------------------------------------------
-
-  -- C.1.1.   UFix := UFix & UFix
-  function "&" (L: UFix; R: UFix) return UFix is
-  begin
-    return UFix(concat(std_logic_vector(L), std_logic_vector(R)));
-  end;
-
-  -- C.1.2.   UFix := UFix & std_ulogic
-  function "&" (L: UFix; R: std_ulogic) return UFix is
-  begin
-    return UFix(concat(std_logic_vector(L), R));
-  end;
-
-  -- C.1.3.   UFix := std_ulogic & UFix
-  function "&" (L: std_ulogic; R: UFix) return UFix is
-  begin
-    return UFix(concat(L, std_logic_vector(R)));
-  end;
-
-
-  -- C.2.1.   SFix := SFix & UFix
-  function "&" (L: SFix; R: UFix) return SFix is
-  begin
-    return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
-  end;
-
-  -- C.2.2.   SFix := SFix & SFix -- ILLEGAL
-  function "&" (L: SFix; R: SFix) return SFix is
-  begin
-    report concat_signLS_msg
-      severity concat_severity;
-    return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
-  end;
-
-  -- C.2.3.   SFix := SFix & std_ulogic
-  function "&" (L: SFix; R: std_ulogic) return SFix is
-  begin
-    return SFix(concat(std_logic_vector(L), R));
-  end;
-
-  -- C.2.4.   SFix := std_ulogic & SFix
-  function "&" (L: std_ulogic; R: SFix) return SFix is
-  begin
-    assert std_match(L, R(R'LEFT))
-      report concat_sxt_msg
-      severity concat_severity;
-    return SFix(concat(L, std_logic_vector(R)));
-  end;
-
-
-end; -- package body fix_std;
diff --git a/lib/fixed/fixed_util_pkg.vhd b/lib/fixed/fixed_util_pkg.vhd
deleted file mode 100644
index 584f186..0000000
--- a/lib/fixed/fixed_util_pkg.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fixed_util_pkg is
-
-	-------------------------------------------------------------
-	-- Frequently used constants
-	constant pi			: real := 3.141592653589793e+000;
-	constant sqrt2		: real := 1.414213562373095e+000;
-	constant sqrt2_inv	: real := 7.071067811865475e-001;
-
-	-- Constructor helpers
-	-- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
-	function uproto (nbits : integer; nbits_frac : integer) return ufixed;
-
-	-- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
-	function sproto (nbits : integer; nbits_frac : integer) return sfixed;
-
-	-- Safe variant of uproto
-	function uhi (nbits : integer; nbits_frac : integer) return integer;
-	function ulo (nbits : integer; nbits_frac : integer) return integer;
-
-	-- Safe variant of sproto
-	function shi (nbits : integer; nbits_frac : integer) return integer;
-	function slo (nbits : integer; nbits_frac : integer) return integer;
-
-	function to_unsigned (src : ufixed) return UNSIGNED;
-	function to_signed (src : sfixed) return SIGNED;
-
-	type real_array_t is array (natural range <>) of real;
-	type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-	type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
-	function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t;
-	function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t;
-
-	-- Slicing functions for unconstrained array types
-	function to_ufixed(src : ufixed_array_t; index : integer) return ufixed;
-	function to_sfixed(src : sfixed_array_t; index : integer) return sfixed;
-	
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
-
-package body fixed_util_pkg is
-
-	-------------------------------------------------------------
-	-- Constuctor helpers
-	function uproto (nbits : integer; nbits_frac : integer) return ufixed is
-	constant result : ufixed (uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac)) := (others => '0');
-	begin 
-	return result(uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac));
-	end uproto;
-
-	-------------------------------------------------------------
-	function sproto (nbits : integer; nbits_frac : integer) return sfixed is
-	constant result : sfixed (shi(nbits,nbits_frac) downto slo(nbits,nbits_frac)) := (others => '0');
-	begin 
-	return result(shi(nbits,nbits_frac) downto slo(nbits,nbits_frac));
-	end sproto;
-
-	-------------------------------------------------------------
-	function uhi (nbits : integer; nbits_frac : integer) return integer is
-	begin 
-	return nbits-nbits_frac-1;
-	end uhi;
-
-	-------------------------------------------------------------
-	function ulo (nbits : integer; nbits_frac : integer) return integer is
-	begin 
-	return -nbits_frac;
-	end ulo;
-
-	-------------------------------------------------------------
-	function shi (nbits : integer; nbits_frac : integer) return integer is
-	begin 
-	return nbits-nbits_frac;
-	end shi;
-
-	-------------------------------------------------------------
-	function slo (nbits : integer; nbits_frac : integer) return integer is
-	begin 
-	return -nbits_frac+1;
-	end slo;
-
-	-------------------------------------------------------------
-	function to_unsigned (src : ufixed) return UNSIGNED is
-	subtype  t is UNSIGNED(src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	slv := t(src);
-	return UNSIGNED(to_X01(std_logic_vector(slv)));
-
-	end function to_unsigned;
-
-	-------------------------------------------------------------
-	function to_signed (src : sfixed) return SIGNED is
-	subtype  t is SIGNED(src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	slv := t(src);
-	return SIGNED(to_X01(std_logic_vector(slv)));
-
-	end function to_signed;
-	
-	function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
-	variable res : sfixed_array_t(0 to x'length-1, proto'range);
-	variable tt : sfixed(proto'range);
-	begin
-		for i in x'range loop
-			tt := to_sfixed(x(i), proto);
-			for j in proto'range loop
-				res(i,j) := tt(j);
-			end loop;	
-		end loop;
-		return res;
-	end to_sfixed_array;	
-
-	---------------------------------------------------------------------------
-	function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
-	variable p : sfixed(shi(nbits, nbits_int) downto slo(nbits, nbits_int));
-	begin
-		return to_sfixed_array(x, p);
-	end to_sfixed_array;	
-		
-	-------------------------------------------------------------------------------
-	-- ufixed <= ufixed_array(i)
-	function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is
-	variable dst : ufixed(src'range(2));
-	begin
-		for j in src'range(2) loop
-			dst(j) := src(index, j);
-		end loop;
-		
-		return dst;
-		
-	end to_ufixed;	
-	
-	-------------------------------------------------------------------------------
-	-- sfixed <= sfixed_array(i)
-	function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
-	variable dst : sfixed(src'range(2));
-	begin
-		for j in src'range(2) loop
-			dst(j) := src(index, j);
-		end loop;
-		
-		return dst;
-		
-	end to_sfixed;	
-
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd
deleted file mode 100644
index bcd2700..0000000
--- a/lib/fixed_ja/fixed_ja.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-package fixed_ja is
-
-
-	type ufixed_t is array (integer range <>) of STD_LOGIC;
-	type sfixed_t is array (integer range <>) of STD_LOGIC;
-	type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-	type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
-	type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent);
-	type saturate_mode_t is (none, saturate);
-	
-		-- Declare functions and procedure
-
-	constant ASSERT_NO_WARN : boolean := false;
-	constant default_round_mode : round_mode_t := none;
-	constant default_saturate_mode : saturate_mode_t := none;
-	
-	-- null array constants
-	constant NAUF : ufixed_t (0 downto 1)         := (others => '0');
-	constant NASF : sfixed_t (0 downto 1)         := (others => '0');
-	constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-
-	-- Constructor helpers
-	-- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range);
-	function uproto (nbits : integer; nbits_int : integer) return ufixed_t;
-
-	-- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range);
-	function sproto (nbits : integer; nbits_int : integer) return sfixed_t;
-
-	function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t;
-	function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t;
-
-	-- Conversion Functions
-	function to_ufixed(src : ufixed_t) return ufixed_t;
-	function to_sfixed(src : sfixed_t) return sfixed_t;
-	function to_ufixed(src : sfixed_t) return ufixed_t;
-	function to_sfixed(src : ufixed_t) return sfixed_t;
-
-	function to_ufixed
-	(
-		src : ufixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t;
-	
-	function to_ufixed
-	(
-		src : ufixed_t; 
-		proto : ufixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t;
-	
-	function to_sfixed
-	(
-		src : sfixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t;
-	
-	function to_sfixed
-	(
-		src : sfixed_t; 
-		proto : sfixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t;
-
-	-- fixed <= integer
-	function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t;
-	function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t;
-
-	-- fixed <= integer
-	function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t;
-	function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t;
-
-	-- ufixed <= unsigned
-	function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t;
-	function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t;
-	
-	-- sfixed <= signed
-	function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t;
-	function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t;
-
-	-- fixed <= slv
-	function to_ufixed (src : STD_LOGIC_VECTOR;	nbits : integer; nbits_int : integer) return ufixed_t;
-	function to_ufixed (src : STD_LOGIC_VECTOR;	proto : ufixed_t) return ufixed_t;
-	function to_sfixed (src : STD_LOGIC_VECTOR;	nbits : integer; nbits_int : integer) return sfixed_t;
-	function to_sfixed (src : STD_LOGIC_VECTOR;	proto : sfixed_t) return sfixed_t;
-	
-	-- ufixed <= real
-	function to_ufixed 
-	(
-		src : real;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t;
-	
-	function to_ufixed 
-	(	
-		src : real;
-		proto : ufixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t;
-	
-	-- sfixed <= real
-	function to_sfixed
-	(
-		src : real;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t;
-	
-	function to_sfixed 
-	(
-		src : real;
-		proto : sfixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t;
-
-	-- Slicing functions for unconstrained array types
-	function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t;
-	function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t;
-	
-	-- ufixed <= string
-	function to_ufixed (src : string) return ufixed_t;
-
-	-- sfixed <= string
-	function to_sfixed (src : string) return sfixed_t;
-
-	-- real <= ufixed
-	function to_real(src : ufixed_t) return real;
-
-	-- real <= sfixed
-	function to_real(src : sfixed_t) return real;
-	
-	-- slv <= ufixed
-	function to_slv(src : ufixed_t) return std_logic_vector;
-
-	-- slv <= sfixed
-	function to_slv(src : sfixed_t) return std_logic_vector;
-	
-	-- UNSIGNED <= ufixed
-	function to_unsigned (src : ufixed_t) return UNSIGNED;
-
-	-- SIGNED <= sfixed
-	function to_signed (src : sfixed_t) return SIGNED;
-
-	-- integer <= ufixed
-	function to_integer (src : ufixed_t) return integer;
-
-	-- integer <= sfixed
-	function to_integer (src : sfixed_t) return integer;
-
-	function to_string(src : ufixed_t) return string;
-	function to_string(src : sfixed_t) return string;
-	function to_string(src : std_logic_vector) return string;
-	
-	-------------------------------------------------------------
-	-- Arithmetic shift left
-	-------------------------------------------------------------
-	function "sla" (src : ufixed_t; count : integer) return ufixed_t;
-	function "sla" (src : sfixed_t; count : integer) return sfixed_t;
-
-	-------------------------------------------------------------
-	-- Arithmetic shift right
-	-------------------------------------------------------------
-	function "sra" (src : ufixed_t; count : integer) return ufixed_t;
-	function "sra" (src : sfixed_t; count : integer) return sfixed_t;
-	
-	-------------------------------------------------------------
-	-- Multiplication
-	-------------------------------------------------------------
-	function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t;
-	function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t;
-	function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t;
-	function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t;
-
-	-------------------------------------------------------------
-	-- Sum
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : integer) return ufixed_t;
-	function "+" (a : sfixed_t; b : integer) return sfixed_t;
-	function "+" (a : ufixed_t; b : unsigned) return ufixed_t;
-	function "+" (a : sfixed_t; b : signed) return sfixed_t;
-	function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t;
-	function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t;
-	function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t;
-	function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t;
-	function "+" (a : ufixed_t; b : std_logic) return ufixed_t;
-	function "+" (a : sfixed_t; b : std_logic) return sfixed_t;
-
-
-	-------------------------------------------------------------
-	-- Difference
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : integer) return ufixed_t;
-	function "-" (a : sfixed_t; b : integer) return sfixed_t;
-	function "-" (a : ufixed_t; b : unsigned) return ufixed_t;
-	function "-" (a : sfixed_t; b : signed) return sfixed_t;
-	function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t;
-	function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t;
-	function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t;
-	function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t;
-	function "-" (a : ufixed_t; b : std_logic) return ufixed_t;
-	function "-" (a : sfixed_t; b : std_logic) return sfixed_t;
-
-	-------------------------------------------------------------
-	-- Equality
-	-------------------------------------------------------------
-	function "=" (a : ufixed_t; b : ufixed_t) return boolean;
-	function "=" (a : sfixed_t; b : sfixed_t) return boolean;
-	function "=" (a : ufixed_t; b : sfixed_t) return boolean;
-	function "=" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Inequality
-	-------------------------------------------------------------
-	function "/=" (a : ufixed_t; b : ufixed_t) return boolean;
-	function "/=" (a : sfixed_t; b : sfixed_t) return boolean;
-	function "/=" (a : ufixed_t; b : sfixed_t) return boolean;
-	function "/=" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Less than
-	-------------------------------------------------------------
-	function "<" (a : ufixed_t; b : ufixed_t) return boolean;
-	function "<" (a : sfixed_t; b : sfixed_t) return boolean;
-	function "<" (a : ufixed_t; b : sfixed_t) return boolean;
-	function "<" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Greater than
-	-------------------------------------------------------------
-	function ">" (a : ufixed_t; b : ufixed_t) return boolean;
-	function ">" (a : sfixed_t; b : sfixed_t) return boolean;
-	function ">" (a : ufixed_t; b : sfixed_t) return boolean;
-	function ">" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Less or equal than
-	-------------------------------------------------------------
-	function "<=" (a : ufixed_t; b : ufixed_t) return boolean;
-	function "<=" (a : sfixed_t; b : sfixed_t) return boolean;
-	function "<=" (a : ufixed_t; b : sfixed_t) return boolean;
-	function "<=" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Greater or equal than
-	-------------------------------------------------------------
-	function ">=" (a : ufixed_t; b : ufixed_t) return boolean;
-	function ">=" (a : sfixed_t; b : sfixed_t) return boolean;
-	function ">=" (a : ufixed_t; b : sfixed_t) return boolean;
-	function ">=" (a : sfixed_t; b : ufixed_t) return boolean;
-	
-	-------------------------------------------------------------
-	-- Unary Arithmetic Operators
-	-------------------------------------------------------------
-	function "abs" (src : sfixed_t) return sfixed_t;
-	function "-" (src : ufixed_t) return sfixed_t;
-	function "-" (src : sfixed_t) return sfixed_t;
-
-	-------------------------------------------------------------
-	-- Misc. Operators
-	-------------------------------------------------------------
-	function ipart (src : ufixed_t) return ufixed_t;
-	function fpart (src : ufixed_t) return ufixed_t;
-	function ipart (src : sfixed_t) return sfixed_t;
-	function fpart (src : sfixed_t) return sfixed_t;
-
-	-------------------------------------------------------------
-	-- Print function
-	-------------------------------------------------------------
-	procedure print_info(src : in ufixed_t; prefix : in string);
-	procedure print_info(src : in sfixed_t; prefix : in string);
-	procedure print_info(src : in string; prefix : in string);
-	
-	-------------------------------------------------------------
-	-- Helpers
-	-------------------------------------------------------------
-	function cmsb(src : ufixed_t) return integer;
-	function clsb(src : ufixed_t) return integer;
-
-	function MIN (X, Y: INTEGER) return INTEGER;
-	function MAX (X, Y: INTEGER) return INTEGER;
-
-	function "MOD" (X, Y: in REAL ) return REAL;
-	function ipart(src : real) return real;
-	function fpart(src : real) return real;
-	
-	function and_red(arg  : ufixed_t) return STD_ULOGIC;
-	function nand_red(arg : ufixed_t) return STD_ULOGIC;
-	function or_red(arg   : ufixed_t) return STD_ULOGIC;
-	function nor_red(arg  : ufixed_t) return STD_ULOGIC;
-	function xor_red(arg  : ufixed_t) return STD_ULOGIC;
-	function xnor_red(arg : ufixed_t) return STD_ULOGIC;
-	function and_red(arg  : sfixed_t) return STD_ULOGIC;
-	function nand_red(arg : sfixed_t) return STD_ULOGIC;
-	function or_red(arg   : sfixed_t) return STD_ULOGIC;
-	function nor_red(arg  : sfixed_t) return STD_ULOGIC;
-	function xor_red(arg  : sfixed_t) return STD_ULOGIC;
-	function xnor_red(arg : sfixed_t) return STD_ULOGIC;
-
-	--------------------------------------------------------------
-
-end; -- package fixed_ja;
-
diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd
deleted file mode 100644
index a85b626..0000000
--- a/lib/fixed_ja/fixed_ja_body.vhd
+++ /dev/null
@@ -1,1921 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
-use std.textio.all;
-
-package body fixed_ja is
-
-	-------------------------------------------------------------
-	-- Local Procedures
-	-------------------------------------------------------------
-	-- adds 1 to the LSB of the number
-	procedure round_up
-	(
-		src       : in  ufixed_t;
-		result    : out ufixed_t;
-		overflowx : out BOOLEAN ) is
-		
-	variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0');
-	begin  -- round_up
-	srcuns (srcuns'high-1 downto 0) := to_unsigned (src);
-	resuns                          := srcuns + 1;
-
-	result := to_ufixed(resuns(src'high-src'low downto 0), src);
-	overflowx := (resuns(resuns'high) = '1');
-
-	end procedure round_up;
-
-	-------------------------------------------------------------
-	-- adds 1 to the LSB of the number
-	procedure round_up 
-	(
-		src       : in  sfixed_t;
-		result    : out sfixed_t;
-		overflowx : out BOOLEAN ) is
-	
-	variable srcs, ress : SIGNED (src'high-src'low+1 downto 0);
-	begin  -- round_up
-	srcs (srcs'high-1 downto 0) := to_signed (src);
-	srcs(srcs'high)             := src(src'high);  -- sign extend
-	ress                        := srcs + 1;
-
-	result := to_sfixed(ress (ress'high-1 downto 0), src);
-	overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0'));
-
-	end procedure round_up;
-	
-	-------------------------------------------------------------
-	-- Local functions
-	-------------------------------------------------------------
-	-- round_fixed()
---	function round_fixed
---	(
---		src : ufixed_t;
---		remainder : ufixed_t;
---		rnd_mode : round_mode_t := default_round_mode
---	) return ufixed_t is
---	variable res : ufixed_t(src'range);
---	begin
---	return res;
---
---	end round_fixed;
-		
-	-------------------------------------------------------------
---	function round_fixed 
---	(
---		src : sfixed_t;
---		remainder : sfixed_t;
---		rnd_mode : round_mode_t := default_round_mode
---	) return sfixed_t is
---	variable res : signed(src'length-1 downto 0);
---	begin
---	return src;
---
---	end round_fixed;
-
-	-------------------------------------------------------------
-	function reshape
-	(
-		src : ufixed_t;
-		proto : ufixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-
-	variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0');
-	variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0');
-	variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0');
-	variable ovf, isTruncLo, isTruncHi : boolean := false;
-	begin
-
-	if proto'high < -1 then
-		assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error;
-	end if;	
-
-	-- Check for high and low truncation
-	isTruncLo := (src'low < dst'low);
-	isTruncHi := (src'high > dst'high);
-	
-	-- Reshape
-	dst := (others => '0');
-	dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low));
-	tmp := dst;
-
-	-- Get low remainder
-	if isTruncLo then
-		RemainLow := src(RemainLow'range);
-	end if;
-	
-	-- Get high remainder
-	if isTruncHi then
-		RemainHigh := src(RemainHigh'range);
-	end if;	
-
-	ovf := false;
-
-	-- Rounding
-	if isTruncLo then
-
-		case rnd_mode is
-
-		-- Round to positive infinity (round ceiling)
-		when round_pos_infinity =>
-			if or_red(RemainLow) = '1' then
-				round_up(tmp, dst, ovf);
-			end if;
-
-		-- Round Half-up
-		-- Round nearest
-		when round_half_up | round_nearest => 
-			if (RemainLow(RemainLow'high) = '1') then
-				round_up(tmp, dst, ovf);
-			end if;
-
-		-- Round convergent
-		when round_convergent =>
-			if RemainLow(RemainLow'high) = '1' then
-				if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
-					round_up(tmp, dst, ovf);
-				elsif tmp(dst'low) = '1' then
-					round_up(tmp, dst, ovf);
-				end if;	
-			end if;
-			
-		-- Round to zero
-		when round_to_zero | none => null;
-		
-		when others =>
-		assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-
-		end case;
-	end if;	
-
-	-- Saturating
-	if sat_mode = saturate then
-
-		-- Check overflow
-		if isTruncHi then
-			ovf := ovf or or_red(RemainHigh) = '1';
-		end if;	
-
-		-- Saturate
-		if ovf then
-			dst := (others => '1');
-		end if;
-
-	end if;
-	
-	return dst;
-
-	end reshape;
-
-	-------------------------------------------------------------
-	function reshape
-	(
-		src : ufixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-	
-	begin
-	return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode);
-	
-	end reshape;
-
-	-------------------------------------------------------------
-	function reshape
-	(
-		src : sfixed_t;
-		proto : sfixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-
-	variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0');
-	variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0');
-	variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0');
-	variable ovf, isTruncLo, isTruncHi : boolean := false;
-	variable sign : std_logic; 
-	begin
-
-	if proto'high < 0 then
-		assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error;
-	end if;
-	
-	-- Check for high and low truncation
-	isTruncLo := (src'low < dst'low);
-	isTruncHi := (src'high > dst'high);
-	
-	-- Reshape
-	sign := src(src'high);
-	dst := (others => '0');
-	dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low));
-	tmp := dst;
-	
-	-- Get low remainder
-	if isTruncLo then
-		RemainLow := src(RemainLow'range);
-	end if;
-	
-	-- Get high remainder
-	if isTruncHi then
-		RemainHigh := src(RemainHigh'range);
-	end if;	
-
-	ovf := false;
-
-	-- Rounding
-	if isTruncLo then
-
-		case rnd_mode is
-
-		-- Round to positive infinity (round ceiling)
-		when round_pos_infinity =>
-			round_up(tmp, dst, ovf);
-			if ovf then
-				dst(dst'high) := '0';
-			end if;	
-
-		-- Round Half-up
-		when round_half_up => 
-			if RemainLow(RemainLow'high) = '1' then
-				round_up(tmp, dst, ovf);
-			end if;	
-
-		-- Round nearest
-		when round_nearest =>
-			if RemainLow(RemainLow'high) = '1' then
-				if RemainLow'length = 1 then
-					if sign = '0' then
-						round_up(tmp, dst, ovf);
-					end if;
-				elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then
-						round_up(tmp, dst, ovf);
-				end if;	
-			end if;	
-		
-		-- Round convergent
-		when round_convergent =>
-			if RemainLow(RemainLow'high) = '1' then
-				if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
-					round_up(tmp, dst, ovf);
-				elsif tmp(dst'low) = '1' then
-					round_up(tmp, dst, ovf);
-				end if;	
-			end if;
-
-		-- Round to zero
-		when round_to_zero =>
-			if (or_red(RemainLow) = '1' and sign = '1') then
-				round_up(tmp, dst, ovf);
-			end if;
-
-		-- No Round
-		when none =>
-			-- Same as RoundToZero but overflow detection is omitted
-			dst := tmp + (or_red(RemainLow) and sign);
-
-		when others =>
-		assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-		
-		end case;
-		
-		-- Check negative zero
-		if dst(dst'high) = '1' then
-			if or_red(dst(dst'high-1 downto dst'low)) = '0' then
-				dst(dst'high) := '0';
-			--	assert false report "Reshape(S): -0 detected" severity note;
-			end if;	
-		end if;	
-	end if;	
-
-	-- Saturating
-	if sat_mode = saturate then
-
-		-- Check overflow
-		if isTruncHi then
-			ovf :=	ovf or
-					(sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or
-					(sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or
-					(sign = '0' and or_red(RemainHigh) = '1');
-		end if;
-		
-		-- Saturate
-		if ovf then
-			if (sign = '1') then
-				dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1';
-			else
-				dst := '0' & (dst'high-1 downto dst'low => '1');
-			end if;
-		end if;
-		
-	end if;
-	
-	return dst;
-
-	end reshape;
-
-	-------------------------------------------------------------
-	function reshape
-	(
-		src : sfixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-	
-	begin
-	return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
-	
-	end reshape;
-
-	-------------------------------------------------------------
-	-- Constuctor helpers
-	-------------------------------------------------------------
-	function uproto (nbits : integer; nbits_int : integer) return ufixed_t is
-	constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0');
-	begin 
-	return result(nbits_int-1 downto nbits_int-nbits);
-	end uproto;
-
-	-------------------------------------------------------------
-	function sproto (nbits : integer; nbits_int : integer) return sfixed_t is
-	constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0');
-	begin 
-	return result(nbits_int downto nbits_int-nbits+1);
-	end sproto;
-
-	-------------------------------------------------------------
-	function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is
-	constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
-	variable hi, lo : integer := 0;
-
-	begin
-
-	case op is
-		when '+' =>
-		hi := max(a'high, b'high);
-		if a'high = b'high then
-			hi := hi + 1;
-		end if;	
-		lo := min(a'low, b'low);
-
-		when '-' =>  
-		hi := max(a'high, b'high);
-		lo := min(a'low, b'low);
-
-		when '*' => 
-		hi := a'high + b'high + 1;
-		if (a'high < 0 or b'high < 0) then
-			if (hi > -1) then
-				hi := hi-1;
-			end if;
-		end if;
-		lo := hi - a'length - b'length + 1;
-
-		when others => null;
-
-	end case;
-
-	return result(hi downto lo);
-	end uproto;
-
-	-------------------------------------------------------------
-	function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is
-	constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
-	variable hi, lo : integer := 0;
-
-	begin
-
-	case op is
-		when '+' =>
-		hi := max(a'high, b'high);
-		if a'high = b'high then
-			hi := hi + 1;
-		end if;	
-		lo := min(a'low, b'low);
-
-		when '-' =>  
-		hi := max(a'high, b'high);
-		lo := min(a'low, b'low);
-
-		when '*' =>  
-		hi := a'high + b'high;
-		if (a'high = 0 or b'high = 0) then
-			if (hi > 0) then
-				hi := hi-1;
-			end if;
-		end if;
-		lo := hi - a'length - b'length + 1;
-
-		when others => null;
-
-	end case;
-
-	return result(hi downto lo);
-	end sproto;
-
-	-------------------------------------------------------------
-	-- Type conversions
-	-------------------------------------------------------------
-    -- ufixed <= ufixed
-	function to_ufixed(src : ufixed_t) return ufixed_t is
-	begin
-	return to_ufixed(src, src);
-
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-    -- ufixed <= sfixed
-	function to_ufixed(src : sfixed_t) return ufixed_t is
-	variable dst : ufixed_t(src'range) := (others => '0');
-	begin
-	dst := ufixed_t(abs(src));
-	return dst(src'high-1 downto src'low);
-
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-    -- sfixed <= sfixed
-	function to_sfixed(src : sfixed_t) return sfixed_t is
-	begin
-	return src;
-
-	end to_sfixed;
-	
-	-------------------------------------------------------------
-    -- sfixed <= ufixed
-	function to_sfixed(src : ufixed_t) return sfixed_t is
-	variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0');
-	begin
-	dst(src'range) := sfixed_t(src);
-	return dst;
-
-	end to_sfixed;
-
-	-------------------------------------------------------------
-    -- ufixed <= ufixed
-	function to_ufixed
-	(
-		src : ufixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-	begin
-	return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-	
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-    -- ufixed <= ufixed
-	function to_ufixed
-	(
-		src : ufixed_t; 
-		proto : ufixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-	begin
-	return reshape(src, proto, rnd_mode, sat_mode);
-	
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-    -- sfixed <= sfixed
-	function to_sfixed
-	(
-		src : sfixed_t;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-	begin
-	return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-	
-	end to_sfixed;
-	
-	-------------------------------------------------------------
-    -- sfixed <= sfixed
-	function to_sfixed
-	(
-		src : sfixed_t; 
-		proto : sfixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-	begin
-	return reshape(src, proto, rnd_mode, sat_mode);
-	
-	end to_sfixed;
-
-	-------------------------------------------------------------
-	-- ufixed <= integer
-	function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is
-	begin
-	return to_ufixed(src, uproto(nbits, nbits_int));
-		
-	end to_ufixed;
-
-	function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is
-	begin
-	return to_ufixed(to_unsigned(src, proto'length), proto);
-		
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-	-- ufixed <= unsigned
-	function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is
-	begin
-	return to_ufixed(src, uproto(nbits, nbits_int));
-
-	end to_ufixed;
-	
-	-------------------------------------------------------------
-	-- ufixed <= unsigned
-	function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is
-	variable dst : ufixed_t(proto'high downto proto'low) := (others => '0');
-	begin
-	
-	dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0));	
-
-	return dst;
-
-	end to_ufixed;
-
-	-------------------------------------------------------------
-	-- sfixed <= integer
-	function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is
-	begin
-	return to_sfixed(src, sproto(nbits, nbits_int));
-		
-	end to_sfixed;
-
-	function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is
-	begin
-	
-	return to_sfixed(to_signed(src, proto'length), proto);
-		
-	end to_sfixed;
-	
-	-------------------------------------------------------------
-	-- sfixed <= signed
-	function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is
-	begin
-	return to_sfixed(src, sproto(nbits, nbits_int));
-	
-	end to_sfixed;
-
-	-------------------------------------------------------------
-	-- sfixed <= signed
-	function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is
-	variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
-	begin
-
-	dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0));	
-	dst(dst'high) := src(src'high);
-
-	return dst;
-	
-	end to_sfixed;
-
-	-------------------------------------------------------------
-	function to_ufixed (src : STD_LOGIC_VECTOR;	proto : ufixed_t) return ufixed_t is
-	variable result : ufixed_t (proto'left downto proto'right);
-	begin
-	if (result'length < 1) then
-		return result;
-	else
-		result := to_ufixed (unsigned(src), proto);
-	return result;
-	end if;
-	
-	end function to_ufixed;
-
-	-------------------------------------------------------------
-	function to_ufixed (src : STD_LOGIC_VECTOR;	nbits : integer; nbits_int : integer) return ufixed_t is
-	begin
-	return to_ufixed(src, uproto(nbits, nbits_int));
-	
-	end function to_ufixed;
-
-	-------------------------------------------------------------
-	function to_sfixed (src : STD_LOGIC_VECTOR;	proto : sfixed_t) return sfixed_t is
-	variable result : sfixed_t (proto'left downto proto'right);
-	begin
-	if (result'length < 1) then
-		return result;
-	else
-		result := to_sfixed (signed(src), proto);
-	return result;
-	end if;
-	
-	end function to_sfixed;
-
-	-------------------------------------------------------------
-	function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is
-	begin
-	return to_sfixed(src, sproto(nbits, nbits_int));
-	
-	end to_sfixed;
-	-------------------------------------------------------------
-	
-	-- ufixed <= real
-	function to_ufixed
-	(
-		src : real; 
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-
-	constant nbits_ext : integer := nbits + 1;
-	constant fix_hi : integer := nbits_int - 1;
-	constant fix_lo : integer := nbits_int - nbits_ext;
-	
-	variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0');
-	variable i : integer := 0;
-	variable remain : real := 0.0;
-	
-	begin
-	
-	if (nbits_int < 0) then
-		assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error;
-	end if;
-	
-	if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then
---		assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") "  severity warning;
---		print_info(dst, "dst: ");
-	end if;
-	
-	remain := abs(src);
-    for i in dst'range loop
-		if remain >= 2.0**i then
-			dst(i) := '1';
-			remain := remain - 2.0**i;
-		else
-			dst(i) := '0';
-		end if;
-    end loop;
-	
-	return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode);
-
-	end to_ufixed;
-
-	-------------------------------------------------------------
-	-- sfixed <= real
-	function to_sfixed
-	(
-		src : real;
-		proto : sfixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-
-	variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0');
-	variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
-	
-	begin
-	utmp := to_ufixed(src, utmp, rnd_mode, sat_mode);
-	if (src < 0.0) then
-		dst := -to_sfixed(utmp);
-	else
-		dst := to_sfixed(utmp);
-	end if;
-	
-	return dst;
-	end to_sfixed;  
-
-	-------------------------------------------------------------
-	-- ufixed <= real
-	function to_ufixed
-	(
-		src : real;
-		proto : ufixed_t;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return ufixed_t is
-	begin
-		return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode);
-	end to_ufixed;
-
-	-------------------------------------------------------------
-	-- sfixed <= real
-	function to_sfixed
-	(
-		src : real;
-		nbits : integer;
-		nbits_int : integer;
-		rnd_mode : round_mode_t := default_round_mode;
-		sat_mode : saturate_mode_t := default_saturate_mode
-	) return sfixed_t is
-	begin
-		return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
-	end to_sfixed;
-
-	-------------------------------------------------------------------------------
-	-- ufixed <= ufixed_array(i)
-	function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is
-	variable dst : ufixed_t(src'range(2));
-	begin
-		for j in src'range(2) loop
-			dst(j) := src(index, j);
-		end loop;
-		
-		return dst;
-		
-	end to_ufixed;	
-	
-	-------------------------------------------------------------------------------
-	-- sfixed <= sfixed_array(i)
-	function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is
-	variable dst : sfixed_t(src'range(2));
-	begin
-		for j in src'range(2) loop
-			dst(j) := src(index, j);
-		end loop;
-		
-		return dst;
-		
-	end to_sfixed;	
-	
-	-------------------------------------------------------------
-	-- ufixed <= string
-	function to_ufixed (src : string) return ufixed_t is
-	
-	variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
-	variable dst : unsigned(src'length downto 0) := (others => '0');
-	variable dp_found : boolean := false;
-	begin
-	
-	for i in src'reverse_range loop
-		case src(i) is 
-			when '.' =>
-			if dp_found then
-				assert false report "More than one DP not found." severity error;
-			else
-				dp_found := true;
-				nbits_frac := j;
-			end if;  
-		
-			when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
-			when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
-			when others => 
-			assert false report "Illegal character in binary string." severity error;
-			
-		end case;
-	
-	end loop ;
-	if not dp_found then
-		assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
-	end if;	
-	
-	nbits_int := nbits - nbits_frac;
-	
-	return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int);
-	
-	end to_ufixed;
-
-	-------------------------------------------------------------
-	-- sfixed <= string
-	function to_sfixed (src : string) return sfixed_t is
-	
-	variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
-	variable dst : signed(src'length downto 0) := (others => '0');
-	variable dp_found : boolean := false;
-	variable is_neg : boolean := false;
-	begin
-
-	is_neg := src(src'left) = '-';
-	
-	for i in src'reverse_range loop
-		case src(i) is 
-			when '-' => null;
-			when '+' => null;
-	
-			when '.' =>
-			if dp_found then
-				assert false report "More than one DP not found." severity error;
-			else
-				dp_found := true;
-				nbits_frac := j;
-			end if;  
-	
-			when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
-			when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
-			when others => 
-			assert false report "Illegal character in binary string." severity error;
-		end case;
-	end loop ;
-	nbits := nbits + 1;
-
-	if not dp_found then
-		assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
-	end if;	
-	
-	nbits_int := nbits - nbits_frac-1;
-
-	if is_neg then
-		dst(nbits-1 downto 0) := -dst(nbits-1 downto 0);
-	end if;
-
-	return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int);
-
-	end to_sfixed;
-
-	-------------------------------------------------------------
-	function to_unsigned (src : ufixed_t) return UNSIGNED is
-	subtype  t is UNSIGNED(src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	slv := t(src);
-	return UNSIGNED(to_X01(std_logic_vector(slv)));
-
-	end function to_unsigned;
-
-	-------------------------------------------------------------
-	function to_signed (src : sfixed_t) return SIGNED is
-	subtype  t is SIGNED(src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	slv := t(src);
-	return SIGNED(to_X01(std_logic_vector(slv)));
-
-	end function to_signed;
-	
-	-------------------------------------------------------------
-	-- integer <= ufixed
-	function to_integer (src : ufixed_t) return integer is
-	begin
-		return to_integer(to_unsigned(src));
-	end to_integer;	
-
-	-------------------------------------------------------------
-	-- integer <= sfixed
-	function to_integer (src : sfixed_t) return integer is
-	begin
-		return to_integer(to_signed(src));
-	end to_integer;	
-
-	-------------------------------------------------------------
-	--  to_real
-	function to_real(src : ufixed_t) return real is
-	variable dst : real := 0.0;
-	begin
-	for i in src'range loop
-		if (src(i) = '1') then
-			dst := dst + real(2.0**i);
-		end if;	
-	end loop;
-	return dst;
-
-	end to_real;		
-
-	-------------------------------------------------------------
-	function to_real(src : sfixed_t) return real is
-	variable dst : real := 0.0;
-	begin
-	dst := to_real(to_ufixed(src));
-
-	if (src(src'high) = '1') then
-		dst := -dst;
-	end if;
-
-	return dst;
-
-	end to_real;		
-
-	-------------------------------------------------------------
-	--  to_slv
-	function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is
-	subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	if src'length < 1 then
-		return NSLV;
-	end if;
-	slv := t (src);
-	return slv;
-
-	end function to_slv;
-
-	-------------------------------------------------------------
-	--  to_slv
-	function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is
-	subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
-	variable slv : t;
-	begin
-	if src'length < 1 then
-		return NSLV;
-	end if;
-	slv := t (src);
-	return slv;
-
-	end function to_slv;
-
-	-------------------------------------------------------------
-	function to_string(src : ufixed_t) return string is
-	variable str : string(src'length+1 downto 1) := (others => '0');
-	variable i, j : integer := 0;
-
-	begin
-	j := src'length+1;
-	for i in src'high downto 0 loop
-		if (src(i) = '1') then
-			str(j) := '1';
-		end if;
-		j := j - 1;
-	end loop;
-
-	str(j) := '.';
-	j := j - 1;
-
-	for i in -1 downto src'low loop
-		if (src(i) = '1') then
-			str(j) := '1';
-		end if;
-		j := j - 1;
-	end loop;
-
-	return str;
-
-	end to_string;
-
-	-------------------------------------------------------------
-	function to_string(src : sfixed_t) return string is
-	variable str : string(src'length+1 downto 1) := (others => '0');
-	variable i, j, start : integer := 0;
-	variable strlen : integer := 0;
-	variable src_abs : sfixed_t(src'range) := (others => '0');
-
-	begin
-	if (src'high < 0) then
-		assert false report "Illegal signed fix point number" severity error;
-	end if;
-	
-	start := src'high;
-	strlen := src'length;
-
-	j := src'length+1;
-	if (src(start) = '1') then
-		str(j) := '-';
-		j := j - 1;
-		start := start - 1;
-		strlen := strlen + 1;
-	end if;
-
-	src_abs := abs(src);
-
-	for i in start downto 0 loop
-		if (src_abs(i) = '1') then
-			str(j) := '1';
-		end if;
-		j := j - 1;
-	end loop;
-
-	str(j) := '.';
-	j := j - 1;
-
-	for i in -1 downto src'low loop
-		if (src_abs(i) = '1') then
-			str(j) := '1';
-		end if;
-		j := j - 1;
-	end loop;
-
-	return str(strlen downto 1);
-
-	end to_string;
-
-	-------------------------------------------------------------
-	function to_string(src : std_logic_vector) return string is
-	variable str : string(src'length downto 1) := (others => '0');
-	variable i : integer := 0;
-
-	begin
-	for i in src'range loop
-		if (src(i) = '1') then
-			str(i+1) := '1';
-		end if;
-	end loop;
-
-	return str;
-
-	end to_string;
-
-	-------------------------------------------------------------
-	-- Binary Operators
-	-------------------------------------------------------------
-	function "sla" (src : ufixed_t; count : integer) return ufixed_t is
-	variable result : ufixed_t (src'high downto src'low) := (others => '0');
-	
-	begin 
-	if (count = 0) then
-		result := src;
-	elsif (count < 0) then
-		result := src sra -count;
-	elsif (count < src'length) then
-		result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0');
-	end if;	
-	return result;
-	
-	end "sla";
-
-	-------------------------------------------------------------
-	function "sla" (src : sfixed_t; count : integer) return sfixed_t is
-	variable result : sfixed_t (src'high downto src'low) := (others => '0');
-	variable sign : std_logic := '0';
-	
-	begin 
-	sign := src(src'high);
-	if (count = 0) then
-		result := src;
-	elsif (count < 0) then
-		result := src sra -count;
-	elsif (count < src'length-1) then
-		result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0');
-	end if;	
-	return result;
-	
-	end "sla";
-
-	-------------------------------------------------------------
-	function "sra" (src : ufixed_t; count : integer) return ufixed_t is
-	variable result : ufixed_t (src'high downto src'low) := (others => '0');
-
-	begin 
-	if (count = 0) then
-		result := src;
-	elsif (count < 0) then
-		result := src sla -count;
-	elsif (count < src'length) then
-		result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count);
-	end if;	
-	return result;
-
-	end "sra";
-	
-	-------------------------------------------------------------
-	function "sra" (src : sfixed_t; count : integer) return sfixed_t is
-	variable result : sfixed_t (src'high downto src'low) := (others => '0');
-	variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0');
-	variable sign, do_sub : std_logic := '0';
-	
-	begin 
-	src_slv := to_signed(src);
-	sign := src(src'high);
-	do_sub := src(src'high) and src(src'low);
-	if (count = 0) then
-		result := src;
-	elsif (count < 0) then
-		result := src sla -count;
-	elsif (count < src'length-1) then
-		res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count);
-		if (do_sub = '1') then
-			result(src'high downto src'low) := to_sfixed(res_slv+1, result);
-		else
-			result(src'high downto src'low) := to_sfixed(res_slv, result);
-		end if;	
-	end if;	
-	return result;
-
-	end "sra";
-	
-	-------------------------------------------------------------
-	function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is
-	variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low);
-
-	begin 
-	if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0)  then
-		result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1;
-	else	
-		result := to_ufixed(to_unsigned(a) * to_unsigned(b), result);
-	end if;	
-	return result;
-
-	end "*";
-
-	-------------------------------------------------------------
-	function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is
-	variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low);
-
-	begin 
-	if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0)  then
-		result := to_sfixed(signed(a) * signed(b), result) sla 2;
-	else
-		result := to_sfixed(signed(a) * signed(b), result) sla 1;
- 	end if;
-	return result;
-
-	end "*";
-
-	-------------------------------------------------------------
-	function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
-	begin 
-	return to_sfixed(a) * b;
-
-	end "*";
-
-	-------------------------------------------------------------
-	function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
-	begin 
-	return b * a;
-
-	end "*";
-
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is
-	variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low);
-
-	begin 
-	result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result)));
-	return result;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is
-	variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low);
-
-	begin 
-	result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result);
---	result := to_sfixed(signed(a) + signed(b), result);
-	return result;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
-	begin 
-	return to_sfixed(a) + b;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
-	begin 
-	return b + a;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : unsigned) return ufixed_t is
-
-	begin 
-	
-	return ufixed_t(unsigned(a) + b);
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : sfixed_t; b : signed) return sfixed_t is
-
-	begin 
-
-	return sfixed_t(signed(a) + b);
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : integer) return ufixed_t is
-
-	begin 
-	
-	return ufixed_t(unsigned(a) + to_unsigned(b, a'length));
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : sfixed_t; b : integer) return sfixed_t is
-
-	begin 
-
-	return sfixed_t(signed(a) + to_signed(b, a'length));
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : ufixed_t; b : std_logic) return ufixed_t is
-	variable result : ufixed_t (a'high downto a'low);
-	variable buns : unsigned(a'length-1 downto 0);
-
-	begin 
-	buns := (a'length-1 downto 1 => '0') & b;
-	result := ufixed_t(to_unsigned(a) + buns);
-	return result;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "+" (a : sfixed_t; b : std_logic) return sfixed_t is
-	variable result : sfixed_t (a'high downto a'low);
-	variable bs : signed(a'length-1 downto 0);
-
-	begin 
-	bs := (a'length-1 downto 1 => '0') & b;
-	result := sfixed_t(to_signed(a) + bs);
-	return result;
-
-	end "+";
-
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is
-	variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low);
-	begin 
-	result := to_ufixed(to_sfixed(a) - to_sfixed(b));
-	return result;
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is
-	variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low);
-
-	begin 
-	result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result);
-	return result;
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-	begin 
-	return to_sfixed(a) - b;
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
-	begin 
-	return a - to_sfixed(b);
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : unsigned) return ufixed_t is
-
-	begin 
-	return ufixed_t(unsigned(a) - b);
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : sfixed_t; b : signed) return sfixed_t is
-
-	begin 
-	return sfixed_t(signed(a) - b);
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : integer) return ufixed_t is
-
-	begin 
-	
-	return ufixed_t(unsigned(a) - to_unsigned(b, a'length));
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : sfixed_t; b : integer) return sfixed_t is
-
-	begin 
-
-	return sfixed_t(signed(a) - to_signed(b, a'length));
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : ufixed_t; b : std_logic) return ufixed_t is
-	variable result : ufixed_t (a'high downto a'low);
-	variable buns : unsigned(a'length-1 downto 0);
-
-	begin 
-	buns := (a'length-1 downto 1 => '0') & b;
-	result := ufixed_t(unsigned(a) - buns);
-	return result;
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (a : sfixed_t; b : std_logic) return sfixed_t is
-	variable result : sfixed_t (a'high downto a'low);
-	variable bs : signed(a'length-1 downto 0);
-
-	begin 
-	bs := (a'length-1 downto 1 => '0') & b;
-	result := sfixed_t(signed(a) - bs);
-	return result;
-
-	end "-";
-
-	-------------------------------------------------------------
-	-- Unary Operators
-	-------------------------------------------------------------
-	function "abs" (src : sfixed_t) return sfixed_t is
-	begin
-	return to_sfixed(abs(signed(src)), src);
-
-	end "abs";
-
-	-------------------------------------------------------------
-	function "-" (src : ufixed_t) return sfixed_t is
-	begin
-	return -to_sfixed(src);
-
-	end "-";
-
-	-------------------------------------------------------------
-	function "-" (src : sfixed_t) return sfixed_t is
-	begin
-	return to_sfixed(-signed(src), src);
-
-	end "-";
-
-	-------------------------------------------------------------
-	-- Binary Equality
-	-------------------------------------------------------------
-	function "=" (a : ufixed_t; b : ufixed_t) return boolean is
-	variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_ufixed(a, ta);
-	tb := to_ufixed(b, tb);
-	return to_unsigned(ta) = to_unsigned(tb);
-
-	end "=";
-	
-	-------------------------------------------------------------
-	function "=" (a : sfixed_t; b : sfixed_t) return boolean is
-	variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_sfixed(a, ta);
-	tb := to_sfixed(b, tb);
-	return to_signed(ta) = to_signed(tb);
-
-	end "=";
-	
-	-------------------------------------------------------------
-	function "=" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return to_sfixed(a) = b;
-	end "=";
-	
-	-------------------------------------------------------------
-	function "=" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return b = a;
-	end "=";
-	
-	-------------------------------------------------------------
-	-- Binary Inequality
-	-------------------------------------------------------------
-	function "/=" (a : ufixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a = b);
-
-	end "/=";
-	
-	-------------------------------------------------------------
-	function "/=" (a : sfixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a = b);
-
-	end "/=";
-	
-	-------------------------------------------------------------
-	function "/=" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a = b);
-	end "/=";
-	
-	-------------------------------------------------------------
-	function "/=" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a = b);
-	end "/=";
-	
-	-------------------------------------------------------------
-	-- Binary less than
-	-------------------------------------------------------------
-	function "<" (a : ufixed_t; b : ufixed_t) return boolean is
-	variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_ufixed(a, ta);
-	tb := to_ufixed(b, tb);
-	return to_unsigned(ta) < to_unsigned(tb);
-	
-	end "<";
-	
-	-------------------------------------------------------------
-	function "<" (a : sfixed_t; b : sfixed_t) return boolean is
-	variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_sfixed(a, ta);
-	tb := to_sfixed(b, tb);
-	return to_signed(ta) < to_signed(tb);
-	
-	end "<";
-
-	-------------------------------------------------------------
-	function "<" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return to_sfixed(a) < b;
-	
-	end "<";
-
-	-------------------------------------------------------------
-	function "<" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return a < to_sfixed(b);
-	
-	end "<";
-	
-	-------------------------------------------------------------
-	-- Binary greater than
-	-------------------------------------------------------------
-	function ">" (a : ufixed_t; b : ufixed_t) return boolean is
-	variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_ufixed(a, ta);
-	tb := to_ufixed(b, tb);
-	return to_unsigned(ta) > to_unsigned(tb);
-	
-	end ">";
-
-	-------------------------------------------------------------
-	function ">" (a : sfixed_t; b : sfixed_t) return boolean is
-	variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
-	begin
-	ta := (others => '0');
-	tb := (others => '0');
-	ta := to_sfixed(a, ta);
-	tb := to_sfixed(b, tb);
-	return to_signed(ta) > to_signed(tb);
-	
-	end ">";
-
-	-------------------------------------------------------------
-	function ">" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return to_sfixed(a) > b;
-	end ">";
-	
-	-------------------------------------------------------------
-	function ">" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return a > to_sfixed(b);
-	end ">";
-	
-	-------------------------------------------------------------
-	-- Binary less equal than
-	-------------------------------------------------------------
-	function "<=" (a : ufixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a > b);
-	end "<=";
-	
-	function "<=" (a : sfixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a > b);
-	end "<=";
-
-	function "<=" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a > b);
-	end "<=";
-
-	function "<=" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a > b);
-	end "<=";
-	
-	-------------------------------------------------------------
-	-- Binary greater or equal than
-	-------------------------------------------------------------
-	function ">=" (a : ufixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a < b);
-	end ">=";
-
-	function ">=" (a : sfixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a < b);
-	end ">=";
-
-	function ">=" (a : ufixed_t; b : sfixed_t) return boolean is
-	begin
-	return not (a < b);
-	end ">=";
-
-	function ">=" (a : sfixed_t; b : ufixed_t) return boolean is
-	begin
-	return not (a < b);
-	end ">=";
-
-	-------------------------------------------------------------
-	-- Misc. Operators
-	-------------------------------------------------------------
-	function ipart (src : ufixed_t) return ufixed_t is
-	begin
-		return src(src'high downto 0);
-	end ipart;
-	
-	function fpart (src : ufixed_t) return ufixed_t is
-	begin
-		return src(-1 downto src'low);
-	end fpart;
-	
-	function ipart (src : sfixed_t) return sfixed_t is
-	begin
-		return src(src'high-1 downto 0);
-	end ipart;
-	
-	function fpart (src : sfixed_t) return sfixed_t is
-	begin
-		return src(-1 downto src'low);
-	end fpart;
-
-	-------------------------------------------------------------
-	-- Print functions
-	-------------------------------------------------------------
-	procedure print_info(src : in ufixed_t; prefix : in string) is
-	variable L : line;
-
-	begin
-	write (L, prefix & "'length     = ");write (L, src'length);
-	writeline (output, L);
-
-	write (L, prefix & "'high(left) = ");
-	write (L, src'high);
-	write (L, '(');
-	write (L, src'left);
-	write (L, ')');
-	writeline (output, L);
-
-	write (L, prefix & "'low(right) = ");
-	write (L, src'low);
-	write (L, '(');
-	write (L, src'right);
-	write (L, ')');
-	writeline (output, L);
-
-	write (L, prefix & "'value      = B");write (L, to_string(src));
-	writeline (output, L);
-
-	write (L, prefix & "'value      = ");write (L, to_real(src));
-	writeline (output, L);
-
-	--      write (L, prefix & "'cmsb       = ");write (L, cmsb(src));
-	--      writeline (output, L);
-
-	--      write (L, prefix & "'clsb       = ");write (L, clsb(src));
-	--      writeline (output, L);
-
-	writeline (output, L);
-
-	end print_info;
-
-	-------------------------------------------------------------
-	procedure print_info(src : in sfixed_t; prefix : in string) is
-	variable L : line;
-
-	begin
-	write (L, prefix & "'length     = ");write (L, src'length);
-	writeline (output, L);
-
-	write (L, prefix & "'high(left) = ");
-	write (L, src'high);
-	write (L, '(');
-	write (L, src'left);
-	write (L, ')');
-	writeline (output, L);
-
-	write (L, prefix & "'low(right) = ");
-	write (L, src'low);
-	write (L, '(');
-	write (L, src'right);
-	write (L, ')');
-	writeline (output, L);
-
-	write (L, prefix & "'value      = B");write (L, to_string(src));
-	writeline (output, L);
-
-	write (L, prefix & "'value      = ");write (L, to_real(src));
-	writeline (output, L);
-
-	--      write (L, prefix & "'cmsb       = ");write (L, cmsb(src));
-	--      writeline (output, L);
-
-	--      write (L, prefix & "'clsb       = ");write (L, clsb(src));
-	--      writeline (output, L);
-
-	writeline (output, L);
-
-	end print_info;
-
-	-------------------------------------------------------------
-	procedure print_info(src : in string; prefix : in string) is
-	variable L : line;
-
-	begin
-	write (L, prefix & "'length     = ");write (L, src'length);
-	writeline (output, L);
-
-	write (L, prefix & "'high(left) = ");
-	write (L, src'high);
-	write (L, '(');
-	write (L, src'left);
-	write (L, ')');
-	writeline (output, L);
-
-	write (L, prefix & "'low(right) = ");
-	write (L, src'low);
-	write (L, '(');
-	write (L, src'right);
-	write (L, ')');
-	writeline (output, L);
-
-	writeline (output, L);
-
-	end print_info;
-
-	-------------------------------------------------------------
-	-- Helpers
-	-------------------------------------------------------------
-	-- Count significant bits for integer part    
-	function cmsb(src : ufixed_t) return integer is
-	variable j, i : integer := src'high;
-	begin
-	for i in src'range loop
-		if src(i) = '1' then
-			exit;
-		end if;
-		j := j - 1;
-	end loop;
-
-	-- LRM nachlesen: hier is i=src'high re-initialisert
-
-	return j;
-
-	end cmsb;
-
-	-------------------------------------------------------------
-	-- Count significant bits for fractional part    
-	function clsb(src : ufixed_t) return integer is
-	variable j, i : integer := src'low;
-	begin
-	for i in src'reverse_range loop
-		if src(i) = '1' then
-			exit;
-		end if;
-		j := j + 1;
-	end loop;
-
-	-- LRM nachlesen: hier is i=src'low re-initialisert
-
-	return j;
-
-	end clsb;
-
-	-------------------------------------------------------------
-	function MIN (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y < X then
-		res := Y;
-	end if;
-
-	return res;
-
-	end MIN;
-
-	-------------------------------------------------------------
-	function MAX (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y > X then
-		res := Y;
-	end if;
-
-	return res;
-	
-	end MAX;
-
-	-------------------------------------------------------------
-	function "MOD" (X, Y: in REAL ) return REAL is
-	-- Description:
-	--        See function declaration in IEEE Std 1076.2-1996
-	-- Notes:
-	--        a) Returns 0.0 on error
-
-	variable XNEGATIVE : BOOLEAN := X < 0.0;
-	variable YNEGATIVE : BOOLEAN := Y < 0.0;
-	variable VALUE : REAL;
-	begin
-	-- Check validity of input arguments
-	if (Y = 0.0) then
-		 assert FALSE
-				report "MOD(X, 0.0) is undefined"
-				severity ERROR;
-		 return 0.0;
-	end if;
-
-	-- Compute value
-	if ( XNEGATIVE ) then
-			if ( YNEGATIVE ) then
-					VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
-			else
-					VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
-			end if;
-	else
-			if ( YNEGATIVE ) then
-					VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
-			else
-					VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
-			end if;
-	end if;
-
-	return VALUE;
-
-	end "MOD";
-
-	-------------------------------------------------------------
-	-- misc. conversion
-	function ipart(src : real) return real is
-	begin
-	return floor(src);
-
-	end ipart;
-
-	-------------------------------------------------------------
-	function fpart(src : real) return real is
-	begin
-	return src - floor(src);
-
-	end fpart;
-
-	-------------------------------------------------------------
-	function or_red (arg : STD_LOGIC_VECTOR)
-	return STD_LOGIC is
-	variable Upper, Lower : STD_LOGIC;
-	variable Half         : INTEGER;
-	variable BUS_int      : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
-	variable Result       : STD_LOGIC;
-	begin
-	if (arg'length < 1) then            -- In the case of a NULL range
-		Result := '0';
-	else
-		BUS_int := to_ux01 (arg);
-		if (BUS_int'length = 1) then
-			Result := BUS_int (BUS_int'left);
-		elsif (BUS_int'length = 2) then
-			Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
-		else
-			Half   := (BUS_int'length + 1) / 2 + BUS_int'right;
-			Upper  := or_red (BUS_int (BUS_int'left downto Half));
-			Lower  := or_red (BUS_int (Half - 1 downto BUS_int'right));
-			Result := Upper or Lower;
-		end if;
-	end if;
-	return Result;
-
-	end function or_red;
-
-	-------------------------------------------------------------
-	function and_red (arg : STD_LOGIC_VECTOR)
-	return STD_LOGIC is
-	variable Upper, Lower : STD_LOGIC;
-	variable Half         : INTEGER;
-	variable BUS_int      : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
-	variable Result       : STD_LOGIC;
-	begin
-	if (arg'length < 1) then            -- In the case of a NULL range
-		Result := '1';
-	else
-		BUS_int := to_ux01 (arg);
-		if (BUS_int'length = 1) then
-			Result := BUS_int (BUS_int'left);
-		elsif (BUS_int'length = 2) then
-			Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
-		else
-			Half   := (BUS_int'length + 1) / 2 + BUS_int'right;
-			Upper  := and_red (BUS_int (BUS_int'left downto Half));
-			Lower  := and_red (BUS_int (Half - 1 downto BUS_int'right));
-			Result := Upper and Lower;
-		end if;
-	end if;
-	return Result;
-
-	end function and_red;
-
-	-------------------------------------------------------------
-	function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
-	variable Upper, Lower : STD_ULOGIC;
-	variable Half         : INTEGER;
-	variable BUS_int      : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
-	variable Result       : STD_ULOGIC := '0';  -- In the case of a NULL range
-	begin
-	if (arg'length >= 1) then
-		BUS_int := to_ux01 (arg);
-		if (BUS_int'length = 1) then
-			Result := BUS_int (BUS_int'left);
-		elsif (BUS_int'length = 2) then
-			Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
-		else
-			Half   := (BUS_int'length + 1) / 2 + BUS_int'right;
-			Upper  := xor_red (BUS_int (BUS_int'left downto Half));
-			Lower  := xor_red (BUS_int (Half - 1 downto BUS_int'right));
-			Result := Upper xor Lower;
-		end if;
-	end if;
-	return Result;
-
-	end function xor_red;
-
-	-------------------------------------------------------------
-	-- Reduction operators, same as numeric_std functions
-	function and_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return and_red (to_slv(arg));
-	end function and_red;
-
-	function nand_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return not and_red (to_slv(arg));
-	end function nand_red;
-
-	function or_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return or_red (to_slv(arg));
-	end function or_red;
-
-	function nor_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return not or_red (to_slv(arg));
-	end function nor_red;
-
-	function xor_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return xor_red (to_slv(arg));
-	end function xor_red;
-
-	function xnor_red(arg : ufixed_t) return STD_ULOGIC is
-	begin
-		return not xor_red (to_slv(arg));
-	end function xnor_red;
-
-	function and_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return and_red (to_slv(arg));
-	end function and_red;
-
-	function nand_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return not and_red (to_slv(arg));
-	end function nand_red;
-
-	function or_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return or_red (to_slv(arg));
-	end function or_red;
-
-	function nor_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return not or_red (to_slv(arg));
-	end function nor_red;
-
-	function xor_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return xor_red (to_slv(arg));
-	end function xor_red;
-
-	function xnor_red(arg : sfixed_t) return STD_ULOGIC is
-	begin
-		return not xor_red (to_slv(arg));
-	end function xnor_red;
-
-	-------------------------------------------------------------
-
-end; -- package body fixed_ja;
diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm
deleted file mode 100644
index 01c36c4..0000000
--- a/lib/jasm/cg.inc.jsm
+++ /dev/null
@@ -1,72 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xio-address equates for
-; reg_cg_char_addr:	equ		0xXX	; RW
-; reg_cg_line_addr:	equ		0xXX	; RW
-; reg_cg_data:		equ		0xXX	; RW
-; reg_cg_ctrl:		equ		0xXX	; WO
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-cg_clr_line:	push	R0
-				mov		R0, 2
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-cg_clr_screen:	push	R0
-				mov		R0, 1
-				xout	(reg_cg_ctrl), R0	
-				pop		R0
-				ret
-				
-; -------------------------------------------------
-; R0 : char address
-; R1 : line address
-cg_set_addr:	call	cg_wait_rdy
-				xout	(reg_cg_line_addr), R1
-				xout	(reg_cg_char_addr), R0
-				ret
-
-; -------------------------------------------------
-; R0 : character
-cg_putchar:		call	cg_wait_rdy
-				xout	(reg_cg_data), R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts:		push	R0
-cg_p_lp:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		ex_cgp
-				call	cg_putchar
-				jmp		cg_p_lp
-ex_cgp:			pop		R0
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_clr_puts:	call	cg_clr_line
-				call	cg_puts
-				ret				
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts_clr:	call	cg_puts
-				call	cg_clr_line
-				ret				
-
-; -------------------------------------------------
-cg_wait_rdy:	push	R0
-cg_wr_lp:		xin		R0, (reg_hwstat)
-				and		R0, 0x02
-				jz		cg_wr_lp
-				pop		R0
-				ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm
deleted file mode 100644
index 06d39d9..0000000
--- a/lib/jasm/cregs.inc.jsm
+++ /dev/null
@@ -1,7 +0,0 @@
-; JCPU On-Chip register
-cpu_revision:		equ		0x00	; RO
-cpu_control:		equ		0x01	; R/W
-cpu_status:			equ		0x02	; RO
-cpu_int_ctrl:		equ		0x03	; RW
-cpu_cmem_high:		equ		0x04	; RW
-cpu_stack_high:		equ		0x05	; RW
diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm
deleted file mode 100644
index 6f002ee..0000000
--- a/lib/jasm/delays.inc.jsm
+++ /dev/null
@@ -1,64 +0,0 @@
-; -------------------------------------------------
-; Delays
-; -------------------------------------------------
-delay1s:		push	R15
-				mov		R15, 10
-loop1s:			call 	delay100ms		
-				dec		R15
-				jnz		loop1s
-				pop		R15
-				ret
-
-delay100ms:		push	R15
-				mov		R15, 10
-loop100ms:		call 	delay10ms		
-				dec		R15
-				jnz		loop100ms
-				pop		R15
-				ret
-			
-delay10ms:		push	R15
-				mov		R15, 10
-loop10ms:		call	delay1ms		
-				dec		R15
-				jnz		loop10ms
-				pop		R15
-				ret
-		
-delay1ms:		push	R15
-				mov		R15, 10
-loop1ms:		call	delay100us
-				dec		R15
-				jnz		loop1ms
-				pop		R15
-				ret
-
-delay100us:		push	R15
-				mov		R15, 10
-loop100us:		call	delay10us
-				dec		R15
-				jnz		loop100us
-				pop		R15
-				ret
-
-delay10us:		push	R15
-				mov		R15, 99
-loop10us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop10us
-				pop		R15
-				ret
-
-delay1us:		push	R15
-				mov		R15, 9
-loop1us:		nop
-				nop
-				nop
-				dec		R15
-				jnz		loop1us
-				pop		R15
-				ret
-				
-; -------------------------------------------------
diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm
deleted file mode 100644
index d2883fa..0000000
--- a/lib/jasm/lcd.inc.jsm
+++ /dev/null
@@ -1,208 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - lcd_port (LCD-Base)
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-lcd_cmd:		equ		0x00
-lcd_rd:			equ		0x20
-lcd_data:		equ		0x40
-lcd_enable:		equ		0x80
-
-LCD_CMD_Z1:		equ		0x80
-LCD_CMD_Z2:		equ		0xC0
-LCD_CMD_CLEAR:	equ		0x01
-
-; -------------------------------------------------
-; Init LCD
-; -------------------------------------------------
-LCD_init:		mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-				mov		R2, 0x00		
-				mov		R0, 0x03
-				call	_write_lcd
-				call	delay10ms
-
-				mov		R2, 0x00		
-				mov		R0, 0x02
-				call	_write_lcd
-				call	delay1ms
-
-				; 1. Function set: 4-Bit mode, two display lines
-				mov		R0, 0x28
-				call	LCD_writecmd
-
-				; 2. Display on, no cursor
-				mov		R0, 0x0C		
-				call	LCD_writecmd
-
-				; 3. Cursor shift during write
-				mov		R0, 0x06
-				call	LCD_writecmd
-
-				; 4. Display clear
-				mov		R0, 0x01
-				call	LCD_writecmd
-
-				ret
-				
-; -------------------------------------------------
-; LCD_waitbsy
-; -------------------------------------------------
-LCD_waitbsy:	push	R0
-bsy_loop:		call	LCD_readstat
-				and		R0, 0x80
-				jz		ex_bsy
-				call	delay1us
-				jmp		bsy_loop
-ex_bsy:			pop		R0
-				ret
-
-; -------------------------------------------------
-; LCD_writecmd
-; -------------------------------------------------
-; R0 = cmd
-LCD_writeaddr:
-LCD_writecmd:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_write
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_putsx
-; -------------------------------------------------
-; R1 = address of null-terminated string in XMEM
-LCD_putsx:		push	R0
-putsx_loop:		movx	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsx_ex
-				call	LCD_writechar
-				jmp		putsx_loop
-putsx_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_putsc
-; -------------------------------------------------
-; R1 = address of null-terminated string in CMEM
-LCD_putsc:		push	R0
-putsc_loop:		movc	R0, (R1)
-				inc		R1
-				tst		R0
-				jz		putsc_ex
-				call	LCD_writechar
-				jmp		putsc_loop
-putsc_ex:		pop		R0
-				ret
-				
-; -------------------------------------------------
-; LCD_writechar
-; -------------------------------------------------
-; R0 = char
-LCD_writedata:
-LCD_writechar:	push	R2
-				mov		R2, lcd_data
-				call	LCD_write
-				pop		R2
-				ret
-				
-; -------------------------------------------------
-; LCD_write
-; -------------------------------------------------
-; R0 = input
-; R2 = register
-LCD_write:		call	LCD_waitbsy
-				push	R0
-				swap	R0
-				call	_write_lcd
-				pop		R0
-				call	_write_lcd
-				ret
-
-; -------------------------------------------------
-; LCD_readstat
-; -------------------------------------------------
-; R0 = status
-LCD_readstat:	push	R2
-				mov		R2, lcd_cmd
-				call	LCD_read
-				pop		R2
-				ret
-
-; -------------------------------------------------
-; LCD_read
-; -------------------------------------------------
-; R0 = output
-; R2 = register
-LCD_read:		call	_read_lcd
-				swap	R0
-				push	R0
-				call	_read_lcd
-				pop		R2
-				or		R0, R2
-				ret
-				
-; -------------------------------------------------
-; _write
-; -------------------------------------------------
-; R0 = input
-_write_lcd:		push	R1
-
-				and		R0, 0x0F
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, R0
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				or		R1, lcd_rd
-				xout	(lcd_port), R1
-
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; _read
-; -------------------------------------------------
-; R0 = output
-_read_lcd:		push	R1
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				or		R1, lcd_enable
-				xout	(lcd_port), R1
-				call	delay1us
-				xin		R0, (lcd_port)
-				and		R0, 0x0F
-
-				mov		R1, lcd_rd
-				or		R1, R2
-				xout	(lcd_port), R1
-				call	delay1us
-
-				pop		R1
-				ret
-
-				
\ No newline at end of file
diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm
deleted file mode 100644
index 2f66e2a..0000000
--- a/lib/jasm/mul8x8.inc.jsm
+++ /dev/null
@@ -1,42 +0,0 @@
-; -------------------------------------------------
-; mul8x8.inc.jsm
-; -------------------------------------------------
-
-; -------------------------------------------------
-; Parameter:
-; R0 : operand 1
-; R1 : operand 2
-; Return:
-; R0 : product low
-; R1 : product high
-mul8x8:			push	R2
-				push	R3
-				push	R4
-				
-				mov		R4, R1
-				mov		R1, 0
-				mov		R2, 0
-				mov		R3, 0
-				
-loop1:			cmp		R4, 0x01
-				jeq		ende1
-
-				shr		R4
-				jnc		next1
-
-				add		R2, R0
-				addc	R3, R1
-
-next1:			shl		R0
-				rolc	R1
-				jmp		loop1
-				
-ende1:			add		R0, R2
-				addc	R1, R3
-				
-				pop		R4
-				pop		R3
-				pop		R2
-				ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm
deleted file mode 100644
index df557b1..0000000
--- a/lib/jasm/uart.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; uart.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - uart_status (Status register)
-; - uart_data	(Data register)
-
-; -------------------------------------------------
-; sout
-; -------------------------------------------------
-; R0 = input
-sout:			push 	R1
-sout1:			xin		R1, (uart_status)
-				and		R1, 0x02
-				jnz		sout1
-				xout	(uart_data), R0
-				pop		R1
-				ret
-
-; -------------------------------------------------
-; sin
-; -------------------------------------------------
-; R0 = output
-sin:			push 	R1
-sin1:			xin		R1, (uart_status)
-				and		R1, 0x10
-				jz		sin1
-				xin		R0, (uart_data)
-				pop		R1
-				ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm
deleted file mode 100644
index f354d7c..0000000
--- a/lib/jasm/utils.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; utils.inc.jsm
-; -------------------------------------------------
-
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value in lower nibble
-; Return
-; R0 : Hex character representing lower nibble
-nibble2hex:		and		R0, 0x0F
-				cmp		R0, 0x0A
-				jlt		isNum1
-				add		R0, 0x07
-isNum1:			add		R0, 0x30
-				ret
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value
-; Return
-; R0 : Hex character high
-; R1 : Hex character low
-bin2hex:		push	R0
-				call	nibble2hex
-				mov		R1, R0
-				pop		R0
-				swap	R0
-				call	nibble2hex
-				ret
-
-; -------------------------------------------------
diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
deleted file mode 100644
index 854edd0..0000000
--- a/lib/misc/async_port_wb.vhd
+++ /dev/null
@@ -1,317 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.async_types.all;
-
-	------------------------------------------------------------------
-entity async_port_wb is
-	Generic
-	(
-		f_sysclk		: real		:= 100.0;
-		addr_width		: natural	:= 32;
-		data_width		: natural	:= 32;
-		byte_sel_width	: natural	:= 4;
-		async_timespec	: async_timespec_t
-	);
-	Port
-	(
-		CLK_I			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ADDR_I			: in  unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		page_mode_en	: in  STD_LOGIC;
-		async_a			: out unsigned(addr_width-1 downto 0);
-		async_d			: inout unsigned(data_width-1 downto 0);
-		async_cs		: out std_logic;
-		async_wr		: out std_logic;
-		async_rd		: out std_logic;
-		async_be		: out unsigned(byte_sel_width-1 downto 0);
-		async_rst		: out std_logic
-	);
-end async_port_wb;
-
-architecture Behavioral of async_port_wb is
-
-	type async_t is record
-		cs		: std_logic;
-		wr		: std_logic;
-		rd		: std_logic;
-		rst		: std_logic;
-		drive_d	: std_logic;
-	end record;
-	
-	type async_state_t is (start, reset, idle, leadin, pulse, leadout, release);
-	
-	signal s, sn			: async_state_t;
-	signal as				: async_t;
-	signal ack				: std_logic;
-	signal cc_rst			: std_logic;
-	signal cycle_cnt		: natural range 0 to 31;
-	signal cycle_reload		: natural range 0 to 31;
-	signal rdy				: std_logic;
-	signal rdyo				: std_logic;
-	signal en				: std_logic;
-	signal is_idle			: std_logic;
-	signal DAT_I_r			: unsigned(data_width-1 downto 0);
-	signal SEL_I_r			: unsigned(byte_sel_width-1 downto 0);
-	signal WE_I_r			: std_logic;
-	signal ADDR_I_r			: unsigned(addr_width-1 downto 0);
-	signal page_mode_en_r	: std_logic;
-	signal do_page_read		: std_logic;
-	
-	------------------------------------------------------------------
-	begin
-	
-	ASSERT to_cycles(async_timespec.T_pulse_rd, f_sysclk) > 0 report "Read pulse length must be greater than zero!" severity failure;
-	ASSERT to_cycles(async_timespec.T_pulse_wr, f_sysclk) > 0 report "Write pulse length must be greater than zero!" severity failure;
-	ASSERT (not async_timespec.can_page_rd OR (to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) > 1)) report "Read page pulse length must be greater than one!" severity failure;
-
-	SRDY_O	<= CYC_I and rdyo;
-	en		<= CYC_I and STB_I;
-	
-	do_page_read	<= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
-	
-	proc_cycle_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if cc_rst = '1' then
-				cycle_cnt <= cycle_reload;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt <= cycle_cnt - 1;
-			end if;
-		end if;
-	end process;
-	
-	------------------------------------------------------------------
-	proc_state_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s <= start;
-			else
-				s <= sn;
-			end if;
-		end if;
-	end process;
-	
-	proc_state:
-	process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read)
-	begin
-		
-		cycle_reload	<= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
-		cc_rst			<= '0';
-		as.rst			<= '0';
-		as.cs			<= '0';
-		as.wr			<= '0';
-		as.rd			<= '0';
-		as.drive_d		<= '0';
-		ack				<= '0';
-		rdy				<= '0';
-		is_idle			<= '0';
-		
-		sn	<= s;
-		case s is
-		
-		when start =>
-			cc_rst	<= '1';
-			sn		<= reset;
-		when reset =>
-			as.rst	<= '1';
-			if cycle_cnt = 0 then
-				sn	<= idle;
-			end if;
-		when idle =>
-			rdy			<= '1';
-			is_idle		<= '1';
-			if en = '1' then
-				as.cs			<= '1';
-				cc_rst			<= '1';
-				if to_cycles(async_timespec.T_leadin, f_sysclk) = 0 then
-					sn			<= pulse;
-					if WE_I = '1' then
-						cycle_reload	<= 0;
-						sn				<= leadin;	-- always lead-in for writes
-					else
-						cycle_reload	<= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
-						as.rd			<= '1';
-					end if;
-				else
-					cycle_reload	<= to_cycles(async_timespec.T_leadin, f_sysclk) - 1;
-					sn				<= leadin;
-				end if;	
-			end if;
-
-		when leadin =>
-			as.cs		<= '1';
-			as.rd		<= not WE_I_r;
-			as.drive_d	<= WE_I_r;
-			as.wr		<= WE_I_r;
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				sn				<= pulse;
-				if WE_I_r = '1' then
-					cycle_reload	<= to_cycles(async_timespec.T_pulse_wr, f_sysclk) - 1;
-				else
-					cycle_reload	<= to_cycles(async_timespec.T_pulse_rd, f_sysclk) - 1;
-				end if;
-			end if;
-
-		when pulse =>
-			as.cs		<= '1';
-			as.rd		<= not WE_I_r;
-			as.drive_d	<= WE_I_r;
-			as.wr		<= WE_I_r;
-			if cycle_cnt = 0 then
-				as.wr			<= '0';
-				cc_rst			<= '1';
-				ack				<= not WE_I_r;
-				rdy				<= do_page_read;
-				if en = '1' and do_page_read = '1' then
-					cycle_reload	<= to_cycles(async_timespec.T_pulse_page_rd, f_sysclk) - 1;
-					sn				<= pulse;
-				elsif to_cycles(async_timespec.T_leadout, f_sysclk) = 0 then
-					if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
-						sn				<= idle;
-					else
-						cycle_reload	<= to_cycles(async_timespec.T_release, f_sysclk) - 1;
-						sn				<= release;
-					end if;
-				else
-					cycle_reload	<= to_cycles(async_timespec.T_leadout, f_sysclk) - 1;
-					sn				<= leadout;
-				end if;
-			end if;
-				
-		when leadout =>
-			as.cs		<= '1';
-			as.drive_d	<= WE_I_r;
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				if to_cycles(async_timespec.T_release, f_sysclk) = 0 then
-					sn				<= idle;
-				else
-					cycle_reload	<= to_cycles(async_timespec.T_release, f_sysclk) - 1;
-					sn				<= release;
-				end if;
-			end if;
-
-		when release =>
-			if cycle_cnt = 0 then
-				sn				<= idle;
-			end if;
-
-		when others =>
-			sn <= idle;
-			
-		end case;		
-	end process;
-
-	------------------------------------------------------------------
-	output_ctrl:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			async_cs	<= (not async_timespec.pol_cs) xor as.cs;
-			async_wr	<= (not async_timespec.pol_we) xor as.wr;
-			async_rd	<= (not async_timespec.pol_oe) xor as.rd;
-			async_rst	<= (not async_timespec.pol_rst) xor as.rst;
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	din_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if as.rd = '1' then
-				DAT_O(data_width-1 downto 0) 	<= async_d;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_addr:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				async_a		<= (others => '0');
-				SEL_I_r		<= (others => '0');
-			elsif en = '1' and rdy = '1' then
-				async_a 	<= ADDR_I(addr_width-1 downto 0);
-				async_be	<= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
-				SEL_I_r		<= SEL_I(byte_sel_width-1 downto 0);
-				if is_idle = '1' then
-					ADDR_I_r 	<= ADDR_I(addr_width-1 downto 0);
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	data_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			page_mode_en_r	<= page_mode_en;
-			if en = '1' and rdy = '1' then
-				DAT_I_r 		<= DAT_I(data_width-1 downto 0);
-				WE_I_r			<= WE_I;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_SRDY:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				rdyo 	<= '1';
-			elsif en = '1' then
-				rdyo 	<= rdy and not rdyo;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_ACK:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				ACK_O 	<= '0';
-			else
-				ACK_O 	<= ack;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_data:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			async_d 	<= (others => 'Z');
-			if as.drive_d = '1' then
-				async_d 	<= DAT_I_r;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd
deleted file mode 100644
index 1509dc1..0000000
--- a/lib/misc/async_types.vhd
+++ /dev/null
@@ -1,60 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file: 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE IEEE.MATH_REAL.ALL;
-
-package async_types is
-
-	type async_timespec_t is record
-		T_leadin			: real;
-		T_pulse_rd			: real;
-		T_pulse_wr			: real;
-		T_leadout			: real;
-		T_release			: real;
-		T_pulse_rst			: real;
-		T_pulse_page_rd		: real;
-		can_page_rd			: boolean;
-		nbits_page_rd		: natural;
-		pol_cs				: std_logic;
-		pol_oe				: std_logic;
-		pol_we				: std_logic;
-		pol_be				: std_logic;
-		pol_rst				: std_logic;
-	end record;
-
-	function to_cycles(T_ns : real; f_Mhz : real) return natural;
-
-end async_types;
-
-package body async_types is
-
-	function to_cycles(T_ns : real; f_Mhz : real) return natural is
-	begin
-		
-		return natural(ceil(1.0E-3*T_ns*f_Mhz));
-
-	end to_cycles;	
-end async_types;
diff --git a/lib/misc/bbfifo.vhd b/lib/misc/bbfifo.vhd
deleted file mode 100644
index aa8799f..0000000
--- a/lib/misc/bbfifo.vhd
+++ /dev/null
@@ -1,123 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity bbfifo is
-	Generic 
-	(
-		depth	   : integer := 2;
-		data_width : integer := 8
-	);
-	Port
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		ready		: out STD_LOGIC;
-		avail		: out STD_LOGIC;
-		din			: in  unsigned(data_width-1 downto 0);
-		dout		: out unsigned(data_width-1 downto 0)
-	);
-end bbfifo;
-
-architecture Behavioral of bbfifo is
-
-	type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
-	signal req : unsigned(0 to depth);
-	signal rdy : unsigned(1 to depth+1);
-	signal bucket_array : bucket_array_t; 
-	signal ce_in : unsigned(1 to depth);
-	signal ce_out : unsigned(1 to depth);
-	
-begin
-	
-	req(0)			<= we;
-	rdy(depth+1)	<= re;
-	ready			<= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0';
-	avail			<= req(depth);
-	bucket_array(0)	<= din;
-	dout			<= bucket_array(depth);
-	
-gen_ce:
-	for i in 1 to depth generate
-	begin
-		process (rdy, req)
-		begin
-			ce_in(i) <= not req(i) and req(i-1);
-		end process;
-	end generate;
-
-gen_rdy:
-	for i in 1 to depth generate
-	begin
-		process (clk)
-		begin
-			if rising_edge(clk) then
-				if rst = '1' then
-					rdy(i) <= '1';
-				elsif req(i-1) = '1' then
-					rdy(i) <= rdy(i+1);
-				end if;
-			end if;
-		end process;
-	end generate;
-
-gen_req:
-	for i in 1 to depth generate
-	begin
-		process (clk)
-		begin
-			if rising_edge(clk) then
-				if rst = '1' then
-					req(i) <= '0';
-				elsif rdy(i+1) = '1' then
-					req(i) <= req(i-1);
-				end if;
-			end if;
-		end process;
-	end generate;
-
-gen_data:
-	for i in 1 to depth generate
-	begin
-		process (clk)
-		begin
-			if rising_edge(clk) then
-				if rst = '1' then
-					bucket_array(i) <= (others => '0');
-				elsif req(i-1) = '1' then
-					bucket_array(i) <= bucket_array(i-1);
-				end if;
-			end if;
-		end process;
-	end generate;
-
-end Behavioral;
-
diff --git a/lib/misc/clockgen_virtex4.vhd b/lib/misc/clockgen_virtex4.vhd
deleted file mode 100644
index 73a4c0e..0000000
--- a/lib/misc/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,237 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee, work;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-USE WORK.utils_pkg.ALL;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clockgen is
-	generic
-	(
-		clk_in_freq			: real		:= 100.0;
-		clk0_out_phaseshift	: integer	:= 0;
-		clk1_out_phaseshift	: integer	:= 0
-	);
-	port 
-	(
-		-- Clocks and Reset
-		rst				: in std_logic;   -- external async reset, low active
-		clk_in			: in std_logic;   -- system clock (e.g. 100MHz), from board
-		clk_fb_in		: in std_logic;   -- feedback clock
-		clk0_0_out		: out std_logic;  -- System clock #0, dcm#0 output 0°
-		clk0_270_out	: out std_logic;  -- System clock #0, dcm#0 output 270°
-		clk1_0_out		: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		clk1_270_out	: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		locked_out		: out std_logic;  -- DCM locked status
-		error_out		: out std_logic   -- indicates DCM Errors
-	);
-end;
-
-architecture tech of clockgen is
-
-	signal locked					: unsigned(1 downto 0);
-	signal dcm_rst					: unsigned(1 downto 0);
-	signal clk1_0					: std_logic;
-	signal clk1_270					: std_logic;
-	signal clk1_0_bufg				: std_logic;
-	signal clk1_270_bufg			: std_logic;
-	signal clk0_0					: std_logic;
-	signal clk0_270					: std_logic;
-	signal clk0_0_bufg				: std_logic;
-	signal clk0_270_bufg			: std_logic;
-	signal dcm1_locked, dcm2_locked	: unsigned(2 downto 0);
-	signal cnt_q 					: unsigned(4 downto 0);
-
-	type STATE_TYPE is (s0, s1, s2, s3, s4);
-	signal state_q : STATE_TYPE;
-
-begin 
-
-	clk1_0_out		<= clk1_0_bufg;
-	clk1_270_out	<= clk1_270_bufg;
-	clk0_0_out		<= clk0_0_bufg;
-	clk0_270_out	<= clk0_270_bufg;
-
-bufg11: bufg
-	port map
-	(
-		o  => clk0_0_bufg,  
-		i  => clk0_0
-	);
-
-bufg12: bufg
-	port map (
-		o  => clk0_270_bufg,  
-		i  => clk0_270
-	);
-
-bufg13: bufg
-	port map
-	(
-		o  => clk1_0_bufg,  
-		i  => clk1_0
-	);
-
-bufg14: bufg
-	port map (
-		o  => clk1_270_bufg,  
-		i  => clk1_270
-	);
-
-	-------------------------------------------------------------------------------------------------------
-	-- Clock generation
-	-------------------------------------------------------------------------------------------------------
-   
-inst_DCM_BASE_0 : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map (
-		CLK0 => clk0_0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => clk0_270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => locked(0),     -- DCM LOCK status output
-		CLKFB => clk_fb_in,       -- DCM clock feedback
-		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(0)            -- DCM asynchronous reset input
-	);
-
-	inst_DCM_BASE_1 : DCM_BASE
-	generic map (
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	port map (
-		CLK0 => clk1_0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => clk1_270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => locked(1),     -- DCM LOCK status output
-		CLKFB => clk1_0_bufg,       -- DCM clock feedback
-		CLKIN => clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(1)            -- DCM asynchronous reset input
-	);
-
-	dcm_rst(1) <= not locked(0);
-	
-dcm_fsm:
-	process(rst, clk_in)
-	begin
-		if rst = '1' then
-			state_q <= s0;
-			dcm_rst(0) <= '0';
-			cnt_q <= "11111";
-			error_out <= '0';
-			locked_out <= '0';
-			dcm1_locked <= (others => '0');
-			dcm2_locked <= (others => '0');
-		elsif rising_edge(clk_in) then
-			case state_q is
-			when s0 =>
-				state_q <= s1;
-
-			when s1 =>
-			cnt_q <= cnt_q - 1;
-				if cnt_q = 0 then
-					dcm_rst(0) <= '1';
-					state_q <= s2;
-				end if;
-
-			when s2 =>
-				cnt_q <= cnt_q - 1;
-				if cnt_q = 0 then
-					dcm_rst(0) <= '0';
-					state_q <= s3;
-				end if;
-
-			when s3 =>
-				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
-					state_q <= s4;
-					error_out <= '0';
-				end if;
-
-			when s4 =>
-				if dcm1_locked(2)='1' and dcm2_locked(2)='1' then
-					locked_out <= '1';
-				else
-					error_out <= '1';
-				end if;
-			end case;
-
-			-- synchronize 'dcm1_locked'
-			dcm1_locked <= dcm1_locked(1 downto 0) & locked(0);
-			dcm2_locked <= dcm2_locked(1 downto 0) & locked(1);
-
-		end if;
-	end process;
-
-end architecture tech;
-
-
diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd
deleted file mode 100644
index 79317a5..0000000
--- a/lib/misc/debounce.vhd
+++ /dev/null
@@ -1,91 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    19:34:24 10/23/05
--- Design Name:    
--- Module Name:    debounce - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity debounce is
-    Generic ( ncyc_latency : integer := 100);
-    Port ( rst : in std_logic;
-           clk : in std_logic;
-           input : in std_logic;
-           output : out std_logic);
-end debounce;
-
-architecture Behavioral of debounce is
-
-type debounce_state_t is (init_st, wait_st, rel_st);
-signal debounce_cs : debounce_state_t;
-signal debounce_ns : debounce_state_t;
-signal count       : integer range 0 to ncyc_latency;
-signal input_last	 : std_logic;
-
-begin
-
-	debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
-	begin
-		if (rst = '1') then
-			count <= 0;
-			output <= input;
-			input_last <= input;
-		else
-			if rising_edge(clk) then
-				debounce_cs <= debounce_ns;
-				if (debounce_cs = wait_st) then
-					if (count /= 0) then
-						count <= count - 1;
-					end if;
-				else
-					count <= ncyc_latency;
-					if	(debounce_cs = rel_st) then
-						output <= input;
-						input_last <= input;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
-	begin
-		debounce_ns <= debounce_cs;
-		case debounce_cs is
-			when init_st =>
-				if (input /= input_last) then
-					debounce_ns <= wait_st;
-				end if;
-			when wait_st =>
-				if (count = 0) then
-					debounce_ns <= rel_st;
-				end if;
-			when others => 
-				debounce_ns <= init_st;
-		end case;
-	end process;
-
-end Behavioral;
diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd
deleted file mode 100644
index 206a61c..0000000
--- a/lib/misc/debounce2.vhd
+++ /dev/null
@@ -1,142 +0,0 @@
-------------------------------------------------- 
--- Signal Debouncer
--- Jeff Bazinet
--- February 14, 2002
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-
-library ieee; 
-use ieee.std_logic_1164.all;
-library lpm;
-use lpm.lpm_components.lpm_counter;
-
-
-entity debounce is
-	generic(BUFFER_WIDTH:	positive:= 30;
-		CLOCK_DIV: 	positive:= 15
-		);
-	port(	clock:		in std_logic;
-		reset:		in std_logic;
-		signal_in:	in std_logic;
-		signal_out:	out std_logic
-		);
-end entity debounce;
-
-
-architecture rtl of debounce is 
-
-	---------------------------------------------------------------
-	-- SIGNAL DECLARATION
-	---------------------------------------------------------------
-	
-	-- General
-	signal reset_n:	std_logic;
-	
-	-- SLOW CLOCK GENERATION
-	signal clock_reg:	std_logic_vector(CLOCK_DIV-1 downto 0);
-	signal clock_reg_high:	std_logic_vector(CLOCK_DIV-1 downto 1);	
-	signal clock_slow:	std_logic;
-	signal clock_slow_wire:	std_logic;
-	
-	-- DATA BUFFER FILL
-	signal counter_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
-	signal data_buffer_reg:	std_logic_vector(BUFFER_WIDTH-1 downto 0);
-	
-	-- CHECK FOR DEBOUNCE STABILITY
-	signal stable:	std_logic;
-	signal stable_old:	std_logic;
-	signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0);
-	
-	-- PUSH BUTTON ENABLE
-	signal button_pushed:	std_logic;
-	
-	begin
-	
-	---------------------------------------------------------------
-	-- SLOW CLOCK GENERATION
-	---------------------------------------------------------------
-	
-	COUNTER_1: lpm_counter
-		generic map (lpm_width => CLOCK_DIV)
-		port map (
-			clock => clock,
-			sclr => reset_n,
-			cout => clock_slow_wire
-			);
-			
-	process (clock) is
-		begin
-		
-		clock_slow <= clock_slow_wire;
-
-		end process;
-		
-	---------------------------------------------------------------
-	-- DATA BUFFER FILL
-	---------------------------------------------------------------
-	
-	process (clock) is
-		begin
-	
-		if (reset = '0') then
-			-- Initialization
-			data_buffer_reg <= (others => '1');
-		elsif rising_edge(clock_slow) then
-			data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in;
-		end if;
-	
-	end process;
-	
-	---------------------------------------------------------------
-	-- CHECK FOR DEBOUNCE STABILITY
-	---------------------------------------------------------------
-	
-	process (clock) is
-		begin
-	
-		if (reset = '0') then
-			-- Initialization
-			stable <= '0';
-			stable_old <= '0';
-			stable_state_reg <= (others => '0');
-		elsif rising_edge(clock) then
-			if (data_buffer_reg = stable_state_reg) then
-				stable <= '1';
-				stable_state_reg <= (others => '0');
-			else
-				stable <= '0';
-			end if;
-			stable_old <= stable;
-		end if;
-	
-	end process;
-	 
-	---------------------------------------------------------------
-	-- PUSH BUTTON ENABLE
-	---------------------------------------------------------------
-	
-	process (clock) is
-		begin
-	
-		if (reset = '0') then
-			-- Initialization
-			button_pushed <= '0';
-		elsif rising_edge(clock) then
-			if (stable_old = '0' and stable = '1') then
-				button_pushed <= '1';
-			else
-				button_pushed <= '0';
-			end if;	
-		end if;
-	
-	end process;
-	
-	---------------------------------------------------------------
-	---------------------------------------------------------------
-	 
-	signal_out <= button_pushed;
-	reset_n <= not reset;
-	
-end rtl; 
diff --git a/lib/misc/dpram_1w1r.vhd b/lib/misc/dpram_1w1r.vhd
deleted file mode 100644
index dee0972..0000000
--- a/lib/misc/dpram_1w1r.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r;
-
-architecture Behavioral of dpram_1w1r is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clka)
-begin
-if clka'event and clka = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clkb)
-begin
-if clkb'event and clkb = '1' then
-	if en_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w1r1c_sim.vhd b/lib/misc/dpram_1w1r1c_sim.vhd
deleted file mode 100644
index 692e773..0000000
--- a/lib/misc/dpram_1w1r1c_sim.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_sim.vhd,v 1.1 2013-02-07 14:15:37 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r1c is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r1c;
-
-architecture Behavioral of dpram_1w1r1c is
-
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clk)
-begin
-if clk'event and clk = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;	
-	end if;	
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-dout_b <= RAM(to_integer(addr_b_r));
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w1r1c_xil.vhd b/lib/misc/dpram_1w1r1c_xil.vhd
deleted file mode 100644
index b47843e..0000000
--- a/lib/misc/dpram_1w1r1c_xil.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r1c is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r1c;
-
-architecture Behavioral of dpram_1w1r1c is
-
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clk)
-begin
-if clk'event and clk = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;	
-	end if;	
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-dout_b <= RAM(to_integer(addr_b_r));
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w1r2c_sim.vhd b/lib/misc/dpram_1w1r2c_sim.vhd
deleted file mode 100644
index dbcfb2d..0000000
--- a/lib/misc/dpram_1w1r2c_sim.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c;
-
-architecture Behavioral of dpram_1w1r2c is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	
-begin
-
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w1r2c_xil.vhd b/lib/misc/dpram_1w1r2c_xil.vhd
deleted file mode 100644
index 0ed9be8..0000000
--- a/lib/misc/dpram_1w1r2c_xil.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c;
-
-architecture Behavioral of dpram_1w1r2c is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	
-begin
-
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd
deleted file mode 100644
index e07555c..0000000
--- a/lib/misc/dpram_1w1r_dist.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r_dist is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clka		: in  STD_LOGIC;
-		clkb		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r_dist;
-
-architecture Behavioral of dpram_1w1r_dist is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-	attribute ram_style : string;
-	attribute ram_style of RAM: signal is "distributed";
-	
-begin
-
-process (clka)
-	begin
-	if clka'event and clka = '1' then
-		if en_a = '1' then
-			if we_a = '1' then
-				RAM(to_integer(addr_a)) <= din_a;
-			end if;
-		end if;
-	end if;
-end process;
-
-process (clkb)
-	begin
-	if clkb'event and clkb = '1' then
-		if en_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
-		end if;
-	end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w2r1c_sim.vhd b/lib/misc/dpram_1w2r1c_sim.vhd
deleted file mode 100644
index d9c9fb4..0000000
--- a/lib/misc/dpram_1w2r1c_sim.vhd
+++ /dev/null
@@ -1,86 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_1w2r1c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w2r1c;
-
-architecture Behavioral of dpram_1w2r1c is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk)
-begin
-if clk'event and clk = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-		addr_a_r	<= addr_a;
-	end if;
-end if;
-end process;
-
-process (clk)
-begin
-if clk'event and clk = '1' then
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_1w2r1c_xil.vhd b/lib/misc/dpram_1w2r1c_xil.vhd
deleted file mode 100644
index aa74983..0000000
--- a/lib/misc/dpram_1w2r1c_xil.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_1w2r1c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w2r1c;
-
-architecture Behavioral of dpram_1w2r1c is
-
-
-begin
-
-inst_dpram: entity work.dpram_2w2r2c
-	GENERIC MAP 
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP
-	(
-		clk_a	=> clk,
-		clk_b	=> clk,
-		en_a	=> en_a,
-		en_b	=> en_b,
-		we_a	=> we_a,
-		we_b	=> '0',
-		addr_a	=> addr_a,
-		addr_b	=> addr_b,
-		din_a	=> din_a,
-		din_b	=> din_a,
-		dout_a	=> dout_a,
-		dout_b	=> dout_b
-	);
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_2w2r.vhd b/lib/misc/dpram_2w2r.vhd
deleted file mode 100644
index e5a9e6a..0000000
--- a/lib/misc/dpram_2w2r.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r;
-
-architecture Behavioral of dpram_2w2r is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_2w2r1c_sim.vhd b/lib/misc/dpram_2w2r1c_sim.vhd
deleted file mode 100644
index 61f04e6..0000000
--- a/lib/misc/dpram_2w2r1c_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r1c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r1c;
-
-architecture Behavioral of dpram_2w2r1c is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal contention : std_logic;	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-	contention	<= en_a and we_a and en_b and we_b;
-	
-process (clk)
-begin
-if clk'event and clk = '1' then
-	assert contention = '0' report "dpram_2w2r1c: Simultaneous write on Port A and Port B!" severity warning;
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-		addr_a_r	<= addr_a;
-	end if;
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) <= din_b;
-		end if;
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_2w2r1c_xil.vhd b/lib/misc/dpram_2w2r1c_xil.vhd
deleted file mode 100644
index 70c79d3..0000000
--- a/lib/misc/dpram_2w2r1c_xil.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r1c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r1c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk			: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r1c;
-
-architecture Behavioral of dpram_2w2r1c is
-
-
-begin
-
-inst_dpram: entity work.dpram_2w2r2c
-	GENERIC MAP 
-	(
-		addr_width	=> addr_width,
-		data_width	=> data_width
-	)
-	PORT MAP
-	(
-		clk_a	=> clk,
-		clk_b	=> clk,
-		en_a	=> en_a,
-		en_b	=> en_b,
-		we_a	=> we_a,
-		we_b	=> we_b,
-		addr_a	=> addr_a,
-		addr_b	=> addr_b,
-		din_a	=> din_a,
-		din_b	=> din_a,
-		dout_a	=> dout_a,
-		dout_b	=> dout_b
-	);
-
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_2w2r2c_sim.vhd b/lib/misc/dpram_2w2r2c_sim.vhd
deleted file mode 100644
index aed56d3..0000000
--- a/lib/misc/dpram_2w2r2c_sim.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_sim.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c;
-
-architecture Behavioral of dpram_2w2r2c is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a, clk_b)
-begin
-	if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
-	elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
-		RAM(to_integer(addr_b)) <= din_b;
-	end if;
-end process;
-
-process (clk_a)
-begin
-	if clk_a'event and clk_a = '1' then
-		if en_a = '1' then
-			addr_a_r	<= addr_a;
-		end if;
-	end if;
-end process;
-
-process (clk_b)
-begin
-	if clk_b'event and clk_b = '1' then
-		if en_b = '1' then
-			addr_b_r	<= addr_b;
-		end if;
-	end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/misc/dpram_2w2r2c_xil.vhd b/lib/misc/dpram_2w2r2c_xil.vhd
deleted file mode 100644
index 773e7cf..0000000
--- a/lib/misc/dpram_2w2r2c_xil.vhd
+++ /dev/null
@@ -1,93 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: Dual-ported register file with asynchrous read
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r2c_xil.vhd,v 1.1 2013-02-07 14:15:38 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c;
-
-architecture Behavioral of dpram_2w2r2c is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		addr_a_r	<= addr_a;
-	end if;
-end if;
-end process;
-
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/misc/flash_port_wb.vhd b/lib/misc/flash_port_wb.vhd
deleted file mode 100644
index 9dcc7fe..0000000
--- a/lib/misc/flash_port_wb.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.async_types.all;
-
-	------------------------------------------------------------------
-entity flash_port_wb is
-	Generic
-	(
-		f_sysclk		: real		:= 100.0;
-		addr_width		: natural	:= 32;
-		data_width		: natural	:= 32;
-		async_timespec	: async_timespec_t
-	);
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		port_bsyi	: in std_logic;
-		port_bsyo	: out std_logic;
-		port_a		: out unsigned(addr_width-1 downto 0);
-		port_di		: in  unsigned(data_width-1 downto 0);
-		port_do		: out unsigned(data_width-1 downto 0);
-		port_d_drv	: out STD_LOGIC;
-		port_wr		: out STD_LOGIC;
-		port_rd		: out STD_LOGIC;
-		flash_cs	: out std_logic;
-		flash_rst	: out std_logic
-	);
-end flash_port_wb;
-
-architecture Behavioral of flash_port_wb is
-
-	type async_t is record
-		cs		: std_logic;
-		wr		: std_logic;
-		rd		: std_logic;
-		rst		: std_logic;
-		drive_d	: std_logic;
-	end record;
-	
-	type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
-	
-	signal s, sn		: async_state_t;
-	signal as			: async_t;
-	signal ack			: std_logic;
-	signal cc_rst		: std_logic;
-	signal cycle_cnt	: natural range 0 to 31;
-	signal cycle_reload	: natural range 0 to 31;
-	signal rdy			: std_logic;
-	signal rdyo			: std_logic;
-	signal en			: std_logic;
-	signal we_reg		: std_logic;
-	signal data_reg		: unsigned(data_width-1 downto 0);
-	signal addr_reg		: unsigned(addr_width-1 downto 0);
-
-	------------------------------------------------------------------
-	begin
-
-	SRDY_O		<= CYC_I and rdyo;
-	en			<= CYC_I and STB_I;
-	port_a		<= addr_reg;
-	port_do		<= data_reg;
-	port_d_drv	<= as.drive_d;
-	port_wr		<= (not async_timespec.pol_we) xor as.wr;
-	port_rd		<= (not async_timespec.pol_oe) xor as.rd;
-	
-	proc_cycle_counter:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if cc_rst = '1' then
-				cycle_cnt <= cycle_reload;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt <= cycle_cnt - 1;
-			end if;
-		end if;
-	end process;
-	
-	------------------------------------------------------------------
-	proc_state_next:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				s <= start;
-			else
-				s <= sn;
-			end if;
-		end if;
-	end process;
-	
-	proc_state:
-	process(s, cycle_cnt, en, we_reg, port_bsyi)
-	begin
-		
-		cycle_reload	<= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
-		cc_rst			<= '0';
-		as.rst			<= '0';
-		as.cs			<= '0';
-		as.wr			<= '0';
-		as.rd			<= '0';
-		as.drive_d		<= '0';
-		ack				<= '0';
-		rdy				<= '0';
-		port_bsyo		<= '1';
-		
-		sn	<= s;
-		case s is
-		
-		when start =>
-			cc_rst	<= '1';
-			sn		<= reset;
-		when reset =>
-			as.rst	<= '1';
-			if cycle_cnt = 0 then
-				sn	<= idle;
-			end if;
-		when idle =>
-			port_bsyo	<= '0';
-			rdy			<= '1';
-			if en = '1' then
-				sn		<= go;
-			end if;	
-		when go =>
-			port_bsyo	<= '0';
-			if port_bsyi = '0' then
-				as.cs			<= '1';
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
-				if we_reg = '0' then
-					sn				<= leadin_rd;
-				else
-					sn				<= leadin_wr;
-				end if;
-			end if;
-		when leadin_rd =>
-			as.cs		<= '1';
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
-				as.rd			<= '1';
-				sn				<= read;
-			end if;
-
-		when leadin_wr =>
-			as.cs		<= '1';
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
-				as.wr			<= '1';
-				as.drive_d		<= '1';
-				sn				<= write;
-			end if;
-	
-		when read =>
-			as.cs		<= '1';
-			as.rd		<= '1';
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
---				as.rd			<= '0';
-				sn				<= leadout_rd;
-				ack				<= '1';
-			end if;
-				
-		when write =>
-			as.drive_d	<= '1';
-			as.cs		<= '1';
-			as.wr		<= '1';
-			if cycle_cnt = 0 then
-				as.wr			<= '0';
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
-				sn				<= leadout_wr;
---				ack				<= '1';
-			end if;
-
-		when leadout_rd =>
-			as.cs		<= '1';
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_release, f_sysclk)-1;
-				sn				<= release;
-				as.cs			<= '0';
-			end if;
-
-		when leadout_wr =>
-			as.cs		<= '1';
-			as.drive_d	<= '1';
-			if cycle_cnt = 0 then
-				cc_rst			<= '1';
-				cycle_reload	<= to_cycles(async_timespec.T_release, f_sysclk)-1;
-				sn				<= release;
-				as.cs			<= '0';
-			end if;
-
-		when release =>
-			if cycle_cnt = 0 then
-				sn				<= idle;
-			end if;
-
-		when others =>
-			sn <= idle;
-			
-		end case;		
-	end process;
-
-	------------------------------------------------------------------
-	output_ctrl:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			flash_cs	<= (not async_timespec.pol_cs) xor as.cs;
-			flash_rst	<= (not async_timespec.pol_rst) xor as.rst;
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	din_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if as.rd = '1' then
-				DAT_O(data_width-1 downto 0) 	<= port_di;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	data_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if en = '1' and rdy = '1' then
-				we_reg		<= WE_I;
-				data_reg 	<= DAT_I(data_width-1 downto 0);
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	addr_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if en = '1' and rdy = '1' then
-				addr_reg 	<= ADDR_I(addr_width-1 downto 0);
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_SRDY:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				rdyo 	<= '1';
-			elsif en = '1' then
-				rdyo 	<= rdy and not rdyo;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-	output_ACK:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				ACK_O 	<= '0';
-			else
-				ACK_O 	<= ack;
-			end if;	
-		end if;
-	end process;
-
-	------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/gpio_wb.vhd b/lib/misc/gpio_wb.vhd
deleted file mode 100644
index 7434f85..0000000
--- a/lib/misc/gpio_wb.vhd
+++ /dev/null
@@ -1,309 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY gpio_wb IS
-	Generic
-	(
-		f_sysclk	: real	:= 100.0
-	);
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_TIM_O	: out STD_LOGIC;
-
-		sys_gpi_0	: in unsigned(31 downto 0);
-		sys_gpo_0	: out unsigned(31 downto 0)
-
-	);
-END gpio_wb;
-
-ARCHITECTURE behavior OF gpio_wb IS
-
-	constant num_timers			: natural := 2;
-	constant ncycles_usec		: natural := natural(f_sysclk);
-	
-	signal gpio_0_dout_reg		: unsigned(31 downto 0);
-	signal gpio_0_dir_reg		: unsigned(31 downto 0);
-	signal gpio_0_din_reg		: unsigned(31 downto 0);
-
-	-- Signals to form an timer generating an interrupt every microsecond
-	subtype tick_usec_t	is natural range 0 to ncycles_usec-1;
-	signal tick_usec			: tick_usec_t := 0;
-	signal cnt_usec				: unsigned(31 downto 0);
-	signal cnt_sec				: unsigned(31 downto 0);
-	signal cnt_usec_preset		: unsigned(31 downto 0);
-	signal cnt_sec_preset		: unsigned(31 downto 0);
-	signal cnt_usec_en			: std_logic;
-	signal cnt_usec_we			: std_logic;
-	signal cnt_sec_en			: std_logic;
-	signal cnt_sec_we			: std_logic;
-
-	type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
-	signal timer_cnt			: timer_array_t;
-	signal timer_cmp			: timer_array_t;
-	signal timer_en				: unsigned(0 to num_timers-1);
-	signal timer_inten			: unsigned(0 to num_timers-1);
-	signal timer_irq			: unsigned(0 to num_timers-1);
-	signal timer_ovl			: unsigned(0 to num_timers-1);
-	signal timer_irq_ack		: unsigned(0 to num_timers-1);
-	signal timer_cnt_we			: unsigned(0 to num_timers-1);
-	signal timer_cmp_we			: unsigned(0 to num_timers-1);
-	
-	signal reg_data_wr			: unsigned(31 downto 0);
-	
-begin
-
-	SRDY_O		<= CYC_I;
-	
-tim_irq:
-	process(timer_irq)
-	variable irq : std_logic;
-	begin
-		irq := '0';
-		for i in 0 to num_timers-1 loop
-			irq	:= irq or timer_irq(i);
-		end loop;
-		INT_TIM_O	<= irq;
-	end process;	
-		
-------------------------------------------------------------------
-gpio_0_out:
-	process(gpio_0_dir_reg, gpio_0_dout_reg)
-	begin
-		for i in 0 to 31 loop
-			sys_gpo_0(i)	<= 'Z';
-			if gpio_0_dir_reg(i) = '1' then
-				sys_gpo_0(i)	<= gpio_0_dout_reg(i);
-			end if;
-		end loop;
-	end process;	
-		
-------------------------------------------------------------------
-gpio_0_in:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			for i in 0 to 31 loop
-				if gpio_0_dir_reg(i) = '1' then
-					gpio_0_din_reg(i)	<= gpio_0_dout_reg(i);
-				else
-					gpio_0_din_reg(i)	<= sys_gpi_0(i);
-				end if;
-			end loop;
-		end if;
-	end process;	
-		
-
-------------------------------------------------------------------
-registers_write: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			cnt_usec_we		<= '0';
-			cnt_sec_we		<= '0';
-			timer_cnt_we	<= (others => '0');
-			timer_cmp_we	<= (others => '0');
-			timer_irq_ack	<= (others => '0');
-			if RST_I = '1' then
-				gpio_0_dout_reg	<= (others => '0');
-				gpio_0_dir_reg	<= (others => '0');
-				timer_en		<= (others => '0');
-				timer_inten		<= (others => '0');
-			elsif (STB_I and CYC_I and WE_I) = '1' then
-				reg_data_wr		<= DAT_I;
-				case ADDR_I(6 downto 2) is
-				
-				when "00000" =>
-					gpio_0_dout_reg <= DAT_I;
-					
-				when "00001" =>
-					gpio_0_dir_reg 	<= DAT_I;
-					
-				when "00010" =>
-					cnt_usec_we		<= '1';
-
-				when "00011" =>
-					cnt_sec_we		<= '1';
-					
-				when "00110" =>		-- timer control
-					for i in 0 to num_timers-1 loop
-						timer_en(i)			<= DAT_I(2*i+0);
-						timer_inten(i)		<= DAT_I(2*i+1);
-					end loop;
-				when "00111" =>		-- timer status
-					for i in 0 to num_timers-1 loop
-						timer_irq_ack(i)	<= DAT_I(2*i);	-- IRQ acknowledge
-					end loop;
-
-				when "01000" =>		-- timer count 0
-					timer_cnt_we(0)	<= '1';
-
-				when "01001" =>		-- timer count 1
-					timer_cnt_we(1)	<= '1';
-
-				when "01100" =>		-- timer compare 0
-					timer_cmp_we(0)	<= '1';
-
-				when "01101" =>		-- timer compare 1
-					timer_cmp_we(1)	<= '1';
-
-				when others => null;
-				end case;
-			end if;	
-		end if;	
-	end process;
-
-registers_read: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			ACK_O			<= '0';
-			if (STB_I and CYC_I) = '1' then
-				ACK_O		<= not WE_I;
-				DAT_O		<= (others => '0');
-				case ADDR_I(6 downto 2) is
-
-				when "00000" =>
-					DAT_O	<= gpio_0_din_reg;
-
-				when "00001" =>
-					DAT_O	<= gpio_0_dir_reg;
-
-				when "00010" =>
-					DAT_O	<= cnt_usec;
-
-				when "00011" =>
-					DAT_O	<= cnt_sec;
-
-				when "00110" =>		-- timer control
-					for i in 0 to num_timers-1 loop
-						DAT_O(2*i+0)	<= timer_en(i);
-						DAT_O(2*i+1)	<= timer_inten(i);
-					end loop;
-					
-				when "00111" =>		-- timer status
-					for i in 0 to num_timers-1 loop
-						DAT_O(2*i+0)	<= timer_irq(i);
-						DAT_O(2*i+1)	<= timer_ovl(i);
-					end loop;
-
-				when "01000" =>		-- timer count 0
-					DAT_O			<= timer_cnt(0);
-
-				when "01001" =>		-- timer count 1
-					DAT_O			<= timer_cnt(1);
-
-				when "01100" =>		-- timer compare 0
-					DAT_O			<= timer_cmp(0);
-
-				when "01101" =>		-- timer compare 1
-					DAT_O			<= timer_cmp(1);
-
-				when others => null;
-				end case;
-			end if;
-		end if;	
-	end process;
-
-cnt_usec_tick:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			cnt_usec_en		<= '0';
-			if tick_usec >= tick_usec_t'high then
-				tick_usec		<= 0;
-				cnt_usec_en		<= '1';
-			else
-				tick_usec		<= tick_usec + 1;
-			end if;
-		end if;
-	end process;
-
--- H/W Clock
-cnt_usec_clock:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			cnt_sec_en		<= '0';
-			if cnt_usec_we = '1' then
-				cnt_usec		<= reg_data_wr;
-			elsif cnt_usec_en = '1' then
-				if to_01(cnt_usec) >= to_unsigned(1E6 - 1, 32) then
-					cnt_usec		<= (others => '0');
-					cnt_sec_en		<= '1';
-				else
-					cnt_usec		<= cnt_usec + 1;
-				end if;
-			end if;	
-		end if;
-	end process;
-
-cnt_sec_clock:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if cnt_sec_we = '1' then
-				cnt_sec		<= reg_data_wr;
-			elsif cnt_sec_en = '1' then
-				cnt_sec		<= cnt_sec + 1;
-			end if;	
-		end if;
-	end process;
-
--- Interrupt timer
-proc_int_timer:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			for i in 0 to num_timers-1 loop
-				if RST_I = '1' then
-					timer_ovl(i) 	<= '0';
-					timer_irq(i)	<= '0';
-				elsif timer_irq_ack(i) = '1' then
-					timer_ovl(i)	<= '0';
-					timer_irq(i)	<= '0';
-				elsif timer_cnt_we(i) = '1' then
-					timer_cnt(i)		<= reg_data_wr;
-				elsif timer_en(i) = '1' then
-					if to_01(timer_cnt(i)) >= timer_cmp(i) then
-						timer_cnt(i)		<= (others => '0');
-						if timer_inten(i) = '1' then
-							if timer_irq(i) = '1' then
-								timer_ovl(i) <= '1';
-							end if;	
-							timer_irq(i)	<= '1';
-						end if;	
-					else
-						timer_cnt(i)		<= timer_cnt(i) + 1;
-					end if;
-				end if;	
-			end loop;	
-		end if;
-	end process;
-
-proc_int_timer_reload:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			for i in 0 to num_timers-1 loop
-				if timer_cmp_we(i) = '1' then
-					timer_cmp(i)	<= reg_data_wr;
-				end if;	
-			end loop;	
-		end if;
-	end process;
-
-------------------------------------------------------------------
-end behavior;
diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd
deleted file mode 100644
index 11f97eb..0000000
--- a/lib/misc/lcd_port.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-	------------------------------------------------------------------
-entity lcd_port is
-	Port (
-			rst			: in std_logic;
-			clk			: in std_logic;
-			we			: in std_logic;
-			din			: in unsigned(7 downto 0);
-			dout		: out unsigned(7 downto 0);
-			lcd_d		: inout unsigned(3 downto 0);
-			lcd_e		: out std_logic;
-			lcd_rs		: out std_logic;
-			lcd_rw		: out std_logic
-		);
-	end lcd_port;
-
-architecture Behavioral of lcd_port is
-
-	constant clcd_e : integer := 7;
-	constant clcd_rs : integer := 6;
-	constant clcd_rw : integer := 5;
-	
-	type lcd_t is record
-		d	: unsigned(3 downto 0);
-		e	: std_logic;
-		rs	: std_logic;
-		rw	: std_logic;
-	end record;
-	
-	------------------------------------------------------------------
-	begin
-
-	proc_lcd_port:
-	process(rst, clk)
-	variable vlcd : lcd_t;
-	begin
-		if (rst = '1') then
-			dout	<= (others => '0');
-			vlcd.d	:= (others => '0');
-			vlcd.e	:= '0';
-			vlcd.rw	:= '1';
-			vlcd.rs	:= '0';
-		elsif rising_edge(clk) then
-			dout <= unsigned("0000" & lcd_d);
-			if we = '1' then
-				vlcd.d	:= din(3 downto 0);
-				vlcd.e	:= din(clcd_e);
-				vlcd.rs	:= din(clcd_rs);
-				vlcd.rw	:= din(clcd_rw);
-			end if;
-		end if;	
-		if vlcd.rw = '0' then	
-			lcd_d <= unsigned(vlcd.d);
-		else
-			lcd_d <= (others => 'Z');
-		end if;
-		lcd_e	<= vlcd.e;
-		lcd_rs	<= vlcd.rs;
-		lcd_rw	<= vlcd.rw;
-	end process;
-	------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/mult_signed.vhd b/lib/misc/mult_signed.vhd
deleted file mode 100644
index 7740b37..0000000
--- a/lib/misc/mult_signed.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-USE ieee.numeric_std.all;
-
-entity signed_mult is
-generic 
-(
-	latency		: natural := 2;
-	data_width	: natural := 16
-);
-port
-(
-	clk			: in std_logic;
-	ce			: in std_logic;
-	a			: in signed (data_width-1 downto 0);
-	b			: in signed (data_width-1 downto 0);
-	result		: out signed (2*data_width-1 downto 0)
-);
-end signed_mult;
-
-architecture rtl of signed_mult is
-	
-	constant in_latency		: natural := latency - 1;
-	constant out_latency	: natural := latency - in_latency;
-	
-	subtype in_t is signed (data_width-1 downto 0);
-	subtype out_t is signed (2*data_width-1 downto 0);
-	type in_pipe_t is array (in_latency downto 1) of in_t;
-	type out_pipe_t is array (out_latency downto 1) of out_t;
-
-	signal a_pipe	: in_pipe_t;
-	signal b_pipe	: in_pipe_t;
-	signal out_pipe	: out_pipe_t;
-
-begin
-
-	result	<= out_pipe(out_latency);
-	
-input_pipe_reg: 
-	process(clk)
-	begin
-	if rising_edge(clk) then
-		if ce = '1' then
-			a_pipe	<= a_pipe(in_latency-1 downto 1) & a;
-			b_pipe	<= b_pipe(in_latency-1 downto 1) & b;
-		end if;	
-	end if;	
-	end process;
-	
-mult_pipe_reg: 
-	process (clk)
-	variable res : out_t;
-	begin
-	if rising_edge(clk) then
-		res := a_pipe(in_latency) * b_pipe(in_latency);
-		if ce = '1' then
-			out_pipe	<= out_pipe(out_latency-1 downto 1) & res;
-		end if;
-	end if;
-	end process;
-
-end rtl;
diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd
deleted file mode 100644
index 2f5d8bd..0000000
--- a/lib/misc/oneshot.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    21:52:19 10/22/05
--- Design Name:    
--- Module Name:    oneshot - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
--- Component Template
---
---	COMPONENT oneshot
---	GENERIC (mode : integer);
---	PORT(
---		rst : IN std_logic;
---		clk : IN std_logic;
---		input : IN std_logic;          
---		output : OUT std_logic
---		);
---	END COMPONENT;
---
--- Instantation Template
---
---	oneshot_int: oneshot 
---	GENERIC MAP (
---		mode => 1)		
---	PORT MAP(
---		rst => ,
---		clk => ,
---		input => ,
---		output => 
---	);
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity oneshot is
-    Generic ( mode : integer range 0 to 2 := 1);
-    Port ( rst : in std_logic;
-           clk : in std_logic;
-           input : in std_logic;
-           output : out std_logic);
-end oneshot;
-
-architecture Behavioral of oneshot is
-
-type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st);
-
-signal shot_cs : shot_state_t;
-signal shot_ns : shot_state_t;
-
-begin
-
-mode_0:
-if mode = 0 generate
-begin
-	shot_clk: process(rst, clk, shot_ns, input)
-	begin
-		if (rst = '1') then
-			if (input = '1') then
-				shot_cs <= release_pos_st;
-			else
-				shot_cs <= release_neg_st;
-			end if;
-		else
-			if rising_edge(clk) then
-				shot_cs <= shot_ns;
-			end if;
-		end if;
-	end process;
-
-	shot_in: process(rst, clk, input, shot_cs)
-	begin
-		shot_ns <= shot_cs;
-		case shot_cs is
-			when release_pos_st =>
-				if (input = '0') then
-					shot_ns <= shot_neg_st;
-				end if;
-			when shot_neg_st =>
-				shot_ns <= release_neg_st;
-			when release_neg_st =>
-				if (input = '1') then
-					shot_ns <= release_pos_st;
-				end if;
-			when others => null;
-		end case;
-	end process;
-
-	shot_out: process(shot_cs)
-	begin
-		output   <= '0';
-		case shot_cs is
-			when shot_pos_st =>
-				output   <= '1';
-			when shot_neg_st =>
-				output   <= '1';
-			when others => null;
-		end case;
-	end process;
-end generate;
-
-mode_1:
-if mode = 1 generate
-begin
-	shot_clk: process(rst, clk, shot_ns, input)
-	begin
-		if (rst = '1') then
-			if (input = '1') then
-				shot_cs <= release_pos_st;
-			else
-				shot_cs <= release_neg_st;
-			end if;
-		else
-			if rising_edge(clk) then
-				shot_cs <= shot_ns;
-			end if;
-		end if;
-	end process;
-
-	shot_in: process(rst, clk, input, shot_cs)
-	begin
-		shot_ns <= shot_cs;
-		case shot_cs is
-			when shot_pos_st =>
-				shot_ns <= release_pos_st;
-			when release_pos_st =>
-				if (input = '0') then
-					shot_ns <= release_neg_st;
-				end if;
-			when release_neg_st =>
-				if (input = '1') then
-					shot_ns <= shot_pos_st;
-				end if;
-			when others => null;
-		end case;
-	end process;
-
-	shot_out: process(shot_cs)
-	begin
-		output   <= '0';
-		case shot_cs is
-			when shot_pos_st =>
-				output   <= '1';
-			when shot_neg_st =>
-				output   <= '1';
-			when others => null;
-		end case;
-	end process;
-end generate;
-
-mode_2:
-if mode = 2 generate
-begin
-	shot_clk: process(rst, clk, shot_ns, input)
-	begin
-		if (rst = '1') then
-			if (input = '1') then
-				shot_cs <= release_pos_st;
-			else
-				shot_cs <= release_neg_st;
-			end if;
-		else
-			if rising_edge(clk) then
-				shot_cs <= shot_ns;
-			end if;
-		end if;
-	end process;
-
-	shot_in: process(rst, clk, input, shot_cs)
-	begin
-		shot_ns <= shot_cs;
-		case shot_cs is
-			when shot_pos_st =>
-				shot_ns <= release_pos_st;
-			when release_pos_st =>
-				if (input = '0') then
-					shot_ns <= shot_neg_st;
-				end if;
-			when shot_neg_st =>
-				shot_ns <= release_neg_st;
-			when release_neg_st =>
-				if (input = '1') then
-					shot_ns <= shot_pos_st;
-				end if;
-		end case;
-	end process;
-
-	shot_out: process(shot_cs)
-	begin
-		output   <= '0';
-		case shot_cs is
-			when shot_pos_st =>
-				output   <= '1';
-			when shot_neg_st =>
-				output   <= '1';
-			when others => null;
-		end case;
-	end process;
-end generate;
-
-			
-
-end Behavioral;
diff --git a/lib/misc/pkg_template.vhd b/lib/misc/pkg_template.vhd
deleted file mode 100644
index fe866e8..0000000
--- a/lib/misc/pkg_template.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package template_pkg is
-	-- Constants
-	-- Types
-	-- Functions
-
-end template_pkg;
-
-package body template_pkg is
-
-end template_pkg;
-
diff --git a/lib/misc/ram_sim.vhd b/lib/misc/ram_sim.vhd
deleted file mode 100644
index 6d26672..0000000
--- a/lib/misc/ram_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-ENTITY ram IS
-	Generic 
-	(
-		word_addr_width 	: integer := 6
-	);
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	constant depth : natural := 2**word_addr_width;
-	
-	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
-
-	function sram_clear return sram_t is
-
-	variable result : sram_t;
-	begin
-		for i in 0 to sram_t'length-1 loop
-			result(i) := (others => '0');
-		end loop;
-		return result;
-	end sram_clear;
-
-	signal sram : sram_t := sram_clear;
-	
-BEGIN
-
-
-SRAM_RW:
-	process(clk)
-	variable index : natural range 0 to depth-1;
-	begin
-		if rising_edge(clk) and ce = '1' then
-			index := to_integer(addr(word_addr_width+1 downto 2));
-			if we(0) = '1' then
-				sram(index)(7 downto 0)		<= din(7 downto 0);
-			end if;	
-			if we(1) = '1' then
-				sram(index)(15 downto 8)	<= din(15 downto 8);
-			end if;	
-			if we(2) = '1' then
-				sram(index)(23 downto 16)	<= din(23 downto 16);
-			end if;	
-			if we(3) = '1' then
-				sram(index)(31 downto 24)	<= din(31 downto 24);
-			end if;	
-			dout <= sram(index);
-		end if;	
-	end process;
-	
-end behavior;
diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd
deleted file mode 100644
index 5169ef9..0000000
--- a/lib/misc/ram_wb.vhd
+++ /dev/null
@@ -1,87 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library work;
-use work.utils_pkg.all;
-
-ENTITY ram_wb IS
-	GENERIC 
-	(
-		NUM_WORDS 	: integer := 64
-	);
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0)
-	);
-END ram_wb;
-
-ARCHITECTURE behavior OF ram_wb IS
-
-	COMPONENT ram
-	GENERIC 
-	(
-		word_addr_width 	: integer
-	);
-	PORT 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	signal data_en : std_logic;
-	signal we : unsigned(3 downto 0);
-
-begin
-
-	we <= SEL_I and (3 downto 0 => WE_I);
-	
-	data_en	<= CYC_I and STB_I and MRDY_I;
-	SRDY_O	<= CYC_I;
-	
-data_valid_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				ACK_O	<= '0';
-			else
-				ACK_O	<= data_en and not WE_I;
-			end if;
-		end if;
-	end process;
-
-inst_ram : ram
-	GENERIC MAP 
-	(
-		word_addr_width	=> NextExpBaseTwo(NUM_WORDS)
-	)
-	PORT MAP 
-	(
-		clk		=> CLK_I,
-		ce		=> data_en,
-		we		=> we,
-		addr	=> ADDR_I,
-		din		=> DAT_I,
-		dout	=> DAT_O
-	);
-
-
-
-end behavior;
diff --git a/lib/misc/rom_sim.vhd b/lib/misc/rom_sim.vhd
deleted file mode 100644
index 409a50c..0000000
--- a/lib/misc/rom_sim.vhd
+++ /dev/null
@@ -1,2086 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	signal addr_r		: unsigned(31 downto 0);
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	constant word_array : word_array_t :=
-	(
-
-		X"3C1A1040", -- 00000000
-		X"375A000C", -- 00000004
-		X"409A6000", -- 00000008
-		X"241A0000", -- 0000000C
-		X"409A6800", -- 00000010
-		X"401A7800", -- 00000014
-		X"00000000", -- 00000018
-		X"409AF800", -- 0000001C
-		X"3C1ABFC0", -- 00000020
-		X"275A01C4", -- 00000024
-		X"03400008", -- 00000028
-		X"00000000", -- 0000002C
-		X"00000000", -- 00000030
-		X"00000000", -- 00000034
-		X"00000000", -- 00000038
-		X"00000000", -- 0000003C
-		X"00000000", -- 00000040
-		X"00000000", -- 00000044
-		X"00000000", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"00000000", -- 00000054
-		X"00000000", -- 00000058
-		X"00000000", -- 0000005C
-		X"00000000", -- 00000060
-		X"00000000", -- 00000064
-		X"00000000", -- 00000068
-		X"00000000", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BA000", -- 00000184
-		X"277B0000", -- 00000188
-		X"001AD082", -- 0000018C
-		X"335A000F", -- 00000190
-		X"035BD025", -- 00000194
-		X"AF7A0000", -- 00000198
-		X"401A6800", -- 0000019C
-		X"00000000", -- 000001A0
-		X"001AD202", -- 000001A4
-		X"335A00FF", -- 000001A8
-		X"1740FFFB", -- 000001AC
-		X"00000000", -- 000001B0
-		X"401A7000", -- 000001B4
-		X"00000000", -- 000001B8
-		X"03400008", -- 000001BC
-		X"42000010", -- 000001C0
-		X"3C1AA001", -- 000001C4
-		X"275A0008", -- 000001C8
-		X"241B000D", -- 000001CC
-		X"A35B0000", -- 000001D0
-		X"3C1DBFD0", -- 000001D4
-		X"27BDFFF0", -- 000001D8
-		X"241A0005", -- 000001DC
-		X"1340009F", -- 000001E0
-		X"241AFFFB", -- 000001E4
-		X"1340009D", -- 000001E8
-		X"241A0000", -- 000001EC
-		X"13400003", -- 000001F0
-		X"00000000", -- 000001F4
-		X"0BF00118", -- 000001F8
-		X"00000000", -- 000001FC
-		X"241A0005", -- 00000200
-		X"241B0006", -- 00000204
-		X"135B0095", -- 00000208
-		X"241AFFFB", -- 0000020C
-		X"135B0093", -- 00000210
-		X"241A0000", -- 00000214
-		X"135B0091", -- 00000218
-		X"241A0006", -- 0000021C
-		X"135B0003", -- 00000220
-		X"00000000", -- 00000224
-		X"0BF00118", -- 00000228
-		X"00000000", -- 0000022C
-		X"241AFFFB", -- 00000230
-		X"0741008A", -- 00000234
-		X"241A0005", -- 00000238
-		X"07410002", -- 0000023C
-		X"00000000", -- 00000240
-		X"0BF00118", -- 00000244
-		X"241A0000", -- 00000248
-		X"07410002", -- 0000024C
-		X"00000000", -- 00000250
-		X"0BF00118", -- 00000254
-		X"241AFFFB", -- 00000258
-		X"1F400080", -- 0000025C
-		X"241A0000", -- 00000260
-		X"1F40007E", -- 00000264
-		X"241A0005", -- 00000268
-		X"1F400002", -- 0000026C
-		X"00000000", -- 00000270
-		X"0BF00118", -- 00000274
-		X"241A0005", -- 00000278
-		X"1B400078", -- 0000027C
-		X"241A0000", -- 00000280
-		X"1B400002", -- 00000284
-		X"00000000", -- 00000288
-		X"0BF00118", -- 0000028C
-		X"241AFFFB", -- 00000290
-		X"1B400002", -- 00000294
-		X"00000000", -- 00000298
-		X"0BF00118", -- 0000029C
-		X"241A0005", -- 000002A0
-		X"0740006E", -- 000002A4
-		X"241A0000", -- 000002A8
-		X"0740006C", -- 000002AC
-		X"241AFFFB", -- 000002B0
-		X"07400002", -- 000002B4
-		X"00000000", -- 000002B8
-		X"0BF00118", -- 000002BC
-		X"241A0005", -- 000002C0
-		X"241B0006", -- 000002C4
-		X"175B0002", -- 000002C8
-		X"00000000", -- 000002CC
-		X"0BF00118", -- 000002D0
-		X"241AFFFB", -- 000002D4
-		X"175B0002", -- 000002D8
-		X"00000000", -- 000002DC
-		X"0BF00118", -- 000002E0
-		X"241AFFFA", -- 000002E4
-		X"175B0002", -- 000002E8
-		X"00000000", -- 000002EC
-		X"0BF00118", -- 000002F0
-		X"241A0000", -- 000002F4
-		X"175B0002", -- 000002F8
-		X"00000000", -- 000002FC
-		X"0BF00118", -- 00000300
-		X"241A0006", -- 00000304
-		X"175B0055", -- 00000308
-		X"241A0005", -- 0000030C
-		X"17400002", -- 00000310
-		X"00000000", -- 00000314
-		X"0BF00118", -- 00000318
-		X"241AFFFB", -- 0000031C
-		X"17400002", -- 00000320
-		X"00000000", -- 00000324
-		X"0BF00118", -- 00000328
-		X"241A0000", -- 0000032C
-		X"1740004B", -- 00000330
-		X"241B0005", -- 00000334
-		X"2F7A0006", -- 00000338
-		X"2F7AFFFA", -- 0000033C
-		X"241BFFFB", -- 00000340
-		X"2F7A0006", -- 00000344
-		X"2F7AFFFA", -- 00000348
-		X"241B0006", -- 0000034C
-		X"2F7A0005", -- 00000350
-		X"2F7AFFFB", -- 00000354
-		X"241BFFFA", -- 00000358
-		X"2F7A0005", -- 0000035C
-		X"2F7AFFFB", -- 00000360
-		X"241B0005", -- 00000364
-		X"2B7A0006", -- 00000368
-		X"2B7AFFFA", -- 0000036C
-		X"241BFFFB", -- 00000370
-		X"2B7A0006", -- 00000374
-		X"2B7AFFFA", -- 00000378
-		X"241B0006", -- 0000037C
-		X"2B7A0005", -- 00000380
-		X"2B7AFFFB", -- 00000384
-		X"241BFFFA", -- 00000388
-		X"2B7A0005", -- 0000038C
-		X"2B7AFFFB", -- 00000390
-		X"241A0005", -- 00000394
-		X"241B0006", -- 00000398
-		X"035BD02B", -- 0000039C
-		X"241A0005", -- 000003A0
-		X"241BFFFA", -- 000003A4
-		X"035BD02B", -- 000003A8
-		X"241AFFFB", -- 000003AC
-		X"241B0006", -- 000003B0
-		X"035BD02B", -- 000003B4
-		X"241AFFFB", -- 000003B8
-		X"241BFFFA", -- 000003BC
-		X"035BD02B", -- 000003C0
-		X"241A0006", -- 000003C4
-		X"241B0005", -- 000003C8
-		X"035BD02B", -- 000003CC
-		X"241A0006", -- 000003D0
-		X"241BFFFB", -- 000003D4
-		X"035BD02B", -- 000003D8
-		X"241AFFFA", -- 000003DC
-		X"241B0005", -- 000003E0
-		X"035BD02B", -- 000003E4
-		X"241AFFFA", -- 000003E8
-		X"241BFFFB", -- 000003EC
-		X"035BD02B", -- 000003F0
-		X"241A0005", -- 000003F4
-		X"241B0006", -- 000003F8
-		X"035BD02A", -- 000003FC
-		X"241A0005", -- 00000400
-		X"241BFFFA", -- 00000404
-		X"035BD02A", -- 00000408
-		X"241AFFFB", -- 0000040C
-		X"241B0006", -- 00000410
-		X"035BD02A", -- 00000414
-		X"241AFFFB", -- 00000418
-		X"241BFFFA", -- 0000041C
-		X"035BD02A", -- 00000420
-		X"241A0006", -- 00000424
-		X"241B0005", -- 00000428
-		X"035BD02A", -- 0000042C
-		X"241A0006", -- 00000430
-		X"241BFFFB", -- 00000434
-		X"035BD02A", -- 00000438
-		X"241AFFFA", -- 0000043C
-		X"241B0005", -- 00000440
-		X"035BD02A", -- 00000444
-		X"241AFFFA", -- 00000448
-		X"241BFFFB", -- 0000044C
-		X"035BD02A", -- 00000450
-		X"3C1ABFC0", -- 00000454
-		X"275A0F2C", -- 00000458
-		X"0340F809", -- 0000045C
-		X"00000000", -- 00000460
-		X"0BF00118", -- 00000464
-		X"00000000", -- 00000468
-		X"27BDFFF0", -- 0000046C
-		X"AFBE000C", -- 00000470
-		X"03A0F021", -- 00000474
-		X"40026000", -- 00000478
-		X"03C0E821", -- 0000047C
-		X"8FBE000C", -- 00000480
-		X"03E00008", -- 00000484
-		X"27BD0010", -- 00000488
-		X"27BDFFF0", -- 0000048C
-		X"AFBE000C", -- 00000490
-		X"03A0F021", -- 00000494
-		X"40027800", -- 00000498
-		X"03C0E821", -- 0000049C
-		X"8FBE000C", -- 000004A0
-		X"03E00008", -- 000004A4
-		X"27BD0010", -- 000004A8
-		X"27BDFFF0", -- 000004AC
-		X"AFBE000C", -- 000004B0
-		X"03A0F021", -- 000004B4
-		X"3C02A001", -- 000004B8
-		X"34420004", -- 000004BC
-		X"AFC20004", -- 000004C0
-		X"3C02A001", -- 000004C4
-		X"AFC20000", -- 000004C8
-		X"8FC20004", -- 000004CC
-		X"00000000", -- 000004D0
-		X"8C420000", -- 000004D4
-		X"00000000", -- 000004D8
-		X"30420010", -- 000004DC
-		X"1040FFFA", -- 000004E0
-		X"00000000", -- 000004E4
-		X"8FC20000", -- 000004E8
-		X"00000000", -- 000004EC
-		X"8C420000", -- 000004F0
-		X"00000000", -- 000004F4
-		X"00021600", -- 000004F8
-		X"00021603", -- 000004FC
-		X"03C0E821", -- 00000500
-		X"8FBE000C", -- 00000504
-		X"27BD0010", -- 00000508
-		X"03E00008", -- 0000050C
-		X"00000000", -- 00000510
-		X"27BDFFE8", -- 00000514
-		X"AFBE0014", -- 00000518
-		X"03A0F021", -- 0000051C
-		X"00801021", -- 00000520
-		X"A3C20008", -- 00000524
-		X"3C02A001", -- 00000528
-		X"34420004", -- 0000052C
-		X"AFC20004", -- 00000530
-		X"3C02A001", -- 00000534
-		X"AFC20000", -- 00000538
-		X"8FC20004", -- 0000053C
-		X"00000000", -- 00000540
-		X"8C420000", -- 00000544
-		X"00000000", -- 00000548
-		X"30420002", -- 0000054C
-		X"1440FFFA", -- 00000550
-		X"00000000", -- 00000554
-		X"83C30008", -- 00000558
-		X"8FC20000", -- 0000055C
-		X"00000000", -- 00000560
-		X"AC430000", -- 00000564
-		X"03C0E821", -- 00000568
-		X"8FBE0014", -- 0000056C
-		X"27BD0018", -- 00000570
-		X"03E00008", -- 00000574
-		X"00000000", -- 00000578
-		X"27BDFFF0", -- 0000057C
-		X"AFBF000C", -- 00000580
-		X"AFBE0008", -- 00000584
-		X"03A0F021", -- 00000588
-		X"00801021", -- 0000058C
-		X"A3C20000", -- 00000590
-		X"83C30000", -- 00000594
-		X"2402000A", -- 00000598
-		X"1462000B", -- 0000059C
-		X"00000000", -- 000005A0
-		X"2404000D", -- 000005A4
-		X"0FF00145", -- 000005A8
-		X"00000000", -- 000005AC
-		X"83C20000", -- 000005B0
-		X"00000000", -- 000005B4
-		X"00402021", -- 000005B8
-		X"0FF00145", -- 000005BC
-		X"00000000", -- 000005C0
-		X"0BF00178", -- 000005C4
-		X"00000000", -- 000005C8
-		X"83C20000", -- 000005CC
-		X"00000000", -- 000005D0
-		X"00402021", -- 000005D4
-		X"0FF00145", -- 000005D8
-		X"00000000", -- 000005DC
-		X"03C0E821", -- 000005E0
-		X"8FBF000C", -- 000005E4
-		X"8FBE0008", -- 000005E8
-		X"27BD0010", -- 000005EC
-		X"03E00008", -- 000005F0
-		X"00000000", -- 000005F4
-		X"27BDFFE8", -- 000005F8
-		X"AFBF0014", -- 000005FC
-		X"AFBE0010", -- 00000600
-		X"03A0F021", -- 00000604
-		X"AFC40008", -- 00000608
-		X"8FC20008", -- 0000060C
-		X"00000000", -- 00000610
-		X"AFC20000", -- 00000614
-		X"0BF00194", -- 00000618
-		X"00000000", -- 0000061C
-		X"8FC20008", -- 00000620
-		X"00000000", -- 00000624
-		X"80420000", -- 00000628
-		X"00000000", -- 0000062C
-		X"00401821", -- 00000630
-		X"8FC20008", -- 00000634
-		X"00000000", -- 00000638
-		X"24420001", -- 0000063C
-		X"AFC20008", -- 00000640
-		X"00602021", -- 00000644
-		X"0FF0015F", -- 00000648
-		X"00000000", -- 0000064C
-		X"8FC20008", -- 00000650
-		X"00000000", -- 00000654
-		X"80420000", -- 00000658
-		X"00000000", -- 0000065C
-		X"1440FFEF", -- 00000660
-		X"00000000", -- 00000664
-		X"8FC30008", -- 00000668
-		X"8FC20000", -- 0000066C
-		X"00000000", -- 00000670
-		X"00621023", -- 00000674
-		X"03C0E821", -- 00000678
-		X"8FBF0014", -- 0000067C
-		X"8FBE0010", -- 00000680
-		X"27BD0018", -- 00000684
-		X"03E00008", -- 00000688
-		X"00000000", -- 0000068C
-		X"27BDFFE8", -- 00000690
-		X"AFBF0014", -- 00000694
-		X"AFBE0010", -- 00000698
-		X"03A0F021", -- 0000069C
-		X"00801021", -- 000006A0
-		X"A3C20008", -- 000006A4
-		X"AFC00004", -- 000006A8
-		X"0BF001CD", -- 000006AC
-		X"00000000", -- 000006B0
-		X"93C20008", -- 000006B4
-		X"00000000", -- 000006B8
-		X"00021102", -- 000006BC
-		X"A3C20000", -- 000006C0
-		X"83C20008", -- 000006C4
-		X"00000000", -- 000006C8
-		X"00021100", -- 000006CC
-		X"A3C20008", -- 000006D0
-		X"93C20000", -- 000006D4
-		X"00000000", -- 000006D8
-		X"2C42000A", -- 000006DC
-		X"10400007", -- 000006E0
-		X"00000000", -- 000006E4
-		X"93C20000", -- 000006E8
-		X"00000000", -- 000006EC
-		X"24420030", -- 000006F0
-		X"A3C20001", -- 000006F4
-		X"0BF001C4", -- 000006F8
-		X"00000000", -- 000006FC
-		X"93C20000", -- 00000700
-		X"00000000", -- 00000704
-		X"24420037", -- 00000708
-		X"A3C20001", -- 0000070C
-		X"83C20001", -- 00000710
-		X"00000000", -- 00000714
-		X"00402021", -- 00000718
-		X"0FF00145", -- 0000071C
-		X"00000000", -- 00000720
-		X"8FC20004", -- 00000724
-		X"00000000", -- 00000728
-		X"24420001", -- 0000072C
-		X"AFC20004", -- 00000730
-		X"8FC20004", -- 00000734
-		X"00000000", -- 00000738
-		X"28420002", -- 0000073C
-		X"1440FFDC", -- 00000740
-		X"00000000", -- 00000744
-		X"03C0E821", -- 00000748
-		X"8FBF0014", -- 0000074C
-		X"8FBE0010", -- 00000750
-		X"27BD0018", -- 00000754
-		X"03E00008", -- 00000758
-		X"00000000", -- 0000075C
-		X"27BDFFE8", -- 00000760
-		X"AFBF0014", -- 00000764
-		X"AFBE0010", -- 00000768
-		X"03A0F021", -- 0000076C
-		X"AFC40008", -- 00000770
-		X"AFC00004", -- 00000774
-		X"0BF001F1", -- 00000778
-		X"00000000", -- 0000077C
-		X"8FC20008", -- 00000780
-		X"00000000", -- 00000784
-		X"00021603", -- 00000788
-		X"A3C20001", -- 0000078C
-		X"83C20001", -- 00000790
-		X"00000000", -- 00000794
-		X"00402021", -- 00000798
-		X"0FF001A4", -- 0000079C
-		X"00000000", -- 000007A0
-		X"8FC20008", -- 000007A4
-		X"00000000", -- 000007A8
-		X"00021200", -- 000007AC
-		X"AFC20008", -- 000007B0
-		X"8FC20004", -- 000007B4
-		X"00000000", -- 000007B8
-		X"24420001", -- 000007BC
-		X"AFC20004", -- 000007C0
-		X"8FC20004", -- 000007C4
-		X"00000000", -- 000007C8
-		X"28420004", -- 000007CC
-		X"1440FFEB", -- 000007D0
-		X"00000000", -- 000007D4
-		X"03C0E821", -- 000007D8
-		X"8FBF0014", -- 000007DC
-		X"8FBE0010", -- 000007E0
-		X"27BD0018", -- 000007E4
-		X"03E00008", -- 000007E8
-		X"00000000", -- 000007EC
-		X"27BDFFE8", -- 000007F0
-		X"AFBE0014", -- 000007F4
-		X"03A0F021", -- 000007F8
-		X"AFC40008", -- 000007FC
-		X"A3C00000", -- 00000800
-		X"AFC00004", -- 00000804
-		X"0BF00229", -- 00000808
-		X"00000000", -- 0000080C
-		X"8FC30004", -- 00000810
-		X"8FC20008", -- 00000814
-		X"00000000", -- 00000818
-		X"00431021", -- 0000081C
-		X"90420000", -- 00000820
-		X"00000000", -- 00000824
-		X"A3C20001", -- 00000828
-		X"93C20001", -- 0000082C
-		X"00000000", -- 00000830
-		X"2C420041", -- 00000834
-		X"14400007", -- 00000838
-		X"00000000", -- 0000083C
-		X"93C20001", -- 00000840
-		X"00000000", -- 00000844
-		X"2442FFC9", -- 00000848
-		X"A3C20001", -- 0000084C
-		X"0BF0021A", -- 00000850
-		X"00000000", -- 00000854
-		X"93C20001", -- 00000858
-		X"00000000", -- 0000085C
-		X"2442FFD0", -- 00000860
-		X"A3C20001", -- 00000864
-		X"93C20000", -- 00000868
-		X"00000000", -- 0000086C
-		X"00021100", -- 00000870
-		X"00021E00", -- 00000874
-		X"00031E03", -- 00000878
-		X"83C20001", -- 0000087C
-		X"00000000", -- 00000880
-		X"00621025", -- 00000884
-		X"00021600", -- 00000888
-		X"00021603", -- 0000088C
-		X"A3C20000", -- 00000890
-		X"8FC20004", -- 00000894
-		X"00000000", -- 00000898
-		X"24420001", -- 0000089C
-		X"AFC20004", -- 000008A0
-		X"8FC20004", -- 000008A4
-		X"00000000", -- 000008A8
-		X"28420002", -- 000008AC
-		X"1440FFD7", -- 000008B0
-		X"00000000", -- 000008B4
-		X"93C20000", -- 000008B8
-		X"03C0E821", -- 000008BC
-		X"8FBE0014", -- 000008C0
-		X"27BD0018", -- 000008C4
-		X"03E00008", -- 000008C8
-		X"00000000", -- 000008CC
-		X"27BDFFD8", -- 000008D0
-		X"AFBF0024", -- 000008D4
-		X"AFBE0020", -- 000008D8
-		X"03A0F021", -- 000008DC
-		X"AFC40010", -- 000008E0
-		X"AFC50014", -- 000008E4
-		X"AFC60018", -- 000008E8
-		X"8FC20018", -- 000008EC
-		X"00000000", -- 000008F0
-		X"14400004", -- 000008F4
-		X"00000000", -- 000008F8
-		X"AFC0001C", -- 000008FC
-		X"0BF00321", -- 00000900
-		X"00000000", -- 00000904
-		X"8FC30010", -- 00000908
-		X"24020003", -- 0000090C
-		X"AC620008", -- 00000910
-		X"AFC00004", -- 00000914
-		X"8FC20014", -- 00000918
-		X"00000000", -- 0000091C
-		X"24420001", -- 00000920
-		X"90420000", -- 00000924
-		X"00000000", -- 00000928
-		X"2C420031", -- 0000092C
-		X"14400015", -- 00000930
-		X"00000000", -- 00000934
-		X"8FC20014", -- 00000938
-		X"00000000", -- 0000093C
-		X"24420001", -- 00000940
-		X"90420000", -- 00000944
-		X"00000000", -- 00000948
-		X"2C420034", -- 0000094C
-		X"1040000D", -- 00000950
-		X"00000000", -- 00000954
-		X"8FC20014", -- 00000958
-		X"00000000", -- 0000095C
-		X"24420001", -- 00000960
-		X"90420000", -- 00000964
-		X"00000000", -- 00000968
-		X"2442FFD1", -- 0000096C
-		X"AFC20004", -- 00000970
-		X"8FC30010", -- 00000974
-		X"24020002", -- 00000978
-		X"AC620008", -- 0000097C
-		X"0BF0028C", -- 00000980
-		X"00000000", -- 00000984
-		X"8FC20014", -- 00000988
-		X"00000000", -- 0000098C
-		X"24420001", -- 00000990
-		X"90420000", -- 00000994
-		X"00000000", -- 00000998
-		X"2C420037", -- 0000099C
-		X"14400017", -- 000009A0
-		X"00000000", -- 000009A4
-		X"8FC20014", -- 000009A8
-		X"00000000", -- 000009AC
-		X"24420001", -- 000009B0
-		X"90420000", -- 000009B4
-		X"00000000", -- 000009B8
-		X"2C42003A", -- 000009BC
-		X"1040000F", -- 000009C0
-		X"00000000", -- 000009C4
-		X"8FC20014", -- 000009C8
-		X"00000000", -- 000009CC
-		X"24420001", -- 000009D0
-		X"90420000", -- 000009D4
-		X"00000000", -- 000009D8
-		X"00401821", -- 000009DC
-		X"2402003B", -- 000009E0
-		X"00431023", -- 000009E4
-		X"AFC20004", -- 000009E8
-		X"8FC30010", -- 000009EC
-		X"24020004", -- 000009F0
-		X"AC620008", -- 000009F4
-		X"0BF0028C", -- 000009F8
-		X"00000000", -- 000009FC
-		X"8FC20014", -- 00000A00
-		X"00000000", -- 00000A04
-		X"24420001", -- 00000A08
-		X"90430000", -- 00000A0C
-		X"24020030", -- 00000A10
-		X"14620006", -- 00000A14
-		X"00000000", -- 00000A18
-		X"24020002", -- 00000A1C
-		X"AFC20004", -- 00000A20
-		X"8FC30010", -- 00000A24
-		X"24020001", -- 00000A28
-		X"AC620008", -- 00000A2C
-		X"8FC20014", -- 00000A30
-		X"00000000", -- 00000A34
-		X"24420002", -- 00000A38
-		X"00402021", -- 00000A3C
-		X"0FF001FC", -- 00000A40
-		X"00000000", -- 00000A44
-		X"A3C20008", -- 00000A48
-		X"93C30008", -- 00000A4C
-		X"8FC20010", -- 00000A50
-		X"00000000", -- 00000A54
-		X"AC430004", -- 00000A58
-		X"93C20008", -- 00000A5C
-		X"00000000", -- 00000A60
-		X"A3C20009", -- 00000A64
-		X"8FC20010", -- 00000A68
-		X"00000000", -- 00000A6C
-		X"AC400000", -- 00000A70
-		X"AFC00000", -- 00000A74
-		X"0BF002C0", -- 00000A78
-		X"00000000", -- 00000A7C
-		X"8FC20000", -- 00000A80
-		X"00000000", -- 00000A84
-		X"24420002", -- 00000A88
-		X"00021040", -- 00000A8C
-		X"00401821", -- 00000A90
-		X"8FC20014", -- 00000A94
-		X"00000000", -- 00000A98
-		X"00431021", -- 00000A9C
-		X"00402021", -- 00000AA0
-		X"0FF001FC", -- 00000AA4
-		X"00000000", -- 00000AA8
-		X"A3C20008", -- 00000AAC
-		X"8FC20010", -- 00000AB0
-		X"00000000", -- 00000AB4
-		X"8C420000", -- 00000AB8
-		X"00000000", -- 00000ABC
-		X"00021A00", -- 00000AC0
-		X"93C20008", -- 00000AC4
-		X"00000000", -- 00000AC8
-		X"00621825", -- 00000ACC
-		X"8FC20010", -- 00000AD0
-		X"00000000", -- 00000AD4
-		X"AC430000", -- 00000AD8
-		X"93C30009", -- 00000ADC
-		X"93C20008", -- 00000AE0
-		X"00000000", -- 00000AE4
-		X"00621021", -- 00000AE8
-		X"A3C20009", -- 00000AEC
-		X"8FC20000", -- 00000AF0
-		X"00000000", -- 00000AF4
-		X"24420001", -- 00000AF8
-		X"AFC20000", -- 00000AFC
-		X"8FC20000", -- 00000B00
-		X"8FC30004", -- 00000B04
-		X"00000000", -- 00000B08
-		X"0043102A", -- 00000B0C
-		X"1440FFDB", -- 00000B10
-		X"00000000", -- 00000B14
-		X"8FC20010", -- 00000B18
-		X"00000000", -- 00000B1C
-		X"8C430004", -- 00000B20
-		X"8FC20004", -- 00000B24
-		X"00000000", -- 00000B28
-		X"00021027", -- 00000B2C
-		X"00621821", -- 00000B30
-		X"8FC20010", -- 00000B34
-		X"00000000", -- 00000B38
-		X"AC430004", -- 00000B3C
-		X"8FC20004", -- 00000B40
-		X"00000000", -- 00000B44
-		X"24420002", -- 00000B48
-		X"00021040", -- 00000B4C
-		X"00401821", -- 00000B50
-		X"8FC20014", -- 00000B54
-		X"00000000", -- 00000B58
-		X"00431821", -- 00000B5C
-		X"8FC20010", -- 00000B60
-		X"00000000", -- 00000B64
-		X"AC43000C", -- 00000B68
-		X"AFC00000", -- 00000B6C
-		X"0BF002FB", -- 00000B70
-		X"00000000", -- 00000B74
-		X"8FC20010", -- 00000B78
-		X"00000000", -- 00000B7C
-		X"8C43000C", -- 00000B80
-		X"8FC20000", -- 00000B84
-		X"00000000", -- 00000B88
-		X"00021040", -- 00000B8C
-		X"00621021", -- 00000B90
-		X"00402021", -- 00000B94
-		X"0FF001FC", -- 00000B98
-		X"00000000", -- 00000B9C
-		X"A3C20008", -- 00000BA0
-		X"8FC20010", -- 00000BA4
-		X"00000000", -- 00000BA8
-		X"8C43000C", -- 00000BAC
-		X"8FC20000", -- 00000BB0
-		X"00000000", -- 00000BB4
-		X"00621821", -- 00000BB8
-		X"93C20008", -- 00000BBC
-		X"00000000", -- 00000BC0
-		X"A0620000", -- 00000BC4
-		X"93C30009", -- 00000BC8
-		X"93C20008", -- 00000BCC
-		X"00000000", -- 00000BD0
-		X"00621021", -- 00000BD4
-		X"A3C20009", -- 00000BD8
-		X"8FC20000", -- 00000BDC
-		X"00000000", -- 00000BE0
-		X"24420001", -- 00000BE4
-		X"AFC20000", -- 00000BE8
-		X"8FC20010", -- 00000BEC
-		X"00000000", -- 00000BF0
-		X"8C420004", -- 00000BF4
-		X"00000000", -- 00000BF8
-		X"00401821", -- 00000BFC
-		X"8FC20000", -- 00000C00
-		X"00000000", -- 00000C04
-		X"0043102A", -- 00000C08
-		X"1440FFDA", -- 00000C0C
-		X"00000000", -- 00000C10
-		X"93C20009", -- 00000C14
-		X"00000000", -- 00000C18
-		X"00021027", -- 00000C1C
-		X"A3C20009", -- 00000C20
-		X"8FC20010", -- 00000C24
-		X"00000000", -- 00000C28
-		X"8C43000C", -- 00000C2C
-		X"8FC20000", -- 00000C30
-		X"00000000", -- 00000C34
-		X"00021040", -- 00000C38
-		X"00621021", -- 00000C3C
-		X"00402021", -- 00000C40
-		X"0FF001FC", -- 00000C44
-		X"00000000", -- 00000C48
-		X"A3C20008", -- 00000C4C
-		X"93C30009", -- 00000C50
-		X"93C20008", -- 00000C54
-		X"00000000", -- 00000C58
-		X"10620004", -- 00000C5C
-		X"00000000", -- 00000C60
-		X"AFC0001C", -- 00000C64
-		X"0BF00321", -- 00000C68
-		X"00000000", -- 00000C6C
-		X"8FC20010", -- 00000C70
-		X"00000000", -- 00000C74
-		X"8C420008", -- 00000C78
-		X"00000000", -- 00000C7C
-		X"AFC2001C", -- 00000C80
-		X"8FC2001C", -- 00000C84
-		X"03C0E821", -- 00000C88
-		X"8FBF0024", -- 00000C8C
-		X"8FBE0020", -- 00000C90
-		X"27BD0028", -- 00000C94
-		X"03E00008", -- 00000C98
-		X"00000000", -- 00000C9C
-		X"27BDFFE8", -- 00000CA0
-		X"AFBF0014", -- 00000CA4
-		X"AFBE0010", -- 00000CA8
-		X"03A0F021", -- 00000CAC
-		X"AFC40008", -- 00000CB0
-		X"AFC00000", -- 00000CB4
-		X"0FF0012B", -- 00000CB8
-		X"00000000", -- 00000CBC
-		X"A3C20004", -- 00000CC0
-		X"83C30004", -- 00000CC4
-		X"24020073", -- 00000CC8
-		X"10620015", -- 00000CCC
-		X"00000000", -- 00000CD0
-		X"83C30004", -- 00000CD4
-		X"24020053", -- 00000CD8
-		X"1462FFF6", -- 00000CDC
-		X"00000000", -- 00000CE0
-		X"0BF00349", -- 00000CE4
-		X"00000000", -- 00000CE8
-		X"8FC30000", -- 00000CEC
-		X"8FC20008", -- 00000CF0
-		X"00000000", -- 00000CF4
-		X"00431821", -- 00000CF8
-		X"93C20004", -- 00000CFC
-		X"00000000", -- 00000D00
-		X"A0620000", -- 00000D04
-		X"8FC20000", -- 00000D08
-		X"00000000", -- 00000D0C
-		X"24420001", -- 00000D10
-		X"AFC20000", -- 00000D14
-		X"0FF0012B", -- 00000D18
-		X"00000000", -- 00000D1C
-		X"A3C20004", -- 00000D20
-		X"83C30004", -- 00000D24
-		X"2402000D", -- 00000D28
-		X"10620005", -- 00000D2C
-		X"00000000", -- 00000D30
-		X"83C30004", -- 00000D34
-		X"2402000A", -- 00000D38
-		X"1462FFEB", -- 00000D3C
-		X"00000000", -- 00000D40
-		X"8FC20000", -- 00000D44
-		X"03C0E821", -- 00000D48
-		X"8FBF0014", -- 00000D4C
-		X"8FBE0010", -- 00000D50
-		X"27BD0018", -- 00000D54
-		X"03E00008", -- 00000D58
-		X"00000000", -- 00000D5C
-		X"27BDFFF0", -- 00000D60
-		X"AFBE000C", -- 00000D64
-		X"03A0F021", -- 00000D68
-		X"AFC40000", -- 00000D6C
-		X"401A6000", -- 00000D70
-		X"3C1BFFBF", -- 00000D74
-		X"377BFFFF", -- 00000D78
-		X"035BD024", -- 00000D7C
-		X"409A6000", -- 00000D80
-		X"00800008", -- 00000D84
-		X"42000010", -- 00000D88
-		X"03C0E821", -- 00000D8C
-		X"8FBE000C", -- 00000D90
-		X"03E00008", -- 00000D94
-		X"27BD0010", -- 00000D98
-		X"27BDFFD0", -- 00000D9C
-		X"AFBF002C", -- 00000DA0
-		X"AFBE0028", -- 00000DA4
-		X"03A0F021", -- 00000DA8
-		X"3C02BFC0", -- 00000DAC
-		X"244215D0", -- 00000DB0
-		X"AFC20008", -- 00000DB4
-		X"3C02BFC0", -- 00000DB8
-		X"244215D8", -- 00000DBC
-		X"AFC2000C", -- 00000DC0
-		X"3C02BFC0", -- 00000DC4
-		X"244215E0", -- 00000DC8
-		X"AFC20010", -- 00000DCC
-		X"3C02BFC0", -- 00000DD0
-		X"244215E8", -- 00000DD4
-		X"AFC20014", -- 00000DD8
-		X"3C02BFC0", -- 00000DDC
-		X"244215F0", -- 00000DE0
-		X"AFC20018", -- 00000DE4
-		X"3C02BFC0", -- 00000DE8
-		X"244215F8", -- 00000DEC
-		X"AFC2001C", -- 00000DF0
-		X"3C02BFC0", -- 00000DF4
-		X"24421604", -- 00000DF8
-		X"AFC20020", -- 00000DFC
-		X"0FF0011B", -- 00000E00
-		X"00000000", -- 00000E04
-		X"AFC20004", -- 00000E08
-		X"3C02BFC0", -- 00000E0C
-		X"2444160C", -- 00000E10
-		X"0FF0017E", -- 00000E14
-		X"00000000", -- 00000E18
-		X"8FC40004", -- 00000E1C
-		X"0FF001D8", -- 00000E20
-		X"00000000", -- 00000E24
-		X"3C02BFC0", -- 00000E28
-		X"24441618", -- 00000E2C
-		X"0FF0017E", -- 00000E30
-		X"00000000", -- 00000E34
-		X"0FF00123", -- 00000E38
-		X"00000000", -- 00000E3C
-		X"AFC20004", -- 00000E40
-		X"8FC20004", -- 00000E44
-		X"00000000", -- 00000E48
-		X"00021203", -- 00000E4C
-		X"304200FF", -- 00000E50
-		X"AFC20000", -- 00000E54
-		X"3C02BFC0", -- 00000E58
-		X"2444161C", -- 00000E5C
-		X"0FF0017E", -- 00000E60
-		X"00000000", -- 00000E64
-		X"8FC20000", -- 00000E68
-		X"00000000", -- 00000E6C
-		X"18400020", -- 00000E70
-		X"00000000", -- 00000E74
-		X"8FC20000", -- 00000E78
-		X"00000000", -- 00000E7C
-		X"28420007", -- 00000E80
-		X"1040001B", -- 00000E84
-		X"00000000", -- 00000E88
-		X"8FC20000", -- 00000E8C
-		X"00000000", -- 00000E90
-		X"00021080", -- 00000E94
-		X"03C21021", -- 00000E98
-		X"8C420008", -- 00000E9C
-		X"00000000", -- 00000EA0
-		X"00402021", -- 00000EA4
-		X"0FF0017E", -- 00000EA8
-		X"00000000", -- 00000EAC
-		X"3C02BFC0", -- 00000EB0
-		X"24441628", -- 00000EB4
-		X"0FF0017E", -- 00000EB8
-		X"00000000", -- 00000EBC
-		X"8FC20004", -- 00000EC0
-		X"00000000", -- 00000EC4
-		X"304200FF", -- 00000EC8
-		X"AFC20000", -- 00000ECC
-		X"8FC20000", -- 00000ED0
-		X"00000000", -- 00000ED4
-		X"00021600", -- 00000ED8
-		X"00021603", -- 00000EDC
-		X"00402021", -- 00000EE0
-		X"0FF001A4", -- 00000EE4
-		X"00000000", -- 00000EE8
-		X"0BF003C1", -- 00000EEC
-		X"00000000", -- 00000EF0
-		X"3C02BFC0", -- 00000EF4
-		X"24441630", -- 00000EF8
-		X"0FF0017E", -- 00000EFC
-		X"00000000", -- 00000F00
-		X"3C02BFC0", -- 00000F04
-		X"24441618", -- 00000F08
-		X"0FF0017E", -- 00000F0C
-		X"00000000", -- 00000F10
-		X"03C0E821", -- 00000F14
-		X"8FBF002C", -- 00000F18
-		X"8FBE0028", -- 00000F1C
-		X"27BD0030", -- 00000F20
-		X"03E00008", -- 00000F24
-		X"00000000", -- 00000F28
-		X"27BDFEA8", -- 00000F2C
-		X"AFBF0154", -- 00000F30
-		X"AFBE0150", -- 00000F34
-		X"03A0F021", -- 00000F38
-		X"AFC40140", -- 00000F3C
-		X"AFC50144", -- 00000F40
-		X"3C02A000", -- 00000F44
-		X"AFC20020", -- 00000F48
-		X"3C02A400", -- 00000F4C
-		X"AFC20010", -- 00000F50
-		X"3C02A002", -- 00000F54
-		X"AFC2000C", -- 00000F58
-		X"3C024000", -- 00000F5C
-		X"AFC20008", -- 00000F60
-		X"3C024000", -- 00000F64
-		X"AFC20004", -- 00000F68
-		X"3C024000", -- 00000F6C
-		X"AFC20000", -- 00000F70
-		X"8FC20020", -- 00000F74
-		X"00000000", -- 00000F78
-		X"AC400000", -- 00000F7C
-		X"AFC00024", -- 00000F80
-		X"3C02BFC0", -- 00000F84
-		X"24441638", -- 00000F88
-		X"0FF0017E", -- 00000F8C
-		X"00000000", -- 00000F90
-		X"3C024000", -- 00000F94
-		X"AFC20014", -- 00000F98
-		X"AFC00018", -- 00000F9C
-		X"AFC00028", -- 00000FA0
-		X"0BF003FD", -- 00000FA4
-		X"00000000", -- 00000FA8
-		X"8FC20018", -- 00000FAC
-		X"00000000", -- 00000FB0
-		X"8C430000", -- 00000FB4
-		X"8FC20014", -- 00000FB8
-		X"00000000", -- 00000FBC
-		X"AC430000", -- 00000FC0
-		X"8FC20014", -- 00000FC4
-		X"00000000", -- 00000FC8
-		X"24420004", -- 00000FCC
-		X"AFC20014", -- 00000FD0
-		X"8FC20018", -- 00000FD4
-		X"00000000", -- 00000FD8
-		X"24420004", -- 00000FDC
-		X"AFC20018", -- 00000FE0
-		X"8FC20028", -- 00000FE4
-		X"00000000", -- 00000FE8
-		X"24420004", -- 00000FEC
-		X"AFC20028", -- 00000FF0
-		X"8FC20028", -- 00000FF4
-		X"00000000", -- 00000FF8
-		X"28423500", -- 00000FFC
-		X"1440FFEA", -- 00001000
-		X"00000000", -- 00001004
-		X"3C044000", -- 00001008
-		X"0FF00358", -- 0000100C
-		X"00000000", -- 00001010
-		X"3C02BFC0", -- 00001014
-		X"24441640", -- 00001018
-		X"0FF0017E", -- 0000101C
-		X"00000000", -- 00001020
-		X"3C02BFC0", -- 00001024
-		X"24441654", -- 00001028
-		X"0FF0017E", -- 0000102C
-		X"00000000", -- 00001030
-		X"AFC00028", -- 00001034
-		X"0BF0041C", -- 00001038
-		X"00000000", -- 0000103C
-		X"8FC30028", -- 00001040
-		X"8FC20008", -- 00001044
-		X"00000000", -- 00001048
-		X"00431821", -- 0000104C
-		X"8FC20028", -- 00001050
-		X"00000000", -- 00001054
-		X"304200FF", -- 00001058
-		X"A0620000", -- 0000105C
-		X"8FC20028", -- 00001060
-		X"00000000", -- 00001064
-		X"24420001", -- 00001068
-		X"AFC20028", -- 0000106C
-		X"8FC20028", -- 00001070
-		X"3C030010", -- 00001074
-		X"0043102A", -- 00001078
-		X"1440FFF0", -- 0000107C
-		X"00000000", -- 00001080
-		X"3C02BFC0", -- 00001084
-		X"2444166C", -- 00001088
-		X"0FF0017E", -- 0000108C
-		X"00000000", -- 00001090
-		X"3C02BFC0", -- 00001094
-		X"24441674", -- 00001098
-		X"0FF0017E", -- 0000109C
-		X"00000000", -- 000010A0
-		X"3C02000F", -- 000010A4
-		X"3442FFFF", -- 000010A8
-		X"AFC20028", -- 000010AC
-		X"0BF0043E", -- 000010B0
-		X"00000000", -- 000010B4
-		X"8FC30028", -- 000010B8
-		X"8FC20008", -- 000010BC
-		X"00000000", -- 000010C0
-		X"00431021", -- 000010C4
-		X"90420000", -- 000010C8
-		X"00000000", -- 000010CC
-		X"304300FF", -- 000010D0
-		X"8FC20028", -- 000010D4
-		X"00000000", -- 000010D8
-		X"304200FF", -- 000010DC
-		X"14620009", -- 000010E0
-		X"00000000", -- 000010E4
-		X"8FC20028", -- 000010E8
-		X"00000000", -- 000010EC
-		X"2442FFFF", -- 000010F0
-		X"AFC20028", -- 000010F4
-		X"8FC20028", -- 000010F8
-		X"00000000", -- 000010FC
-		X"0441FFED", -- 00001100
-		X"00000000", -- 00001104
-		X"8FC20028", -- 00001108
-		X"00000000", -- 0000110C
-		X"24420001", -- 00001110
-		X"AFC20028", -- 00001114
-		X"8FC20028", -- 00001118
-		X"00000000", -- 0000111C
-		X"10400007", -- 00001120
-		X"00000000", -- 00001124
-		X"3C02BFC0", -- 00001128
-		X"24441690", -- 0000112C
-		X"0FF0017E", -- 00001130
-		X"00000000", -- 00001134
-		X"0BF00454", -- 00001138
-		X"00000000", -- 0000113C
-		X"3C02BFC0", -- 00001140
-		X"2444169C", -- 00001144
-		X"0FF0017E", -- 00001148
-		X"00000000", -- 0000114C
-		X"3C02BFC0", -- 00001150
-		X"244416A8", -- 00001154
-		X"0FF0017E", -- 00001158
-		X"00000000", -- 0000115C
-		X"AFC00028", -- 00001160
-		X"0BF00469", -- 00001164
-		X"00000000", -- 00001168
-		X"8FC20028", -- 0000116C
-		X"00000000", -- 00001170
-		X"00021840", -- 00001174
-		X"8FC20004", -- 00001178
-		X"00000000", -- 0000117C
-		X"00431821", -- 00001180
-		X"8FC20028", -- 00001184
-		X"00000000", -- 00001188
-		X"3042FFFF", -- 0000118C
-		X"A4620000", -- 00001190
-		X"8FC20028", -- 00001194
-		X"00000000", -- 00001198
-		X"24420001", -- 0000119C
-		X"AFC20028", -- 000011A0
-		X"8FC20028", -- 000011A4
-		X"3C030008", -- 000011A8
-		X"0043102A", -- 000011AC
-		X"1440FFEE", -- 000011B0
-		X"00000000", -- 000011B4
-		X"3C02BFC0", -- 000011B8
-		X"2444166C", -- 000011BC
-		X"0FF0017E", -- 000011C0
-		X"00000000", -- 000011C4
-		X"3C02BFC0", -- 000011C8
-		X"244416C4", -- 000011CC
-		X"0FF0017E", -- 000011D0
-		X"00000000", -- 000011D4
-		X"3C020007", -- 000011D8
-		X"3442FFFF", -- 000011DC
-		X"AFC20028", -- 000011E0
-		X"0BF0048D", -- 000011E4
-		X"00000000", -- 000011E8
-		X"8FC20028", -- 000011EC
-		X"00000000", -- 000011F0
-		X"00021840", -- 000011F4
-		X"8FC20004", -- 000011F8
-		X"00000000", -- 000011FC
-		X"00431021", -- 00001200
-		X"94420000", -- 00001204
-		X"00000000", -- 00001208
-		X"3043FFFF", -- 0000120C
-		X"8FC20028", -- 00001210
-		X"00000000", -- 00001214
-		X"3042FFFF", -- 00001218
-		X"14620009", -- 0000121C
-		X"00000000", -- 00001220
-		X"8FC20028", -- 00001224
-		X"00000000", -- 00001228
-		X"2442FFFF", -- 0000122C
-		X"AFC20028", -- 00001230
-		X"8FC20028", -- 00001234
-		X"00000000", -- 00001238
-		X"0441FFEB", -- 0000123C
-		X"00000000", -- 00001240
-		X"8FC20028", -- 00001244
-		X"00000000", -- 00001248
-		X"24420001", -- 0000124C
-		X"AFC20028", -- 00001250
-		X"8FC20028", -- 00001254
-		X"00000000", -- 00001258
-		X"10400007", -- 0000125C
-		X"00000000", -- 00001260
-		X"3C02BFC0", -- 00001264
-		X"24441690", -- 00001268
-		X"0FF0017E", -- 0000126C
-		X"00000000", -- 00001270
-		X"0BF004A3", -- 00001274
-		X"00000000", -- 00001278
-		X"3C02BFC0", -- 0000127C
-		X"2444169C", -- 00001280
-		X"0FF0017E", -- 00001284
-		X"00000000", -- 00001288
-		X"3C02BFC0", -- 0000128C
-		X"244416E0", -- 00001290
-		X"0FF0017E", -- 00001294
-		X"00000000", -- 00001298
-		X"AFC00028", -- 0000129C
-		X"0BF004B7", -- 000012A0
-		X"00000000", -- 000012A4
-		X"8FC20028", -- 000012A8
-		X"00000000", -- 000012AC
-		X"00021880", -- 000012B0
-		X"8FC20000", -- 000012B4
-		X"00000000", -- 000012B8
-		X"00431821", -- 000012BC
-		X"8FC20028", -- 000012C0
-		X"00000000", -- 000012C4
-		X"AC620000", -- 000012C8
-		X"8FC20028", -- 000012CC
-		X"00000000", -- 000012D0
-		X"24420001", -- 000012D4
-		X"AFC20028", -- 000012D8
-		X"8FC20028", -- 000012DC
-		X"3C030004", -- 000012E0
-		X"0043102A", -- 000012E4
-		X"1440FFEF", -- 000012E8
-		X"00000000", -- 000012EC
-		X"3C02BFC0", -- 000012F0
-		X"2444166C", -- 000012F4
-		X"0FF0017E", -- 000012F8
-		X"00000000", -- 000012FC
-		X"3C02BFC0", -- 00001300
-		X"244416FC", -- 00001304
-		X"0FF0017E", -- 00001308
-		X"00000000", -- 0000130C
-		X"3C020003", -- 00001310
-		X"3442FFFF", -- 00001314
-		X"AFC20028", -- 00001318
-		X"0BF004D8", -- 0000131C
-		X"00000000", -- 00001320
-		X"8FC20028", -- 00001324
-		X"00000000", -- 00001328
-		X"00021880", -- 0000132C
-		X"8FC20000", -- 00001330
-		X"00000000", -- 00001334
-		X"00431021", -- 00001338
-		X"8C430000", -- 0000133C
-		X"8FC20028", -- 00001340
-		X"00000000", -- 00001344
-		X"14620009", -- 00001348
-		X"00000000", -- 0000134C
-		X"8FC20028", -- 00001350
-		X"00000000", -- 00001354
-		X"2442FFFF", -- 00001358
-		X"AFC20028", -- 0000135C
-		X"8FC20028", -- 00001360
-		X"00000000", -- 00001364
-		X"0441FFEE", -- 00001368
-		X"00000000", -- 0000136C
-		X"8FC20028", -- 00001370
-		X"00000000", -- 00001374
-		X"24420001", -- 00001378
-		X"AFC20028", -- 0000137C
-		X"8FC20028", -- 00001380
-		X"00000000", -- 00001384
-		X"10400007", -- 00001388
-		X"00000000", -- 0000138C
-		X"3C02BFC0", -- 00001390
-		X"24441690", -- 00001394
-		X"0FF0017E", -- 00001398
-		X"00000000", -- 0000139C
-		X"0BF004EE", -- 000013A0
-		X"00000000", -- 000013A4
-		X"3C02BFC0", -- 000013A8
-		X"2444169C", -- 000013AC
-		X"0FF0017E", -- 000013B0
-		X"00000000", -- 000013B4
-		X"AFC00028", -- 000013B8
-		X"0BF004FC", -- 000013BC
-		X"00000000", -- 000013C0
-		X"8FC20028", -- 000013C4
-		X"00000000", -- 000013C8
-		X"00021880", -- 000013CC
-		X"8FC20000", -- 000013D0
-		X"00000000", -- 000013D4
-		X"00431021", -- 000013D8
-		X"AC400000", -- 000013DC
-		X"8FC20028", -- 000013E0
-		X"00000000", -- 000013E4
-		X"24420001", -- 000013E8
-		X"AFC20028", -- 000013EC
-		X"8FC20028", -- 000013F0
-		X"3C030004", -- 000013F4
-		X"0043102A", -- 000013F8
-		X"1440FFF1", -- 000013FC
-		X"00000000", -- 00001400
-		X"3C02BFC0", -- 00001404
-		X"24441638", -- 00001408
-		X"0FF0017E", -- 0000140C
-		X"00000000", -- 00001410
-		X"27C20030", -- 00001414
-		X"00402021", -- 00001418
-		X"0FF00328", -- 0000141C
-		X"00000000", -- 00001420
-		X"AFC2002C", -- 00001424
-		X"27C20130", -- 00001428
-		X"27C30030", -- 0000142C
-		X"00402021", -- 00001430
-		X"00602821", -- 00001434
-		X"8FC6002C", -- 00001438
-		X"0FF00234", -- 0000143C
-		X"00000000", -- 00001440
-		X"AFC2002C", -- 00001444
-		X"8FC20020", -- 00001448
-		X"00000000", -- 0000144C
-		X"AC400000", -- 00001450
-		X"8FC2002C", -- 00001454
-		X"00000000", -- 00001458
-		X"AFC20148", -- 0000145C
-		X"24020002", -- 00001460
-		X"8FC30148", -- 00001464
-		X"00000000", -- 00001468
-		X"10620008", -- 0000146C
-		X"00000000", -- 00001470
-		X"24020004", -- 00001474
-		X"8FC30148", -- 00001478
-		X"00000000", -- 0000147C
-		X"1062002F", -- 00001480
-		X"00000000", -- 00001484
-		X"0BF0056B", -- 00001488
-		X"00000000", -- 0000148C
-		X"8FC30130", -- 00001490
-		X"8FC20134", -- 00001494
-		X"00000000", -- 00001498
-		X"00621821", -- 0000149C
-		X"8FC20024", -- 000014A0
-		X"00000000", -- 000014A4
-		X"0043102B", -- 000014A8
-		X"10400006", -- 000014AC
-		X"00000000", -- 000014B0
-		X"8FC20130", -- 000014B4
-		X"8FC30134", -- 000014B8
-		X"00000000", -- 000014BC
-		X"00431021", -- 000014C0
-		X"AFC20024", -- 000014C4
-		X"8FC20130", -- 000014C8
-		X"00000000", -- 000014CC
-		X"AFC2001C", -- 000014D0
-		X"AFC00028", -- 000014D4
-		X"0BF00548", -- 000014D8
-		X"00000000", -- 000014DC
-		X"8FC3013C", -- 000014E0
-		X"8FC20028", -- 000014E4
-		X"00000000", -- 000014E8
-		X"00621021", -- 000014EC
-		X"90430000", -- 000014F0
-		X"8FC2001C", -- 000014F4
-		X"00000000", -- 000014F8
-		X"A0430000", -- 000014FC
-		X"8FC2001C", -- 00001500
-		X"00000000", -- 00001504
-		X"24420001", -- 00001508
-		X"AFC2001C", -- 0000150C
-		X"8FC20028", -- 00001510
-		X"00000000", -- 00001514
-		X"24420001", -- 00001518
-		X"AFC20028", -- 0000151C
-		X"8FC20028", -- 00001520
-		X"8FC30134", -- 00001524
-		X"00000000", -- 00001528
-		X"0043102B", -- 0000152C
-		X"1440FFEB", -- 00001530
-		X"00000000", -- 00001534
-		X"0BF0056B", -- 00001538
-		X"00000000", -- 0000153C
-		X"8FC30020", -- 00001540
-		X"24020001", -- 00001544
-		X"AC620000", -- 00001548
-		X"8FC20130", -- 0000154C
-		X"00000000", -- 00001550
-		X"00402021", -- 00001554
-		X"0FF001D8", -- 00001558
-		X"00000000", -- 0000155C
-		X"3C02BFC0", -- 00001560
-		X"24441718", -- 00001564
-		X"0FF0017E", -- 00001568
-		X"00000000", -- 0000156C
-		X"8FC20024", -- 00001570
-		X"00000000", -- 00001574
-		X"2442FFFC", -- 00001578
-		X"00402021", -- 0000157C
-		X"0FF001D8", -- 00001580
-		X"00000000", -- 00001584
-		X"3C02BFC0", -- 00001588
-		X"24441720", -- 0000158C
-		X"0FF0017E", -- 00001590
-		X"00000000", -- 00001594
-		X"8FC20130", -- 00001598
-		X"00000000", -- 0000159C
-		X"00402021", -- 000015A0
-		X"0FF00358", -- 000015A4
-		X"00000000", -- 000015A8
-		X"8FC2002C", -- 000015AC
-		X"00000000", -- 000015B0
-		X"1440FF97", -- 000015B4
-		X"00000000", -- 000015B8
-		X"8FC30020", -- 000015BC
-		X"3C024000", -- 000015C0
-		X"AC620000", -- 000015C4
-		X"0BF00501", -- 000015C8
-		X"00000000", -- 000015CC
-		X"61766E69", -- 000015D0
-		X"0064696C", -- 000015D4
-		X"30303252", -- 000015D8
-		X"00000030", -- 000015DC
-		X"30303352", -- 000015E0
-		X"00000030", -- 000015E4
-		X"30303652", -- 000015E8
-		X"00000030", -- 000015EC
-		X"30303452", -- 000015F0
-		X"00000030", -- 000015F4
-		X"65736572", -- 000015F8
-		X"64657672", -- 000015FC
-		X"00000000", -- 00001600
-		X"30303652", -- 00001604
-		X"00004130", -- 00001608
-		X"74617453", -- 0000160C
-		X"20207375", -- 00001610
-		X"0000203A", -- 00001614
-		X"0000000A", -- 00001618
-		X"20555043", -- 0000161C
-		X"65707974", -- 00001620
-		X"0000203A", -- 00001624
-		X"76655220", -- 00001628
-		X"0000002E", -- 0000162C
-		X"6E6B6E55", -- 00001630
-		X"006E776F", -- 00001634
-		X"544F4F42", -- 00001638
-		X"00000020", -- 0000163C
-		X"41524453", -- 00001640
-		X"654D204D", -- 00001644
-		X"79726F6D", -- 00001648
-		X"73655420", -- 0000164C
-		X"000A0D74", -- 00001650
-		X"74697257", -- 00001654
-		X"38282065", -- 00001658
-		X"7469422D", -- 0000165C
-		X"63636120", -- 00001660
-		X"29737365", -- 00001664
-		X"002E2E2E", -- 00001668
-		X"656E6F64", -- 0000166C
-		X"00000A0D", -- 00001670
-		X"69726556", -- 00001674
-		X"28207966", -- 00001678
-		X"69422D38", -- 0000167C
-		X"63612074", -- 00001680
-		X"73736563", -- 00001684
-		X"2E2E2E29", -- 00001688
-		X"00000000", -- 0000168C
-		X"6C696166", -- 00001690
-		X"0A0D6465", -- 00001694
-		X"00000000", -- 00001698
-		X"73736170", -- 0000169C
-		X"0A0D6465", -- 000016A0
-		X"00000000", -- 000016A4
-		X"74697257", -- 000016A8
-		X"31282065", -- 000016AC
-		X"69422D36", -- 000016B0
-		X"63612074", -- 000016B4
-		X"73736563", -- 000016B8
-		X"2E2E2E29", -- 000016BC
-		X"00000000", -- 000016C0
-		X"69726556", -- 000016C4
-		X"28207966", -- 000016C8
-		X"422D3631", -- 000016CC
-		X"61207469", -- 000016D0
-		X"73656363", -- 000016D4
-		X"2E2E2973", -- 000016D8
-		X"0000002E", -- 000016DC
-		X"74697257", -- 000016E0
-		X"33282065", -- 000016E4
-		X"69422D32", -- 000016E8
-		X"63612074", -- 000016EC
-		X"73736563", -- 000016F0
-		X"2E2E2E29", -- 000016F4
-		X"00000000", -- 000016F8
-		X"69726556", -- 000016FC
-		X"28207966", -- 00001700
-		X"422D3233", -- 00001704
-		X"61207469", -- 00001708
-		X"73656363", -- 0000170C
-		X"2E2E2973", -- 00001710
-		X"0000002E", -- 00001714
-		X"206F7420", -- 00001718
-		X"00000000", -- 0000171C
-		X"00000A0D", -- 00001720
-		X"00000000", -- 00001724
-		X"00000000", -- 00001728
-		X"00000000", -- 0000172C
-		X"00000000", -- 00001730
-		X"00000000", -- 00001734
-		X"00000000", -- 00001738
-		X"00000000", -- 0000173C
-		X"00000000", -- 00001740
-		X"00000000", -- 00001744
-		X"00000000", -- 00001748
-		X"00000000", -- 0000174C
-		X"00000000", -- 00001750
-		X"00000000", -- 00001754
-		X"00000000", -- 00001758
-		X"00000000", -- 0000175C
-		X"00000000", -- 00001760
-		X"00000000", -- 00001764
-		X"00000000", -- 00001768
-		X"00000000", -- 0000176C
-		X"00000000", -- 00001770
-		X"00000000", -- 00001774
-		X"00000000", -- 00001778
-		X"00000000", -- 0000177C
-		X"00000000", -- 00001780
-		X"00000000", -- 00001784
-		X"00000000", -- 00001788
-		X"00000000", -- 0000178C
-		X"00000000", -- 00001790
-		X"00000000", -- 00001794
-		X"00000000", -- 00001798
-		X"00000000", -- 0000179C
-		X"00000000", -- 000017A0
-		X"00000000", -- 000017A4
-		X"00000000", -- 000017A8
-		X"00000000", -- 000017AC
-		X"00000000", -- 000017B0
-		X"00000000", -- 000017B4
-		X"00000000", -- 000017B8
-		X"00000000", -- 000017BC
-		X"00000000", -- 000017C0
-		X"00000000", -- 000017C4
-		X"00000000", -- 000017C8
-		X"00000000", -- 000017CC
-		X"00000000", -- 000017D0
-		X"00000000", -- 000017D4
-		X"00000000", -- 000017D8
-		X"00000000", -- 000017DC
-		X"00000000", -- 000017E0
-		X"00000000", -- 000017E4
-		X"00000000", -- 000017E8
-		X"00000000", -- 000017EC
-		X"00000000", -- 000017F0
-		X"00000000", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-	dout <= word_array(to_integer(addr_r(12 downto 2)));
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			addr_r	<= addr;
-		end if;
-	end process;
-
-end data;
diff --git a/lib/misc/rom_wb.vhd b/lib/misc/rom_wb.vhd
deleted file mode 100644
index 41b25ec..0000000
--- a/lib/misc/rom_wb.vhd
+++ /dev/null
@@ -1,62 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom_wb IS
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		WE_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0)
-	);
-END rom_wb;
-
-ARCHITECTURE behavior OF rom_wb IS
-
-	COMPONENT rom
-	PORT
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr	: in  unsigned(31 downto 0);
-		dout	: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	signal data_en : std_logic;
-
-begin
-
-	data_en	<= CYC_I and STB_I and MRDY_I;
-	SRDY_O	<= CYC_I;
-	
-data_valid_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				ACK_O	<= '0';
-			else
-				ACK_O	<= data_en and not WE_I;
-			end if;
-		end if;
-	end process;
-
-inst_rom : rom
-	PORT MAP
-	(
-		clk		=> CLK_I,
-		ce		=> data_en,
-		addr	=> ADDR_I,
-		dout	=> DAT_O
-	);
-
-
-end behavior;
diff --git a/lib/misc/sim/ModelSim SE .lnk b/lib/misc/sim/ModelSim SE .lnk
deleted file mode 100644
index 6ce41f0..0000000
Binary files a/lib/misc/sim/ModelSim SE .lnk and /dev/null differ
diff --git a/lib/misc/sim/tb_bbfifo.fdo b/lib/misc/sim/tb_bbfifo.fdo
deleted file mode 100644
index 5a23c76..0000000
--- a/lib/misc/sim/tb_bbfifo.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../bbfifo.vhd"
-vcom -explicit  -93 "../tb_bbfifo.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_bbfifo
-do {tb_bbfifo.wdo}
-view wave
-view structure
-view signals
-run 1us
diff --git a/lib/misc/sim/tb_bbfifo.wdo b/lib/misc/sim/tb_bbfifo.wdo
deleted file mode 100644
index 06b107e..0000000
--- a/lib/misc/sim/tb_bbfifo.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_bbfifo/rst
-add wave -noupdate -format Logic /tb_bbfifo/clk
-add wave -noupdate -format Logic /tb_bbfifo/re
-add wave -noupdate -format Logic /tb_bbfifo/we
-add wave -noupdate -format Logic /tb_bbfifo/ready
-add wave -noupdate -format Logic /tb_bbfifo/avail
-add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/req
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/rdy
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_bbfifo/inst_bbfifo/bucket_array
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_in
-add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce_out
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {170000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {76738 ps} {299465 ps}
diff --git a/lib/misc/sim/tb_ram_wb.fdo b/lib/misc/sim/tb_ram_wb.fdo
deleted file mode 100644
index 34f771c..0000000
--- a/lib/misc/sim/tb_ram_wb.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit  -93 "../utils_pkg.vhd"
-vcom -explicit  -93 "../ram_sim.vhd"
-vcom -explicit  -93 "../ram_wb.vhd"
-vcom -explicit  -93 "../tb_ram_wb.vhd"
-
-vsim -t 1ps   -lib work tb_ram_wb
-do {tb_ram_wb.wdo}
-view wave
-view structure
-view signals
-run 1.5us
-			 
\ No newline at end of file
diff --git a/lib/misc/sim/tb_ram_wb.wdo b/lib/misc/sim/tb_ram_wb.wdo
deleted file mode 100644
index 144e7a9..0000000
--- a/lib/misc/sim/tb_ram_wb.wdo
+++ /dev/null
@@ -1,33 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ram_wb/clk_o
-add wave -noupdate -format Logic /tb_ram_wb/rst_o
-add wave -noupdate -format Logic /tb_ram_wb/cyc_o
-add wave -noupdate -format Logic /tb_ram_wb/stb_o
-add wave -noupdate -format Logic /tb_ram_wb/we_o
-add wave -noupdate -format Literal /tb_ram_wb/sel_o
-add wave -noupdate -format Logic /tb_ram_wb/ack_i
-add wave -noupdate -format Logic /tb_ram_wb/mrdy_o
-add wave -noupdate -format Logic /tb_ram_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_ram_wb/dout_reg
-add wave -noupdate -format Literal /tb_ram_wb/dout_cnt
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ram_wb/inst_ram_wb/inst_ram/sram
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {23564 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {179430 ps}
diff --git a/lib/misc/sim/tb_rom_wb.fdo b/lib/misc/sim/tb_rom_wb.fdo
deleted file mode 100644
index e8732f0..0000000
--- a/lib/misc/sim/tb_rom_wb.fdo
+++ /dev/null
@@ -1,16 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-
-# Top and TB
-vcom -explicit  -93 "../rom_sim.vhd"
-vcom -explicit  -93 "../rom_wb.vhd"
-vcom -explicit  -93 "../tb_rom_wb.vhd"
-
-vsim -t 1ps   -lib work tb_rom_wb
-do {tb_rom_wb.wdo}
-view wave
-view structure
-view signals
-run 1us
-			 
\ No newline at end of file
diff --git a/lib/misc/sim/tb_rom_wb.wdo b/lib/misc/sim/tb_rom_wb.wdo
deleted file mode 100644
index b8663ed..0000000
--- a/lib/misc/sim/tb_rom_wb.wdo
+++ /dev/null
@@ -1,29 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_rom_wb/clk_o
-add wave -noupdate -format Logic /tb_rom_wb/rst_o
-add wave -noupdate -format Logic /tb_rom_wb/cyc_o
-add wave -noupdate -format Logic /tb_rom_wb/stb_o
-add wave -noupdate -format Logic /tb_rom_wb/ack_i
-add wave -noupdate -format Logic /tb_rom_wb/mrdy_o
-add wave -noupdate -format Logic /tb_rom_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_rom_wb/dout_reg
-add wave -noupdate -format Literal /tb_rom_wb/dout_cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {796036 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/misc/singleshot.vhd b/lib/misc/singleshot.vhd
deleted file mode 100644
index 25f7013..0000000
--- a/lib/misc/singleshot.vhd
+++ /dev/null
@@ -1,155 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    21:52:19 10/22/05
--- Design Name:    
--- Module Name:    singleshot - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
--- Component Template
---
---	COMPONENT singleshot
---	GENERIC (mode : integer);
---	PORT(
---		rst : IN std_logic;
---		clk : IN std_logic;
---		input : IN std_logic;          
---		output : OUT std_logic
---		);
---	END COMPONENT;
---
--- Instantation Template
---
---	singleshot_int: oneshot 
---	GENERIC MAP (
---		mode => 1)		
---	PORT MAP(
---		rst => ,
---		clk => ,
---		input => ,
---		output => 
---	);
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity singleshot is
-    Generic ( mode : integer range 0 to 2 := 1);
-    Port ( rst : in std_logic;
-           clk : in std_logic;
-           input : in std_logic;
-           output : out std_logic);
-end singleshot;
-
-architecture Behavioral of singleshot is
-
-type s_t is (idle, shot_in, active, shot_out);
-signal s, sn : s_t;
-
-begin
-
-process (rst, clk, sn)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			s <= idle;
-		else
-			s <= sn;
-		end if;
-	end if;	
-end process;
-
-mode_1:
-if mode = 1 generate
-begin
-	process (input, s)
-	begin
-		output <= '0';
-		sn <= s;
-		case s is
-			when idle =>
-			if input = '1' then 
-				sn <= shot_in;
-			end if;	
-			when shot_in =>
-				output <= '1';
-				sn <= active;
-			when active =>
-			if input = '0' then 
-				sn <= shot_out;
-			end if;
-			when shot_out =>
-				sn <= idle;
-			when others => null;
-		end case;	
-	end process;
-end generate;
-
-mode_0:
-if mode = 0 generate
-begin
-	process (input, s)
-	begin
-		output <= '0';
-		sn <= s;
-		case s is
-			when idle =>
-			if input = '1' then 
-				sn <= shot_in;
-			end if;	
-			when shot_in =>
-				sn <= active;
-			when active =>
-			if input = '0' then 
-				sn <= shot_out;
-			end if;
-			when shot_out =>
-				output <= '1';
-				sn <= idle;
-			when others => null;
-		end case;	
-	end process;
-end generate;
-
-mode_2:
-if mode = 2 generate
-begin
-	process (input, s)
-	begin
-		output <= '0';
-		sn <= s;
-		case s is
-			when idle =>
-			if input = '1' then 
-				sn <= shot_in;
-			end if;	
-			when shot_in =>
-				output <= '1';
-				sn <= active;
-			when active =>
-			if input = '0' then 
-				sn <= shot_out;
-			end if;
-			when shot_out =>
-				output <= '1';
-				sn <= idle;
-			when others => null;
-		end case;	
-	end process;
-end generate;
-
-end Behavioral;
diff --git a/lib/misc/tb_bbfifo.vhd b/lib/misc/tb_bbfifo.vhd
deleted file mode 100644
index 95fa7b9..0000000
--- a/lib/misc/tb_bbfifo.vhd
+++ /dev/null
@@ -1,136 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: cpu_embedded using cpu_core and rom
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity tb_bbfifo is
-end;
-
-architecture behave of tb_bbfifo is
-
-	-- Number of user data words for simulation
-	constant CLK_PERIOD		: time := 10 ns;
-
-	signal rst				: std_logic := '1';  
-	signal clk				: std_logic := '1';  
-	signal re				: std_logic := '0';  
-	signal we				: std_logic := '0';  
-	signal ready			: std_logic;  
-	signal avail			: std_logic;  
-	signal din				: unsigned(7 downto 0) := (others => '0');
-	signal dout				: unsigned(7 downto 0);
-	signal dout_reg			: unsigned(7 downto 0);
-
-
-begin 
-   
-inst_bbfifo : entity work.bbfifo
-	GENERIC MAP 
-	(
-		depth		=> 4,
-		data_width	=> 8
-	)
-	PORT MAP
-	(
-		rst		=> rst,
-		clk		=> clk,
-		re		=> re,
-		we		=> we,
-		ready	=> ready,
-		avail	=> avail,
-		din		=> din,
-		dout	=> dout
-	);
-
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		clk <= not clk;
-	end process;
-
-RE_GEN: process
-	begin
-		wait for 2*CLK_PERIOD;
-		wait until rising_edge(clk) and avail = '1';
-		re <= '0';
-		dout_reg <= dout;
-		wait until rising_edge(clk);
-		re <= '0';
-	end process;
-
-------------------------------------------------------------------------------------------
-
-STIMULUS: process
-
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		rst <= '0';
-		din <= X"10";
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		wait until rising_edge(clk) and ready = '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '0';
-		wait until rising_edge(clk) and ready = '1';
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '0';
-		wait until rising_edge(clk) and ready = '1';
-		wait until rising_edge(clk) and ready = '1';
-		wait until rising_edge(clk) and ready = '1';
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		we <= '1';
-		din <= din + 1;
-		wait until rising_edge(clk) and ready = '1';
-		
-
-		wait; 
-	
-	end process;
-	
-end architecture behave;
diff --git a/lib/misc/tb_ram_wb.vhd b/lib/misc/tb_ram_wb.vhd
deleted file mode 100644
index fb39a90..0000000
--- a/lib/misc/tb_ram_wb.vhd
+++ /dev/null
@@ -1,414 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-ENTITY tb_ram_wb IS
-END tb_ram_wb;
-
-ARCHITECTURE behavior OF tb_ram_wb IS 
-
-	constant CLK_PERIOD		: time := 10 ns;
-	constant RAM_NUM_WORDS	: integer := 256;
-	
-	signal CLK_O	: std_logic := '1';
-	signal RST_O	: std_logic := '1';
-	signal CYC_O	: std_logic := '0';
-	signal STB_O	: std_logic := '0';
-	signal WE_O		: std_logic := '0';
-	signal SEL_O	: unsigned(3 downto 0) := (others => '1');
-	signal ACK_I	: std_logic;
-	signal MRDY_O	: std_logic := '1';
-	signal SRDY_I	: std_logic;
-	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I	: unsigned(31 downto 0);
-	signal DAT_O	: unsigned(31 downto 0) := (others => '-');
-
-	signal dout_rst			: std_logic := '0';
-	signal dout_reg			: unsigned(31 downto 0);
-	signal dout_cnt			: natural range 0 to 255;
-
-BEGIN
-
-inst_ram_wb : entity work.ram_wb
-	GENERIC MAP
-	(
-		NUM_WORDS	=> RAM_NUM_WORDS
-	)
-	PORT MAP
-	(
-		RST_I		=> RST_O,
-		CLK_I		=> CLK_O,
-		CYC_I		=> CYC_O,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_I,
-		SRDY_O		=> SRDY_I,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> DAT_O,
-		DAT_O		=> DAT_I
-	);
-
-read_register:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if dout_rst = '1' then
-				dout_cnt <= 0;
-			elsif ACK_I = '1' and WE_O = '0' then
-				dout_reg	<= DAT_I;
-				dout_cnt 	<= dout_cnt + 1;
-			end if;
-		end if;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		RST_O <= '0';
-
-		-- 8 single cycles
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		DAT_O	<= X"1234_CAF0";
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		DAT_O	<= DAT_O + 1;
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		
-		-- 8-word burst cycle
-		wait for 3*CLK_PERIOD;
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		wait until rising_edge(CLK_O) and dout_cnt = 7;
-		CYC_O	<= '0';
-
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '1';
-		SEL_O	<= "0011";
-		ADDR_O	<= X"0000_0080";
-		DAT_O	<= X"DEADBEEF";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		wait for 3*CLK_PERIOD;
-		wait until rising_edge(CLK_O);
-		-- 1-word burst cycle
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0080";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		wait until rising_edge(CLK_O);
-		CYC_O	<= '0';
-
-		-- 8-word burst cycle
-		wait for 3*CLK_PERIOD;
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		WE_O	<= '0';
-		ADDR_O	<= X"0000_0000";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		MRDY_O	<= '0';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		MRDY_O	<= '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		wait until rising_edge(CLK_O) and dout_cnt = 54;
-		CYC_O	<= '0';
-
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/misc/tb_rom_wb.vhd b/lib/misc/tb_rom_wb.vhd
deleted file mode 100644
index 0e414f9..0000000
--- a/lib/misc/tb_rom_wb.vhd
+++ /dev/null
@@ -1,223 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-ENTITY tb_rom_wb IS
-END tb_rom_wb;
-
-ARCHITECTURE behavior OF tb_rom_wb IS 
-
-	constant CLK_PERIOD : time := 10 ns;
-	signal CLK_O	: std_logic := '1';
-	signal RST_O	: std_logic := '1';
-	signal CYC_O	: std_logic := '0';
-	signal STB_O	: std_logic := '0';
-	signal ACK_I	: std_logic;
-	signal MRDY_O	: std_logic := '1';
-	signal SRDY_I	: std_logic;
-	signal ADDR_O	: unsigned(31 downto 0) := (others => '-');
-	signal DAT_I	: unsigned(31 downto 0);
-
-	signal dout_rst			: std_logic := '0';
-	signal dout_reg			: unsigned(31 downto 0);
-	signal dout_cnt			: natural range 0 to 255;
-
-BEGIN
-
-inst_rom_wb : entity work.rom_wb
-	PORT MAP
-	(
-		RST_I		=> RST_O,
-		CLK_I		=> CLK_O,
-		CYC_I		=> CYC_O,
-		STB_I		=> STB_O,
-		ACK_O		=> ACK_I,
-		SRDY_O		=> SRDY_I,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_O		=> DAT_I
-	);
-
-read_register:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if dout_rst = '1' then
-				dout_cnt <= 0;
-			elsif ACK_I = '1' then
-				dout_reg	<= DAT_I;
-				dout_cnt 	<= dout_cnt + 1;
-			end if;
-		end if;
-	end process;
-
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		CLK_O <= not CLK_O;
-	end process;
-
-STIMULUS: process
-
-	begin
-
-		wait for 3*CLK_PERIOD;
-		RST_O <= '0';
-
-		-- 8-word burst cycle
-		wait for 3*CLK_PERIOD;
-		dout_rst	<= '1';
-		wait until rising_edge(CLK_O);
-		dout_rst	<= '0';
-		CYC_O	<= '1';
-		STB_O	<= '1';
-		ADDR_O	<= X"0000_0180";
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		MRDY_O	<= '0';
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '1';
-		MRDY_O	<= '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		ADDR_O	<= ADDR_O + 4;
-		wait until rising_edge(CLK_O) and SRDY_I = '1';
-		STB_O	<= '0';
-		
-		wait until rising_edge(CLK_O) and dout_cnt = 54;
-		CYC_O	<= '0';
-
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd
deleted file mode 100644
index f96f294..0000000
--- a/lib/misc/tb_template.vhd
+++ /dev/null
@@ -1,63 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.MATH_REAL.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE STD.TEXTIO.ALL;
-
--- LIBRARY WORK;
--- USE.YOURLIB.WHATELSE
-
-ENTITY tb_template IS
-END tb_template;
-
-ARCHITECTURE behavior OF tb_template IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT your_comp
-	GENERIC
-	(
-	);
-	PORT
-	(
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-
-	--Inputs
-	signal clk		: STD_LOGIC := '0';
-
-	--Outputs
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: your_comp 
-	GENERIC MAP
-	(
-	)
-	PORT MAP
-	(
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-		
-	END PROCESS;
-	
-END tb_template;
diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd
deleted file mode 100644
index 7212852..0000000
--- a/lib/misc/utils_pkg.vhd
+++ /dev/null
@@ -1,196 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.6 2010-03-22 07:25:40 Jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-package utils_pkg is
-	
-	-- Constants
-
-	-- Functions
-	function MIN (X, Y: INTEGER) return INTEGER;
-	function MAX (X, Y: INTEGER) return INTEGER;
-
-	function NextPowerOfTwo(x : real) return real;
-	function NextExpBaseTwo(x : real) return real;
-	function NextPowerOfTwo(x : natural) return natural;
-	function NextExpBaseTwo(x : natural) return natural;
-	function GCD(a, b : natural) return natural;
-	function LCM(a, b : natural) return natural;
-	function UTILS_PERIOD_NS(f_in_MHz : real) return real;
-	function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural;
-	function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural;
-	function f_correct(f : real) return natural;
-	
-end utils_pkg;
-
-
-package body utils_pkg is
-
-	-------------------------------------------------------------
-	function MIN (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y < X then
-		res := Y;
-	end if;
-
-	return res;
-
-	end MIN;
-
-	-------------------------------------------------------------
-	function MAX (X, Y: INTEGER) return INTEGER is
-	variable res : integer := X;
-	begin
-	if Y > X then
-		res := Y;
-	end if;
-
-	return res;
-	
-	end MAX;
-
-	-------------------------------------------------------------
-	function NextExpBaseTwo(x : real) return real is
-	begin
-		return ceil(log2(x));
-	end NextExpBaseTwo;	
-	
-	-------------------------------------------------------------
-	function NextPowerOfTwo(x : real) return real is
-	begin
-
-		return 2.0**NextExpBaseTwo(x);
-	end NextPowerOfTwo;	
-
-	-------------------------------------------------------------
-	function NextExpBaseTwo(x : natural) return natural is
-	begin
-		return natural(NextExpBaseTwo(real(x)));
-	end NextExpBaseTwo;	
-	
-	-------------------------------------------------------------
-	function NextPowerOfTwo(x : natural) return natural is
-	begin
-
-		return 2**NextExpBaseTwo(x);
-	end NextPowerOfTwo;	
-	
-	-------------------------------------------------------------
-	function GCD(a, b : natural) return natural is
-	variable aa : natural;
-	variable bb : natural;
-	begin
-		aa := a;
-		bb := b;
-		while bb /= 0 loop
-			if aa > bb then
-				aa := aa - bb;
-			else
-				bb := bb - aa;
-			end if;
-		end loop;
-		
-		return aa;
-
-	end GCD;	
-
-	-------------------------------------------------------------
-	function LCM(a, b : natural) return natural is
-	begin
-
-		return (a * b)/GCD(a, b);
-
-	end LCM;	
-
-	-------------------------------------------------------------
-	function UTILS_PERIOD_NS(f_in_MHz : real) return real is
-	begin
-		
-		return 1.0E3/f_in_MHz;
-
-	end UTILS_PERIOD_NS;	
-	
-	-------------------------------------------------------------
-	function UTILS_FREQ_M(f_in_MHz, f_out_MHz : real) return natural is
-	variable f_in  : natural;
-	variable f_out : natural;
-	variable C : natural;
-	variable M : natural;
-	variable D : natural;
-	begin
-		C := f_correct(f_out_MHz);
-		if C < 2 then
-			C := f_correct(f_in_MHz);
-		end if;
-
-		f_out := natural(ceil(real(C)*f_out_MHz));
-		f_in  := natural(ceil(real(C)*f_in_MHz));
-
-		M := LCM(f_in, f_out)/f_in;
-		D := f_in/GCD(f_in, f_out);
-
-		assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
-		if M = 1 then
-			M := 2;
-		end if;
-
-		return M;
-		
-	end UTILS_FREQ_M;	
-
-	-------------------------------------------------------------
-	function UTILS_FREQ_D(f_in_MHz, f_out_MHz : real) return natural is
-	variable f_in  : natural;
-	variable f_out : natural;
-	variable C : natural;
-	variable M : natural;
-	variable D : natural;
-	begin
-		C := f_correct(f_out_MHz);
-		if C < 2 then
-			C := f_correct(f_in_MHz);
-		end if;
-
-		f_out := natural(ceil(real(C)*f_out_MHz));
-		f_in  := natural(ceil(real(C)*f_in_MHz));
-
-		M := LCM(f_in, f_out)/f_in;
-		D := f_in/GCD(f_in, f_out);
-
-		assert (M*D) /= (f_in*f_out) report "Finding M and D failed!" severity failure;
-
-		if M = 1 then
-			D := 2*D;
-		end if;
-		
-		return D;
-
-	end UTILS_FREQ_D;	
-
-	-------------------------------------------------------------
-	function f_correct(f : real) return natural is
-	constant MAX_ITER	: positive	:= 100;
-	constant MAX_ERR	: real		:= 0.01;
-	variable fpart		: real;
-	variable err		: real;
-	begin
-		for i in 1 to MAX_ITER loop
-			fpart := real(i)*f - ceil(real(i)*f);
-			err := abs(fpart);
-			if err < max_err then
-				return i;
-			end if;
-		end loop;
-	end f_correct;	
-
-	-------------------------------------------------------------
-end utils_pkg;
-
-
diff --git a/lib/misc/wire_delay.vhd b/lib/misc/wire_delay.vhd
deleted file mode 100644
index 2a5b89c..0000000
--- a/lib/misc/wire_delay.vhd
+++ /dev/null
@@ -1,42 +0,0 @@
-library IEEE;  
-  use IEEE.Std_Logic_1164.all;
-
-entity wire_delay is
-  generic(a_to_b_loss : time := 1 ns;
-          b_to_a_loss : time := 2 ns);
-  port
-    (A : inout Std_Logic;
-     B : inout Std_Logic
-     );
-end wire_delay;
-
-architecture behave of wire_delay is
-begin
-
-  ABC0_Lbl: process
-    variable ThenTime_v : time := 0 ns;
-
-    function max(t1,t2 : time) return time is
-    begin
-        if (t1 > t2) then
-          return t1;
-        else
-          return t2;
-        end if;
-    end;
-
-  begin
-    wait on A'transaction, B'transaction
-                      until ThenTime_v + max(a_to_b_loss, b_to_a_loss) < now;
-    -- Break
-    ThenTime_v := now;
-    A <= 'Z';
-    B <= 'Z';
-    wait for 0 ns;
-
-    -- Make
-    A <= transport B after b_to_a_loss;
-    B <= transport A after a_to_b_loss;
-
-  end process ABC0_Lbl;
-end behave; 
\ No newline at end of file
diff --git a/lib/ps2_port/sim/tb_ps2_core.fdo b/lib/ps2_port/sim/tb_ps2_core.fdo
deleted file mode 100644
index 7faa8a4..0000000
--- a/lib/ps2_port/sim/tb_ps2_core.fdo
+++ /dev/null
@@ -1,13 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-
-vlib work
-vcom -explicit  -93 "../src/ps2_core.vhd"
-vcom -explicit  -93 "../src/tb_ps2_core.vhd"
-
-vsim -t 1ps   -lib work tb_ps2_core
-do {tb_ps2_core.wdo}
-view wave
-view structure
-view signals
-run 10 ms
diff --git a/lib/ps2_port/sim/tb_ps2_core.wdo b/lib/ps2_port/sim/tb_ps2_core.wdo
deleted file mode 100644
index d36d5e4..0000000
--- a/lib/ps2_port/sim/tb_ps2_core.wdo
+++ /dev/null
@@ -1,48 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ps2_core/rst
-add wave -noupdate -format Logic /tb_ps2_core/clk
-add wave -noupdate -format Literal /tb_ps2_core/din
-add wave -noupdate -format Logic /tb_ps2_core/tx_empty
-add wave -noupdate -format Logic /tb_ps2_core/din_vld
-add wave -noupdate -format Literal /tb_ps2_core/dout
-add wave -noupdate -format Logic /tb_ps2_core/rx_present
-add wave -noupdate -format Logic /tb_ps2_core/read_en
-add wave -noupdate -format Literal /tb_ps2_core/dout_reg
-add wave -noupdate -format Logic /tb_ps2_core/ps2_data_rx
-add wave -noupdate -format Logic /tb_ps2_core/ps2_clk_rx
-add wave -noupdate -format Logic /tb_ps2_core/ps2_clk_tx
-add wave -noupdate -format Logic /tb_ps2_core/ps2_data_tx
-add wave -noupdate -format Logic /tb_ps2_core/ps2_clk_i
-add wave -noupdate -format Logic /tb_ps2_core/tx_trig
-add wave -noupdate -format Logic /tb_ps2_core/rx_err_flag
-add wave -noupdate -format Logic /tb_ps2_core/rx_err_par
-add wave -noupdate -divider DEBUG
-add wave -noupdate -format Literal /tb_ps2_core/uut/read_cs
-add wave -noupdate -format Literal /tb_ps2_core/uut/write_cs
-add wave -noupdate -format Logic /tb_ps2_core/uut/rx_busy
-add wave -noupdate -format Logic /tb_ps2_core/uut/tx_busy
-add wave -noupdate -format Logic /tb_ps2_core/uut/rx_rdy
-add wave -noupdate -format Logic /tb_ps2_core/uut/tx_rdy
-add wave -noupdate -format Literal /tb_ps2_core/uut/rx_reg
-add wave -noupdate -format Literal /tb_ps2_core/uut/tx_reg
-add wave -noupdate -format Logic /tb_ps2_core/uut/parity_rx
-add wave -noupdate -format Logic /tb_ps2_core/uut/parity_tx
-add wave -noupdate -format Literal /tb_ps2_core/uut/sipo_reg
-add wave -noupdate -format Literal /tb_ps2_core/uut/piso_reg
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2894250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {5250 us}
diff --git a/lib/ps2_port/src/debounce.vhd b/lib/ps2_port/src/debounce.vhd
deleted file mode 100644
index 3c5cd39..0000000
--- a/lib/ps2_port/src/debounce.vhd
+++ /dev/null
@@ -1,89 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    19:34:24 10/23/05
--- Design Name:    
--- Module Name:    debounce - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity debounce is
-    Generic ( ncyc_latency : integer := 100);
-    Port ( rst : in std_logic;
-           clk : in std_logic;
-           input : in std_logic;
-           output : out std_logic);
-end debounce;
-
-architecture Behavioral of debounce is
-
-type debounce_state_t is (init_st, wait_st, rel_st);
-signal debounce_cs : debounce_state_t;
-signal debounce_ns : debounce_state_t;
-signal count       : integer range 0 to ncyc_latency-1;
-signal input_last	 : std_logic;
-
-begin
-
-	debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input)
-	begin
-		if (rst = '1') then
-			count <= 0;
-			output <= input;
-			input_last <= input;
-		else
-			if rising_edge(clk) then
-				debounce_cs <= debounce_ns;
-				if (debounce_cs = wait_st) then
-					if (count /= 0) then
-						count <= count - 1;
-					end if;
-				else
-					count <= ncyc_latency-1;
-					if	(debounce_cs = rel_st) then
-						output <= input;
-						input_last <= input;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	debounce_in: process(rst, clk, input, input_last, debounce_cs, count)
-	begin
-		debounce_ns <= debounce_cs;
-		case debounce_cs is
-			when init_st =>
-				if (input /= input_last) then
-					debounce_ns <= wait_st;
-				end if;
-			when wait_st =>
-				if (count = 0) then
-					debounce_ns <= rel_st;
-				end if;
-			when others => 
-				debounce_ns <= init_st;
-		end case;
-	end process;
-
-end Behavioral;
diff --git a/lib/ps2_port/src/ps2_core.vhd b/lib/ps2_port/src/ps2_core.vhd
deleted file mode 100644
index 9a3dab0..0000000
--- a/lib/ps2_port/src/ps2_core.vhd
+++ /dev/null
@@ -1,620 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    18:05:41 10/22/05
--- Design Name:    
--- Module Name:    ps2_core - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ps2_core is
-	Generic 
-	(
-		f_sys_clk	: real	:= 100.0
-	);
-    Port
-    (
-		rst : in std_logic;
-		clk : in std_logic;
-		din : in unsigned(7 downto 0);
-		dout : out unsigned(7 downto 0);
-		tx_empty : out std_logic;
-		rx_present : out std_logic;
-		rx_err_flag : out std_logic;
-		rx_err_par : out std_logic;
-		din_vld : in std_logic;
-		read_en : in std_logic;
-		ps2_clk_rx : in std_logic;
-		ps2_data_rx : in std_logic;
-		ps2_clk_tx : out std_logic;
-		ps2_data_tx : out std_logic
-	);
-
-end ps2_core;
-
-architecture Behavioral of ps2_core is
-
--- Types
-type line_state_rx_t is (start_wait_st, start_trans_st, start_sample_st,
-                      data_wait_st, data_trans_st, data_sample_st, 
-                      parity_wait_st, parity_trans_st, parity_sample_st, 
-                      stop_wait_st, stop_trans_st, stop_sample_st,
-							 valid_st, abort_st);
-
-type line_state_tx_t is (tx_idle_st, tx_clock_assert_st, tx_start_latency_st,
-                         tx_start_assert_st, tx_clock_release_st, tx_dev_trans_st,
-								 tx_data_wait_st, tx_data_trans_st, tx_data_sample_st,
-								 tx_parity_update_st, tx_dev_wait_st, 
-								 tx_parity_wait_st, tx_parity_trans_st, tx_parity_sample_st,
-								 tx_stop_wait_st, tx_stop_trans_st, tx_stop_sample_st,
-								 tx_ack_trans_st, tx_ack_sample_st, tx_valid_st);
-
--- Constant
-constant prescaler_us          : integer := integer(f_sys_clk);
-constant timeout_us            : integer := 15000;
-constant time_clock_assert     : integer := 120;
-constant time_clock_abort      : integer := 500;
-
--- Signals
-signal en_us               : std_logic;
-signal timeout_rx_load_en     : std_logic;
-signal timeout_rx_flag     : std_logic;
-
-signal timeout_tx_load_en  : std_logic;
-signal timeout_tx_flag     : std_logic;
-
-signal read_cs             : line_state_rx_t;
-signal read_ns             : line_state_rx_t;
-signal write_cs            : line_state_tx_t;
-signal write_ns            : line_state_tx_t;
-
-signal data_cnt_en         : std_logic;
-signal data_cnt_rst        : std_logic;
-signal data_cnt            : integer range 0 to 7;
-
-signal data_cnt_tx_en      : std_logic;
-signal data_cnt_tx_rst     : std_logic;
-signal data_cnt_tx         : integer range 0 to 7;
-
-signal sipo_en             : std_logic;
-signal piso_en             : std_logic;
-signal piso_out            : std_logic;
-signal piso_load_en        : std_logic;
-signal rx_en               : std_logic;
-signal tx_en               : std_logic;
-signal rx_busy             : std_logic;
-signal rx_full             : std_logic;
-signal rx_err              : std_logic;
-signal parity_rx_err_en    : std_logic;
-signal rx_err_set 	   		: std_logic;
-signal rx_err_clr   	   : std_logic;
-
-signal tx_busy             : std_logic;
-signal rx_rdy              : std_logic;
-signal tx_rdy              : std_logic;
-signal tx_req              : std_logic;
-signal rx_reg              : unsigned(7 downto 0);
-signal tx_reg              : unsigned(7 downto 0);
-
-signal parity_rx_rst       : std_logic;
-signal parity_rx_en        : std_logic;
-signal parity_rx           : std_logic;
-signal parity_tx_rst       : std_logic;
-signal parity_tx_en        : std_logic;
-signal parity_tx           : std_logic;
-
-signal timeout_count_rx		: integer range 0 to timeout_us-1;
-signal timeout_count_tx		: integer range 0 to timeout_us-1;
-signal timeval_tx			: integer range 0 to timeout_us-1;
-signal timeval_rx			: integer range 0 to timeout_us-1;
-
-signal sipo_reg				: unsigned(7 downto 0);
-signal piso_reg				: unsigned(7 downto 0);
-
-signal clk_tx  		        : std_logic;
-signal data_tx  	        : std_logic;
-signal rx_abort		        : std_logic;
-
-begin
-
-proc_prescaler:
-process(clk)
-	variable cnt_prescaler : integer range 0 to prescaler_us-1;
-	begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			cnt_prescaler := prescaler_us - 1;
-			en_us <= '0';
-		elsif cnt_prescaler = 0 then
-			cnt_prescaler := prescaler_us - 1;
-			en_us <= '1';
-		else
-			cnt_prescaler := cnt_prescaler - 1;
-			en_us <= '0';
-		end if;
-	end if;
-end process proc_prescaler;
-
-proc_timeout_counter_rx:
-process (clk) 
-begin
-	if rising_edge(clk) then
-		if timeout_rx_load_en ='1' then
-			timeout_count_rx <= timeval_rx;
-			timeout_rx_flag <= '0';
-		elsif en_us = '1' then
-			if (timeout_count_rx /= 0) then
-				timeout_count_rx <= timeout_count_rx - 1;
-			else
-				timeout_rx_flag <= '1';
-			end if;		
-		end if;
-	end if;
-end process;
-
-proc_timeout_counter_tx:
-process (clk) 
-begin
-	if rising_edge(clk) then
-		if timeout_tx_load_en ='1' then
-			timeout_count_tx <= timeval_tx;
-			timeout_tx_flag <= '0';
-		elsif en_us = '1' then
-			if (timeout_count_tx /= 0) then
-				timeout_count_tx <= timeout_count_tx - 1;
-			else
-				timeout_tx_flag <= '1';
-			end if;		
-		end if;
-	end if;
-end process;
-
-proc_rx_sipo:
-process (clk)
-begin
-	if rising_edge(clk) then
-		if (rst = '1') then
-			sipo_reg <= (others => '0'); 
-		elsif sipo_en = '1' then 
-			sipo_reg <= ps2_data_rx & sipo_reg(sipo_reg'left downto 1);
-		end if; 
-	end if;
-	rx_reg <= sipo_reg;
-end process;
-
-proc_tx_piso:
-process (clk)
-begin
-	if rising_edge(clk) then
-		if rst ='1' then 
-			piso_reg <= (others => '0'); 
-		elsif piso_load_en = '1' then 
-			piso_reg <= tx_reg; 
-		elsif piso_en = '1' then 
-			piso_reg <= '0' & piso_reg(piso_reg'left downto 1);
-		end if; 
-	end if;
-	piso_out <= piso_reg(0);
-end process;
-
-proc_parity_bitser_rx:
-process (clk) 
-begin
-	if rising_edge(clk) then
-		if parity_rx_rst='1' then 
-			parity_rx <= '1';
-		elsif parity_rx_en = '1' and ps2_data_rx = '1' then
-			parity_rx <= not parity_rx;
-		end if;
-	end if;
-end process;
-
-proc_rx_error_reg:
-process (clk) 
-begin
-	if rising_edge(clk) then
-		if rst='1' then 
-			rx_err_flag <= '0';
-			rx_err_par <= '0';
-		elsif parity_rx_err_en = '1' then
-			rx_err_flag <= parity_rx;
-			rx_err_par <= parity_rx;
-		elsif rx_err_set = '1' then
-			rx_err_flag <= '1';
-		elsif rx_err_clr = '1' then
-			rx_err_flag <= '0';
-		end if;
-	end if;
-end process;
-
-proc_parity_bitser_tx:
-process (clk) 
-begin
-	if rising_edge(clk) then
-		if parity_tx_rst='1' then 
-			parity_tx <= '1';
-		elsif parity_tx_en = '1' and piso_out = '1' then
-			parity_tx <= not parity_tx;
-		end if;
-	end if;
-end process;
-
-
-	-------------------------------------------
-	tx_en <= tx_req and (not rx_busy);
-	rx_en <= not tx_busy;
-
-	-------------------------------------------
-rx_present <= rx_full;
-proc_out_reg:
-process(clk)
-begin
-	if rising_edge(clk) then
-		ps2_clk_tx		<= clk_tx and not rx_abort;
-		ps2_data_tx		<= data_tx;
-		if rst = '1' then
-			dout      <= (others => '0');
-			rx_full <= '0';
-		elsif rx_rdy = '1' then
-			dout      <= rx_reg;
-			rx_full <= '1';
-		elsif read_en = '1' then
-			rx_full <= '0';
-		end if;
-	end if;
-end process;
-
-proc_in_reg:
-process(clk)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			tx_empty    <= '1';
-			tx_req       <= '0';
-		elsif piso_load_en = '1' then
-			tx_reg       <= din;
-			tx_empty    <= '1';
-			tx_req       <= '0';
-		elsif	din_vld = '1' then
-			tx_empty    <= '0';
-			tx_req       <= '1';
-		end if;
-	end if;
-end process;
-
-	-------------------------------------------
-proc_read_state_clk:
-process(clk)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			read_cs <= start_wait_st;
-		else
-			read_cs <= read_ns;
-			if (data_cnt_rst = '1') then
-				data_cnt <= 7;
-			elsif (data_cnt_en = '1') then
-				if (data_cnt /= 0) then
-					data_cnt <= data_cnt - 1;
-				end if;
-			end if;
-		end if;
-	end if;
-end process;
-
-	-------------------------------------------
-proc_write_state_clk:
-process(rst, clk)
-begin
-	if rising_edge(clk) then
-		if rst = '1' then
-			write_cs <= tx_idle_st;
-		else	
-			write_cs <= write_ns;
-			if (data_cnt_tx_rst = '1') then
-				data_cnt_tx <= 7;
-			elsif (data_cnt_tx_en = '1') then
-				if (data_cnt_tx /= 0) then
-					data_cnt_tx <= data_cnt_tx - 1;
-				end if;
-			end if;
-		end if;
-	end if;
-end process;
-
-read_state_decode:
-process (read_cs, timeout_rx_flag, rx_en, data_cnt, ps2_data_rx, ps2_clk_rx, rx_full)
-begin
-	timeout_rx_load_en <= '0';
-	timeval_rx			<= timeout_us - 1;
-	data_cnt_en     <= '0';
-	data_cnt_rst    <= '0';
-	sipo_en         <= '0';
-	rx_rdy          <= '0';
-	parity_rx_en 		 <= '0';
-	parity_rx_rst		 <= '0';
-	parity_rx_err_en	<= '0';
-	rx_busy         <= '1';
-	rx_abort		<= '0';
-	rx_err_set	<= '0';
-	rx_err_clr	<= '0';
-	
-      --declare default state for next_state to avoid latches
-      read_ns <= read_cs;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-      case (read_cs) is
-         when start_wait_st =>
-			timeout_rx_load_en <= '1';
-			rx_busy         <= '0';
-				if ps2_data_rx = '0' and ps2_clk_rx = '1' and rx_en = '1' then
-               read_ns <= start_trans_st;
-            end if;
-         when start_trans_st =>
-			data_cnt_rst    <= '1';
-			parity_rx_rst		 <= '1';
-			timeout_rx_load_en <= '1';
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_data_rx = '0' and ps2_clk_rx = '0' then
-               read_ns <= start_sample_st;
-            end if;
-         when start_sample_st =>
-				read_ns <= data_wait_st;
-         -- Wait data change
-			when data_wait_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '1' then
-               read_ns <= data_trans_st;
-            end if;
-         -- Wait data trans
-         when data_trans_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '0' then
-               read_ns <= data_sample_st;
-            end if;
-         -- Data sample
-         when data_sample_st =>
-			data_cnt_en     <= '1';	
-			parity_rx_en 		 <= '1';
-			sipo_en			 <= '1';	
-			timeout_rx_load_en <= '1';
-				read_ns <= data_wait_st;
-				if data_cnt = 0 then
-	            read_ns <= parity_wait_st;
-				end if;
-         when parity_wait_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '1' then
-               read_ns <= parity_trans_st;
-            end if;
-         when parity_trans_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '0' then
-               read_ns <= parity_sample_st;
-            end if;
-         when parity_sample_st =>
-			timeout_rx_load_en <= '1';
-			parity_rx_en 		 <= '1';
-				read_ns <= stop_wait_st;
-				if rx_full = '1' then -- buffer full
-					timeval_rx <=  time_clock_abort - 1;
-					read_ns <= abort_st;
-					rx_err_set <= '1';
-				end if;	
-         when stop_wait_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '1' then
-               read_ns <= stop_trans_st;
-            end if;
-         when stop_trans_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-            elsif ps2_clk_rx = '0' and ps2_data_rx = '1' then
-               read_ns <= stop_sample_st;
-            end if;
-         when stop_sample_st =>
-				if timeout_rx_flag = '1' then
-               read_ns <= start_wait_st;
-				elsif ps2_clk_rx = '1' then
-               read_ns <= valid_st;
-            end if;
-         when valid_st =>
-			parity_rx_err_en	<= '1';
-			rx_busy         <= '0';
-			rx_rdy          <= '1';
-			rx_err_clr <= '1';
-            read_ns <= start_wait_st;
-         when abort_st =>
-         	rx_abort <= '1';
-			if timeout_rx_flag = '1' then
-            	read_ns <= start_wait_st;
-            end if;
-         when others =>
-            read_ns <= start_wait_st;
-      end case;      
-   end process;
-
-	-------------------------------------------
-write_state_output:
-process(write_cs, piso_out, parity_tx)
-	begin
-	
-		timeout_tx_load_en <= '0';
-		tx_rdy             <= '0';
-		tx_busy            <= '1';
-		piso_load_en		 <= '0';
-      clk_tx        <= '1';
-      data_tx       <= '1';
-		piso_en            <= '0';
-		timeval_tx         <= time_clock_assert - 1;
-		data_cnt_tx_en		 <= '0';
-		data_cnt_tx_rst    <= '0';
-		parity_tx_rst      <= '0';
-		parity_tx_en       <= '0';
-      case (write_cs) is
-         when tx_idle_st =>
-				tx_busy            <= '0';
-				timeout_tx_load_en <= '1';
-         when tx_clock_assert_st =>
-				parity_tx_rst      <= '1';
-				piso_load_en		 <= '1';
-				data_cnt_tx_rst    <= '1';
-		      clk_tx        <= '0';
-         when tx_start_assert_st =>
-		      clk_tx        <= '0';
-            data_tx       <= '0';
-         when tx_clock_release_st =>
-            data_tx       <= '0';
-				timeout_tx_load_en <= '1';
-				timeval_tx         <=  timeout_us - 1;
-         when tx_dev_wait_st =>
-            data_tx       <= '0';
-         when tx_dev_trans_st =>
-            data_tx       <= '0';
-				timeout_tx_load_en <= '1';
-				timeval_tx         <=  timeout_us - 1;
-         when tx_data_wait_st => 
-				data_tx       <= piso_out;
-         when tx_data_trans_st => 
-				data_cnt_tx_en		 <= '1';
-				data_tx       <= piso_out;
-				piso_en            <= '1';
-				timeout_tx_load_en <= '1';
-				timeval_tx         <=  timeout_us - 1;
-				parity_tx_en       <= '1';
-         when tx_data_sample_st => 
-				data_tx       <= piso_out;
-         when tx_parity_update_st => 
-				parity_tx_en       <= '1';
-				data_tx       <= piso_out;
-         when tx_parity_sample_st => 
-				data_tx       <= parity_tx;
-         when tx_parity_wait_st => 
-				data_tx       <= parity_tx;
-         when tx_parity_trans_st => 
-				data_tx       <= piso_out;
-				timeout_tx_load_en <= '1';
-				timeval_tx         <=  timeout_us - 1;
-         when tx_valid_st => 
-				tx_rdy             <= '1';
-         when others => null; 
-      end case;      
-	end process;
-
-write_state_decode:
-process (write_cs, tx_en, data_cnt_tx, timeout_tx_flag, ps2_data_rx, ps2_clk_rx)
-   begin
-      --declare default state for next_state to avoid latches
-      write_ns <= write_cs;  --default is to stay in current state
-      --insert statements to decode next_state
-      --below is a simple example
-      case (write_cs) is
-			when tx_idle_st =>
-				if tx_en = '1' then
-					write_ns <= tx_clock_assert_st;
-				end if;
-         when tx_clock_assert_st =>
-				if timeout_tx_flag = '1' then
-	            write_ns <= tx_start_assert_st;
-            end if;
-         when tx_start_assert_st =>
-				write_ns <= tx_clock_release_st;
-         when tx_clock_release_st =>
-            write_ns <= tx_dev_wait_st;
-         when tx_dev_wait_st =>
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '1' then
-	            write_ns <= tx_dev_trans_st;
-            end if;
-         when tx_dev_trans_st =>
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '0' then
-	            write_ns <= tx_data_wait_st;
-            end if;
-         when tx_data_wait_st =>
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '1' then
-	            write_ns <= tx_data_sample_st;
-            end if;
-         when tx_data_sample_st => 
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '0' then
-	            write_ns <= tx_data_trans_st;
-					if (data_cnt_tx = 0)	then
-						write_ns <= tx_parity_update_st;
-					end if;		
-            end if;
-         when tx_data_trans_st => 
-				write_ns <= tx_data_wait_st;
-         when tx_parity_update_st => 
-				write_ns <= tx_parity_trans_st;
-         when tx_parity_trans_st => 
-            write_ns <= tx_parity_wait_st;
-         when tx_parity_wait_st =>
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '1' then
-	            write_ns <= tx_parity_sample_st;
-            end if;
-         when tx_parity_sample_st => 
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '0' then
-	            write_ns <= tx_stop_trans_st;
-            end if;
-         when tx_stop_trans_st => 
-            write_ns <= tx_stop_wait_st;
-         when tx_stop_wait_st =>
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '1' then
-	            write_ns <= tx_ack_trans_st;
-            end if;
-         when tx_ack_trans_st => 
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '0' and ps2_data_rx = '0' then
-	            write_ns <= tx_ack_sample_st;
-            end if;
-         when tx_ack_sample_st => 
-				if timeout_tx_flag = '1' then
-					write_ns <= tx_idle_st;
-				elsif ps2_clk_rx = '1' and ps2_data_rx = '1' then
-	            write_ns <= tx_valid_st;
-            end if;
-         when others =>
-            write_ns <= tx_idle_st;
-      end case;      
-   end process;
-
-	-------------------------------------------
-end Behavioral;
diff --git a/lib/ps2_port/src/ps2_phy_virtex.vhd b/lib/ps2_port/src/ps2_phy_virtex.vhd
deleted file mode 100644
index 3b8d685..0000000
--- a/lib/ps2_port/src/ps2_phy_virtex.vhd
+++ /dev/null
@@ -1,122 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    20:52:44 10/26/05
--- Design Name:    
--- Module Name:    ps2_phy - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity ps2_phy is
-    Port 
-    (
-		rst : in std_logic;
-		clk : in std_logic;
-		ps2_clk : inout std_logic;
-		ps2_data : inout std_logic;
-		rx_clk : out std_logic;
-		rx_data : out std_logic;
-		tx_clk : in std_logic;
-		tx_data : in std_logic
-	);
-end ps2_phy;
-
-architecture Behavioral of ps2_phy is
-
-	COMPONENT debounce
-	GENERIC (ncyc_latency : integer);
-	PORT
-	(
-		rst : IN std_logic;
-		clk : IN std_logic;
-		input : IN std_logic;          
-		output : OUT std_logic
-	);
-	END COMPONENT;
-
-signal clk_in               : std_logic;
-signal data_in              : std_logic;
-
-begin
-
-	Inst_debounce_clk: debounce
-	GENERIC MAP 
-	(
-		ncyc_latency => 8
-	)		
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		input => clk_in,
-		output => rx_clk
-	);
-
-	Inst_debounce_data: debounce
-	GENERIC MAP 
-	(
-		ncyc_latency => 8
-	)		
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		input => data_in,
-		output => rx_data
-	);
-
-IOBUF_inst_ps2_clk : IOBUF
-	generic map 
-	(
-		DRIVE => 2,
-		IBUF_DELAY_VALUE => "0",   -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
-		IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
-		IOSTANDARD => "DEFAULT",
-		SLEW => "SLOW"
-	)
-	port map
-	(
-		O  => clk_in,             -- Buffer output
-		IO => ps2_clk,            -- Buffer inout port (connect directly to top-level port)
-		I  => tx_clk,             -- Buffer input
-		T  => tx_clk              -- 3-state enable input 
-	);
-
-	IOBUF_inst_ps2_data : IOBUF
-	generic map
-	(
-		DRIVE => 2,
-		IBUF_DELAY_VALUE => "0",   -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
-		IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
-		IOSTANDARD => "DEFAULT",
-		SLEW => "SLOW"
-	)
-	port map
-	(
-		O  => data_in,            -- Buffer output
-		IO => ps2_data,           -- Buffer inout port (connect directly to top-level port)
-		I  => tx_data,            -- Buffer input
-		T  => tx_data             -- 3-state enable input 
-	);
-
-end Behavioral;
diff --git a/lib/ps2_port/src/ps2_wb.vhd b/lib/ps2_port/src/ps2_wb.vhd
deleted file mode 100644
index af42d75..0000000
--- a/lib/ps2_port/src/ps2_wb.vhd
+++ /dev/null
@@ -1,143 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY ps2_wb IS
-	Generic
-	(
-		f_sys_clk	: real	:= 100.0
-	);
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_O		: out STD_LOGIC;
-		clk_rx		: in std_logic;
-		data_rx		: in std_logic;
-		clk_tx		: out std_logic;
-		data_tx		: out std_logic
-	);
-END ps2_wb;
-
-ARCHITECTURE behavior OF ps2_wb IS
-
-
-	-- Signals for ps2 connections
-	signal reg_we_ps2_tx	: std_logic;
-	signal reg_re_ps2_rx	: std_logic;
-	signal reg_ps2_tx		: unsigned(7 downto 0);
-	signal reg_ps2_rx		: unsigned(7 downto 0);
-	signal rx_data_present	: std_logic;
-	signal ps2_status_port	: unsigned(15 downto 0);
-	signal rx_int_en		: std_logic;
-	signal tx_int_en		: std_logic;
-	signal irq_rx			: std_logic;
-	signal irq_tx			: std_logic;
-	signal tx_empty			: std_logic;
-	signal rx_err_flag		: std_logic;
-	signal rx_err_par		: std_logic;
-	signal stat_clk			: std_logic;
-	signal stat_data		: std_logic;
-	
-begin
-
-	SRDY_O	<= CYC_I;
-	
-------------------------------------------------------------------
-registers_write: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			reg_we_ps2_tx	<= '0';
-			if RST_I = '1' then
-				rx_int_en		<= '0';
-				tx_int_en		<= '0';
-			elsif (STB_I and CYC_I and WE_I) = '1' then
-				case ADDR_I(5 downto 2) is
-				
-				when "0000" =>
-					reg_we_ps2_tx	<= '1';
-					reg_ps2_tx		<= DAT_I(7 downto 0);
-					
-				when "0001" =>
-					rx_int_en		<= DAT_I(6);
-					tx_int_en		<= DAT_I(5);
-					
-				when others => null;
-				end case;
-			end if;	
-		end if;	
-	end process;
-
-registers_read: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			reg_re_ps2_rx	<= '0';
-			ACK_O			<= '0';
-			if (STB_I and CYC_I) = '1' then
-				ACK_O		<= not WE_I;
-				DAT_O		<= (others => '0');
-				case ADDR_I(5 downto 2) is
-
-				when "0000" =>
-					reg_re_ps2_rx		<= not WE_I;
-					DAT_O(7 downto 0)	<= unsigned(reg_ps2_rx);
-
-				when "0001" =>
-					DAT_O(15 downto 0)	<= ps2_status_port;
-
-				when others => null;
-				end case;
-			end if;
-		end if;	
-	end process;
-
-irq_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			INT_O		<= irq_rx or irq_tx;
-			irq_tx		<= tx_empty and tx_int_en;
-			irq_rx		<= rx_data_present and rx_int_en;
-			stat_clk	<= clk_rx;
-			stat_data	<= data_rx;
-		end if;
-	end process;
-
-inst_ps2_core: entity work.ps2_core 
-	GENERIC MAP
-	(
-		f_sys_clk => f_sys_clk
-	)
-	PORT MAP
-	(
-		rst => RST_I,
-		clk => CLK_I,
-		din => reg_ps2_tx,
-		dout => reg_ps2_rx,
-		tx_empty => tx_empty,
-		rx_present => rx_data_present,
-		rx_err_flag => rx_err_flag,
-		rx_err_par => rx_err_par,
-		din_vld => reg_we_ps2_tx,
-		read_en => reg_re_ps2_rx,
-		ps2_clk_rx => clk_rx,
-		ps2_data_rx => data_rx,
-		ps2_clk_tx => clk_tx,
-		ps2_data_tx => data_tx
-	);
-
-	ps2_status_port	<= rx_err_flag & "000" & rx_err_par & '0' & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & stat_data & stat_clk & rx_data_present & '0' & tx_empty;
-
-end behavior;
diff --git a/lib/ps2_port/src/tb_ps2_core.vhd b/lib/ps2_port/src/tb_ps2_core.vhd
deleted file mode 100644
index b2aa534..0000000
--- a/lib/ps2_port/src/tb_ps2_core.vhd
+++ /dev/null
@@ -1,280 +0,0 @@
-
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   20:35:49 10/22/2005
--- Design Name:   ps2_core
--- Module Name:   tb_ps2_core.vhd
--- Project Name:  ps2if
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: ps2_core
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY tb_ps2_core IS
-END tb_ps2_core;
-
-ARCHITECTURE behavior OF tb_ps2_core IS 
-
-	--Constants
-	constant SYSPERIOD : time := 10 ns;
-	constant PS2PERIOD : time := 100 us;
-
-	--Inputs
-	SIGNAL rst :  std_logic := '1';
-	SIGNAL clk :  std_logic := '0';
-	SIGNAL din_vld :  std_logic := '0';
-	SIGNAL read_en :  std_logic := '0';
-	SIGNAL ps2_clk_rx :  std_logic := '1';
-	SIGNAL ps2_data_rx :  std_logic := '1';
-	SIGNAL din :  unsigned(7 downto 0) := (others=>'0');
-
-	--Outputs
-	SIGNAL dout :  unsigned(7 downto 0);
-	SIGNAL dout_reg :  unsigned(7 downto 0);
-	SIGNAL tx_empty :  std_logic;
-	SIGNAL rx_present :  std_logic;
-	SIGNAL rx_err_flag :  std_logic;
-	SIGNAL rx_err_par :  std_logic;
-	SIGNAL ps2_clk_i :  std_logic := '1';
-	SIGNAL ps2_clk_j :  std_logic := '1';
-	SIGNAL ps2_clk_tx :  std_logic;
-	SIGNAL ps2_data_tx :  std_logic;
-	SIGNAl tx_trig : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-uut: entity work.ps2_core
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		din => din,
-		dout => dout,
-		tx_empty => tx_empty,
-		rx_present => rx_present,
-		rx_err_flag => rx_err_flag,
-		rx_err_par => rx_err_par,
-		din_vld => din_vld,
-		read_en => read_en,
-		ps2_clk_rx => ps2_clk_rx,
-		ps2_data_rx => ps2_data_rx,
-		ps2_clk_tx => ps2_clk_tx,
-		ps2_data_tx => ps2_data_tx
-	);
-
-	ps2_clk_j <= ps2_clk_i after PS2PERIOD/4;
- 	tb_pswclk : PROCESS
-	BEGIN
-		wait until ps2_clk_j'event;  
-		ps2_clk_rx <= ps2_clk_j;
-
---		wait for SYSPERIOD;
---		ps2_clk_rx <= not ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= not ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= not ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= not ps2_clk_j;
---		wait for SYSPERIOD;
---		ps2_clk_rx <= ps2_clk_j;
-	END PROCESS;
-
- 	tb_sysclk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for SYSPERIOD/2;
-	END PROCESS;
-
-	read_en <= rx_present after 1.6 ms;
- 	tb_read : PROCESS(clk)
-	BEGIN
-		if rising_edge(clk) then
-			if rx_present = '1' then
-				dout_reg <= dout;
-			end if;
-		end if;
-
-	END PROCESS;
-
- 	tb_write : PROCESS
-	BEGIN
-		wait until ps2_clk_tx = '0';
-		wait for PS2PERIOD;
-		wait until ps2_data_tx = '0';
-		wait until ps2_clk_tx = '1';
-		wait for PS2PERIOD/2;
-		tx_trig <= '1';
-
-	END PROCESS;
-	
-	tb : PROCESS
-	BEGIN
-
-		wait for 20*SYSPERIOD;
-		rst <= '0';
-
- 	   for iter in 1 to 4 loop
---		wait for 2*PS2PERIOD;
-		wait until rising_edge(clk) and ps2_clk_tx = '1';
-
-		--Start bit
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '0';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 0
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx	<= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 1
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx	<= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 2
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '0';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 3
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 4
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 5
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '0';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 6
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Data bit 7
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Parity
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		if iter = 3 then
-			ps2_data_rx <= '0';
-		end if;	
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		--Stop
-		wait for PS2PERIOD/2;
-		ps2_clk_i  <= '0';
-		ps2_data_rx <= '1';
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-
-		end loop;
-
-		ps2_data_rx <= '1';
-		ps2_clk_i <= '1';
-
-		wait for PS2PERIOD;
-		wait until rising_edge(clk);
- 		din     <= x"A5";
-		din_vld	<= '1';
-		wait until rising_edge(clk);
-		din_vld	<= '0';
-
-		wait until tx_trig = '1';
-		wait for 2*PS2PERIOD;
-		-- Start
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-
- 	   for iter in 1 to 8 loop
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		end loop;
-
-		-- Stop
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-
-		-- Parity
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-
-		ps2_data_rx <= '0';
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-
-		ps2_clk_i <= not ps2_clk_i;
-		wait for PS2PERIOD/2;
-		ps2_data_rx <= '1';
-		ps2_clk_i <= '1';
-		-- Place stimulus here
-
-		wait; -- will wait forever
-	END PROCESS;
-
-END;
diff --git a/lib/radio/cordic/eval_cordic.m b/lib/radio/cordic/eval_cordic.m
deleted file mode 100644
index 8754ccd..0000000
--- a/lib/radio/cordic/eval_cordic.m
+++ /dev/null
@@ -1,171 +0,0 @@
-function eval_cordic(Nmax, doplot)
-N = 100;
-
-arctan_tbl = (atan(2.^-(0:N-1))/pi)'
-%gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
-
-% Rotation mode
-disp('Rotation:')
-for i=1:N,
-    phi(i) = 2*pi*(i-N/2)/N;
-    [x(i),y(i)] = cordic_rot(0, 1, phi(i), Nmax, 0);
-end;
-close all;
-figure
-plot(1:N, x, 1:N, y);
-legend('x','y')
-grid;
-
-% Vector mode
-disp('Magnitude and phase:')
-for i=1:N,
-    [mag(i), phi(i)] = cordic_vec(x(i), y(i), Nmax, 0);
-end;
-figure
-plot(1:N, mag, 1:N, phi);
-legend('Magnitude','Phase')
-grid;
-
-
-% ------------------------------------------------------------
-function [mag, phi] = cordic_cart2polar(x, y, Nmax, doplot)
-    [mag, phi] = cordic_vec(x, y, Nmax, doplot);
-  
-% ------------------------------------------------------------
-function [x, y] = cordic_polar2cart(mag, phi, Nmax, doplot)
-    [mag, phi] = cordic_vec(x, y, Nmax, doplot);
-  
-% ------------------------------------------------------------
-function [xout, yout] = cordic_rot(xin, yin, phi, N, doplot)
-
-    % Initialize
-    arctan_tbl = atan(2.^-(0:N-1));
-    gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
-
-    coeffs = arctan_tbl';
-    gains = gain_tbl';
-
-    % Calculate initial rotation
-    if (phi < (-pi/2))
-        z = phi + pi;
-        x = -xin;
-        y = -yin;
-    else
-        if (phi > pi/2)
-            z = phi - pi;
-            x = -xin;
-            y = -yin;
-        else
-            x = xin;
-            y = yin;
-            z = phi;
-        end;
-    end;
-
-    % Loop
-    for i=1:N,
-        xi(i) = x;
-        yi(i) = y;
-        zi(i) = z;
-    
-        S = 2^(-(i-1));
-        if (z < 0)
-			t = x + y*S;
-			y = y - x*S;
-			z = z + arctan_tbl(i);
-			x = t;
-        else
-			t = x - y*S;
-			y = y + x*S;
-			z = z - arctan_tbl(i);
-			x = t;
-        end;
-        
-    end;
-
-    % Result
-    k = gain_tbl(i);
-    xout = k*x;
-    yout = k*y;
-
-    % Output
-    if(doplot)
-        close all;
-        figure(1);
-        plot(1:N, xi, 1:N, yi, 1:N, zi)
-        legend('x','y','z');
-        title('Convergence');
-        grid;
-
-        figure(2);
-        plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
-        title('Polar plot');
-        grid;
-    end;
-
-% ------------------------------------------------------------
-function [mag, phi] = cordic_vec(xin, yin, N, doplot)
-
-    % Initialize
-    arctan_tbl = atan(2.^-(0:N-1));
-    gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1))));
-
-    coeffs = arctan_tbl';
-    gains = gain_tbl';
-    
-    % Calculate initial rotation
-    if (xin < 0)
-        x = -xin;
-        y = -yin;
-        if (yin < 0)
-            z = -pi;
-        else
-            z = pi;
-        end;
-    else
-        x = xin;
-        y = yin;
-        z = 0;
-    end;
-  
-    % Loop
-    for i=1:N,
-        xi(i) = x;
-        yi(i) = y;
-        zi(i) = z;
-    
-        S = 2^(-(i-1));
-        if (y < 0)
-			t = x - y*S;
-			y = y + x*S;
-			z = z - arctan_tbl(i);
-			x = t;
-        else
-			t = x + y*S;
-			y = y - x*S;
-			z = z + arctan_tbl(i);
-			x = t;
-        end;
-        
-    end;
-
-    % Result
-    k = gain_tbl(i);
-    mag = k*x;
-    phi = z;
-    
-    % Output
-    if(doplot)
-        close all;
-        figure(1);
-        plot(1:N, xi, 1:N, yi, 1:N, zi)
-        legend('x','y','z');
-        title('Convergence');
-        grid;
-
-        figure(2);
-        plot(xi.*gain_tbl, yi.*gain_tbl, '-x')
-        title('Polar plot');
-        grid;
-    end;
-    
\ No newline at end of file
diff --git a/lib/radio/cordic/sim/eval_cordic.m b/lib/radio/cordic/sim/eval_cordic.m
deleted file mode 100644
index dc42068..0000000
--- a/lib/radio/cordic/sim/eval_cordic.m
+++ /dev/null
@@ -1,10 +0,0 @@
-% function eval_cordic(x0,y0,z0, mode)
-function eval_cordic(x0,y0,z0, mode)
-
-if (mode == 'rot')
-    Xn = x0*cos(z0) - y0*sin(z0)
-    Yn = y0*cos(z0) + x0*sin(z0)
-else    
-    Xn = sqrt(x0^2 + y0^2)
-    Yn = z0 + atan(y0/x0)
-end;
\ No newline at end of file
diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo
deleted file mode 100644
index 562789d..0000000
--- a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo
+++ /dev/null
@@ -1,18 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/cordic_pkg.vhd"
-vcom -explicit  -93 "../src/cordic_pipe_stage.vhd"
-vcom -explicit  -93 "../src/cordic_pipe_pre.vhd"
-vcom -explicit  -93 "../src/cordic_pipe_post.vhd"
-vcom -explicit  -93 "../src/cordic_pipe_top.vhd"
-vcom -explicit  -93 "../src/tb_cordic_pipe_top.vhd"
-vsim -t 1ps   -lib work tb_cordic_pipe_top
-do {tb_cordic_pipe_top.wdo}
-view wave
-view structure
-view signals
-run 2000us
diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo
deleted file mode 100644
index 3e65178..0000000
--- a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo
+++ /dev/null
@@ -1,37 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cordic_pipe_top/clk
-add wave -noupdate -format Logic /tb_cordic_pipe_top/rst
-add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zout
-add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_out
-add wave -noupdate -divider {Pre stage}
-add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_in
-add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zin
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yout
-add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {10770000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {48466483 ps}
diff --git a/lib/radio/cordic/sim/tb_cordic_top.fdo b/lib/radio/cordic/sim/tb_cordic_top.fdo
deleted file mode 100644
index 1cb5c84..0000000
--- a/lib/radio/cordic/sim/tb_cordic_top.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/cordic_pkg.vhd"
-vcom -explicit  -93 "../src/cordic_rom.vhd"
-vcom -explicit  -93 "../src/cordic_stage.vhd"
-vcom -explicit  -93 "../src/cordic_stage_pre.vhd"
-vcom -explicit  -93 "../src/cordic_stage_post.vhd"
-vcom -explicit  -93 "../src/cordic_top.vhd"
-vcom -explicit  -93 "../src/tb_cordic_top.vhd"
-vsim -t 1ps   -lib work tb_cordic_top
-do {tb_cordic_top.wdo}
-view wave
-view structure
-view signals
-run 2000us
diff --git a/lib/radio/cordic/sim/tb_cordic_top.wdo b/lib/radio/cordic/sim/tb_cordic_top.wdo
deleted file mode 100644
index 6cec344..0000000
--- a/lib/radio/cordic/sim/tb_cordic_top.wdo
+++ /dev/null
@@ -1,64 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider Top
-add wave -noupdate -format Literal /tb_cordic_top/uut/cordic_mode
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zout
-add wave -noupdate -format Logic /tb_cordic_top/ce
-add wave -noupdate -format Logic /tb_cordic_top/valid
-add wave -noupdate -divider {Pre stage}
-add wave -noupdate -format Literal /tb_cordic_top/uut/inst_cordic_stage_pre/cordic_mode
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zout
-add wave -noupdate -divider {Process stage}
-add wave -noupdate -format Literal /tb_cordic_top/uut/count
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/coeff
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zout
-add wave -noupdate -divider {Post stage}
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zin
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yout
-add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zout
-add wave -noupdate -divider Signals
-add wave -noupdate -format Logic /tb_cordic_top/uut/ce
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_valid
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_valid
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_ready
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_en
-add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_valid
-add wave -noupdate -format Literal /tb_cordic_top/uut/state
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1463518 ps} 0}
-configure wave -namecolwidth 184
-configure wave -valuecolwidth 124
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {655140 ps} {1967644 ps}
diff --git a/lib/radio/cordic/sim/tb_results.m b/lib/radio/cordic/sim/tb_results.m
deleted file mode 100644
index 9f68f7c..0000000
--- a/lib/radio/cordic/sim/tb_results.m
+++ /dev/null
@@ -1,34 +0,0 @@
-% Read data
-X = TEXTREAD('x.txt');
-Y = TEXTREAD('y.txt');
-Z = TEXTREAD('z.txt');
-
-% Output
-close all;
-plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, Z);
-title ('Output');
-legend('X','Y','Z');
-grid;
-
-W= 2*pi/100;
-phi = 0;
-
-xd = -cos(phi+W*(0:length(X)-1))';
-yd = -sin(phi+W*(0:length(Y)-1))';
-
-VarErrorX = var(X-xd)
-VarErrorY = var(Y-yd)
-MeanErrorX = mean(X-xd)
-MeanErrorY = mean(Y-yd)
-
-figure;
-plot(0:length(X)-1, X-xd, 0:length(Y)-1, Y-yd, 0:length(Z)-1, Z);
-title ('Error');
-legend('X - X_D','Y - Y_D', 'Z');
-grid;
-
-figure;
-plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, xd, 0:length(yd)-1, yd);
-title ('Output');
-legend('X','Y','X_D','Y_D');
-grid;
diff --git a/lib/radio/cordic/src/cordic_pipe_post.vhd b/lib/radio/cordic/src/cordic_pipe_post.vhd
deleted file mode 100644
index c1203cc..0000000
--- a/lib/radio/cordic/src/cordic_pipe_post.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_post is
-Generic
-(
-	cordic_mode		: cordic_mode_t := cordic_mode_rotate;
-	nstages			: integer := 0;
-	nbits_x			: integer := 8;
-	nbits_x_frac	: integer := 6;
-	nbits_y			: integer := 8;
-	nbits_y_frac	: integer := 6;
-	nbits_z			: integer := 8;
-	nbits_z_frac	: integer := 8
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cordic_pipe_post;
-
-architecture Behavioral of cordic_pipe_post is
-
-constant gain_x	: sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_x, nbits_x_frac), fixed_wrap, fixed_round);
-constant gain_y	: sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_y, nbits_y_frac), fixed_wrap, fixed_round);
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-cordic_proc_pre_stage: 
-	process(clk)
-	variable xi, xo			: sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
-	variable yi, yo			: sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
-	variable zi, zo			: sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
-	begin
-
-		if rising_edge(clk) then
-			vld_out <= '0';
-			if rst = '1' then
-				xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
-				yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
-				zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
-			elsif vld_in = '1' then
-
-				vld_out <= '1';
-				
-				xi := resize(xin, xi);
-				yi := resize(yin, yi);
-				zi := resize(zin, zi);
-
-				xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode);
-				yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode);
-				zo := zi;
-
-				xout	<= xo after tpd;
-				yout	<= yo after tpd;
-				zout	<= zo after tpd;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pipe_pre.vhd b/lib/radio/cordic/src/cordic_pipe_pre.vhd
deleted file mode 100644
index ae03c5e..0000000
--- a/lib/radio/cordic/src/cordic_pipe_pre.vhd
+++ /dev/null
@@ -1,137 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_pre is
-Generic
-(
-	cordic_mode		: cordic_mode_t := cordic_mode_rotate;
-	z_range			: real := pi;
-	nbits_x			: integer := 8;
-	nbits_x_frac	: integer := 6;
-	nbits_y			: integer := 8;
-	nbits_y_frac	: integer := 6;
-	nbits_z			: integer := 8;
-	nbits_z_frac	: integer := 8
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cordic_pipe_pre;
-
-architecture Behavioral of cordic_pipe_pre is
-
-constant pi_sfix 		: sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-constant pi2_sfix 		: sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-cordic_proc_pre_stage: 
-	process(clk)
-	variable xi, xo			: sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
-	variable yi, yo			: sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
-	variable zi, zo			: sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
-	begin
-
-		if rising_edge(clk) then
-			vld_out <= '0';
-			if rst = '1' then
-				xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
-				yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
-				zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
-			elsif vld_in = '1' then
-
-				vld_out <= '1';
-				
-				xi := xin;
-				yi := yin;
-				zi := zin;
-
-				xo := xi;
-				yo := yi;
-				zo := zi;
-
-				if (zi < -pi2_sfix) then
-					xo := resize(-xi, xo);
-					yo := resize(-yi, yo);
-					zo := resize(zi + pi_sfix, zo);
-				elsif (zi > pi2_sfix) then
-					xo := resize(-xi, xo);
-					yo := resize(-yi, yo);
-					zo := resize(zi - pi_sfix, zo);
-				end if;
-				
-				xout	<= xo after tpd;
-				yout	<= yo after tpd;
-				zout	<= zo after tpd;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
-
--- if (y < 0) then
--- 	x' = -y
--- 	y' =  x
--- 	z' = z + pi/2;
--- else
--- 	x' =  y
--- 	y' = -x
--- 	z' = z - pi/2;
--- end if;
--- 
--- if (x < 0) then
--- 	x' = -x;
--- 	y' = -y;
--- 	z' = z - pi
--- else
--- 	x' = x;
--- 	y' = y;
--- 	z' = z
--- end if;
diff --git a/lib/radio/cordic/src/cordic_pipe_stage.vhd b/lib/radio/cordic/src/cordic_pipe_stage.vhd
deleted file mode 100644
index 0428f8a..0000000
--- a/lib/radio/cordic/src/cordic_pipe_stage.vhd
+++ /dev/null
@@ -1,115 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_pipe_stage is
-Generic
-(
-	cordic_mode		: cordic_mode_t := cordic_mode_rotate;
-	z_range			: real := pi;
-	stage_num		: integer := 0;
-	nbits_x			: integer := 8;
-	nbits_x_frac	: integer := 6;
-	nbits_y			: integer := 8;
-	nbits_y_frac	: integer := 6;
-	nbits_z			: integer := 8;
-	nbits_z_frac	: integer := 8
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cordic_pipe_stage;
-
-architecture Behavioral of cordic_pipe_stage is
-
-constant coeff	: sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round);
-
-begin
-
-------------------------------------------------------------
-cordic_proc_stage: 
-	process(clk)
-	variable xi, xt, xo		: sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac));
-	variable yi, yt, yo		: sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac));
-	variable zi, zo			: sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac));
-
-	begin
-
-		if rising_edge(clk) then
-			vld_out <= '0';
-			if rst = '1' then
-				xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0');
-				yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0');
-				zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0');
-			elsif vld_in = '1' then
-
-				vld_out <= '1';
-				
-				xi := xin;
-				yi := yin;
-				zi := zin;
-
-				xt := xi sra stage_num;
-				yt := yi sra stage_num;
-
-				if zi(zi'high) = '1' then
-					xo := resize(xi + yt, xo);
-					yo := resize(yi - xt, yo);
-					zo := resize(zi + coeff, zo);
-				else
-					xo := resize(xi - yt, xo);
-					yo := resize(yi + xt, yo);
-					zo := resize(zi - coeff, zo);
-				end if;
-				
-				xout	<= xo after tpd;
-				yout	<= yo after tpd;
-				zout	<= zo after tpd;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pipe_top.vhd b/lib/radio/cordic/src/cordic_pipe_top.vhd
deleted file mode 100644
index e4b73f8..0000000
--- a/lib/radio/cordic/src/cordic_pipe_top.vhd
+++ /dev/null
@@ -1,319 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:52:30 10/02/05
--- Design Name:    
--- Module Name:    cordic_top - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity cordic_pipe_top is
-Generic
-(
-	cordic_mode			: cordic_mode_t := cordic_mode_rotate;
-	z_range				: real := 1.0;
-	gain_corr_mode		: gain_corr_mode_t := gain_mode_disabled;
-	nstages				: integer := 18;
-	nbits_x_in			: integer := 18;
-	nbits_y_in			: integer := 18;
-	nbits_z_in			: integer := 18;
-	nbits_frac_x_in		: integer := 16;
-	nbits_frac_y_in		: integer := 16;
-	nbits_frac_z_in		: integer := 16;
-	nbits_x_out			: integer := 18;
-	nbits_y_out			: integer := 18;
-	nbits_z_out			: integer := 18;
-	nbits_frac_x_out	: integer := 17;
-	nbits_frac_y_out	: integer := 17;
-	nbits_frac_z_out	: integer := 17
-);
-Port 
-( 
-	rst		: in std_logic;
-	clk		: in std_logic;
-	vld_in	: in std_logic;
-	xin		: in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in));
-	yin		: in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in));
-	zin		: in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in));
-	xout	: out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
-	yout	: out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
-	zout	: out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
-	vld_out	: out std_logic
-);
-end cordic_pipe_top;
-
-architecture Behavioral of cordic_pipe_top is
-
------------------------------------------------------------------------
-COMPONENT cordic_pipe_pre is
-GENERIC
-(
-	cordic_mode		: cordic_mode_t;
-	z_range			: real;
-	nbits_x			: integer;
-	nbits_x_frac	: integer;
-	nbits_y			: integer;
-	nbits_y_frac	: integer;
-	nbits_z			: integer;
-	nbits_z_frac	: integer
-);
-PORT(
-	rst			: IN std_logic;
-	clk			: IN std_logic;
-	vld_in		: IN std_logic;
-	xin			: IN sfixed;
-	yin			: IN sfixed;
-	zin			: IN sfixed;
-	xout		: OUT sfixed;
-	yout		: OUT sfixed;
-	zout		: OUT sfixed;
-	vld_out		: out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_pipe_stage
-GENERIC
-(
-	cordic_mode		: cordic_mode_t;
-	z_range			: real;
-	stage_num		: integer;
-	nbits_x			: integer;
-	nbits_x_frac	: integer;
-	nbits_y			: integer;
-	nbits_y_frac	: integer;
-	nbits_z			: integer;
-	nbits_z_frac	: integer
-);
-PORT(
-	rst			: IN std_logic;
-	clk			: IN std_logic;
-	vld_in		: IN std_logic;
-	xin			: IN sfixed;
-	yin			: IN sfixed;
-	zin			: IN sfixed;
-	xout		: OUT sfixed;
-	yout		: OUT sfixed;
-	zout		: OUT sfixed;
-	vld_out		: out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_pipe_post is
-GENERIC
-(
-	cordic_mode		: cordic_mode_t;
-	nstages			: integer;
-	nbits_x			: integer;
-	nbits_x_frac	: integer;
-	nbits_y			: integer;
-	nbits_y_frac	: integer;
-	nbits_z			: integer;
-	nbits_z_frac	: integer
-);
-PORT(
-	rst			: IN std_logic;
-	clk			: IN std_logic;
-	vld_in		: IN std_logic;
-	xin			: IN sfixed;
-	yin			: IN sfixed;
-	zin			: IN sfixed;
-	xout		: OUT sfixed;
-	yout		: OUT sfixed;
-	zout		: OUT sfixed;
-	vld_out		: out std_logic
-);
-END COMPONENT;
-
------------------------------------------------------------------------
-
--- Define number of internal stage bits
-constant stage_x_nbits			: integer := nbits_x_in			+ integer(log2(real(nbits_x_in))+0.5);
-constant stage_x_nbits_frac		: integer := nbits_frac_x_in	+ integer(log2(real(nbits_x_in))+0.5);
-constant stage_y_nbits			: integer := nbits_y_in			+ integer(log2(real(nbits_y_in))+0.5);
-constant stage_y_nbits_frac		: integer := nbits_frac_y_in	+ integer(log2(real(nbits_y_in))+0.5);
-constant stage_z_nbits			: integer := nbits_z_in			+ integer(log2(real(nbits_z_in))+0.5);
-constant stage_z_nbits_frac		: integer := nbits_frac_z_in	+ integer(log2(real(nbits_z_in))+0.5);
-
--- INPUT
--- Input pre stage
-signal pre_xin	: sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-signal pre_yin	: sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-signal pre_zin	: sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-signal pre_xout	: sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-signal pre_yout	: sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-signal pre_zout	: sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-
--- Input processing stage
-subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac));
-subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac));
-subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac));
-type stage_x_array_t is array(0 to nstages) of stage_x_t;
-type stage_y_array_t is array(0 to nstages) of stage_y_t;
-type stage_z_array_t is array(0 to nstages) of stage_z_t;
-
-signal stage_vld: unsigned(0 to nstages);
-signal stage_x 			: stage_x_array_t;
-signal stage_y			: stage_y_array_t;
-signal stage_z			: stage_z_array_t;
- 
--- Output post stage
-signal post_xin		: sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
-signal post_yin		: sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
-signal post_zin		: sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
-signal post_xout	: sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out));
-signal post_yout	: sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out));
-signal post_zout	: sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out));
-signal post_vld		: std_logic;
-
-begin
-
-	pre_xin			<= resize(xin, pre_xin);
-	pre_yin			<= resize(yin, pre_yin);
-	pre_zin			<= resize(zin, pre_zin);
-
-	stage_x(0)		<= resize(pre_xout, stage_x(0));
-	stage_y(0)		<= resize(pre_yout, stage_y(0));
-	stage_z(0)		<= resize(pre_zout, stage_z(0));
-
-	post_xin		<= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode);
-	post_yin		<= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode);
-	post_zin		<= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode);
-
-gen_output_unity:
-	if gain_corr_mode = gain_mode_unity generate
-	begin
-		xout			<= post_xout;
-		yout			<= post_yout;
-		zout			<= post_zout;
-		vld_out			<= post_vld;
-	end generate;
-	
-gen_output_disabled:
-	if gain_corr_mode = gain_mode_disabled generate
-	begin
-		xout			<= post_xin;
-		yout			<= post_yin;
-		zout			<= post_zin;
-		vld_out			<= stage_vld(nstages);
-	end generate;
-	
------------------------------------------------------------------------
-Inst_cordic_pipe_pre: cordic_pipe_pre 
-GENERIC MAP
-(
-	cordic_mode		=> cordic_mode_rotate,
-	z_range			=> z_range,
-	nbits_x			=> stage_x_nbits,
-	nbits_x_frac	=> stage_x_nbits_frac,
-	nbits_y			=> stage_y_nbits,
-	nbits_y_frac	=> stage_y_nbits_frac,
-	nbits_z			=> stage_z_nbits,
-	nbits_z_frac	=> stage_z_nbits_frac
-)
-PORT MAP
-(
-	rst				=> rst,
-	clk				=> clk,
-	vld_in			=> vld_in,
-	xin				=> pre_xin,
-	yin				=> pre_yin,
-	zin				=> pre_zin,
-	xout			=> pre_xout,
-	yout			=> pre_yout,
-	zout			=> pre_zout,
-	vld_out			=> stage_vld(0)
-);
-
-gen_pipe:
-	for i in 1 to nstages generate
-	
-	Inst_cordic_pipe: cordic_pipe_stage 
-	GENERIC MAP
-	(
-		cordic_mode		=> cordic_mode_rotate,
-		z_range			=> z_range,
-		stage_num		=> i-1,
-		nbits_x			=> stage_x_nbits,
-		nbits_x_frac	=> stage_x_nbits_frac,
-		nbits_y			=> stage_y_nbits,
-		nbits_y_frac	=> stage_y_nbits_frac,
-		nbits_z			=> stage_z_nbits,
-		nbits_z_frac	=> stage_z_nbits_frac
-	)
-	PORT MAP
-	(
-		rst				=> rst,
-		clk				=> clk,
-		vld_in			=> stage_vld(i-1),
-		xin				=> stage_x(i-1),
-		yin				=> stage_y(i-1),
-		zin				=> stage_z(i-1),
-		xout			=> stage_x(i),
-		yout			=> stage_y(i),
-		zout			=> stage_z(i),
-		vld_out			=> stage_vld(i)
-	);
-
-	end generate;
-	
-gen_post_process:
-	if gain_corr_mode = gain_mode_unity generate
-	begin
-
-	Inst_cordic_pipe_post: cordic_pipe_post
-	GENERIC MAP
-	(
-		cordic_mode		=> cordic_mode_rotate,
-		nstages			=> nstages,
-		nbits_x			=> nbits_x_out,
-		nbits_x_frac	=> nbits_frac_x_out,
-		nbits_y			=> nbits_y_out,
-		nbits_y_frac	=> nbits_frac_y_out,
-		nbits_z			=> nbits_z_out,
-		nbits_z_frac	=> nbits_frac_z_out
-	)
-	PORT MAP
-	(
-		rst				=> rst,
-		clk				=> clk,
-		vld_in			=> stage_vld(nstages),
-		xin				=> post_xin,
-		yin				=> post_yin,
-		zin				=> post_zin,
-		xout			=> post_xout,
-		yout			=> post_yout,
-		zout			=> post_zout,
-		vld_out			=> post_vld
-	);
-
-	end generate;
-
---------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_pkg.vhd b/lib/radio/cordic/src/cordic_pkg.vhd
deleted file mode 100644
index d26d2b6..0000000
--- a/lib/radio/cordic/src/cordic_pkg.vhd
+++ /dev/null
@@ -1,208 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-package cordic_pkg is
-
-	constant tpd : time := 0 ns;
-
-	type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector);
-	type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout);
-	type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity);
-
-	-- Global set arithmetic rounding mode
-	constant cordic_round_mode : fixed_round_style_type := fixed_round;
-
-	-- Global set arithmetic saturating mode
-	constant cordic_saturate_mode : fixed_overflow_style_type := fixed_wrap;
-	
-	constant max_iteration : integer := 80;
-	
-	-- Normalized Arctan table (for phases z = -1..+1)
-	-- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)'
-	-- (Print format: long e, compact)
-	constant arctan_tbl : real_array_t (0 to max_iteration-1) :=
-	(
-		2.500000000000000e-001,
-		1.475836176504333e-001,
-		7.797913037736932e-002,
-		3.958342416056555e-002,
-		1.986852430554084e-002,
-		9.943947823589275e-003,
-		4.973187278950414e-003,
-		2.486745393669739e-003,
-		1.243391668714101e-003,
-		6.216982059233716e-004,
-		3.108493994100204e-004,
-		1.554247367611316e-004,
-		7.771237301258342e-005,
-		3.885618708529400e-005,
-		1.942809361502228e-005,
-		9.714046816558053e-006,
-		4.857023409409890e-006,
-		2.428511704846303e-006,
-		1.214255852440821e-006,
-		6.071279262226194e-007,
-		3.035639631115858e-007,
-		1.517819815558274e-007,
-		7.589099077791802e-008,
-		3.794549538895954e-008,
-		1.897274769447984e-008,
-		9.486373847239929e-009,
-		4.743186923619965e-009,
-		2.371593461809983e-009,
-		1.185796730904992e-009,
-		5.928983654524958e-010,
-		2.964491827262479e-010,
-		1.482245913631239e-010,
-		7.411229568156197e-011,
-		3.705614784078099e-011,
-		1.852807392039049e-011,
-		9.264036960195246e-012,
-		4.632018480097623e-012,
-		2.316009240048812e-012,
-		1.158004620024406e-012,
-		5.790023100122029e-013,
-		2.895011550061015e-013,
-		1.447505775030507e-013,
-		7.237528875152536e-014,
-		3.618764437576268e-014,
-		1.809382218788134e-014,
-		9.046911093940670e-015,
-		4.523455546970335e-015,
-		2.261727773485168e-015,
-		1.130863886742584e-015,
-		5.654319433712919e-016,
-		2.827159716856459e-016,
-		1.413579858428230e-016,
-		7.067899292141149e-017,
-		3.533949646070574e-017,
-		1.766974823035287e-017,
-		8.834874115176436e-018,
-		4.417437057588218e-018,
-		2.208718528794109e-018,
-		1.104359264397055e-018,
-		5.521796321985272e-019,
-		2.760898160992636e-019,
-		1.380449080496318e-019,
-		6.902245402481590e-020,
-		3.451122701240795e-020,
-		1.725561350620398e-020,
-		8.627806753101988e-021,
-		4.313903376550994e-021,
-		2.156951688275497e-021,
-		1.078475844137749e-021,
-		5.392379220688743e-022,
-		2.696189610344371e-022,
-		1.348094805172186e-022,
-		6.740474025860928e-023,
-		3.370237012930464e-023,
-		1.685118506465232e-023,
-		8.425592532326160e-024,
-		4.212796266163080e-024,
-		2.106398133081540e-024,
-		1.053199066540770e-024,
-		5.265995332703850e-025
-	);
-	
-	-- Gain correction table
-	-- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))'
-	-- (Print format: long e, compact)
-	constant gain_tbl : real_array_t (0 to max_iteration-1) :=
-	(
-		7.071067811865475e-001,
-		6.324555320336759e-001,
-		6.135719910778963e-001,
-		6.088339125177524e-001,
-		6.076482562561681e-001,
-		6.073517701412959e-001,
-		6.072776440935260e-001,
-		6.072591122988928e-001,
-		6.072544793325624e-001,
-		6.072533210898752e-001,
-		6.072530315291344e-001,
-		6.072529591389448e-001,
-		6.072529410413973e-001,
-		6.072529365170103e-001,
-		6.072529353859135e-001,
-		6.072529351031394e-001,
-		6.072529350324457e-001,
-		6.072529350147724e-001,
-		6.072529350103540e-001,
-		6.072529350092495e-001,
-		6.072529350089733e-001,
-		6.072529350089043e-001,
-		6.072529350088870e-001,
-		6.072529350088827e-001,
-		6.072529350088816e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001,
-		6.072529350088813e-001
-	);
-
-end; -- package cordic_pkg;
-
--------------------------------------------------------------------------------
-package body cordic_pkg is
-
-end; -- package body cordic_pkg;
diff --git a/lib/radio/cordic/src/cordic_rom.vhd b/lib/radio/cordic/src/cordic_rom.vhd
deleted file mode 100644
index 9af2ac8..0000000
--- a/lib/radio/cordic/src/cordic_rom.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:37:26 10/02/05
--- Design Name:    
--- Module Name:    coeff_rom - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity rom_arctan is
-	Generic 
-	(
-	        nbits : integer := 8;
-	        nbits_frac : integer := 8
-	);
-	Port 
-	(
-			addr : in unsigned(6 downto 0);
-			dout : out sfixed
-	);
-end rom_arctan;
-
-architecture Behavioral of rom_arctan is
-
-subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-type rom_t is array (natural range <>) of word_t;
-
--------------------------------------------------------------------------------
-function rom_gen(nstages : integer; round_mode : fixed_round_style_type) return rom_t is
-variable rom : rom_t (0 to nstages-1);
-variable word : word_t;
-begin
-
-	for i in 0 to nstages-1 loop
-		word := to_sfixed(arctan_tbl(i)*pi, word, fixed_wrap, round_mode);
-		rom(i) := word;
-	end loop;
-	
-	return rom;
-end rom_gen;
-
--------------------------------------------------------------------------------
--- Create ROM
-constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode);
-
--------------------------------------------------------------------------------
-
-begin
-
--- ROM implementation
-rom_arctan: process(addr)
-begin
-	dout <= arctan_rom(to_integer(addr));
-end process;
-
--------------------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage.vhd b/lib/radio/cordic/src/cordic_stage.vhd
deleted file mode 100644
index 26953ce..0000000
--- a/lib/radio/cordic/src/cordic_stage.vhd
+++ /dev/null
@@ -1,291 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage is
-Generic
-(
-	nbits			: integer := 8;
-	nbits_frac		: integer := 6;
-	nbits_out		: integer := 8;
-	nbits_frac_out	: integer := 6;
-	reg_mode		: reg_mode_t := reg_mode_in
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	ce			: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	coeff		: in sfixed;
-	dir_cw		: in std_logic;
-	stage_count : in integer;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: out std_logic;
-	valid 		: out std_logic
-);
-end cordic_stage;
-
-architecture Behavioral of cordic_stage is
-
-type xyz_in_t is record
-	x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
-	x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-begin
-------------------------------------------------------------
-gen_direct: if reg_mode = none generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-			
- 		else
- 			ready_r <= '1';
- 			valid_r <= ce;
- 			xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
- 			xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
- 			xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
- 
- 	reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
- 
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
-			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
- 		else
- 			ready_r <= '1';
-			valid_r <= ce;
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
- 
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
- 			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
-end generate;
-
-------------------------------------------------------------
-cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in)
-variable dir_cw_r : std_logic;
-variable stage_count_r : integer range 0 to nbits-1;
-variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
-begin
-	
-	if (rst = '1') then
-		dir_cw_r := dir_cw;
-		stage_count_r := 0;
-		x2 := zero_in_sfix;
-		y2 := zero_in_sfix;
-		xyz_out.x <= zero_out_sfix;
-		xyz_out.y <= zero_out_sfix;
-		xyz_out.z <= zero_out_sfix;
-	else
-		if (clk'event and clk = '1') then
-			dir_cw_r := dir_cw;
-			stage_count_r := stage_count;
-		end if;
-
-		x2 := xyz_in.x sra stage_count_r;
-		y2 := xyz_in.y sra stage_count_r;
-
-		if (dir_cw_r = '1') then
-			xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd;
-			xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd;
-			xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
-		else
-			xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd;
-			xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd;
-			xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd;
-		end if;
-	end if;
-end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage_post.vhd b/lib/radio/cordic/src/cordic_stage_post.vhd
deleted file mode 100644
index a17c665..0000000
--- a/lib/radio/cordic/src/cordic_stage_post.vhd
+++ /dev/null
@@ -1,279 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_post - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage_post is
-Generic
-(
-	nbits			: integer := 8;
-	nbits_frac		: integer := 6;
-	nbits_out		: integer := 8;
-	nbits_frac_out	: integer := 6;
-	reg_mode		: reg_mode_t := reg_mode_in
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	ce			: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: out std_logic;
-	valid 		: out std_logic
-);
-end cordic_stage_post;
-
-architecture Behavioral of cordic_stage_post is
-
-type xyz_in_t is record
-	x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
-	x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-------------------------------------------------------------
-begin
-
-gen_direct: if reg_mode = none generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-			
- 		else
- 			ready_r <= '1';
- 			valid_r <= ce;
-			xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-			xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-			xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
- 
- 	reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
- 
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
-			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
- 		else
- 			ready_r <= '1';
-			valid_r <= ce;
-			xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-			xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-			xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
- 
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
- 			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
- end generate;
-
-------------------------------------------------------------
-cordic_post_stage: process(xyz_in, cordic_mode)
-begin
-
-	xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-	xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-	xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
-
-	case cordic_mode is
-
-		when cordic_mode_rotate =>
-
-		xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
-		xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
-		xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
-
-		when cordic_mode_vector =>
-
-		xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode);
-		xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode);
-		xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode);
-
-		when others => null;
-
-	end case;
-end process;
-	
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/cordic_stage_pre.vhd b/lib/radio/cordic/src/cordic_stage_pre.vhd
deleted file mode 100644
index 0e9f82a..0000000
--- a/lib/radio/cordic/src/cordic_stage_pre.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cordic_stage_pre is
-Generic
-(
-	nbits			: integer := 8;
-	nbits_frac		: integer := 6;
-	nbits_out		: integer := 8;
-	nbits_frac_out	: integer := 6;
-	reg_mode		: reg_mode_t := reg_mode_in
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	ce			: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: out std_logic;
-	valid 		: out std_logic
-);
-end cordic_stage_pre;
-
-architecture Behavioral of cordic_stage_pre is
-
-type xyz_in_t is record
-	x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-end record;
-
-type xyz_out_t is record
-	x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-end record;
-
-constant zero_in_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-constant zero_out_sfix 		: sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi_out_sfix 		: sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi2_out_sfix 		: sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-constant pi2_in_sfix 		: sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-
-signal xyz_in : xyz_in_t;
-signal xyz_out : xyz_out_t;
-signal valid_r, ready_r : std_logic;
-
-------------------------------------------------------------
-begin
-
-gen_direct: if reg_mode = none generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-			
- 		else
- 			ready_r <= '1';
- 			valid_r <= ce;
-			xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-			xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-			xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
- 
- 	reg_out : process (rst, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
- 
-end generate;
-------------------------------------------------------------
-
-gen_reg_in: if (reg_mode = reg_mode_in) generate
-
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
-			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		else
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			xout <= xyz_out.x;
- 			yout <= xyz_out.y;
- 			zout <= xyz_out.z;
- 		end if;	
- 	end process;
-
-end generate;
-
-------------------------------------------------------------
-gen_reg_out: if (reg_mode = reg_mode_out) generate
- 
- 	reg_in : process (rst, ce, xin, yin, zin)
- 	begin
- 		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
- 		else
- 			ready_r <= '1';
-			valid_r <= ce;
-			xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-			xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-			xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
- 		end if;	
- 	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
-end generate;
-
-------------------------------------------------------------
-gen_reg_inout: if (reg_mode = reg_mode_inout) generate
- 
-	reg_in : process (rst, clk, ce, xin, yin, zin)
-	begin
-		if (rst = '1') then
- 			ready_r <= '0';
- 			valid_r <= '0';
-			xyz_in.x <= zero_in_sfix;
-			xyz_in.y <= zero_in_sfix;
-			xyz_in.z <= zero_in_sfix;
-		elsif rising_edge(clk) then
- 			ready_r <= '1';
-			valid_r <= ce;
-			if (ce = '1') then
-				xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right);
-				xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right);
-				xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right);
-			end if;
-		end if;	
-	end process;
-
- 	reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out)
- 	begin
- 		if (rst = '1') then
- 			ready <= '0';
- 			valid <= '0';
- 			xout <= zero_out_sfix;
- 			yout <= zero_out_sfix;
- 			zout <= zero_out_sfix;
- 		elsif rising_edge(clk) then
- 			ready <= ready_r;
- 			valid <= valid_r;
- 			if (ce = '1') then
- 				xout <= xyz_out.x;
- 				yout <= xyz_out.y;
- 				zout <= xyz_out.z;
- 			end if;
- 		end if;	
- 	end process;
- 
- end generate;
-
-------------------------------------------------------------
-cordic_proc_pre_stage: process(xyz_in, cordic_mode)
-begin
-
-	xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-	xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-	xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right);
-
-	case cordic_mode is
-
-		when cordic_mode_rotate =>
-
-		if (xyz_in.z < -pi2_in_sfix) then
-			xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-			xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-			xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
-		elsif (xyz_in.z > pi2_in_sfix) then
-			xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
-			xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
-			xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
-		end if;
-
-
-		when cordic_mode_vector =>
-
--- 		if (xyz_in.x < zero_in_sfix) then
---			xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right);
--- 			xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right);
--- 			xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right);
---   		end if;
-		if (xyz_in.y < zero_in_sfix) then
-  			xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right);
-  			xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right);
-  			xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
-  		else	
-  			xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right);
-  			xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right);
-  			xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right);
-  		end if;
-
-		when others => null;
-
-	end case;
-end process;
-	
-------------------------------------------------------------
-end Behavioral;
-
--- if (y < 0) then
--- 	x' = -y
--- 	y' =  x
--- 	z' = z + pi/2;
--- else
--- 	x' =  y
--- 	y' = -x
--- 	z' = z - pi/2;
--- end if;
--- 
--- if (x < 0) then
--- 	x' = -x;
--- 	y' = -y;
--- 	z' = z - pi
--- else
--- 	x' = x;
--- 	y' = y;
--- 	z' = z
--- end if;
diff --git a/lib/radio/cordic/src/cordic_top.vhd b/lib/radio/cordic/src/cordic_top.vhd
deleted file mode 100644
index 8f41847..0000000
--- a/lib/radio/cordic/src/cordic_top.vhd
+++ /dev/null
@@ -1,466 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    11:52:30 10/02/05
--- Design Name:    
--- Module Name:    cordic_top - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity cordic_top is
-Generic
-(
-	nbits			: integer := 8;
-	nbits_frac		: integer := 6;
-	nbits_out		: integer := 8;
-	nbits_frac_out	: integer := 6
-);
-Port ( 
-	rst : in std_logic;
-	clk : in std_logic;
-	ce : in std_logic;
-	xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-	xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	ready : out std_logic;
-	valid : out std_logic;
-	cordic_mode	: in cordic_mode_t
-);
-end cordic_top;
-
-architecture Behavioral of cordic_top is
-
------------------------------------------------------------------------
-COMPONENT cordic_stage_pre is
-GENERIC
-(
-	nbits			: integer;
-	nbits_frac		: integer;
-	nbits_out		: integer;
-	nbits_frac_out	: integer;
-	reg_mode		: reg_mode_t
-);
-PORT
-(
-	rst			: in std_logic;
-	clk			: in std_logic;
-	ce			: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: OUT std_logic;
-	valid 		: out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_stage
-GENERIC
-(
-	nbits			: integer;
-	nbits_frac		: integer;
-	nbits_out		: integer;
-	nbits_frac_out	: integer;
-	reg_mode		: reg_mode_t
-);
-PORT(
-	rst			: IN std_logic;
-	clk			: IN std_logic;
-	ce			: IN std_logic;
-	xin			: IN sfixed;       
-	yin			: IN sfixed;
-	zin			: IN sfixed;
-	xout		: OUT sfixed;
-	yout		: OUT sfixed;
-	zout		: OUT sfixed;
-	coeff		: in sfixed;
-	dir_cw		: in std_logic;
-	stage_count	: IN integer;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: OUT std_logic;
-	valid 		: out std_logic
-);
-END COMPONENT;
-
-COMPONENT cordic_stage_post is
-GENERIC
-(
-	nbits			: integer;
-	nbits_frac		: integer;
-	nbits_out		: integer;
-	nbits_frac_out	: integer;
-	reg_mode		: reg_mode_t
-);
-PORT
-(
-	rst			: in std_logic;
-	clk			: in std_logic;
-	ce			: in std_logic;
-	xin			: in sfixed;
-	yin			: in sfixed;
-	zin			: in sfixed;
-	xout		: out sfixed;
-	yout		: out sfixed;
-	zout		: out sfixed;
-	cordic_mode	: in cordic_mode_t;
-	ready 		: OUT std_logic;
-	valid 		: out std_logic
-);
-END COMPONENT;
-
-COMPONENT rom_arctan is
-GENERIC 
-(
-	nbits		: integer := 8;
-	nbits_frac	: integer := 8
-);
-PORT 
-(
-	addr		: in unsigned(6 downto 0);
-	dout		: out sfixed
-);
-END COMPONENT;
-
------------------------------------------------------------------------
-type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out); 
-
-constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low);
-
--- Define number of LSB guard bits
-constant guard_nbits			: integer := integer(log2(real(nbits))+0.5);
-
--- Define number of internal stage bits
-constant stage_nbits			: integer := nbits + guard_nbits; -- add more internal precision
-constant stage_nbits_frac		: integer := nbits_frac;
-
--- Set number of coefficient bits
-constant coeff_nbits			: integer := nbits;
-constant coeff_nbits_frac		: integer := nbits; -- coeffs have no integer part
-
--- Set number of iteration with respect to bit size
-constant max_stage_count 		: integer := stage_nbits;
-
--- INPUT
--- Input pre stage
-signal pre_stage_en : std_logic;
-signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
--- Output pre stage
-signal pre_stage_ready, pre_stage_valid : std_logic;
-signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Input processing stage
-signal proc_stage_en: std_logic;
-signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Output processing stage
-signal proc_stage_ready, proc_stage_valid : std_logic;
-signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Input post stage
-signal post_stage_en : std_logic;
-signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low);
-
--- Output post stage
-signal post_stage_ready, post_stage_valid : std_logic;
-signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low);
-
--- ROM
-signal rom_addr : unsigned (6 downto 0);
-signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low);
-
--- Misc.
-signal state, next_state : state_type; 
-signal count : integer range 0 to max_stage_count-1 := 0;
-signal count_en, dir_cw, valid_s : std_logic;
-
-
-begin
-
------------------------------------------------------------------------
-cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode)
-
-begin
-	
-	if (rst = '1') then
-		dir_cw <= '0';
-	else
-		dir_cw <= '0';
-		case cordic_mode is
-
-			when cordic_mode_rotate =>
-				if (zin_stage(zin_stage'high) = '1') then 
-					dir_cw <= '1';
-				end if;
-				
-			when cordic_mode_vector =>
-				if (yin_stage(yin_stage'high) = '1') then 
-					dir_cw <= '0';
-				else	
-					dir_cw <= '1';
-				end if;
-				
-			when others => null;
-
-		end case;
-	end if;
-end process;
-	
------------------------------------------------------------------------
-counter: process (clk, rst, count, count_en)
-begin
-	if (rst = '1') then
-		count <= 0;
-		rom_addr <= (others => '0');
-	else
-		if (clk'event and clk = '1') then
-			rom_addr <= to_unsigned(count, rom_addr'length);
-			if (count_en = '1' and count < max_stage_count-1) then
-				count <= count + 1 after tpd;
-			else
-				count <= 0;
-			end if;
-		end if;
-	end if;
-end process;
-
------------------------------------------------------------------------
-OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage)
-begin
-	if (rst='1') then
-		valid <= '0';
-		xout <= zero_sfix after tpd;
-		yout <= zero_sfix after tpd;
-		zout <= zero_sfix after tpd;
-
-	 -- assign other outputs to reset value      
-	elsif (clk'event and clk = '1') then
-		valid <= '0';
-		if(post_stage_valid = '1') then
-			xout <= xout_post;
-			yout <= yout_post;
-			zout <= zout_post;
-			valid <= '1';
-		end if;
-  end if;
-end process;
-
------------------------------------------------------------------------
---Insert the following in the architecture after the begin keyword
-   FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage)
-   begin
-      if (rst='1') then
-      	state <= st_ready;
-         -- assign other outputs to reset value      
-      elsif (clk'event and clk = '1') then
-         state <= next_state after tpd;
-         -- assign other outputs to internal signals        
-      end if;
-   end process;
- 
-   --MOORE State Machine - Outputs based on state only
-Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage)
-begin
-      --insert statements to decode internal output signals
-      --below is simple example
-	ready <= '0';
-	valid_s <= '0';
-	count_en <= '0';
-	pre_stage_en <= '0';
-	proc_stage_en <= '0';
-	post_stage_en <= '0';
-
-	xin_pre <= xin;
-	yin_pre <= yin;
-	zin_pre <= zin;
-	xin_stage <= xout_stage;
-	yin_stage <= yout_stage;
-	zin_stage <= zout_stage;
-	xin_post <= xout_stage;
-	yin_post <= yout_stage;
-	zin_post <= zout_stage;
-	
-	case (state) is
-	when st_ready =>
-		ready <= '1';
-	when st_pre_stage_in =>
-		pre_stage_en <= '1';
-	when st_pre_stage_out =>
-		count_en <= '1';
-		proc_stage_en <= '1';
-		xin_stage <= xout_pre;
-		yin_stage <= yout_pre;
-		zin_stage <= zout_pre;
-	when st_proc_stage_in =>
-		count_en <= '1';
-		proc_stage_en <= '1';
-	when st_post_stage_in =>
-		post_stage_en <= '1';
-		
-	when others =>
-	end case;      
-end process;
- 
-NEXT_STATE_DECODE: process (state, ce, count)
-begin
-	--declare default state for next_state to avoid latches
-	next_state <= state;  --default is to stay in current state
-	--insert statements to decode next_state
-	--below is a simple example
-	case (state) is
-	 when st_ready =>
-		if ce = '1' then
-		   next_state <= st_input;
-		end if;
-
-	 when st_input =>
-		if ce = '0' then
-		   next_state <= st_pre_stage_in;
-		end if;
-
-	 when st_pre_stage_in =>
-		next_state <= st_pre_stage_out;
-
-	 when st_pre_stage_out =>
-		next_state <= st_proc_stage_in;
-
-	 when st_proc_stage_in =>
-		if (count = max_stage_count-2) then
-			next_state <= st_post_stage_in;
-		end if;
-
-	 when st_post_stage_in =>
-		next_state <= st_ready;
-
-	 when others =>
-		next_state <= st_ready;
-		
-	end case;      
-end process;
-
------------------------------------------------------------------------
-Inst_cordic_stage_pre: cordic_stage_pre 
-GENERIC MAP
-(
-	nbits => nbits,
-	nbits_frac => nbits_frac,
-	nbits_out => stage_nbits,
-	nbits_frac_out => stage_nbits_frac,
-	reg_mode => reg_mode_in
-)
-PORT MAP
-(
-	rst => rst,
-	clk => clk,
-	ce => pre_stage_en,
-	xin => xin_pre,
-	yin => yin_pre,
-	zin => zin_pre,
-	xout => xout_pre,
-	yout => yout_pre,
-	zout => zout_pre,
-	ready => pre_stage_ready,
-	valid => pre_stage_valid,
-	cordic_mode => cordic_mode
-);
-
-Inst_cordic_stage: cordic_stage 
-GENERIC MAP
-(
-	nbits => stage_nbits,
-	nbits_frac => stage_nbits_frac,
-	nbits_out => stage_nbits,
-	nbits_frac_out => stage_nbits_frac,
-	reg_mode => reg_mode_in
-)
-PORT MAP
-(
-	rst => rst,
-	clk => clk,
-	ce => proc_stage_en,
-	xin => xin_stage,
-	yin => yin_stage,
-	zin => zin_stage,
-	xout => xout_stage,
-	yout => yout_stage,
-	zout => zout_stage,
-	coeff => rom_data,
-	dir_cw => dir_cw,
-	stage_count => count,
-	ready => proc_stage_ready,
-	valid => proc_stage_valid,
-	cordic_mode => cordic_mode
-);
-
-Inst_cordic_stage_post: cordic_stage_post
-GENERIC MAP
-(
-	nbits => stage_nbits,
-	nbits_frac => stage_nbits_frac,
-	nbits_out => nbits_out,
-	nbits_frac_out => nbits_frac_out,
-	reg_mode => reg_mode_in
-)
-PORT MAP
-(
-	rst => rst,
-	clk => clk,
-	ce => post_stage_en,
-	xin => xin_post,
-	yin => yin_post,
-	zin => zin_post,
-	xout => xout_post,
-	yout => yout_post,
-	zout => zout_post,
-	ready => post_stage_ready,
-	valid => post_stage_valid,
-	cordic_mode => cordic_mode
-);
-
-Inst_rom_arctan: rom_arctan
-GENERIC MAP
-(
-	nbits		=> coeff_nbits,
-	nbits_frac	=> coeff_nbits_frac
-)
-PORT MAP
-(
-	addr		=> rom_addr,
-	dout		=> rom_data
-);
-
---------------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd b/lib/radio/cordic/src/tb_cordic_pipe_top.vhd
deleted file mode 100644
index c88dd33..0000000
--- a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd
+++ /dev/null
@@ -1,653 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 10/02/2005
--- Design Name:   cordic_top
--- Module Name:   tb_cordic_top.vhd
--- Project Name:  cordic
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: cordic_top
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
--- Results:In 16i2 and Out 16i0
-------------------------------
--- xmean = -3.051757808671257e-7
--- ymean = 1.525878906192144e-6
--- zmean = 0.0
--- xvar  = 7.723598281502283e-10
--- yvar  = 8.539443970667266e-10
--- zvar  = 0.0
--- xstd  = 2.779136247380161e-5
--- ystd  = 2.922232703031582e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i1
-------------------------------
--- xmean = 6.103515628828741e-7
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar  = 9.76293486677989e-10
--- yvar  = 7.934037490259732e-10
--- zvar  = 0.0
--- xstd  = 3.124569549038697e-5
--- ystd  = 2.816742354256017e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i2
-------------------------------
--- xmean = 2.441406250382875e-6
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar  = 2.126680036682826e-9
--- yvar  = 2.117107754473399e-9
--- zvar  = 0.0
--- xstd  = 4.611594124251206e-5
--- ystd  = 4.601203923402438e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i0
-------------------------------
--- xmean = -9.312842871812748e-12 
--- ymean = -5.78558739545293e-17 
--- zmean = 0.0 
--- xvar  = 1.671709854744817e-19 
--- yvar  = 1.790442305004033e-19 
--- zvar  = 0.0 
--- xstd  = 4.088654857951228e-10 
--- ystd  = 4.231361843430591e-10 
--- zstd  = 0.0 
---
-------------------------------
--- Results:In 32i2 and Out 32i1
-------------------------------
--- xmean = 9.313608620496825e-12
--- ymean = 9.31316789028083e-12
--- zmean = 0.0
--- xvar  = 1.876480788588237e-19
--- yvar  = 2.238344116260579e-19
--- zvar  = 0.0
--- xstd  = 4.331836548841885e-10
--- ystd  = 4.731114156581492e-10
--- zstd  = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i2
-------------------------------
--- xmean = -3.72525201102771e-11
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar  = 5.458335981037092e-19
--- yvar  = 5.704280631341228e-19
--- zvar  = 0.0
--- xstd  = 7.388055211648797e-10
--- ystd  = 7.552668820583376e-10
--- zstd  = 0.0
---
-------------------------------
--- Results:In 64i2 and Out 64i0
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar  = 5.54111959258452e-28
--- yvar  = 5.549496221074054e-28
--- zvar  = 7.916891206490056e-29
--- xstd  = 2.353958281827551e-14
--- ystd  = 2.355736874329146e-14
--- zstd  = 8.897691389619023e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i1
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar  = 5.541120861185077e-28
--- yvar  = 5.549497432144743e-28
--- zvar  = 7.916856202525234e-29
--- xstd  = 2.353958551288674e-14
--- ystd  = 2.355737131376237e-14
--- zstd  = 8.897671719346156e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i2
-------------------------------
--- xmean = 3.343164503913365e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205223850748616e-16
--- xvar  = 5.540559656182732e-28
--- yvar  = 5.549495010008071e-28
--- zvar  = 7.916821581863743e-29
--- xstd  = 2.353839343749427e-14
--- ystd  = 2.355736617283025e-14
--- zstd  = 8.897652264425568e-15
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cordic_pipe_top IS
-	Generic (
-			nbits_x_in			: integer := 18;
-			nbits_y_in			: integer := 18;
-			nbits_z_in			: integer := 24;
-			nbits_frac_x_in		: integer := 17;
-			nbits_frac_y_in		: integer := 17;
-			nbits_frac_z_in		: integer := 22;
-			nbits_x_out			: integer := 18;
-			nbits_y_out			: integer := 18;
-			nbits_z_out			: integer := 18;
-			nbits_frac_x_out	: integer := 17;
-			nbits_frac_y_out	: integer := 17;
-			nbits_frac_z_out	: integer := 17
-	        );
-END tb_cordic_pipe_top;
-
-ARCHITECTURE behavior OF tb_cordic_pipe_top IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cordic_pipe_top
-	GENERIC 
-	(
-		cordic_mode			: cordic_mode_t;
-		z_range				: real;
-		gain_corr_mode		: gain_corr_mode_t;
-		nstages				: integer;
-		nbits_x_in			: integer;
-		nbits_y_in			: integer;
-		nbits_z_in			: integer;
-		nbits_frac_x_in		: integer;
-		nbits_frac_y_in		: integer;
-		nbits_frac_z_in		: integer;
-		nbits_x_out			: integer;
-		nbits_y_out			: integer;
-		nbits_z_out			: integer;
-		nbits_frac_x_out	: integer;
-		nbits_frac_y_out	: integer;
-		nbits_frac_z_out	: integer
-	);
-	PORT
-	(
-		rst					: in std_logic;
-		clk					: in std_logic;
-		vld_in				: in std_logic;
-		xin					: in sfixed;
-		yin					: in sfixed;
-		zin					: in sfixed;
-		xout				: out sfixed;
-		yout				: out sfixed;
-		zout				: out sfixed;
-		vld_out				: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant num_cycles : integer := 5;
-	constant num_steps_per_cycle : integer := 100;
-	constant PERIOD : time := 10 ns;
-
-	--Inputs
-	SIGNAL clk :  std_logic := '0';
-	SIGNAL rst :  std_logic := '1';
-	SIGNAL vld_in  :  std_logic := '0';
-	SIGNAL xin	: sfixed(sproto(nbits_x_in, nbits_frac_x_in)'high downto sproto(nbits_x_in, nbits_frac_x_in)'low) := to_sfixed(0.0, sproto(nbits_x_in, nbits_frac_x_in)'high, sproto(nbits_x_in, nbits_frac_x_in)'low);
-	SIGNAL yin	: sfixed(sproto(nbits_y_in, nbits_frac_y_in)'high downto sproto(nbits_y_in, nbits_frac_y_in)'low) := to_sfixed(0.0, sproto(nbits_y_in, nbits_frac_y_in)'high, sproto(nbits_y_in, nbits_frac_y_in)'low);
-	SIGNAL zin	: sfixed(sproto(nbits_z_in, nbits_frac_z_in)'high downto sproto(nbits_z_in, nbits_frac_z_in)'low) := to_sfixed(0.0, sproto(nbits_z_in, nbits_frac_z_in)'high, sproto(nbits_z_in, nbits_frac_z_in)'low);
-
-	--Outputs
-	SIGNAL xout	: sfixed(sproto(nbits_x_out, nbits_frac_x_out)'high downto sproto(nbits_x_out, nbits_frac_x_out)'low);
-	SIGNAL yout	: sfixed(sproto(nbits_y_out, nbits_frac_y_out)'high downto sproto(nbits_y_out, nbits_frac_y_out)'low);
-	SIGNAL zout	: sfixed(sproto(nbits_z_out, nbits_frac_z_out)'high downto sproto(nbits_z_out, nbits_frac_z_out)'low);
-	SIGNAL vld_out :  std_logic;
-	
-	--------------------------------------------------------------------
-	--Functions
-	--------------------------------------------------------------------
-	type real_vector_t is array (natural range <>) of real;
-	function mean(x : real_vector_t; len : integer) return real is
-	variable xm : real := 0.0;
-	begin
-		for i in 0 to len-1 loop
-			xm := xm + x(i);
-		end loop;
-		
-		return xm / real(len);
-	end mean;	
-	
-	--------------------------------------------------------------------
-	function var(x : real_vector_t; len : integer) return real is
-	variable xv, xm, xp : real := 0.0;
-	begin
-		xm := mean(x, len);
-		
-		for i in 0 to len-1 loop
-			xp := x(i) - xm;
-			xv := xv + xp*xp;
-		end loop;
-	
-		return xv / real(len);
-	end var;
-	
-	--------------------------------------------------------------------
-	function stddev(x : real_vector_t; len : integer) return real is
-	variable xv, xs : real := 0.0;
-	begin
-		xv := var(x, len);
-		if xv > 0.0 then
-			xs := sqrt(xv);
-		end if;
-		
-		return xs;
-	end stddev;
-		
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cordic_pipe_top 
-	GENERIC MAP
-	(
-		cordic_mode 		=> cordic_mode_rotate,
-		z_range				=> pi,
-		gain_corr_mode		=> gain_mode_disabled,
-		nstages				=> 18,
-		nbits_x_in			=> nbits_x_in,
-		nbits_frac_x_in		=> nbits_frac_x_in,
-		nbits_y_in			=> nbits_y_in,
-		nbits_frac_y_in		=> nbits_frac_y_in,
-		nbits_z_in			=> nbits_z_in,
-		nbits_frac_z_in		=> nbits_frac_z_in,
-		nbits_x_out			=> nbits_x_out,
-		nbits_frac_x_out	=> nbits_frac_x_out,
-		nbits_y_out			=> nbits_y_out,
-		nbits_frac_y_out	=> nbits_frac_y_out,
-		nbits_z_out			=> nbits_z_out,
-		nbits_frac_z_out	=> nbits_frac_z_out
-	)
-	PORT MAP
-	(
-		rst => rst,
-		clk => clk,
-		vld_in => vld_in,
-		xin => xin,
-		yin => yin,
-		zin => zin,
-		xout => xout,
-		yout => yout,
-		zout => zout,
-		vld_out => vld_out
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
-	variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
-	variable argx, argy, argz : real := 0.0;
-	variable phi, dphi : real := 0.0;
-	file RESULT:        text open write_mode is "STD_OUTPUT"; 
-	file RESULT_X:      text open write_mode is "x.txt"; 
-	file RESULT_Y:      text open write_mode is "y.txt"; 
-	file RESULT_Z:      text open write_mode is "z.txt"; 
-	variable L:         line;
-	variable j : integer := 0;
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		rst <= '0';
-
-		wait for 2*PERIOD;
-
-		for i in 0 to arctan_tbl'length-1 loop
-			fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
-		end loop;	
-		for i in 0 to gain_tbl'length-1 loop
-			fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
-		end loop;	
-		fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
-		fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
-		fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-			
-		-------------------------------------------
-		-- 1
-		argx		:= 1.0;
-		argy		:= 0.0;
-		argz		:= -pi/4.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 2
-		argx		:= 1.0;
-		argy		:= 0.0;
-		argz		:= pi/2.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 3
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= pi/2.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 4
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= -pi/4.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 5
-		argx		:= 1.0;
-		argy		:= 1.0;
-		argz		:= 0.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 6
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= 0.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 7
-		argx		:= -sqrt2_inv;
-		argy		:= sqrt2_inv;
-		argz		:= 0.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 8
-		argx		:= -sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= 0.0;
-
-		wait until rising_edge(clk);
-		xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round);
-		yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round);
-		zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round);
-
-		vld_in <= '1';
-		wait until rising_edge(clk);
-		vld_in <= '0';
-
-		wait until rising_edge(clk) and vld_out = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
---		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- Place stimulus here
-		wait for 10*PERIOD;
-		wait until rising_edge(clk) and vld_out = '0';
-		j := 0;
-		dphi := 2.0*pi/real(num_steps_per_cycle);
-		for k in 0 to num_cycles-1 loop
-			phi := -pi;
-			for i in 0 to num_steps_per_cycle-1 loop
-				xin <= to_sfixed(1.0, xin);
-				yin <= to_sfixed(0.0, yin);
-				zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round);
-
-				vld_in <= '1';
-				wait until rising_edge(clk);
-				vld_in <= '0';
-
-				wait until rising_edge(clk) and vld_out = '1';
-
-				fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
-				fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
-				fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-
---				fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
---				fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
---				fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
-
-				xerr(j) := to_real(xout) - cos(phi);
-				yerr(j) := to_real(yout) - sin(phi);
-				zerr(j) := to_real(zout);
-				j := j + 1;
-				phi := (phi + dphi);
-			end loop;	
-		end loop;
-		xmean := mean(xerr, j);
-		ymean := mean(yerr, j);
-		zmean := mean(zerr, j);
-		xvar := var(xerr, j);
-		yvar := var(yerr, j);
-		zvar := var(zerr, j);
-		xstd := stddev(xerr, j);
-		ystd := stddev(yerr, j);
-		zstd := stddev(zerr, j);
-		fprint(RESULT, L,"------------------------------------------\n");
-		fprint(RESULT, L,"Results: \n");
-		fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
-		fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
-		fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
-		fprint(RESULT, L,"xvar  = %s\n", REAL'image(xvar));
-		fprint(RESULT, L,"yvar  = %s\n", REAL'image(yvar));
-		fprint(RESULT, L,"zvar  = %s\n", REAL'image(zvar));
-		fprint(RESULT, L,"xstd  = %s\n", REAL'image(xstd));
-		fprint(RESULT, L,"ystd  = %s\n", REAL'image(ystd));
-		fprint(RESULT, L,"zstd  = %s\n", REAL'image(zstd));
-		fprint(RESULT, L,"------------------------------------------\n");
-		
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-
-END;
diff --git a/lib/radio/cordic/src/tb_cordic_top.vhd b/lib/radio/cordic/src/tb_cordic_top.vhd
deleted file mode 100644
index ff75043..0000000
--- a/lib/radio/cordic/src/tb_cordic_top.vhd
+++ /dev/null
@@ -1,649 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 10/02/2005
--- Design Name:   cordic_top
--- Module Name:   tb_cordic_top.vhd
--- Project Name:  cordic
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: cordic_top
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
--- that these types always be used for the top-level I/O of a design in order 
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
--- Results:In 16i2 and Out 16i0
-------------------------------
--- xmean = -3.051757808671257e-7
--- ymean = 1.525878906192144e-6
--- zmean = 0.0
--- xvar  = 7.723598281502283e-10
--- yvar  = 8.539443970667266e-10
--- zvar  = 0.0
--- xstd  = 2.779136247380161e-5
--- ystd  = 2.922232703031582e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i1
-------------------------------
--- xmean = 6.103515628828741e-7
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar  = 9.76293486677989e-10
--- yvar  = 7.934037490259732e-10
--- zvar  = 0.0
--- xstd  = 3.124569549038697e-5
--- ystd  = 2.816742354256017e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 16i2 and Out 16i2
-------------------------------
--- xmean = 2.441406250382875e-6
--- ymean = -1.220703125057855e-6
--- zmean = 0.0
--- xvar  = 2.126680036682826e-9
--- yvar  = 2.117107754473399e-9
--- zvar  = 0.0
--- xstd  = 4.611594124251206e-5
--- ystd  = 4.601203923402438e-5
--- zstd  = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i0
-------------------------------
--- xmean = -9.312842871812748e-12 
--- ymean = -5.78558739545293e-17 
--- zmean = 0.0 
--- xvar  = 1.671709854744817e-19 
--- yvar  = 1.790442305004033e-19 
--- zvar  = 0.0 
--- xstd  = 4.088654857951228e-10 
--- ystd  = 4.231361843430591e-10 
--- zstd  = 0.0 
---
-------------------------------
--- Results:In 32i2 and Out 32i1
-------------------------------
--- xmean = 9.313608620496825e-12
--- ymean = 9.31316789028083e-12
--- zmean = 0.0
--- xvar  = 1.876480788588237e-19
--- yvar  = 2.238344116260579e-19
--- zvar  = 0.0
--- xstd  = 4.331836548841885e-10
--- ystd  = 4.731114156581492e-10
--- zstd  = 0.0
---
-------------------------------
--- Results:In 32i2 and Out 32i2
-------------------------------
--- xmean = -3.72525201102771e-11
--- ymean = -5.78558739545293e-17
--- zmean = 0.0
--- xvar  = 5.458335981037092e-19
--- yvar  = 5.704280631341228e-19
--- zvar  = 0.0
--- xstd  = 7.388055211648797e-10
--- ystd  = 7.552668820583376e-10
--- zstd  = 0.0
---
-------------------------------
--- Results:In 64i2 and Out 64i0
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar  = 5.54111959258452e-28
--- yvar  = 5.549496221074054e-28
--- zvar  = 7.916891206490056e-29
--- xstd  = 2.353958281827551e-14
--- ystd  = 2.355736874329146e-14
--- zstd  = 8.897691389619023e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i1
-------------------------------
--- xmean = 3.45418680637588e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205267218835516e-16
--- xvar  = 5.541120861185077e-28
--- yvar  = 5.549497432144743e-28
--- zvar  = 7.916856202525234e-29
--- xstd  = 2.353958551288674e-14
--- ystd  = 2.355737131376237e-14
--- zstd  = 8.897671719346156e-15
---
-------------------------------
--- Results:In 64i2 and Out 64i2
-------------------------------
--- xmean = 3.343164503913365e-17
--- ymean = 3.859475130978118e-17
--- zmean = 2.205223850748616e-16
--- xvar  = 5.540559656182732e-28
--- yvar  = 5.549495010008071e-28
--- zvar  = 7.916821581863743e-29
--- xstd  = 2.353839343749427e-14
--- ystd  = 2.355736617283025e-14
--- zstd  = 8.897652264425568e-15
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_cordic_top IS
-	Generic (
-	        nbits			: integer := 32;
-	        nbits_frac		: integer := 30;
-	        nbits_out		: integer := 32;
-	        nbits_frac_out	: integer := 31
-	        );
-END tb_cordic_top;
-
-ARCHITECTURE behavior OF tb_cordic_top IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cordic_top
-	GENERIC (
-		nbits			: integer;
-		nbits_frac		: integer;
-		nbits_out		: integer;
-		nbits_frac_out	: integer
-		);
-	PORT(
-		rst : IN std_logic;
-		clk : IN std_logic;
-		ce : in std_logic;
-		xin : IN sfixed;
-		yin : IN sfixed;
-		zin : IN sfixed;
-		xout : OUT sfixed;
-		yout : OUT sfixed;
-		zout : OUT sfixed;
-		ready : OUT std_logic;
-		valid : out std_logic;
-		cordic_mode	: in cordic_mode_t
-	);
-	END COMPONENT;
-
-	--Constants
-	constant num_cycles : integer := 5;
-	constant num_steps_per_cycle : integer := 100;
-	constant PERIOD : time := 10 ns;
-
-	constant one_sfix  : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-	constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low);
-	
-	--Inputs
-	SIGNAL clk :  std_logic := '0';
-	SIGNAL rst :  std_logic := '1';
-	SIGNAL ce  :  std_logic := '0';
-	SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low) := zero_sfix;
-
-	--Outputs
-	SIGNAL xout, yout, zout :  sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low);
-	SIGNAL valid, ready :  std_logic;
-	SIGNAL cordic_mode : cordic_mode_t := cordic_mode_vector;
-	
-
-	--------------------------------------------------------------------
-	--Functions
-	--------------------------------------------------------------------
-	type real_vector_t is array (natural range <>) of real;
-	function mean(x : real_vector_t; len : integer) return real is
-	variable xm : real := 0.0;
-	begin
-		for i in 0 to len-1 loop
-			xm := xm + x(i);
-		end loop;
-		
-		return xm / real(len);
-	end mean;	
-	
-	--------------------------------------------------------------------
-	function var(x : real_vector_t; len : integer) return real is
-	variable xv, xm, xp : real := 0.0;
-	begin
-		xm := mean(x, len);
-		
-		for i in 0 to len-1 loop
-			xp := x(i) - xm;
-			xv := xv + xp*xp;
-		end loop;
-	
-		return xv / real(len);
-	end var;
-	
-	--------------------------------------------------------------------
-	function stddev(x : real_vector_t; len : integer) return real is
-	variable xv, xs : real := 0.0;
-	begin
-		xv := var(x, len);
-		if xv > 0.0 then
-			xs := sqrt(xv);
-		end if;
-		
-		return xs;
-	end stddev;
-		
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cordic_top 
-	GENERIC MAP (
-		nbits			=> nbits,
-		nbits_frac		=> nbits_frac,
-		nbits_out		=> nbits_out,
-		nbits_frac_out	=> nbits_frac_out
-		)
-	PORT MAP(
-		rst => rst,
-		clk => clk,
-		ce => ce,
-		xin => xin,
-		yin => yin,
-		zin => zin,
-		xout => xout,
-		yout => yout,
-		zout => zout,
-		ready => ready,
-		valid => valid,
-		cordic_mode => cordic_mode
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1);
-	variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real;
-	variable argx, argy, argz : real := 0.0;
-	variable phi, dphi : real := 0.0;
-	file RESULT:        text open write_mode is "STD_OUTPUT"; 
-	file RESULT_X:      text open write_mode is "x.txt"; 
-	file RESULT_Y:      text open write_mode is "y.txt"; 
-	file RESULT_Z:      text open write_mode is "z.txt"; 
-	variable L:         line;
-	variable j : integer := 0;
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		rst <= '0';
-
-		wait for 2*PERIOD;
-
-		for i in 0 to arctan_tbl'length-1 loop
-			fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i)));
-		end loop;	
-		for i in 0 to gain_tbl'length-1 loop
-			fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i)));
-		end loop;	
-		fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI));
-		fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0)));
-		fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0)));
-			
-		-------------------------------------------
-		-- 1
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_rotate;
-		argx		:= 1.0;
-		argy		:= 0.0;
-		argz		:= -pi/4.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 2
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_rotate;
-		argx		:= 1.0;
-		argy		:= 0.0;
-		argz		:= pi/2.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 3
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_rotate;
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= pi/2.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 4
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_rotate;
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= -pi/4.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n");
-		fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 5
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_vector;
-		argx		:= 1.0;
-		argy		:= 1.0;
-		argz		:= 0.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 6
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_vector;
-		argx		:= sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= 0.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 7
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_vector;
-		argx		:= -sqrt2_inv;
-		argy		:= sqrt2_inv;
-		argz		:= 0.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- 8
-		wait until rising_edge(clk) and ready = '1';
-
-		cordic_mode	<= cordic_mode_vector;
-		argx		:= -sqrt2_inv;
-		argy		:= -sqrt2_inv;
-		argz		:= 0.0;
-
-		xin <= to_sfixed(argx, xin);
-		yin <= to_sfixed(argy, yin);
-		zin <= to_sfixed(argz, zin);
-
-		ce <= '1';
-		wait until rising_edge(clk);
-		ce <= '0';
-
-		wait until rising_edge(clk) and ready = '0';
-		wait until rising_edge(clk) and valid = '1';
-
-		fprint(RESULT, L,"--------------------------------\n");
-		fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode));
-		fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n");
-		fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n");
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin)));
-		fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin)));
-		fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin)));
-		fprint(RESULT, L,"\n");
-		fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout)));
-		fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout)));
-		fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout)));
-		fprint(RESULT, L,"\n");
-
-		-------------------------------------------
-		-- Place stimulus here
-		wait for 10*PERIOD;
-		j := 0;
-		cordic_mode	<= cordic_mode_rotate;
-		dphi := 2.0*pi/real(num_steps_per_cycle);
-		for k in 0 to num_cycles-1 loop
-			phi := -pi;
-			for i in 0 to num_steps_per_cycle-1 loop
-				xin <= one_sfix;
-				yin <= zero_sfix;
-				zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round);
-
-				wait until rising_edge(clk) and ready = '1';
-				ce <= '1';
-				wait until rising_edge(clk);
-				ce <= '0';
-
-				wait until rising_edge(clk) and ready = '0';
-				wait until rising_edge(clk) and valid = '1';
-
-				fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout)));
-				fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout)));
-				fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout)));
-
---				fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi)));
---				fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi)));
---				fprint(RESULT_Z, L,"%s\n", REAL'image(0.0));
-
-				xerr(j) := to_real(xout) - cos(phi);
-				yerr(j) := to_real(yout) - sin(phi);
-				zerr(j) := to_real(zout);
-				j := j + 1;
-				phi := (phi + dphi);
-			end loop;	
-		end loop;
-		xmean := mean(xerr, j);
-		ymean := mean(yerr, j);
-		zmean := mean(zerr, j);
-		xvar := var(xerr, j);
-		yvar := var(yerr, j);
-		zvar := var(zerr, j);
-		xstd := stddev(xerr, j);
-		ystd := stddev(yerr, j);
-		zstd := stddev(zerr, j);
-		fprint(RESULT, L,"------------------------------------------\n");
-		fprint(RESULT, L,"Results: \n");
-		fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean));
-		fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean));
-		fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean));
-		fprint(RESULT, L,"xvar  = %s\n", REAL'image(xvar));
-		fprint(RESULT, L,"yvar  = %s\n", REAL'image(yvar));
-		fprint(RESULT, L,"zvar  = %s\n", REAL'image(zvar));
-		fprint(RESULT, L,"xstd  = %s\n", REAL'image(xstd));
-		fprint(RESULT, L,"ystd  = %s\n", REAL'image(ystd));
-		fprint(RESULT, L,"zstd  = %s\n", REAL'image(zstd));
-		fprint(RESULT, L,"------------------------------------------\n");
-		
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-
-END;
diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo
deleted file mode 100644
index 0a69c83..0000000
--- a/lib/radio/ddc/sim/tb_ddc.fdo
+++ /dev/null
@@ -1,34 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../misc/dpram_1w1r.vhd"
-vcom -explicit  -93 "../../../filter/src/filter_pkg.vhd"
-vcom -explicit  -93 "../../../filter/src/fir_pkg.vhd"
-vcom -explicit  -93 "../../../filter/src/fir_stage_sys.vhd"
-vcom -explicit  -93 "../../../filter/src/delay_line.vhd"
-vcom -explicit  -93 "../../../filter/src/fir_semi_parallel.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit  -93 "../../nco/src/mix_cordic.vhd"
-vcom -explicit  -93 "../../decimator/CIC/src/cic_i_pipe.vhd"
-vcom -explicit  -93 "../../decimator/CIC/src/cic_c_pipe.vhd"
-vcom -explicit  -93 "../../decimator/CIC/src/cic_decim_pipe.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../src/ddc.vhd"
-vcom -explicit  -93 "../src/tb_ddc.vhd"
-vsim -t 1ps   -lib work tb_ddc
-do {tb_ddc.wdo}
-view wave
-view structure
-view signals
-run 1000us
-
diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo
deleted file mode 100644
index ce7f996..0000000
--- a/lib/radio/ddc/sim/tb_ddc.wdo
+++ /dev/null
@@ -1,126 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_ddc/clk
-add wave -noupdate -format Logic /tb_ddc/rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q
-add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q
-add wave -noupdate -format Logic /tb_ddc/fileout_enable
-add wave -noupdate -divider DDC
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/din_vld
-add wave -noupdate -format Logic /tb_ddc/uut/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f
-add wave -noupdate -format Logic /tb_ddc/clk
-add wave -noupdate -format Logic /tb_ddc/rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst
-add wave -noupdate -format Logic /tb_ddc/ddc_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q
-add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q
-add wave -noupdate -format Logic /tb_ddc/fileout_enable
-add wave -noupdate -divider DDC
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/din_vld
-add wave -noupdate -format Logic /tb_ddc/uut/dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f
-add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f
-add wave -noupdate -divider CFIR
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_write_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_q
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i
-add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_q
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
-add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_h_data
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_h_addr
-add wave -noupdate -format Logic /tb_ddc/uut/cfir_h_we
-add wave -noupdate -format Logic /tb_ddc/uut/hclr_mode
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_addr
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_we
-add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_din
-add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_dout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {2590000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {98190775 ps} {100095223 ps}
diff --git a/lib/radio/ddc/sim/tb_results.m b/lib/radio/ddc/sim/tb_results.m
deleted file mode 100644
index 4d25ce5..0000000
--- a/lib/radio/ddc/sim/tb_results.m
+++ /dev/null
@@ -1,57 +0,0 @@
-% Read data
-function tb_results()
-%fa = 100.0;
-fa = TEXTREAD('fa.txt')/1E6
-R = TEXTREAD('ratio.txt');
-N = TEXTREAD('nstages.txt');;
-M = 1;
-fa_dec = fa/R
-N_pfir = 63;
-
-I_out_dec = TEXTREAD('i_dec.txt')';
-Q_out_dec = TEXTREAD('q_dec.txt')';
-I_out_fir = TEXTREAD('i_fir.txt')';
-Q_out_fir = TEXTREAD('q_fir.txt')';
-
-N_dec = length(I_out_dec)-2*N_pfir;
-N_fft_dec = N_dec
-N_fft2_dec = N_fft_dec/2;
-
-N_fir = length(I_out_fir)-2*N_pfir;
-N_fft_fir = N_fir
-N_fft2_fir = N_fft_fir/2;
-
-fft_y2_fir = 2/N_fft_fir*abs(fft(I_out_fir(2*N_pfir+1:N_fft_fir+2*N_pfir).*hann(N_fft_fir)'));
-
-fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-f = (1:N_fft_dec)/N_fft_dec;
-g = (R*M)^N;
-H = abs(sin(pi*M.*f)./sin(pi.*f/R)).^N;
-
-[v, j] = max(fft_y2_dec(1:N_fft2_dec/2))
-H = v*H/H(j);
-
-wavwrite(0.5*[I_out_dec' Q_out_dec'], 16000, 16, 'iq.wav');
-wavwrite(0.5*[I_out_fir' Q_out_fir'], 8000, 16, 'iq_cfir.wav');
-
-% Output
-close all;
-
-plot(1:length(I_out_dec), I_out_dec, 1:length(Q_out_dec), Q_out_dec); grid;
-
-figure;
-cic_plot(M, N, R);
-
-figure;
-subplot(2,1,1)
-plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(H(1:N_fft2_dec+1)), 'r-');
-legend('CIC', 'Droop');
-xlabel('MHz');
-grid;
-subplot(2,1,2)
-plot(fa/(2*R*N_fft_fir)*(0:N_fft2_fir),20*log10(fft_y2_fir(1:N_fft2_fir+1)), '-');
-legend('CFIR');
-xlabel('MHz');
-grid;
-
diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd
deleted file mode 100644
index a70b50b..0000000
--- a/lib/radio/ddc/src/ddc.vhd
+++ /dev/null
@@ -1,508 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-ENTITY ddc IS
-	Generic 
-	(
-		nbits_in			: integer := 18;
-		nbits_in_frac		: integer := 16;
-		nbits_out			: integer := 18;
-		nbits_out_frac		: integer := 16;
-		lo_nbits_phase		: integer := 20;
-		lo_nbits_freq		: integer := 20;
-		cic_nstages			: integer := 3;
-		cic_ratio			: integer := 64;
-		cic_scale_nbits		: integer := 18
-	);
-	PORT
-	(
-		rst					: in std_logic;
-		clk					: in std_logic;
-		lo_nco_rst			: in std_logic;
-		lo_nco_en			: in std_logic;
-		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
-		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
-		din_i				: in  sfixed;
-		din_q				: in  sfixed;
-		din_vld				: in  std_logic;
-		dec_i				: out sfixed;
-		dec_q				: out sfixed;
-		dec_vld				: out std_logic;
-		dout_i				: out sfixed;
-		dout_q				: out sfixed;
-		dout_vld			: out std_logic
-	);
-END ddc;
-
-ARCHITECTURE behavior OF ddc IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT mix
-	GENERIC
-	(
-		nbits_din		: integer;
-		nbits_din_frac	: integer;
-		nbits_dout		: integer;
-		nbits_dout_frac	: integer;
-		nbits_phase		: integer;
-		nbits_freq		: integer
-	);
-	PORT
-	(
-		rst				: in std_logic;
-		clk				: in std_logic;
-		nco_rst			: in std_logic;
-		nco_en			: in std_logic;
-		freq_in			: in unsigned(nbits_freq-1 downto 0);
-		phase_in		: in unsigned(nbits_phase-1 downto 0);
-		din_i			: in  sfixed;
-		din_q			: in  sfixed;
-		dout_i			: out sfixed;
-		dout_q			: out sfixed;
-		din_vld			: in std_logic;
-		dout_vld		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT cic_decim_pipe
-	GENERIC
-	(
-		nstages			: integer;
-		ratio			: integer;
-		scale_nbits		: integer;
-		in_width		: integer;
-		in_width_frac	: integer;
-		out_width		: integer;
-		out_width_frac	: integer
-	);
-	PORT
-	(
-		clk				: in std_logic;
-		rst				: in std_logic;
-		vld_in			: in std_logic;
-		din				: in sfixed;
-		dout			: out sfixed;
-		vld_out 		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT fifo_sync
-	GENERIC 
-	(
-		addr_width			: natural;
-		data_width			: natural;
-		almost_full_thresh	: integer;
-		almost_empty_thresh	: integer
-	);
-	PORT
-	(
-		rst			: in  STD_LOGIC;
-		clk			: in  STD_LOGIC;
-		we			: in  STD_LOGIC;
-		re			: in  STD_LOGIC;
-		fifo_full	: out STD_LOGIC;
-		fifo_empty	: out STD_LOGIC;
-		fifo_afull	: out STD_LOGIC;
-		fifo_aempty	: out STD_LOGIC;
-		data_w		: in  unsigned (data_width-1 downto 0);
-		data_r		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT fir_semi_parallel
-	GENERIC
-	(
-		ntaps_per_stage		: integer;
-		nstages				: integer;
-		pipe_latency		: integer;
-		nbits_in			: integer;
-		nbits_in_frac		: integer;
-		nbits_stages		: integer;
-		nbits_stages_frac	: integer;
-		nbits_out			: integer;
-		nbits_out_frac		: integer
-	);
-	PORT
-	(
-		rst			: in std_logic;
-		clk			: in std_logic;
-		h_addr		: in natural range 0 to nstages*ntaps_per_stage-1;
-		h_we		: in std_logic;
-		h_in		: in sfixed;
-		din_vld		: in std_logic;
-		din			: in sfixed;
-		dout_vld	: out std_logic;
-		rdy			: out std_logic;
-		dout		: out sfixed
-	);
-	END COMPONENT;
-	
-	constant lo_nbits_in			: integer := nbits_in;
-	constant lo_nbits_in_frac		: integer := nbits_in_frac;
-	constant lo_nbits_out			: integer := nbits_in;
-	constant lo_nbits_out_frac		: integer := nbits_in_frac;
-	
-	constant cic_nbits_in			: integer := lo_nbits_out;
-	constant cic_nbits_in_frac		: integer := lo_nbits_out_frac;
-	constant cic_nbits_out			: integer := nbits_out;
-	constant cic_nbits_out_frac		: integer := nbits_out_frac;
-
-	constant cfir_pipe_latency		: integer := 5;
-	constant cfir_ntaps				: integer := 63;
-	constant cfir_nstages			: integer := 2;
-	constant cfir_nbits_in			: integer := cic_nbits_out;
-	constant cfir_nbits_in_frac		: integer := cic_nbits_out_frac;
-	constant cfir_nbits_out			: integer := nbits_out;
-	constant cfir_nbits_out_frac	: integer := nbits_out_frac;
-	constant cfir_nbits_stages		: integer := cfir_nbits_in;
-	constant cfir_nbits_stages_frac	: integer := cfir_nbits_in_frac;
-
-	constant cfir_ntaps_per_stage	: integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages;
-
-	SIGNAL mix_dout_i			: sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
-	SIGNAL mix_dout_q			: sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
-	SIGNAL mix_dout_vld			: std_logic;
-
-	SIGNAL dec_dout_i			: sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
-	SIGNAL dec_dout_q			: sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
-	SIGNAL dec_dout_vld_i		: std_logic;
-	SIGNAL dec_dout_vld_q		: std_logic;
-
-	SIGNAL cfir_h_data			: sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
-	SIGNAL cfir_h_addr			: natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
-	SIGNAL cfir_dout_i			: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL cfir_dout_q			: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL cfir_h_we			: std_logic;
-	SIGNAL cfir_vld_i			: std_logic;
-	SIGNAL cfir_vld_q			: std_logic;
-	SIGNAL cfir_ready_i			: std_logic;
-	SIGNAL cfir_ready_q			: std_logic;
-	SIGNAL cfir_start_i			: std_logic;
-	SIGNAL cfir_start_q			: std_logic;
-	SIGNAL cfir_din_vld_i		: std_logic;
-	SIGNAL cfir_din_vld_q		: std_logic;
-	SIGNAL cfir_din_i			: sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
-	SIGNAL cfir_din_q			: sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
-	SIGNAL cfir_write_i			: std_logic;
-	SIGNAL cfir_write_q			: std_logic;
-	
-	SIGNAL fifo_empty_i			: std_logic;
-	SIGNAL fifo_empty_q			: std_logic;
-	SIGNAL fifo_full_i			: std_logic;
-	SIGNAL fifo_full_q			: std_logic;
-	SIGNAL fifo_din_i			: unsigned(cfir_nbits_in-1 downto 0);
-	SIGNAL fifo_din_q			: unsigned(cfir_nbits_in-1 downto 0);
-	SIGNAL fifo_dout_i			: unsigned(cfir_nbits_in-1 downto 0);
-	SIGNAL fifo_dout_q			: unsigned(cfir_nbits_in-1 downto 0);
-
-	constant cfir_coef 			: real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.40, 1.0);
-
-	type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
-
-	function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
-	variable res : h_mem_t;
-	begin
-		for i in 0 to ntaps-1 loop
-			res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
-		end loop;
-		
-		return res;
-	end to_h_mem;	
-
-	SIGNAL hclr_mode			: std_logic;
-	CONSTANT h_mem				: h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data);
-
-BEGIN
-
---	assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note;
- 	dec_vld		<= dec_dout_vld_i and dec_dout_vld_q;
- 	dec_i		<= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
- 	dec_q		<= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-	
-	dout_vld	<= cfir_vld_i and cfir_vld_q;
-	dout_i		<= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-	dout_q		<= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-
---	cfir_start	<= dec_dout_vld_i and dec_dout_vld_q;
-	
-	-- Instantiate the Unit Under Test (UUT)
-	inst_mixer: mix 
-	GENERIC MAP
-	(
-		nbits_din			=> lo_nbits_in,
-		nbits_din_frac		=> lo_nbits_in_frac,
-		nbits_dout			=> lo_nbits_out,
-		nbits_dout_frac		=> lo_nbits_out_frac,
-		nbits_phase			=> lo_nbits_phase,
-		nbits_freq			=> lo_nbits_freq
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		nco_rst				=> lo_nco_rst,
-		nco_en				=> lo_nco_en,
-		freq_in				=> lo_freq_in,
-		phase_in			=> lo_phase_in,
-		din_i				=> din_i,
-		din_q				=> din_q,
-		dout_i				=> mix_dout_i,
-		dout_q				=> mix_dout_q,
-		din_vld				=> din_vld,
-		dout_vld			=> mix_dout_vld
-	);
-
-	inst_cic_decim_pipe_I : cic_decim_pipe
-	GENERIC MAP
-	(
-		nstages				=> cic_nstages,
-		ratio				=> cic_ratio,
-		scale_nbits			=> cic_scale_nbits,
-		in_width			=> cic_nbits_in,
-		in_width_frac		=> cic_nbits_in_frac,
-		out_width			=> cic_nbits_out,
-		out_width_frac		=> cic_nbits_out_frac
-	)
-	PORT MAP
-	(
-		clk					=> clk,
-		rst					=> rst,
-		vld_in				=> mix_dout_vld,
-		din					=> mix_dout_i,
-		dout				=> dec_dout_i,
-		vld_out				=> dec_dout_vld_i
-	);
-
-	inst_cic_decim_pipe_Q : cic_decim_pipe
-	GENERIC MAP
-	(
-		nstages				=> cic_nstages,
-		ratio				=> cic_ratio,
-		scale_nbits			=> cic_scale_nbits,
-		in_width			=> cic_nbits_in,
-		in_width_frac		=> cic_nbits_in_frac,
-		out_width			=> cic_nbits_out,
-		out_width_frac		=> cic_nbits_out_frac
-	)
-	PORT MAP
-	(
-		clk					=> clk,
-		rst					=> rst,
-		vld_in				=> mix_dout_vld,
-		din					=> mix_dout_q,
-		dout				=> dec_dout_q,
-		vld_out				=> dec_dout_vld_q
-	);
-
-	cfir_I : entity work.fir_semi_parallel
-	GENERIC MAP
-	(
-		ntaps_per_stage		=> cfir_ntaps_per_stage,
-		nstages				=> cfir_nstages,
-		pipe_latency		=> cfir_pipe_latency,
-		nbits_in			=> cfir_nbits_in,
-		nbits_in_frac		=> cfir_nbits_in_frac,
-		nbits_stages		=> cfir_nbits_stages,
-		nbits_stages_frac	=> cfir_nbits_stages_frac,
-		nbits_out			=> cfir_nbits_out,
-		nbits_out_frac		=> cfir_nbits_out_frac
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		h_addr				=> cfir_h_addr,
-		h_we				=> cfir_h_we,
-		h_in				=> cfir_h_data,
-		din_vld				=> cfir_din_vld_i,
-		din					=> cfir_din_i,
-		dout_vld			=> cfir_vld_i,
-		start				=> cfir_start_i,
-		rdy					=> cfir_ready_i,
-		dout				=> cfir_dout_i
-	);
-	
-	cfir_Q : entity work.fir_semi_parallel
-	GENERIC MAP
-	(
-		ntaps_per_stage		=> cfir_ntaps_per_stage,
-		nstages				=> cfir_nstages,
-		pipe_latency		=> cfir_pipe_latency,
-		nbits_in			=> cfir_nbits_in,
-		nbits_in_frac		=> cfir_nbits_in_frac,
-		nbits_stages		=> cfir_nbits_stages,
-		nbits_stages_frac	=> cfir_nbits_stages_frac,
-		nbits_out			=> cfir_nbits_out,
-		nbits_out_frac		=> cfir_nbits_out_frac
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		h_addr				=> cfir_h_addr,
-		h_we				=> cfir_h_we,
-		h_in				=> cfir_h_data,
-		din_vld				=> cfir_din_vld_q,
-		din					=> cfir_din_q,
-		dout_vld			=> cfir_vld_q,
-		start				=> cfir_start_q,
-		rdy					=> cfir_ready_q,
-		dout				=> cfir_dout_q
-	);
-	
-	cfir_din_vld_i	<= not fifo_empty_i and cfir_ready_i and cfir_write_i;
-	cfir_start_i	<= fifo_empty_i and cfir_write_i;
-
-	fifo_din_i	<= to_unsigned(ufixed(dec_dout_i)); 
-	cfir_din_i	<= sfixed(fifo_dout_i);
-	
--- 	cfir_din_vld_i	<= dec_dout_vld_i;
--- 	cfir_start_i	<= dec_dout_vld_i;
--- 
--- 	cfir_din_i		<= dec_dout_i; 
-	
-inst_fifo_sync_i : fifo_sync
-	GENERIC MAP 
-	(
-		addr_width			=> 1,
-		data_width			=> cfir_nbits_in,
-		almost_full_thresh	=> 1,
-		almost_empty_thresh	=> 1
-	)
-	PORT MAP
-	(
-		rst	=> rst,
-		clk	=> clk,
-		we	=> dec_dout_vld_i,
-		re	=> cfir_write_i,
-		fifo_full	=> fifo_full_i,
-		fifo_empty	=> fifo_empty_i,
-		fifo_afull	=> open,
-		fifo_aempty	=> open,
-		data_w	=> fifo_din_i,
-		data_r	=> fifo_dout_i
-	);
-
-	cfir_din_vld_q	<= not fifo_empty_q and cfir_ready_q and cfir_write_q;
-	cfir_start_q	<= fifo_empty_q and cfir_write_q;
-
-	fifo_din_q	<= to_unsigned(ufixed(dec_dout_q)); 
-	cfir_din_q	<= sfixed(fifo_dout_q);
-	
--- 	cfir_din_vld_q	<= dec_dout_vld_q;
--- 	cfir_start_q	<= dec_dout_vld_q;
--- 
--- 	cfir_din_q		<= dec_dout_q; 
-
-inst_fifo_sync_q : fifo_sync
-	GENERIC MAP 
-	(
-		addr_width			=> 1,
-		data_width			=> cfir_nbits_in,
-		almost_full_thresh	=> 1,
-		almost_empty_thresh	=> 1
-	)
-	PORT MAP
-	(
-		rst	=> rst,
-		clk	=> clk,
-		we	=> dec_dout_vld_q,
-		re	=> cfir_write_q,
-		fifo_full	=> fifo_full_q,
-		fifo_empty	=> fifo_empty_q,
-		fifo_afull	=> open,
-		fifo_aempty	=> open,
-		data_w	=> fifo_din_q,
-		data_r	=> fifo_dout_q
-	);
-
-cfir_write_logic_i:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cfir_write_i <= '0';
-			elsif fifo_full_i = '1' then
-				cfir_write_i <= '1';
-			elsif fifo_empty_i = '1' then
-				cfir_write_i <= '0';
-			end if;
-		end if;
-	end process;
-			
-cfir_write_logic_q:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				cfir_write_q <= '0';
-			elsif fifo_full_q = '1' then
-				cfir_write_q <= '1';
-			elsif fifo_empty_q = '1' then
-				cfir_write_q <= '0';
-			end if;
-		end if;
-	end process;
-			
-coef_load_counter:
-	process(clk)
-	variable count			: natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
-	variable we				: std_logic;
-	begin
-		if rising_edge(clk) then
-			cfir_h_addr <= count;	
-			cfir_h_we	<= we;
-			if rst = '1' then
-				we := '1';
-				hclr_mode <= '1';
-				count := 0;
-			else
-				if hclr_mode = '1' then
-					cfir_h_data <= to_sfixed(0.0, cfir_h_data);
-					if count /= NextPowerOfTwo(cfir_ntaps)-1 then
-						we := '1';
-						count	:= count + 1;
-					else
-						count := 0;
-						hclr_mode <= '0';
-					end if;
-				else
-					cfir_h_data <= h_mem(count);
-					if count /= cfir_ntaps-1 then
-						we := '1';
-						count	:= count + 1;
-					else
-						we := '0';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-						
-
-END;
diff --git a/lib/radio/ddc/src/syn_ddc.vhd b/lib/radio/ddc/src/syn_ddc.vhd
deleted file mode 100644
index 751ca44..0000000
--- a/lib/radio/ddc/src/syn_ddc.vhd
+++ /dev/null
@@ -1,419 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library altera;
-use altera.altera_syn_attributes.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-	ENTITY syn_ddc IS
-	Generic 
-	(
-		nbits_in			: integer := 16;
-		nbits_in_frac		: integer := 14;
-		nbits_out			: integer := 32;
-		nbits_out_frac		: integer := 30;
-		lo_nbits_phase		: integer := 24;
-		lo_nbits_freq		: integer := 24;
-		cic_nstages			: integer := 5;
-		cic_ratio			: integer := 25;
-		cic_scale_nbits		: integer := 22
-	);
-	PORT
-	(
-		rst					: in  std_logic;
-
-		adc_clk				: in  std_logic;
-		adc_da				: in  signed(15 downto 0);
-		adc_ofa				: in  std_logic;
-		adc_rand			: out std_logic;
-		adc_pga				: out std_logic;
-		adc_dith			: out std_logic;
-		adc_shdn			: out std_logic;
-
-		usb_usbclk			: in  std_logic;
-		usb_ifclk			: in  std_logic;
-		usb_fd				: out signed(15 downto 0);
-		usb_pktend			: out std_logic;
-		usb_fifoadr			: out unsigned(1 downto 0);
-		usb_slcs_n			: out std_logic;
-		usb_slwr_n			: out std_logic;
-		usb_slrd_n			: out std_logic;
-		usb_sloe			: out std_logic;
-		usb_flaga			: in  std_logic;
-		usb_flagb			: in  std_logic;
-		usb_flagc			: in  std_logic;
-		
-		cl_clk_out			: out std_logic;
-		cl_dout				: out unsigned(23 downto 0);
-		cl_pat_sel			: out std_logic;
-		cl_prbs_en			: out std_logic;
-		cl_ds_opt			: out std_logic;
-		cl_bal				: out std_logic;
-		cl_pd_n				: out std_logic;
-		cl_tsen				: in  std_logic;
-		
-		reg_aen				: in  std_logic;
-		reg_dio				: inout unsigned(7 downto 0);
-		reg_oe				: in  std_logic;
-		reg_we				: in  std_logic
-
-	);
-	END syn_ddc;
-
-ARCHITECTURE behavior OF syn_ddc IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT ddc
-	GENERIC 
-	(
-		nbits_in			: integer;
-		nbits_in_frac		: integer;
-		nbits_out			: integer;
-		nbits_out_frac		: integer;
-		lo_nbits_phase		: integer;
-		lo_nbits_freq		: integer;
-		cic_nstages			: integer;
-		cic_ratio			: integer;
-		cic_scale_nbits		: integer
-	);
-	PORT
-	(
-		rst					: in std_logic;
-		clk					: in std_logic;
-		lo_nco_rst			: in std_logic;
-		lo_nco_en			: in std_logic;
-		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
-		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
-		din_vld				: in  std_logic;
-		din_i				: in  sfixed;
-		din_q				: in  sfixed;
-		dec_vld				: out std_logic;
-		dec_i				: out sfixed;
-		dec_q				: out sfixed;
-		dout_vld			: out std_logic;
-		dout_i				: out sfixed;
-		dout_q				: out sfixed
-	);
-	END COMPONENT;
-
-	--Outputs
-	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-	SIGNAL dec_vld			: std_logic;
-	SIGNAL ddc_dec_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dec_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-
-	SIGNAL reg_lo_nco_rst	: std_logic;
-	SIGNAL reg_lo_nco_en	: std_logic;
-	SIGNAL reg_lo_freq_in	: unsigned(31 downto 0);
-	SIGNAL reg_lo_phase_in	: unsigned(31 downto 0);
-
-	SIGNAL reg_en_addr		: std_logic;
-	SIGNAL reg_en_data		: std_logic;
-	SIGNAL reg_addr_last	: std_logic;
-	SIGNAL reg_data_last	: std_logic;
-	SIGNAL reg_addr_async 	: unsigned (7 downto 0);
-	SIGNAL reg_data_async 	: unsigned (7 downto 0);
-	SIGNAL reg_addr			: unsigned (7 downto 0);
-	SIGNAL reg_data		 	: unsigned (7 downto 0);
-
-	SIGNAL fifo_usb_we		: std_logic;
-	SIGNAL fifo_usb_re		: std_logic;
-	SIGNAL fifo_usb_ff		: std_logic;
-	SIGNAL fifo_usb_ef		: std_logic;
-	SIGNAL fifo_usb_aff		: std_logic;
-	SIGNAL fifo_usb_aef		: std_logic;
-	
-	type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
-	SIGNAL fifo_usb_in	 	: fifo_usb_array_t;
-	SIGNAL fifo_usb_out	 	: unsigned (15 downto 0);
-	
-	SIGNAL fifo_usb_we_pipe	: unsigned(3 downto 0);
-	SIGNAL enable			: std_logic;
-	SIGNAL ddc_din_vld		: std_logic;
-	SIGNAL ddc_dout_vld		: std_logic;
-
-	SIGNAL cl_we_pipe		: unsigned(1 downto 0);
-	type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
-	SIGNAL cl_sd_data	 	: cl_data_array_t;
-	
-	SIGNAL cl_dout_L		: std_logic_vector(24 downto 0);
-	SIGNAL cl_dout_H		: std_logic_vector(24 downto 0);
-	SIGNAL cl_dout_clk		: std_logic_vector(24 downto 0);
-	
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	inst_ddc : ddc
-	GENERIC MAP 
-	(
-		nbits_in			=> nbits_in,
-		nbits_in_frac		=> nbits_in_frac,
-		nbits_out			=> nbits_out,
-		nbits_out_frac		=> nbits_out_frac,
-		lo_nbits_phase		=> lo_nbits_phase,
-		lo_nbits_freq		=> lo_nbits_freq,
-		cic_nstages			=> cic_nstages,
-		cic_ratio			=> cic_ratio,
-		cic_scale_nbits		=> cic_scale_nbits
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> adc_clk,
-		lo_nco_rst			=> reg_lo_nco_rst,
-		lo_nco_en			=> reg_lo_nco_en,
-		lo_freq_in			=> reg_lo_freq_in(lo_nbits_freq-1 downto 0),
-		lo_phase_in			=> reg_lo_phase_in(lo_nbits_phase-1 downto 0),
-		din_vld				=> ddc_din_vld,
-		din_i				=> ddc_din_i,
-		din_q				=> ddc_din_q,
-		dec_vld				=> dec_vld,
-		dec_i				=> ddc_dec_i,
-		dec_q				=> ddc_dec_q,
-		dout_vld			=> ddc_dout_vld,
-		dout_i				=> ddc_dout_i,
-		dout_q				=> ddc_dout_q
-	);
-
-reg_dio	<= reg_addr when reg_oe = '1' else (others => 'Z');
-
-----------------------------------------------------------
--- Register control
-----------------------------------------------------------
-proc_reg_da_async:
-	process(reg_we)
-	begin
-		if rising_edge(reg_we) then
-			if reg_aen = '1' then
-				reg_addr_async <= reg_dio;
-			else	
-				reg_data_async <= reg_dio;
-			end if;
-		end if;
-	end process;
-	
-proc_reg_da_sync:
-	process(adc_clk)
---	process(usb_usbclk)
-	begin
-		if rising_edge(adc_clk) then
---		if rising_edge(usb_usbclk) then
-			if rst = '1' then
-				reg_en_addr		<= '0';
-				reg_en_data		<= '0';
-				reg_addr_last	<= '0';
-				reg_data_last	<= '0';
-			elsif reg_we = '1' then
-				reg_en_addr		<= reg_aen and not reg_addr_last;
-				reg_en_data		<= not (reg_aen or reg_data_last);
-				reg_addr_last	<= reg_aen;
-				reg_data_last	<= not reg_aen;
-			else
-				reg_addr_last	<= '0';
-				reg_data_last	<= '0';
-			end if;	
-			reg_data		<= reg_data_async;
-			reg_addr		<= reg_addr_async;
-		end if;
-	end process;
-
-	-- Registers
-proc_register_write:
-	process(adc_clk)
---	process(usb_usbclk)
-	begin
-		if rising_edge(adc_clk) then
---		if rising_edge(usb_usbclk) then
-			if rst = '1' then
-				reg_lo_nco_rst	<= '0';
-				reg_lo_nco_en	<= '0';
-			elsif reg_en_data = '1' then
-				case reg_addr is
-				when X"00" =>		-- Control
-					reg_lo_nco_rst	<= reg_data(0);
-					reg_lo_nco_en	<= reg_data(1);
-					
-				when X"10"	=>		-- freqency
-					reg_lo_freq_in(7 downto 0)		<= reg_data;
-					
-				when X"11"	=>		-- freqency
-					reg_lo_freq_in(15 downto 8)		<= reg_data;
-			
-				when X"12"	=>		-- freqency
-					reg_lo_freq_in(23 downto 16)	<= reg_data;
-
-				when X"13"	=>		-- freqency
-					reg_lo_freq_in(31 downto 24)	<= reg_data;
-
-				when X"20"	=>		-- phase
-					reg_lo_phase_in(7 downto 0)		<= reg_data;
-					
-				when X"21"	=>		-- phase
-					reg_lo_phase_in(15 downto 8)	<= reg_data;
-			
-				when X"22"	=>		-- phase
-					reg_lo_phase_in(23 downto 16)	<= reg_data;
-
-				when X"23"	=>		-- phase
-					reg_lo_phase_in(31 downto 24)	<= reg_data;
-					
-				when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-----------------------------------------------------------
--- DDC input
-----------------------------------------------------------
-proc_adc_input_register:
-	process(adc_clk)
-	begin
-		if rising_edge(adc_clk) then
-			ddc_din_vld	<= enable;
-			if enable = '1' then
-				ddc_din_i	<= sfixed(resize(adc_da, nbits_in));
-			end if;	
-		end if;	
-	end process;
-
-	ddc_din_q	<= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
-	
-	enable		<= '1';
-	adc_rand	<= '0';
-	adc_pga		<= '0';
-	adc_dith	<= '0';
-	adc_shdn	<= not enable;
-
-----------------------------------------------------------
--- USB FIFO output
-----------------------------------------------------------
-proc_usb_interleave_iq:
-	process(adc_clk)
-	variable i, q : unsigned(31 downto 0);
-	begin
-		if rising_edge(adc_clk) then
-			if rst = '1' then
-				fifo_usb_we_pipe			<= (others => '0');
-			elsif ddc_dout_vld = '1' then
-				fifo_usb_we_pipe			<= (others => '1');
-				i					:= unsigned(ddc_dout_i);
-				q					:= unsigned(ddc_dout_q);
-				fifo_usb_in(0)		<= i(15 downto 0);
-				fifo_usb_in(1)		<= i(31 downto 16);
-				fifo_usb_in(2)		<= q(15 downto 0);
-				fifo_usb_in(3)		<= q(31 downto 16);
-			elsif fifo_usb_ff = '0' then
-				fifo_usb_we_pipe	<= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
-				fifo_usb_in(0)		<= fifo_usb_in(1);
-				fifo_usb_in(1)		<= fifo_usb_in(2);
-				fifo_usb_in(2)		<= fifo_usb_in(3);
-			end if;	
-		end if;	
-	end process;
-
-inst_usbfifo: entity work.fifo_async
-	GENERIC MAP 
-	(
-		addr_width			=> 7,
-		data_width			=> 16,
-		almost_full_thresh	=> 96,
-		almost_empty_thresh	=> 32
-	)
-	PORT MAP
-	(
-		rst				=> rst,
-		clk_w			=> adc_clk,
-		clk_r			=> usb_ifclk,
-		we				=> fifo_usb_we,
-		re				=> fifo_usb_re,
-		data_w			=> fifo_usb_in(0),
-		data_r			=> fifo_usb_out,
-		fifo_full		=> fifo_usb_ff,
-		fifo_empty		=> fifo_usb_ef,
-		fifo_afull		=> fifo_usb_aff,
-		fifo_aempty		=> fifo_usb_aef
-		
-	);
-
-	fifo_usb_we	<= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
-	usb_fd		<= signed(fifo_usb_out);
-	fifo_usb_re	<= usb_flaga;
-	usb_slcs_n	<= '0';
-	usb_slwr_n	<= not usb_flaga;
-	usb_slrd_n	<= '1';
-	usb_sloe	<= '0';
-
-
-----------------------------------------------------------
--- Channel-Link DDR output
-----------------------------------------------------------
-proc_cl_interleave_iq:
-	process(adc_clk)
-	variable i, q : unsigned(31 downto 0);
-	begin
-		if rising_edge(adc_clk) then
-			if rst = '1' then
-				cl_we_pipe		<= (others => '0');
-			elsif ddc_dout_vld = '1' then
-				cl_we_pipe		<= (others => '1');
-				i				:= unsigned(ddc_dout_i);
-				q				:= unsigned(ddc_dout_q);
-				cl_sd_data(0)	<= i;
-				cl_sd_data(1)	<= q;
-			else
-				cl_we_pipe		<= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
-				cl_sd_data(0)	<= cl_sd_data(1);
-			end if;	
-		end if;	
-	end process;
-	
-inst_cl_ddr_out: entity work.cl_ddr_out
-	PORT MAP
-	(
-		aclr		=> rst,
-		datain_h	=> cl_dout_H,
-		datain_l	=> cl_dout_L,
-		outclock	=> adc_clk,
-		outclocken	=> '1',
-		dataout		=> cl_dout_clk
-	);
-	
-	cl_dout_H		<= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
-	cl_dout_L		<= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
-	cl_dout			<= unsigned(cl_dout_clk(23 downto 0));	
-	cl_clk_out		<= cl_dout_clk(24);
-	cl_pat_sel		<= '0';
-	cl_prbs_en		<= '0';
-	cl_ds_opt		<= '0';
-	cl_bal			<= '0';
-	cl_pd_n			<= '1';
-
-----------------------------------------------------------
-END;
diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd
deleted file mode 100644
index fa3a61e..0000000
--- a/lib/radio/ddc/src/tb_ddc.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_ddc IS
-	Generic 
-	(
-		nbits_in			: integer := 16;
-		nbits_in_frac		: integer := 14;
-		nbits_out			: integer := 32;
-		nbits_out_frac		: integer := 30;
-		lo_nbits_phase		: integer := 24;
-		lo_nbits_freq		: integer := 24;
-		cic_nstages			: integer := 5;
-		cic_ratio			: integer := 25;
-		cic_scale_nbits		: integer := 22;
-		rfgen_nbits_phase	: integer := 32;
-		rfgen_nbits_freq	: integer := 32
-	);
-END tb_ddc;
-
-ARCHITECTURE behavior OF tb_ddc IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT ddc
-	GENERIC 
-	(
-		nbits_in			: integer;
-		nbits_in_frac		: integer;
-		nbits_out			: integer;
-		nbits_out_frac		: integer;
-		lo_nbits_phase		: integer;
-		lo_nbits_freq		: integer;
-		cic_nstages			: integer;
-		cic_ratio			: integer;
-		cic_scale_nbits		: integer
-	);
-	PORT
-	(
-		rst					: in std_logic;
-		clk					: in std_logic;
-		lo_nco_rst			: in std_logic;
-		lo_nco_en			: in std_logic;
-		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
-		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
-		din_i				: in  sfixed;
-		din_q				: in  sfixed;
-		din_vld				: in  std_logic;
-		dec_i				: out sfixed;
-		dec_q				: out sfixed;
-		dec_vld				: out std_logic;
-		dout_i				: out sfixed;
-		dout_q				: out sfixed;
-		dout_vld			: out std_logic
-	);
-	END COMPONENT;
-
-	-- Rf-Generator
-	COMPONENT mix
-	GENERIC
-	(
-		nbits_din		: integer;
-		nbits_din_frac	: integer;
-		nbits_dout		: integer;
-		nbits_dout_frac	: integer;
-		nbits_phase		: integer;
-		nbits_freq		: integer
-	);
-	PORT
-	(
-		rst				: in std_logic;
-		clk				: in std_logic;
-		nco_rst			: in std_logic;
-		nco_en			: in std_logic;
-		freq_in			: in unsigned(nbits_freq-1 downto 0);
-		phase_in		: in unsigned(nbits_phase-1 downto 0);
-		din_i			: in  sfixed;
-		din_q			: in  sfixed;
-		dout_i			: out sfixed;
-		dout_q			: out sfixed;
-		din_vld			: in std_logic;
-		dout_vld		: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant fa : REAL := 2.0**27;
-	constant frf1 : REAL := 33.99E6;
-	constant frf2 : REAL := 2.1E6;
-	constant frf3 : REAL := 19.01E6;
-	constant flo : REAL := 2.00E6;
-	constant PERIOD : time := 10 ns;
-
-	SIGNAL rfgen1_freq_word	: integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
-	SIGNAL rfgen2_freq_word	: integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
-	SIGNAL rfgen3_freq_word	: integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
-	SIGNAL lo_freq_word		: integer := integer(flo/fa*2.0**lo_nbits_freq);
-
-	--Inputs
-	SIGNAL clk				: std_logic := '0';
-	SIGNAL rst				: std_logic := '1';
-	SIGNAL ddc_nco_rst		: std_logic := '0';
-	SIGNAL ddc_nco_en		: std_logic := '0';
-	SIGNAL ddc_freq_in		: unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL ddc_phase_in		: unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
-
-	--Outputs
-	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL ddc_din_vld		: std_logic := '0';
-
-	SIGNAL ddc_dec_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dec_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dec_vld		: std_logic;
-
-	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-	SIGNAL ddc_dout_vld		: std_logic;
-		
-	SIGNAL rfgen_nco_rst	: std_logic := '0';
-	SIGNAL rfgen_nco_en		: std_logic := '0';
-	SIGNAL rfgen1_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL rfgen1_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
-	SIGNAL rfgen2_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL rfgen2_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
-	SIGNAL rfgen3_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL rfgen3_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
-
-	--Outputs
-	signal rfgen_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
-	signal rfgen_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen_dout_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen_dout_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen1_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen1_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen1_dout_vld	: std_logic;
-	SIGNAL rfgen2_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen2_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen2_dout_vld	: std_logic;
-	SIGNAL rfgen3_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen3_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-	SIGNAL rfgen3_dout_vld	: std_logic;
-
-	SIGNAL fileout_enable   : std_logic := '0';
-
-	-- Debug
-	signal ddc_i_out_f		: real;
-	signal ddc_q_out_f		: real;
-	signal rfgen_i_out_f	: real;
-	signal rfgen_q_out_f	: real;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut : ddc
-	GENERIC MAP 
-	(
-		nbits_in			=> nbits_in,
-		nbits_in_frac		=> nbits_in_frac,
-		nbits_out			=> nbits_out,
-		nbits_out_frac		=> nbits_out_frac,
-		lo_nbits_phase		=> lo_nbits_phase,
-		lo_nbits_freq		=> lo_nbits_freq,
-		cic_nstages			=> cic_nstages,
-		cic_ratio			=> cic_ratio,
-		cic_scale_nbits		=> cic_scale_nbits
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		lo_nco_rst			=> ddc_nco_rst,
-		lo_nco_en			=> ddc_nco_en,
-		lo_freq_in			=> ddc_freq_in,
-		lo_phase_in			=> ddc_phase_in,
-		din_i				=> ddc_din_i,
-		din_q				=> ddc_din_q,
-		din_vld				=> ddc_din_vld,
-		dec_i				=> ddc_dec_i,
-		dec_q				=> ddc_dec_q,
-		dec_vld				=> ddc_dec_vld,
-		dout_i				=> ddc_dout_i,
-		dout_q				=> ddc_dout_q,
-		dout_vld			=> ddc_dout_vld
-	);
-	
-	rfgen1: mix 
-	GENERIC MAP
-	(
-		nbits_din			=> nbits_in,
-		nbits_din_frac		=> nbits_in_frac,
-		nbits_dout			=> nbits_in,
-		nbits_dout_frac		=> nbits_in_frac,
-		nbits_phase			=> rfgen_nbits_phase,
-		nbits_freq			=> rfgen_nbits_freq
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		nco_rst				=> rfgen_nco_rst,
-		nco_en				=> rfgen_nco_en,
-		freq_in				=> rfgen1_freq_in,
-		phase_in			=> rfgen1_phase_in,
-		din_i				=> rfgen_din_i,
-		din_q				=> rfgen_din_q,
-		dout_i				=> rfgen1_dout_i,
-		dout_q				=> rfgen1_dout_q,
-		din_vld				=> '1',
-		dout_vld			=> rfgen1_dout_vld
-	);
-
-	rfgen2: mix 
-	GENERIC MAP
-	(
-		nbits_din			=> nbits_in,
-		nbits_din_frac		=> nbits_in_frac,
-		nbits_dout			=> nbits_in,
-		nbits_dout_frac		=> nbits_in_frac,
-		nbits_phase			=> rfgen_nbits_phase,
-		nbits_freq			=> rfgen_nbits_freq
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		nco_rst				=> rfgen_nco_rst,
-		nco_en				=> rfgen_nco_en,
-		freq_in				=> rfgen2_freq_in,
-		phase_in			=> rfgen2_phase_in,
-		din_i				=> rfgen_din_i,
-		din_q				=> rfgen_din_q,
-		dout_i				=> rfgen2_dout_i,
-		dout_q				=> rfgen2_dout_q,
-		din_vld				=> '1',
-		dout_vld			=> rfgen2_dout_vld
-	);
-
-	rfgen3: mix 
-	GENERIC MAP
-	(
-		nbits_din			=> nbits_in,
-		nbits_din_frac		=> nbits_in_frac,
-		nbits_dout			=> nbits_in,
-		nbits_dout_frac		=> nbits_in_frac,
-		nbits_phase			=> rfgen_nbits_phase,
-		nbits_freq			=> rfgen_nbits_freq
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		nco_rst				=> rfgen_nco_rst,
-		nco_en				=> rfgen_nco_en,
-		freq_in				=> rfgen3_freq_in,
-		phase_in			=> rfgen3_phase_in,
-		din_i				=> rfgen_din_i,
-		din_q				=> rfgen_din_q,
-		dout_i				=> rfgen3_dout_i,
-		dout_q				=> rfgen3_dout_q,
-		din_vld				=> '1',
-		dout_vld			=> rfgen3_dout_vld
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	rfgen_dout_i	<= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
-	rfgen_dout_q	<= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
-
-	ddc_din_i	<= rfgen_dout_i;
-	ddc_din_q	<= to_sfixed(0.0, ddc_din_q);
-	ddc_din_vld	<= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
-	
-	ddc_i_out_f	<= to_real(ddc_dout_i);
-	ddc_q_out_f	<= to_real(ddc_dout_q);
-	
-	rfgen_i_out_f	<= to_real(rfgen_dout_i);
-	rfgen_q_out_f	<= to_real(rfgen_dout_q);
-	
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		rst <= '0';
-
-		wait for 2*PERIOD;
-		-------------------------------------------
-		-- Program gains
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-
-		-- start DDC
-		ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
-		ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
-		wait until rising_edge(clk);
-		ddc_nco_en	<= '1';
-		
-		wait for 20*PERIOD;
-		fileout_enable <= '1';
-
-		wait; 
-	END PROCESS;
-	
-	
-	rfgen_ctrl : PROCESS
-
-	BEGIN
-			wait until rising_edge(clk) and rst = '0';
-			rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
-			rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
-			rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
-			rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
-			rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
-			rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
-			wait until rising_edge(clk);
-			rfgen_nco_en <= '1';
-	
-
-		wait; 
-	END PROCESS;
-
-	tb_param : PROCESS
-	file RESULT_R:        text open write_mode is "ratio.txt"; 
-	file RESULT_N:        text open write_mode is "nstages.txt"; 
-	file FSAMPLE:        text open write_mode is "fa.txt"; 
-	variable L:         line;
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait until rising_edge(clk) and rst = '0';
-		fprint(RESULT_R, L,"%s\n", natural'image(cic_ratio));
-		fprint(RESULT_N, L,"%s\n", natural'image(cic_nstages));
-		fprint(FSAMPLE, L,"%s\n", real'image(fa));
-		wait; 
-
-	END PROCESS;
-
-	tb_fo : PROCESS(clk)
-	file RESULT_Ii:	      text open write_mode is "i_in.txt"; 
-	file RESULT_Qi:	      text open write_mode is "q_in.txt"; 
-	file RESULT_Ifir:      text open write_mode is "i_fir.txt"; 
-	file RESULT_Qfir:      text open write_mode is "q_fir.txt"; 
-	file RESULT_Idec:      text open write_mode is "i_dec.txt"; 
-	file RESULT_Qdec:      text open write_mode is "q_dec.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) then
-			if fileout_enable = '1' then
-				if ddc_din_vld = '1' then
-					fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
-					fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
-				end if;
-				if ddc_dout_vld = '1' then
-					fprint(RESULT_Ifir, L,"%s\n", REAL'image(to_real(ddc_dout_i)));
-					fprint(RESULT_Qfir, L,"%s\n", REAL'image(to_real(ddc_dout_q)));
-				end if;
-				if ddc_dec_vld = '1' then
-					fprint(RESULT_Idec, L,"%s\n", REAL'image(to_real(ddc_dec_i)));
-					fprint(RESULT_Qdec, L,"%s\n", REAL'image(to_real(ddc_dec_q)));
-				end if;
-			end if;
-		end if;
-	END PROCESS;
-
-END;
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
deleted file mode 100644
index 40910c8..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/cic_c_pipe.vhd"
-vcom -explicit  -93 "../src/tb_cic_c_pipe.vhd"
-vsim -t 1ps   -lib work tb_cic_c_pipe
-do {tb_cic_c_pipe.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
deleted file mode 100644
index 901e089..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
+++ /dev/null
@@ -1,26 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_c_pipe/clk
-add wave -noupdate -format Logic /tb_cic_c_pipe/srst
-add wave -noupdate -format Logic /tb_cic_c_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/din
-add wave -noupdate -format Literal /tb_cic_c_pipe/diff_delay
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/dout
-add wave -noupdate -format Logic /tb_cic_c_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/uut/word_pipe
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {500608 ps}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
deleted file mode 100644
index b0525de..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/cic_i_pipe.vhd"
-vcom -explicit  -93 "../src/cic_c_pipe.vhd"
-vcom -explicit  -93 "../src/cic_decim_pipe.vhd"
-vcom -explicit  -93 "../src/tb_cic_decim_pipe.vhd"
-vsim -t 1ps   -lib work tb_cic_decim_pipe
-do {tb_cic_decim_pipe.wdo}
-view wave
-view structure
-view signals
-run 140us
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
deleted file mode 100644
index 0296151..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
+++ /dev/null
@@ -1,39 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
-add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
-add wave -noupdate -divider Debug
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/xr
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/yr
-add wave -noupdate -divider -height 50 Trenn
-add wave -noupdate -format Literal -radix decimal -expand /tb_cic_decim_pipe/uut/word_i_pipe
-add wave -noupdate -format Literal /tb_cic_decim_pipe/uut/vld_i_pipe
-add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
-add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
-add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/uut/word_c_pipe
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {34745455 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {147 us}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
deleted file mode 100644
index b1c190a..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
+++ /dev/null
@@ -1,14 +0,0 @@
-vmap ieee_proposed ../../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/cic_i_pipe.vhd"
-vcom -explicit  -93 "../src/tb_cic_i_pipe.vhd"
-vsim -t 1ps   -lib work tb_cic_i_pipe
-do {tb_cic_i_pipe.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
deleted file mode 100644
index 140032c..0000000
--- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
+++ /dev/null
@@ -1,30 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_cic_i_pipe/srst
-add wave -noupdate -format Logic /tb_cic_i_pipe/clk
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
-add wave -noupdate -format Logic /tb_cic_i_pipe/srst
-add wave -noupdate -format Logic /tb_cic_i_pipe/clk
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
-add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
-add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {373333 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
deleted file mode 100644
index 41063f0..0000000
--- a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
+++ /dev/null
@@ -1,104 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cic_c_pipe is
-Generic
-(
-	max_diff_delay	: integer := 1;
-	max_width		: integer := 32;
-	max_width_frac	: integer := 20
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	diff_delay	: in natural range 1 to max_diff_delay;
-	din			: in sfixed;
-	dout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cic_c_pipe;
-
-architecture Behavioral of cic_c_pipe is
-
-subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-type word_pipe_t is array (1 to max_diff_delay) of word_t;
-
-signal word_pipe	: word_pipe_t;
-
-------------------------------------------------------------
-begin
-
-------------------------------------------------------------
-delay_pipe_proc: 
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
---				for i in 1 to max_diff_delay loop
---					word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
---				end loop;
-			elsif vld_in = '1' then
-				word_pipe(1)	<= resize(din, word_pipe(1));
-				for i in 2 to max_diff_delay loop
-					word_pipe(i)	<= word_pipe(i-1);
-				end loop;
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-comb_proc: 
-	process(clk)
-	variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-	begin
-		if rising_edge(clk) then
-			vld_out <= '0';
-			x0	:= resize(din, x0);
-			x1	:= word_pipe(diff_delay);
-			if rst = '1' then
-				dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
-			elsif vld_in = '1' then
-				vld_out <= '1';
-				dout	<= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
deleted file mode 100644
index 139c81a..0000000
--- a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+++ /dev/null
@@ -1,203 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.utils_pkg.all;
-
-ENTITY cic_decim_pipe IS
-	Generic
-	(
-		nstages			: integer := 3;
-		diff_delay		: integer := 1;
-		ratio			: integer := 64;
-		scale_nbits		: integer := 9;
-		in_width		: integer := 32;
-		in_width_frac	: integer := 20;
-		out_width		: integer := 32;
-		out_width_frac	: integer := 20
-	);
-	Port
-	(
-		clk				: in std_logic;
-		rst				: in std_logic;
-		vld_in			: in std_logic;
-		din				: in sfixed;
-		dout			: out sfixed;
-		vld_out 		: out std_logic
-	);
-END cic_decim_pipe;
-
-ARCHITECTURE behavior OF cic_decim_pipe IS 
-
-	COMPONENT cic_i_pipe
-	GENERIC
-	(
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT cic_c_pipe
-	GENERIC
-	(
-		max_diff_delay	: integer;
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		diff_delay	: in natural range 1 to max_diff_delay;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	constant max_gain_bits		: natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
-
-	constant integ_nbits		: natural := in_width + max_gain_bits;
-	constant integ_nbits_frac	: natural := integ_nbits - (in_width - in_width_frac);
-	
-	constant comb_nbits			: natural := out_width+1;
-	constant comb_nbits_frac	: natural := out_width_frac+1;
-
-	subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-	type word_i_pipe_t is array (0 to nstages) of word_i_t;
-
-	signal word_i_pipe	: word_i_pipe_t;
-	signal vld_i_pipe	: unsigned (0 to nstages);
-	signal vld_i		: std_logic;
-	
-	subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac));
-	type word_c_pipe_t is array (0 to nstages) of word_c_t;
-
-	signal word_c_pipe	: word_c_pipe_t;
-	signal vld_c_pipe	: unsigned (0 to nstages);
-	signal vld_c		: std_logic;
-
-	signal resample_cnt	: natural range 1 to ratio;
-	signal resample_vld	: std_logic;
-
-BEGIN
-
-	assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
-	assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
-	assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
-
-	vld_i			<= vld_i_pipe(nstages);
-
-input_scale:
-	process(clk)
-	variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-	variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-	variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
-	begin
-		if rising_edge(clk) then
-			x				:= resize(din, x);
-			xs				:= x sra scale_nbits;
-			word_i_pipe(0)	<= xs;
-			vld_i_pipe(0)	<= vld_in;
-		end if;
-	end process;		
-
-	gen_i_stages:
-	for i in 1 to nstages generate
-	begin
-		inst_cic_i_pipe: cic_i_pipe 
-		GENERIC MAP
-		(
-			max_width		=> integ_nbits,
-			max_width_frac	=> integ_nbits_frac
-		)
-		PORT MAP
-		(
-			clk				=> clk,
-			rst				=> rst,
-			vld_in			=> vld_i_pipe(i-1),
-			din				=> word_i_pipe(i-1),
-			dout			=> word_i_pipe(i),
-			vld_out			=> vld_i_pipe(i)
-		);
-	end generate;
-	
-	word_c_pipe(0)	<= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
-	vld_c_pipe(0)	<= resample_vld;
-	vld_c			<= vld_c_pipe(nstages);
-
-	vld_out			<= vld_c;
-	
-	gen_c_stages:
-	for i in 1 to nstages generate
-	begin
-		inst_cic_c_pipe: cic_c_pipe 
-		GENERIC MAP
-		(
-			max_diff_delay	=> diff_delay,
-			max_width		=> comb_nbits,
-			max_width_frac	=> comb_nbits_frac
-		)
-		PORT MAP
-		(
-			clk				=> clk,
-			rst				=> rst,
-			vld_in			=> vld_c_pipe(i-1),
-			diff_delay		=> diff_delay,
-			din				=> word_c_pipe(i-1),
-			dout			=> word_c_pipe(i),
-			vld_out			=> vld_c_pipe(i)
-		);
-	end generate;
-	
-resampler_proc:
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			resample_vld	<= '0';
-			if rst = '1' then
-				resample_cnt	<= 1;
-			elsif vld_i = '1' then
-				if resample_cnt = ratio then
-					resample_vld	<= '1';
-					resample_cnt	<= 1;
-				else
-					resample_cnt	<= resample_cnt + 1;
-				end if ;
-			end if;
-		end if;
-	end process;		
-
-	dout		<= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac));
-
-END;
diff --git a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
deleted file mode 100644
index 0880ca3..0000000
--- a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage_pre - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity cic_i_pipe is
-Generic
-(
-	max_width		: integer := 32;
-	max_width_frac	: integer := 20
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	din			: in sfixed;
-	dout		: out sfixed;
-	vld_out 	: out std_logic
-);
-end cic_i_pipe;
-
-architecture Behavioral of cic_i_pipe is
-
-signal accu			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-
-------------------------------------------------------------
-begin
-
-	dout	<= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-	
-------------------------------------------------------------
-integ_proc: 
-	process(clk)
-	variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	begin
-		if rising_edge(clk) then
-			vld_out <= '0';
-			if rst = '1' then
-				accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
-			elsif vld_in = '1' then
-				vld_out <= '1';
-				x		:= resize(din, x);
-				accu	<= resize(x + accu, accu);
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
-
diff --git a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
deleted file mode 100644
index 70e3007..0000000
--- a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
+++ /dev/null
@@ -1,98 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-entity syn_cic_c_pipe is
-Generic
-(
-	max_diff_delay	: integer := 2;
-	max_width		: integer := 32;
-	max_width_frac	: integer := 20
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	diff_delay	: in natural range 1 to max_diff_delay;
-	din			: in signed(max_width-1 downto 0);
-	dout		: out signed(max_width-1 downto 0);
-	vld_out 	: out std_logic
-);
-end syn_cic_c_pipe;
-
-ARCHITECTURE behavior OF syn_cic_c_pipe IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cic_c_pipe
-	GENERIC
-	(
-		max_diff_delay	: integer;
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		diff_delay	: in natural range 1 to max_diff_delay;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	--Inputs
-	SIGNAL sdin			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-	--Outputs
-	SIGNAL sdout		: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cic_c_pipe 
-	GENERIC MAP
-	(
-		max_diff_delay	=> max_diff_delay,
-		max_width		=> max_width,
-		max_width_frac	=> max_width_frac
-	)
-	PORT MAP
-	(
-		clk				=> clk,
-		rst				=> rst,
-		vld_in			=> vld_in,
-		diff_delay		=> diff_delay,
-		din				=> sdin,
-		dout			=> sdout,
-		vld_out			=> vld_out
-	);
-
-	sdin	<= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-	dout	<= signed(sdout);
-
-END;
diff --git a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
deleted file mode 100644
index 52428ed..0000000
--- a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
+++ /dev/null
@@ -1,92 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
-entity syn_cic_i_pipe is
-Generic
-(
-	max_width		: integer := 32;
-	max_width_frac	: integer := 20
-);
-Port
-(
-	clk			: in std_logic;
-	rst			: in std_logic;
-	vld_in		: in std_logic;
-	din			: in signed(max_width-1 downto 0);
-	dout		: out signed(max_width-1 downto 0);
-	vld_out 	: out std_logic
-);
-end syn_cic_i_pipe;
-
-ARCHITECTURE behavior OF syn_cic_i_pipe IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cic_i_pipe
-	GENERIC
-	(
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	--Inputs
-	SIGNAL sdin			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-	--Outputs
-	SIGNAL sdout		: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cic_i_pipe 
-	GENERIC MAP
-	(
-		max_width		=> max_width,
-		max_width_frac	=> max_width_frac
-	)
-	PORT MAP
-	(
-		clk				=> clk,
-		rst				=> rst,
-		vld_in			=> vld_in,
-		din				=> sdin,
-		dout			=> sdout,
-		vld_out			=> vld_out
-	);
-
-	sdin	<= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
-	dout	<= signed(sdout);
-
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
deleted file mode 100644
index d36268d..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
+++ /dev/null
@@ -1,136 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_c_pipe IS
-	Generic
-	(
-		max_width		: integer := 32;
-		max_width_frac	: integer := 20
-	);
-END tb_cic_c_pipe;
-
-ARCHITECTURE behavior OF tb_cic_c_pipe IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cic_c_pipe
-	GENERIC
-	(
-		max_diff_delay	: integer;
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		diff_delay	: in natural range 1 to max_diff_delay;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk			: std_logic := '0';
-	SIGNAL srst			: std_logic := '1';
-	SIGNAL vld_in		: std_logic := '0';
-	SIGNAL din			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	SIGNAL diff_delay	: natural := 1;
-	
-	--Outputs
-	SIGNAL dout			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	SIGNAL vld_out		: std_logic;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cic_c_pipe 
-	GENERIC MAP
-	(
-		max_diff_delay	=> 2,
-		max_width		=> max_width,
-		max_width_frac	=> max_width_frac
-	)
-	PORT MAP
-	(
-		clk				=> clk,
-		rst				=> srst,
-		vld_in			=> vld_in,
-		diff_delay		=> diff_delay,
-		din				=> din,
-		dout			=> dout,
-		vld_out			=> vld_out
-	);
-
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		din		<= to_sfixed(0.0, din);
-		vld_in	<= '1';
-
-		wait for 9*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(0.5, din);
-
-		wait for 9*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(0.0, din);
-
-		wait for 9*PERIOD;
-		wait until rising_edge(clk);
-		vld_in	<= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
deleted file mode 100644
index f6f1d91..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+++ /dev/null
@@ -1,153 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_decim_pipe IS
-	Generic
-	(
-		nstages			: integer := 3;
-		ratio			: integer := 64;
-		scale_nbits		: integer := 18;
-		in_width		: integer := 18;
-		in_width_frac	: integer := 16;
-		out_width		: integer := 18;
-		out_width_frac	: integer := 16
-	);
-END tb_cic_decim_pipe;
-
-ARCHITECTURE behavior OF tb_cic_decim_pipe IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cic_decim_pipe
-	GENERIC
-	(
-		nstages			: integer;
-		ratio			: integer;
-		scale_nbits		: integer;
-		in_width		: integer;
-		in_width_frac	: integer;
-		out_width		: integer;
-		out_width_frac	: integer
-	);
-	PORT
-	(
-		clk				: in std_logic;
-		rst				: in std_logic;
-		vld_in			: in std_logic;
-		din				: in sfixed;
-		dout			: out sfixed;
-		vld_out 		: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk				: std_logic := '0';
-	SIGNAL srst				: std_logic := '1';
-	SIGNAL vld_in			: std_logic := '0';
-	SIGNAL din				: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
-	
-	--Outputs
-	SIGNAL dout				: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
-	SIGNAL vld_out			: std_logic;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-
-	signal XR, YR		: real;
-	
-BEGIN
-
-	XR	<= to_real(din);
-	YR	<= to_real(dout);
-	
-	-- Instantiate the Unit Under Test (UUT)
-	uut : cic_decim_pipe
-	GENERIC MAP
-	(
-		nstages			=> nstages,
-		ratio			=> ratio,
-		scale_nbits		=> scale_nbits,
-		in_width		=> in_width,
-		in_width_frac	=> in_width_frac,
-		out_width		=> out_width,
-		out_width_frac	=> out_width_frac
-	)
-	PORT MAP
-	(
-		clk				=> clk,
-		rst				=> srst,
-		vld_in			=> vld_in,
-		din				=> din,
-		dout			=> dout,
-		vld_out			=> vld_out
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		din		<= to_sfixed(0.0, din);
-		vld_in	<= '1';
-
-		wait for 49*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(0.5, din);
-
-		wait for 4999*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(-0.5, din);
-
-		wait for 99*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(0.0, din);
-
-		wait for 499*PERIOD;
-		wait until rising_edge(clk);
-		vld_in	<= '0';
-
-		wait; 
-	END PROCESS;
-	
-END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
deleted file mode 100644
index b3ae7d5..0000000
--- a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
+++ /dev/null
@@ -1,126 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.PCK_FIO.all;
-use work.fixed_util_pkg.all;
-
-ENTITY tb_cic_i_pipe IS
-	Generic
-	(
-		max_width		: integer := 32;
-		max_width_frac	: integer := 20
-	);
-END tb_cic_i_pipe;
-
-ARCHITECTURE behavior OF tb_cic_i_pipe IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT cic_i_pipe
-	GENERIC
-	(
-		max_width		: integer;
-		max_width_frac	: integer
-	);
-	PORT
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		vld_in		: in std_logic;
-		din			: in sfixed;
-		dout		: out sfixed;
-		vld_out 	: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk			: std_logic := '0';
-	SIGNAL srst			: std_logic := '1';
-	SIGNAL vld_in		: std_logic := '0';
-	SIGNAL din			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	
-	--Outputs
-	SIGNAL dout			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
-	SIGNAL vld_out		: std_logic;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: cic_i_pipe 
-	GENERIC MAP
-	(
-		max_width		=> max_width,
-		max_width_frac	=> max_width_frac
-	)
-	PORT MAP
-	(
-		clk				=> clk,
-		rst				=> srst,
-		vld_in			=> vld_in,
-		din				=> din,
-		dout			=> dout,
-		vld_out			=> vld_out
-	);
-
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		din		<= to_sfixed(0.0, din);
-		vld_in	<= '1';
-
-		wait for 9*PERIOD;
-		wait until rising_edge(clk);
-
-		din		<= to_sfixed(0.5, din);
-
-		wait for 9*PERIOD;
-		wait until rising_edge(clk);
-		vld_in	<= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-END;
diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo
deleted file mode 100644
index 78a7729..0000000
--- a/lib/radio/mix/sim/tb_mix_cpx.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/mix_cpx.vhd"
-vcom -explicit  -93 "../src/tb_mix_cpx.vhd"
-vsim -t 1ps   -lib work tb_mix_cpx
-do {tb_mix_cpx.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo
deleted file mode 100644
index c84c651..0000000
--- a/lib/radio/mix/sim/tb_mix_cpx.wdo
+++ /dev/null
@@ -1,42 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix_cpx/clk
-add wave -noupdate -format Logic /tb_mix_cpx/srst
-add wave -noupdate -divider {Fixed In}
-add wave -noupdate -format Logic /tb_mix_cpx/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in
-add wave -noupdate -divider {Fixed OUT}
-add wave -noupdate -format Logic /tb_mix_cpx/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out
-add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out
-add wave -noupdate -divider {Convenient real out}
-add wave -noupdate -format Literal /tb_mix_cpx/x_re
-add wave -noupdate -format Literal /tb_mix_cpx/x_im
-add wave -noupdate -format Literal /tb_mix_cpx/y_re
-add wave -noupdate -format Literal /tb_mix_cpx/y_im
-add wave -noupdate -format Literal /tb_mix_cpx/z_re
-add wave -noupdate -format Literal /tb_mix_cpx/z_im
-add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left
-add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {90000 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo
deleted file mode 100644
index 0dbc45f..0000000
--- a/lib/radio/mix/sim/tb_mix_real.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/mix_real.vhd"
-vcom -explicit  -93 "../src/tb_mix_real.vhd"
-vsim -t 1ps   -lib work tb_mix_real
-do {tb_mix_real.wdo}
-view wave
-view structure
-view signals
-run 500ns
diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo
deleted file mode 100644
index 6643ce3..0000000
--- a/lib/radio/mix/sim/tb_mix_real.wdo
+++ /dev/null
@@ -1,36 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix_real/clk
-add wave -noupdate -format Logic /tb_mix_real/srst
-add wave -noupdate -divider {Fixed In}
-add wave -noupdate -format Logic /tb_mix_real/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din
-add wave -noupdate -divider {Fixed OUT}
-add wave -noupdate -format Logic /tb_mix_real/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout
-add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout
-add wave -noupdate -divider {Convenient real out}
-add wave -noupdate -format Literal /tb_mix_real/x_re
-add wave -noupdate -format Literal /tb_mix_real/y_re
-add wave -noupdate -format Literal /tb_mix_real/y_im
-add wave -noupdate -format Literal /tb_mix_real/z_re
-add wave -noupdate -format Literal /tb_mix_real/z_im
-add wave -noupdate -format Logic /tb_mix_real/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {120000 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {348406 ps}
diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo
deleted file mode 100644
index 2450220..0000000
--- a/lib/radio/mix/sim/tb_undc_real.fdo
+++ /dev/null
@@ -1,15 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/undc_real.vhd"
-vcom -explicit  -93 "../src/tb_undc_real.vhd"
-vsim -t 1ps   -lib work tb_undc_real
-do {tb_undc_real.wdo}
-view wave
-view structure
-view signals
-run 500us
diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo
deleted file mode 100644
index f965905..0000000
--- a/lib/radio/mix/sim/tb_undc_real.wdo
+++ /dev/null
@@ -1,38 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_undc_real/clk
-add wave -noupdate -format Logic /tb_undc_real/srst
-add wave -noupdate -format Logic /tb_undc_real/din_valid
-add wave -noupdate -format Logic /tb_undc_real/kin_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out
-add wave -noupdate -format Logic /tb_undc_real/dout_valid
-add wave -noupdate -format Literal /tb_undc_real/k
-add wave -noupdate -format Literal /tb_undc_real/x
-add wave -noupdate -format Literal /tb_undc_real/y
-add wave -noupdate -format Literal /tb_undc_real/dc
-add wave -noupdate -divider UUT
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2
-add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {97905405 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {157500 ns}
diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd
deleted file mode 100644
index 3df161e..0000000
--- a/lib/radio/mix/src/mix_cpx.vhd
+++ /dev/null
@@ -1,171 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    mix_cpx - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity mix_cpx is
-Generic
-(
-	nbits_in		: integer := 12;
-	nbits_in_frac	: integer := 12;
-	nbits_out		: integer := 12;
-	nbits_out_frac	: integer := 12;
-	nbits_scale_z	: integer := 0;
-	has_in_reg		: boolean := false;
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false;
-	rounding		: fixed_round_style_type := fixed_round;
-	saturating		: fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	in_valid	: in std_logic;
-	x_re_in		: in sfixed;
-	x_im_in		: in sfixed;
-	y_re_in		: in sfixed;
-	y_im_in		: in sfixed;
-	out_valid	: out std_logic;
-	z_re_out	: out sfixed;
-	z_im_out	: out sfixed
-);
-end mix_cpx;
-
-architecture Behavioral of mix_cpx is
-constant nbits_prod : integer := nbits_out + nbits_scale_z;
-constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
-
-signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
-	proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in)
-	begin
-		if has_in_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					x_re <= to_sfixed(0, x_re);
-					x_im <= to_sfixed(0, x_im);
-					y_re <= to_sfixed(0, y_re);
-					y_im <= to_sfixed(0, y_im);
-					valid <= '0';
-				else
-					valid <= in_valid;
-					if in_valid = '1' then
-						x_re <= x_re_in;
-						x_im <= x_im_in;
-						y_re <= y_re_in;
-						y_im <= y_im_in;
-					end if;
-				end if;
-			end if;
-		else
-			x_re <= x_re_in;
-			x_im <= x_im_in;
-			y_re <= y_re_in;
-			y_im <= y_im_in;
-			valid <= in_valid;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im)
-	variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
-	variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low);
-	
-	begin
-		re_left  := resize(x_re * y_re, re_left);
-		re_right := resize(x_im * y_im, re_right);
-		im_left  := resize(x_re * y_im, im_left);
-		im_right := resize(x_im * y_re, im_right);
-		if has_pipe_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					p_re_left  <= to_sfixed(0, p_re_left);
-					p_re_right <= to_sfixed(0, p_re_right);
-					p_im_left  <= to_sfixed(0, p_im_left);
-					p_im_right <= to_sfixed(0, p_im_right);
-					p_valid <= '0';
-				else
-					p_re_left  <= re_left;
-					p_re_right <= re_right;
-					p_im_left  <= im_left;
-					p_im_right <= im_right;
-					p_valid <= valid;
-				end if;	
-			end if;	
-		else	
-			p_re_left  <= re_left;
-			p_re_right <= re_right;
-			p_im_left  <= im_left;
-			p_im_right <= im_right;
-			p_valid <= valid;
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-	proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right)
-	variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	begin
-		sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, saturating, rounding);
-		sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, saturating, rounding);
-		if has_out_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					z_re_out  <= to_sfixed(0, re);
-					z_im_out  <= to_sfixed(0, im);
-					out_valid <= '0';
-				else
-					z_re_out <= sum_re;
-					z_im_out <= sum_im;
-					out_valid <= p_valid;
-				end if;	
-			end if;	
-		else	
-			z_re_out <= re;
-			z_im_out <= im;
-			out_valid <= p_valid;
-		end if;	
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd
deleted file mode 100644
index 37e96de..0000000
--- a/lib/radio/mix/src/mix_real.vhd
+++ /dev/null
@@ -1,160 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    mix_cpx - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity mix_real is
-Generic
-(
-	nbits_in		: integer := 12;
-	nbits_in_frac	: integer := 12;
-	nbits_out		: integer := 12;
-	nbits_out_frac	: integer := 12;
-	nbits_scale_z	: integer := 0;
-	has_in_reg		: boolean := false;
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false;
-	rounding		: fixed_round_style_type := fixed_round;
-	saturating		: fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	in_valid	: in std_logic;
-	x_re_din	: in sfixed;
-	y_re_din	: in sfixed;
-	y_im_din	: in sfixed;
-	out_valid	: out std_logic;
-	z_re_dout	: out sfixed;
-	z_im_dout	: out sfixed
-);
-end mix_real;
-
-architecture Behavioral of mix_real is
-
-constant nbits_prod : integer := nbits_out + nbits_scale_z;
-constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z;
-
-signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
-	proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din)
-	begin
-		if has_in_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					x_re <= to_sfixed(0, x_re);
-					y_re <= to_sfixed(0, y_re);
-					y_im <= to_sfixed(0, y_im);
-					valid <= '0';
-				else
-					valid <= in_valid;
-					if in_valid = '1' then
-						x_re <= x_re_din;
-						y_re <= y_re_din;
-						y_im <= y_im_din;
-					end if;
-				end if;
-			end if;
-		else
-			x_re <= x_re_din;
-			y_re <= y_re_din;
-			y_im <= y_im_din;
-			valid <= in_valid;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im)
-	variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-	variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low);
-	
-	begin
-		re_left  := resize(x_re * y_re, re_left);
-		im_left  := resize(x_re * y_im, im_left);
-		if has_pipe_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					p_re_left  <= to_sfixed(0, p_re_left);
-					p_im_left  <= to_sfixed(0, p_im_left);
-					p_valid <= '0';
-				else
-					p_re_left  <= re_left;
-					p_im_left  <= im_left;
-					p_valid <= valid;
-				end if;	
-			end if;	
-		else	
-			p_re_left  <= re_left;
-			p_im_left  <= im_left;
-			p_valid <= valid;
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-	proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left)
-	variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	begin
-		sum_re := resize(scalb(p_re_left, nbits_scale_z), re, saturating, rounding);
-		sum_im := resize(scalb(p_im_left, nbits_scale_z), im, saturating, rounding);
-		if has_out_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					z_re_dout  <= to_sfixed(0, re);
-					z_im_dout  <= to_sfixed(0, im);
-					out_valid <= '0';
-				else
-					z_re_dout <= sum_re;
-					z_im_dout <= sum_im;
-					out_valid <= p_valid;
-				end if;	
-			end if;	
-		else	
-			z_re_dout <= re;
-			z_im_dout <= im;
-			out_valid <= p_valid;
-		end if;	
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd
deleted file mode 100644
index 5eac130..0000000
--- a/lib/radio/mix/src/tb_mix_cpx.vhd
+++ /dev/null
@@ -1,211 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix_cpx IS
-	Generic (
-		nbits_in		: integer := 24;
-		nbits_in_frac	: integer := 24;
-		nbits_out		: integer := 24;
-		nbits_out_frac	: integer := 24;
-		nbits_scale_z	: integer := 0;
-		has_in_reg		: boolean := true;
-		has_pipe_reg	: boolean := true;
-		has_out_reg		: boolean := true;
-		rounding		: fixed_round_style_type := fixed_round;
-		saturating		: fixed_overflow_style_type := fixed_saturate
-	        );
-END tb_mix_cpx;
-
-ARCHITECTURE behavior OF tb_mix_cpx IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT mix_cpx
-	GENERIC
-	(
-		nbits_in		: integer;
-		nbits_in_frac	: integer;
-		nbits_out		: integer;
-		nbits_out_frac	: integer;
-		nbits_scale_z	: integer;
-		has_in_reg		: boolean;
-		has_pipe_reg	: boolean;
-		has_out_reg		: boolean;
-		rounding		: fixed_round_style_type;
-		saturating		: fixed_overflow_style_type
-	);
-	PORT
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		in_valid	: in std_logic;
-		x_re_in		: in sfixed;
-		x_im_in		: in sfixed;
-		y_re_in		: in sfixed;
-		y_im_in		: in sfixed;
-		out_valid	: out std_logic;
-		z_re_out	: out sfixed;
-		z_im_out	: out sfixed
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_re_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	SIGNAL x_im_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	SIGNAL y_re_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	SIGNAL y_im_in     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-
-	--Outputs
-	SIGNAL z_re_out    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	SIGNAL z_im_out    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	SIGNAL out_valid   : std_logic;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-	SIGNAL x_re    : real := 0.0;
-	SIGNAL x_im    : real := 0.0;
-	SIGNAL y_re    : real := 0.0;
-	SIGNAL y_im    : real := 0.0;
-	SIGNAL z_re    : real := 0.0;
-	SIGNAL z_im    : real := 0.0;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: mix_cpx 
-	GENERIC MAP
-	(
-		nbits_in		=> nbits_in,
-		nbits_in_frac	=> nbits_in_frac,
-		nbits_out		=> nbits_out,
-		nbits_out_frac	=> nbits_out_frac,
-		nbits_scale_z	=> nbits_scale_z,
-		has_in_reg		=> has_in_reg,
-		has_pipe_reg	=> has_pipe_reg,
-		has_out_reg		=> has_out_reg,
-		rounding		=> rounding,
-		saturating		=> saturating
-	)
-	PORT MAP
-	(
-		srst		=> srst,
-		clk			=> clk,
-		in_valid	=> in_valid,
-		x_re_in		=> x_re_in,
-		x_im_in		=> x_im_in,
-		y_re_in		=> y_re_in,
-		y_im_in		=> y_im_in,
-		out_valid	=> out_valid,
-		z_re_out	=> z_re_out,
-		z_im_out	=> z_im_out
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.5, x_re_in);
-		x_im_in <= to_sfixed(0.5, x_im_in);
-		y_re_in <= to_sfixed(0.5, y_re_in);
-		y_im_in <= to_sfixed(0.5, y_im_in);
-		in_valid <= '1';
-		wait until rising_edge(clk);
-		in_valid <= '0';
-		wait for 5*PERIOD;
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.125, x_re_in);
-		x_im_in <= to_sfixed(0.25, x_im_in);
-		y_re_in <= to_sfixed(0.25, y_re_in);
-		y_im_in <= to_sfixed(0.125, y_im_in);
-		in_valid <= '1';
-		wait until rising_edge(clk);
-		in_valid <= '0';
-		wait for 5*PERIOD;
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.125, x_re_in);
-		x_im_in <= to_sfixed(-0.25, x_im_in);
-		y_re_in <= to_sfixed(0.25, y_re_in);
-		y_im_in <= to_sfixed(0.125, y_im_in);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.125, x_re_in);
-		x_im_in <= to_sfixed(-0.25, x_im_in);
-		y_re_in <= to_sfixed(0.25, y_re_in);
-		y_im_in <= to_sfixed(0.125, y_im_in);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.3, x_re_in);
-		x_im_in <= to_sfixed(0.0, x_im_in);
-		y_re_in <= to_sfixed(-0.5, y_re_in);
-		y_im_in <= to_sfixed(0.5, y_im_in);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_in <= to_sfixed(0.0, x_re_in);
-		x_im_in <= to_sfixed(-0.7071, x_im_in);
-		y_re_in <= to_sfixed(0.0, y_re_in);
-		y_im_in <= to_sfixed(-0.7071, y_im_in);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		in_valid <= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	x_re <= to_real(x_re_in);
-	x_im <= to_real(x_im_in);
-	y_re <= to_real(y_re_in);
-	y_im <= to_real(y_im_in);
-	z_re <= to_real(z_re_out);
-	z_im <= to_real(z_im_out);
-	
-END;
diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd
deleted file mode 100644
index 8f0ce40..0000000
--- a/lib/radio/mix/src/tb_mix_real.vhd
+++ /dev/null
@@ -1,200 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix_real IS
-	Generic (
-		nbits_in		: integer := 24;
-		nbits_in_frac	: integer := 24;
-		nbits_out		: integer := 24;
-		nbits_out_frac	: integer := 24;
-		nbits_scale_z	: integer := 0;
-		has_in_reg		: boolean := true;
-		has_pipe_reg	: boolean := true;
-		has_out_reg		: boolean := true;
-		rounding		: fixed_round_style_type := fixed_round;
-		saturating		: fixed_overflow_style_type := fixed_saturate
-	        );
-END tb_mix_real;
-
-ARCHITECTURE behavior OF tb_mix_real IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT mix_real
-	GENERIC
-	(
-		nbits_in		: integer;
-		nbits_in_frac	: integer;
-		nbits_out		: integer;
-		nbits_out_frac	: integer;
-		nbits_scale_z	: integer;
-		has_in_reg		: boolean;
-		has_pipe_reg	: boolean;
-		has_out_reg		: boolean;
-		rounding		: fixed_round_style_type;
-		saturating		: fixed_overflow_style_type
-	);
-	PORT
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		in_valid	: in std_logic;
-		x_re_din		: in sfixed;
-		y_re_din		: in sfixed;
-		y_im_din		: in sfixed;
-		out_valid	: out std_logic;
-		z_re_dout	: out sfixed;
-		z_im_dout	: out sfixed
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL in_valid    : std_logic := '0';
-	SIGNAL x_re_din     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	SIGNAL y_re_din     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-	SIGNAL y_im_din     : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low);
-
-	--Outputs
-	SIGNAL z_re_dout    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	SIGNAL z_im_dout    : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
-	SIGNAL out_valid   : std_logic;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-	SIGNAL x_re    : real := 0.0;
-	SIGNAL y_re    : real := 0.0;
-	SIGNAL y_im    : real := 0.0;
-	SIGNAL z_re    : real := 0.0;
-	SIGNAL z_im    : real := 0.0;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: mix_real 
-	GENERIC MAP
-	(
-		nbits_in		=> nbits_in,
-		nbits_in_frac	=> nbits_in_frac,
-		nbits_out		=> nbits_out,
-		nbits_out_frac	=> nbits_out_frac,
-		nbits_scale_z	=> nbits_scale_z,
-		has_in_reg		=> has_in_reg,
-		has_pipe_reg	=> has_pipe_reg,
-		has_out_reg		=> has_out_reg,
-		rounding		=> rounding,
-		saturating		=> saturating
-	)
-	PORT MAP
-	(
-		srst		=> srst,
-		clk			=> clk,
-		in_valid	=> in_valid,
-		x_re_din		=> x_re_din,
-		y_re_din		=> y_re_din,
-		y_im_din		=> y_im_din,
-		out_valid	=> out_valid,
-		z_re_dout	=> z_re_dout,
-		z_im_dout	=> z_im_dout
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.5, x_re_din);
-		y_re_din <= to_sfixed(0.5, y_re_din);
-		y_im_din <= to_sfixed(0.5, y_im_din);
-		in_valid <= '1';
-		wait until rising_edge(clk);
-		in_valid <= '0';
-		wait for 5*PERIOD;
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.125, x_re_din);
-		y_re_din <= to_sfixed(0.25, y_re_din);
-		y_im_din <= to_sfixed(0.125, y_im_din);
-		in_valid <= '1';
-		wait until rising_edge(clk);
-		in_valid <= '0';
-		wait for 5*PERIOD;
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.125, x_re_din);
-		y_re_din <= to_sfixed(0.25, y_re_din);
-		y_im_din <= to_sfixed(0.125, y_im_din);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.125, x_re_din);
-		y_re_din <= to_sfixed(0.25, y_re_din);
-		y_im_din <= to_sfixed(0.125, y_im_din);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.3, x_re_din);
-		y_re_din <= to_sfixed(-0.5, y_re_din);
-		y_im_din <= to_sfixed(0.5, y_im_din);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		x_re_din <= to_sfixed(0.0, x_re_din);
-		y_re_din <= to_sfixed(0.0, y_re_din);
-		y_im_din <= to_sfixed(-0.7071, y_im_din);
-		in_valid <= '1';
-		------------------------------------------
-		wait until rising_edge(clk);
-		in_valid <= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	x_re <= to_real(x_re_din);
-	y_re <= to_real(y_re_din);
-	y_im <= to_real(y_im_din);
-	z_re <= to_real(z_re_dout);
-	z_im <= to_real(z_im_dout);
-	
-END;
diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd
deleted file mode 100644
index 3fc872b..0000000
--- a/lib/radio/mix/src/tb_undc_real.vhd
+++ /dev/null
@@ -1,161 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_mix_cpx
--- Module Name:   tb_mix_cpx.vhd
--- Project Name:  mix_cpx
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_undc_real IS
-	Generic (
-		nbits_data		: integer := 24;
-		nbits_data_frac	: integer := 24;
-		nbits_k			: integer := 24;
-		nbits_k_frac	: integer := 24;
-		has_in_reg		: boolean := true;
-		rounding		: fixed_round_style_type := fixed_round;
-		saturating		: fixed_overflow_style_type := fixed_saturate
-        );
-END tb_undc_real;
-
-ARCHITECTURE behavior OF tb_undc_real IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT undc_real
-	Generic
-	(
-		nbits_data		: integer;
-		nbits_data_frac	: integer;
-		nbits_k			: integer;
-		nbits_k_frac	: integer;
-		has_in_reg		: boolean;
-		rounding		: fixed_round_style_type;
-		saturating		: fixed_overflow_style_type
-	);
-	Port
-	(
-		srst		: in std_logic;
-		clk			: in std_logic;
-		din_valid	: in std_logic;
-		din			: in sfixed;
-		kin_valid	: in std_logic;
-		kin			: in sfixed;
-		dout_valid	: out std_logic;
-		dout		: out sfixed;
-		dc_out		: out sfixed
-	);
-	END COMPONENT;
-
-	--Constants
-	constant PERIOD : time := 10 ns;
-	
-
-	--Inputs
-	SIGNAL clk       : std_logic := '0';
-	SIGNAL srst      : std_logic := '1';
-	SIGNAL din_valid : std_logic := '0';
-	SIGNAL kin_valid : std_logic := '0';
-	SIGNAL din	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
-	SIGNAL kin	     : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
-
-	--Outputs
-	SIGNAL dout	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
-	SIGNAL dc_out	     : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
-	SIGNAL dout_valid   : std_logic;
-	
-	SIGNAL k    : real := 0.0;
-	SIGNAL x    : real := 0.0;
-	SIGNAL y    : real := 0.0;
-	SIGNAL dc    : real := 0.0;
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: undc_real 
-	GENERIC MAP
-	(
-		nbits_data		=> nbits_data,
-		nbits_data_frac	=> nbits_data_frac,
-		nbits_k			=> nbits_k,
-		nbits_k_frac	=> nbits_k_frac,
-		has_in_reg		=> has_in_reg,
-		rounding		=> rounding,
-		saturating		=> saturating
-	)
-	PORT MAP
-	(
-		srst		=> srst,
-		clk			=> clk,
-		din_valid	=> din_valid,
-		din			=> din,
-		kin_valid	=> kin_valid,
-		kin			=> kin,
-		dout_valid	=> dout_valid,
-		dout		=> dout,
-		dc_out		=> dc_out
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-		------------------------------------------
-		-- Load k
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		kin <= to_sfixed(0.0005, kin);
-		kin_valid <= '1';
-		wait until rising_edge(clk);
-		kin_valid <= '1';
-		------------------------------------------
-		-- Process
-		------------------------------------------
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-		din <= to_sfixed(0.5, din);
-		din_valid <= '1';
-		wait until rising_edge(clk);
-		din_valid <= '1';
-		wait for 5*PERIOD;
-
-		wait for 200*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	k <= to_real(kin);
-	x <= to_real(din);
-	y <= to_real(dout);
-	dc <= to_real(dc_out);
-	
-END;
diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd
deleted file mode 100644
index e4a3bba..0000000
--- a/lib/radio/mix/src/undc_real.vhd
+++ /dev/null
@@ -1,143 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    mix_cpx - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-use work.fixed_util_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity undc_real is
-Generic
-(
-	nbits_data		: integer := 12;
-	nbits_data_frac	: integer := 12;
-	nbits_k			: integer := 12;
-	nbits_k_frac	: integer := 12;
-	has_in_reg		: boolean := false;
-	rounding		: fixed_round_style_type := fixed_round;
-	saturating		: fixed_overflow_style_type := fixed_saturate
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	din_valid	: in std_logic;
-	din			: in sfixed;
-	kin_valid	: in std_logic;
-	kin			: in sfixed;
-	dout_valid	: out std_logic;
-	dout		: out sfixed;
-	dc_out		: out sfixed
-);
-end undc_real;
-
-architecture Behavioral of undc_real is
-
-constant nbits_internal : integer := nbits_data + nbits_data;
-constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac;
-
-signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low);
-signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low);
-signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low);
-
-begin
-
-dout <= resize(y, sproto(nbits_data, nbits_data_frac), saturating, rounding);
-dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), fixed_wrap, fixed_truncate);
-
-------------------------------------------------------------
-	proc_din_reg: process(clk, din_valid, din)
-	begin
-		if has_in_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					x <= to_sfixed(0, x);
-				else
-					if din_valid = '1' then
-						x <= din;
-					end if;
-				end if;
-			end if;
-		else
-			x <= din;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_valid_reg: process(clk, din_valid)
-	begin
-		if has_in_reg = true then
-			if rising_edge(clk) then
-				if srst = '1' then
-					dout_valid <= '0';
-				else
-					dout_valid <= din_valid;
-				end if;
-			end if;
-		else
-			dout_valid <= din_valid;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_kin_reg: process(clk, kin_valid, kin)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				k <= to_sfixed(0, k);
-			else
-				if kin_valid = '1' then
-					k <= kin;
-				end if;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_y: process(clk, x, dc)
-	begin
-		y <= resize(x - dc, y, fixed_wrap, fixed_truncate);
-		if rising_edge(clk) then
-			if srst = '1' then
-				y1 <= to_sfixed(0, y1);
-				y2 <= to_sfixed(0, y2);
-				dc <= to_sfixed(0, dc);
-			else
-				y1 <= y;
-				y2 <= resize(y1 * k, y2, fixed_wrap, fixed_truncate);
-				dc <= resize(y2 + dc, dc, fixed_wrap, fixed_truncate);
-			end if;	
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/sim/tb_mix_cordic.fdo b/lib/radio/nco/sim/tb_mix_cordic.fdo
deleted file mode 100644
index 3bd3ff4..0000000
--- a/lib/radio/nco/sim/tb_mix_cordic.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit  -93 "../src/mix_cordic.vhd"
-vcom -explicit  -93 "../src/tb_mix_cordic.vhd"
-vsim -t 1ps   -lib work tb_mix
-do {tb_mix_cordic.wdo}
-view wave
-view structure
-view signals
-run 400us
diff --git a/lib/radio/nco/sim/tb_mix_cordic.wdo b/lib/radio/nco/sim/tb_mix_cordic.wdo
deleted file mode 100644
index dc928bd..0000000
--- a/lib/radio/nco/sim/tb_mix_cordic.wdo
+++ /dev/null
@@ -1,42 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_mix/clk
-add wave -noupdate -format Logic /tb_mix/srst
-add wave -noupdate -format Logic /tb_mix/clk
-add wave -noupdate -format Logic /tb_mix/srst
-add wave -noupdate -format Logic /tb_mix/mix_nco_rst
-add wave -noupdate -format Logic /tb_mix/mix_nco_en
-add wave -noupdate -format Literal /tb_mix/mix_freq_in
-add wave -noupdate -format Literal /tb_mix/mix_phase_in
-add wave -noupdate -format Literal /tb_mix/mix_din_i
-add wave -noupdate -format Literal /tb_mix/mix_din_q
-add wave -noupdate -format Literal /tb_mix/mix_dout_i
-add wave -noupdate -format Literal /tb_mix/mix_dout_q
-add wave -noupdate -format Logic /tb_mix/mix_dout_vld
-add wave -noupdate -format Logic /tb_mix/mix_din_vld
-add wave -noupdate -format Logic /tb_mix/rfgen_nco_rst
-add wave -noupdate -format Logic /tb_mix/rfgen_nco_en
-add wave -noupdate -format Literal /tb_mix/rfgen_freq_in
-add wave -noupdate -format Literal /tb_mix/rfgen_phase_in
-add wave -noupdate -format Literal /tb_mix/rfgen_din_i
-add wave -noupdate -format Literal /tb_mix/rfgen_din_q
-add wave -noupdate -format Literal /tb_mix/rfgen_dout_i
-add wave -noupdate -format Literal /tb_mix/rfgen_dout_q
-add wave -noupdate -format Logic /tb_mix/rfgen_dout_vld
-add wave -noupdate -format Logic /tb_mix/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {249834550 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {146645950 ps} {228944950 ps}
diff --git a/lib/radio/nco/sim/tb_mix_results.m b/lib/radio/nco/sim/tb_mix_results.m
deleted file mode 100644
index 5997fea..0000000
--- a/lib/radio/nco/sim/tb_mix_results.m
+++ /dev/null
@@ -1,90 +0,0 @@
-% Read data
-function tb_mix_results()
-fa = 100.0;
-f = TEXTREAD('freq.txt')*1E-6
-R = 128;
-fa_dec = fa/R
-N_pfir = 63;
-
-I_in = TEXTREAD('i_in.txt')';
-I_out = TEXTREAD('i_out.txt')';
-Q_out = TEXTREAD('q_out.txt')';
-
-N= length(I_out)
-N_fft = N;
-N_fft2 = N_fft/2;
-
-fft_y2 = 2/N_fft*abs(fft(I_out(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y2, fa, f);
-max_spur_freq = (i*fa/N_fft);
-max_spur_value = 20*log10(v);
-
-fft_y3 = 2/N_fft*abs(fft(I_in(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y3, fa, f);
-max_ditherd_spur_freq = (i*fa/N_fft);
-max_ditherd_spur_value = 20*log10(v);
-
-I_out_dec = cic_filter(R, 1, 3, I_out);
-Q_out_dec = cic_filter(R, 1, 3, Q_out);
-N_dec = length(I_out_dec)-2*N_pfir;
-N_fft_dec = N_dec
-N_fft2_dec = N_fft_dec/2;
-fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-pfir_b = sinc(0.1*(-(N_pfir-1)/2:1:(N_pfir)/2));
-pfir_b = pfir_b/sum(pfir_b).*blackman(N_pfir)';
-I_out_dec_pfir = filter(pfir_b, 1, I_out_dec);
-Q_out_dec_pfir = filter(pfir_b, 1, Q_out_dec);
-fft_y2_dec_pfir = 2/N_fft_dec*abs(fft(I_out_dec_pfir(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
-
-% Output
-close all;
-
-plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec_pfir(1:N_fft2_dec+1)), '-'); grid;
-
-figure;
-plot(1:length(I_out_dec_pfir), I_out_dec_pfir, 1:length(Q_out_dec_pfir), Q_out_dec_pfir); grid;
-
-figure;
-freqz(pfir_b, 1, 1000);
-
-figure;
-plot(pfir_b); grid;
-
-
-figure;
-subplot(2,1,1)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_spur_value, max_spur_freq);
-legend('With dithering', spur_legend);
-legend('No dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-subplot(2,1,2)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
-legend('With dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-
-plot(1:N, I_out, 1:N, Q_out); grid;
-
-function [max_i, max_v] = get_maxpur(spec, fa, f)
-max_v = 0;
-max_i = 0;
-for ii=1:fix(length(spec)/2+1),
-	fi = ii*fa/length(spec);
-	dfi = fi - f;
-	if abs(dfi) > 0.005*f
-		if spec(ii) > max_v
-			max_v = spec(ii);
-			max_i = ii-1;
-		end
-	end;
-end;
diff --git a/lib/radio/nco/sim/tb_nco_cordic.fdo b/lib/radio/nco/sim/tb_nco_cordic.fdo
deleted file mode 100644
index 5c5e619..0000000
--- a/lib/radio/nco/sim/tb_nco_cordic.fdo
+++ /dev/null
@@ -1,19 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pkg.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_stage.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
-vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
-vcom -explicit  -93 "../src/mix_cordic.vhd"
-vcom -explicit  -93 "../src/tb_nco_cordic.vhd"
-vsim -t 1ps   -lib work tb_nco
-do {tb_nco_cordic.wdo}
-view wave
-view structure
-view signals
-run 250us
diff --git a/lib/radio/nco/sim/tb_nco_cordic.wdo b/lib/radio/nco/sim/tb_nco_cordic.wdo
deleted file mode 100644
index d41d308..0000000
--- a/lib/radio/nco/sim/tb_nco_cordic.wdo
+++ /dev/null
@@ -1,32 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_nco/uut/clk
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
-add wave -noupdate -divider Cordic
-add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin
-add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin
-add wave -noupdate -format Literal /tb_nco/mix_din_i
-add wave -noupdate -format Literal /tb_nco/mix_din_q
-add wave -noupdate -format Literal /tb_nco/mix_dout_i
-add wave -noupdate -format Literal /tb_nco/mix_dout_q
-add wave -noupdate -format Logic /tb_nco/mix_dout_vld
-add wave -noupdate -format Logic /tb_nco/mix_din_vld
-add wave -noupdate -format Logic /tb_nco/fileout_enable
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {243331511 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {239972168 ps} {248698737 ps}
diff --git a/lib/radio/nco/sim/tb_nco_lut.fdo b/lib/radio/nco/sim/tb_nco_lut.fdo
deleted file mode 100644
index 12f120e..0000000
--- a/lib/radio/nco/sim/tb_nco_lut.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit  -93 "../src/nco_pkg.vhd"
-vcom -explicit  -93 "../src/waverom_dual.vhd"
-vcom -explicit  -93 "../src/wavelut.vhd"
-vcom -explicit  -93 "../src/nco_lut_dbg.vhd"
-vcom -explicit  -93 "../src/tb_nco_lut.vhd"
-vsim -t 1ps   -lib work tb_nco
-do {tb_nco_lut.wdo}
-view wave
-view structure
-view signals
-run 250us
diff --git a/lib/radio/nco/sim/tb_nco_lut.wdo b/lib/radio/nco/sim/tb_nco_lut.wdo
deleted file mode 100644
index 0fd0917..0000000
--- a/lib/radio/nco/sim/tb_nco_lut.wdo
+++ /dev/null
@@ -1,46 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_nco/uut/srst
-add wave -noupdate -format Logic /tb_nco/uut/clk
-add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
-add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
-add wave -noupdate -format Logic /tb_nco/uut/freq_load
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
-add wave -noupdate -format Logic /tb_nco/uut/phase_load
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
-add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i
-add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q
-add wave -noupdate -format Logic /tb_nco/uut/out_valid
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud
-add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_i_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_q_d
-add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud
-add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud
-add wave -noupdate -format Literal /tb_nco/uut/lfsr
-add wave -noupdate -format Literal /tb_nco/uut/lfsr_out
-add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid
-add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid
-add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid
-add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {249141632 ps} 0}
-configure wave -namecolwidth 193
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {249024188 ps} {250051359 ps}
diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m
deleted file mode 100644
index b3fe27a..0000000
--- a/lib/radio/nco/sim/tb_nco_results.m
+++ /dev/null
@@ -1,61 +0,0 @@
-% Read data
-function tb_nco_results(nbins)
-fa = 100.0;
-f = TEXTREAD('freq.txt')*1E-6
-
-I_ud = TEXTREAD('q_ud.txt')';
-I_d = TEXTREAD('q_d.txt')';
-LFSR = TEXTREAD('lfsr.txt');
-
-N= length(I_ud);
-N_fft = min(16384, N);
-N_fft2 = N_fft/2;
-
-fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)'));
-fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)'));
-
-[i, v] = get_maxpur(fft_y2, fa, f);
-max_spur_freq = (i*fa/N_fft);
-max_spur_value = 20*log10(v);
-
-[i, v] = get_maxpur(fft_y3, fa, f);
-max_ditherd_spur_freq = (i*fa/N_fft);
-max_ditherd_spur_value = 20*log10(v);
-
-% Output
-close all;
-
-subplot(2,1,1)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq);
-legend('With dithering', spur_legend);
-legend('No dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-subplot(2,1,2)
-plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid;
-spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq);
-legend('With dithering', spur_legend);
-title('Table');
-ylabel('dB');
-xlabel('f/MHz');
-axis([0 fa/2 -140 0]);
-
-figure;
-hist(LFSR, nbins)
-
-function [max_i, max_v] = get_maxpur(spec, fa, f)
-max_v = 0;
-max_i = 0;
-for ii=1:fix(length(spec)/2+1),
-	fi = ii*fa/length(spec);
-	dfi = fi - f;
-	if abs(dfi) > 0.05*f
-		if spec(ii) > max_v
-			max_v = spec(ii);
-			max_i = ii;
-		end
-	end;
-end;
diff --git a/lib/radio/nco/src/mix_cordic.vhd b/lib/radio/nco/src/mix_cordic.vhd
deleted file mode 100644
index ad002a0..0000000
--- a/lib/radio/nco/src/mix_cordic.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity mix is
-Generic
-(
-	nbits_din		: integer := 18;
-	nbits_din_frac	: integer := 16;
-	nbits_dout		: integer := 18;
-	nbits_dout_frac	: integer := 16;
-	nbits_phase		: integer := 16;
-	nbits_freq		: integer := 16
-);
-Port
-(
-	rst				: in std_logic;
-	clk				: in std_logic;
-	nco_rst			: in std_logic;
-	nco_en			: in std_logic;
-	freq_in			: in unsigned(nbits_freq-1 downto 0);
-	phase_in		: in unsigned(nbits_phase-1 downto 0);
-	din_i			: in  sfixed;
-	din_q			: in  sfixed;
-	dout_i			: out sfixed;
-	dout_q			: out sfixed;
-	din_vld			: in std_logic;
-	dout_vld		: out std_logic
-);
-end mix;
-
-architecture Behavioral of mix is
-
-	COMPONENT cordic_pipe_top
-	GENERIC 
-	(
-		cordic_mode			: cordic_mode_t;
-		z_range				: real;
-		gain_corr_mode		: gain_corr_mode_t;
-		nstages				: integer;
-		nbits_x_in			: integer;
-		nbits_y_in			: integer;
-		nbits_z_in			: integer;
-		nbits_frac_x_in		: integer;
-		nbits_frac_y_in		: integer;
-		nbits_frac_z_in		: integer;
-		nbits_x_out			: integer;
-		nbits_y_out			: integer;
-		nbits_z_out			: integer;
-		nbits_frac_x_out	: integer;
-		nbits_frac_y_out	: integer;
-		nbits_frac_z_out	: integer
-	);
-	PORT
-	(
-		rst					: in std_logic;
-		clk					: in std_logic;
-		vld_in				: in std_logic;
-		xin					: in sfixed;
-		yin					: in sfixed;
-		zin					: in sfixed;
-		xout				: out sfixed;
-		yout				: out sfixed;
-		zout				: out sfixed;
-		vld_out				: out std_logic
-	);
-	END COMPONENT;
-
--------------------------------------------------------------------------------
-	constant nbits_phase_frac : integer := nbits_phase;
-
--------------------------------------------------------------------------------
-	signal phase : signed(nbits_phase-1 downto 0);
-	signal xin, yin : sfixed(shi(nbits_din, nbits_din_frac) downto slo(nbits_din, nbits_din_frac));
-	signal xout, yout : sfixed(shi(nbits_dout, nbits_dout_frac) downto slo(nbits_dout, nbits_dout_frac));
-	
-	signal dout_valid : std_logic;
-
-	signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
-	signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
-	
--------------------------------------------------------------------------------
-begin
-
-	dout_i		<= xout;
-	dout_q		<= yout;
-	xin			<= din_i;
-	yin			<= din_q;
-	
-	dout_vld	<= dout_valid;
-
-------------------------------------------------------------
-	proc_phase_accu: process(clk)
-	variable phase_accu : signed(nbits_phase-1 downto 0);
-
-	begin
-		if rising_edge(clk) then 
-			if rst = '1' or nco_rst = '1' then
-				phase_accu	:= (others => '0');
-			elsif nco_en = '1' then
-				phase		<= phase_accu + signed(phase_in);
-				phase_accu	:= phase_accu + signed(freq_in);
-			end if;	
-		end if;
-		zin	<= sfixed(phase);
-	end process;
-
-------------------------------------------------------------
-	inst_cordic: cordic_pipe_top
-	GENERIC MAP
-	(
-		cordic_mode 		=> cordic_mode_rotate,
-		z_range				=> 1.0,
-		gain_corr_mode		=> gain_mode_disabled,
-		nstages				=> nbits_phase,
-		nbits_x_in			=> nbits_din,
-		nbits_frac_x_in		=> nbits_din_frac,
-		nbits_y_in			=> nbits_din,
-		nbits_frac_y_in		=> nbits_din_frac,
-		nbits_z_in			=> nbits_phase,
-		nbits_frac_z_in		=> nbits_phase_frac,
-		nbits_x_out			=> nbits_dout,
-		nbits_frac_x_out	=> nbits_dout_frac,
-		nbits_y_out			=> nbits_dout,
-		nbits_frac_y_out	=> nbits_dout_frac,
-		nbits_z_out			=> nbits_phase,
-		nbits_frac_z_out	=> nbits_phase_frac
-	)
-	PORT MAP
-	(
-		rst					=> rst,
-		clk					=> clk,
-		vld_in				=> din_vld,
-		xin					=> xin,
-		yin					=> yin,
-		zin					=> zin,
-		xout				=> xout,
-		yout				=> yout,
-		zout				=> zout,
-		vld_out				=> dout_valid
-	);
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak
deleted file mode 100644
index 657b97a..0000000
--- a/lib/radio/nco/src/nco.vhd.bak
+++ /dev/null
@@ -1,240 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use work.fixed_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
-	nbits_wave		: integer := 12;
-	nbits_phase		: integer := 16; 
-	nbits_lut_depth	: integer := 12; 
-	nbits_dither	: integer := 4; 
-	nbits_lfsr		: integer := 12; 
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	pacc_clr	: in std_logic;
-	pacc_inc	: in std_logic;
-	freq_in		: in unsigned(nbits_phase-1 downto 0);
-	freq_load	: in std_logic;
-	phase_in	: in unsigned(nbits_phase-1 downto 0);
-	phase_load	: in std_logic;
-	phase_out	: out unsigned(nbits_phase-1 downto 0);
-	wave_out_i	: out sfixed;
-	wave_out_q	: out sfixed;
-	out_valid	: out std_logic
-);
-end nco;
-
-architecture Behavioral of nco is
-
-	COMPONENT wavelut
-	Generic
-	(
-		nbits_wave		: integer;
-		nbits_wave_frac	: integer;
-		nbits_lut_depth	: integer; 
-		has_out_reg		: boolean
-	);
-	Port
-	(
-		clk			: in std_logic;
-		addr_valid	: in std_logic;
-		addr		: in unsigned(nbits_lut_depth-1 downto 0);
-		wave_i_out	: out sfixed;
-		wave_q_out	: out sfixed
-	);
-	END COMPONENT;
-
--------------------------------------------------------------------------------
-	constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
-	constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr);	-- 24
-	
-	signal valid : std_logic_vector(3 downto 0);
-	signal phase : unsigned(nbits_phase-1 downto 0);
-	signal freq_in_r : unsigned(nbits_phase-1 downto 0);
-	signal phase_in_r : unsigned(nbits_phase-1 downto 0);
-	signal lsfr_sum : unsigned(nbits_phase-1 downto 0);
-	signal lut_addr : unsigned(nbits_lut_depth-1 downto 0);
-	signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
-	signal lfsr : lfsr_t;
-	signal lfsr_out : unsigned(nbits_dither-1 downto 0);
-	signal lut_addr_valid _ std_logic;
-	
--------------------------------------------------------------------------------
-begin
-
-	wave_out_i <= wave_i;
-	wave_out_q <= wave_q;
-
-------------------------------------------------------------
-	proc_ctrl: process(srst, clk, pacc_inc, pacc_clr)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				valid <= (others => '0');
-			else
-				valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr);
-			end if;	
-		end if;	
-	end process;
-
-------------------------------------------------------------
-	proc_lfsr: process(srst, clk, lfsr, pacc_inc)
-	variable lo : unsigned(nbits_dither downto 0);
-	begin
-	   if rising_edge(clk) then
-		  if srst = '1' then
-				for i in lfsr'range loop
-					lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr); 
-				end loop;	
-		  elsif pacc_inc ='1' then 
-				lo := (others => '0'); 
-				for i in lfsr'range loop
-					if lfsr(i)(lfsr(i)'left) = '1' then
-						lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
-			else
-						lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
-			end if;	
-				end loop;	
-				for i in lfsr'range loop
-					lo := lo + lfsr(i)(nbits_dither-1 downto 0); 
-				end loop;	
---				lo := lfsr(0)(nbits_dither downto 0); 
-				lfsr_out <= lo(nbits_dither-1 downto 0);
-		  end if;
-	   end if;
-	end process;
-
-------------------------------------------------------------
-	proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
-	variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
-	begin
-		if rising_edge(clk) then 
-			if srst = '1' then
-				phase_accu := (others => '0');
-			else
-				phase <= phase_accu + phase_in_r;
-				if pacc_clr = '1' then
-					phase_accu := (others => '0');
-				elsif pacc_inc = '1' then
-					phase_accu := phase_accu + freq_in_r;
-				end if;	
-			end if;	
-		end if;
-	end process;
-
-------------------------------------------------------------
-	freq_in_reg: process(srst, clk, freq_load, freq_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				freq_in_r <= (others => '0');
-			elsif freq_load = '1' then
-				freq_in_r <= freq_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	phase_in_reg: process(srst, clk, phase_load, phase_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				phase_in_r <= (others => '0');
-			elsif phase_load = '1' then
-				phase_in_r <= phase_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(clk)
-	begin
-		if rising_edge(clk) then
-			lsfr_sum <= lfsr_out + phase;
-			lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
-		end if;	
-	end process;
-	
-------------------------------------------------------------
-	proc_out_reg: process(clk, phase)
-	begin
-		if has_out_reg = true then
-			if rising_edge(clk) then
-				phase_out <= phase;
-			end if;	
-		else	
-			phase_out <= phase;
-		end if;	
-	end process;
-
-------------------------------------------------------------
-	proc_valid_reg: process(clk, valid)
-	begin
-		out_valid <= valid(valid'right+1);
-		if has_out_reg = true then
-			out_valid <= valid(valid'right+2);
-			if has_pipe_reg = true then
-				out_valid <= valid(valid'right+3);
-			end if;	
-		elsif has_pipe_reg = true then
-			out_valid <= valid(valid'right+2);
-		end if;
-	end process;
-
-------------------------------------------------------------
-	inst_wavelut_d: wavelut
-	GENERIC MAP
-	(
-		nbits_wave		=> nbits_wave,
-		nbits_wave_frac	=> nbits_wave_frac,
-		nbits_lut_depth	=> nbits_lut_depth,
-		has_out_reg		=> has_out_reg
-	)
-	PORT MAP
-	(
-		clk			=> clk,
-		addr		=> lut_addr,
-		addr_valid	=> lut_addr_valid,
-		wave_i_out	=> wave_i,
-		wave_q_out	=> wave_q
-	);
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_lut.vhd b/lib/radio/nco/src/nco_lut.vhd
deleted file mode 100644
index 09e1e87..0000000
--- a/lib/radio/nco/src/nco_lut.vhd
+++ /dev/null
@@ -1,229 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
-	nbits_wave		: integer := 18;
-	nbits_phase		: integer := 16; 
-	nbits_lut_depth	: integer := 12; 
-	nbits_dither	: integer := 4; 
-	nbits_lfsr		: integer := 12; 
-	q_phase			: phase_relation_t := phase_90deg;
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	pacc_clr	: in std_logic;
-	pacc_inc	: in std_logic;
-	freq_in		: in unsigned(nbits_phase-1 downto 0);
-	freq_load	: in std_logic;
-	phase_in	: in unsigned(nbits_phase-1 downto 0);
-	phase_load	: in std_logic;
-	phase_out	: out unsigned(nbits_phase-1 downto 0);
-	wave_out_i	: out sfixed;
-	wave_out_q	: out sfixed;
-	out_valid	: out std_logic
-);
-end nco;
-
-architecture Behavioral of nco is
-
-	COMPONENT wavelut
-	Generic
-	(
-		nbits_wave		: integer;
-		nbits_wave_frac	: integer;
-		nbits_lut_depth	: integer; 
-		q_phase			: phase_relation_t;
-		has_out_reg		: boolean
-	);
-	Port
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		addr_valid	: in std_logic;
-		addr		: in unsigned(nbits_lut_depth-1 downto 0);
-		wave_i_out	: out sfixed;
-		wave_q_out	: out sfixed;
-		valid_out	: out std_logic
-	);
-	END COMPONENT;
-
--------------------------------------------------------------------------------
-	constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
-	constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr);	-- 24
-	
-	signal phase : unsigned(nbits_phase-1 downto 0);
-	signal freq_in_r : unsigned(nbits_phase-1 downto 0);
-	signal phase_in_r : unsigned(nbits_phase-1 downto 0);
-	signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
-	signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	
-	type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
-	signal lfsr : lfsr_t;
-	signal lfsr_out : unsigned(nbits_dither-1 downto 0);
-	signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic;
-	
--------------------------------------------------------------------------------
-begin
-
-	wave_out_i <= wave_i_d;
-	wave_out_q <= wave_q_d;
-	out_valid <= wave_d_valid;
-
-------------------------------------------------------------
-	proc_lfsr: process(srst, clk, lfsr, pacc_inc)
-	variable lo : unsigned(nbits_dither-1 downto 0);
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				lfsr_valid <= '0';
-				lfsr_out <= (others => '0'); 
-				for i in lfsr'range loop
-					lfsr(i) <= to_unsigned(2**i, nbits_lfsr); 
-				end loop;	
-			else
-				lfsr_valid <= '0';
-				if pacc_inc ='1' then 
-					lfsr_valid <= '1';
-					lo := (others => '0'); 
-					for i in lfsr'range loop
-						if lfsr(i)(lfsr(i)'left) = '1' then
-							lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
-						else
-							lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
-						end if;
-					end loop;	
-					for i in lfsr'range loop
-						lo := lo + lfsr(i)(nbits_dither-1 downto 0); 
-					end loop;	
-	--				lo := lfsr(0)(nbits_dither downto 0); 
-					lfsr_out <= lo(nbits_dither-1 downto 0);
-				end if;	
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_phase_accu: process(clk, phase)
-	variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
-	begin
-		if rising_edge(clk) then 
-			if srst = '1' then
-				phase_accu := (others => '0');
-			else
-				phase <= phase_accu + phase_in_r;
-				if pacc_clr = '1' then
-					phase_accu := (others => '0');
-				elsif pacc_inc = '1' then
-					phase_accu := phase_accu + freq_in_r;
-				end if;	
-			end if;	
-		end if;
-		phase_out <= phase;
-	end process;
-
-------------------------------------------------------------
-	freq_in_reg: process(srst, clk, freq_load, freq_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				freq_in_r <= (others => '0');
-			elsif freq_load = '1' then
-				freq_in_r <= freq_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	phase_in_reg: process(srst, clk, phase_load, phase_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				phase_in_r <= (others => '0');
-			elsif phase_load = '1' then
-				phase_in_r <= phase_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(clk)
-	variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
-	begin
-		if rising_edge(clk) then
-			lut_addr_valid <= '0';
-			if srst = '1' then
-				lfsr_sum := (others => '0');
-			elsif lfsr_valid = '1' then
-				lut_addr_valid <= '1';
-				lfsr_sum := lfsr_out + phase;
-			end if;	
-		end if;	
-		lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
-	end process;
-	
-------------------------------------------------------------
-	inst_wavelut_d: wavelut
-	GENERIC MAP
-	(
-		nbits_wave		=> nbits_wave,
-		nbits_wave_frac	=> nbits_wave_frac,
-		nbits_lut_depth	=> nbits_lut_depth,
-		q_phase			=> q_phase,
-		has_out_reg		=> has_out_reg
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		addr_valid	=> lut_addr_valid,
-		addr		=> lut_addr_d,
-		wave_i_out	=> wave_i_d,
-		wave_q_out	=> wave_q_d,
-		valid_out	=> wave_d_valid
-	);
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_lut_dbg.vhd b/lib/radio/nco/src/nco_lut_dbg.vhd
deleted file mode 100644
index a766e7d..0000000
--- a/lib/radio/nco/src/nco_lut_dbg.vhd
+++ /dev/null
@@ -1,259 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity nco is
-Generic
-(
-	nbits_wave		: integer := 18;
-	nbits_phase		: integer := 16; 
-	nbits_lut_depth	: integer := 12; 
-	nbits_dither	: integer := 4; 
-	nbits_lfsr		: integer := 12; 
-	q_phase			: phase_relation_t := phase_90deg;
-	has_pipe_reg	: boolean := false;
-	has_out_reg		: boolean := false
-);
-Port
-(
-	srst		: in std_logic;
-	clk			: in std_logic;
-	pacc_clr	: in std_logic;
-	pacc_inc	: in std_logic;
-	freq_in		: in unsigned(nbits_phase-1 downto 0);
-	freq_load	: in std_logic;
-	phase_in	: in unsigned(nbits_phase-1 downto 0);
-	phase_load	: in std_logic;
-	phase_out	: out unsigned(nbits_phase-1 downto 0);
-	wave_out_i	: out sfixed;
-	wave_out_q	: out sfixed;
-	out_valid	: out std_logic;
-	debug_out	: out debug_out_t
-);
-end nco;
-
-architecture Behavioral of nco is
-
-	COMPONENT wavelut
-	Generic
-	(
-		nbits_wave		: integer;
-		nbits_wave_frac	: integer;
-		nbits_lut_depth	: integer; 
-		q_phase			: phase_relation_t;
-		has_out_reg		: boolean
-	);
-	Port
-	(
-		clk			: in std_logic;
-		rst			: in std_logic;
-		addr_valid	: in std_logic;
-		addr		: in unsigned(nbits_lut_depth-1 downto 0);
-		wave_i_out	: out sfixed;
-		wave_q_out	: out sfixed;
-		valid_out	: out std_logic
-	);
-	END COMPONENT;
-
--------------------------------------------------------------------------------
-	constant nbits_wave_frac : integer := nbits_wave;
-
--------------------------------------------------------------------------------
-	constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr);	-- 24
-	
-	signal phase : unsigned(nbits_phase-1 downto 0);
-	signal freq_in_r : unsigned(nbits_phase-1 downto 0);
-	signal phase_in_r : unsigned(nbits_phase-1 downto 0);
-	signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0);
-	signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0);
-	signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	
-	type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0);
-	signal lfsr : lfsr_t;
-	signal lfsr_out : unsigned(nbits_dither-1 downto 0);
-	signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic;
-	
--------------------------------------------------------------------------------
-begin
-
-	wave_out_i <= wave_i_d;
-	wave_out_q <= wave_q_d;
-	out_valid <= wave_d_valid;
-
-	debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out;
-	debug_out.i_d <= to_real(wave_i_d);
-	debug_out.q_d <= to_real(wave_q_d);
-	debug_out.i_ud <= to_real(wave_i_ud);
-	debug_out.q_ud <= to_real(wave_q_ud);
-
-------------------------------------------------------------
-	proc_lfsr: process(srst, clk, lfsr, pacc_inc)
-	variable lo : unsigned(nbits_dither-1 downto 0);
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				lfsr_valid <= '0';
-				lfsr_out <= (others => '0'); 
-				for i in lfsr'range loop
-					lfsr(i) <= to_unsigned(2**i, nbits_lfsr); 
-				end loop;	
-			else
-				lfsr_valid <= '0';
-				if pacc_inc ='1' then 
-					lfsr_valid <= '1';
-					lo := (others => '0'); 
-					for i in lfsr'range loop
-						if lfsr(i)(lfsr(i)'left) = '1' then
-							lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly;
-						else
-							lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left);
-						end if;
-					end loop;	
-					for i in lfsr'range loop
-						lo := lo + lfsr(i)(nbits_dither-1 downto 0); 
-					end loop;	
-	--				lo := lfsr(0)(nbits_dither downto 0); 
-					lfsr_out <= lo(nbits_dither-1 downto 0);
-				end if;	
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
-	variable phase_accu : unsigned(nbits_phase-1 downto 0);
-
-	begin
-		if rising_edge(clk) then 
-			if srst = '1' then
-				phase_accu := (others => '0');
-			else
-				phase <= phase_accu + phase_in_r;
-				if pacc_clr = '1' then
-					phase_accu := (others => '0');
-				elsif pacc_inc = '1' then
-					phase_accu := phase_accu + freq_in_r;
-				end if;	
-			end if;	
-		end if;
-		phase_out <= phase;
-	end process;
-
-------------------------------------------------------------
-	freq_in_reg: process(srst, clk, freq_load, freq_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				freq_in_r <= (others => '0');
-			elsif freq_load = '1' then
-				freq_in_r <= freq_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	phase_in_reg: process(srst, clk, phase_load, phase_in)
-	begin
-		if rising_edge(clk) then
-			if srst = '1' then
-				phase_in_r <= (others => '0');
-			elsif phase_load = '1' then
-				phase_in_r <= phase_in;
-			end if;
-		end if;
-	end process;
-
-------------------------------------------------------------
-	proc_pipe_reg: process(clk)
-	variable lfsr_sum : unsigned(nbits_phase-1 downto 0);
-	begin
-		if rising_edge(clk) then
-			lut_addr_valid <= '0';
-			if srst = '1' then
-				lfsr_sum := (others => '0');
-			elsif lfsr_valid = '1' then
-				lut_addr_valid <= '1';
-				lfsr_sum := lfsr_out + phase;
-			end if;	
-		end if;	
-		lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
-		lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth);
-	end process;
-	
-------------------------------------------------------------
-	inst_wavelut_ud: wavelut
-	GENERIC MAP
-	(
-		nbits_wave		=> nbits_wave,
-		nbits_wave_frac	=> nbits_wave_frac,
-		nbits_lut_depth	=> nbits_lut_depth,
-		q_phase			=> q_phase,
-		has_out_reg		=> has_out_reg
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		addr_valid	=> lut_addr_valid,
-		addr		=> lut_addr_ud,
-		wave_i_out	=> wave_i_ud,
-		wave_q_out	=> wave_q_ud,
-		valid_out	=> wave_ud_valid
-	);
-
-	inst_wavelut_d: wavelut
-	GENERIC MAP
-	(
-		nbits_wave		=> nbits_wave,
-		nbits_wave_frac	=> nbits_wave_frac,
-		nbits_lut_depth	=> nbits_lut_depth,
-		q_phase			=> q_phase,
-		has_out_reg		=> has_out_reg
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		addr_valid	=> lut_addr_valid,
-		addr		=> lut_addr_d,
-		wave_i_out	=> wave_i_d,
-		wave_q_out	=> wave_q_d,
-		valid_out	=> wave_d_valid
-	);
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd
deleted file mode 100644
index d64b23a..0000000
--- a/lib/radio/nco/src/nco_pkg.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use IEEE.MATH_REAL.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-
--------------------------------------------------------------------------------
-package nco_pkg is
-
-	constant tpd : time := 0 ns;
-
-	type real_array_t is array (natural range <>) of real;
-	type natural_array_t is array (natural range <>) of natural;
-	type phase_relation_t is (phase_90deg, phase_270deg);
-	
-	type debug_out_t is record 
-		lfsr : unsigned(31 downto 0);
-		i_ud : real;
-		q_ud : real;
-		i_d : real;
-		q_d : real;
-	end record;
-
-	constant lfsr_poly : natural_array_t(3 to 24) := 
-	(
-		12,			-- 3
-		24,			-- 4
-		58,			-- 5
-		114,		-- 6
-		210,		-- 7
-		500,		-- 8
-		1000,		-- 9
-		1824,		-- 10
-		3712,		-- 11
-		7184,		-- 12
-		14592,		-- 13
-		28674,		-- 14
-		59392,		-- 15
-		106512,		-- 16
-		245760,		-- 17
-		466944,		-- 18
-		933888,		-- 19
-		1654784,	-- 20
-		3735552,	-- 21
-		7342080,	-- 22
-		14745600,	-- 23
-		14811138	-- 24
-	);
-	
-	function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
-	function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t;
-	
-end; -- package nco_pkg;
-
--------------------------------------------------------------------------------
-package body nco_pkg is
-
-	function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
-	variable tbl : real_array_t (0 to nsamples-1);
-	variable phi : real := phi_in;
-	variable dphi : real := 2.0*pi*omega;
-
-	begin
-		for i in 0 to nsamples-1 loop
-			tbl(i) := sin(phi);
-			phi := phi + dphi;
-		end loop;
-
-		return tbl;
-	end sin_tbl;
-
-	-------------------------------------------------------------
-	function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is
-	variable tbl : real_array_t (0 to nsamples-1);
-	variable phi : real := phi_in;
-	variable dphi : real := 2.0*pi*omega;
-
-	begin
-		for i in 0 to nsamples-1 loop
-			tbl(i) := cos(phi);
-			phi := phi + dphi;
-		end loop;
-
-		return tbl;
-	end cos_tbl;
-
--------------------------------------------------------------------------------
-end; -- package nco_pkg;
diff --git a/lib/radio/nco/src/tb_mix_cordic.vhd b/lib/radio/nco/src/tb_mix_cordic.vhd
deleted file mode 100644
index 335c619..0000000
--- a/lib/radio/nco/src/tb_mix_cordic.vhd
+++ /dev/null
@@ -1,331 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.cordic_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_mix IS
-	Generic 
-	(
-		nbits_wave_in	: integer := 16;
-		nbits_wave_out	: integer := 18;		-- Gain of 2.6 (mix + rfgen)
-		nbits_phase		: integer := 20;
-		nbits_freq		: integer := 20
-	);
-END tb_mix;
-
-ARCHITECTURE behavior OF tb_mix IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT mix
-	GENERIC
-	(
-		nbits_din		: integer;
-		nbits_din_frac	: integer;
-		nbits_dout		: integer;
-		nbits_dout_frac	: integer;
-		nbits_phase		: integer;
-		nbits_freq		: integer
-	);
-	PORT
-	(
-		rst				: in std_logic;
-		clk				: in std_logic;
-		nco_rst			: in std_logic;
-		nco_en			: in std_logic;
-		freq_in			: in unsigned(nbits_freq-1 downto 0);
-		phase_in		: in unsigned(nbits_phase-1 downto 0);
-		din_i			: in  sfixed;
-		din_q			: in  sfixed;
-		dout_i			: out sfixed;
-		dout_q			: out sfixed;
-		din_vld			: in std_logic;
-		dout_vld		: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant fa : REAL := 100.0E6;
-	constant frf : REAL := 3.333E5;
-	constant flo : REAL := 3.333E5;
-	constant df : REAL := 10.0E3;
-	constant PERIOD : time := 10 ns;
-	constant num_steps : integer := 1000000;
-
-	constant nbits_wave_in_frac : integer := nbits_wave_in-2;
-	constant nbits_wave_out_frac : integer := nbits_wave_out-2;
-	
-	SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_freq);
-	SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_freq);
-	SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_freq);
-
-	--Inputs
-	SIGNAL clk			: std_logic := '0';
-	SIGNAL srst			: std_logic := '1';
-	SIGNAL mix_nco_rst	: std_logic := '0';
-	SIGNAL mix_nco_en	: std_logic := '0';
-	SIGNAL mix_freq_in	: unsigned(nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL mix_phase_in	: unsigned(nbits_phase-1 downto 0) := (others => '0');
-
-	--Outputs
-	SIGNAL mix_din_i	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL mix_din_q	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL mix_dout_i	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
-	SIGNAL mix_dout_q	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
-	SIGNAL mix_dout_vld	: std_logic;
-	SIGNAL mix_din_vld	: std_logic := '0';
-	
-	SIGNAL rfgen_nco_rst	: std_logic := '0';
-	SIGNAL rfgen_nco_en		: std_logic := '0';
-	SIGNAL rfgen_freq_in	: unsigned(nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL rfgen_phase_in	: unsigned(nbits_phase-1 downto 0) := (others => '0');
-
-	--Outputs
-	signal rfgen_din_i		: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
-	signal rfgen_din_q		: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL rfgen_dout_i		: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL rfgen_dout_q		: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL rfgen_dout_vld	: std_logic;
-	SIGNAL fileout_enable   : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: mix 
-	GENERIC MAP
-	(
-		nbits_din		=> nbits_wave_in,
-		nbits_din_frac	=> nbits_wave_in_frac,
-		nbits_dout		=> nbits_wave_out,
-		nbits_dout_frac	=> nbits_wave_out_frac,
-		nbits_phase		=> nbits_phase,
-		nbits_freq		=> nbits_freq
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		nco_rst		=> mix_nco_rst,
-		nco_en		=> mix_nco_en,
-		freq_in		=> mix_freq_in,
-		phase_in	=> mix_phase_in,
-		din_i		=> mix_din_i,
-		din_q		=> mix_din_q,
-		dout_i		=> mix_dout_i,
-		dout_q		=> mix_dout_q,
-		din_vld		=> mix_din_vld,
-		dout_vld	=> mix_dout_vld
-	);
-
-	rfgen1: mix 
-	GENERIC MAP
-	(
-		nbits_din		=> nbits_wave_in,
-		nbits_din_frac	=> nbits_wave_in_frac,
-		nbits_dout		=> nbits_wave_in,
-		nbits_dout_frac	=> nbits_wave_in_frac,
-		nbits_phase		=> nbits_phase,
-		nbits_freq		=> nbits_freq
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		nco_rst		=> rfgen_nco_rst,
-		nco_en		=> rfgen_nco_en,
-		freq_in		=> rfgen_freq_in,
-		phase_in	=> rfgen_phase_in,
-		din_i		=> rfgen_din_i,
-		din_q		=> rfgen_din_q,
-		dout_i		=> rfgen_dout_i,
-		dout_q		=> rfgen_dout_q,
-		din_vld		=> '1',
-		dout_vld	=> rfgen_dout_vld
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	mix_din_i	<= rfgen_dout_i;
-	mix_din_q	<= to_sfixed(0.0, mix_din_q);
-	mix_din_vld	<= rfgen_dout_vld;
-	
-	tb : PROCESS
-	file RESULT_FREQ:   text open write_mode is "freq.txt"; 
-	variable L:         line;
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-
-		fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
-
-		wait for 2*PERIOD;
-		-------------------------------------------
-		-- 1
-		mix_phase_in <= to_unsigned(0,nbits_phase);
-		wait until rising_edge(clk);
-		
-		mix_freq_in <= to_unsigned(1411,nbits_freq);
-		wait until rising_edge(clk);
-
-		wait for 2*PERIOD;
-		mix_nco_en <= '1';
-		
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		mix_freq_in <= to_unsigned(643,nbits_freq);
-		wait until rising_edge(clk);
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(800,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(45072,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(20593,nbits_phase);
-		wait until rising_edge(clk);
-
-		-------------------------------------------
-		mix_freq_in <= to_unsigned(freq_word,nbits_freq);
-		wait until rising_edge(clk);
-	
-		wait for 20*PERIOD;
-		fileout_enable <= '1';
-
-		wait for 200000*PERIOD;
-		fileout_enable <= '0';
-
-		-------------------------------------------
-		-- Sweep
-		freq_word <= 100;
-		for i in 1 to 200 loop
-			wait for 20*PERIOD;
-			freq_word <= freq_word + dfreq_word;
-			
-			mix_freq_in <= to_unsigned(freq_word,nbits_freq);
-			wait until rising_edge(clk);
-	
-		end loop;
-		
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		fileout_enable <= '0';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '1';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		mix_nco_rst <= '1';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		mix_nco_en <= '1';
-		wait until rising_edge(clk);
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		mix_freq_in <= to_unsigned(freq_word,nbits_freq);
-		wait until rising_edge(clk);
-		
-		wait for 20*PERIOD;
-		mix_nco_en <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	
-	rfgen_ctrl : PROCESS
-
-	BEGIN
-			wait for 20*PERIOD;
-			wait until rising_edge(clk) and srst = '0';
-			rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_freq);
-			wait until rising_edge(clk);
-			
-			wait for 20*PERIOD;
-			rfgen_nco_en <= '1';
-	
-			wait for 20*PERIOD;
-
-		wait; 
-	END PROCESS;
-
-	tb_fo : PROCESS(clk)
-	file RESULT_Ii:      text open write_mode is "i_in.txt"; 
-	file RESULT_Qi:      text open write_mode is "q_in.txt"; 
-	file RESULT_Io:      text open write_mode is "i_out.txt"; 
-	file RESULT_Qo:      text open write_mode is "q_out.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' then
-			if rfgen_dout_vld = '1' then
-				fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
-				fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
-			end if;
-			if mix_dout_vld = '1' then
-				fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(mix_dout_i)));
-				fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(mix_dout_q)));
-			end if;
-		end if;
-
-	END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/tb_nco_cordic.vhd b/lib/radio/nco/src/tb_nco_cordic.vhd
deleted file mode 100644
index 0bcfd93..0000000
--- a/lib/radio/nco/src/tb_nco_cordic.vhd
+++ /dev/null
@@ -1,265 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_nco IS
-	Generic 
-	(
-		nbits_wave_in	: integer := 16;
-		nbits_wave_out	: integer := 16;
-		nbits_phase		: integer := 20;
-		nbits_freq		: integer := 20
-	);
-END tb_nco;
-
-ARCHITECTURE behavior OF tb_nco IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT mix
-	GENERIC
-	(
-		nbits_din		: integer;
-		nbits_din_frac	: integer;
-		nbits_dout		: integer;
-		nbits_dout_frac	: integer;
-		nbits_phase		: integer;
-		nbits_freq		: integer
-	);
-	PORT
-	(
-		rst				: in std_logic;
-		clk				: in std_logic;
-		nco_rst			: in std_logic;
-		nco_en			: in std_logic;
-		freq_in			: in unsigned(nbits_freq-1 downto 0);
-		phase_in		: in unsigned(nbits_phase-1 downto 0);
-		din_i			: in  sfixed;
-		din_q			: in  sfixed;
-		dout_i			: out sfixed;
-		dout_q			: out sfixed;
-		din_vld			: in std_logic;
-		dout_vld		: out std_logic
-	);
-	END COMPONENT;
-
-	--Constants
-	constant fa : REAL := 100.0E6;
-	constant f : REAL := 5.0*fa/24.0;
-	constant df : REAL := 10.0E3;
-	constant PERIOD : time := 10 ns;
-
-	constant nbits_wave_in_frac : integer := nbits_wave_in-2;
-	constant nbits_wave_out_frac : integer := nbits_wave_out-2;
-	
-	SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
-	SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL mix_nco_rst	: std_logic := '0';
-	SIGNAL mix_nco_en	: std_logic := '0';
-	SIGNAL mix_freq_in	: unsigned(nbits_freq-1 downto 0) := (others => '0');
-	SIGNAL mix_phase_in	: unsigned(nbits_phase-1 downto 0) := (others => '0');
-
-	--Outputs
-	SIGNAL mix_din_i	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL mix_din_q	: sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
-	SIGNAL mix_dout_i	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
-	SIGNAL mix_dout_q	: sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
-	SIGNAL mix_dout_vld	: std_logic;
-	SIGNAL mix_din_vld	: std_logic := '1';
-
-	SIGNAL fileout_enable   : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: mix 
-	GENERIC MAP
-	(
-		nbits_din		=> nbits_wave_in,
-		nbits_din_frac	=> nbits_wave_in_frac,
-		nbits_dout		=> nbits_wave_out,
-		nbits_dout_frac	=> nbits_wave_out_frac,
-		nbits_phase		=> nbits_phase,
-		nbits_freq		=> nbits_freq
-	)
-	PORT MAP
-	(
-		rst			=> srst,
-		clk			=> clk,
-		nco_rst		=> mix_nco_rst,
-		nco_en		=> mix_nco_en,
-		freq_in		=> mix_freq_in,
-		phase_in	=> mix_phase_in,
-		din_i		=> mix_din_i,
-		din_q		=> mix_din_q,
-		dout_i		=> mix_dout_i,
-		dout_q		=> mix_dout_q,
-		din_vld		=> mix_din_vld,
-		dout_vld	=> mix_dout_vld
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	file RESULT_FREQ:   text open write_mode is "freq.txt"; 
-	variable L:         line;
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-
-		fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
-
-		wait for 2*PERIOD;
-		-------------------------------------------
-		-- 1
-		mix_phase_in <= to_unsigned(0,nbits_phase);
-		wait until rising_edge(clk);
-		
-		mix_freq_in <= to_unsigned(1411,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 2*PERIOD;
-		mix_nco_en <= '1';
-		
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		mix_freq_in <= to_unsigned(643,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(800,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(45072,nbits_phase);
-		wait until rising_edge(clk);
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		mix_phase_in <= to_unsigned(20593,nbits_phase);
-		wait until rising_edge(clk);
-
-		-------------------------------------------
-		mix_freq_in <= to_unsigned(freq_word,nbits_phase);
-		wait until rising_edge(clk);
-	
-		wait for 20*PERIOD;
-		fileout_enable <= '1';
-
-		wait for 20000*PERIOD;
-		fileout_enable <= '0';
-
-		-------------------------------------------
-		-- Sweep
-		freq_word <= 100;
-		for i in 1 to 200 loop
-			wait for 20*PERIOD;
-			freq_word <= freq_word + dfreq_word;
-			
-			mix_freq_in <= to_unsigned(freq_word,nbits_phase);
-			wait until rising_edge(clk);
-	
-		end loop;
-		
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		fileout_enable <= '0';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '1';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		mix_nco_rst <= '1';
-		wait until rising_edge(clk);
-		mix_nco_rst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		mix_nco_en <= '1';
-		wait until rising_edge(clk);
-		mix_nco_en <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		mix_freq_in <= to_unsigned(freq_word,nbits_phase);
-		wait until rising_edge(clk);
-		
-		wait for 20*PERIOD;
-		mix_nco_en <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		wait for 20*PERIOD;
-		mix_nco_en <= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk)
-	file RESULT_I:      text open write_mode is "i_ud.txt"; 
-	file RESULT_Q:      text open write_mode is "q_ud.txt"; 
-	file RESULT_ID:      text open write_mode is "i_d.txt"; 
-	file RESULT_QD:      text open write_mode is "q_d.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' and mix_dout_vld = '1' then
-			fprint(RESULT_I, L,"%s\n", REAL'image(to_real(mix_dout_i)));
-			fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(mix_dout_q)));
-			fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(mix_dout_i)));
-			fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(mix_dout_q)));
-		end if;
-
-	END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/tb_nco_lut.vhd b/lib/radio/nco/src/tb_nco_lut.vhd
deleted file mode 100644
index 53a480d..0000000
--- a/lib/radio/nco/src/tb_nco_lut.vhd
+++ /dev/null
@@ -1,303 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   17:16:42 13.05.2007
--- Design Name:   tb_nco
--- Module Name:   tb_nco.vhd
--- Project Name:  nco
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-use work.PCK_FIO.all;
-
-ENTITY tb_nco IS
-	Generic (
-		nbits_wave		: integer := 18;
-		nbits_phase		: integer := 16; 
-		nbits_lut_depth	: integer := 12; 
-		nbits_dither	: integer := 4; 
-		nbits_lfsr		: integer := 12; 
-		q_phase			: phase_relation_t := phase_270deg;
-		has_pipe_reg	: boolean := true;
-		has_out_reg		: boolean := true
-	        );
-END tb_nco;
-
-ARCHITECTURE behavior OF tb_nco IS 
-
-	-- Component Declaration for the Unit Under Test (UUT)
-	COMPONENT nco
-	GENERIC (
-		nbits_wave		: integer;
-		nbits_phase		: integer;
-		nbits_lut_depth	: integer;
-		nbits_dither	: integer;
-		nbits_lfsr		: integer;
-		q_phase			: phase_relation_t;
-		has_pipe_reg	: boolean;
-		has_out_reg		: boolean
-		);
-	PORT(
-		srst		: in std_logic;
-		clk			: in std_logic;
---		ce			: in std_logic;
-		pacc_clr	: in std_logic;
-		pacc_inc	: in std_logic;
-		freq_in		: in unsigned(nbits_phase-1 downto 0);
-		freq_load	: in std_logic;
-		phase_in	: in unsigned(nbits_phase-1 downto 0);
-		phase_load	: in std_logic;
-		phase_out	: out unsigned(nbits_phase-1 downto 0);
-		wave_out_i	: out sfixed;
-		wave_out_q	: out sfixed;
-		out_valid	: out std_logic;
-		debug_out	: out debug_out_t
-	);
-	END COMPONENT;
-
-	--Constants
-	constant fa : REAL := 100.0E6;
-	constant f : REAL := 5.0*fa/24.0;
-	constant df : REAL := 10.0E3;
-	constant PERIOD : time := 10 ns;
-	constant nbits_wave_frac : integer := nbits_wave;
-	
-	SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
-	SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
-
-	--Inputs
-	SIGNAL clk         : std_logic := '0';
---	SIGNAL ce          : std_logic := '0';
-	SIGNAL srst        : std_logic := '1';
-	SIGNAL pacc_clr   : std_logic := '0';
-	SIGNAL pacc_inc   : std_logic := '0';
-	SIGNAL phase_load  : std_logic := '0';
-	SIGNAL freq_load   : std_logic := '0';
-	SIGNAL freq_in     : unsigned(nbits_phase-1 downto 0);
-	SIGNAL phase_in    : unsigned(nbits_phase-1 downto 0);
-
-	--Outputs
-	SIGNAL wave_out_i  : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	SIGNAL wave_out_q  : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	SIGNAL out_valid   : std_logic;
-	SIGNAL phase_out   : unsigned(nbits_phase-1 downto 0);
-	SIGNAL debug_out   : debug_out_t;
-	
-	SIGNAL fileout_enable   : std_logic := '0';
-
-BEGIN
-
-	-- Instantiate the Unit Under Test (UUT)
-	uut: nco 
-	GENERIC MAP (
-		nbits_wave		=> nbits_wave,
-		nbits_phase		=> nbits_phase,
-		nbits_lut_depth	=> nbits_lut_depth,
-		nbits_dither	=> nbits_dither,
-		nbits_lfsr		=> nbits_lfsr,
-		q_phase			=> q_phase,
-		has_pipe_reg	=> has_pipe_reg,
-		has_out_reg		=> has_out_reg
-		)
-	PORT MAP(
-		srst		=> srst,
-		clk			=> clk,
---		ce			=> ce,
-		pacc_clr	=> pacc_clr,
-		pacc_inc	=> pacc_inc,
-		freq_in		=> freq_in,
-		freq_load	=> freq_load,
-		phase_in	=> phase_in,
-		phase_load	=> phase_load,
-		phase_out	=> phase_out,
-		wave_out_i	=> wave_out_i,
-		wave_out_q	=> wave_out_q,
-		out_valid	=> out_valid,
-		debug_out	=> debug_out
-	);
-
- 	tb_clk : PROCESS
-	BEGIN
-		clk <= not clk;
-		wait for PERIOD/2;
-	END PROCESS;
-
-	tb : PROCESS
-	file RESULT_FREQ:   text open write_mode is "freq.txt"; 
-	variable L:         line;
-
-	BEGIN
-
-		-- Wait 100 ns for global reset to finish
-		wait for 4*PERIOD;
-		srst <= '0';
-
-		fprint(RESULT_FREQ, L,"%s\n", REAL'image(f));
-
-		wait for 2*PERIOD;
---		ce <= '1';
-		-------------------------------------------
-		-- 1
-		phase_in <= to_unsigned(0,nbits_phase);
-		wait until rising_edge(clk);
-		phase_load <= '1';
-		wait until rising_edge(clk);
-		phase_load <= '0';
-		
-		freq_in <= to_unsigned(1411,nbits_phase);
-		wait until rising_edge(clk);
-		freq_load <= '1';
-		wait until rising_edge(clk);
-		freq_load <= '0';
-
-		wait for 2*PERIOD;
-		pacc_inc <= '1';
-		
-		wait for 2*PERIOD;
-		wait until rising_edge(clk);
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		freq_in <= to_unsigned(643,nbits_phase);
-		wait until rising_edge(clk);
-		freq_load <= '1';
-		wait until rising_edge(clk);
-		freq_load <= '0';
-
-		wait for 40*PERIOD;
-		-------------------------------------------
-		phase_in <= to_unsigned(800,nbits_phase);
-		wait until rising_edge(clk);
-		phase_load <= '1';
-		wait until rising_edge(clk);
-		phase_load <= '0';
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		phase_in <= to_unsigned(45072,nbits_phase);
-		wait until rising_edge(clk);
-		phase_load <= '1';
-		wait until rising_edge(clk);
-		phase_load <= '0';
-
-		wait for 20*PERIOD;
-		-------------------------------------------
-		phase_in <= to_unsigned(20593,nbits_phase);
-		wait until rising_edge(clk);
-		phase_load <= '1';
-		wait until rising_edge(clk);
-		phase_load <= '0';
-
-		-------------------------------------------
-		freq_in <= to_unsigned(freq_word,nbits_phase);
-		wait until rising_edge(clk);
-		freq_load <= '1';
-		wait until rising_edge(clk);
-		freq_load <= '0';
-	
-		wait for 20*PERIOD;
-		fileout_enable <= '1';
-
-		wait for 20000*PERIOD;
-		fileout_enable <= '0';
-
-		-------------------------------------------
-		-- Sweep
-		freq_word <= 100;
-		for i in 1 to 200 loop
-			wait for 20*PERIOD;
-			freq_word <= freq_word + dfreq_word;
-			
-			freq_in <= to_unsigned(freq_word,nbits_phase);
-			wait until rising_edge(clk);
-			freq_load <= '1';
-			wait until rising_edge(clk);
-			freq_load <= '0';
-	
-		end loop;
-		
-		pacc_inc <= '0';
-		wait for 20*PERIOD;
-		fileout_enable <= '0';
-		wait until rising_edge(clk);
-		pacc_clr <= '1';
-		wait until rising_edge(clk);
-		pacc_clr <= '0';
-		wait for 20*PERIOD;
-		pacc_inc <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		pacc_clr <= '1';
-		wait until rising_edge(clk);
-		pacc_clr <= '0';
-		wait for 20*PERIOD;
-		pacc_inc <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		pacc_inc <= '1';
-		wait until rising_edge(clk);
-		pacc_inc <= '0';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		freq_in <= to_unsigned(freq_word,nbits_phase);
-		wait until rising_edge(clk);
-		freq_load <= '1';
-		wait until rising_edge(clk);
-		freq_load <= '0';
-		
-		wait for 20*PERIOD;
-		pacc_inc <= '1';
-		wait for 20*PERIOD;
-		wait until rising_edge(clk);
-		srst <= '1';
-		wait until rising_edge(clk);
-		srst <= '0';
-		wait for 20*PERIOD;
-		pacc_inc <= '0';
-
-		wait for 20*PERIOD;
-
-		assert false report "Test finished" severity error;
-		wait; 
-	END PROCESS;
-	
-	tb_fo : PROCESS(clk, fileout_enable, out_valid)
-	file RESULT_I:      text open write_mode is "i_ud.txt"; 
-	file RESULT_Q:      text open write_mode is "q_ud.txt"; 
-	file RESULT_ID:      text open write_mode is "i_d.txt"; 
-	file RESULT_QD:      text open write_mode is "q_d.txt"; 
-	file RESULT_LFSR:   text open write_mode is "lfsr.txt"; 
-	variable L:         line;
-
-	BEGIN
-		if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
-			fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud));
-			fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud));
-			fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d));
-			fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d));
-			fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr)));
-		end if;
-
-	END PROCESS;
-
-
-END;
diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd
deleted file mode 100644
index 6f8eaed..0000000
--- a/lib/radio/nco/src/wavelut.vhd
+++ /dev/null
@@ -1,245 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity wavelut is
-Generic
-(
-	nbits_wave		: integer := 12;
-	nbits_wave_frac	: integer := 12;
-	nbits_lut_depth	: integer := 12; 
-	q_phase			: phase_relation_t := phase_90deg;
-	has_out_reg		: boolean := false
-);
-Port
-(
-	rst			: in std_logic;
-	clk			: in std_logic;
-	addr_valid	: in std_logic;
-	addr		: in unsigned(nbits_lut_depth-1 downto 0);
-	wave_i_out	: out sfixed;
-	wave_q_out	: out sfixed;
-	valid_out	: out std_logic
-);
-end wavelut;
-
-architecture Behavioral of wavelut is
-
-	COMPONENT waverom_dual
-	Generic
-	(
-		nbits_wave		: integer;
-		nbits_wave_frac	: integer;
-		nbits_rom_depth	: integer
-	);
-	Port
-	(
-		clk			: in std_logic;
-		addr_i		: in unsigned(nbits_rom_depth-1 downto 0);
-		addr_q		: in unsigned(nbits_rom_depth-1 downto 0);
-		wave_i_out	: out sfixed;
-		wave_q_out	: out sfixed
-	);
-	END COMPONENT;
-
--------------------------------------------------------------------------------
-constant nbits_rom_depth : integer := nbits_lut_depth-2;
-
--------------------------------------------------------------------------------
-signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-signal inv_i : std_logic;
-signal inv_q : std_logic;
-signal addr_i : unsigned(nbits_rom_depth-1 downto 0);
-signal addr_q : unsigned(nbits_rom_depth-1 downto 0);
-signal zero_i : std_logic;
-signal zero_q : std_logic;
-
--------------------------------------------------------------------------------
-begin
-
-	inst_waverom_dual: waverom_dual
-	GENERIC MAP
-	(
-		nbits_wave		=> nbits_wave,
-		nbits_wave_frac	=> nbits_wave_frac,
-		nbits_rom_depth	=> nbits_rom_depth
-	)
-	PORT MAP
-	(
-		clk			=> clk,
-		addr_i		=> addr_i,
-		addr_q		=> addr_q,
-		wave_i_out	=> wave_i,
-		wave_q_out	=> wave_q
-	);
-	
-------------------------------------------------------------
-proc_valid: process(clk)
-	variable v : unsigned(0 to 1);
-	begin
-		if rising_edge(clk) then
-			if rst = '1' then
-				v := (others => '0');
-				valid_out <= '0';
-			else
-				valid_out <= v(1);
-				v(1) := v(0);
-				v(0) := addr_valid;
-			end if;		
-		end if;	
-	end process;
-
-------------------------------------------------------------
-proc_tbl_addr_i: process(clk, addr)
-	variable index : unsigned(addr'left downto addr'right);
-	variable n2 : integer;
-	constant N_2 : integer := 2**(nbits_lut_depth-1);
-	constant N_4 : integer := 2**(nbits_lut_depth-2);
-	begin
-		n2 := to_integer(addr(addr'left-1 downto addr'right));
-		if n2 > N_4 then
-			index := to_unsigned(N_2 - n2, index'length);
-		else
-			index := to_unsigned(n2, index'length);
-		end if;
-
-		if rising_edge(clk) then
-			if rst = '1' then
-				addr_i <= (others => '0');
-				zero_i <= '0';
-				inv_i <= '0';
-			elsif addr_valid = '1' then
-				addr_i <= index(addr'left-2 downto addr'right);
-				zero_i <= index(addr'left-1);
-				inv_i <= addr(addr'left) xor addr(addr'left-1);
-			end if;	
-		end if;	
-		
-	end process;
-
--------------------------------------------------------------------------------
-proc_tbl_addr_q: process(clk, addr)
-	variable index : unsigned(addr'left downto addr'right);
-	variable n2 : integer;
-	constant N_4 : integer := 2**(nbits_lut_depth-2);
-	
-	begin
-		n2 := to_integer(addr(addr'left-1 downto addr'right));
-		if n2 > N_4 then
-			index := to_unsigned(n2 - N_4, index'length);
-		else
-			index := to_unsigned(N_4 - n2, index'length);
-		end if;
-
-		if rising_edge(clk) then
-			if rst = '1' then
-				addr_q <= (others => '0');
-				zero_q <= '0';
-				inv_q <= '0';
-			elsif addr_valid = '1' then
-				addr_q <= index(addr'left-2 downto addr'right);
-				zero_q <= index(addr'left-1);
-				if q_phase = phase_90deg then
-					inv_q <= addr(addr'left);
-				elsif q_phase = phase_270deg then	
-					inv_q <= not addr(addr'left);
-				end if;	
-			end if;	
-		end if;	
-		
-	end process;
-
-------------------------------------------------------------
-proc_out_i: process(clk, wave_i, inv_i, zero_i)
-	variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	variable z, inv : std_logic;
-	begin
-
-		w := to_sfixed(0.0, w);
-		if z = '0' then
-			w := wave_i;
-			if inv = '1' then
-				w := resize(-wave_i, w, fixed_wrap, fixed_truncate);
-			end if;
-		end if;
-		
-		if has_out_reg = true then
-			if rising_edge(clk) then
-				wave_i_out <= w;
-			end if;	
-		else	
-			wave_i_out <= w;
-		end if;	
-
-		if rising_edge(clk) then
-			z := zero_i;
-			inv := inv_i;
-		end if;	
-
-	end process;
-
-------------------------------------------------------------
-proc_out_q: process(clk, wave_q, inv_q, zero_q)
-	variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-	variable z, inv : std_logic;
-	begin
-	
-		w := to_sfixed(0.0, w);
-		if z = '0' then
-			w := wave_q;
-			if inv = '1' then
-				w := resize(-wave_q, w, fixed_wrap, fixed_truncate);
-			end if;
-		end if;
-		
-		if has_out_reg = true then
-			if rising_edge(clk) then
-				wave_q_out <= w;
-			end if;	
-		else	
-			wave_q_out <= w;
-		end if;	
-
-		if rising_edge(clk) then
-			z := zero_q;
-			inv := inv_q;
-		end if;	
-
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd
deleted file mode 100644
index b39e2a7..0000000
--- a/lib/radio/nco/src/waverom_dual.vhd
+++ /dev/null
@@ -1,92 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:    12:16:14 10/02/05
--- Design Name:    
--- Module Name:    cordic_stage - Behavioral
--- Project Name:   
--- Target Device:  
--- Tool versions:  
--- Description:
---
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.nco_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity waverom_dual is
-Generic
-(
-	nbits_wave		: integer := 12;
-	nbits_wave_frac	: integer := 12;
-	nbits_rom_depth	: integer := 12
-);
-Port
-(
-	clk			: in std_logic;
-	addr_i		: in unsigned(nbits_rom_depth-1 downto 0);
-	addr_q		: in unsigned(nbits_rom_depth-1 downto 0);
-	wave_i_out	: out sfixed;
-	wave_q_out	: out sfixed
-);
-end waverom_dual;
-
-architecture Behavioral of waverom_dual is
-
--------------------------------------------------------------------------------
-constant rom_depth : integer := 2**nbits_rom_depth;
-type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
-
-constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0');
-
--------------------------------------------------------------------------------
-function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is
-variable res : wave_mem_t;
-begin
-	for i in 0 to len-1 loop
-		res(i) := to_sfixed(wave_real(i), proto, fixed_saturate, fixed_round);
-	end loop;
-
-	return res;
-end to_wave_mem;	
-
--------------------------------------------------------------------------------
--- Create ROM
-constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0);
-constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto);
-
--------------------------------------------------------------------------------
-begin
-
--------------------------------------------------------------------------------
-proc_wave: process(clk)
-	begin
-		if rising_edge(clk) then
-			wave_i_out <= wave_tbl(to_integer(addr_i));
-			wave_q_out <= wave_tbl(to_integer(addr_q));
-		end if;	
-	end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/rams/dpram_1w1r2c_ra_sim.vhd b/lib/rams/dpram_1w1r2c_ra_sim.vhd
deleted file mode 100644
index 7b44736..0000000
--- a/lib/rams/dpram_1w1r2c_ra_sim.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c_ra is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c_ra;
-
-architecture Behavioral of dpram_1w1r2c_ra is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	
-begin
-
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_1w1r2c_ra_xil.vhd b/lib/rams/dpram_1w1r2c_ra_xil.vhd
deleted file mode 100644
index 8c0b54b..0000000
--- a/lib/rams/dpram_1w1r2c_ra_xil.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c_ra is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c_ra;
-
-architecture Behavioral of dpram_1w1r2c_ra is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	
-begin
-
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_1w1r2c_ro_sim.vhd b/lib/rams/dpram_1w1r2c_ro_sim.vhd
deleted file mode 100644
index d549f16..0000000
--- a/lib/rams/dpram_1w1r2c_ro_sim.vhd
+++ /dev/null
@@ -1,80 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c_ro is
-	Generic (
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port (
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c_ro;
-
-architecture Behavioral of dpram_1w1r2c_ro is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) <= din_a;
-		end if;
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_1w1r2c_ro_xil.vhd b/lib/rams/dpram_1w1r2c_ro_xil.vhd
deleted file mode 100644
index 32e4b42..0000000
--- a/lib/rams/dpram_1w1r2c_ro_xil.vhd
+++ /dev/null
@@ -1,81 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered output
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_1w1r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-entity dpram_1w1r2c_ro is
-	Generic
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_1w1r2c_ro;
-
-architecture Behavioral of dpram_1w1r2c_ro is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-process (clk_a)
-	begin
-	if clk_a'event and clk_a = '1' then
-		if en_a = '1' then
-			if we_a = '1' then
-				RAM(to_integer(addr_a)) <= din_a;
-			end if;
-		end if;
-	end if;
-end process;
-
-process (clk_b)
-	begin
-	if clk_b'event and clk_b = '1' then
-		if en_b = '1' then
-			dout_b <= RAM(to_integer(addr_b));
-		end if;
-	end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_2w2r2c_ra_sim.vhd b/lib/rams/dpram_2w2r2c_ra_sim.vhd
deleted file mode 100644
index 1d860c7..0000000
--- a/lib/rams/dpram_2w2r2c_ra_sim.vhd
+++ /dev/null
@@ -1,95 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c_ra is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c_ra;
-
-architecture Behavioral of dpram_2w2r2c_ra is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a, clk_b)
-begin
-	if clk_a'event and clk_a = '1' and en_a = '1' and we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
-	elsif clk_b'event and clk_b = '1' and en_b = '1' and we_b = '1' then
-		RAM(to_integer(addr_b)) <= din_b;
-	end if;
-end process;
-
-process (clk_a)
-begin
-	if clk_a'event and clk_a = '1' then
-		if en_a = '1' then
-			addr_a_r	<= addr_a;
-		end if;
-	end if;
-end process;
-
-process (clk_b)
-begin
-	if clk_b'event and clk_b = '1' then
-		if en_b = '1' then
-			addr_b_r	<= addr_b;
-		end if;
-	end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_2w2r2c_ra_xil.vhd b/lib/rams/dpram_2w2r2c_ra_xil.vhd
deleted file mode 100644
index 8847b0b..0000000
--- a/lib/rams/dpram_2w2r2c_ra_xil.vhd
+++ /dev/null
@@ -1,93 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered address
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ra_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c_ra is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c_ra;
-
-architecture Behavioral of dpram_2w2r2c_ra is
-
-	constant depth : integer := 2**addr_width;
-	signal addr_a_r : unsigned (addr_width-1 downto 0);
-	signal addr_b_r : unsigned (addr_width-1 downto 0);
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-	dout_a <= RAM(to_integer(addr_a_r));
-	dout_b <= RAM(to_integer(addr_b_r));
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		addr_a_r	<= addr_a;
-	end if;
-end if;
-end process;
-
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		addr_b_r	<= addr_b;
-	end if;
-end if;
-end process;
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_2w2r2c_ro_sim.vhd b/lib/rams/dpram_2w2r2c_ro_sim.vhd
deleted file mode 100644
index 79203ba..0000000
--- a/lib/rams/dpram_2w2r2c_ro_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_sim.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c_ro is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c_ro;
-
-architecture Behavioral of dpram_2w2r2c_ro is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/rams/dpram_2w2r2c_ro_xil.vhd b/lib/rams/dpram_2w2r2c_ro_xil.vhd
deleted file mode 100644
index 664a144..0000000
--- a/lib/rams/dpram_2w2r2c_ro_xil.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: Dual-Port RAM with 1 clock latency for simulation
--- This file: Dual-Port RAM 2 write, 2 read, 2 clocks, registered output
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/rams/dpram_2w2r2c_ro_xil.vhd,v 1.1 2013-02-09 09:27:21 jens Exp $
------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.ALL;
-
-entity dpram_2w2r2c_ro is
-	Generic 
-	(
-		addr_width : integer := 3;
-		data_width : integer := 8
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-end dpram_2w2r2c_ro;
-
-architecture Behavioral of dpram_2w2r2c_ro is
-
-	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	shared variable RAM : RAMtype;
-	
-begin
-
-process (clk_a)
-begin
-if clk_a'event and clk_a = '1' then
-	if en_a = '1' then
-		if we_a = '1' then
-			RAM(to_integer(addr_a)) := din_a;
-		end if;
-		dout_a <= RAM(to_integer(addr_a));
-	end if;
-end if;
-end process;
-
-process (clk_b)
-begin
-if clk_b'event and clk_b = '1' then
-	if en_b = '1' then
-		if we_b = '1' then
-			RAM(to_integer(addr_b)) := din_b;
-		end if;
-		dout_b <= RAM(to_integer(addr_b));
-	end if;
-end if;
-end process;
-
-
-end Behavioral;
-
diff --git a/lib/uart/bbfifo_16x8.vhd b/lib/uart/bbfifo_16x8.vhd
deleted file mode 100644
index d6604a6..0000000
--- a/lib/uart/bbfifo_16x8.vhd
+++ /dev/null
@@ -1,281 +0,0 @@
--- 'Bucket Brigade' FIFO  
--- 16 deep
--- 8-bit data
---
--- Version : 1.10 
--- Version Date : 3rd December 2003
--- Reason : '--translate' directives changed to '--synthesis translate' directives
---
--- Version : 1.00
--- Version Date : 14th October 2002
---
--- Start of design entry : 14th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for BBFIFO_16x8
---
-entity bbfifo_16x8 is
-    Port (       data_in : in std_logic_vector(7 downto 0);
-                data_out : out std_logic_vector(7 downto 0);
-                   reset : in std_logic;               
-                   write : in std_logic; 
-                    read : in std_logic;
-                    full : out std_logic;
-               half_full : out std_logic;
-            data_present : out std_logic;
-                     clk : in std_logic);
-    end bbfifo_16x8;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for BBFIFO_16x8
---	 
-architecture low_level_definition of bbfifo_16x8 is
---
-------------------------------------------------------------------------------------
---
-------------------------------------------------------------------------------------
---
--- Signals used in BBFIFO_16x8
---
-------------------------------------------------------------------------------------
---
-signal pointer             : std_logic_vector(3 downto 0);
-signal next_count          : std_logic_vector(3 downto 0);
-signal half_count          : std_logic_vector(3 downto 0);
-signal count_carry         : std_logic_vector(2 downto 0);
-
-signal pointer_zero        : std_logic;
-signal pointer_full        : std_logic;
-signal decode_data_present : std_logic;
-signal data_present_int    : std_logic;
-signal valid_write         : std_logic;
---
---
-------------------------------------------------------------------------------------
---
--- Attributes to define LUT contents during implementation 
--- The information is repeated in the generic map for functional simulation--
---
-------------------------------------------------------------------------------------
---
-attribute INIT : string; 
-attribute INIT of zero_lut      : label is "0001";
-attribute INIT of full_lut      : label is "8000";
-attribute INIT of dp_lut        : label is "BFA0";
-attribute INIT of valid_lut     : label is "C4";
---
-------------------------------------------------------------------------------------
---
--- Start of BBFIFO_16x8 circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  -- SRL16E data storage
-
-  data_width_loop: for i in 0 to 7 generate
-  --
-  attribute INIT : string; 
-  attribute INIT of data_srl : label is "0000"; 
-  --
-  begin
-
-     data_srl: SRL16E
-     --synthesis translate_off
-     generic map (INIT => X"0000")
-     --synthesis translate_on
-     port map(   D => data_in(i),
-                CE => valid_write,
-               CLK => clk,
-                A0 => pointer(0),
-                A1 => pointer(1),
-                A2 => pointer(2),
-                A3 => pointer(3),
-                 Q => data_out(i) );
-
-  end generate data_width_loop;
- 
-  -- 4-bit counter to act as data pointer
-  -- Counter is clock enabled by 'data_present'
-  -- Counter will be reset when 'reset' is active
-  -- Counter will increment when 'valid_write' is active
-
-  count_width_loop: for i in 0 to 3 generate
-  --
-  attribute INIT : string; 
-  attribute INIT of count_lut : label is "6606"; 
-  --
-  begin
-
-     register_bit: FDRE
-     port map ( D => next_count(i),
-                Q => pointer(i),
-               CE => data_present_int,
-                R => reset,
-                C => clk);
-
-     count_lut: LUT4
-     --synthesis translate_off
-     generic map (INIT => X"6606")
-     --synthesis translate_on
-     port map( I0 => pointer(i),
-               I1 => read,
-               I2 => pointer_zero,
-               I3 => write,
-                O => half_count(i));
-
-     lsb_count: if i=0 generate
-     begin
-
-       count_muxcy: MUXCY
-       port map( DI => pointer(i),
-                 CI => valid_write,
-                  S => half_count(i),
-                  O => count_carry(i));
-       
-       count_xor: XORCY
-       port map( LI => half_count(i),
-                 CI => valid_write,
-                  O => next_count(i));
-
-     end generate lsb_count;
-
-     mid_count: if i>0 and i<3 generate
-     begin
-
-       count_muxcy: MUXCY
-       port map( DI => pointer(i),
-                 CI => count_carry(i-1),
-                  S => half_count(i),
-                  O => count_carry(i));
-       
-       count_xor: XORCY
-       port map( LI => half_count(i),
-                 CI => count_carry(i-1),
-                  O => next_count(i));
-
-     end generate mid_count;
-
-     upper_count: if i=3 generate
-     begin
-
-       count_xor: XORCY
-       port map( LI => half_count(i),
-                 CI => count_carry(i-1),
-                  O => next_count(i));
-
-     end generate upper_count;
-
-  end generate count_width_loop;
-
-
-  -- Detect when pointer is zero and maximum
-
-  zero_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"0001")
-  --synthesis translate_on
-  port map( I0 => pointer(0),
-            I1 => pointer(1),
-            I2 => pointer(2),
-            I3 => pointer(3),
-             O => pointer_zero );
-
-
-  full_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"8000")
-  --synthesis translate_on
-  port map( I0 => pointer(0),
-            I1 => pointer(1),
-            I2 => pointer(2),
-            I3 => pointer(3),
-             O => pointer_full );
-
-
-  -- Data Present status
-
-  dp_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"BFA0")
-  --synthesis translate_on
-  port map( I0 => write,
-            I1 => read,
-            I2 => pointer_zero,
-            I3 => data_present_int,
-             O => decode_data_present );
-
-  dp_flop: FDR
-  port map ( D => decode_data_present,
-             Q => data_present_int,
-             R => reset,
-             C => clk);
-
-  -- Valid write signal
-
-  valid_lut: LUT3
-  --synthesis translate_off
-    generic map (INIT => X"C4")
-  --synthesis translate_on
-  port map( I0 => pointer_full,
-            I1 => write,
-            I2 => read,
-             O => valid_write );
-
-
-  -- assign internal signals to outputs
-
-  full <= pointer_full;  
-  half_full <= pointer(3);  
-  data_present <= data_present_int;
-
-end low_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE BBFIFO_16x8.VHD
---
-------------------------------------------------------------------------------------
-
-
diff --git a/lib/uart/kcuart_rx.vhd b/lib/uart/kcuart_rx.vhd
deleted file mode 100644
index a7ac1a2..0000000
--- a/lib/uart/kcuart_rx.vhd
+++ /dev/null
@@ -1,352 +0,0 @@
--- Constant (K) Compact UART Receiver
---
--- Version : 1.10 
--- Version Date : 3rd December 2003
--- Reason : '--translate' directives changed to '--synthesis translate' directives
---
--- Version : 1.00
--- Version Date : 16th October 2002
---
--- Start of design entry : 16th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for KCUART_RX
---
-entity kcuart_rx is
-    Port (      serial_in : in std_logic;  
-                 data_out : out std_logic_vector(7 downto 0);
-              data_strobe : out std_logic;
-             en_16_x_baud : in std_logic;
-                      clk : in std_logic);
-    end kcuart_rx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for KCUART_RX
---	 
-architecture low_level_definition of kcuart_rx is
---
-------------------------------------------------------------------------------------
---
-------------------------------------------------------------------------------------
---
--- Signals used in KCUART_RX
---
-------------------------------------------------------------------------------------
---
-signal sync_serial        : std_logic;
-signal stop_bit           : std_logic;
-signal data_int           : std_logic_vector(7 downto 0);
-signal data_delay         : std_logic_vector(7 downto 0);
-signal start_delay        : std_logic;
-signal start_bit          : std_logic;
-signal edge_delay         : std_logic;
-signal start_edge         : std_logic;
-signal decode_valid_char  : std_logic;
-signal valid_char         : std_logic;
-signal decode_purge       : std_logic;
-signal purge              : std_logic;
-signal valid_srl_delay    : std_logic_vector(8 downto 0);
-signal valid_reg_delay    : std_logic_vector(8 downto 0);
-signal decode_data_strobe : std_logic;
---
---
-------------------------------------------------------------------------------------
---
--- Attributes to define LUT contents during implementation 
--- The information is repeated in the generic map for functional simulation--
---
-------------------------------------------------------------------------------------
---
-attribute INIT : string; 
-attribute INIT of start_srl     : label is "0000";
-attribute INIT of edge_srl      : label is "0000";
-attribute INIT of valid_lut     : label is "0040";
-attribute INIT of purge_lut     : label is "54";
-attribute INIT of strobe_lut    : label is "8";
---
-------------------------------------------------------------------------------------
---
--- Start of KCUART_RX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  -- Synchronise input serial data to system clock
-
-  sync_reg: FD
-  port map ( D => serial_in,
-             Q => sync_serial,
-             C => clk);
-
-  stop_reg: FD
-  port map ( D => sync_serial,
-             Q => stop_bit,
-             C => clk);
-
-
-  -- Data delays to capture data at 16 time baud rate
-  -- Each SRL16E is followed by a flip-flop for best timing
-
-  data_loop: for i in 0 to 7 generate
-  begin
-
-     lsbs: if i<7 generate
-     --
-     attribute INIT : string; 
-     attribute INIT of delay15_srl : label is "0000"; 
-     --
-     begin
-
-       delay15_srl: SRL16E
-       --synthesis translate_off
-       generic map (INIT => X"0000")
-       --synthesis translate_on
-       port map(   D => data_int(i+1),
-                  CE => en_16_x_baud,
-                 CLK => clk,
-                  A0 => '0',
-                  A1 => '1',
-                  A2 => '1',
-                  A3 => '1',
-                   Q => data_delay(i) );
-
-     end generate lsbs;
-
-     msb: if i=7 generate
-     --
-     attribute INIT : string; 
-     attribute INIT of delay15_srl : label is "0000"; 
-     --
-     begin
-
-       delay15_srl: SRL16E
-       --synthesis translate_off
-       generic map (INIT => X"0000")
-       --synthesis translate_on
-       port map(   D => stop_bit,
-                  CE => en_16_x_baud,
-                 CLK => clk,
-                  A0 => '0',
-                  A1 => '1',
-                  A2 => '1',
-                  A3 => '1',
-                   Q => data_delay(i) );
-
-     end generate msb;
-
-     data_reg: FDE
-     port map ( D => data_delay(i),
-                Q => data_int(i),
-               CE => en_16_x_baud,
-                C => clk);
-
-  end generate data_loop;
-
-  -- Assign internal signals to outputs
-
-  data_out <= data_int;
- 
-  -- Data delays to capture start bit at 16 time baud rate
-
-  start_srl: SRL16E
-  --synthesis translate_off
-  generic map (INIT => X"0000")
-  --synthesis translate_on
-  port map(   D => data_int(0),
-             CE => en_16_x_baud,
-            CLK => clk,
-             A0 => '0',
-             A1 => '1',
-             A2 => '1',
-             A3 => '1',
-              Q => start_delay );
-
-  start_reg: FDE
-  port map ( D => start_delay,
-             Q => start_bit,
-            CE => en_16_x_baud,
-             C => clk);
-
-
-  -- Data delays to capture start bit leading edge at 16 time baud rate
-  -- Delay ensures data is captured at mid-bit position
-
-  edge_srl: SRL16E
-  --synthesis translate_off
-  generic map (INIT => X"0000")
-  --synthesis translate_on
-  port map(   D => start_bit,
-             CE => en_16_x_baud,
-            CLK => clk,
-             A0 => '1',
-             A1 => '0',
-             A2 => '1',
-             A3 => '0',
-              Q => edge_delay );
-
-  edge_reg: FDE
-  port map ( D => edge_delay,
-             Q => start_edge,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Detect a valid character 
-
-  valid_lut: LUT4
-  --synthesis translate_off
-  generic map (INIT => X"0040")
-  --synthesis translate_on
-  port map( I0 => purge,
-            I1 => stop_bit,
-            I2 => start_edge,
-            I3 => edge_delay,
-             O => decode_valid_char );  
-
-  valid_reg: FDE
-  port map ( D => decode_valid_char,
-             Q => valid_char,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Purge of data status 
-
-  purge_lut: LUT3
-  --synthesis translate_off
-  generic map (INIT => X"54")
-  --synthesis translate_on
-  port map( I0 => valid_reg_delay(8),
-            I1 => valid_char,
-            I2 => purge,
-             O => decode_purge );  
-
-  purge_reg: FDE
-  port map ( D => decode_purge,
-             Q => purge,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Delay of valid_char pulse of length equivalent to the time taken 
-  -- to purge data shift register of all data which has been used.
-  -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with 
-  -- up to 16 delays and utilising the dedicated flip flop in each stage.
-
-  valid_loop: for i in 0 to 8 generate
-  begin
-
-     lsb: if i=0 generate
-     --
-     attribute INIT : string; 
-     attribute INIT of delay15_srl : label is "0000"; 
-     --
-     begin
-
-       delay15_srl: SRL16E
-       --synthesis translate_off
-       generic map (INIT => X"0000")
-       --synthesis translate_on
-       port map(   D => valid_char,
-                  CE => en_16_x_baud,
-                 CLK => clk,
-                  A0 => '0',
-                  A1 => '1',
-                  A2 => '1',
-                  A3 => '1',
-                   Q => valid_srl_delay(i) );
-
-     end generate lsb;
-
-     msbs: if i>0 generate
-     --
-     attribute INIT : string; 
-     attribute INIT of delay16_srl : label is "0000"; 
-     --
-     begin
-
-       delay16_srl: SRL16E
-       --synthesis translate_off
-       generic map (INIT => X"0000")
-       --synthesis translate_on
-       port map(   D => valid_reg_delay(i-1),
-                  CE => en_16_x_baud,
-                 CLK => clk,
-                  A0 => '1',
-                  A1 => '1',
-                  A2 => '1',
-                  A3 => '1',
-                   Q => valid_srl_delay(i) );
-
-     end generate msbs;
-
-     data_reg: FDE
-     port map ( D => valid_srl_delay(i),
-                Q => valid_reg_delay(i),
-               CE => en_16_x_baud,
-                C => clk);
-
-  end generate valid_loop;
-
-  -- Form data strobe
-
-  strobe_lut: LUT2
-  --synthesis translate_off
-  generic map (INIT => X"8")
-  --synthesis translate_on
-  port map( I0 => valid_char,
-            I1 => en_16_x_baud,
-             O => decode_data_strobe );
-
-  strobe_reg: FD
-  port map ( D => decode_data_strobe,
-             Q => data_strobe,
-             C => clk);
-
-end low_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE KCUART_RX.VHD
---
-------------------------------------------------------------------------------------
-
-
diff --git a/lib/uart/kcuart_tx.vhd b/lib/uart/kcuart_tx.vhd
deleted file mode 100644
index 556ac58..0000000
--- a/lib/uart/kcuart_tx.vhd
+++ /dev/null
@@ -1,394 +0,0 @@
--- Constant (K) Compact UART Transmitter
---
--- Version : 1.10 
--- Version Date : 3rd December 2003
--- Reason : '--translate' directives changed to '--synthesis translate' directives
---
--- Version : 1.00
--- Version Date : 14th October 2002
---
--- Start of design entry : 2nd October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for KCUART_TX
---
-entity kcuart_tx is
-    Port (        data_in : in std_logic_vector(7 downto 0);
-           send_character : in std_logic;
-             en_16_x_baud : in std_logic;
-               serial_out : out std_logic;
-              Tx_complete : out std_logic;
-                      clk : in std_logic);
-    end kcuart_tx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for KCUART_TX
---	 
-architecture low_level_definition of kcuart_tx is
---
-------------------------------------------------------------------------------------
---
-------------------------------------------------------------------------------------
---
--- Signals used in KCUART_TX
---
-------------------------------------------------------------------------------------
---
-signal data_01            : std_logic;
-signal data_23            : std_logic;
-signal data_45            : std_logic;
-signal data_67            : std_logic;
-signal data_0123          : std_logic;
-signal data_4567          : std_logic;
-signal data_01234567      : std_logic;
-signal bit_select         : std_logic_vector(2 downto 0);
-signal next_count         : std_logic_vector(2 downto 0);
-signal mask_count         : std_logic_vector(2 downto 0);
-signal mask_count_carry   : std_logic_vector(2 downto 0);
-signal count_carry        : std_logic_vector(2 downto 0);
-signal ready_to_start     : std_logic;
-signal decode_Tx_start    : std_logic;
-signal Tx_start           : std_logic;
-signal decode_Tx_run      : std_logic;
-signal Tx_run             : std_logic;
-signal decode_hot_state   : std_logic;
-signal hot_state          : std_logic;
-signal hot_delay          : std_logic;
-signal Tx_bit             : std_logic;
-signal decode_Tx_stop     : std_logic;
-signal Tx_stop            : std_logic;
-signal decode_Tx_complete : std_logic;
---
---
-------------------------------------------------------------------------------------
---
--- Attributes to define LUT contents during implementation 
--- The information is repeated in the generic map for functional simulation--
---
-------------------------------------------------------------------------------------
---
-attribute INIT : string; 
-attribute INIT of mux1_lut      : label is "E4FF";
-attribute INIT of mux2_lut      : label is "E4FF";
-attribute INIT of mux3_lut      : label is "E4FF";
-attribute INIT of mux4_lut      : label is "E4FF";
-attribute INIT of ready_lut     : label is "10";
-attribute INIT of start_lut     : label is "0190";
-attribute INIT of run_lut       : label is "1540";
-attribute INIT of hot_state_lut : label is "94";
-attribute INIT of delay14_srl   : label is "0000";
-attribute INIT of stop_lut      : label is "0180";
-attribute INIT of complete_lut  : label is "8";
---
-------------------------------------------------------------------------------------
---
--- Start of KCUART_TX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  -- 8 to 1 multiplexer to convert parallel data to serial
-
-  mux1_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"E4FF")
-  --synthesis translate_on
-  port map( I0 => bit_select(0),
-            I1 => data_in(0),
-            I2 => data_in(1),
-            I3 => Tx_run,
-             O => data_01 );
-
-  mux2_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"E4FF")
-  --synthesis translate_on
-  port map( I0 => bit_select(0),
-            I1 => data_in(2),
-            I2 => data_in(3),
-            I3 => Tx_run,
-             O => data_23 );
-
-  mux3_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"E4FF")
-  --synthesis translate_on
-  port map( I0 => bit_select(0),
-            I1 => data_in(4),
-            I2 => data_in(5),
-            I3 => Tx_run,
-             O => data_45 );
-
-  mux4_lut: LUT4
-  --synthesis translate_off
-    generic map (INIT => X"E4FF")
-  --synthesis translate_on
-  port map( I0 => bit_select(0),
-            I1 => data_in(6),
-            I2 => data_in(7),
-            I3 => Tx_run,
-             O => data_67 );
-
-  mux5_muxf5: MUXF5
-  port map(  I1 => data_23,
-             I0 => data_01,
-              S => bit_select(1),
-              O => data_0123 );
-
-  mux6_muxf5: MUXF5
-  port map(  I1 => data_67,
-             I0 => data_45,
-              S => bit_select(1),
-              O => data_4567 );
-
-  mux7_muxf6: MUXF6
-  port map(  I1 => data_4567,
-             I0 => data_0123,
-              S => bit_select(2),
-              O => data_01234567 );
-
-  -- Register serial output and force start and stop bits
-
-  pipeline_serial: FDRS
-  port map ( D => data_01234567,
-             Q => serial_out,
-             R => Tx_start,
-             S => Tx_stop,
-             C => clk);
-
-  -- 3-bit counter
-  -- Counter is clock enabled by en_16_x_baud
-  -- Counter will be reset when 'Tx_start' is active
-  -- Counter will increment when Tx_bit is active
-  -- Tx_run must be active to count
-  -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
-
-  count_width_loop: for i in 0 to 2 generate
-  --
-  attribute INIT : string; 
-  attribute INIT of count_lut : label is "8"; 
-  --
-  begin
-
-     register_bit: FDRE
-     port map ( D => next_count(i),
-                Q => bit_select(i),
-               CE => en_16_x_baud,
-                R => Tx_start,
-                C => clk);
-
-     count_lut: LUT2
-     --synthesis translate_off
-     generic map (INIT => X"8")
-     --synthesis translate_on
-     port map( I0 => bit_select(i),
-               I1 => Tx_run,
-                O => mask_count(i));
-
-     mask_and: MULT_AND
-     port map( I0 => bit_select(i),
-               I1 => Tx_run,
-               LO => mask_count_carry(i));
-
-     lsb_count: if i=0 generate
-     begin
-
-       count_muxcy: MUXCY
-       port map( DI => mask_count_carry(i),
-                 CI => Tx_bit,
-                  S => mask_count(i),
-                  O => count_carry(i));
-       
-       count_xor: XORCY
-       port map( LI => mask_count(i),
-                 CI => Tx_bit,
-                  O => next_count(i));
-
-     end generate lsb_count;
-
-     upper_count: if i>0 generate
-     begin
-
-       count_muxcy: MUXCY
-       port map( DI => mask_count_carry(i),
-                 CI => count_carry(i-1),
-                  S => mask_count(i),
-                  O => count_carry(i));
-       
-       count_xor: XORCY
-       port map( LI => mask_count(i),
-                 CI => count_carry(i-1),
-                  O => next_count(i));
-
-     end generate upper_count;
-
-  end generate count_width_loop;
- 
-  -- Ready to start decode
-
-  ready_lut: LUT3
-  --synthesis translate_off
-  generic map (INIT => X"10")
-  --synthesis translate_on
-  port map( I0 => Tx_run,
-            I1 => Tx_start,
-            I2 => send_character,
-             O => ready_to_start );
-
-  -- Start bit enable
-
-  start_lut: LUT4
-  --synthesis translate_off
-  generic map (INIT => X"0190")
-  --synthesis translate_on
-  port map( I0 => Tx_bit,
-            I1 => Tx_stop,
-            I2 => ready_to_start,
-            I3 => Tx_start,
-             O => decode_Tx_start );
-
-  Tx_start_reg: FDE
-  port map ( D => decode_Tx_start,
-             Q => Tx_start,
-            CE => en_16_x_baud,
-             C => clk);
-
-
-  -- Run bit enable
-
-  run_lut: LUT4
-  --synthesis translate_off
-  generic map (INIT => X"1540")
-  --synthesis translate_on
-  port map( I0 => count_carry(2),
-            I1 => Tx_bit,
-            I2 => Tx_start,
-            I3 => Tx_run,
-             O => decode_Tx_run );
-
-  Tx_run_reg: FDE
-  port map ( D => decode_Tx_run,
-             Q => Tx_run,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Bit rate enable
-
-  hot_state_lut: LUT3
-  --synthesis translate_off
-  generic map (INIT => X"94")
-  --synthesis translate_on
-  port map( I0 => Tx_stop,
-            I1 => ready_to_start,
-            I2 => Tx_bit,
-             O => decode_hot_state );
-
-  hot_state_reg: FDE
-  port map ( D => decode_hot_state,
-             Q => hot_state,
-            CE => en_16_x_baud,
-             C => clk);
-
-  delay14_srl: SRL16E
-  --synthesis translate_off
-  generic map (INIT => X"0000")
-  --synthesis translate_on
-  port map(   D => hot_state,
-             CE => en_16_x_baud,
-            CLK => clk,
-             A0 => '1',
-             A1 => '0',
-             A2 => '1',
-             A3 => '1',
-              Q => hot_delay );
-
-  Tx_bit_reg: FDE
-  port map ( D => hot_delay,
-             Q => Tx_bit,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Stop bit enable
-
-  stop_lut: LUT4
-  --synthesis translate_off
-  generic map (INIT => X"0180")
-  --synthesis translate_on
-  port map( I0 => Tx_bit,
-            I1 => Tx_run,
-            I2 => count_carry(2),
-            I3 => Tx_stop,
-             O => decode_Tx_stop );
-
-  Tx_stop_reg: FDE
-  port map ( D => decode_Tx_stop,
-             Q => Tx_stop,
-            CE => en_16_x_baud,
-             C => clk);
-
-  -- Tx_complete strobe
-
-  complete_lut: LUT2
-  --synthesis translate_off
-  generic map (INIT => X"8")
-  --synthesis translate_on
-  port map( I0 => count_carry(2),
-            I1 => en_16_x_baud,
-             O => decode_Tx_complete );
-
-  Tx_complete_reg: FD
-  port map ( D => decode_Tx_complete,
-             Q => Tx_complete,
-             C => clk);
-
-
-end low_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE KCUART_TX.VHD
---
-------------------------------------------------------------------------------------
-
-
diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd
deleted file mode 100644
index 69eb70e..0000000
--- a/lib/uart/uart_rx.vhd
+++ /dev/null
@@ -1,146 +0,0 @@
--- UART Receiver with integral 16 byte FIFO buffer
---
--- 8 bit, no parity, 1 stop bit
---
--- Version : 1.00
--- Version Date : 16th October 2002
---
--- Start of design entry : 16th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_RX
---
-entity uart_rx is
-    Port (            serial_in : in std_logic;
-                       data_out : out std_logic_vector(7 downto 0);
-                    read_buffer : in std_logic;
-                   reset_buffer : in std_logic;
-                   en_16_x_baud : in std_logic;
-            buffer_data_present : out std_logic;
-                    buffer_full : out std_logic;
-               buffer_half_full : out std_logic;
-                            clk : in std_logic);
-    end uart_rx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for UART_RX
---	 
-architecture macro_level_definition of uart_rx is
---
-------------------------------------------------------------------------------------
---
--- Components used in UART_RX and defined in subsequent entities.
---	
-------------------------------------------------------------------------------------
---
--- Constant (K) Compact UART Receiver
---
-component kcuart_rx 
-    Port (      serial_in : in std_logic;  
-                 data_out : out std_logic_vector(7 downto 0);
-              data_strobe : out std_logic;
-             en_16_x_baud : in std_logic;
-                      clk : in std_logic);
-    end component;
---
--- 'Bucket Brigade' FIFO 
---
-component bbfifo_16x8 
-    Port (       data_in : in std_logic_vector(7 downto 0);
-                data_out : out std_logic_vector(7 downto 0);
-                   reset : in std_logic;               
-                   write : in std_logic; 
-                    read : in std_logic;
-                    full : out std_logic;
-               half_full : out std_logic;
-            data_present : out std_logic;
-                     clk : in std_logic);
-    end component;
---
-------------------------------------------------------------------------------------
---
--- Signals used in UART_RX
---
-------------------------------------------------------------------------------------
---
-signal uart_data_out      : std_logic_vector(7 downto 0);
-signal fifo_write          : std_logic;
---
-------------------------------------------------------------------------------------
---
--- Start of UART_RX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  -- 8 to 1 multiplexer to convert parallel data to serial
-
-  kcuart: kcuart_rx
-  port map (     serial_in => serial_in,
-                  data_out => uart_data_out,
-               data_strobe => fifo_write,
-              en_16_x_baud => en_16_x_baud,
-                       clk => clk );
-
-
-  buf: bbfifo_16x8 
-  port map (       data_in => uart_data_out,
-                  data_out => data_out,
-                     reset => reset_buffer,              
-                     write => fifo_write,
-                      read => read_buffer,
-                      full => buffer_full,
-                 half_full => buffer_half_full,
-              data_present => buffer_data_present,
-                       clk => clk);
-
-end macro_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_RX.VHD
---
-------------------------------------------------------------------------------------
-
-
diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd
deleted file mode 100644
index ca42d04..0000000
--- a/lib/uart/uart_tx.vhd
+++ /dev/null
@@ -1,153 +0,0 @@
--- UART Transmitter with integral 16 byte FIFO buffer
---
--- 8 bit, no parity, 1 stop bit
---
--- Version : 1.00
--- Version Date : 14th October 2002
---
--- Start of design entry : 14th October 2002
---
--- Ken Chapman
--- Xilinx Ltd
--- Benchmark House
--- 203 Brooklands Road
--- Weybridge
--- Surrey KT13 ORH
--- United Kingdom
---
--- chapman@xilinx.com
---
-------------------------------------------------------------------------------------
---
--- NOTICE:
---
--- Copyright Xilinx, Inc. 2002.   This code may be contain portions patented by other 
--- third parties.  By providing this core as one possible implementation of a standard,
--- Xilinx is making no representation that the provided implementation of this standard 
--- is free from any claims of infringement by any third party.  Xilinx expressly 
--- disclaims any warranty with respect to the adequacy of the implementation, including 
--- but not limited to any warranty or representation that the implementation is free 
--- from claims of any third party.  Futhermore, Xilinx is providing this core as a 
--- courtesy to you and suggests that you contact all third parties to obtain the 
--- necessary rights to use this implementation.
---
-------------------------------------------------------------------------------------
---
--- Library declarations
---
--- The Unisim Library is used to define Xilinx primitives. It is also used during
--- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
---
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library unisim;
-use unisim.vcomponents.all;
---
-------------------------------------------------------------------------------------
---
--- Main Entity for UART_TX
---
-entity uart_tx is
-    Port (            data_in : in std_logic_vector(7 downto 0);
-                 write_buffer : in std_logic;
-                 reset_buffer : in std_logic;
-                 en_16_x_baud : in std_logic;
-                   serial_out : out std_logic;
-                  buffer_full : out std_logic;
-             buffer_half_full : out std_logic;
-             tx_complete	  : out std_logic;
-             tx_empty		  : out std_logic;
-                          clk : in std_logic);
-    end uart_tx;
---
-------------------------------------------------------------------------------------
---
--- Start of Main Architecture for UART_TX
---	 
-architecture macro_level_definition of uart_tx is
---
-------------------------------------------------------------------------------------
---
--- Components used in UART_TX and defined in subsequent entities.
---	
-------------------------------------------------------------------------------------
---
--- Constant (K) Compact UART Transmitter
---
-component kcuart_tx 
-    Port (        data_in : in std_logic_vector(7 downto 0);
-           send_character : in std_logic;
-             en_16_x_baud : in std_logic;
-               serial_out : out std_logic;
-              Tx_complete : out std_logic;
-                      clk : in std_logic);
-    end component;
---
--- 'Bucket Brigade' FIFO 
---
-component bbfifo_16x8 
-    Port (       data_in : in std_logic_vector(7 downto 0);
-                data_out : out std_logic_vector(7 downto 0);
-                   reset : in std_logic;               
-                   write : in std_logic; 
-                    read : in std_logic;
-                    full : out std_logic;
-               half_full : out std_logic;
-            data_present : out std_logic;
-                     clk : in std_logic);
-    end component;
---
-------------------------------------------------------------------------------------
---
--- Signals used in UART_TX
---
-------------------------------------------------------------------------------------
---
-signal fifo_data_out      : std_logic_vector(7 downto 0);
-signal fifo_data_present  : std_logic;
-signal fifo_read          : std_logic;
---
-------------------------------------------------------------------------------------
---
--- Start of UART_TX circuit description
---
-------------------------------------------------------------------------------------
---	
-begin
-
-  tx_complete	<= fifo_read;
-  tx_empty		<= not fifo_data_present;
-  
-  -- 8 to 1 multiplexer to convert parallel data to serial
-
-  kcuart: kcuart_tx
-  port map (        data_in => fifo_data_out,
-             send_character => fifo_data_present,
-               en_16_x_baud => en_16_x_baud,
-                 serial_out => serial_out,
-                Tx_complete => fifo_read,
-                        clk => clk);
-
-
-  buf: bbfifo_16x8 
-  port map (       data_in => data_in,
-                  data_out => fifo_data_out,
-                     reset => reset_buffer,              
-                     write => write_buffer,
-                      read => fifo_read,
-                      full => buffer_full,
-                 half_full => buffer_half_full,
-              data_present => fifo_data_present,
-                       clk => clk);
-
-end macro_level_definition;
-
-------------------------------------------------------------------------------------
---
--- END OF FILE UART_TX.VHD
---
-------------------------------------------------------------------------------------
-
-
diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
deleted file mode 100644
index 2b724e1..0000000
--- a/lib/uart/uart_wb.vhd
+++ /dev/null
@@ -1,219 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-ENTITY uart_wb IS
-	Generic 
-	(
-		simulate_tx	: boolean := false
-	);
-	Port
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		INT_O		: out STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		ser_rx		: in std_logic;
-		ser_tx		: out std_logic
-	);
-END uart_wb;
-
-ARCHITECTURE behavior OF uart_wb IS
-
-	COMPONENT uart_tx
-    Port
-    (
-		data_in				: in std_logic_vector(7 downto 0);
-		write_buffer		: in std_logic;
-		reset_buffer		: in std_logic;
-		en_16_x_baud		: in std_logic;
-		serial_out			: out std_logic;
-		buffer_full			: out std_logic;
-		buffer_half_full	: out std_logic;
-		tx_complete			: out std_logic;
-		tx_empty			: out std_logic;
-		clk					: in std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT uart_rx
-	Port 
-	(
-		serial_in			: in std_logic;
-		data_out			: out std_logic_vector(7 downto 0);
-		read_buffer			: in std_logic;
-		reset_buffer		: in std_logic;
-		en_16_x_baud		: in std_logic;
-		buffer_data_present	: out std_logic;
-		buffer_full			: out std_logic;
-		buffer_half_full	: out std_logic;
-		clk					: in std_logic
-	);
-	END COMPONENT;
-
-	-- Signals for UART connections
-	signal baud_count		: unsigned(15 downto 0);
-	signal en_16_x_baud		: std_logic;
-	signal reg_we_uart_tx	: std_logic;
-	signal tx_full			: std_logic;
-	signal tx_half_full		: std_logic;
-	signal reg_re_uart_rx	: std_logic;
-	signal reg_uart_tx		: unsigned(7 downto 0);
-	signal reg_uart_rx		: std_logic_vector(7 downto 0);
-	signal rx_data_present	: std_logic;
-	signal rx_full			: std_logic;
-	signal rx_half_full		: std_logic;
-	signal uart_status_port	: unsigned(15 downto 0);
-	signal reg_uart_baud	: unsigned(15 downto 0);
-	signal rx_int_en		: std_logic;
-	signal tx_int_en		: std_logic;
-	signal irq_rx			: std_logic;
-	signal irq_tx			: std_logic;
-	signal tx_complete		: std_logic;
-	signal tx_empty			: std_logic;
-	signal status_real		: unsigned(15 downto 0);
-	signal status_sim		: unsigned(15 downto 0);
-	
-begin
-
-	SRDY_O	<= CYC_I;
-	
-------------------------------------------------------------------
-registers_write: 
-	process(CLK_I)
-	file output:	      text open write_mode is "STD_OUTPUT"; 
-	variable L : line; 
-	begin
-		if rising_edge(CLK_I) then
-			reg_we_uart_tx	<= '0';
-			if RST_I = '1' then
-				reg_uart_baud	<= to_unsigned(53, 16);
-				rx_int_en		<= '0';
-				tx_int_en		<= '0';
-			elsif (STB_I and CYC_I and WE_I) = '1' then
-				case ADDR_I(5 downto 2) is
-				
-				when "0000" =>
-					reg_uart_tx		<= DAT_I(7 downto 0);
-					if simulate_tx then
-						if DAT_I(7 downto 0) /= X"0D" then
-							write(L, character'val(to_integer(DAT_I(7 downto 0))));
-						end if;	
-						if DAT_I(7 downto 0) = X"0A" then
-							writeline(output, L);
-						end if;
-					else	
-						reg_we_uart_tx	<= '1';
-					end if;
-					
-				when "0001" =>
-					rx_int_en		<= DAT_I(6);
-					tx_int_en		<= DAT_I(5);
-					
-				when "0010" =>
-					reg_uart_baud	<= DAT_I(15 downto 0);
-
-				when others => null;
-				end case;
-			end if;	
-		end if;	
-	end process;
-
-registers_read: 
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			reg_re_uart_rx	<= '0';
-			ACK_O			<= '0';
-			if (STB_I and CYC_I) = '1' then
-				ACK_O		<= not WE_I;
-				DAT_O		<= (others => '0');
-				case ADDR_I(5 downto 2) is
-
-				when "0000" =>
-					reg_re_uart_rx		<= not WE_I;
-					DAT_O(7 downto 0)	<= unsigned(reg_uart_rx);
-
-				when "0001" =>
-					DAT_O(15 downto 0)	<= uart_status_port;
-
-				when "0010" =>
-					DAT_O(15 downto 0)	<= reg_uart_baud;
-
-				when others => null;
-				end case;
-			end if;
-		end if;	
-	end process;
-
-baud_timer:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			if RST_I = '1' then
-				baud_count <= (others => '0');
-			elsif baud_count = reg_uart_baud then
-				baud_count <= (others => '0');
-				en_16_x_baud <= '1';
-			else
-				baud_count <= baud_count + 1;
-				en_16_x_baud <= '0';
-			end if;
-		end if;
-	end process;
-
-irq_register:
-	process(CLK_I)
-	begin
-		if rising_edge(CLK_I) then
-			irq_tx		<= tx_empty and tx_int_en;
-			irq_rx		<= rx_data_present and rx_int_en;
-		end if;
-	end process;
-
-inst_uart_tx: uart_tx 
-	port map
-	(
-		data_in				=> std_logic_vector(reg_uart_tx), 
-		write_buffer		=> reg_we_uart_tx,
-		reset_buffer		=> RST_I,
-		en_16_x_baud		=> en_16_x_baud,
-		serial_out			=> ser_tx,
-		buffer_full			=> tx_full,
-		buffer_half_full	=> tx_half_full,
-		tx_complete			=> tx_complete,
-		tx_empty			=> tx_empty,
-		clk					=> CLK_I
-	);
-	
-inst_uart_rx: uart_rx
-	port map
-	(
-		serial_in			=> ser_rx,
-		data_out			=> reg_uart_rx,
-		read_buffer			=> reg_re_uart_rx,
-		reset_buffer		=> RST_I,
-		en_16_x_baud		=> en_16_x_baud,
-		buffer_data_present => rx_data_present,
-		buffer_full			=> rx_full,
-		buffer_half_full	=> rx_half_full,
-		clk					=> CLK_I
-	);  
-	
-	status_sim	 		<= "0000000000000000";
-	status_real	 		<= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
-	uart_status_port	<= status_sim when simulate_tx else status_real;
-	
-	INT_O				<= irq_rx or irq_tx;
-
-end behavior;
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par
deleted file mode 100644
index 20658d1..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.par
+++ /dev/null
@@ -1,201 +0,0 @@
-Release 10.1.03 par K.39 (nt)
-Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
-
-JUPITER::  Tue Mar 09 13:07:50 2010
-
-par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd
-mips_sys.pcf 
-
-
-Constraints file: mips_sys.pcf.
-Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
-   "mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
-The STEPPING level for this design is ES.
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version:  "PRODUCTION 1.68 2008-07-25".
-
-
-
-Device Utilization Summary:
-
-   Number of BSCANs                          1 out of 4      25%
-   Number of BUFGs                          12 out of 32     37%
-   Number of DCM_ADVs                        4 out of 8      50%
-   Number of ILOGICs                        99 out of 448    22%
-   Number of External IOBs                 226 out of 448    50%
-      Number of LOCed IOBs                 226 out of 226   100%
-
-   Number of OLOGICs                       182 out of 448    40%
-   Number of RAMB16s                        51 out of 192    26%
-   Number of Slices                       5907 out of 15360  38%
-      Number of SLICEMs                    543 out of 7680    7%
-
-
-
-Overall effort level (-ol):   High 
-Router effort level (-rl):    High 
-
-Starting initial Timing Analysis.  REAL time: 14 secs 
-Finished initial Timing Analysis.  REAL time: 15 secs 
-
-Starting Router
-
-Phase 1: 47928 unrouted;       REAL time: 16 secs 
-
-Phase 2: 40960 unrouted;       REAL time: 17 secs 
-
-Phase 3: 15655 unrouted;       REAL time: 24 secs 
-
-Phase 4: 15655 unrouted; (245197)      REAL time: 24 secs 
-
-Phase 5: 16281 unrouted; (4341)      REAL time: 27 secs 
-
-Phase 6: 16339 unrouted; (710)      REAL time: 28 secs 
-
-Phase 7: 0 unrouted; (9891)      REAL time: 53 secs 
-
-Updating file: mips_sys.ncd with current fully routed design.
-
-Phase 8: 0 unrouted; (9891)      REAL time: 1 mins 4 secs 
-
-Phase 9: 0 unrouted; (5549)      REAL time: 1 mins 14 secs 
-
-Phase 10: 0 unrouted; (5549)      REAL time: 1 mins 21 secs 
-
-Updating file: mips_sys.ncd with current fully routed design.
-
-Phase 11: 0 unrouted; (5549)      REAL time: 2 mins 23 secs 
-
-Phase 12: 0 unrouted; (1304)      REAL time: 2 mins 58 secs 
-
-Phase 13: 0 unrouted; (1304)      REAL time: 3 mins 2 secs 
-
-Phase 14: 0 unrouted; (1304)      REAL time: 3 mins 7 secs 
-
-Total REAL time to Router completion: 3 mins 9 secs 
-Total CPU time to Router completion: 3 mins 3 secs 
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-|             cpu_clk |BUFGCTRL_X0Y12| No   | 1610 |  0.400     |  4.025      |
-+---------------------+--------------+------+------+------------+-------------+
-|               CLK_O | BUFGCTRL_X0Y2| No   | 2256 |  0.541     |  3.930      |
-+---------------------+--------------+------+------+------------+-------------+
-|inst_rom_wb/inst_rom |              |      |      |            |             |
-|            /bs_clk1 | BUFGCTRL_X0Y0| No   |   76 |  0.190     |  3.686      |
-+---------------------+--------------+------+------+------------+-------------+
-|             vga_clk |BUFGCTRL_X0Y11| No   |  167 |  0.408     |  3.881      |
-+---------------------+--------------+------+------+------------+-------------+
-|          sdram_clk0 |BUFGCTRL_X0Y31| No   |  227 |  0.492     |  3.933      |
-+---------------------+--------------+------+------+------------+-------------+
-|sys_ac97_bit_clk_IBU |              |      |      |            |             |
-|                   F | BUFGCTRL_X0Y8| No   |  251 |  0.428     |  3.823      |
-+---------------------+--------------+------+------+------------+-------------+
-|    sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No   |   55 |  0.205     |  3.675      |
-+---------------------+--------------+------+------+------------+-------------+
-|        sdram_clk270 |BUFGCTRL_X0Y16| No   |   68 |  0.158     |  3.932      |
-+---------------------+--------------+------+------+------------+-------------+
-|     sdram_clk270var |BUFGCTRL_X0Y28| No   |   32 |  0.025     |  3.930      |
-+---------------------+--------------+------+------+------------+-------------+
-|inst_rom_wb/inst_rom |              |      |      |            |             |
-|         /bs_update1 |BUFGCTRL_X0Y26| No   |    4 |  0.044     |  3.631      |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-Timing Score: 1304
-
-WARNING:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
-   your design.
-
-      Review the timing report using Timing Analyzer (In ISE select "Post-Place &
-      Route Static Timing Report").  Go to the failing constraint(s) and select
-      the "Timing Improvement Wizard" link for suggestions to correct each problem.
-
-   Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
-   ensure the best options are set in the tools for timing closure.
-
-   Use the Xilinx "SmartXplorer" script to try special combinations of
-   options known to produce very good results.
-
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
-   requested value.
-Asterisk (*) preceding a constraint indicates it was not met.
-   This may be due to a setup or hold violation.
-
-------------------------------------------------------------------------------------------------------
-  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
-                                            |         |    Slack   | Achievable | Errors |    Score   
-------------------------------------------------------------------------------------------------------
-* TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns  | SETUP   |    -0.293ns|    10.193ns|       9|        1107
-  HIGH 50%                                  | HOLD    |     0.365ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP   |    -0.197ns|    10.294ns|       1|         197
-   ns HIGH 50%                              | HOLD    |     0.346ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-  TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP   |     0.170ns|     7.330ns|       0|           0
-   7.5 ns HIGH 50%                          | HOLD    |     0.513ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-  TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP   |     0.386ns|     7.614ns|       0|           0
-  s HIGH 50%                                | HOLD    |     0.514ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-  NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80  | SETUP   |    36.650ns|     6.700ns|       0|           0
-  ns HIGH 50%                               | HOLD    |     0.518ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-  TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP   |    74.716ns|     5.284ns|       0|           0
-   ns HIGH 50%                              | HOLD    |     0.802ns|            |       0|           0
-------------------------------------------------------------------------------------------------------
-  PATH "TS_unrelate_SDRAM_path" TIG         | SETUP   |         N/A|     9.594ns|     N/A|           0
-------------------------------------------------------------------------------------------------------
-  PATH "TS_unrelate_VGA_path" TIG           | SETUP   |         N/A|     6.138ns|     N/A|           0
-------------------------------------------------------------------------------------------------------
-
-
-2 constraints not met.
-INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
-   constraint does not cover any paths or that it has no requested value.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-Total REAL time to PAR completion: 3 mins 18 secs 
-Total CPU time to PAR completion: 3 mins 9 secs 
-
-Peak Memory Usage:  428 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - 10 errors found.
-
-Number of error messages: 0
-Number of warning messages: 1
-Number of info messages: 1
-
-Writing design to file mips_sys.ncd
-
-
-
-PAR done!
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj
deleted file mode 100644
index b8b35cd..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj
+++ /dev/null
@@ -1,47 +0,0 @@
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../src/sdram_config.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/misc/singleshot.vhd"
-vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
-vhdl work "../../src/bootloader.ROM_ld.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
-vhdl work "../../../../lib/uart/uart_tx.vhd"
-vhdl work "../../../../lib/uart/uart_rx.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/ps2_port/src/ps2_core.vhd"
-vhdl work "../../../../lib/ps2_port/src/debounce.vhd"
-vhdl work "../../../../lib/misc/async_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
-vhdl work "../../src/clockgen_virtex4.vhd"
-vhdl work "../../src/async_defs.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-vhdl work "../../../../lib/uart/uart_wb.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-vhdl work "../../../../lib/ps2_port/src/ps2_wb.vhd"
-vhdl work "../../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
-vhdl work "../../../../lib/misc/rom_wb.vhd"
-vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/misc/gpio_wb.vhd"
-vhdl work "../../../../lib/misc/async_port_wb.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
-vhdl work "../../src/mips_sys.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr
deleted file mode 100644
index 51fc424..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr
+++ /dev/null
@@ -1,5227 +0,0 @@
-Release 10.1.03 - xst K.39 (nt)
-Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
---> Parameter TMPDIR set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
- 
---> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst
-
-
-Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.13 secs
- 
---> Reading design: mips_sys.prj
-
-TABLE OF CONTENTS
-  1) Synthesis Options Summary
-  2) HDL Compilation
-  3) Design Hierarchy Analysis
-  4) HDL Analysis
-  5) HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Advanced HDL Synthesis
-     6.1) Advanced HDL Synthesis Report
-  7) Low Level Synthesis
-  8) Partition Report
-  9) Final Report
-     9.1) Device utilization summary
-     9.2) Partition Resource Summary
-     9.3) TIMING REPORT
-
-
-=========================================================================
-*                      Synthesis Options Summary                        *
-=========================================================================
----- Source Parameters
-Input File Name                    : "mips_sys.prj"
-Input Format                       : mixed
-Ignore Synthesis Constraint File   : NO
-
----- Target Parameters
-Output File Name                   : "mips_sys"
-Output Format                      : NGC
-Target Device                      : xc4vsx35-10-ff668
-
----- Source Options
-Top Module Name                    : mips_sys
-Automatic FSM Extraction           : YES
-FSM Encoding Algorithm             : Auto
-Safe Implementation                : No
-FSM Style                          : lut
-RAM Extraction                     : Yes
-RAM Style                          : Auto
-ROM Extraction                     : Yes
-Mux Style                          : Auto
-Decoder Extraction                 : YES
-Priority Encoder Extraction        : YES
-Shift Register Extraction          : YES
-Logical Shifter Extraction         : YES
-XOR Collapsing                     : YES
-ROM Style                          : Auto
-Mux Extraction                     : YES
-Resource Sharing                   : NO
-Asynchronous To Synchronous        : NO
-Use DSP Block                      : auto
-Automatic Register Balancing       : Yes
-
----- Target Options
-Add IO Buffers                     : YES
-Global Maximum Fanout              : 500
-Add Generic Clock Buffer(BUFG)     : 32
-Number of Regional Clock Buffers   : 24
-Register Duplication               : YES
-Move First FlipFlop Stage          : YES
-Move Last FlipFlop Stage           : YES
-Slice Packing                      : YES
-Optimize Instantiated Primitives   : NO
-Use Clock Enable                   : Auto
-Use Synchronous Set                : Auto
-Use Synchronous Reset              : Auto
-Pack IO Registers into IOBs        : true
-Equivalent register Removal        : YES
-
----- General Options
-Optimization Goal                  : Speed
-Optimization Effort                : 1
-Power Reduction                    : NO
-Library Search Order               : mips_sys.lso
-Keep Hierarchy                     : NO
-Netlist Hierarchy                  : as_optimized
-RTL Output                         : Yes
-Global Optimization                : AllClockNets
-Read Cores                         : YES
-Write Timing Constraints           : NO
-Cross Clock Analysis               : NO
-Hierarchy Separator                : /
-Bus Delimiter                      : <>
-Case Specifier                     : maintain
-Slice Utilization Ratio            : 100
-BRAM Utilization Ratio             : 100
-DSP48 Utilization Ratio            : 100
-Verilog 2001                       : YES
-Auto BRAM Packing                  : NO
-Slice Utilization Ratio Delta      : 5
-
-=========================================================================
-
-
-=========================================================================
-*                          HDL Compilation                              *
-=========================================================================
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_ctrl_pkg.vhd" in Library work.
-Architecture fifo_ctrl_pkg of Entity fifo_ctrl_pkg is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_types.vhd" in Library work.
-Architecture vga_types of Entity vga_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/sdram_config.vhd" in Library work.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/gray_counter.vhd" in Library work.
-Architecture behavioral of Entity gray_counter is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/singleshot.vhd" in Library work.
-Architecture behavioral of Entity singleshot is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd" in Library work.
-Architecture behavioral of Entity vga_sync is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" in Library work.
-Architecture sdram_types of Entity sdram_types is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd" in Library work.
-Architecture behavioral of Entity fifo_async_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work.
-Architecture behavioral of Entity dpram_1w1r is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work.
-WARNING:HDLParsers:3534 - "W:/vhdl/lib/misc/utils_pkg.vhd" Line 155. In the function f_correct, not all control paths contain a return statement.
-Architecture utils_pkg of Entity utils_pkg is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work.
-Architecture behavioral of Entity ac_in is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" in Library work.
-Architecture behavioral of Entity ac_out is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd" in Library work.
-Architecture behavioral of Entity fifo_sync_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" in Library work.
-Architecture rtl of Entity char_rom is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd" in Library work.
-Architecture behavioral of Entity vga_timing is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" in Library work.
-Architecture behaviour of Entity sdram_ctrl is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async.vhd" in Library work.
-Architecture behavioral of Entity fifo_async is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" in Library work.
-Architecture behaviour of Entity sdram_cmd is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" in Library work.
-Architecture tech of Entity ddr_phy is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/kcuart_rx.vhd" in Library work.
-Architecture low_level_definition of Entity kcuart_rx is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/bbfifo_16x8.vhd" in Library work.
-Architecture low_level_definition of Entity bbfifo_16x8 is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/kcuart_tx.vhd" in Library work.
-Architecture low_level_definition of Entity kcuart_tx is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work.
-Architecture behavioral of Entity debounce is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work.
-Architecture behavioral of Entity ps2_core is up to date.
-Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work.
-Architecture behavioral of Entity fifo_sync is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work.
-Architecture behavioral of Entity ac_io is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd" in Library work.
-Architecture behavioral of Entity vga_backend is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd" in Library work.
-Architecture behavioral of Entity char_gen is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" in Library work.
-Architecture rtl of Entity sdram_ctrl_top is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_tx.vhd" in Library work.
-Architecture macro_level_definition of Entity uart_tx is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_rx.vhd" in Library work.
-Architecture macro_level_definition of Entity uart_rx is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work.
-Architecture async_types of Entity async_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work.
-Architecture data of Entity rom is up to date.
-Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work.
-Architecture mips_types of Entity mips_types is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work.
-Compiling vhdl file "W:/vhdl/lib/misc/rom_wb.vhd" in Library work.
-Architecture behavior of Entity rom_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work.
-Architecture behavioral of Entity lcd_port is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work.
-Architecture behavior of Entity gpio_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work.
-Architecture behavioral of Entity async_port_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work.
-Architecture behavior of Entity uart_wb is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work.
-Architecture tech of Entity clockgen is up to date.
-Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work.
-Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work.
-Architecture behavioral of Entity vga_frontend64 is up to date.
-Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd" in Library work.
-Architecture behavior of Entity ac97_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd" in Library work.
-Architecture behavior of Entity ps2_wb is up to date.
-Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work.
-Architecture behavioral of Entity ps2_phy is up to date.
-Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work.
-Architecture behavior of Entity mips_sys is up to date.
-
-=========================================================================
-*                     Design Hierarchy Analysis                         *
-=========================================================================
-Analyzing hierarchy for entity <mips_sys> in library <work> (architecture <behavior>) with generics.
-	sdram_phaseshift = 0
-	sys_freq = 100.000000
-	sys_freq_in = 100.000000
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-
-Analyzing hierarchy for entity <rom_wb> in library <work> (architecture <behavior>).
-
-Analyzing hierarchy for entity <lcd_port> in library <work> (architecture <behavioral>).
-
-Analyzing hierarchy for entity <gpio_wb> in library <work> (architecture <behavior>) with generics.
-	f_sysclk = 100.000000
-
-Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
-	addr_width = 25
-	async_timespec = (T_leadin => 0.000000
-	                  T_pulse_rd => 120.000000
-	                  T_pulse_wr => 70.000000
-	                  T_leadout => 0.000000
-	                  T_release => 40.000000
-	                  T_pulse_rst => 80.000000
-	                  T_pulse_page_rd => 30.000000
-	                  can_page_rd => true
-	                  nbits_page_rd => 4
-	                  pol_cs => '1'
-	                  pol_oe => '0'
-	                  pol_we => '0'
-	                  pol_be => '0'
-	                  pol_rst => '0')
-	byte_sel_width = 1
-	data_width = 32
-	f_sysclk = 100.000000
-
-Analyzing hierarchy for entity <async_port_wb> in library <work> (architecture <behavioral>) with generics.
-	addr_width = 4
-	async_timespec = (T_leadin => 10.000000
-	                  T_pulse_rd => 60.000000
-	                  T_pulse_wr => 60.000000
-	                  T_leadout => 10.000000
-	                  T_release => 80.000000
-	                  T_pulse_rst => 80.000000
-	                  T_pulse_page_rd => 0.000000
-	                  can_page_rd => false
-	                  nbits_page_rd => 0
-	                  pol_cs => '0'
-	                  pol_oe => '0'
-	                  pol_we => '0'
-	                  pol_be => '0'
-	                  pol_rst => '0')
-	byte_sel_width = 1
-	data_width = 16
-	f_sysclk = 100.000000
-
-Analyzing hierarchy for entity <uart_wb> in library <work> (architecture <behavior>) with generics.
-	simulate_tx = false
-
-Analyzing hierarchy for entity <clockgen> in library <work> (architecture <tech>) with generics.
-	clk_in_freq = 100.000000
-	sdr0_clk_out_phaseshift = 0
-	sdr1_clk_out_phaseshift = 0
-	sys_clk_out_freq = 100.000000
-	vga_clk_out_freq = 40.000000
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 131: VHDL Assertion Statement with non constant condition is ignored.
-WARNING:Xst:1748 - "W:/vhdl/lib/misc/utils_pkg.vhd" line 103: VHDL Assertion Statement with non constant condition is ignored.
-
-Analyzing hierarchy for entity <sdram_ctrl_frontend64_wb> in library <work> (architecture <struct>) with generics.
-	BL = 2
-	f_sdrclk = 100.000000
-	f_sysclk = 100.000000
-	fifo_depth = 5
-
-Analyzing hierarchy for entity <vga_frontend64> in library <work> (architecture <behavioral>) with generics.
-	fifo_almost_empty_thresh = 256
-	fifo_almost_full_thresh = 1920
-	fifo_depth = 2048
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-
-Analyzing hierarchy for entity <ac97_wb> in library <work> (architecture <behavior>) with generics.
-	fifo_depth = 8
-
-Analyzing hierarchy for entity <ps2_wb> in library <work> (architecture <behavior>) with generics.
-	f_sys_clk = 100.000000
-
-Analyzing hierarchy for entity <ps2_phy> in library <work> (architecture <Behavioral>).
-
-Analyzing hierarchy for entity <rom> in library <work> (architecture <data>).
-
-Analyzing hierarchy for entity <uart_tx> in library <work> (architecture <macro_level_definition>).
-
-Analyzing hierarchy for entity <uart_rx> in library <work> (architecture <macro_level_definition>).
-
-Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 30
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 72
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 64
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <sdram_ctrl_top> in library <work> (architecture <rtl>) with generics.
-	BL = 2
-	f_sdrclk = 100.000000
-	f_sysclk = 100.000000
-	fifo_depth = 5
-
-Analyzing hierarchy for entity <vga_backend> in library <work> (architecture <Behavioral>) with generics.
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-
-Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 11
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 256
-	almost_full_thresh = 1920
-	data_width = 64
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 9
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 64
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 2
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 105
-	do_last_read_update = false
-
-Analyzing hierarchy for entity <char_gen> in library <work> (architecture <Behavioral>) with generics.
-	CHARACTER_SCALE = 1
-	CHAR_ROM_DEPTH = 256
-	CHAR_ROM_SIZE_X = 8
-	CHAR_ROM_SIZE_Y = 16
-	CHAR_SPACING_X = 0
-	CHAR_SPACING_Y = 0
-	MAX_CHAR_PER_LINE = 80
-	MAX_LINE_PER_FRAME = 32
-	SCREEN_OFFSET_X = 16
-	SCREEN_OFFSET_Y = 16
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-
-Analyzing hierarchy for entity <fifo_sync> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 8
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 25
-	almost_full_thresh = 230
-	data_width = 18
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <ac_io> in library <work> (architecture <Behavioral>).
-
-Analyzing hierarchy for entity <ps2_core> in library <work> (architecture <Behavioral>) with generics.
-	f_sys_clk = 100.000000
-
-Analyzing hierarchy for entity <debounce> in library <work> (architecture <behavioral>) with generics.
-	ncyc_latency = 8
-
-Analyzing hierarchy for entity <kcuart_tx> in library <work> (architecture <low_level_definition>).
-
-Analyzing hierarchy for entity <bbfifo_16x8> in library <work> (architecture <low_level_definition>).
-
-Analyzing hierarchy for entity <kcuart_rx> in library <work> (architecture <low_level_definition>).
-
-Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	data_width = 30
-
-Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	data_width = 72
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	data_width = 64
-
-Analyzing hierarchy for entity <sdram_ctrl> in library <work> (architecture <behaviour>) with generics.
-	BL = 2
-	f_sysclk = 100.000000
-
-Analyzing hierarchy for entity <fifo_async> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 32
-	do_last_read_update = true
-
-Analyzing hierarchy for entity <sdram_cmd> in library <work> (architecture <behaviour>) with generics.
-	BL = 2
-	f_sdrclk = 100.000000
-
-Analyzing hierarchy for entity <ddr_phy> in library <work> (architecture <tech>).
-
-Analyzing hierarchy for entity <vga_timing> in library <work> (architecture <Behavioral>) with generics.
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-
-Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 11
-	almost_empty_thresh = 256
-	almost_full_thresh = 1920
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 11
-	data_width = 64
-
-Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 9
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 9
-	data_width = 64
-
-Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 2
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 2
-	data_width = 105
-
-Analyzing hierarchy for entity <char_rom> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 12
-	data_width = 8
-
-Analyzing hierarchy for entity <fifo_sync_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 8
-	almost_empty_thresh = 25
-	almost_full_thresh = 230
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 8
-	data_width = 18
-
-Analyzing hierarchy for entity <ac_in> in library <work> (architecture <behavioral>).
-
-Analyzing hierarchy for entity <ac_out> in library <work> (architecture <behavioral>).
-
-Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
-	init_value = 0
-	width = 6
-
-Analyzing hierarchy for entity <fifo_async_ctrl> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-
-Analyzing hierarchy for entity <dpram_1w1r> in library <work> (architecture <Behavioral>) with generics.
-	addr_width = 5
-	data_width = 32
-
-Analyzing hierarchy for entity <vga_sync> in library <work> (architecture <Behavioral>) with generics.
-	ts = (ncyc_scan => 800
-	      ncyc_porch_front => 40
-	      ncyc_sync_pulse => 128
-	      ncyc_porch_back => 88
-	      sync_polarity => '0')
-
-Analyzing hierarchy for entity <vga_sync> in library <work> (architecture <Behavioral>) with generics.
-	ts = (ncyc_scan => 600
-	      ncyc_porch_front => 1
-	      ncyc_sync_pulse => 4
-	      ncyc_porch_back => 23
-	      sync_polarity => '0')
-
-Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
-	init_value = 0
-	width = 12
-
-Analyzing hierarchy for entity <singleshot> in library <work> (architecture <behavioral>) with generics.
-	mode = 0
-
-Analyzing hierarchy for entity <singleshot> in library <work> (architecture <behavioral>) with generics.
-	mode = 1
-
-Analyzing hierarchy for entity <gray_counter> in library <work> (architecture <Behavioral>) with generics.
-	init_value = 0
-	width = 6
-
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 221: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 270: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 318: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 257: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 254: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 133: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 281: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 300: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 354: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 158: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 215: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 226: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 239: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 236: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-
-=========================================================================
-*                            HDL Analysis                               *
-=========================================================================
-Analyzing generic Entity <mips_sys> in library <work> (Architecture <behavior>).
-	sdram_phaseshift = 0
-	sys_freq = 100.000000
-	sys_freq_in = 100.000000
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-    Set user-defined property "KEEP =  TRUE" for signal <cpu_clk>.
-    Set user-defined property "KEEP =  TRUE" for signal <sdram_clk0>.
-    Set user-defined property "KEEP =  TRUE" for signal <vga_clk>.
-    Set user-defined property "KEEP =  TRUE" for signal <CLK_O>.
-    Set user-defined property "KEEP =  TRUE" for signal <RST_O>.
-WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 678: Instantiating black box module <mips_top>.
-WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 715: Unconnected output port 'dout' of component 'lcd_port'.
-WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 756: Unconnected output port 'async_be' of component 'async_port_wb'.
-WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_be' of component 'async_port_wb'.
-WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 789: Unconnected output port 'async_rst' of component 'async_port_wb'.
-WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 863: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'.
-Entity <mips_sys> analyzed. Unit <mips_sys> generated.
-
-Analyzing Entity <rom_wb> in library <work> (Architecture <behavior>).
-Entity <rom_wb> analyzed. Unit <rom_wb> generated.
-
-Analyzing Entity <rom> in library <work> (Architecture <data>).
-    Set user-defined property "JTAG_CHAIN =  1" for instance <BSCAN_VIRTEX4_inst1> in unit <rom>.
-Entity <rom> analyzed. Unit <rom> generated.
-
-Analyzing Entity <lcd_port> in library <work> (Architecture <behavioral>).
-Entity <lcd_port> analyzed. Unit <lcd_port> generated.
-
-Analyzing generic Entity <gpio_wb> in library <work> (Architecture <behavior>).
-	f_sysclk = 100.000000
-Entity <gpio_wb> analyzed. Unit <gpio_wb> generated.
-
-Analyzing generic Entity <async_port_wb.1> in library <work> (Architecture <behavioral>).
-	addr_width = 25
-	async_timespec = (T_leadin => 0.000000
-	                  T_pulse_rd => 120.000000
-	                  T_pulse_wr => 70.000000
-	                  T_leadout => 0.000000
-	                  T_release => 40.000000
-	                  T_pulse_rst => 80.000000
-	                  T_pulse_page_rd => 30.000000
-	                  can_page_rd => true
-	                  nbits_page_rd => 4
-	                  pol_cs => '1'
-	                  pol_oe => '0'
-	                  pol_we => '0'
-	                  pol_be => '0'
-	                  pol_rst => '0')
-	byte_sel_width = 1
-	data_width = 32
-	f_sysclk = 100.000000
-Entity <async_port_wb.1> analyzed. Unit <async_port_wb.1> generated.
-
-Analyzing generic Entity <async_port_wb.2> in library <work> (Architecture <behavioral>).
-	addr_width = 4
-	async_timespec = (T_leadin => 10.000000
-	                  T_pulse_rd => 60.000000
-	                  T_pulse_wr => 60.000000
-	                  T_leadout => 10.000000
-	                  T_release => 80.000000
-	                  T_pulse_rst => 80.000000
-	                  T_pulse_page_rd => 0.000000
-	                  can_page_rd => false
-	                  nbits_page_rd => 0
-	                  pol_cs => '0'
-	                  pol_oe => '0'
-	                  pol_we => '0'
-	                  pol_be => '0'
-	                  pol_rst => '0')
-	byte_sel_width = 1
-	data_width = 16
-	f_sysclk = 100.000000
-Entity <async_port_wb.2> analyzed. Unit <async_port_wb.2> generated.
-
-Analyzing generic Entity <uart_wb> in library <work> (Architecture <behavior>).
-	simulate_tx = false
-INFO:Xst:2679 - Register <DAT_O<31>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<30>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<29>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<28>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<27>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<26>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<25>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<24>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<23>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<22>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<21>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<20>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<19>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<18>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<17>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<16>> in unit <uart_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <uart_wb> analyzed. Unit <uart_wb> generated.
-
-Analyzing Entity <uart_tx> in library <work> (Architecture <macro_level_definition>).
-Entity <uart_tx> analyzed. Unit <uart_tx> generated.
-
-Analyzing Entity <kcuart_tx> in library <work> (Architecture <low_level_definition>).
-    Set user-defined property "INIT =  E4FF" for instance <mux1_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  E4FF" for instance <mux2_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  E4FF" for instance <mux3_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  E4FF" for instance <mux4_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <pipeline_serial> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[0].register_bit> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  8" for instance <count_width_loop[0].count_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[1].register_bit> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  8" for instance <count_width_loop[1].count_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[2].register_bit> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  8" for instance <count_width_loop[2].count_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  10" for instance <ready_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0190" for instance <start_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <Tx_start_reg> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  1540" for instance <run_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <Tx_run_reg> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  94" for instance <hot_state_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <hot_state_reg> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0000" for instance <delay14_srl> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <Tx_bit_reg> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0180" for instance <stop_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <Tx_stop_reg> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  8" for instance <complete_lut> in unit <kcuart_tx>.
-    Set user-defined property "INIT =  0" for instance <Tx_complete_reg> in unit <kcuart_tx>.
-Entity <kcuart_tx> analyzed. Unit <kcuart_tx> generated.
-
-Analyzing Entity <bbfifo_16x8> in library <work> (Architecture <low_level_definition>).
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[0].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[1].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[2].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[3].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[4].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[5].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[6].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0000" for instance <data_width_loop[7].data_srl> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[0].register_bit> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  6606" for instance <count_width_loop[0].count_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[1].register_bit> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  6606" for instance <count_width_loop[1].count_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[2].register_bit> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  6606" for instance <count_width_loop[2].count_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0" for instance <count_width_loop[3].register_bit> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  6606" for instance <count_width_loop[3].count_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0001" for instance <zero_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  8000" for instance <full_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  BFA0" for instance <dp_lut> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  0" for instance <dp_flop> in unit <bbfifo_16x8>.
-    Set user-defined property "INIT =  C4" for instance <valid_lut> in unit <bbfifo_16x8>.
-Entity <bbfifo_16x8> analyzed. Unit <bbfifo_16x8> generated.
-
-Analyzing Entity <uart_rx> in library <work> (Architecture <macro_level_definition>).
-Entity <uart_rx> analyzed. Unit <uart_rx> generated.
-
-Analyzing Entity <kcuart_rx> in library <work> (Architecture <low_level_definition>).
-    Set user-defined property "INIT =  0" for instance <sync_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <stop_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[0].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[0].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[1].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[1].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[2].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[2].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[3].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[3].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[4].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[4].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[5].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[5].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[6].lsbs.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[6].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <data_loop[7].msb.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <data_loop[7].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <start_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <start_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <edge_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <edge_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0040" for instance <valid_lut> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  54" for instance <purge_lut> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <purge_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[0].lsb.delay15_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[0].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[1].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[1].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[2].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[2].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[3].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[3].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[4].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[4].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[5].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[5].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[6].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[6].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[7].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[7].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0000" for instance <valid_loop[8].msbs.delay16_srl> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <valid_loop[8].data_reg> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  8" for instance <strobe_lut> in unit <kcuart_rx>.
-    Set user-defined property "INIT =  0" for instance <strobe_reg> in unit <kcuart_rx>.
-Entity <kcuart_rx> analyzed. Unit <kcuart_rx> generated.
-
-Analyzing generic Entity <clockgen> in library <work> (Architecture <tech>).
-	clk_in_freq = 100.000000
-	sdr0_clk_out_phaseshift = 0
-	sdr1_clk_out_phaseshift = 0
-	sys_clk_out_freq = 100.000000
-	vga_clk_out_freq = 40.000000
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKFX_DIVIDE =  5" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DESKEW_ADJUST =  SOURCE_SYNCHRONOUS" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "FACTORY_JF =  F0F0" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <inst_DCM_VGA_FX> in unit <clockgen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKFX_DIVIDE =  2" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DESKEW_ADJUST =  SOURCE_SYNCHRONOUS" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "FACTORY_JF =  F0F0" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <inst_DCM_SYS_FX> in unit <clockgen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  FIXED" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DESKEW_ADJUST =  SOURCE_SYNCHRONOUS" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "FACTORY_JF =  F0F0" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <inst_DCM_SDRCLK_0> in unit <clockgen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  FIXED" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DCM_AUTOCALIBRATION =  TRUE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DCM_PERFORMANCE_MODE =  MAX_SPEED" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "FACTORY_JF =  F0F0" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <inst_DCM_SDRCLK_1> in unit <clockgen>.
-WARNING:Xst:819 - "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" line 345: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <sdr0_lock>, <sdr1_lock>, <sys_fx_lock>, <vga_fx_lock>
-Entity <clockgen> analyzed. Unit <clockgen> generated.
-
-Analyzing generic Entity <sdram_ctrl_frontend64_wb> in library <work> (Architecture <struct>).
-	BL = 2
-	f_sdrclk = 100.000000
-	f_sysclk = 100.000000
-	fifo_depth = 5
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_afull' of component 'fifo_async'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_afull' of component 'fifo_async'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
-Entity <sdram_ctrl_frontend64_wb> analyzed. Unit <sdram_ctrl_frontend64_wb> generated.
-
-Analyzing generic Entity <fifo_sync.1> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 30
-	do_last_read_update = true
-Entity <fifo_sync.1> analyzed. Unit <fifo_sync.1> generated.
-
-Analyzing generic Entity <fifo_sync_ctrl.1> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-Entity <fifo_sync_ctrl.1> analyzed. Unit <fifo_sync_ctrl.1> generated.
-
-Analyzing generic Entity <dpram_1w1r.1> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	data_width = 30
-Entity <dpram_1w1r.1> analyzed. Unit <dpram_1w1r.1> generated.
-
-Analyzing generic Entity <fifo_async.1> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 72
-	do_last_read_update = true
-Entity <fifo_async.1> analyzed. Unit <fifo_async.1> generated.
-
-Analyzing generic Entity <fifo_async_ctrl.1> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-Entity <fifo_async_ctrl.1> analyzed. Unit <fifo_async_ctrl.1> generated.
-
-Analyzing generic Entity <gray_counter.1> in library <work> (Architecture <Behavioral>).
-	init_value = 0
-	width = 6
-Entity <gray_counter.1> analyzed. Unit <gray_counter.1> generated.
-
-Analyzing generic Entity <dpram_1w1r.2> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	data_width = 72
-Entity <dpram_1w1r.2> analyzed. Unit <dpram_1w1r.2> generated.
-
-Analyzing generic Entity <fifo_async.2> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 64
-	do_last_read_update = true
-Entity <fifo_async.2> analyzed. Unit <fifo_async.2> generated.
-
-Analyzing generic Entity <dpram_1w1r.3> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	data_width = 64
-Entity <dpram_1w1r.3> analyzed. Unit <dpram_1w1r.3> generated.
-
-Analyzing generic Entity <sdram_ctrl_top> in library <work> (Architecture <rtl>).
-	BL = 2
-	f_sdrclk = 100.000000
-	f_sysclk = 100.000000
-	fifo_depth = 5
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_afull' of component 'fifo_async'.
-WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_aempty' of component 'fifo_async'.
-Entity <sdram_ctrl_top> analyzed. Unit <sdram_ctrl_top> generated.
-
-Analyzing generic Entity <sdram_ctrl> in library <work> (Architecture <behaviour>).
-	BL = 2
-	f_sysclk = 100.000000
-Entity <sdram_ctrl> analyzed. Unit <sdram_ctrl> generated.
-
-Analyzing generic Entity <fifo_async.4> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 32
-	do_last_read_update = true
-Entity <fifo_async.4> analyzed. Unit <fifo_async.4> generated.
-
-Analyzing generic Entity <dpram_1w1r.9> in library <work> (Architecture <Behavioral>).
-	addr_width = 5
-	data_width = 32
-Entity <dpram_1w1r.9> analyzed. Unit <dpram_1w1r.9> generated.
-
-Analyzing generic Entity <sdram_cmd> in library <work> (Architecture <behaviour>).
-	BL = 2
-	f_sdrclk = 100.000000
-Entity <sdram_cmd> analyzed. Unit <sdram_cmd> generated.
-
-Analyzing Entity <ddr_phy> in library <work> (Architecture <tech>).
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <ODDR_clk_p> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <ODDR_clk_p> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <ODDR_clk_p> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <ODDR_clk_n> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <ODDR_clk_n> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <ODDR_clk_n> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[0].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[1].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[2].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[3].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[4].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[5].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[6].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[7].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[8].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[9].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[10].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[11].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[12].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[13].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[14].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[15].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[16].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[17].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[18].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[19].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[20].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[21].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[22].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[23].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[24].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[25].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[26].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[27].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[28].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[29].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[30].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_out[31].ODDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_dm_out[0].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_dm_out[1].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_dm_out[2].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_dm_out[3].ODDR_dm> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_dqs_out[0].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_dqs_out[1].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_dqs_out[2].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  OPPOSITE_EDGE" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "INIT =  0" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_dqs_out[3].ODDR_dqs> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[0].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[1].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[2].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[3].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[4].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[5].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[6].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[7].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[8].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[9].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[10].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[11].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[12].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[13].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[14].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[15].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[16].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[17].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[18].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[19].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[20].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[21].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[22].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[23].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[24].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[25].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[26].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[27].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[28].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[29].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[30].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "DDR_CLK_EDGE =  SAME_EDGE" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q1 =  0" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "INIT_Q2 =  0" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <gen_ddr_data_in[31].IDDR_data> in unit <ddr_phy>.
-Entity <ddr_phy> analyzed. Unit <ddr_phy> generated.
-
-Analyzing generic Entity <vga_frontend64> in library <work> (Architecture <behavioral>).
-	fifo_almost_empty_thresh = 256
-	fifo_almost_full_thresh = 1920
-	fifo_depth = 2048
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
-WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
-WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_afull' of component 'fifo_sync'.
-WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_aempty' of component 'fifo_sync'.
-WARNING:Xst:819 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 436: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <blit_request>
-Entity <vga_frontend64> analyzed. Unit <vga_frontend64> generated.
-
-Analyzing generic Entity <vga_backend> in library <work> (Architecture <Behavioral>).
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-Entity <vga_backend> analyzed. Unit <vga_backend> generated.
-
-Analyzing generic Entity <vga_timing> in library <work> (Architecture <Behavioral>).
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-Entity <vga_timing> analyzed. Unit <vga_timing> generated.
-
-Analyzing generic Entity <vga_sync.1> in library <work> (Architecture <Behavioral>).
-	ts = (ncyc_scan => 800
-	      ncyc_porch_front => 40
-	      ncyc_sync_pulse => 128
-	      ncyc_porch_back => 88
-	      sync_polarity => '0')
-Entity <vga_sync.1> analyzed. Unit <vga_sync.1> generated.
-
-Analyzing generic Entity <vga_sync.2> in library <work> (Architecture <Behavioral>).
-	ts = (ncyc_scan => 600
-	      ncyc_porch_front => 1
-	      ncyc_sync_pulse => 4
-	      ncyc_porch_back => 23
-	      sync_polarity => '0')
-Entity <vga_sync.2> analyzed. Unit <vga_sync.2> generated.
-
-Analyzing generic Entity <fifo_async.3> in library <work> (Architecture <Behavioral>).
-	addr_width = 11
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 256
-	almost_full_thresh = 1920
-	data_width = 64
-	do_last_read_update = true
-Entity <fifo_async.3> analyzed. Unit <fifo_async.3> generated.
-
-Analyzing generic Entity <fifo_async_ctrl.2> in library <work> (Architecture <Behavioral>).
-	addr_width = 11
-	almost_empty_thresh = 256
-	almost_full_thresh = 1920
-Entity <fifo_async_ctrl.2> analyzed. Unit <fifo_async_ctrl.2> generated.
-
-Analyzing generic Entity <gray_counter.2> in library <work> (Architecture <Behavioral>).
-	init_value = 0
-	width = 12
-Entity <gray_counter.2> analyzed. Unit <gray_counter.2> generated.
-
-Analyzing generic Entity <dpram_1w1r.4> in library <work> (Architecture <Behavioral>).
-	addr_width = 11
-	data_width = 64
-Entity <dpram_1w1r.4> analyzed. Unit <dpram_1w1r.4> generated.
-
-Analyzing generic Entity <fifo_sync.2> in library <work> (Architecture <Behavioral>).
-	addr_width = 9
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 64
-	do_last_read_update = true
-Entity <fifo_sync.2> analyzed. Unit <fifo_sync.2> generated.
-
-Analyzing generic Entity <fifo_sync_ctrl.2> in library <work> (Architecture <Behavioral>).
-	addr_width = 9
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-Entity <fifo_sync_ctrl.2> analyzed. Unit <fifo_sync_ctrl.2> generated.
-
-Analyzing generic Entity <dpram_1w1r.5> in library <work> (Architecture <Behavioral>).
-	addr_width = 9
-	data_width = 64
-Entity <dpram_1w1r.5> analyzed. Unit <dpram_1w1r.5> generated.
-
-Analyzing generic Entity <fifo_sync.3> in library <work> (Architecture <Behavioral>).
-	addr_width = 2
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-	data_width = 105
-	do_last_read_update = false
-Entity <fifo_sync.3> analyzed. Unit <fifo_sync.3> generated.
-
-Analyzing generic Entity <fifo_sync_ctrl.3> in library <work> (Architecture <Behavioral>).
-	addr_width = 2
-	almost_empty_thresh = 4
-	almost_full_thresh = 12
-INFO:Xst:2679 - Register <fifo_afull> in unit <fifo_sync_ctrl.3> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <fifo_sync_ctrl.3> analyzed. Unit <fifo_sync_ctrl.3> generated.
-
-Analyzing generic Entity <dpram_1w1r.6> in library <work> (Architecture <Behavioral>).
-	addr_width = 2
-	data_width = 105
-Entity <dpram_1w1r.6> analyzed. Unit <dpram_1w1r.6> generated.
-
-Analyzing generic Entity <char_gen> in library <work> (Architecture <Behavioral>).
-	CHARACTER_SCALE = 1
-	CHAR_ROM_DEPTH = 256
-	CHAR_ROM_SIZE_X = 8
-	CHAR_ROM_SIZE_Y = 16
-	CHAR_SPACING_X = 0
-	CHAR_SPACING_Y = 0
-	MAX_CHAR_PER_LINE = 80
-	MAX_LINE_PER_FRAME = 32
-	SCREEN_OFFSET_X = 16
-	SCREEN_OFFSET_Y = 16
-	tsvga = (f_pxl_clk => 40000000
-	         nfps => 60
-	         ts_h => (ncyc_scan => 800
-	                  ncyc_porch_front => 40
-	                  ncyc_sync_pulse => 128
-	                  ncyc_porch_back => 88
-	                  sync_polarity => '0')
-	         ts_v => (ncyc_scan => 600
-	                  ncyc_porch_front => 1
-	                  ncyc_sync_pulse => 4
-	                  ncyc_porch_back => 23
-	                  sync_polarity => '0'))
-Entity <char_gen> analyzed. Unit <char_gen> generated.
-
-Analyzing Entity <char_rom> in library <work> (Architecture <RTL>).
-Entity <char_rom> analyzed. Unit <char_rom> generated.
-
-Analyzing generic Entity <dpram_1w1r.7> in library <work> (Architecture <Behavioral>).
-	addr_width = 12
-	data_width = 8
-Entity <dpram_1w1r.7> analyzed. Unit <dpram_1w1r.7> generated.
-
-Analyzing generic Entity <ac97_wb> in library <work> (Architecture <behavior>).
-	fifo_depth = 8
-Entity <ac97_wb> analyzed. Unit <ac97_wb> generated.
-
-Analyzing generic Entity <fifo_sync.4> in library <work> (Architecture <Behavioral>).
-	addr_width = 8
-	allow_empty_reads = false
-	allow_full_writes = false
-	almost_empty_thresh = 25
-	almost_full_thresh = 230
-	data_width = 18
-	do_last_read_update = true
-Entity <fifo_sync.4> analyzed. Unit <fifo_sync.4> generated.
-
-Analyzing generic Entity <fifo_sync_ctrl.4> in library <work> (Architecture <Behavioral>).
-	addr_width = 8
-	almost_empty_thresh = 25
-	almost_full_thresh = 230
-Entity <fifo_sync_ctrl.4> analyzed. Unit <fifo_sync_ctrl.4> generated.
-
-Analyzing generic Entity <dpram_1w1r.8> in library <work> (Architecture <Behavioral>).
-	addr_width = 8
-	data_width = 18
-Entity <dpram_1w1r.8> analyzed. Unit <dpram_1w1r.8> generated.
-
-Analyzing Entity <ac_io> in library <work> (Architecture <Behavioral>).
-Entity <ac_io> analyzed. Unit <ac_io> generated.
-
-Analyzing Entity <ac_in> in library <work> (Architecture <behavioral>).
-WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" line 128: Index value(s) does not match array range, simulation mismatch.
-Entity <ac_in> analyzed. Unit <ac_in> generated.
-
-Analyzing generic Entity <singleshot.1> in library <work> (Architecture <behavioral>).
-	mode = 0
-Entity <singleshot.1> analyzed. Unit <singleshot.1> generated.
-
-Analyzing generic Entity <singleshot.2> in library <work> (Architecture <behavioral>).
-	mode = 1
-Entity <singleshot.2> analyzed. Unit <singleshot.2> generated.
-
-Analyzing Entity <ac_out> in library <work> (Architecture <behavioral>).
-WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 127: Index value(s) does not match array range, simulation mismatch.
-WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 128: Index value(s) does not match array range, simulation mismatch.
-Entity <ac_out> analyzed. Unit <ac_out> generated.
-
-Analyzing generic Entity <ps2_wb> in library <work> (Architecture <behavior>).
-	f_sys_clk = 100.000000
-INFO:Xst:2679 - Register <DAT_O<31>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<30>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<29>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<28>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<27>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<26>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<25>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<24>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<23>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<22>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<21>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<20>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<19>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<18>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<17>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <DAT_O<16>> in unit <ps2_wb> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <ps2_wb> analyzed. Unit <ps2_wb> generated.
-
-Analyzing generic Entity <ps2_core> in library <work> (Architecture <Behavioral>).
-	f_sys_clk = 100.000000
-WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 191: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <sipo_reg>
-WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 204: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <piso_reg>
-Entity <ps2_core> analyzed. Unit <ps2_core> generated.
-
-Analyzing Entity <ps2_phy> in library <work> (Architecture <Behavioral>).
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "DRIVE =  2" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "SLEW =  SLOW" for instance <IOBUF_inst_ps2_clk> in unit <ps2_phy>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-    Set user-defined property "DRIVE =  2" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-    Set user-defined property "SLEW =  SLOW" for instance <IOBUF_inst_ps2_data> in unit <ps2_phy>.
-Entity <ps2_phy> analyzed. Unit <ps2_phy> generated.
-
-Analyzing generic Entity <debounce> in library <work> (Architecture <behavioral>).
-	ncyc_latency = 8
-Entity <debounce> analyzed. Unit <debounce> generated.
-
-
-=========================================================================
-*                           HDL Synthesis                               *
-=========================================================================
-
-Performing bidirectional port resolution...
-
-Synthesizing Unit <lcd_port>.
-    Related source file is "W:/vhdl/lib/misc/lcd_port.vhd".
-WARNING:Xst:647 - Input <din<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 4-bit tristate buffer for signal <lcd_d>.
-    Found 8-bit register for signal <dout>.
-    Found 4-bit register for signal <vlcd.d>.
-    Found 1-bit register for signal <vlcd.e>.
-    Found 1-bit register for signal <vlcd.rs>.
-    Found 1-bit register for signal <vlcd.rw>.
-    Summary:
-	inferred  15 D-type flip-flop(s).
-	inferred   4 Tristate(s).
-Unit <lcd_port> synthesized.
-
-
-Synthesizing Unit <gpio_wb>.
-    Related source file is "W:/vhdl/lib/misc/gpio_wb.vhd".
-WARNING:Xst:647 - Input <ADDR_I<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1780 - Signal <cnt_usec_preset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cnt_sec_preset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 32-bit register for signal <DAT_O>.
-    Found 32-bit register for signal <sys_gpo0>.
-    Found 32-bit register for signal <sys_gpo1>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 32-bit up counter for signal <cnt_sec>.
-    Found 1-bit register for signal <cnt_sec_en>.
-    Found 32-bit comparator less for signal <cnt_sec_en$cmp_lt0000> created at line 259.
-    Found 1-bit register for signal <cnt_sec_we>.
-    Found 32-bit up counter for signal <cnt_usec>.
-    Found 32-bit comparator greatequal for signal <cnt_usec$cmp_ge0000> created at line 259.
-    Found 1-bit register for signal <cnt_usec_en>.
-    Found 1-bit register for signal <cnt_usec_we>.
-    Found 32-bit register for signal <gpi0_reg>.
-    Found 32-bit register for signal <gpi1_reg>.
-    Found 32-bit register for signal <gpo0_reg>.
-    Found 32-bit register for signal <gpo1_reg>.
-    Found 32-bit register for signal <reg_data_wr>.
-    Found 7-bit up counter for signal <tick_usec>.
-    Found 7-bit comparator greatequal for signal <tick_usec$cmp_ge0000> created at line 241.
-    Found 64-bit register for signal <timer_cmp>.
-    Found 2-bit register for signal <timer_cmp_we>.
-    Found 32-bit up counter for signal <timer_cnt>.
-    Found 32-bit comparator greatequal for signal <timer_cnt_0$cmp_ge0000> created at line 296.
-    Found 32-bit comparator greatequal for signal <timer_cnt_1$cmp_ge0000> created at line 296.
-    Found 2-bit register for signal <timer_cnt_we>.
-    Found 2-bit register for signal <timer_en>.
-    Found 2-bit register for signal <timer_inten>.
-    Found 2-bit register for signal <timer_irq>.
-    Found 2-bit register for signal <timer_irq_ack>.
-    Found 2-bit register for signal <timer_ovl>.
-    Found 32-bit comparator less for signal <timer_ovl_0$cmp_lt0000> created at line 296.
-    Found 32-bit comparator less for signal <timer_ovl_1$cmp_lt0000> created at line 296.
-    Summary:
-	inferred   5 Counter(s).
-	inferred 339 D-type flip-flop(s).
-	inferred   7 Comparator(s).
-Unit <gpio_wb> synthesized.
-
-
-Synthesizing Unit <async_port_wb_1>.
-    Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd".
-WARNING:Xst:647 - Input <SEL_I<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<31:25>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <page_mode_en_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SEL_I_r<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ADDR_I_r<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-INFO:Xst:1799 - State leadout is never reached in FSM <s>.
-    Found finite state machine <FSM_0> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 6                                              |
-    | Transitions        | 14                                             |
-    | Inputs             | 4                                              |
-    | Outputs            | 5                                              |
-    | Clock              | CLK_I (rising_edge)                            |
-    | Reset              | RST_I (positive)                               |
-    | Reset type         | synchronous                                    |
-    | Reset State        | start                                          |
-    | Power Up State     | start                                          |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 32-bit register for signal <DAT_O>.
-    Found 1-bit register for signal <async_wr>.
-    Found 1-bit register for signal <async_rst>.
-    Found 25-bit register for signal <async_a>.
-    Found 32-bit tristate buffer for signal <async_d>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 1-bit register for signal <async_be<0>>.
-    Found 1-bit register for signal <async_cs>.
-    Found 1-bit register for signal <async_rd>.
-    Found 25-bit register for signal <ADDR_I_r>.
-    Found 5-bit down counter for signal <cycle_cnt>.
-    Found 32-bit register for signal <DAT_I_r>.
-    Found 21-bit comparator equal for signal <do_page_read$cmp_eq0000> created at line 83.
-    Found 32-bit register for signal <Mtridata_async_d> created at line 310.
-    Found 1-bit register for signal <Mtrien_async_d> created at line 310.
-    Found 1-bit register for signal <rdyo>.
-    Found 1-bit register for signal <WE_I_r>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 Counter(s).
-	inferred 155 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-	inferred  32 Tristate(s).
-Unit <async_port_wb_1> synthesized.
-
-
-Synthesizing Unit <async_port_wb_2>.
-    Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd".
-WARNING:Xst:647 - Input <DAT_I<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1305 - Output <DAT_O<31:16>> is never assigned. Tied to value 0000000000000000.
-WARNING:Xst:647 - Input <SEL_I<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<31:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <page_mode_en_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SEL_I_r<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ADDR_I_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_1> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 7                                              |
-    | Transitions        | 13                                             |
-    | Inputs             | 2                                              |
-    | Outputs            | 6                                              |
-    | Clock              | CLK_I (rising_edge)                            |
-    | Reset              | RST_I (positive)                               |
-    | Reset type         | synchronous                                    |
-    | Reset State        | start                                          |
-    | Power Up State     | start                                          |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 16-bit register for signal <DAT_O<15:0>>.
-    Found 1-bit register for signal <async_wr>.
-    Found 1-bit register for signal <async_rst>.
-    Found 4-bit register for signal <async_a>.
-    Found 16-bit tristate buffer for signal <async_d>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 1-bit register for signal <async_be<0>>.
-    Found 1-bit register for signal <async_cs>.
-    Found 1-bit register for signal <async_rd>.
-    Found 5-bit down counter for signal <cycle_cnt>.
-    Found 16-bit register for signal <DAT_I_r>.
-    Found 16-bit register for signal <Mtridata_async_d> created at line 310.
-    Found 1-bit register for signal <Mtrien_async_d> created at line 310.
-    Found 1-bit register for signal <rdyo>.
-    Found 1-bit register for signal <WE_I_r>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 Counter(s).
-	inferred  61 D-type flip-flop(s).
-	inferred  16 Tristate(s).
-Unit <async_port_wb_2> synthesized.
-
-
-Synthesizing Unit <fifo_sync_ctrl_1>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
-WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 1-bit register for signal <fifo_afull>.
-    Found 6-bit updown counter for signal <diff>.
-    Found 1-bit register for signal <empty>.
-    Found 6-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
-    Found 6-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
-    Found 1-bit register for signal <full>.
-    Found 5-bit register for signal <pR>.
-    Found 5-bit adder for signal <pR_next$addsub0000> created at line 192.
-    Found 5-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
-    Found 5-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
-    Found 5-bit register for signal <pW>.
-    Found 5-bit adder for signal <pW_next$addsub0000> created at line 174.
-    Found 1-bit register for signal <was_write>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  15 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <fifo_sync_ctrl_1> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_1>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 32x30-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 30-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  30 D-type flip-flop(s).
-Unit <dpram_1w1r_1> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_2>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 32x72-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 72-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  72 D-type flip-flop(s).
-Unit <dpram_1w1r_2> synthesized.
-
-
-Synthesizing Unit <gray_counter_1>.
-    Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd".
-    Found 6-bit register for signal <cntb>.
-    Found 6-bit register for signal <cntg>.
-    Found 6-bit adder for signal <nxtb$addsub0000> created at line 78.
-    Found 1-bit xor2 for signal <nxtg$xor0000> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0001> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0002> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0003> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0004> created at line 48.
-    Summary:
-	inferred  12 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <gray_counter_1> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_3>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 32x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 64-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  64 D-type flip-flop(s).
-Unit <dpram_1w1r_3> synthesized.
-
-
-Synthesizing Unit <sdram_ctrl>.
-    Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd".
-WARNING:Xst:646 - Signal <row_addr_last<10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <col_addr_last> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_2> for signal <st_ctrl>.
-    -----------------------------------------------------------------------
-    | States             | 13                                             |
-    | Transitions        | 37                                             |
-    | Inputs             | 12                                             |
-    | Outputs            | 15                                             |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | reset                                          |
-    | Power Up State     | reset                                          |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 15x27-bit ROM for signal <$rom0000>.
-    Found 4-bit register for signal <bank_active_reg>.
-    Found 2-bit register for signal <bank_addr_last>.
-    Found 2-bit register for signal <bank_addr_reg>.
-    Found 1-bit 4-to-1 multiplexer for signal <bank_is_active>.
-    Found 9-bit register for signal <col_addr_reg>.
-    Found 8-bit down counter for signal <cycle_cnt>.
-    Found 1-bit register for signal <cycle_finished>.
-    Found 15-bit down counter for signal <pwr_up_cnt>.
-    Found 1-bit register for signal <pwr_up_finished>.
-    Found 10-bit down counter for signal <refresh_cnt>.
-    Found 1-bit register for signal <refresh_request>.
-    Found 13-bit register for signal <row_addr_last>.
-    Found 13-bit register for signal <row_addr_reg>.
-    Found 5-bit up counter for signal <seq_cnt>.
-    Found 13-bit comparator not equal for signal <st_ctrl$cmp_ne0000> created at line 264.
-    Found 4-bit register for signal <u_tag_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 ROM(s).
-	inferred   4 Counter(s).
-	inferred  50 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-	inferred   1 Multiplexer(s).
-Unit <sdram_ctrl> synthesized.
-
-
-Synthesizing Unit <sdram_cmd>.
-    Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd".
-INFO:Xst:1799 - State write_a is never reached in FSM <st_sdr>.
-INFO:Xst:1799 - State read_a is never reached in FSM <st_sdr>.
-INFO:Xst:1799 - State burst_stop is never reached in FSM <st_sdr>.
-INFO:Xst:1799 - State self_ref is never reached in FSM <st_sdr>.
-INFO:Xst:1799 - State pre_pwr_down is never reached in FSM <st_sdr>.
-INFO:Xst:1799 - State act_pwr_down is never reached in FSM <st_sdr>.
-    Found finite state machine <FSM_3> for signal <st_sdr>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 28                                             |
-    | Inputs             | 10                                             |
-    | Outputs            | 5                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | pwr_down                                       |
-    | Power Up State     | pwr_down                                       |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 10x4-bit ROM for signal <$mux0000> created at line 98.
-    Found 2-bit register for signal <burst_cnt>.
-    Found 2-bit subtractor for signal <burst_cnt$addsub0000> created at line 281.
-    Found 1-bit register for signal <burst_finished>.
-    Found 4-bit down counter for signal <cycle_cnt>.
-    Found 1-bit register for signal <cycle_finished>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 ROM(s).
-	inferred   1 Counter(s).
-	inferred   4 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <sdram_cmd> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_9>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 32x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 32-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  32 D-type flip-flop(s).
-Unit <dpram_1w1r_9> synthesized.
-
-
-Synthesizing Unit <vga_sync_1>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd".
-    Found finite state machine <FSM_4> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 5                                              |
-    | Transitions        | 9                                              |
-    | Inputs             | 4                                              |
-    | Outputs            | 5                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Clock enable       | ce (positive)                                  |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | st_init                                        |
-    | Power Up State     | st_init                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 10-bit up counter for signal <count>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 Counter(s).
-Unit <vga_sync_1> synthesized.
-
-
-Synthesizing Unit <vga_sync_2>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd".
-    Found finite state machine <FSM_5> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 5                                              |
-    | Transitions        | 9                                              |
-    | Inputs             | 4                                              |
-    | Outputs            | 5                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Clock enable       | ce (positive)                                  |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | st_init                                        |
-    | Power Up State     | st_init                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 10-bit up counter for signal <count>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 Counter(s).
-Unit <vga_sync_2> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_4>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 2048x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 64-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  64 D-type flip-flop(s).
-Unit <dpram_1w1r_4> synthesized.
-
-
-Synthesizing Unit <gray_counter_2>.
-    Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd".
-    Found 12-bit register for signal <cntb>.
-    Found 12-bit register for signal <cntg>.
-    Found 12-bit adder for signal <nxtb$addsub0000> created at line 78.
-    Found 1-bit xor2 for signal <nxtg$xor0000> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0001> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0002> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0003> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0004> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0005> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0006> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0007> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0008> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0009> created at line 48.
-    Found 1-bit xor2 for signal <nxtg$xor0010> created at line 48.
-    Summary:
-	inferred  24 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <gray_counter_2> synthesized.
-
-
-Synthesizing Unit <fifo_sync_ctrl_2>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
-WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 1-bit register for signal <fifo_afull>.
-    Found 10-bit updown counter for signal <diff>.
-    Found 1-bit register for signal <empty>.
-    Found 10-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
-    Found 10-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
-    Found 1-bit register for signal <full>.
-    Found 9-bit register for signal <pR>.
-    Found 9-bit adder for signal <pR_next$addsub0000> created at line 192.
-    Found 9-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
-    Found 9-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
-    Found 9-bit register for signal <pW>.
-    Found 9-bit adder for signal <pW_next$addsub0000> created at line 174.
-    Found 1-bit register for signal <was_write>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  23 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <fifo_sync_ctrl_2> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_5>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 512x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 64-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  64 D-type flip-flop(s).
-Unit <dpram_1w1r_5> synthesized.
-
-
-Synthesizing Unit <fifo_sync_ctrl_3>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
-WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 3-bit updown counter for signal <diff>.
-    Found 1-bit register for signal <empty>.
-    Found 3-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
-    Found 1-bit register for signal <full>.
-    Found 2-bit register for signal <pR>.
-    Found 2-bit adder for signal <pR_next$addsub0000> created at line 192.
-    Found 2-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
-    Found 2-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
-    Found 2-bit register for signal <pW>.
-    Found 2-bit adder for signal <pW_next$addsub0000> created at line 174.
-    Found 1-bit register for signal <was_write>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred   8 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   3 Comparator(s).
-Unit <fifo_sync_ctrl_3> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_6>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 4x105-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 105-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred 105 D-type flip-flop(s).
-Unit <dpram_1w1r_6> synthesized.
-
-
-Synthesizing Unit <char_rom>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd".
-    Found 4096x8-bit ROM for signal <DATA$rom0000> created at line 4378.
-    Found 8-bit register for signal <DATA>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <char_rom> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_7>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 4096x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 8-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <dpram_1w1r_7> synthesized.
-
-
-Synthesizing Unit <fifo_sync_ctrl_4>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd".
-WARNING:Xst:1780 - Signal <pW_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <pR_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 1-bit register for signal <fifo_afull>.
-    Found 9-bit updown counter for signal <diff>.
-    Found 1-bit register for signal <empty>.
-    Found 9-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 104.
-    Found 9-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 90.
-    Found 1-bit register for signal <full>.
-    Found 8-bit register for signal <pR>.
-    Found 8-bit adder for signal <pR_next$addsub0000> created at line 192.
-    Found 8-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 140.
-    Found 8-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 135.
-    Found 8-bit register for signal <pW>.
-    Found 8-bit adder for signal <pW_next$addsub0000> created at line 174.
-    Found 1-bit register for signal <was_write>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  21 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <fifo_sync_ctrl_4> synthesized.
-
-
-Synthesizing Unit <dpram_1w1r_8>.
-    Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd".
-    Found 256x18-bit dual-port RAM <Mram_RAM> for signal <RAM>.
-    Found 18-bit register for signal <dout_b>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred  18 D-type flip-flop(s).
-Unit <dpram_1w1r_8> synthesized.
-
-
-Synthesizing Unit <singleshot_1>.
-    Related source file is "W:/vhdl/lib/misc/singleshot.vhd".
-    Found finite state machine <FSM_6> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 1                                              |
-    | Outputs            | 1                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | synchronous                                    |
-    | Reset State        | idle                                           |
-    | Power Up State     | idle                                           |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Summary:
-	inferred   1 Finite State Machine(s).
-Unit <singleshot_1> synthesized.
-
-
-Synthesizing Unit <singleshot_2>.
-    Related source file is "W:/vhdl/lib/misc/singleshot.vhd".
-    Found finite state machine <FSM_7> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 1                                              |
-    | Outputs            | 1                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | synchronous                                    |
-    | Reset State        | idle                                           |
-    | Power Up State     | idle                                           |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Summary:
-	inferred   1 Finite State Machine(s).
-Unit <singleshot_2> synthesized.
-
-
-Synthesizing Unit <ps2_core>.
-    Related source file is "W:/vhdl/lib/ps2_port/src/ps2_core.vhd".
-WARNING:Xst:646 - Signal <tx_rdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <rx_err> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-INFO:Xst:1799 - State tx_start_latency_st is never reached in FSM <write_cs>.
-INFO:Xst:1799 - State tx_stop_sample_st is never reached in FSM <write_cs>.
-    Found finite state machine <FSM_8> for signal <write_cs>.
-    -----------------------------------------------------------------------
-    | States             | 18                                             |
-    | Transitions        | 41                                             |
-    | Inputs             | 5                                              |
-    | Outputs            | 30                                             |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | synchronous                                    |
-    | Reset State        | tx_idle_st                                     |
-    | Power Up State     | tx_idle_st                                     |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found finite state machine <FSM_9> for signal <read_cs>.
-    -----------------------------------------------------------------------
-    | States             | 14                                             |
-    | Transitions        | 38                                             |
-    | Inputs             | 6                                              |
-    | Outputs            | 8                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | synchronous                                    |
-    | Reset State        | start_wait_st                                  |
-    | Power Up State     | start_wait_st                                  |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <rx_err_flag>.
-    Found 1-bit register for signal <tx_empty>.
-    Found 1-bit register for signal <ps2_data_tx>.
-    Found 1-bit register for signal <rx_err_par>.
-    Found 1-bit register for signal <ps2_clk_tx>.
-    Found 8-bit register for signal <dout>.
-    Found 7-bit down counter for signal <cnt_prescaler>.
-    Found 3-bit down counter for signal <data_cnt>.
-    Found 3-bit down counter for signal <data_cnt_tx>.
-    Found 1-bit register for signal <en_us>.
-    Found 1-bit register for signal <parity_rx>.
-    Found 1-bit register for signal <parity_tx>.
-    Found 8-bit register for signal <piso_reg>.
-    Found 1-bit register for signal <rx_full>.
-    Found 8-bit register for signal <sipo_reg>.
-    Found 14-bit down counter for signal <timeout_count_rx>.
-    Found 14-bit down counter for signal <timeout_count_tx>.
-    Found 1-bit register for signal <timeout_rx_flag>.
-    Found 1-bit register for signal <timeout_tx_flag>.
-    Found 8-bit register for signal <tx_reg>.
-    Found 1-bit register for signal <tx_req>.
-    Summary:
-	inferred   2 Finite State Machine(s).
-	inferred   5 Counter(s).
-	inferred  44 D-type flip-flop(s).
-Unit <ps2_core> synthesized.
-
-
-Synthesizing Unit <debounce>.
-    Related source file is "W:/vhdl/lib/ps2_port/src/debounce.vhd".
-    Found finite state machine <FSM_10> for signal <debounce_cs>.
-    -----------------------------------------------------------------------
-    | States             | 3                                              |
-    | Transitions        | 7                                              |
-    | Inputs             | 3                                              |
-    | Outputs            | 2                                              |
-    | Clock              | clk (rising_edge)                              |
-    | Clock enable       | rst (negative)                                 |
-    | Power Up State     | init_st                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <output>.
-    Found 3-bit register for signal <count>.
-    Found 3-bit subtractor for signal <count$addsub0000> created at line 59.
-    Found 1-bit register for signal <input_last>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   5 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <debounce> synthesized.
-
-
-Synthesizing Unit <clockgen>.
-    Related source file is "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd".
-    Found 1-bit register for signal <sys_rst_out>.
-    Found 5-bit down counter for signal <reset_cnt>.
-    Found 20-bit register for signal <reset_pipe0>.
-    Found 20-bit register for signal <reset_pipe1>.
-    Found 20-bit register for signal <reset_pipe2>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  61 D-type flip-flop(s).
-Unit <clockgen> synthesized.
-
-
-Synthesizing Unit <ps2_wb>.
-    Related source file is "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd".
-WARNING:Xst:647 - Input <DAT_I<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 16-bit register for signal <DAT_O<15:0>>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 1-bit register for signal <INT_O>.
-    Found 1-bit register for signal <irq_rx>.
-    Found 1-bit register for signal <irq_tx>.
-    Found 8-bit register for signal <reg_ps2_tx>.
-    Found 1-bit register for signal <reg_re_ps2_rx>.
-    Found 1-bit register for signal <reg_we_ps2_tx>.
-    Found 1-bit register for signal <rx_int_en>.
-    Found 1-bit register for signal <stat_clk>.
-    Found 1-bit register for signal <stat_data>.
-    Found 1-bit register for signal <tx_int_en>.
-    Summary:
-	inferred  34 D-type flip-flop(s).
-Unit <ps2_wb> synthesized.
-
-
-Synthesizing Unit <ps2_phy>.
-    Related source file is "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd".
-Unit <ps2_phy> synthesized.
-
-
-Synthesizing Unit <rom>.
-    Related source file is "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd".
-WARNING:Xst:647 - Input <addr<31:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <jtag_ld_addr<15:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <bs_capture> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 2048x32-bit dual-port RAM <Mram_word_array> for signal <word_array>.
-    Found 32-bit register for signal <dout>.
-    Found 32-bit register for signal <jtag_ld_dout>.
-    Found 48-bit register for signal <user_regi>.
-    Found 48-bit register for signal <user_rego>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred 160 D-type flip-flop(s).
-Unit <rom> synthesized.
-
-
-Synthesizing Unit <kcuart_tx>.
-    Related source file is "W:/vhdl/lib/uart/kcuart_tx.vhd".
-Unit <kcuart_tx> synthesized.
-
-
-Synthesizing Unit <bbfifo_16x8>.
-    Related source file is "W:/vhdl/lib/uart/bbfifo_16x8.vhd".
-Unit <bbfifo_16x8> synthesized.
-
-
-Synthesizing Unit <kcuart_rx>.
-    Related source file is "W:/vhdl/lib/uart/kcuart_rx.vhd".
-Unit <kcuart_rx> synthesized.
-
-
-Synthesizing Unit <fifo_sync_1>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_sync_1> synthesized.
-
-
-Synthesizing Unit <fifo_async_ctrl_1>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd".
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 1-bit register for signal <fifo_afull>.
-    Found 6-bit register for signal <bcnt2_ar>.
-    Found 6-bit register for signal <bcnt2_aw>.
-    Found 6-bit register for signal <diff>.
-    Found 6-bit adder for signal <diff$addsub0000>.
-    Found 6-bit subtractor for signal <diff$sub0000> created at line 189.
-    Found 6-bit register for signal <diff0>.
-    Found 6-bit adder for signal <diff0$addsub0000>.
-    Found 6-bit subtractor for signal <diff0$sub0000> created at line 209.
-    Found 1-bit register for signal <empty>.
-    Found 6-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 204.
-    Found 6-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 184.
-    Found 1-bit register for signal <full>.
-    Found 6-bit register for signal <gcnt2_r>.
-    Found 6-bit register for signal <gcnt2_w>.
-    Found 6-bit register for signal <p1>.
-    Found 6-bit register for signal <p10>.
-    Found 6-bit register for signal <p11>.
-    Found 6-bit register for signal <p12>.
-    Found 6-bit register for signal <p2>.
-    Found 6-bit register for signal <p20>.
-    Found 6-bit register for signal <p21>.
-    Found 6-bit register for signal <p22>.
-    Found 6-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 144.
-    Found 6-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 134.
-    Summary:
-	inferred  88 D-type flip-flop(s).
-	inferred   4 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <fifo_async_ctrl_1> synthesized.
-
-
-Synthesizing Unit <ddr_phy>.
-    Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd".
-    Found 4-bit register for signal <u_tag_wr>.
-    Found 13-bit register for signal <part_addr>.
-    Found 1-bit register for signal <part_we_n>.
-    Found 1-bit register for signal <part_ras_n>.
-    Found 4-bit tristate buffer for signal <part_dqs>.
-    Found 2-bit register for signal <part_ba>.
-    Found 1-bit register for signal <part_cas_n>.
-    Found 1-bit register for signal <sdr_data_req_w>.
-    Found 64-bit register for signal <sdr_data_r>.
-    Found 4-bit register for signal <u_tag_rd>.
-    Found 32-bit tristate buffer for signal <part_data>.
-    Found 1-bit register for signal <sdr_data_vld>.
-    Found 1-bit register for signal <part_cke>.
-    Found 1-bit register for signal <part_cs_n>.
-    Found 64-bit register for signal <data_reg_r>.
-    Found 1-bit register for signal <dqs_rst>.
-    Found 4-bit register for signal <dqs_zen>.
-    Found 1-bit register for signal <drive>.
-    Found 32-bit register for signal <drive270>.
-    Found 2-bit register for signal <p>.
-    Found 4-bit register for signal <p0>.
-    Found 13-bit register for signal <part_ctrl_reg.addr>.
-    Found 2-bit register for signal <part_ctrl_reg.ba>.
-    Found 1-bit register for signal <part_ctrl_reg.cke>.
-    Found 1-bit register for signal <part_ctrl_reg.cmd.cas_n>.
-    Found 1-bit register for signal <part_ctrl_reg.cmd.cs_n>.
-    Found 1-bit register for signal <part_ctrl_reg.cmd.ras_n>.
-    Found 1-bit register for signal <part_ctrl_reg.cmd.we_n>.
-    Found 1-bit register for signal <read_en>.
-    Found 20-bit register for signal <u_tag_pipe>.
-    Found 1-bit register for signal <we_reg>.
-    Summary:
-	inferred 244 D-type flip-flop(s).
-	inferred  36 Tristate(s).
-Unit <ddr_phy> synthesized.
-
-
-Synthesizing Unit <fifo_sync_2>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_sync_2> synthesized.
-
-
-Synthesizing Unit <fifo_sync_3>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_sync_3> synthesized.
-
-
-Synthesizing Unit <char_gen>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd".
-    Found 32x12-bit ROM for signal <a_addr_rd$rom0000> created at line 99.
-    Found 32x8-bit ROM for signal <cursor_rom_data$rom0000> created at line 451.
-    Found 32x12-bit ROM for signal <line_addr$rom0000> created at line 99.
-    Found finite state machine <FSM_11> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 8                                              |
-    | Inputs             | 4                                              |
-    | Outputs            | 5                                              |
-    | Clock              | sys_clk (rising_edge)                          |
-    | Reset              | rst (positive)                                 |
-    | Reset type         | synchronous                                    |
-    | Reset State        | cg_init                                        |
-    | Power Up State     | cg_init                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <char_draw_en>.
-    Found 8-bit register for signal <dout>.
-    Found 12-bit adder for signal <a_addr_rd>.
-    Found 12-bit adder for signal <a_addr_wr$addsub0000> created at line 267.
-    Found 12-bit adder for signal <a_addr_wr$addsub0001> created at line 245.
-    Found 12-bit up counter for signal <a_cnt>.
-    Found 12-bit comparator greatequal for signal <a_cnt$cmp_ge0000> created at line 304.
-    Found 8-bit register for signal <a_data_reg>.
-    Found 8-bit comparator less for signal <a_data_reg$cmp_lt0000> created at line 330.
-    Found 8-bit subtractor for signal <a_data_reg$sub0000> created at line 338.
-    Found 1-bit register for signal <a_data_we>.
-    Found 7-bit up counter for signal <cell_x_cnt>.
-    Found 7-bit comparator greatequal for signal <cell_x_cnt$cmp_ge0000> created at line 518.
-    Found 5-bit register for signal <cell_y_cnt>.
-    Found 5-bit adder for signal <cell_y_cnt$addsub0000> created at line 527.
-    Found 5-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0000> created at line 526.
-    Found 4-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0001> created at line 522.
-    Found 3-bit comparator greatequal for signal <cell_y_cnt$cmp_ge0002> created at line 514.
-    Found 5-bit comparator less for signal <cell_y_cnt$cmp_lt0000> created at line 526.
-    Found 1-bit register for signal <char_en>.
-    Found 1-bit register for signal <char_en2>.
-    Found 8-bit register for signal <char_reg>.
-    Found 1-bit xor2 for signal <char_reg_0$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_1$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_2$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_3$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_4$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_5$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_6$xor0000> created at line 473.
-    Found 1-bit xor2 for signal <char_reg_7$xor0000> created at line 473.
-    Found 4-bit register for signal <char_rom_row>.
-    Found 3-bit register for signal <char_x_cnt>.
-    Found 3-bit adder for signal <char_x_cnt$addsub0000> created at line 515.
-    Found 3-bit comparator less for signal <char_x_cnt$cmp_lt0000> created at line 514.
-    Found 4-bit up counter for signal <char_y_cnt>.
-    Found 4-bit comparator less for signal <char_y_cnt$cmp_lt0000> created at line 522.
-    Found 7-bit comparator less for signal <char_y_cnt$cmp_lt0001> created at line 518.
-    Found 7-bit register for signal <csr_posx_cnt_din>.
-    Found 1-bit register for signal <csr_posx_cnt_en>.
-    Found 1-bit register for signal <csr_posx_cnt_set>.
-    Found 1-bit register for signal <csr_posx_overflow>.
-    Found 7-bit comparator less for signal <csr_posx_overflow$cmp_lt0000> created at line 356.
-    Found 7-bit up counter for signal <csr_posx_reg>.
-    Found 7-bit comparator greatequal for signal <csr_posx_reg$cmp_ge0000> created at line 356.
-    Found 7-bit register for signal <csr_posx_synced>.
-    Found 5-bit register for signal <csr_posy_cnt_din>.
-    Found 1-bit register for signal <csr_posy_cnt_en>.
-    Found 8-bit comparator greatequal for signal <csr_posy_cnt_en$cmp_ge0000> created at line 330.
-    Found 1-bit register for signal <csr_posy_cnt_set>.
-    Found 1-bit register for signal <csr_posy_overflow>.
-    Found 5-bit comparator less for signal <csr_posy_overflow$cmp_lt0000> created at line 376.
-    Found 5-bit up counter for signal <csr_posy_reg>.
-    Found 5-bit comparator greatequal for signal <csr_posy_reg$cmp_ge0000> created at line 376.
-    Found 5-bit register for signal <csr_posy_synced>.
-    Found 5-bit up counter for signal <cursor_cnt>.
-    Found 8-bit register for signal <cursor_rom_data>.
-    Found 7-bit comparator equal for signal <cursor_rom_data$cmp_eq0000> created at line 450.
-    Found 5-bit comparator equal for signal <cursor_rom_data$cmp_eq0001> created at line 450.
-    Found 1-bit register for signal <cursor_visible>.
-    Found 5-bit comparator less for signal <cursor_visible$cmp_lt0000> created at line 436.
-    Found 1-bit register for signal <enable_x>.
-    Found 1-bit register for signal <enable_y>.
-    Found 5-bit register for signal <line_offset>.
-    Found 5-bit adder for signal <line_offset$addsub0000> created at line 532.
-    Found 5-bit comparator less for signal <line_offset$cmp_lt0000> created at line 531.
-    Found 7-bit register for signal <p1>.
-    Found 5-bit register for signal <p10>.
-    Found 7-bit register for signal <p2>.
-    Found 5-bit register for signal <p20>.
-    Found 1-bit register for signal <scroll_active>.
-    Found 5-bit register for signal <scroll_offset>.
-    Found 5-bit adder for signal <scroll_offset$addsub0000> created at line 399.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   3 ROM(s).
-	inferred   6 Counter(s).
-	inferred 116 D-type flip-flop(s).
-	inferred   8 Adder/Subtractor(s).
-	inferred  19 Comparator(s).
-Unit <char_gen> synthesized.
-
-
-Synthesizing Unit <vga_timing>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd".
-Unit <vga_timing> synthesized.
-
-
-Synthesizing Unit <fifo_async_ctrl_2>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd".
-    Found 1-bit register for signal <fifo_aempty>.
-    Found 1-bit register for signal <fifo_afull>.
-    Found 12-bit register for signal <bcnt2_ar>.
-    Found 12-bit register for signal <bcnt2_aw>.
-    Found 12-bit register for signal <diff>.
-    Found 12-bit adder for signal <diff$addsub0000>.
-    Found 12-bit subtractor for signal <diff$sub0000> created at line 189.
-    Found 12-bit register for signal <diff0>.
-    Found 12-bit adder for signal <diff0$addsub0000>.
-    Found 12-bit subtractor for signal <diff0$sub0000> created at line 209.
-    Found 1-bit register for signal <empty>.
-    Found 12-bit comparator lessequal for signal <fifo_aempty$cmp_le0000> created at line 204.
-    Found 12-bit comparator greatequal for signal <fifo_afull$cmp_ge0000> created at line 184.
-    Found 1-bit register for signal <full>.
-    Found 12-bit register for signal <gcnt2_r>.
-    Found 12-bit register for signal <gcnt2_w>.
-    Found 12-bit register for signal <p1>.
-    Found 12-bit register for signal <p10>.
-    Found 12-bit register for signal <p11>.
-    Found 12-bit register for signal <p12>.
-    Found 12-bit register for signal <p2>.
-    Found 12-bit register for signal <p20>.
-    Found 12-bit register for signal <p21>.
-    Found 12-bit register for signal <p22>.
-    Found 12-bit comparator equal for signal <pre_empty$cmp_eq0000> created at line 144.
-    Found 12-bit comparator equal for signal <pre_full$cmp_eq0000> created at line 134.
-    Summary:
-	inferred 172 D-type flip-flop(s).
-	inferred   4 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <fifo_async_ctrl_2> synthesized.
-
-
-Synthesizing Unit <fifo_sync_4>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_sync_4> synthesized.
-
-
-Synthesizing Unit <ac_in>.
-    Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd".
-WARNING:Xst:646 - Signal <tag<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <last_slot> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_12> for signal <sac>.
-    -----------------------------------------------------------------------
-    | States             | 3                                              |
-    | Transitions        | 9                                              |
-    | Inputs             | 5                                              |
-    | Outputs            | 3                                              |
-    | Clock              | ac_bit_clk (rising_edge)                       |
-    | Reset              | ac_reset (positive)                            |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | ac_idle                                        |
-    | Power Up State     | ac_idle                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 13-bit register for signal <slot_valid>.
-    Found 1-bit register for signal <sync_status>.
-    Found 20-bit register for signal <stat_data>.
-    Found 20-bit register for signal <stat_addr>.
-    Found 5-bit up counter for signal <bitcnt>.
-    Found 240-bit register for signal <data_array>.
-    Found 4-bit comparator greater for signal <pcm_out_data$cmp_gt0000> created at line 127.
-    Found 20-bit register for signal <rx_reg>.
-    Found 4-bit up counter for signal <slotcnt>.
-    Found 1-bit register for signal <stat_read>.
-    Found 16-bit register for signal <tag>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   2 Counter(s).
-	inferred 331 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-Unit <ac_in> synthesized.
-
-
-Synthesizing Unit <ac_out>.
-    Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd".
-    Found finite state machine <FSM_13> for signal <sac>.
-    -----------------------------------------------------------------------
-    | States             | 3                                              |
-    | Transitions        | 6                                              |
-    | Inputs             | 3                                              |
-    | Outputs            | 3                                              |
-    | Clock              | ac_bit_clk (rising_edge)                       |
-    | Reset              | ac_reset (positive)                            |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | ac_idle                                        |
-    | Power Up State     | ac_idle                                        |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <ac_ssync>.
-    Found 1-bit register for signal <ac_sdata_out>.
-    Found 5-bit up counter for signal <bitcnt>.
-    Found 240-bit register for signal <data_array>.
-    Found 1-bit register for signal <last_slot>.
-    Found 12-bit register for signal <slot_valid>.
-    Found 4-bit up counter for signal <slotcnt>.
-    Found 20-bit register for signal <tx_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   2 Counter(s).
-	inferred 275 D-type flip-flop(s).
-Unit <ac_out> synthesized.
-
-
-Synthesizing Unit <rom_wb>.
-    Related source file is "W:/vhdl/lib/misc/rom_wb.vhd".
-    Found 1-bit register for signal <ACK_O>.
-    Summary:
-	inferred   1 D-type flip-flop(s).
-Unit <rom_wb> synthesized.
-
-
-Synthesizing Unit <uart_tx>.
-    Related source file is "W:/vhdl/lib/uart/uart_tx.vhd".
-Unit <uart_tx> synthesized.
-
-
-Synthesizing Unit <uart_rx>.
-    Related source file is "W:/vhdl/lib/uart/uart_rx.vhd".
-Unit <uart_rx> synthesized.
-
-
-Synthesizing Unit <fifo_async_1>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_async_1> synthesized.
-
-
-Synthesizing Unit <fifo_async_2>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_async_2> synthesized.
-
-
-Synthesizing Unit <fifo_async_4>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_async_4> synthesized.
-
-
-Synthesizing Unit <vga_backend>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd".
-WARNING:Xst:647 - Input <color_op> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <color_in<0><3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <color_in<1><3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <sys_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 8-bit register for signal <vga_blue>.
-    Found 1-bit register for signal <vga_hsync>.
-    Found 8-bit register for signal <vga_red>.
-    Found 1-bit register for signal <vga_vsync>.
-    Found 8-bit register for signal <vga_green>.
-    Found 1-bit register for signal <hsync_r>.
-    Found 1-bit register for signal <scan_enable>.
-    Found 1-bit register for signal <vsync_r>.
-    Summary:
-	inferred  29 D-type flip-flop(s).
-Unit <vga_backend> synthesized.
-
-
-Synthesizing Unit <fifo_async_3>.
-    Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd".
-WARNING:Xst:646 - Signal <pre_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pre_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <fifo_async_3> synthesized.
-
-
-Synthesizing Unit <ac_io>.
-    Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd".
-    Found 1-bit register for signal <ac_reset_n>.
-    Found 1-bit register for signal <ac_reset>.
-    Found 10-bit down counter for signal <cnt>.
-    Found 10-bit subtractor for signal <cnt$addsub0000> created at line 165.
-    Found 1-bit register for signal <rstate<0>>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred   3 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <ac_io> synthesized.
-
-
-Synthesizing Unit <uart_wb>.
-    Related source file is "W:/vhdl/lib/uart/uart_wb.vhd".
-WARNING:Xst:647 - Input <DAT_I<31:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<31:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <tx_complete> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 16-bit register for signal <DAT_O<15:0>>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 16-bit up counter for signal <baud_count>.
-    Found 16-bit comparator equal for signal <baud_count$cmp_eq0000> created at line 162.
-    Found 1-bit register for signal <en_16_x_baud>.
-    Found 1-bit register for signal <irq_rx>.
-    Found 1-bit register for signal <irq_tx>.
-    Found 1-bit register for signal <reg_re_uart_rx>.
-    Found 16-bit register for signal <reg_uart_baud>.
-    Found 8-bit register for signal <reg_uart_tx>.
-    Found 1-bit register for signal <reg_we_uart_tx>.
-    Found 1-bit register for signal <rx_int_en>.
-    Found 1-bit register for signal <tx_int_en>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  48 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-Unit <uart_wb> synthesized.
-
-
-Synthesizing Unit <vga_frontend64>.
-    Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd".
-WARNING:Xst:647 - Input <SEL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <stat_vsync> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <stat_vscan> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <stat_hsync> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <stat_hscan> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <odd_pixel<9:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <blitfifo_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <back> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
-    Found finite state machine <FSM_14> for signal <s>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 22                                             |
-    | Inputs             | 10                                             |
-    | Outputs            | 9                                              |
-    | Clock              | CLK_I (rising_edge)                            |
-    | Reset              | RST_I (positive)                               |
-    | Reset type         | synchronous                                    |
-    | Reset State        | init                                           |
-    | Power Up State     | init                                           |
-    | Encoding           | automatic                                      |
-    | Implementation     | LUT                                            |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <ACK_O>.
-    Found 1-bit register for signal <INT_O>.
-    Found 32-bit register for signal <SDAT_O>.
-    Found 32-bit adder for signal <ADDR_O_blit_dst>.
-    Found 32-bit adder for signal <ADDR_O_blit_src>.
-    Found 32-bit adder for signal <ADDR_O_scan>.
-    Found 32-bit register for signal <blit_addr_dst>.
-    Found 32-bit register for signal <blit_addr_src_0>.
-    Found 32-bit register for signal <blit_addr_src_1>.
-    Found 9-bit down counter for signal <blit_chunk_cnt>.
-    Found 4-bit register for signal <blit_comb_sel>.
-    Found 1-bit register for signal <blit_complete>.
-    Found 1-bit register for signal <blit_complete_ack>.
-    Found 1-bit register for signal <blit_complete_inten>.
-    Found 32-bit register for signal <blit_dimx_dst>.
-    Found 32-bit register for signal <blit_dimx_src_0>.
-    Found 32-bit register for signal <blit_dimx_src_1>.
-    Found 32-bit register for signal <blit_dst_cnt_x>.
-    Found 32-bit adder for signal <blit_dst_cnt_x$addsub0000> created at line 640.
-    Found 32-bit comparator equal for signal <blit_dst_cnt_x$cmp_eq0000> created at line 639.
-    Found 32-bit comparator not equal for signal <blit_dst_cnt_x$cmp_ne0000> created at line 639.
-    Found 32-bit up counter for signal <blit_dst_cnt_y>.
-    Found 1-bit register for signal <blit_dst_finish>.
-    Found 32-bit comparator not equal for signal <blit_dst_finish$cmp_ne0000> created at line 643.
-    Found 32-bit up accumulator for signal <blit_dst_off_y>.
-    Found 32-bit comparator equal for signal <blit_dst_off_y$cmp_eq0000> created at line 643.
-    Found 32-bit register for signal <blit_dst_offset>.
-    Found 32-bit adder for signal <blit_dst_offset$addsub0000> created at line 641.
-    Found 4-bit register for signal <blit_func_sel>.
-    Found 32-bit register for signal <blit_nx>.
-    Found 32-bit register for signal <blit_ny>.
-    Found 1-bit register for signal <blit_request>.
-    Found 1-bit register for signal <blit_request_set>.
-    Found 32-bit register for signal <blit_src_cnt_x>.
-    Found 32-bit adder for signal <blit_src_cnt_x$addsub0000> created at line 610.
-    Found 32-bit comparator equal for signal <blit_src_cnt_x$cmp_eq0000> created at line 609.
-    Found 32-bit comparator not equal for signal <blit_src_cnt_x$cmp_ne0000> created at line 609.
-    Found 32-bit up counter for signal <blit_src_cnt_y>.
-    Found 1-bit register for signal <blit_src_finish>.
-    Found 32-bit comparator not equal for signal <blit_src_finish$cmp_ne0000> created at line 613.
-    Found 32-bit up accumulator for signal <blit_src_off_y>.
-    Found 32-bit comparator equal for signal <blit_src_off_y$cmp_eq0000> created at line 613.
-    Found 32-bit register for signal <blit_src_offset>.
-    Found 32-bit adder for signal <blit_src_offset$addsub0000> created at line 611.
-    Found 1-bit register for signal <bufchg>.
-    Found 1-bit register for signal <bufchg_flag>.
-    Found 1-bit register for signal <bufchg_flag_ack>.
-    Found 1-bit register for signal <bufchg_irq_en>.
-    Found 1-bit register for signal <bus_read_fin>.
-    Found 29-bit comparator equal for signal <bus_read_fin$cmp_eq0000> created at line 550.
-    Found 1-bit register for signal <cg_ascii_we>.
-    Found 1-bit register for signal <cg_clr_line>.
-    Found 1-bit register for signal <cg_clr_screen>.
-    Found 32-bit register for signal <cg_color>.
-    Found 8-bit register for signal <cg_din>.
-    Found 1-bit register for signal <cg_posx_we>.
-    Found 1-bit register for signal <cg_posy_we>.
-    Found 32-bit register for signal <front>.
-    Found 32-bit register for signal <host_blit_nx>.
-    Found 32-bit register for signal <host_fb_back>.
-    Found 32-bit register for signal <host_fb_front>.
-    Found 18-bit up counter for signal <pixel_cnt>.
-    Found 29-bit up counter for signal <read_cnt>.
-    Found 29-bit up counter for signal <request_cnt>.
-    Found 32-bit register for signal <vga_fb_back>.
-    Found 32-bit register for signal <vga_fb_front>.
-    Found 1-bit register for signal <vga_scan_dma_en>.
-    Found 1-bit register for signal <vga_scan_dma_en2>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   6 Counter(s).
-	inferred   2 Accumulator(s).
-	inferred 677 D-type flip-flop(s).
-	inferred   7 Adder/Subtractor(s).
-	inferred   9 Comparator(s).
-Unit <vga_frontend64> synthesized.
-
-
-Synthesizing Unit <ac97_wb>.
-    Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd".
-WARNING:Xst:647 - Input <MRDY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <tx_fifo_almost_empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <rx_state_n> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <rx_state> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <rx_fifo_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <request<5:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <data_reg<31:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <addr_reg<31:10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <addr_reg<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ac_stat_data<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ac_stat_addr<19:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ac_stat_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ac_slot_valid<5:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ac_rx_pcm_data<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 32-bit register for signal <DAT_O>.
-    Found 1-bit register for signal <ACK_O>.
-    Found 20-bit register for signal <ac_cmd_addr>.
-    Found 20-bit register for signal <ac_cmd_data>.
-    Found 1-bit register for signal <ac_cmd_we>.
-    Found 4-bit up counter for signal <ac_tx_pcm_addr>.
-    Found 32-bit register for signal <addr_reg>.
-    Found 32-bit 4-to-1 multiplexer for signal <addr_reg$mux0000> created at line 296.
-    Found 1-bit register for signal <cmd_pending>.
-    Found 1-bit register for signal <cmd_reg_we>.
-    Found 32-bit 4-to-1 multiplexer for signal <DAT_O$mux0000> created at line 296.
-    Found 32-bit register for signal <data_reg>.
-    Found 32-bit 4-to-1 multiplexer for signal <data_reg$mux0000> created at line 296.
-    Found 1-bit register for signal <int_en_frame_sync>.
-    Found 1-bit register for signal <int_en_rx>.
-    Found 1-bit register for signal <int_en_tx>.
-    Found 1-bit register for signal <rx_data_ack>.
-    Found 1-bit register for signal <rx_data_irq>.
-    Found 1-bit register for signal <rx_en>.
-    Found 1-bit register for signal <stat_pending>.
-    Found 16-bit register for signal <stat_reg>.
-    Found 1-bit register for signal <stat_reg_re>.
-    Found 1-bit register for signal <stat_valid>.
-    Found 1-bit register for signal <tx_data_start>.
-    Found 1-bit register for signal <tx_en>.
-    Found 1-bit register for signal <tx_fifo_we>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred 168 D-type flip-flop(s).
-	inferred  96 Multiplexer(s).
-Unit <ac97_wb> synthesized.
-
-
-Synthesizing Unit <sdram_ctrl_top>.
-    Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd".
-Unit <sdram_ctrl_top> synthesized.
-
-
-Synthesizing Unit <sdram_ctrl_frontend64_wb>.
-    Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd".
-WARNING:Xst:647 - Input <ADDR_I<31:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ADDR_I<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <u_tag_wr<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <u_tag_rd<3:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-Unit <sdram_ctrl_frontend64_wb> synthesized.
-
-
-Synthesizing Unit <mips_sys>.
-    Related source file is "W:/vhdl/projects/mips_sys/src/mips_sys.vhd".
-WARNING:Xst:646 - Signal <usb_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <gpo1<31:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <gpo0<31:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <gpi1<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000.
-WARNING:Xst:653 - Signal <gpi0<31:5>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000.
-WARNING:Xst:646 - Signal <flash_addr<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Using one-hot encoding for signal <mem_area>.
-    Found 32-bit 4-to-1 multiplexer for signal <ADDR_O>.
-    Found 2-bit register for signal <arb_gnt>.
-    Found 1-bit register for signal <arb_idx<0>>.
-    Found 6-bit register for signal <INT>.
-    Found 64-bit 4-to-1 multiplexer for signal <MDAT_O>.
-    Summary:
-	inferred   9 D-type flip-flop(s).
-	inferred  96 Multiplexer(s).
-Unit <mips_sys> synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# RAMs                                                 : 10
- 2048x32-bit dual-port RAM                             : 1
- 2048x64-bit dual-port RAM                             : 1
- 256x18-bit dual-port RAM                              : 1
- 32x30-bit dual-port RAM                               : 1
- 32x32-bit dual-port RAM                               : 1
- 32x64-bit dual-port RAM                               : 1
- 32x72-bit dual-port RAM                               : 1
- 4096x8-bit dual-port RAM                              : 1
- 4x105-bit dual-port RAM                               : 1
- 512x64-bit dual-port RAM                              : 1
-# ROMs                                                 : 6
- 10x4-bit ROM                                          : 1
- 15x27-bit ROM                                         : 1
- 32x12-bit ROM                                         : 2
- 32x8-bit ROM                                          : 1
- 4096x8-bit ROM                                        : 1
-# Adders/Subtractors                                   : 53
- 10-bit subtractor                                     : 1
- 12-bit adder                                          : 7
- 12-bit subtractor                                     : 2
- 2-bit adder                                           : 2
- 2-bit subtractor                                      : 1
- 3-bit adder                                           : 1
- 3-bit subtractor                                      : 4
- 32-bit adder                                          : 7
- 5-bit adder                                           : 5
- 6-bit adder                                           : 12
- 6-bit subtractor                                      : 6
- 8-bit adder                                           : 2
- 8-bit subtractor                                      : 1
- 9-bit adder                                           : 2
-# Counters                                             : 49
- 10-bit down counter                                   : 2
- 10-bit up counter                                     : 2
- 10-bit updown counter                                 : 1
- 12-bit up counter                                     : 1
- 14-bit down counter                                   : 4
- 15-bit down counter                                   : 1
- 16-bit up counter                                     : 2
- 18-bit up counter                                     : 1
- 29-bit up counter                                     : 2
- 3-bit down counter                                    : 4
- 3-bit updown counter                                  : 1
- 32-bit up counter                                     : 6
- 4-bit down counter                                    : 1
- 4-bit up counter                                      : 4
- 5-bit down counter                                    : 3
- 5-bit up counter                                      : 5
- 6-bit updown counter                                  : 1
- 7-bit down counter                                    : 2
- 7-bit up counter                                      : 3
- 8-bit down counter                                    : 1
- 9-bit down counter                                    : 1
- 9-bit updown counter                                  : 1
-# Accumulators                                         : 2
- 32-bit up loadable accumulator                        : 2
-# Registers                                            : 731
- 1-bit register                                        : 493
- 105-bit register                                      : 1
- 12-bit register                                       : 18
- 13-bit register                                       : 5
- 16-bit register                                       : 6
- 18-bit register                                       : 1
- 2-bit register                                        : 10
- 20-bit register                                       : 33
- 25-bit register                                       : 2
- 3-bit register                                        : 5
- 30-bit register                                       : 1
- 32-bit register                                       : 34
- 4-bit register                                        : 15
- 48-bit register                                       : 2
- 5-bit register                                        : 9
- 6-bit register                                        : 55
- 64-bit register                                       : 5
- 7-bit register                                        : 4
- 72-bit register                                       : 1
- 8-bit register                                        : 28
- 9-bit register                                        : 3
-# Comparators                                          : 71
- 10-bit comparator greatequal                          : 1
- 10-bit comparator lessequal                           : 1
- 12-bit comparator equal                               : 2
- 12-bit comparator greatequal                          : 2
- 12-bit comparator lessequal                           : 1
- 13-bit comparator not equal                           : 1
- 16-bit comparator equal                               : 2
- 2-bit comparator equal                                : 2
- 21-bit comparator equal                               : 1
- 29-bit comparator equal                               : 1
- 3-bit comparator greatequal                           : 1
- 3-bit comparator less                                 : 1
- 3-bit comparator lessequal                            : 1
- 32-bit comparator equal                               : 4
- 32-bit comparator greatequal                          : 3
- 32-bit comparator less                                : 3
- 32-bit comparator not equal                           : 4
- 4-bit comparator greatequal                           : 1
- 4-bit comparator greater                              : 1
- 4-bit comparator less                                 : 1
- 5-bit comparator equal                                : 3
- 5-bit comparator greatequal                           : 2
- 5-bit comparator less                                 : 4
- 6-bit comparator equal                                : 6
- 6-bit comparator greatequal                           : 4
- 6-bit comparator lessequal                            : 4
- 7-bit comparator equal                                : 1
- 7-bit comparator greatequal                           : 3
- 7-bit comparator less                                 : 2
- 8-bit comparator equal                                : 2
- 8-bit comparator greatequal                           : 1
- 8-bit comparator less                                 : 1
- 9-bit comparator equal                                : 2
- 9-bit comparator greatequal                           : 1
- 9-bit comparator lessequal                            : 1
-# Multiplexers                                         : 6
- 1-bit 4-to-1 multiplexer                              : 1
- 32-bit 4-to-1 multiplexer                             : 4
- 64-bit 4-to-1 multiplexer                             : 1
-# Tristates                                            : 39
- 1-bit tristate buffer                                 : 36
- 16-bit tristate buffer                                : 1
- 32-bit tristate buffer                                : 1
- 4-bit tristate buffer                                 : 1
-# Xors                                                 : 60
- 1-bit xor2                                            : 60
-
-=========================================================================
-
-=========================================================================
-*                       Advanced HDL Synthesis                          *
-=========================================================================
-
-Analyzing FSM <FSM_14> for best encoding.
-Optimizing FSM <inst_vga_frontend/s/FSM> on signal <s[1:8]> with one-hot encoding.
-----------------------------------
- State                | Encoding
-----------------------------------
- init                 | 00000001
- rdy                  | 00000010
- scan_bus_request     | 00000100
- scan_bus_read        | 00100000
- blit_src_bus_request | 00001000
- blit_src_bus_read    | 01000000
- blit_dst_bus_request | 00010000
- blit_dst_bus_fin     | 10000000
-----------------------------------
-Analyzing FSM <FSM_13> for best encoding.
-Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_out/sac/FSM> on signal <sac[1:2]> with sequential encoding.
----------------------
- State   | Encoding
----------------------
- ac_idle | 00
- ac_tag  | 01
- ac_data | 10
----------------------
-Analyzing FSM <FSM_12> for best encoding.
-Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/sac/FSM> on signal <sac[1:2]> with sequential encoding.
----------------------
- State   | Encoding
----------------------
- ac_idle | 00
- ac_tag  | 01
- ac_data | 10
----------------------
-Analyzing FSM <FSM_11> for best encoding.
-Optimizing FSM <inst_vga_frontend/inst_char_gen/s/FSM> on signal <s[1:2]> with gray encoding.
----------------------------
- State         | Encoding
----------------------------
- cg_init       | 00
- cg_ready      | 10
- cg_clr_line   | 11
- cg_clr_screen | 01
----------------------------
-Analyzing FSM <FSM_9> for best encoding.
-Optimizing FSM <inst_ps2_wb_0/inst_ps2_core/read_cs/FSM> on signal <read_cs[1:4]> with gray encoding.
-Optimizing FSM <inst_ps2_wb_1/inst_ps2_core/read_cs/FSM> on signal <read_cs[1:4]> with gray encoding.
-------------------------------
- State            | Encoding
-------------------------------
- start_wait_st    | 0000
- start_trans_st   | 0001
- start_sample_st  | 0011
- data_wait_st     | 0010
- data_trans_st    | 0110
- data_sample_st   | 0111
- parity_wait_st   | 0101
- parity_trans_st  | 0100
- parity_sample_st | 1100
- stop_wait_st     | 1111
- stop_trans_st    | 1110
- stop_sample_st   | 1010
- valid_st         | 1011
- abort_st         | 1101
-------------------------------
-Analyzing FSM <FSM_8> for best encoding.
-Optimizing FSM <inst_ps2_wb_0/inst_ps2_core/write_cs/FSM> on signal <write_cs[1:18]> with one-hot encoding.
-Optimizing FSM <inst_ps2_wb_1/inst_ps2_core/write_cs/FSM> on signal <write_cs[1:18]> with one-hot encoding.
--------------------------------------------
- State               | Encoding
--------------------------------------------
- tx_idle_st          | 000000000000000001
- tx_clock_assert_st  | 000000000000000010
- tx_start_latency_st | unreached
- tx_start_assert_st  | 000000000000000100
- tx_clock_release_st | 000000000000001000
- tx_dev_trans_st     | 000000000000100000
- tx_data_wait_st     | 000000000001000000
- tx_data_trans_st    | 000000001000000000
- tx_data_sample_st   | 000000000010000000
- tx_parity_update_st | 000000000100000000
- tx_dev_wait_st      | 000000000000010000
- tx_parity_wait_st   | 000000100000000000
- tx_parity_trans_st  | 000000010000000000
- tx_parity_sample_st | 000001000000000000
- tx_stop_wait_st     | 000100000000000000
- tx_stop_trans_st    | 000010000000000000
- tx_stop_sample_st   | unreached
- tx_ack_trans_st     | 001000000000000000
- tx_ack_sample_st    | 010000000000000000
- tx_valid_st         | 100000000000000000
--------------------------------------------
-Analyzing FSM <FSM_7> for best encoding.
-Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2/s/FSM> on signal <s[1:2]> with gray encoding.
-----------------------
- State    | Encoding
-----------------------
- idle     | 00
- shot_in  | 01
- active   | 11
- shot_out | 10
-----------------------
-Analyzing FSM <FSM_6> for best encoding.
-Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1/s/FSM> on signal <s[1:2]> with gray encoding.
-Optimizing FSM <inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1/s/FSM> on signal <s[1:2]> with gray encoding.
-----------------------
- State    | Encoding
-----------------------
- idle     | 00
- shot_in  | 01
- active   | 11
- shot_out | 10
-----------------------
-Analyzing FSM <FSM_5> for best encoding.
-Optimizing FSM <inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state/FSM> on signal <state[1:3]> with sequential encoding.
-----------------------
- State    | Encoding
-----------------------
- st_init  | 000
- st_scan  | 100
- st_front | 001
- st_sync  | 010
- st_back  | 011
-----------------------
-Analyzing FSM <FSM_4> for best encoding.
-Optimizing FSM <inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state/FSM> on signal <state[1:3]> with sequential encoding.
-----------------------
- State    | Encoding
-----------------------
- st_init  | 000
- st_scan  | 100
- st_front | 001
- st_sync  | 010
- st_back  | 011
-----------------------
-Analyzing FSM <FSM_3> for best encoding.
-Optimizing FSM <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr/FSM> on signal <st_sdr[1:8]> with one-hot encoding.
---------------------------
- State        | Encoding
---------------------------
- pwr_down     | 00000001
- precharge    | 00000100
- mode         | 00001000
- idle         | 00000010
- row_act      | 00010000
- write        | 10000000
- write_a      | unreached
- read         | 01000000
- read_a       | unreached
- burst_stop   | unreached
- self_ref     | unreached
- auto_ref     | 00100000
- pre_pwr_down | unreached
- act_pwr_down | unreached
---------------------------
-Analyzing FSM <FSM_2> for best encoding.
-Optimizing FSM <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl/FSM> on signal <st_ctrl[1:13]> with one-hot encoding.
----------------------------------
- State          | Encoding
----------------------------------
- reset          | 0000000000001
- power_wait     | 0000000000010
- init           | 0000000000100
- init_wait      | 0000000010000
- user_ready     | 0000000001000
- user_write_pre | 0000001000000
- user_write_act | 0000010000000
- user_write     | 0000100000000
- user_read_pre  | 0001000000000
- user_read_act  | 0010000000000
- user_read      | 0100000000000
- refresh_pre    | 0000000100000
- refresh        | 1000000000000
----------------------------------
-Analyzing FSM <FSM_1> for best encoding.
-Optimizing FSM <inst_usb_port/s/FSM> on signal <s[1:3]> with gray encoding.
----------------------
- State   | Encoding
----------------------
- start   | 000
- reset   | 001
- idle    | 011
- leadin  | 010
- pulse   | 110
- leadout | 111
- release | 101
----------------------
-Analyzing FSM <FSM_0> for best encoding.
-Optimizing FSM <inst_flash_port/s/FSM> on signal <s[1:3]> with sequential encoding.
----------------------
- State   | Encoding
----------------------
- start   | 000
- reset   | 001
- idle    | 010
- leadin  | 011
- pulse   | 100
- leadout | unreached
- release | 101
----------------------
-Analyzing FSM <FSM_10> for best encoding.
-Optimizing FSM <inst_ps2_phy_0/Inst_debounce_clk/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
-Optimizing FSM <inst_ps2_phy_1/Inst_debounce_clk/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
-Optimizing FSM <inst_ps2_phy_0/Inst_debounce_data/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
-Optimizing FSM <inst_ps2_phy_1/Inst_debounce_data/debounce_cs> on signal <debounce_cs[1:2]> with gray encoding.
----------------------
- State   | Encoding
----------------------
- init_st | 00
- wait_st | 01
- rel_st  | 11
----------------------
-Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE.
-WARNING:Xst:2404 -  FFs/Latches <dout<7:4>> (without init value) have a constant value of 0 in block <lcd_port>.
-WARNING:Xst:2404 -  FFs/Latches <vlcd.d<3:0>> (without init value) have a constant value of 0 in block <lcd_port>.
-WARNING:Xst:2404 -  FFs/Latches <vga_fb_back<31:0>> (without init value) have a constant value of 0 in block <vga_frontend64>.
-WARNING:Xst:2404 -  FFs/Latches <blit_nx<31:31>> (without init value) have a constant value of 0 in block <vga_frontend64>.
-
-Synthesizing (advanced) Unit <char_gen>.
-INFO:Xst - In order to maximize performance and save block RAM resources, the small ROM <Mrom_cursor_rom_data_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-Unit <char_gen> synthesized (advanced).
-
-Synthesizing (advanced) Unit <char_rom>.
-INFO:Xst - The ROM <Mrom_DATA_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <DATA>.
-INFO:Xst - The RAM <Mrom_DATA_rom0000> will be implemented as BLOCK RAM
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 4096-word x 8-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <CLK>           | rise     |
-    |     weA            | connected to internal node          | high     |
-    |     addrA          | connected to signal <ADDR>          |          |
-    |     diA            | connected to internal node          |          |
-    |     doA            | connected to signal <DATA>          |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <char_rom> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_1>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 32-word x 30-bit                    |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 32-word x 30-bit                    |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_1> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_2>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 32-word x 72-bit                    |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 32-word x 72-bit                    |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_2> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_3>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 32-word x 64-bit                    |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 32-word x 64-bit                    |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_3> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_4>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 2048-word x 64-bit                  |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 2048-word x 64-bit                  |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_4> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_5>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 512-word x 64-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 512-word x 64-bit                   |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_5> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_6>.
-INFO:Xst - The small RAM <Mram_RAM> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-    -----------------------------------------------------------------------
-    | ram_type           | Distributed                         |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 4-word x 105-bit                    |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 4-word x 105-bit                    |          |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to internal node          |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_6> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_7>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 4096-word x 8-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 4096-word x 8-bit                   |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_7> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_8>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 256-word x 18-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 256-word x 18-bit                   |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_8> synthesized (advanced).
-
-Synthesizing (advanced) Unit <dpram_1w1r_9>.
-INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dout_b>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 32-word x 32-bit                    |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clka>          | rise     |
-    |     weA            | connected to signal <we_a>          | high     |
-    |     addrA          | connected to signal <addr_a>        |          |
-    |     diA            | connected to signal <din_a>         |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 32-word x 32-bit                    |          |
-    |     mode           | read-first                          |          |
-    |     clkB           | connected to signal <clkb>          | rise     |
-    |     addrB          | connected to signal <addr_b>        |          |
-    |     doB            | connected to signal <dout_b>        |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <dpram_1w1r_9> synthesized (advanced).
-
-Synthesizing (advanced) Unit <rom>.
-INFO:Xst - The RAM <Mram_word_array> will be implemented as a BLOCK RAM, absorbing the following register(s): <jtag_ld_dout> <dout>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 2048-word x 32-bit                  |          |
-    |     mode           | no-change                           |          |
-    |     clkA           | connected to signal <bs_update1>    | rise     |
-    |     weA            | connected to signal <bs_sel>        | high     |
-    |     addrA          | connected to signal <user_regi>     |          |
-    |     diA            | connected to signal <user_regi>     |          |
-    |     doA            | connected to signal <jtag_ld_dout>  |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 2048-word x 32-bit                  |          |
-    |     mode           | write-first                         |          |
-    |     clkB           | connected to signal <clk>           | rise     |
-    |     enB            | connected to signal <ce>            | high     |
-    |     addrB          | connected to signal <addr>          |          |
-    |     doB            | connected to signal <dout>          |          |
-    -----------------------------------------------------------------------
-    | optimization       | speed                               |          |
-    -----------------------------------------------------------------------
-Unit <rom> synthesized (advanced).
-WARNING:Xst:1710 - FF/Latch <vlcd.rw> (without init value) has a constant value of 1 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vlcd.e> (without init value) has a constant value of 0 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vlcd.rs> (without init value) has a constant value of 0 in block <lcd_port>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <ADDR_I_r_0> of sequential type is unconnected in block <async_port_wb_1>.
-WARNING:Xst:2677 - Node <ADDR_I_r_1> of sequential type is unconnected in block <async_port_wb_1>.
-WARNING:Xst:2677 - Node <ADDR_I_r_2> of sequential type is unconnected in block <async_port_wb_1>.
-WARNING:Xst:2677 - Node <ADDR_I_r_3> of sequential type is unconnected in block <async_port_wb_1>.
-WARNING:Xst:2677 - Node <row_addr_last_10> of sequential type is unconnected in block <sdram_ctrl>.
-INFO:Xst:2261 - The FF/Latch <input_last> in Unit <debounce> is equivalent to the following FF/Latch, which will be removed : <output> 
-INFO:Xst:2261 - The FF/Latch <we_reg> in Unit <ddr_phy> is equivalent to the following FF/Latch, which will be removed : <sdr_data_req_w> 
-INFO:Xst:2261 - The FF/Latch <drive270_10> in Unit <ddr_phy> is equivalent to the following 31 FFs/Latches, which will be removed : <drive270_11> <drive270_14> <drive270_12> <drive270_13> <drive270_15> <drive270_20> <drive270_16> <drive270_21> <drive270_0> <drive270_17> <drive270_22> <drive270_23> <drive270_18> <drive270_1> <drive270_2> <drive270_19> <drive270_24> <drive270_30> <drive270_25> <drive270_26> <drive270_3> <drive270_31> <drive270_4> <drive270_27> <drive270_28> <drive270_5> <drive270_29> <drive270_6> <drive270_7> <drive270_8> <drive270_9> 
-INFO:Xst:2261 - The FF/Latch <dqs_zen_0> in Unit <ddr_phy> is equivalent to the following 3 FFs/Latches, which will be removed : <dqs_zen_1> <dqs_zen_2> <dqs_zen_3> 
-WARNING:Xst:1710 - FF/Latch <DAT_O_10> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_12> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_13> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <DAT_O_14> (without init value) has a constant value of 0 in block <ps2_wb>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <csr_posx_cnt_en> in Unit <char_gen> is equivalent to the following FF/Latch, which will be removed : <a_data_we> 
-WARNING:Xst:2677 - Node <tag_0> of sequential type is unconnected in block <ac_in>.
-WARNING:Xst:2677 - Node <tag_1> of sequential type is unconnected in block <ac_in>.
-WARNING:Xst:2677 - Node <tag_2> of sequential type is unconnected in block <ac_in>.
-INFO:Xst:2261 - The FF/Latch <slot_valid_1> in Unit <ac_out> is equivalent to the following FF/Latch, which will be removed : <slot_valid_2> 
-WARNING:Xst:1710 - FF/Latch <blit_dimx_src_1_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_1_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_1_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_src_0_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dimx_dst_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_dst_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <host_fb_back_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_0_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_addr_src_1_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <vga_fb_front_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_25> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_24> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_30> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_29> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_31> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_30> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_26> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_25> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_27> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_26> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_28> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_27> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_29> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_28> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_1> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_0> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_2> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_1> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_3> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_2> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_4> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_3> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_5> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_4> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_6> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_5> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_7> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_6> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_8> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_7> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_9> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_8> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_10> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_9> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_11> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_10> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_12> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_11> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_13> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_12> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_14> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_13> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_15> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_14> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_20> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_19> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_16> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_15> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_21> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_20> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_17> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_16> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_22> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_21> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_18> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_17> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_23> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_22> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_19> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_18> 
-INFO:Xst:2261 - The FF/Latch <host_blit_nx_24> in Unit <vga_frontend64> is equivalent to the following FF/Latch, which will be removed : <blit_nx_23> 
-WARNING:Xst:1710 - FF/Latch <ac_cmd_data_0> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_1> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_2> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_data_3> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_0> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_1> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_2> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_3> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_4> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_5> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_6> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_7> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_8> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_9> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_10> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ac_cmd_addr_11> (without init value) has a constant value of 0 in block <ac97_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_2_3> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_2_2> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_2_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_2_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_11> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_10> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_9> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_8> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_7> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_6> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_5> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_4> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_3> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_2> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_1_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_31> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_30> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_29> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_28> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_27> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_26> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_12_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_12_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_11_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_11_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_10_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_10_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_9_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_9_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_8_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_8_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_7_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_7_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <tx_reg_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <tx_reg_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_6_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_6_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_5_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_5_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_4_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_4_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_3_1> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <data_array_3_0> (without init value) has a constant value of 0 in block <inst_ac_out>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_26> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_25> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_24> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_23> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_22> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_21> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_20> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_19> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_18> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_17> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_16> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_15> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_14> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_13> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_12> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_11> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_10> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_9> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_8> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_7> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_6> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_5> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_25> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_24> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_23> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_22> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_21> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_20> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_19> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_18> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_17> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_16> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_15> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_14> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_13> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_12> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_11> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_10> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_9> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi1_reg_8> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_31> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_30> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_29> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_28> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_27> (without init value) has a constant value of 0 in block <inst_gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <dout_0> of sequential type is unconnected in block <inst_lcd_port>.
-WARNING:Xst:2677 - Node <dout_1> of sequential type is unconnected in block <inst_lcd_port>.
-WARNING:Xst:2677 - Node <dout_2> of sequential type is unconnected in block <inst_lcd_port>.
-WARNING:Xst:2677 - Node <dout_3> of sequential type is unconnected in block <inst_lcd_port>.
-WARNING:Xst:2677 - Node <gpo1_reg_3> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_4> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_10> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_5> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_11> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_6> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_10> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_12> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_7> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_11> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_8> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_13> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_12> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_14> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_9> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_13> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_15> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_20> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_14> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_16> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_21> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_20> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_15> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_17> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_22> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_21> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_16> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_18> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_23> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_22> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_17> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_19> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_24> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_23> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_18> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_25> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_30> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_24> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_19> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_26> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_31> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_30> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_25> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_9> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_27> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_31> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_28> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_26> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_27> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo1_reg_29> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_28> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <gpo0_reg_29> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_9> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_10> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_11> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_12> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_13> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_14> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_15> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_16> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_17> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_18> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_19> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_20> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_21> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_22> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_23> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_24> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_25> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_26> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_27> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_28> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_29> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_30> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo0_31> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_3> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_4> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_5> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_6> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_7> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_8> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_9> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_10> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_11> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_12> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_13> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_14> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_15> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_16> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_17> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_18> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_19> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_20> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_21> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_22> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_23> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_24> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_25> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_26> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_27> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_28> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_29> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_30> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <sys_gpo1_31> of sequential type is unconnected in block <inst_gpio_wb>.
-WARNING:Xst:2677 - Node <async_be_0> of sequential type is unconnected in block <inst_flash_port>.
-WARNING:Xst:2677 - Node <async_a_0> of sequential type is unconnected in block <inst_flash_port>.
-WARNING:Xst:2677 - Node <async_a_1> of sequential type is unconnected in block <inst_flash_port>.
-WARNING:Xst:2677 - Node <async_be_0> of sequential type is unconnected in block <inst_usb_port>.
-WARNING:Xst:2677 - Node <async_rst> of sequential type is unconnected in block <inst_usb_port>.
-WARNING:Xst:2677 - Node <async_a_0> of sequential type is unconnected in block <inst_usb_port>.
-WARNING:Xst:2677 - Node <async_a_1> of sequential type is unconnected in block <inst_usb_port>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_async_ctrl>.
-WARNING:Xst:2677 - Node <u_tag_pipe_0_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_0_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_0_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_1_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_1_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_1_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_wr_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_wr_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_wr_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_2_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_2_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_2_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_3_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_3_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_3_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_4_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_4_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_pipe_4_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_rd_1> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_rd_2> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <u_tag_rd_3> of sequential type is unconnected in block <inst_ddr_phy>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <fifo_afull> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <fifo_aempty> of sequential type is unconnected in block <inst_fifo_sync_ctrl>.
-WARNING:Xst:2677 - Node <tag_3> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_4> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_5> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_6> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_7> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_8> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_9> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <tag_10> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_1_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_1_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_4_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_4_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_2_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_2_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_3_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_3_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_7_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_7_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_5_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_5_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_6_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_6_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_10_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_10_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_8_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_8_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_9_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_9_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_11_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_11_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_12_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <data_array_12_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_data_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_data_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_data_2> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_data_3> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_0> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_1> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_2> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_3> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_4> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_5> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_6> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_7> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_8> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_9> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_12> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_13> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_14> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_15> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_16> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_17> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_18> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <stat_addr_19> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_12> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_11> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_10> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_9> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_8> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_7> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_6> of sequential type is unconnected in block <inst_ac_in>.
-WARNING:Xst:2677 - Node <slot_valid_5> of sequential type is unconnected in block <inst_ac_in>.
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Macro Statistics
-# RAMs                                                 : 11
- 2048x32-bit dual-port block RAM                       : 1
- 2048x64-bit dual-port block RAM                       : 1
- 256x18-bit dual-port block RAM                        : 1
- 32x30-bit dual-port block RAM                         : 1
- 32x32-bit dual-port block RAM                         : 1
- 32x64-bit dual-port block RAM                         : 1
- 32x72-bit dual-port block RAM                         : 1
- 4096x8-bit dual-port block RAM                        : 1
- 4096x8-bit single-port block RAM                      : 1
- 4x105-bit dual-port distributed RAM                   : 1
- 512x64-bit dual-port block RAM                        : 1
-# ROMs                                                 : 5
- 10x4-bit ROM                                          : 1
- 15x27-bit ROM                                         : 1
- 32x12-bit ROM                                         : 2
- 32x8-bit ROM                                          : 1
-# Adders/Subtractors                                   : 53
- 10-bit subtractor                                     : 1
- 12-bit adder                                          : 7
- 12-bit subtractor                                     : 2
- 2-bit adder                                           : 2
- 2-bit subtractor                                      : 1
- 3-bit adder                                           : 1
- 3-bit subtractor                                      : 4
- 32-bit adder                                          : 7
- 5-bit adder                                           : 5
- 6-bit adder                                           : 12
- 6-bit subtractor                                      : 6
- 8-bit adder                                           : 2
- 8-bit subtractor                                      : 1
- 9-bit adder                                           : 2
-# Counters                                             : 49
- 10-bit down counter                                   : 2
- 10-bit up counter                                     : 2
- 10-bit updown counter                                 : 1
- 12-bit up counter                                     : 1
- 14-bit down counter                                   : 4
- 15-bit down counter                                   : 1
- 16-bit up counter                                     : 2
- 18-bit up counter                                     : 1
- 29-bit up counter                                     : 2
- 3-bit down counter                                    : 4
- 3-bit updown counter                                  : 1
- 32-bit up counter                                     : 6
- 4-bit down counter                                    : 1
- 4-bit up counter                                      : 4
- 5-bit down counter                                    : 3
- 5-bit up counter                                      : 5
- 6-bit updown counter                                  : 1
- 7-bit down counter                                    : 2
- 7-bit up counter                                      : 3
- 8-bit down counter                                    : 1
- 9-bit down counter                                    : 1
- 9-bit updown counter                                  : 1
-# Accumulators                                         : 2
- 32-bit up loadable accumulator                        : 2
-# Registers                                            : 3649
- Flip-Flops                                            : 3649
-# Comparators                                          : 71
- 10-bit comparator greatequal                          : 1
- 10-bit comparator lessequal                           : 1
- 12-bit comparator equal                               : 2
- 12-bit comparator greatequal                          : 2
- 12-bit comparator lessequal                           : 1
- 13-bit comparator not equal                           : 1
- 16-bit comparator equal                               : 2
- 2-bit comparator equal                                : 2
- 21-bit comparator equal                               : 1
- 29-bit comparator equal                               : 1
- 3-bit comparator greatequal                           : 1
- 3-bit comparator less                                 : 1
- 3-bit comparator lessequal                            : 1
- 32-bit comparator equal                               : 4
- 32-bit comparator greatequal                          : 3
- 32-bit comparator less                                : 3
- 32-bit comparator not equal                           : 4
- 4-bit comparator greatequal                           : 1
- 4-bit comparator greater                              : 1
- 4-bit comparator less                                 : 1
- 5-bit comparator equal                                : 3
- 5-bit comparator greatequal                           : 2
- 5-bit comparator less                                 : 4
- 6-bit comparator equal                                : 6
- 6-bit comparator greatequal                           : 4
- 6-bit comparator lessequal                            : 4
- 7-bit comparator equal                                : 1
- 7-bit comparator greatequal                           : 3
- 7-bit comparator less                                 : 2
- 8-bit comparator equal                                : 2
- 8-bit comparator greatequal                           : 1
- 8-bit comparator less                                 : 1
- 9-bit comparator equal                                : 2
- 9-bit comparator greatequal                           : 1
- 9-bit comparator lessequal                            : 1
-# Multiplexers                                         : 6
- 1-bit 4-to-1 multiplexer                              : 1
- 32-bit 4-to-1 multiplexer                             : 4
- 64-bit 4-to-1 multiplexer                             : 1
-# Xors                                                 : 60
- 1-bit xor2                                            : 60
-
-=========================================================================
-
-=========================================================================
-*                         Low Level Synthesis                           *
-=========================================================================
-INFO:Xst:2261 - The FF/Latch <gpi0_reg_5> in Unit <gpio_wb> is equivalent to the following 50 FFs/Latches, which will be removed : <gpi0_reg_6> <gpi0_reg_7> <gpi0_reg_8> <gpi0_reg_9> <gpi0_reg_10> <gpi0_reg_11> <gpi0_reg_12> <gpi0_reg_13> <gpi0_reg_14> <gpi0_reg_15> <gpi0_reg_16> <gpi0_reg_17> <gpi0_reg_18> <gpi0_reg_19> <gpi0_reg_20> <gpi0_reg_21> <gpi0_reg_22> <gpi0_reg_23> <gpi0_reg_24> <gpi0_reg_25> <gpi0_reg_26> <gpi0_reg_27> <gpi0_reg_28> <gpi0_reg_29> <gpi0_reg_30> <gpi0_reg_31> <gpi1_reg_8> <gpi1_reg_9> <gpi1_reg_10> <gpi1_reg_11> <gpi1_reg_12> <gpi1_reg_13> <gpi1_reg_14> <gpi1_reg_15> <gpi1_reg_16> <gpi1_reg_17> <gpi1_reg_18> <gpi1_reg_19> <gpi1_reg_20> <gpi1_reg_21> <gpi1_reg_22> <gpi1_reg_23> <gpi1_reg_24> <gpi1_reg_25> <gpi1_reg_26> <gpi1_reg_27> <gpi1_reg_28> <gpi1_reg_29> <gpi1_reg_30> <gpi1_reg_31> 
-WARNING:Xst:1710 - FF/Latch <gpi0_reg_5> (without init value) has a constant value of 0 in block <gpio_wb>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_write_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_read_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_aw_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/bcnt2_ar_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_afull> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_aempty> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p22_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p21_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p12_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p11_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff0_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_5> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_4> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_3> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_2> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_1> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/diff_0> of sequential type is unconnected in block <sdram_ctrl_frontend64_wb>.
-WARNING:Xst:2677 - Node <inst_lcd_port/dout_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_lcd_port/dout_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_lcd_port/dout_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_lcd_port/dout_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <diff0_0> of sequential type is unconnected in block <fifo_async_ctrl_2>.
-WARNING:Xst:1710 - FF/Latch <blit_src_offset_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_offset_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_offset_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_offset_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_src_off_y_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_0> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_1> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blit_dst_off_y_2> (without init value) has a constant value of 0 in block <vga_frontend64>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <data_reg_18> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_19> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_20> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_21> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_22> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_23> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_24> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_25> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_26> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_27> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_28> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_29> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_30> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <data_reg_31> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_0> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_1> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_10> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_11> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_12> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_13> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_14> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_15> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_16> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_17> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_18> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_19> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_20> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_21> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_22> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_23> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_24> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_25> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_26> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_27> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_28> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_29> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_30> of sequential type is unconnected in block <ac97_wb>.
-WARNING:Xst:2677 - Node <addr_reg_31> of sequential type is unconnected in block <ac97_wb>.
-INFO:Xst:1901 - Instance inst_DCM_VGA_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
-INFO:Xst:1901 - Instance inst_DCM_SYS_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
-INFO:Xst:1901 - Instance inst_DCM_SDRCLK_0 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
-INFO:Xst:1901 - Instance inst_DCM_SDRCLK_1 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV
-WARNING:Xst:2677 - Node <inst_flash_port/async_a_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_flash_port/async_a_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_flash_port/async_be_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_usb_port/async_a_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_usb_port/async_a_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_usb_port/async_rst> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_usb_port/async_be_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_0_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_1_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_wr_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_2_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_3_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_rd_3> of sequential type is unconnected in block <mips_sys>.
-INFO:Xst:2261 - The FF/Latch <cursor_rom_data_0> in Unit <char_gen> is equivalent to the following 7 FFs/Latches, which will be removed : <cursor_rom_data_1> <cursor_rom_data_2> <cursor_rom_data_3> <cursor_rom_data_4> <cursor_rom_data_5> <cursor_rom_data_6> <cursor_rom_data_7> 
-
-Optimizing unit <mips_sys> ...
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/p0_2> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/read_en> 
-
-Optimizing unit <gpio_wb> ...
-
-Optimizing unit <fifo_sync_ctrl_1> ...
-
-Optimizing unit <gray_counter_1> ...
-INFO:Xst:2261 - The FF/Latch <cntb_5> in Unit <gray_counter_1> is equivalent to the following FF/Latch, which will be removed : <cntg_5> 
-INFO:Xst:2261 - The FF/Latch <cntb_5> in Unit <gray_counter_1> is equivalent to the following FF/Latch, which will be removed : <cntg_5> 
-
-Optimizing unit <sdram_ctrl> ...
-
-Optimizing unit <sdram_cmd> ...
-WARNING:Xst:1710 - FF/Latch <burst_finished> (without init value) has a constant value of 1 in block <sdram_cmd>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <burst_cnt_1> has a constant value of 0 in block <sdram_cmd>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <burst_cnt_0> of sequential type is unconnected in block <sdram_cmd>.
-
-Optimizing unit <gray_counter_2> ...
-INFO:Xst:2261 - The FF/Latch <cntb_11> in Unit <gray_counter_2> is equivalent to the following FF/Latch, which will be removed : <cntg_11> 
-INFO:Xst:2261 - The FF/Latch <cntb_11> in Unit <gray_counter_2> is equivalent to the following FF/Latch, which will be removed : <cntg_11> 
-
-Optimizing unit <fifo_sync_ctrl_2> ...
-
-Optimizing unit <fifo_sync_ctrl_3> ...
-
-Optimizing unit <dpram_1w1r_6> ...
-
-Optimizing unit <fifo_sync_ctrl_4> ...
-
-Optimizing unit <ps2_core> ...
-
-Optimizing unit <debounce> ...
-
-Optimizing unit <clockgen> ...
-
-Optimizing unit <rom> ...
-
-Optimizing unit <kcuart_tx> ...
-
-Optimizing unit <bbfifo_16x8> ...
-
-Optimizing unit <kcuart_rx> ...
-
-Optimizing unit <char_gen> ...
-
-Optimizing unit <fifo_async_ctrl_2> ...
-
-Optimizing unit <ac_in> ...
-
-Optimizing unit <ac_out> ...
-
-Optimizing unit <vga_backend> ...
-
-Optimizing unit <ac_io> ...
-
-Optimizing unit <vga_frontend64> ...
-
-Optimizing unit <ac97_wb> ...
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_4_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_3_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_3_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_3> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_2> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_2_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_11> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_10> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_9> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_8> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_7> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_6> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_5> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_4> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_3> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_2> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_1_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_12_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_12_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_10_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_10_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_9_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_9_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_8_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_8_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_7_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_7_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_6_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_6_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_5_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_5_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_4_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_1> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_0> (without init value) has a constant value of 0 in block <mips_sys>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_31> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_30> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_29> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_28> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_27> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_26> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_25> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_24> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_23> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_22> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_21> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_20> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_11> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo1_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_31> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_30> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_29> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_28> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_27> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_26> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_25> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_24> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_23> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_22> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_21> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_20> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_11> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/sys_gpo0_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_29> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_28> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_29> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_27> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_26> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_28> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_31> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_27> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_25> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_30> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_31> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_26> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_24> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_30> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_25> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_23> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_24> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_22> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_23> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_21> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_22> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_20> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_21> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_20> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_11> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo0_reg_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_11> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_gpio_wb/gpo1_reg_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/fifo_afull> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/Mram_RAM1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/Mram_RAM2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/fifo_afull> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/diff_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_11> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/slot_valid_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_addr_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/stat_data_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_11_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_11_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_9_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_9_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_8_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_8_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_10_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_10_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_6_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_6_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_5_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_5_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_4_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_4_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_19> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_18> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_17> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_16> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_15> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_14> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_13> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_12> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_2> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_1> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_0> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_10> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_9> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_8> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_7> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_6> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_5> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_4> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_ac_io/inst_ac_in/tag_3> of sequential type is unconnected in block <mips_sys>.
-WARNING:Xst:2677 - Node <inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/fifo_aempty> of sequential type is unconnected in block <mips_sys>.
-
-Mapping all equations...
-WARNING:Xst:2036 - Inserting OBUF on port <sys_error<1>> driven by black box <mips_top>. Possible simulation mismatch.
-WARNING:Xst:2036 - Inserting OBUF on port <sys_error<0>> driven by black box <mips_top>. Possible simulation mismatch.
-Building and optimizing final netlist ...
-Changing polarity of register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute
-INFO:Xst:2261 - The FF/Latch <INT_0> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_gpio_wb/gpi0_reg_4> 
-Found area constraint ratio of 100 (+ 5) on block mips_sys, actual ratio is 19.
-Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/Mcount_count_cy<0>
-Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/Mcount_count_cy<0>
-Forward register balancing over carry chain inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/Madd_nxtb_addsub0000_cy<0>
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_11> 
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2260 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_11> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_11> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_5> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_5> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p10_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p12_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p11_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p1_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p20_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p22_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p21_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/p2_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_11> 
-INFO:Xst:2261 - The FF/Latch <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_11> in Unit <mips_sys> is equivalent to the following FF/Latch, which will be removed : <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_11> 
-
-Pipelining and Register Balancing Report ...
-
-Processing Unit <mips_sys> :
-	Register(s) inst_vga_frontend/s_FSM_FFd4 inst_vga_frontend/s_FSM_FFd1 has(ve) been forward balanced into : inst_vga_frontend/s_FSM_Out51_FRB.
-	Register(s) inst_ac97_wb/ac_cmd_addr_19 has(ve) been backward balanced into : inst_ac97_wb/ac_cmd_addr_19_BRB0.
-	Register(s) inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19 has(ve) been backward balanced into : inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB1 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB2.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB2 .
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB2.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB3.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB1.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB1.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB2.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB2.
-	Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB2.
-	Register(s) inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full has(ve) been backward balanced into : inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB0 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB1 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB1.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB1.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB2.
-	Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB2.
-	Register(s) inst_vga_frontend/inst_vga_backend/hsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/hsync_r_BRB0 inst_vga_frontend/inst_vga_backend/hsync_r_BRB1.
-	Register(s) inst_vga_frontend/inst_vga_backend/vsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/vsync_r_BRB0.
-Unit <mips_sys> processed.
-Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute
-Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute
-Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute
-Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute
-Replicating register inst_ac97_wb/inst_ac_io/inst_ac_out/ac_ssync to handle IOB=TRUE attribute
-Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute
-Replicating register inst_usb_port/Mtrien_async_d to handle IOB=TRUE attribute
-Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0 to handle IOB=TRUE attribute
-Replicating register inst_flash_port/Mtrien_async_d to handle IOB=TRUE attribute
-
-FlipFlop arb_gnt_0 has been replicated 2 time(s)
-FlipFlop arb_gnt_1 has been replicated 1 time(s)
-FlipFlop inst_clockgen/sys_rst_out has been replicated 14 time(s)
-FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s)
-FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s)
-FlipFlop inst_vga_frontend/s_FSM_Out51_FRB has been replicated 1 time(s)
-
-Final Macro Processing ...
-
-Processing Unit <mips_sys> :
-	Found 4-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/u_tag_pipe_4_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_3>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_3>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_w_0>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_5>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_4>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_3>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_2>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_1>.
-	Found 3-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/gcnt2_r_0>.
-	Found 20-bit shift register for signal <inst_clockgen/reset_pipe2_19>.
-	Found 20-bit shift register for signal <inst_clockgen/reset_pipe1_19>.
-	Found 20-bit shift register for signal <inst_clockgen/reset_pipe0_19>.
-	Found 6-bit shift register for signal <inst_rom_wb/inst_rom/user_regi_42>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_5>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_6>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_7>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_8>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_9>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_10>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar_11>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_5>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_6>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_7>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_8>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_9>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_10>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_aw_11>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_5>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_6>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_7>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_8>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_9>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_r_10>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_5>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_6>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_7>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_8>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_9>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gcnt2_w_10>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posy_synced_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_0>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_1>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_2>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_3>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_4>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_5>.
-	Found 3-bit shift register for signal <inst_vga_frontend/inst_char_gen/csr_posx_synced_6>.
-	Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB0>.
-	Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB1>.
-	Found 2-bit shift register for signal <inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB2>.
-Unit <mips_sys> processed.
-
-=========================================================================
-Final Register Report
-
-Macro Statistics
-# Registers                                            : 3559
- Flip-Flops                                            : 3559
-# Shift Registers                                      : 101
- 2-bit shift register                                  : 3
- 20-bit shift register                                 : 3
- 3-bit shift register                                  : 93
- 4-bit shift register                                  : 1
- 6-bit shift register                                  : 1
-
-=========================================================================
-
-=========================================================================
-*                           Partition Report                             *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-*                            Final Report                               *
-=========================================================================
-Final Results
-RTL Top Level Output File Name     : mips_sys.ngr
-Top Level Output File Name         : mips_sys
-Output Format                      : NGC
-Optimization Goal                  : Speed
-Keep Hierarchy                     : NO
-
-Design Statistics
-# IOs                              : 226
-
-Cell Usage :
-# BELS                             : 6423
-#      GND                         : 1
-#      INV                         : 93
-#      LUT1                        : 352
-#      LUT2                        : 539
-#      LUT2_D                      : 4
-#      LUT2_L                      : 3
-#      LUT3                        : 1056
-#      LUT3_D                      : 10
-#      LUT3_L                      : 6
-#      LUT4                        : 2167
-#      LUT4_D                      : 33
-#      LUT4_L                      : 55
-#      MULT_AND                    : 6
-#      MUXCY                       : 1017
-#      MUXF5                       : 245
-#      MUXF6                       : 2
-#      VCC                         : 1
-#      XORCY                       : 833
-# FlipFlops/Latches                : 3800
-#      FD                          : 318
-#      FD_1                        : 85
-#      FDC                         : 268
-#      FDC_1                       : 20
-#      FDCE                        : 255
-#      FDCPE                       : 4
-#      FDE                         : 1373
-#      FDP                         : 78
-#      FDPE                        : 21
-#      FDR                         : 192
-#      FDR_1                       : 1
-#      FDRE                        : 937
-#      FDRS                        : 58
-#      FDRSE                       : 6
-#      FDS                         : 26
-#      FDSE                        : 84
-#      IDDR                        : 32
-#      ODDR                        : 42
-# RAMS                             : 127
-#      RAM16X1D                    : 103
-#      RAMB16                      : 24
-# Shift Registers                  : 176
-#      SRL16                       : 100
-#      SRL16E                      : 73
-#      SRLC16                      : 3
-# Clock Buffers                    : 12
-#      BUFG                        : 12
-# IO Buffers                       : 226
-#      IBUF                        : 21
-#      IBUFG                       : 2
-#      IOBUF                       : 84
-#      OBUF                        : 111
-#      OBUFT                       : 8
-# DCM_ADVs                         : 4
-#      DCM_ADV                     : 4
-# Others                           : 2
-#      BSCAN_VIRTEX4               : 1
-#      mips_top                    : 1
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 4vsx35ff668-10 
-
- Number of Slices:                     2787  out of  15360    18%  
- Number of Slice Flip Flops:           3515  out of  30720    11%  
- Number of 4 input LUTs:               4700  out of  30720    15%  
-    Number used as logic:              4318
-    Number used as Shift registers:     176
-    Number used as RAMs:                206
- Number of IOs:                         226
- Number of bonded IOBs:                 226  out of    448    50%  
-    IOB Flip Flops:                     285
- Number of FIFO16/RAMB16s:               24  out of    192    12%  
-    Number used as RAMB16s:              24
- Number of GCLKs:                        12  out of     32    37%  
- Number of DCM_ADVs:                      4  out of      8    50%  
-
----------------------------
-Partition Resource Summary:
----------------------------
-
-  No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-TIMING REPORT
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
-      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
-      GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
------------------------------------+---------------------------------------------------------------------------+-------+
-Clock Signal                       | Clock buffer(FF name)                                                     | Load  |
------------------------------------+---------------------------------------------------------------------------+-------+
-sys_clk_in                         | inst_clockgen/inst_DCM_SYS_FX:CLKFX                                       | 3392  |
-sys_clk_in                         | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68    |
-inst_rom_wb/inst_rom/bs_clk0       | BUFG                                                                      | 98    |
-sys_clk_in                         | inst_clockgen/inst_DCM_VGA_FX:CLKFX                                       | 252   |
-sys_ac97_bit_clk                   | IBUF+BUFG                                                                 | 270   |
-sys_sdr_clk_fb                     | inst_clockgen/inst_DCM_SDRCLK_1:CLK270                                    | 32    |
-inst_rom_wb/inst_rom/bs_update0    | BUFG                                                                      | 4     |
------------------------------------+---------------------------------------------------------------------------+-------+
-
-Asynchronous Control Signals Information:
-----------------------------------------
------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
-Control Signal                                                                                       | Buffer(FF name)                                                                                                   | Load  |
------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
-RST_O_7(inst_clockgen/sys_rst_out_13:Q)                                                              | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_4)| 289   |
-inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET)                          | NONE(inst_rom_wb/inst_rom/user_regi_8)                                                                            | 96    |
-RST_O(inst_clockgen/sys_rst_out:Q)                                                                   | NONE(inst_ps2_phy_1/Inst_debounce_data/count_2)                                                                   | 75    |
-inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q)                                 | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_6)                                                                | 52    |
-inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O)                                                | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_1)                                                          | 29    |
-inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O)                                        | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5)                                                    | 21    |
-inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O)                                    | NONE(inst_clockgen/sdr0_lock_inv_shift1)                                                                          | 20    |
-inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O)                                 | NONE(inst_clockgen/reset_cnt_3)                                                                                   | 20    |
-inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O)                                | NONE(inst_clockgen/vga_fx_lock_inv_shift17)                                                                       | 20    |
-rst_in(rst_in1:O)                                                                                    | NONE(rst_in_shift2)                                                                                               | 20    |
-inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O)  | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last)                                                                 | 1     |
-inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O)  | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last)                                                                 | 1     |
-inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last)                                                                | 1     |
-inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last)                                                                | 1     |
-inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O)  | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last)                                                                 | 1     |
-inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O)  | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last)                                                                 | 1     |
-inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last)                                                                | 1     |
-inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last)                                                                | 1     |
------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+-------+
-
-Timing Summary:
----------------
-Speed Grade: -10
-
-   Minimum period: 9.187ns (Maximum Frequency: 108.846MHz)
-   Minimum input arrival time before clock: 8.055ns
-   Maximum output required time after clock: 10.710ns
-   Maximum combinational path delay: 10.288ns
-
-Timing Detail:
---------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'sys_clk_in'
-  Clock period: 9.187ns (frequency: 108.846MHz)
-  Total number of paths / destination ports: 289830 / 8693
--------------------------------------------------------------------------
-Delay:               2.297ns (Levels of Logic = 0)
-  Source:            inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (FF)
-  Destination:       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32 (FF)
-  Source Clock:      sys_clk_in falling
-  Destination Clock: sys_clk_in rising +270
-
-  Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FD_1:C->Q            32   0.307   0.928  inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive)
-     FDR:R                     1.062          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32
-    ----------------------------------------
-    Total                      2.297ns (1.369ns logic, 0.928ns route)
-                                       (59.6% logic, 40.4% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'inst_rom_wb/inst_rom/bs_clk0'
-  Clock period: 2.225ns (frequency: 449.438MHz)
-  Total number of paths / destination ports: 97 / 96
--------------------------------------------------------------------------
-Delay:               2.225ns (Levels of Logic = 0)
-  Source:            inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF)
-  Destination:       inst_rom_wb/inst_rom/user_regi_42 (FF)
-  Source Clock:      inst_rom_wb/inst_rom/bs_clk0 rising
-  Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising
-
-  Data Path: inst_rom_wb/inst_rom/Mshreg_user_regi_42 to inst_rom_wb/inst_rom/user_regi_42
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     SRL16E:CLK->Q         1   2.203   0.000  inst_rom_wb/inst_rom/Mshreg_user_regi_42 (inst_rom_wb/inst_rom/Mshreg_user_regi_42)
-     FDE:D                     0.022          inst_rom_wb/inst_rom/user_regi_42
-    ----------------------------------------
-    Total                      2.225ns (2.225ns logic, 0.000ns route)
-                                       (100.0% logic, 0.0% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk'
-  Clock period: 5.862ns (frequency: 170.582MHz)
-  Total number of paths / destination ports: 3505 / 518
--------------------------------------------------------------------------
-Delay:               5.862ns (Levels of Logic = 6)
-  Source:            inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (FF)
-  Destination:       inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF)
-  Source Clock:      sys_ac97_bit_clk rising
-  Destination Clock: sys_ac97_bit_clk rising
-
-  Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDRE:C->Q            42   0.360   1.295  inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0)
-     LUT3_D:I0->O         25   0.195   1.228  inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27)
-     LUT4:I1->O            1   0.195   0.741  inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26)
-     LUT4:I0->O            1   0.195   0.000  inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105_G (N1375)
-     MUXF5:I1->O           1   0.374   0.688  inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105)
-     LUT4:I1->O            1   0.195   0.000  inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169)
-     MUXF5:I1->O           1   0.374   0.000  inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>)
-     FDCE:D                    0.022          inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_8
-    ----------------------------------------
-    Total                      5.862ns (1.910ns logic, 3.952ns route)
-                                       (32.6% logic, 67.4% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in'
-  Total number of paths / destination ports: 44049 / 2324
--------------------------------------------------------------------------
-Offset:              8.055ns (Levels of Logic = 9)
-  Source:            inst_mips_top:ADDR_O<28> (PAD)
-  Destination:       inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF)
-  Destination Clock: sys_clk_in rising
-
-  Data Path: inst_mips_top:ADDR_O<28> to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-    mips_top:ADDR_O<28>    1   0.000   0.741  inst_mips_top (ADDR_O_cpu<28>)
-     LUT4_D:I0->O          5   0.195   0.711  Mmux_ADDR_O211 (ADDR_O<28>)
-     LUT4:I1->O            3   0.195   0.600  CYC_I_ac971_SW0 (N403)
-     LUT4_D:I2->O          1   0.195   0.523  CYC_I_ac971_1 (CYC_I_ac971)
-     LUT3_L:I2->LO         1   0.195   0.225  SRDY_I26_SW0 (N739)
-     LUT4:I2->O            1   0.195   0.523  SRDY_I26 (SRDY_I26)
-     LUT4_D:I3->LO         1   0.195   0.163  SRDY_I36 (N1558)
-     LUT3:I2->O            5   0.195   0.546  inst_vga_frontend/inst_bus_fifo/rinc1 (inst_vga_frontend/inst_bus_fifo/rinc)
-     LUT4_D:I3->O          1   0.195   0.523  inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N405)
-     LUT3:I2->O          103   0.195   1.205  inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en)
-     FDE:CE                    0.540          inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2
-    ----------------------------------------
-    Total                      8.055ns (2.295ns logic, 5.760ns route)
-                                       (28.5% logic, 71.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_clk0'
-  Total number of paths / destination ports: 99 / 99
--------------------------------------------------------------------------
-Offset:              2.301ns (Levels of Logic = 0)
-  Source:            inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT (PAD)
-  Destination:       inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF)
-  Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising
-
-  Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT to inst_rom_wb/inst_rom/Mshreg_user_regi_42
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-    BSCAN_VIRTEX4:SHIFT   98   0.000   1.186  inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_shift)
-     SRL16E:CE                 1.115          inst_rom_wb/inst_rom/Mshreg_user_regi_42
-    ----------------------------------------
-    Total                      2.301ns (1.115ns logic, 1.186ns route)
-                                       (48.5% logic, 51.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_ac97_bit_clk'
-  Total number of paths / destination ports: 1 / 1
--------------------------------------------------------------------------
-Offset:              1.347ns (Levels of Logic = 1)
-  Source:            sys_ac97_sdata_in (PAD)
-  Destination:       inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0 (FF)
-  Destination Clock: sys_ac97_bit_clk falling
-
-  Data Path: sys_ac97_sdata_in to inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   0.965   0.360  sys_ac97_sdata_in_IBUF (sys_ac97_sdata_in_IBUF)
-     FDC_1:D                   0.022          inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0
-    ----------------------------------------
-    Total                      1.347ns (0.987ns logic, 0.360ns route)
-                                       (73.3% logic, 26.7% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_sdr_clk_fb'
-  Total number of paths / destination ports: 32 / 32
--------------------------------------------------------------------------
-Offset:              6.702ns (Levels of Logic = 1)
-  Source:            sys_sdr_data<31> (PAD)
-  Destination:       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data (FF)
-  Destination Clock: sys_sdr_clk_fb rising +270
-
-  Data Path: sys_sdr_data<31> to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IOBUF:IO->O           1   0.965   0.360  sys_sdr_data_31_IOBUF (N407)
-     IDDR:D                    5.377          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data
-    ----------------------------------------
-    Total                      6.702ns (6.342ns logic, 0.360ns route)
-                                       (94.6% logic, 5.4% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_update0'
-  Total number of paths / destination ports: 16 / 16
--------------------------------------------------------------------------
-Offset:              1.341ns (Levels of Logic = 0)
-  Source:            inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL (PAD)
-  Destination:       inst_rom_wb/inst_rom/Mram_word_array3 (RAM)
-  Destination Clock: inst_rom_wb/inst_rom/bs_update0 rising
-
-  Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL to inst_rom_wb/inst_rom/Mram_word_array3
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-    BSCAN_VIRTEX4:SEL     16   0.000   0.593  inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_sel)
-     RAMB16:WEA0               0.748          inst_rom_wb/inst_rom/Mram_word_array3
-    ----------------------------------------
-    Total                      1.341ns (0.748ns logic, 0.593ns route)
-                                       (55.8% logic, 44.2% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in'
-  Total number of paths / destination ports: 19309 / 226
--------------------------------------------------------------------------
-Offset:              10.710ns (Levels of Logic = 12)
-  Source:            inst_vga_frontend/s_FSM_FFd2_1 (FF)
-  Destination:       inst_mips_top:DAT_I<13> (PAD)
-  Source Clock:      sys_clk_in rising
-
-  Data Path: inst_vga_frontend/s_FSM_FFd2_1 to inst_mips_top:DAT_I<13>
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDRS:C->Q             1   0.360   0.585  inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1)
-     LUT2_D:I0->O          3   0.195   0.538  inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src)
-     LUT4_D:I3->LO         1   0.195   0.163  inst_vga_frontend/CYC_O1 (N1553)
-     LUT4:I3->O            9   0.195   0.632  CYC_O1 (CYC_O)
-     LUT4_D:I3->O         17   0.195   0.743  CYC_I_ac971 (N57)
-     LUT4_D:I3->O         48   0.195   1.371  CYC_I_ac972 (CYC_I_ac97)
-     LUT4:I0->O            1   0.195   0.741  MDAT_I<13>36_SW0 (N1207)
-     LUT4:I0->O            1   0.195   0.585  MDAT_I<13>36 (MDAT_I<13>36)
-     LUT4:I2->O            1   0.195   0.741  MDAT_I<13>84_SW0 (N903)
-     LUT4:I0->O            1   0.195   0.741  MDAT_I<13>84_SW1 (N1340)
-     LUT4:I0->O            1   0.195   0.585  MDAT_I<13>84 (MDAT_I<13>84)
-     LUT4:I2->O            1   0.195   0.585  MDAT_I<13>170_SW0 (N875)
-     LUT4:I2->O            0   0.195   0.000  MDAT_I<13>170 (MDAT_I<13>)
-    mips_top:DAT_I<13>         0.000          inst_mips_top
-    ----------------------------------------
-    Total                     10.710ns (2.700ns logic, 8.010ns route)
-                                       (25.2% logic, 74.8% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk'
-  Total number of paths / destination ports: 2 / 2
--------------------------------------------------------------------------
-Offset:              4.677ns (Levels of Logic = 1)
-  Source:            inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (FF)
-  Destination:       sys_ac97_sdata_out (PAD)
-  Source Clock:      sys_ac97_bit_clk rising
-
-  Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out to sys_ac97_sdata_out
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              1   0.360   0.360  inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out)
-     OBUF:I->O                 3.957          sys_ac97_sdata_out_OBUF (sys_ac97_sdata_out)
-    ----------------------------------------
-    Total                      4.677ns (4.317ns logic, 0.360ns route)
-                                       (92.3% logic, 7.7% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'inst_rom_wb/inst_rom/bs_clk0'
-  Total number of paths / destination ports: 1 / 1
--------------------------------------------------------------------------
-Offset:              0.720ns (Levels of Logic = 0)
-  Source:            inst_rom_wb/inst_rom/user_rego_0 (FF)
-  Destination:       inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO (PAD)
-  Source Clock:      inst_rom_wb/inst_rom/bs_clk0 rising
-
-  Data Path: inst_rom_wb/inst_rom/user_rego_0 to inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              1   0.360   0.360  inst_rom_wb/inst_rom/user_rego_0 (inst_rom_wb/inst_rom/user_rego_0)
-    BSCAN_VIRTEX4:TDO          0.000          inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1
-    ----------------------------------------
-    Total                      0.720ns (0.360ns logic, 0.360ns route)
-                                       (50.0% logic, 50.0% route)
-
-=========================================================================
-Timing constraint: Default path analysis
-  Total number of paths / destination ports: 5396 / 38
--------------------------------------------------------------------------
-Delay:               10.288ns (Levels of Logic = 11)
-  Source:            inst_mips_top:ADDR_O<28> (PAD)
-  Destination:       inst_mips_top:DAT_I<13> (PAD)
-
-  Data Path: inst_mips_top:ADDR_O<28> to inst_mips_top:DAT_I<13>
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-    mips_top:ADDR_O<28>    1   0.000   0.741  inst_mips_top (ADDR_O_cpu<28>)
-     LUT4_D:I0->O          5   0.195   0.711  Mmux_ADDR_O211 (ADDR_O<28>)
-     LUT4:I1->O            3   0.195   0.600  CYC_I_ac971_SW0 (N403)
-     LUT4_D:I2->O         17   0.195   0.743  CYC_I_ac971 (N57)
-     LUT4_D:I3->O         48   0.195   1.371  CYC_I_ac972 (CYC_I_ac97)
-     LUT4:I0->O            1   0.195   0.741  MDAT_I<13>36_SW0 (N1207)
-     LUT4:I0->O            1   0.195   0.585  MDAT_I<13>36 (MDAT_I<13>36)
-     LUT4:I2->O            1   0.195   0.741  MDAT_I<13>84_SW0 (N903)
-     LUT4:I0->O            1   0.195   0.741  MDAT_I<13>84_SW1 (N1340)
-     LUT4:I0->O            1   0.195   0.585  MDAT_I<13>84 (MDAT_I<13>84)
-     LUT4:I2->O            1   0.195   0.585  MDAT_I<13>170_SW0 (N875)
-     LUT4:I2->O            0   0.195   0.000  MDAT_I<13>170 (MDAT_I<13>)
-    mips_top:DAT_I<13>         0.000          inst_mips_top
-    ----------------------------------------
-    Total                     10.288ns (2.145ns logic, 8.143ns route)
-                                       (20.8% logic, 79.2% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 128.00 secs
-Total CPU time to Xst completion: 128.61 secs
- 
---> 
-
-Total memory usage is 357364 kilobytes
-
-Number of errors   :    0 (   0 filtered)
-Number of warnings : 1003 (   0 filtered)
-Number of infos    :  126 (   0 filtered)
-
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr
deleted file mode 100644
index 1852459..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.twr
+++ /dev/null
@@ -1,1177 +0,0 @@
---------------------------------------------------------------------------------
-Release 10.1.03 Trace  (nt)
-Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
-
-C:\Programme\Xilinx101\ISE\bin\nt\unwrapped\trce.exe -ise
-W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -v 3 -s 10
--xml mips_sys mips_sys.ncd -o mips_sys.twr mips_sys.pcf -ucf
-W:/vhdl/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
-
-Design file:              mips_sys.ncd
-Physical constraint file: mips_sys.pcf
-Device,package,speed:     xc4vsx35,ff668,-10 (PRODUCTION 1.68 2008-07-25, STEPPING level ES)
-Report level:             verbose report
-
-Environment Variable      Effect 
---------------------      ------ 
-NONE                      No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
-   option. All paths that are not constrained will be reported in the 
-   unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
-   a 50 Ohm transmission line loading model.  For the details of this model, 
-   and for more information on accounting for different loading conditions, 
-   please see the device datasheet.
-
-================================================================================
-Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%;
-
- 3447 paths analyzed, 643 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum period is   6.700ns.
---------------------------------------------------------------------------------
-Slack:                  36.650ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 (FF)
-  Requirement:          40.000ns
-  Data Path Delay:      3.345ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.005ns (2.621 - 2.626)
-  Source Clock:         sys_ac97_bit_clk_IBUF falling at 40.000ns
-  Destination Clock:    sys_ac97_bit_clk_IBUF rising at 80.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X33Y79.YQ      Tcko                  0.286   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11>
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11
-    SLICE_X58Y78.BY      net (fanout=14)       2.779   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11>
-    SLICE_X58Y78.CLK     Tdick                 0.280   inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11
-    -------------------------------------------------  ---------------------------
-    Total                                      3.345ns (0.566ns logic, 2.779ns route)
-                                                       (16.9% logic, 83.1% route)
-
---------------------------------------------------------------------------------
-Slack:                  37.046ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF)
-  Requirement:          40.000ns
-  Data Path Delay:      2.678ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.276ns (2.456 - 2.732)
-  Source Clock:         sys_ac97_bit_clk_IBUF falling at 40.000ns
-  Destination Clock:    sys_ac97_bit_clk_IBUF rising at 80.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X27Y85.YQ      Tcko                  0.286   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15>
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15
-    SLICE_X47Y78.BY      net (fanout=13)       2.100   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15>
-    SLICE_X47Y78.CLK     Tdick                 0.292   inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15>
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15
-    -------------------------------------------------  ---------------------------
-    Total                                      2.678ns (0.578ns logic, 2.100ns route)
-                                                       (21.6% logic, 78.4% route)
-
---------------------------------------------------------------------------------
-Slack:                  37.336ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 (FF)
-  Requirement:          40.000ns
-  Data Path Delay:      2.643ns (Levels of Logic = 0)
-  Clock Path Skew:      -0.021ns (2.621 - 2.642)
-  Source Clock:         sys_ac97_bit_clk_IBUF falling at 40.000ns
-  Destination Clock:    sys_ac97_bit_clk_IBUF rising at 80.000ns
-  Clock Uncertainty:    0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X32Y89.YQ      Tcko                  0.307   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10>
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10
-    SLICE_X58Y78.BX      net (fanout=13)       2.057   inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10>
-    SLICE_X58Y78.CLK     Tdick                 0.279   inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
-                                                       inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
-    -------------------------------------------------  ---------------------------
-    Total                                      2.643ns (0.586ns logic, 2.057ns route)
-                                                       (22.2% logic, 77.8% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%;
-
- 450849 paths analyzed, 11154 endpoints analyzed, 9 failing endpoints
- 9 timing errors detected. (9 setup errors, 0 hold errors)
- Minimum period is  10.193ns.
---------------------------------------------------------------------------------
-Slack:                  -0.293ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               arb_gnt_0 (FF)
-  Destination:          inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F (RAM)
-  Requirement:          9.900ns
-  Data Path Delay:      10.084ns (Levels of Logic = 10)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 9.900ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X40Y64.XQ      Tcko                  0.360   arb_gnt<0>
-                                                       arb_gnt_0
-    SLICE_X38Y63.G2      net (fanout=117)      1.138   arb_gnt<0>
-    SLICE_X38Y63.Y       Tilo                  0.195   N739
-                                                       Mmux_ADDR_O241
-    SLICE_X40Y59.BX      net (fanout=8)        0.973   ADDR_O<30>
-    SLICE_X40Y59.XMUX    Tbxx                  0.513   N105
-                                                       CYC_O1_SW1
-    SLICE_X40Y61.G4      net (fanout=2)        0.416   N105
-    SLICE_X40Y61.Y       Tilo                  0.195   CYC_I_usb
-                                                       CYC_I_ac971
-    SLICE_X38Y67.G4      net (fanout=15)       0.917   CYC_I_ac971
-    SLICE_X38Y67.Y       Tilo                  0.195   MDAT_I<8>27
-                                                       CYC_I_gpio1
-    SLICE_X36Y60.G3      net (fanout=27)       0.668   CYC_I_gpio
-    SLICE_X36Y60.Y       Tilo                  0.195   N54
-                                                       MDAT_I<2>56_SW0_SW0
-    SLICE_X47Y59.G4      net (fanout=1)        0.949   N135
-    SLICE_X47Y59.Y       Tilo                  0.194   MDAT_I<2>56
-                                                       MDAT_I<2>56_SW0
-    SLICE_X47Y59.F4      net (fanout=1)        0.159   N1197
-    SLICE_X47Y59.X       Tilo                  0.194   MDAT_I<2>56
-                                                       MDAT_I<2>56
-    SLICE_X44Y57.G4      net (fanout=1)        0.384   MDAT_I<2>56
-    SLICE_X44Y57.Y       Tilo                  0.195   MDAT_I<2>
-                                                       MDAT_I<2>89_SW0
-    SLICE_X44Y57.F3      net (fanout=1)        0.213   N1324
-    SLICE_X44Y57.X       Tilo                  0.195   MDAT_I<2>
-                                                       MDAT_I<2>89
-    SLICE_X34Y53.BY      net (fanout=1)        0.774   MDAT_I<2>
-    SLICE_X34Y53.CLK     Tds                   1.062   inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<2>
-                                                       inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F
-    -------------------------------------------------  ---------------------------
-    Total                                     10.084ns (3.493ns logic, 6.591ns route)
-                                                       (34.6% logic, 65.4% route)
-
---------------------------------------------------------------------------------
-Slack:                  -0.194ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               arb_gnt_0 (FF)
-  Destination:          inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM)
-  Requirement:          9.900ns
-  Data Path Delay:      9.985ns (Levels of Logic = 10)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 9.900ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X40Y64.XQ      Tcko                  0.360   arb_gnt<0>
-                                                       arb_gnt_0
-    SLICE_X38Y63.G2      net (fanout=117)      1.138   arb_gnt<0>
-    SLICE_X38Y63.Y       Tilo                  0.195   N739
-                                                       Mmux_ADDR_O241
-    SLICE_X40Y59.BX      net (fanout=8)        0.973   ADDR_O<30>
-    SLICE_X40Y59.XMUX    Tbxx                  0.513   N105
-                                                       CYC_O1_SW1
-    SLICE_X40Y61.G4      net (fanout=2)        0.416   N105
-    SLICE_X40Y61.Y       Tilo                  0.195   CYC_I_usb
-                                                       CYC_I_ac971
-    SLICE_X38Y67.G4      net (fanout=15)       0.917   CYC_I_ac971
-    SLICE_X38Y67.Y       Tilo                  0.195   MDAT_I<8>27
-                                                       CYC_I_gpio1
-    SLICE_X42Y64.G3      net (fanout=27)       0.918   CYC_I_gpio
-    SLICE_X42Y64.Y       Tilo                  0.195   N851
-                                                       MDAT_I<0>56_SW0_SW0
-    SLICE_X45Y64.G4      net (fanout=1)        0.322   N143
-    SLICE_X45Y64.Y       Tilo                  0.194   MDAT_I<0>56
-                                                       MDAT_I<0>56_SW0
-    SLICE_X45Y64.F3      net (fanout=1)        0.222   N1205
-    SLICE_X45Y64.X       Tilo                  0.194   MDAT_I<0>56
-                                                       MDAT_I<0>56
-    SLICE_X40Y53.G2      net (fanout=1)        0.757   MDAT_I<0>56
-    SLICE_X40Y53.Y       Tilo                  0.195   MDAT_I<0>
-                                                       MDAT_I<0>89_SW0
-    SLICE_X40Y53.F3      net (fanout=1)        0.213   N1332
-    SLICE_X40Y53.X       Tilo                  0.195   MDAT_I<0>
-                                                       MDAT_I<0>89
-    SLICE_X38Y53.BY      net (fanout=1)        0.616   MDAT_I<0>
-    SLICE_X38Y53.CLK     Tds                   1.062   inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0>
-                                                       inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
-    -------------------------------------------------  ---------------------------
-    Total                                      9.985ns (3.493ns logic, 6.492ns route)
-                                                       (35.0% logic, 65.0% route)
-
---------------------------------------------------------------------------------
-Slack:                  -0.174ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               arb_gnt_0 (FF)
-  Destination:          inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM)
-  Requirement:          9.900ns
-  Data Path Delay:      9.965ns (Levels of Logic = 10)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 9.900ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X40Y64.XQ      Tcko                  0.360   arb_gnt<0>
-                                                       arb_gnt_0
-    SLICE_X38Y63.G2      net (fanout=117)      1.138   arb_gnt<0>
-    SLICE_X38Y63.Y       Tilo                  0.195   N739
-                                                       Mmux_ADDR_O241
-    SLICE_X40Y59.BX      net (fanout=8)        0.973   ADDR_O<30>
-    SLICE_X40Y59.XMUX    Tbxx                  0.513   N105
-                                                       CYC_O1_SW1
-    SLICE_X40Y61.G4      net (fanout=2)        0.416   N105
-    SLICE_X40Y61.Y       Tilo                  0.195   CYC_I_usb
-                                                       CYC_I_ac971
-    SLICE_X39Y61.G4      net (fanout=15)       0.719   CYC_I_ac971
-    SLICE_X39Y61.Y       Tilo                  0.194   N1207
-                                                       CYC_I_ac972
-    SLICE_X42Y64.G2      net (fanout=58)       1.097   CYC_I_ac97
-    SLICE_X42Y64.Y       Tilo                  0.195   N851
-                                                       MDAT_I<0>56_SW0_SW0
-    SLICE_X45Y64.G4      net (fanout=1)        0.322   N143
-    SLICE_X45Y64.Y       Tilo                  0.194   MDAT_I<0>56
-                                                       MDAT_I<0>56_SW0
-    SLICE_X45Y64.F3      net (fanout=1)        0.222   N1205
-    SLICE_X45Y64.X       Tilo                  0.194   MDAT_I<0>56
-                                                       MDAT_I<0>56
-    SLICE_X40Y53.G2      net (fanout=1)        0.757   MDAT_I<0>56
-    SLICE_X40Y53.Y       Tilo                  0.195   MDAT_I<0>
-                                                       MDAT_I<0>89_SW0
-    SLICE_X40Y53.F3      net (fanout=1)        0.213   N1332
-    SLICE_X40Y53.X       Tilo                  0.195   MDAT_I<0>
-                                                       MDAT_I<0>89
-    SLICE_X38Y53.BY      net (fanout=1)        0.616   MDAT_I<0>
-    SLICE_X38Y53.CLK     Tds                   1.062   inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0>
-                                                       inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
-    -------------------------------------------------  ---------------------------
-    Total                                      9.965ns (3.492ns logic, 6.473ns route)
-                                                       (35.0% logic, 65.0% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%;
-
- 1524 paths analyzed, 435 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum period is   7.330ns.
---------------------------------------------------------------------------------
-Slack:                  0.170ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty (FF)
-  Requirement:          7.500ns
-  Data Path Delay:      7.206ns (Levels of Logic = 6)
-  Clock Path Skew:      0.000ns
-  Source Clock:         sdram_clk0 rising at 0.000ns
-  Destination Clock:    sdram_clk0 rising at 7.500ns
-  Clock Uncertainty:    0.124ns
-
-  Clock Uncertainty:          0.124ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X1Y18.DOB26   Trcko_DORB            2.100   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
-    SLICE_X14Y155.G1     net (fanout=15)       1.217   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26>
-    SLICE_X14Y155.Y      Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0
-    SLICE_X16Y156.G2     net (fanout=6)        0.794   N318
-    SLICE_X16Y156.Y      Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<3>
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc
-    SLICE_X17Y155.G1     net (fanout=7)        0.595   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc
-    SLICE_X17Y155.XMUX   Tif5x                 0.574   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<5>
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>1
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>_f5
-    SLICE_X16Y157.F3     net (fanout=3)        0.464   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<5>
-    SLICE_X16Y157.X      Tilo                  0.195   N1006
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677_SW0
-    SLICE_X17Y156.G3     net (fanout=1)        0.226   N1006
-    SLICE_X17Y156.Y      Tilo                  0.194   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677
-    SLICE_X17Y156.F3     net (fanout=1)        0.222   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677/O
-    SLICE_X17Y156.CLK    Tfck                  0.235   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty6100
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
-    -------------------------------------------------  ---------------------------
-    Total                                      7.206ns (3.688ns logic, 3.518ns route)
-                                                       (51.2% logic, 48.8% route)
-
---------------------------------------------------------------------------------
-Slack:                  0.180ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 (FF)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5 (FF)
-  Requirement:          3.750ns
-  Data Path Delay:      3.446ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         sdram_clk0 rising at 0.000ns
-  Destination Clock:    sdram_clk0 falling at 3.750ns
-  Clock Uncertainty:    0.124ns
-
-  Clock Uncertainty:          0.124ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X6Y167.XQ      Tcko                  0.360   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
-    SLICE_X6Y171.G3      net (fanout=9)        0.927   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
-    SLICE_X6Y171.Y       Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_5_mux00041
-    OLOGIC_X0Y187.D1     net (fanout=1)        1.337   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5
-    OLOGIC_X0Y187.CLK    Todck                 0.627   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<5>
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5
-    -------------------------------------------------  ---------------------------
-    Total                                      3.446ns (1.182ns logic, 2.264ns route)
-                                                       (34.3% logic, 65.7% route)
-
---------------------------------------------------------------------------------
-Slack:                  0.190ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3 (FF)
-  Requirement:          7.500ns
-  Data Path Delay:      7.186ns (Levels of Logic = 5)
-  Clock Path Skew:      0.000ns
-  Source Clock:         sdram_clk0 rising at 0.000ns
-  Destination Clock:    sdram_clk0 rising at 7.500ns
-  Clock Uncertainty:    0.124ns
-
-  Clock Uncertainty:          0.124ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    RAMB16_X1Y18.DOB26   Trcko_DORB            2.100   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
-    SLICE_X14Y155.G1     net (fanout=15)       1.217   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26>
-    SLICE_X14Y155.Y      Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0
-    SLICE_X13Y158.G2     net (fanout=6)        0.745   N318
-    SLICE_X13Y158.Y      Tilo                  0.194   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6
-    SLICE_X13Y158.F3     net (fanout=2)        0.228   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N24
-    SLICE_X13Y158.X      Tilo                  0.194   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en1
-    SLICE_X13Y161.G2     net (fanout=6)        0.562   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
-    SLICE_X13Y161.Y      Tilo                  0.194   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001_SW0
-    SLICE_X13Y161.F4     net (fanout=2)        0.168   N316
-    SLICE_X13Y161.X      Tilo                  0.194   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
-    SLICE_X15Y160.CE     net (fanout=4)        0.642   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
-    SLICE_X15Y160.CLK    Tceck                 0.553   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt<3>
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3
-    -------------------------------------------------  ---------------------------
-    Total                                      7.186ns (3.624ns logic, 3.562ns route)
-                                                       (50.4% logic, 49.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG;
-
- 24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
---------------------------------------------------------------------------------
-Delay:                  9.594ns (data path - clock path skew + uncertainty)
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF)
-  Data Path Delay:      3.036ns (Levels of Logic = 1)
-  Clock Path Skew:      -6.314ns (-2.401 - 3.913)
-  Source Clock:         CLK_O rising
-  Destination Clock:    sdram_clk0 rising
-  Clock Uncertainty:    0.244ns
-
-  Clock Uncertainty:          0.244ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.120ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X9Y176.YQ      Tcko                  0.340   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-    SLICE_X4Y154.G1      net (fanout=20)       1.519   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-    SLICE_X4Y154.Y       Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141
-    SLICE_X5Y154.CE      net (fanout=1)        0.429   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke
-    SLICE_X5Y154.CLK     Tceck                 0.553   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-    -------------------------------------------------  ---------------------------
-    Total                                      3.036ns (1.088ns logic, 1.948ns route)
-                                                       (35.8% logic, 64.2% route)
-
---------------------------------------------------------------------------------
-Delay:                  9.133ns (data path - clock path skew + uncertainty)
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF)
-  Data Path Delay:      2.602ns (Levels of Logic = 1)
-  Clock Path Skew:      -6.287ns (-2.401 - 3.886)
-  Source Clock:         CLK_O rising
-  Destination Clock:    sdram_clk0 rising
-  Clock Uncertainty:    0.244ns
-
-  Clock Uncertainty:          0.244ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.120ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X11Y167.YQ     Tcko                  0.340   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
-    SLICE_X4Y154.G4      net (fanout=9)        1.085   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
-    SLICE_X4Y154.Y       Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141
-    SLICE_X5Y154.CE      net (fanout=1)        0.429   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke
-    SLICE_X5Y154.CLK     Tceck                 0.553   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
-    -------------------------------------------------  ---------------------------
-    Total                                      2.602ns (1.088ns logic, 1.514ns route)
-                                                       (41.8% logic, 58.2% route)
-
---------------------------------------------------------------------------------
-Delay:                  8.894ns (data path - clock path skew + uncertainty)
-  Source:               inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF)
-  Destination:          inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF)
-  Data Path Delay:      2.328ns (Levels of Logic = 2)
-  Clock Path Skew:      -6.322ns (-2.409 - 3.913)
-  Source Clock:         CLK_O rising
-  Destination Clock:    sdram_clk0 rising
-  Clock Uncertainty:    0.244ns
-
-  Clock Uncertainty:          0.244ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.248ns
-    Phase Error (PE):           0.120ns
-
-  Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X9Y176.YQ      Tcko                  0.340   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-    SLICE_X10Y162.F2     net (fanout=20)       1.171   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
-    SLICE_X10Y162.X      Tilo                  0.195   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
-    SLICE_X11Y162.F1     net (fanout=1)        0.387   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
-    SLICE_X11Y162.CLK    Tfck                  0.235   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62
-                                                       inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
-    -------------------------------------------------  ---------------------------
-    Total                                      2.328ns (0.770ns logic, 1.558ns route)
-                                                       (33.1% logic, 66.9% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%;
-
- 12615 paths analyzed, 693 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum period is   7.614ns.
---------------------------------------------------------------------------------
-Slack:                  0.386ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF)
-  Destination:          inst_vga_frontend/inst_vga_backend/Result<5>1_FRB (FF)
-  Requirement:          8.000ns
-  Data Path Delay:      7.479ns (Levels of Logic = 5)
-  Clock Path Skew:      0.000ns
-  Source Clock:         vga_clk rising at 0.000ns
-  Destination Clock:    vga_clk rising at 8.000ns
-  Clock Uncertainty:    0.135ns
-
-  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.270ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y177.YQ     Tcko                  0.360   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7
-    SLICE_X55Y173.F4     net (fanout=2)        1.037   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
-    SLICE_X55Y173.X      Tilo                  0.194   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3>
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311
-    SLICE_X54Y173.BX     net (fanout=3)        0.154   inst_vga_frontend/inst_vga_backend/N13
-    SLICE_X54Y173.XMUX   Tbxx                  0.513   inst_vga_frontend/inst_vga_backend/N15
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5
-    SLICE_X54Y171.BX     net (fanout=3)        0.827   inst_vga_frontend/inst_vga_backend/N15
-    SLICE_X54Y171.XMUX   Tbxx                  0.513   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5
-    SLICE_X54Y170.G1     net (fanout=1)        0.587   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
-    SLICE_X54Y170.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129
-    SLICE_X54Y172.G1     net (fanout=2)        0.568   inst_vga_frontend/inst_vga_backend/N11
-    SLICE_X54Y172.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001
-    SLICE_X60Y179.SR     net (fanout=14)       1.179   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000
-    SLICE_X60Y179.CLK    Tsrck                 1.157   inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
-                                                       inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
-    -------------------------------------------------  ---------------------------
-    Total                                      7.479ns (3.127ns logic, 4.352ns route)
-                                                       (41.8% logic, 58.2% route)
-
---------------------------------------------------------------------------------
-Slack:                  0.496ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF)
-  Destination:          inst_vga_frontend/inst_vga_backend/Result<4>1_FRB (FF)
-  Requirement:          8.000ns
-  Data Path Delay:      7.369ns (Levels of Logic = 5)
-  Clock Path Skew:      0.000ns
-  Source Clock:         vga_clk rising at 0.000ns
-  Destination Clock:    vga_clk rising at 8.000ns
-  Clock Uncertainty:    0.135ns
-
-  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.270ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X60Y177.YQ     Tcko                  0.360   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7
-    SLICE_X55Y173.F4     net (fanout=2)        1.037   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
-    SLICE_X55Y173.X      Tilo                  0.194   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3>
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311
-    SLICE_X54Y173.BX     net (fanout=3)        0.154   inst_vga_frontend/inst_vga_backend/N13
-    SLICE_X54Y173.XMUX   Tbxx                  0.513   inst_vga_frontend/inst_vga_backend/N15
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5
-    SLICE_X54Y171.BX     net (fanout=3)        0.827   inst_vga_frontend/inst_vga_backend/N15
-    SLICE_X54Y171.XMUX   Tbxx                  0.513   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5
-    SLICE_X54Y170.G1     net (fanout=1)        0.587   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
-    SLICE_X54Y170.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129
-    SLICE_X54Y172.G1     net (fanout=2)        0.568   inst_vga_frontend/inst_vga_backend/N11
-    SLICE_X54Y172.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002
-                                                       inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001
-    SLICE_X59Y178.SR     net (fanout=14)       1.189   inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000
-    SLICE_X59Y178.CLK    Tsrck                 1.037   inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
-                                                       inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
-    -------------------------------------------------  ---------------------------
-    Total                                      7.369ns (3.007ns logic, 4.362ns route)
-                                                       (40.8% logic, 59.2% route)
-
---------------------------------------------------------------------------------
-Slack:                  0.505ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 (FF)
-  Destination:          inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM)
-  Requirement:          8.000ns
-  Data Path Delay:      7.156ns (Levels of Logic = 7)
-  Clock Path Skew:      -0.204ns (2.503 - 2.707)
-  Source Clock:         vga_clk rising at 0.000ns
-  Destination Clock:    vga_clk rising at 8.000ns
-  Clock Uncertainty:    0.135ns
-
-  Clock Uncertainty:          0.135ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.270ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X56Y157.XQ     Tcko                  0.360   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1
-    SLICE_X57Y156.G3     net (fanout=3)        0.633   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>
-    SLICE_X57Y156.COUT   Topcyg                0.559   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>_rt
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
-    SLICE_X57Y157.CIN    net (fanout=1)        0.000   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
-    SLICE_X57Y157.COUT   Tbyp                  0.086   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
-    SLICE_X57Y158.CIN    net (fanout=1)        0.000   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
-    SLICE_X57Y158.COUT   Tbyp                  0.086   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<4>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
-    SLICE_X57Y159.CIN    net (fanout=1)        0.000   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
-    SLICE_X57Y159.COUT   Tbyp                  0.086   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<6>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
-    SLICE_X57Y160.CIN    net (fanout=1)        0.000   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
-    SLICE_X57Y160.COUT   Tbyp                  0.086   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<8>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
-    SLICE_X57Y161.CIN    net (fanout=1)        0.000   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
-    SLICE_X57Y161.XMUX   Tcinx                 0.438   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<11>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<10>
-    SLICE_X57Y153.G4     net (fanout=1)        0.728   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<10>
-    SLICE_X57Y153.Y      Tilo                  0.194   inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<9>
-                                                       inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<10>1
-    RAMB16_X4Y13.ADDRB13 net (fanout=10)       3.474   inst_vga_frontend/inst_linefifo/ptr_r<10>
-    RAMB16_X4Y13.CLKB    Trcck_ADDRB           0.426   inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
-                                                       inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
-    -------------------------------------------------  ---------------------------
-    Total                                      7.156ns (2.321ns logic, 4.835ns route)
-                                                       (32.4% logic, 67.6% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: PATH "TS_unrelate_VGA_path" TIG;
-
- 64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
---------------------------------------------------------------------------------
-Delay:                  6.138ns (data path - clock path skew + uncertainty)
-  Source:               inst_vga_frontend/cg_color_2_5 (FF)
-  Destination:          inst_vga_frontend/inst_vga_backend/vga_blue_5 (FF)
-  Data Path Delay:      5.597ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising
-  Destination Clock:    vga_clk rising
-  Clock Uncertainty:    0.541ns
-
-  Clock Uncertainty:          0.541ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.347ns
-    Phase Error (PE):           0.367ns
-
-  Maximum Data Path: inst_vga_frontend/cg_color_2_5 to inst_vga_frontend/inst_vga_backend/vga_blue_5
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X47Y109.YQ     Tcko                  0.340   inst_vga_frontend/cg_color_2_4
-                                                       inst_vga_frontend/cg_color_2_5
-    SLICE_X65Y142.G1     net (fanout=2)        2.110   inst_vga_frontend/cg_color_2_5
-    SLICE_X65Y142.Y      Tilo                  0.194   inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
-                                                       inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
-    OLOGIC_X2Y171.REV    net (fanout=1)        1.656   inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
-    OLOGIC_X2Y171.CLK    Tosrck                1.297   inst_vga_frontend/inst_vga_backend/vga_blue<5>
-                                                       inst_vga_frontend/inst_vga_backend/vga_blue_5
-    -------------------------------------------------  ---------------------------
-    Total                                      5.597ns (1.831ns logic, 3.766ns route)
-                                                       (32.7% logic, 67.3% route)
-
---------------------------------------------------------------------------------
-Delay:                  6.087ns (data path - clock path skew + uncertainty)
-  Source:               inst_vga_frontend/cg_color_0_7 (FF)
-  Destination:          inst_vga_frontend/inst_vga_backend/vga_red_7 (FF)
-  Data Path Delay:      5.546ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising
-  Destination Clock:    vga_clk rising
-  Clock Uncertainty:    0.541ns
-
-  Clock Uncertainty:          0.541ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.347ns
-    Phase Error (PE):           0.367ns
-
-  Maximum Data Path: inst_vga_frontend/cg_color_0_7 to inst_vga_frontend/inst_vga_backend/vga_red_7
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X48Y107.XQ     Tcko                  0.360   inst_vga_frontend/cg_color_0_7
-                                                       inst_vga_frontend/cg_color_0_7
-    SLICE_X66Y137.G2     net (fanout=2)        2.036   inst_vga_frontend/cg_color_0_7
-    SLICE_X66Y137.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
-                                                       inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
-    OLOGIC_X2Y157.REV    net (fanout=1)        1.658   inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
-    OLOGIC_X2Y157.CLK    Tosrck                1.297   inst_vga_frontend/inst_vga_backend/vga_red<7>
-                                                       inst_vga_frontend/inst_vga_backend/vga_red_7
-    -------------------------------------------------  ---------------------------
-    Total                                      5.546ns (1.852ns logic, 3.694ns route)
-                                                       (33.4% logic, 66.6% route)
-
---------------------------------------------------------------------------------
-Delay:                  6.021ns (data path - clock path skew + uncertainty)
-  Source:               inst_vga_frontend/cg_color_1_3 (FF)
-  Destination:          inst_vga_frontend/inst_vga_backend/vga_green_3 (FF)
-  Data Path Delay:      5.480ns (Levels of Logic = 1)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising
-  Destination Clock:    vga_clk rising
-  Clock Uncertainty:    0.541ns
-
-  Clock Uncertainty:          0.541ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.347ns
-    Phase Error (PE):           0.367ns
-
-  Maximum Data Path: inst_vga_frontend/cg_color_1_3 to inst_vga_frontend/inst_vga_backend/vga_green_3
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X50Y108.YQ     Tcko                  0.360   inst_vga_frontend/cg_color_1_3
-                                                       inst_vga_frontend/cg_color_1_3
-    SLICE_X66Y133.G3     net (fanout=2)        2.016   inst_vga_frontend/cg_color_1_3
-    SLICE_X66Y133.Y      Tilo                  0.195   inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
-                                                       inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
-    OLOGIC_X2Y148.REV    net (fanout=1)        1.612   inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
-    OLOGIC_X2Y148.CLK    Tosrck                1.297   inst_vga_frontend/inst_vga_backend/vga_green<3>
-                                                       inst_vga_frontend/inst_vga_backend/vga_green_3
-    -------------------------------------------------  ---------------------------
-    Total                                      5.480ns (1.852ns logic, 3.628ns route)
-                                                       (33.8% logic, 66.2% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%;
-
- 864692 paths analyzed, 11651 endpoints analyzed, 1 failing endpoint
- 1 timing error detected. (1 setup error, 0 hold errors)
- Minimum period is  10.294ns.
---------------------------------------------------------------------------------
-Slack:                  -0.197ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_mips_top/inst_pipeline/bcu_op_a_2 (FF)
-  Destination:          inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
-  Requirement:          4.950ns
-  Data Path Delay:      4.917ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.170ns (2.881 - 3.051)
-  Source Clock:         cpu_clk rising at 0.000ns
-  Destination Clock:    cpu_clk falling at 4.950ns
-  Clock Uncertainty:    0.060ns
-
-  Clock Uncertainty:          0.060ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.120ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X8Y30.XQ       Tcko                  0.360   inst_mips_top/inst_pipeline/bcu_op_a<2>
-                                                       inst_mips_top/inst_pipeline/bcu_op_a_2
-    SLICE_X10Y30.G3      net (fanout=1)        0.816   inst_mips_top/inst_pipeline/bcu_op_a<2>
-    SLICE_X10Y30.COUT    Topcyg                0.561   inst_mips_top/inst_pipeline/EX_stage.reg_a_17
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_a<1>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_b<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/EX_stage.reg_a_16
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
-    SLICE_X13Y42.G4      net (fanout=2)        1.015   inst_mips_top/inst_pipeline/bcu_flags_eq
-    SLICE_X13Y42.Y       Tilo                  0.194   inst_mips_top/inst_pipeline/pc.branch_take
-                                                       _LC_2_0
-    SLICE_X13Y42.F3      net (fanout=1)        0.222   _LC_2_0
-    SLICE_X13Y42.X       Tilo                  0.194   inst_mips_top/inst_pipeline/pc.branch_take
-                                                       inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.BY      net (fanout=3)        0.590   inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.CLK     Tdick                 0.342   inst_mips_top/inst_pipeline/pc.branch_take_1
-                                                       inst_mips_top/inst_pipeline/pc.branch_take_1
-    -------------------------------------------------  ---------------------------
-    Total                                      4.917ns (2.274ns logic, 2.643ns route)
-                                                       (46.2% logic, 53.8% route)
-
---------------------------------------------------------------------------------
-Slack:                  -0.140ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_mips_top/inst_pipeline/bcu_op_a_2 (FF)
-  Destination:          inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
-  Requirement:          4.950ns
-  Data Path Delay:      4.860ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.170ns (2.881 - 3.051)
-  Source Clock:         cpu_clk rising at 0.000ns
-  Destination Clock:    cpu_clk falling at 4.950ns
-  Clock Uncertainty:    0.060ns
-
-  Clock Uncertainty:          0.060ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.120ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X8Y30.XQ       Tcko                  0.360   inst_mips_top/inst_pipeline/bcu_op_a<2>
-                                                       inst_mips_top/inst_pipeline/bcu_op_a_2
-    SLICE_X10Y30.G3      net (fanout=1)        0.816   inst_mips_top/inst_pipeline/bcu_op_a<2>
-    SLICE_X10Y30.COUT    Topcyg                0.561   inst_mips_top/inst_pipeline/EX_stage.reg_a_17
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_a<1>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_b<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/EX_stage.reg_a_16
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
-    SLICE_X13Y39.F4      net (fanout=2)        0.836   inst_mips_top/inst_pipeline/bcu_flags_eq
-    SLICE_X13Y39.X       Tilo                  0.194   inst_mips_top/inst_pipeline/pc_branch_take_mux000240
-                                                       inst_mips_top/inst_pipeline/pc_branch_take_mux000240
-    SLICE_X13Y42.F4      net (fanout=1)        0.344   inst_mips_top/inst_pipeline/pc_branch_take_mux000240
-    SLICE_X13Y42.X       Tilo                  0.194   inst_mips_top/inst_pipeline/pc.branch_take
-                                                       inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.BY      net (fanout=3)        0.590   inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.CLK     Tdick                 0.342   inst_mips_top/inst_pipeline/pc.branch_take_1
-                                                       inst_mips_top/inst_pipeline/pc.branch_take_1
-    -------------------------------------------------  ---------------------------
-    Total                                      4.860ns (2.274ns logic, 2.586ns route)
-                                                       (46.8% logic, 53.2% route)
-
---------------------------------------------------------------------------------
-Slack:                  -0.073ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_mips_top/inst_pipeline/bcu_op_a_0 (FF)
-  Destination:          inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
-  Requirement:          4.950ns
-  Data Path Delay:      4.793ns (Levels of Logic = 10)
-  Clock Path Skew:      -0.170ns (2.881 - 3.051)
-  Source Clock:         cpu_clk rising at 0.000ns
-  Destination Clock:    cpu_clk falling at 4.950ns
-  Clock Uncertainty:    0.060ns
-
-  Clock Uncertainty:          0.060ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.120ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_0 to inst_mips_top/inst_pipeline/pc.branch_take_1
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X9Y30.YQ       Tcko                  0.340   inst_mips_top/inst_pipeline/bcu_op_b<13>
-                                                       inst_mips_top/inst_pipeline/bcu_op_a_0
-    SLICE_X10Y30.F2      net (fanout=1)        0.697   inst_mips_top/inst_pipeline/bcu_op_a<0>
-    SLICE_X10Y30.COUT    Topcyf                0.576   inst_mips_top/inst_pipeline/EX_stage.reg_a_17
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<0>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<0>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
-    SLICE_X10Y31.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_a<1>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
-    SLICE_X10Y32.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/bcu_op_b<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
-    SLICE_X10Y33.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
-    SLICE_X10Y34.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
-    SLICE_X10Y35.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
-    SLICE_X10Y36.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.CIN     net (fanout=1)        0.000   inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
-    SLICE_X10Y37.COUT    Tbyp                  0.089   inst_mips_top/inst_pipeline/EX_stage.reg_a_16
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
-                                                       inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
-    SLICE_X13Y42.G4      net (fanout=2)        1.015   inst_mips_top/inst_pipeline/bcu_flags_eq
-    SLICE_X13Y42.Y       Tilo                  0.194   inst_mips_top/inst_pipeline/pc.branch_take
-                                                       _LC_2_0
-    SLICE_X13Y42.F3      net (fanout=1)        0.222   _LC_2_0
-    SLICE_X13Y42.X       Tilo                  0.194   inst_mips_top/inst_pipeline/pc.branch_take
-                                                       inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.BY      net (fanout=3)        0.590   inst_mips_top/inst_pipeline/pc_branch_take_mux0002
-    SLICE_X17Y41.CLK     Tdick                 0.342   inst_mips_top/inst_pipeline/pc.branch_take_1
-                                                       inst_mips_top/inst_pipeline/pc.branch_take_1
-    -------------------------------------------------  ---------------------------
-    Total                                      4.793ns (2.269ns logic, 2.524ns route)
-                                                       (47.3% logic, 52.7% route)
-
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%;
-
- 787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Minimum period is   5.284ns.
---------------------------------------------------------------------------------
-Slack:                  74.716ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/cnt_0 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/cnt_7 (FF)
-  Requirement:          80.000ns
-  Data Path Delay:      5.175ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 80.000ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_7
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X65Y23.XQ      Tcko                  0.340   inst_ac97_wb/inst_ac_io/cnt<0>
-                                                       inst_ac97_wb/inst_ac_io/cnt_0
-    SLICE_X66Y26.G1      net (fanout=9)        0.836   inst_ac97_wb/inst_ac_io/cnt<0>
-    SLICE_X66Y26.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
-    SLICE_X66Y26.F4      net (fanout=1)        0.159   N1018
-    SLICE_X66Y26.X       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
-    SLICE_X64Y27.G3      net (fanout=3)        0.427   inst_ac97_wb/inst_ac_io/N9
-    SLICE_X64Y27.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
-                                                       inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
-    SLICE_X57Y28.G1      net (fanout=10)       1.115   inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
-    SLICE_X57Y28.Y       Tilo                  0.194   inst_ac97_wb/inst_ac_io/cnt_not0002
-                                                       inst_ac97_wb/inst_ac_io/cnt_not00021
-    SLICE_X65Y26.CE      net (fanout=5)        0.966   inst_ac97_wb/inst_ac_io/cnt_not0002
-    SLICE_X65Y26.CLK     Tceck                 0.553   inst_ac97_wb/inst_ac_io/cnt<6>
-                                                       inst_ac97_wb/inst_ac_io/cnt_7
-    -------------------------------------------------  ---------------------------
-    Total                                      5.175ns (1.672ns logic, 3.503ns route)
-                                                       (32.3% logic, 67.7% route)
-
---------------------------------------------------------------------------------
-Slack:                  74.716ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/cnt_0 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/cnt_9 (FF)
-  Requirement:          80.000ns
-  Data Path Delay:      5.175ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 80.000ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_9
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X65Y23.XQ      Tcko                  0.340   inst_ac97_wb/inst_ac_io/cnt<0>
-                                                       inst_ac97_wb/inst_ac_io/cnt_0
-    SLICE_X66Y26.G1      net (fanout=9)        0.836   inst_ac97_wb/inst_ac_io/cnt<0>
-    SLICE_X66Y26.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
-    SLICE_X66Y26.F4      net (fanout=1)        0.159   N1018
-    SLICE_X66Y26.X       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
-    SLICE_X64Y27.G3      net (fanout=3)        0.427   inst_ac97_wb/inst_ac_io/N9
-    SLICE_X64Y27.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
-                                                       inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
-    SLICE_X57Y28.G1      net (fanout=10)       1.115   inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
-    SLICE_X57Y28.Y       Tilo                  0.194   inst_ac97_wb/inst_ac_io/cnt_not0002
-                                                       inst_ac97_wb/inst_ac_io/cnt_not00021
-    SLICE_X65Y27.CE      net (fanout=5)        0.966   inst_ac97_wb/inst_ac_io/cnt_not0002
-    SLICE_X65Y27.CLK     Tceck                 0.553   inst_ac97_wb/inst_ac_io/cnt<8>
-                                                       inst_ac97_wb/inst_ac_io/cnt_9
-    -------------------------------------------------  ---------------------------
-    Total                                      5.175ns (1.672ns logic, 3.503ns route)
-                                                       (32.3% logic, 67.7% route)
-
---------------------------------------------------------------------------------
-Slack:                  74.716ns (requirement - (data path - clock path skew + uncertainty))
-  Source:               inst_ac97_wb/inst_ac_io/cnt_0 (FF)
-  Destination:          inst_ac97_wb/inst_ac_io/cnt_8 (FF)
-  Requirement:          80.000ns
-  Data Path Delay:      5.175ns (Levels of Logic = 4)
-  Clock Path Skew:      0.000ns
-  Source Clock:         CLK_O rising at 0.000ns
-  Destination Clock:    CLK_O rising at 80.000ns
-  Clock Uncertainty:    0.109ns
-
-  Clock Uncertainty:          0.109ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
-    Total System Jitter (TSJ):  0.000ns
-    Total Input Jitter (TIJ):   0.000ns
-    Discrete Jitter (DJ):       0.217ns
-    Phase Error (PE):           0.000ns
-
-  Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_8
-    Location             Delay type         Delay(ns)  Physical Resource
-                                                       Logical Resource(s)
-    -------------------------------------------------  -------------------
-    SLICE_X65Y23.XQ      Tcko                  0.340   inst_ac97_wb/inst_ac_io/cnt<0>
-                                                       inst_ac97_wb/inst_ac_io/cnt_0
-    SLICE_X66Y26.G1      net (fanout=9)        0.836   inst_ac97_wb/inst_ac_io/cnt<0>
-    SLICE_X66Y26.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
-    SLICE_X66Y26.F4      net (fanout=1)        0.159   N1018
-    SLICE_X66Y26.X       Tilo                  0.195   inst_ac97_wb/inst_ac_io/N9
-                                                       inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
-    SLICE_X64Y27.G3      net (fanout=3)        0.427   inst_ac97_wb/inst_ac_io/N9
-    SLICE_X64Y27.Y       Tilo                  0.195   inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
-                                                       inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
-    SLICE_X57Y28.G1      net (fanout=10)       1.115   inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
-    SLICE_X57Y28.Y       Tilo                  0.194   inst_ac97_wb/inst_ac_io/cnt_not0002
-                                                       inst_ac97_wb/inst_ac_io/cnt_not00021
-    SLICE_X65Y27.CE      net (fanout=5)        0.966   inst_ac97_wb/inst_ac_io/cnt_not0002
-    SLICE_X65Y27.CLK     Tceck                 0.553   inst_ac97_wb/inst_ac_io/cnt<8>
-                                                       inst_ac97_wb/inst_ac_io/cnt_8
-    -------------------------------------------------  ---------------------------
-    Total                                      5.175ns (1.672ns logic, 3.503ns route)
-                                                       (32.3% logic, 67.7% route)
-
---------------------------------------------------------------------------------
-
-
-2 constraints not met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Clock to Setup on destination clock sys_ac97_bit_clk
-----------------+---------+---------+---------+---------+
-                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-sys_ac97_bit_clk|    6.390|    3.350|         |    2.174|
-----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock sys_clk_in
----------------+---------+---------+---------+---------+
-               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-sys_clk_in     |   10.193|    4.880|    5.147|    3.200|
----------------+---------+---------+---------+---------+
-
-
-Timing summary:
----------------
-
-Timing errors: 10  Score: 1304
-
-Constraints cover 1334002 paths, 0 nets, and 42582 connections
-
-Design statistics:
-   Minimum period:  10.294ns{1}   (Maximum frequency:  97.144MHz)
-
-
-------------------------------------Footnotes-----------------------------------
-1)  The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Tue Mar 09 13:11:34 2010 
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings 
-
-Peak Memory Usage: 349 MB
-
-
-
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.ut b/projects/mips_sys/ise101/mips_sys/mips_sys.ut
deleted file mode 100644
index c22b05a..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.ut
+++ /dev/null
@@ -1,33 +0,0 @@
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:4
--g CclkPin:PullUp
--g M0Pin:PullUp
--g M1Pin:PullUp
--g M2Pin:PullUp
--g ProgPin:PullUp
--g DonePin:PullUp
--g InitPin:Pullup
--g CsPin:Pullup
--g DinPin:Pullup
--g BusyPin:Pullup
--g RdWrPin:Pullup
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullUp
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCIUpdateMode:AsRequired
--g StartUpClk:JtagClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Match_cycle:Auto
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g Encrypt:No
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.xst b/projects/mips_sys/ise101/mips_sys/mips_sys.xst
deleted file mode 100644
index 8b21e6b..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys.xst
+++ /dev/null
@@ -1,62 +0,0 @@
-set -tmpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp"
-set -xsthdpdir "W:/vhdl/projects/mips_sys/ise101/mips_sys/xst"
-run
--ifn mips_sys.prj
--ifmt mixed
--ofn mips_sys
--ofmt NGC
--p xc4vsx35-10-ff668
--top mips_sys
--opt_mode Speed
--opt_level 1
--power NO
--iuc NO
--lso mips_sys.lso
--keep_hierarchy NO
--netlist_hierarchy as_optimized
--rtlview Yes
--glob_opt AllClockNets
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
--dsp_utilization_ratio 100
--verilog2001 YES
--fsm_extract YES -fsm_encoding Auto
--safe_implementation No
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract YES
--shreg_extract YES
--shift_extract YES
--xor_collapse YES
--rom_style Auto
--auto_bram_packing NO
--mux_extract YES
--resource_sharing NO
--async_to_sync NO
--use_dsp48 auto
--iobuf YES
--max_fanout 500
--bufg 32
--bufr 24
--register_duplication YES
--register_balancing Yes
--move_first_stage YES
--move_last_stage YES
--slice_packing YES
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob true
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
deleted file mode 100644
index 7ea5658..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp
+++ /dev/null
@@ -1,1792 +0,0 @@
-Release 10.1.03 Map K.39 (nt)
-Xilinx Mapping Report File for Design 'mips_sys'
-
-Design Information
-------------------
-Command Line   : map -ise W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -p xc4vsx35-ff668-10
--timing -logic_opt on -ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal
-on -cm area -pr b -k 4 -power off -o mips_sys_map.ncd mips_sys.ngd mips_sys.pcf 
-Target Device  : xc4vsx35
-Target Package : ff668
-Target Speed   : -10
-Stepping Level : ES
-Mapper Version : virtex4 -- $Revision: 1.5 $
-Mapped Date    : Tue Mar 09 12:59:05 2010
-
-Design Summary
---------------
-Number of errors:      0
-Number of warnings:   68
-Logic Utilization:
-  Number of Slice Flip Flops:         5,422 out of  30,720   17%
-  Number of 4 input LUTs:             8,643 out of  30,720   28%
-Logic Distribution:
-  Number of occupied Slices:          5,907 out of  15,360   38%
-    Number of Slices containing only related logic:   5,907 out of   5,907 100%
-    Number of Slices containing unrelated logic:          0 out of   5,907   0%
-      *See NOTES below for an explanation of the effects of unrelated logic.
-  Total Number of 4 input LUTs:       9,032 out of  30,720   29%
-    Number used as logic:             7,643
-    Number used as a route-thru:        389
-    Number used for Dual Port RAMs:     792
-      (Two LUTs used per Dual Port RAM)
-    Number used as Shift registers:     208
-  Number of bonded IOBs:                226 out of     448   50%
-    IOB Flip Flops:                     350
-    IOB Dual-Data Rate Flops:            42
-  Number of BUFG/BUFGCTRLs:              12 out of      32   37%
-    Number used as BUFGs:                12
-  Number of FIFO16/RAMB16s:              51 out of     192   26%
-    Number used as RAMB16s:              51
-  Number of DCM_ADVs:                     4 out of       8   50%
-  Number of BSCAN_VIRTEX4s:               1 out of       4   25%
-
-Peak Memory Usage:  530 MB
-Total REAL time to MAP completion:  8 mins 27 secs 
-Total CPU time to MAP completion:   8 mins 9 secs 
-
-Table of Contents
------------------
-Section 1 - Errors
-Section 2 - Warnings
-Section 3 - Informational
-Section 4 - Removed Logic Summary
-Section 5 - Removed Logic
-Section 6 - IOB Properties
-Section 7 - RPMs
-Section 8 - Guide Report
-Section 9 - Area Group and Partition Summary
-Section 10 - Modular Design Summary
-Section 11 - Timing Report
-Section 12 - Configuration String Information
-Section 13 - Control Set Information
-Section 14 - Utilization by Hierarchy
-
-Section 1 - Errors
-------------------
-
-Section 2 - Warnings
---------------------
-WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 18 (RAMB16
-   symbol "inst_mips_top/inst_biu/inst_icache/inst_tag_ram/Mram_RAM1").
-WARNING:LIT:243 - Logical network sys_usb_d_15_IOBUF/N2 has no load.
-WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 167
-   more times for the following (max. 5 shown):
-   sys_usb_d_15_IOBUF/N3,
-   sys_usb_d_14_IOBUF/N2,
-   sys_usb_d_14_IOBUF/N3,
-   sys_usb_d_13_IOBUF/N2,
-   sys_usb_d_13_IOBUF/N3
-   To see the details of these warning messages, please use the -detail switch.
-WARNING:Pack:2549 - The register
-   "inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
-   IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
-   register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
-   general routing.
-WARNING:Pack:2549 - The register
-   "inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property
-   IOB=TRUE, but was not packed into the OLOGIC component. The output signal for
-   register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires
-   general routing.
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_765".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_763".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_761".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_759".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_757".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_755".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_753".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_751".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_749".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_747".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_745".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_743".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_741".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_725".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_739".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_723".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_721".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_737".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_705".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_719".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_735".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_703".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_25" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_717".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_17" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_733".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_18" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_731".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_26" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_715".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_19" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_729".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_27" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_713".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_20" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_727".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_28" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_711".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_29" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_709".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_30" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not
-   match the ILOGIC SR signal "N0_707".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
-   ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the
-   ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
-   ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the
-   ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000".
-
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. Register
-   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4
-   set/reset disagrees with another register in the OLOGIC component.
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. Register
-   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3
-   set/reset disagrees with another register in the OLOGIC component.
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. Register
-   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2
-   set/reset disagrees with another register in the OLOGIC component.
-WARNING:Pack:2549 - The register
-   "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. Register
-   inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1
-   set/reset disagrees with another register in the OLOGIC component.
-WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "N25" does not match the ILOGIC SR signal
-   "inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
-   The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
-   match the ILOGIC REV signal
-   "inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "N25" does not match the ILOGIC SR signal
-   "inst_ps2_phy_0/Inst_debounce_clk/output_and0000".
-   The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not
-   match the ILOGIC REV signal
-   "inst_ps2_phy_0/Inst_debounce_clk/output_and0001".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "N21" does not match the ILOGIC SR signal
-   "inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
-   The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
-   match the ILOGIC REV signal
-   "inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
-
-WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx_1" has
-   the property IOB=TRUE, but was not packed into the OLOGIC component. The
-   OLOGIC SR signal "N21" does not match the ILOGIC SR signal
-   "inst_ps2_phy_1/Inst_debounce_clk/output_and0000".
-   The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not
-   match the ILOGIC REV signal
-   "inst_ps2_phy_1/Inst_debounce_clk/output_and0001".
-
-WARNING:Pack:2548 - The register "inst_gpio_wb/gpi1_reg_7" has the property
-   IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC component
-   already contains an IFF1.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000028 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000011_f6/MUXF5.I0
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000231 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000032 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00007_f6/MUXF5.I0.
-    Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000351 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000035_f6/MUXF5.I0
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000034 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00005_f6/MUXF5.I0.
-    Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000271 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000251 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000331 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000033_f6/MUXF5.I0
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000036 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00003_f6/MUXF5.I0.
-    Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000312 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008_f6/MUXF5.I1.
-    Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000291 failed to
-   merge with F5 multiplexer
-   inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010_f6/MUXF5.I1
-   .  Tried to combine two collections of symbols from different layers.  The
-   alignment requirements of the two layers conflict.  The design will exhibit
-   suboptimal timing.
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.
-   Components associated with this bus are as follows: 
-   	 Comp: sys_vga_blue<0>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_blue<1>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_blue<2>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_blue<3>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_blue<4>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_blue<5>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_blue<6>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_blue<7>   IOSTANDARD = LVCMOS25
-
-
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.
-   Components associated with this bus are as follows: 
-   	 Comp: sys_vga_green<0>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_green<1>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_green<2>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_green<3>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_green<4>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_green<5>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_green<6>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_green<7>   IOSTANDARD = LVCMOS25
-
-
-WARNING:Place:838 - An IO Bus with more than one IO standard is found.
-   Components associated with this bus are as follows: 
-   	 Comp: sys_vga_red<0>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_red<1>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_red<2>   IOSTANDARD = LVCMOS33
-   	 Comp: sys_vga_red<3>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_red<4>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_red<5>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_red<6>   IOSTANDARD = LVCMOS25
-   	 Comp: sys_vga_red<7>   IOSTANDARD = LVCMOS25
-
-
-WARNING:PhysDesignRules:1236 - Unknown DCM_ADV feedback loop. The signal sys_sdr_clk_fb_IBUFG on the CLKFB pin of
-   DCM_ADV comp inst_clockgen/inst_DCM_SDRCLK_0 was driven by an IOB site but the signal loop could not be traced back
-   to the CLK0 pin of comp inst_clockgen/inst_DCM_SDRCLK_0. The signal out the CLK0 pin must drive an IOB input pin with
-   programming out to the PAD.
-
-Section 3 - Informational
--------------------------
-INFO:MapLib:564 - The following environment variables are currently set:
-INFO:MapLib:591 - XIL_MAP_LOCWARN 	Value: 1
-INFO:MapLib:159 - Net Timing constraints on signal sys_ac97_bit_clk are pushed
-   forward through input buffer.
-INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices.
-   Please note that there are new specifications for the DCMs to guarantee
-   maximum frequency performance. If the DCM input clock might stop or if the
-   DCM reset might be asserted for an extended time, then use of the dcm_standby
-   macro may be required. Please see Answer Record 21127.
-INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
-   0.000 to 85.000 Celsius)
-INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
-   1.260 Volts)
-INFO:Pack:1679 - FLOP symbol "inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0" (Output Signal =
-   inst_mips_top/inst_pipeline/EX_stage.reg_b_3_REPLICA_0) was replicated from FLOP symbol
-   "inst_mips_top/inst_pipeline/EX_stage.reg_b_3" (Output Signal = inst_mips_top/inst_pipeline/EX_stage.reg_b_3)
-INFO:Pack:1650 - Map created a placed design.
-INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
-   the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet.
-INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of
-   the DCM_ADV comp inst_clockgen/inst_DCM_SYS_FX, consult the device Data Sheet.
-
-Section 4 - Removed Logic Summary
----------------------------------
- 168 block(s) removed
-   4 block(s) optimized away
- 168 signal(s) removed
-
-Section 5 - Removed Logic
--------------------------
-
-The trimmed logic report below shows the logic removed from your design due to
-sourceless or loadless signals, and VCC or ground connections.  If the removal
-of a signal or symbol results in the subsequent removal of an additional signal
-or symbol, the message explaining that second removal will be indented.  This
-indentation will be repeated as a chain of related logic is removed.
-
-To quickly locate the original cause for the removal of a chain of logic, look
-above the place where that logic is listed in the trimming report, then locate
-the lines that are least indented (begin at the leftmost edge).
-
-The signal "sys_usb_d_15_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_15_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_14_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_14_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_13_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_13_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_12_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_12_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_11_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_11_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_10_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_10_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_9_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_9_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_8_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_8_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_7_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_7_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_6_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_6_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_5_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_5_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_4_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_4_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_3_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_3_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_2_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_2_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_1_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_1_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_usb_d_0_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_usb_d_0_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_31_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_31_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_30_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_30_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_29_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_29_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_28_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_28_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_27_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_27_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_26_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_26_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_25_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_25_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_24_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_24_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_23_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_23_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_22_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_22_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_21_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_21_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_20_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_20_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_19_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_19_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_18_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_18_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_17_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_17_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_16_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_16_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_15_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_15_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_14_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_14_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_13_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_13_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_12_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_12_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_11_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_11_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_10_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_10_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_9_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_9_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_8_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_8_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_7_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_7_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_6_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_6_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_5_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_5_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_4_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_4_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_3_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_3_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_2_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_2_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_1_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_1_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_flash_d_0_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_flash_d_0_IOBUF/N3" is sourceless and has been removed.
-The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N2" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N3" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N2" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N3" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N2" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N3" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N2" is sourceless and has been
-removed.
-The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N3" is sourceless and has been
-removed.
-The signal "sys_sdr_data_31_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_31_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_30_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_30_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_29_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_29_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_28_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_28_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_27_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_27_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_26_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_26_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_25_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_25_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_24_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_24_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_23_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_23_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_22_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_22_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_21_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_21_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_20_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_20_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_19_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_19_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_18_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_18_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_17_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_17_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_16_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_16_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_15_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_15_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_14_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_14_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_13_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_13_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_12_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_12_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_11_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_11_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_10_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_10_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_9_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_9_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_8_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_8_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_7_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_7_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_6_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_6_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_5_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_5_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_4_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_4_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_3_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_3_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_2_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_2_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_1_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_1_IOBUF/N3" is sourceless and has been removed.
-The signal "sys_sdr_data_0_IOBUF/N2" is sourceless and has been removed.
-The signal "sys_sdr_data_0_IOBUF/N3" is sourceless and has been removed.
-Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
-Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
-Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
-Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
-Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed.
-Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed.
-Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed.
-Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_0_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_0_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_10_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_10_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_11_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_11_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_12_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_12_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_13_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_13_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_14_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_14_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_15_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_15_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_16_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_16_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_17_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_17_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_18_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_18_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_19_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_19_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_1_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_1_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_20_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_20_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_21_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_21_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_22_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_22_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_23_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_23_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_24_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_24_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_25_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_25_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_26_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_26_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_27_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_27_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_28_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_28_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_29_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_29_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_2_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_2_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_30_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_30_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_31_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_31_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_3_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_3_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_4_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_4_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_5_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_5_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_6_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_6_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_7_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_7_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_8_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_8_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_flash_d_9_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_flash_d_9_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_0_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_0_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_10_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_10_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_11_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_11_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_12_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_12_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_13_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_13_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_14_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_14_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_15_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_15_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_16_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_16_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_17_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_17_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_18_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_18_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_19_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_19_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_1_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_1_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_20_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_20_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_21_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_21_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_22_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_22_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_23_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_23_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_24_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_24_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_25_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_25_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_26_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_26_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_27_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_27_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_28_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_28_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_29_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_29_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_2_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_2_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_30_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_30_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_31_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_31_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_3_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_3_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_4_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_4_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_5_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_5_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_6_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_6_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_7_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_7_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_8_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_8_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_sdr_data_9_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_sdr_data_9_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_0_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_0_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_10_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_10_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_11_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_11_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_12_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_12_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_13_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_13_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_14_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_14_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_15_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_15_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_1_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_1_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_2_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_2_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_3_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_3_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_4_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_4_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_5_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_5_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_6_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_6_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_7_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_7_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_8_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_8_IOBUF/XST_VCC" (ONE) removed.
-Unused block "sys_usb_d_9_IOBUF/XST_GND" (ZERO) removed.
-Unused block "sys_usb_d_9_IOBUF/XST_VCC" (ONE) removed.
-
-Optimized Block(s):
-TYPE 		BLOCK
-GND 		XST_GND
-VCC 		XST_VCC
-GND 		inst_mips_top/XST_GND
-VCC 		inst_mips_top/XST_VCC
-
-To enable printing of redundant blocks removed and signals merged, set the
-detailed map report option and rerun map.
-
-Section 6 - IOB Properties
---------------------------
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-| IOB Name                           | Type             | Direction | IO Standard          | Drive    | Slew | Reg (s)      | Resistor | IOB      |
-|                                    |                  |           |                      | Strength | Rate |              |          | Delay    |
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-| sys_ac97_bit_clk                   | IOB              | INPUT     | LVCMOS33             |          |      |              |          |          |
-| sys_ac97_sdata_in                  | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         |          |          |
-| sys_ac97_sdata_out                 | IOB              | OUTPUT    | LVCMOS25             | 12       | FAST | OFF1         |          |          |
-| sys_ac97_ssync                     | IOB              | OUTPUT    | LVCMOS25             | 12       | FAST | OFF1         |          |          |
-| sys_btn<0>                         | IOB              | INPUT     | LVCMOS25             |          |      | IFF1         | PULLDOWN |          |
-| sys_btn<1>                         | IOB              | INPUT     | LVCMOS25             |          |      | IFF1         | PULLDOWN |          |
-| sys_btn<2>                         | IOB              | INPUT     | LVCMOS25             |          |      | IFF1         | PULLDOWN |          |
-| sys_btn<3>                         | IOB              | INPUT     | LVCMOS25             |          |      | IFF1         | PULLDOWN |          |
-| sys_btn<4>                         | IOB              | INPUT     | LVCMOS25             |          |      | IFF1         | PULLDOWN |          |
-| sys_clk_in                         | IOB              | INPUT     | LVCMOS33             |          |      |              |          |          |
-| sys_dip<0>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<1>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<2>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<3>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<4>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<5>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<6>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_dip<7>                         | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         | PULLDOWN |          |
-| sys_error<0>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW | OFF1         |          |          |
-| sys_error<1>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW | OFF1         |          |          |
-| sys_flash_a<0>                     | IOB              | OUTPUT    | LVDCI_33             |          |      |              |          |          |
-| sys_flash_a<1>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<2>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<3>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<4>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<5>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<6>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<7>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<8>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<9>                     | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<10>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<11>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<12>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<13>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<14>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<15>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<16>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<17>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<18>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<19>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<20>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<21>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<22>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<23>                    | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_a<24>                    | IOB              | OUTPUT    | LVDCI_33             |          |      |              |          |          |
-| sys_flash_ac97_rstn                | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST |              |          |          |
-| sys_flash_byten                    | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST |              |          |          |
-| sys_flash_ce                       | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_d<0>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<1>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<2>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<3>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<4>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<5>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<6>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<7>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<8>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<9>                     | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<10>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<11>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<12>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<13>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<14>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<15>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<16>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<17>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<18>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<19>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<20>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<21>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<22>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<23>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<24>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<25>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<26>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<27>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<28>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<29>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<30>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_d<31>                    | IOB              | BIDIR     | LVCMOS33             | 12       | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_flash_rdn                      | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_flash_wrn                      | IOB              | OUTPUT    | LVDCI_33             |          |      | OFF1         |          |          |
-| sys_lcd_d<0>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              | PULLDOWN |          |
-| sys_lcd_d<1>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              | PULLDOWN |          |
-| sys_lcd_d<2>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              | PULLDOWN |          |
-| sys_lcd_d<3>                       | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              | PULLDOWN |          |
-| sys_lcd_e                          | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              |          |          |
-| sys_lcd_rs                         | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              |          |          |
-| sys_lcd_rw                         | IOB              | OUTPUT    | LVCMOS33             | 2        | SLOW |              |          |          |
-| sys_led<0>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<1>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<2>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<3>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<4>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<5>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<6>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<7>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_led<8>                         | IOB              | OUTPUT    | LVCMOS25             | 2        | SLOW | OFF1         |          |          |
-| sys_ps2_0_clk                      | IOB              | BIDIR     | LVCMOS25             | 2        | SLOW | IFF1         |          |          |
-| sys_ps2_0_data                     | IOB              | BIDIR     | LVCMOS25             | 2        | SLOW | IFF1         |          |          |
-| sys_ps2_1_clk                      | IOB              | BIDIR     | LVCMOS25             | 2        | SLOW | IFF1         |          |          |
-| sys_ps2_1_data                     | IOB              | BIDIR     | LVCMOS25             | 2        | SLOW | IFF1         |          |          |
-| sys_rst_n_in                       | IOB              | INPUT     | LVCMOS25             |          |      |              | PULLUP   |          |
-| sys_sdr_a_q<0>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<1>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<2>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<3>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<4>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<5>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<6>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<7>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<8>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<9>                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<10>                    | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<11>                    | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_a_q<12>                    | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_ba_q<0>                    | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_ba_q<1>                    | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_cas_qn                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_cke_q                      | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_clk_fb                     | IOB              | INPUT     | LVCMOS25             |          |      |              |          |          |
-| sys_sdr_clk_n                      | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_clk_p                      | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_cs_qn                      | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_data<0>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<1>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<2>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<3>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<4>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<5>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<6>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<7>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<8>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<9>                    | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<10>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<11>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<12>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<13>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<14>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<15>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<16>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<17>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<18>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<19>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<20>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<21>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<22>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<23>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<24>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<25>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<26>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<27>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<28>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<29>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<30>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_data<31>                   | IOB              | BIDIR     | SSTL2_II             |          |      | IFF1         |          |          |
-|                                    | IDDR:SAMEODDR:SA |           |                      |          |      | IFF2         |          |          |
-|                                    |                  |           |                      |          |      | IFF4         |          |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_dm_q<0>                    | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:SAME        |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_dm_q<1>                    | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:SAME        |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_dm_q<2>                    | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:SAME        |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_dm_q<3>                    | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:SAME        |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFF3         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRB      |          |          |
-| sys_sdr_dqs_q<0>                   | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_dqs_q<1>                   | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_dqs_q<2>                   | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_dqs_q<3>                   | IOB              | OUTPUT    | SSTL2_II             |          |      | OFF1         |          |          |
-|                                    | ODDR:OPPOSITE    |           |                      |          |      | OFF2         |          |          |
-|                                    |                  |           |                      |          |      | OFFDDRA      |          |          |
-| sys_sdr_ras_qn                     | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_sdr_we_qn                      | IOB              | OUTPUT    | SSTL2_I              |          |      | OFF1         |          |          |
-| sys_uart0_rx                       | IOB              | INPUT     | LVCMOS33             |          |      | IFF1         |          |          |
-| sys_uart0_tx                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW | OFF1         |          |          |
-| sys_uart1_rx                       | IOB              | INPUT     | LVCMOS33             |          |      |              |          |          |
-| sys_uart1_tx                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW |              |          |          |
-| sys_uart2_rx                       | IOB              | INPUT     | LVCMOS33             |          |      |              |          |          |
-| sys_uart2_tx                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW |              |          |          |
-| sys_uart3_rx                       | IOB              | INPUT     | LVCMOS33             |          |      |              |          |          |
-| sys_uart3_tx                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW |              |          |          |
-| sys_usb_a<0>                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW | OFF1         |          |          |
-| sys_usb_a<1>                       | IOB              | OUTPUT    | LVCMOS33             | 12       | SLOW | OFF1         |          |          |
-| sys_usb_csn                        | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_usb_d<0>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<1>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<2>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<3>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<4>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<5>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<6>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<7>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<8>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<9>                       | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<10>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<11>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<12>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<13>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<14>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_d<15>                      | IOB              | BIDIR     | LVCMOS33             | 8        | FAST | IFF1         | PULLDOWN |          |
-|                                    |                  |           |                      |          |      | OFF1         |          |          |
-|                                    |                  |           |                      |          |      | TFF1         |          |          |
-| sys_usb_int                        | IOB              | INPUT     | LVCMOS33             |          |      |              | PULLDOWN |          |
-| sys_usb_rdn                        | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_usb_rstn                       | IOB              | OUTPUT    | LVCMOS25             | 12       | SLOW |              |          |          |
-| sys_usb_wrn                        | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blank_n                    | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST |              |          |          |
-| sys_vga_blue<0>                    | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<1>                    | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<2>                    | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<3>                    | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<4>                    | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<5>                    | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<6>                    | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_blue<7>                    | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_clk                        | IOB              | OUTPUT    | LVDCI_33             |          |      |              |          |          |
-| sys_vga_green<0>                   | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<1>                   | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<2>                   | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<3>                   | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<4>                   | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<5>                   | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<6>                   | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_green<7>                   | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_hsync                      | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<0>                     | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<1>                     | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<2>                     | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<3>                     | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<4>                     | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<5>                     | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<6>                     | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_red<7>                     | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-| sys_vga_sync_n                     | IOB              | OUTPUT    | LVCMOS33             | 8        | FAST |              |          |          |
-| sys_vga_vsync                      | IOB              | OUTPUT    | LVCMOS25             | 8        | FAST | OFF1         |          |          |
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-
-Section 7 - RPMs
-----------------
-
-Section 8 - Guide Report
-------------------------
-Guide not run on this design.
-
-Section 9 - Area Group and Partition Summary
---------------------------------------------
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-Area Group Information
-----------------------
-
-Area Group "AG_inst_mips_top"
-  No COMPRESSION specified for Area Group "AG_inst_mips_top"
-  RANGE: SLICE_X0Y53:SLICE_X39Y0
-  RANGE:
-RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X
-3Y0:RAMB16_X3Y6
-  Area Group Logic Utilization:
-  Number of Slice Flip Flops:            1,962 out of  4,320   45%
-  Logic Distribution:
-    Number of occupied Slices:           2,157 out of  2,160   99%
-      Number of Slices containing only related logic:  2,157 out of  2,157 100%
-  Total Number of 4 input LUTs:          4,309 out of  4,320   99%
-    Number used as logic:                3,649
-    Number used as route-thru:              49
-    Number used as Dual Port RAMs:         586
-      (Two LUTs used per Dual Port RAM)
-    Number used as Shift registers:         25
-  Number of Block RAMs:                     27 out of     28   96%
-
-
-Section 10 - Modular Design Summary
------------------------------------
-Modular Design not used for this design.
-
-Section 11 - Timing Report
---------------------------
-A logic-level (pre-route) timing report can be generated by using Xilinx static
-timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
-mapped NCD and PCF files. Please note that this timing report will be generated
-using estimated delay information. For accurate numbers, please generate a
-timing report with the post Place and Route NCD file.
-
-For more information about the Timing Analyzer, consult the Xilinx Timing
-Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
-Development System Reference Guide "TRACE" chapter.
-
-Section 12 - Configuration String Details
------------------------------------------
-Use the "-detail" map option to print out Configuration Strings
-
-Section 13 - Control Set Information
-------------------------------------
-No control set information for this architecture.
-
-Section 14 - Utilization by Hierarchy
--------------------------------------
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| Module                           | Partition | Slices        | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48   | BUFG  | BUFIO | BUFR  | DCM   | Full Hierarchical Name                                                                                         |
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| mips_sys/                        |           | 1376/8103     | 28/5422       | 845/9032      | 2/1000        | 0/51      | 0/0     | 2/12  | 0/0   | 0/0   | 0/4   | mips_sys                                                                                                       |
-| +inst_ac97_wb                    |           | 181/823       | 118/672       | 186/631       | 0/0           | 0/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb                                                                                          |
-| ++inst_ac_io                     |           | 21/598        | 13/525        | 29/380        | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io                                                                               |
-| +++inst_ac_in                    |           | 254/260       | 258/262       | 98/103        | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in                                                                    |
-| ++++singleshot_inst1             |           | 3/3           | 2/2           | 2/2           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1                                                   |
-| ++++singleshot_inst2             |           | 3/3           | 2/2           | 3/3           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2                                                   |
-| +++inst_ac_out                   |           | 314/317       | 248/250       | 246/248       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out                                                                   |
-| ++++singleshot_inst1             |           | 3/3           | 2/2           | 2/2           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1                                                  |
-| ++inst_tx_fifo                   |           | 1/44          | 0/29          | 1/65          | 0/0           | 0/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_tx_fifo                                                                             |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 1/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r                                                             |
-| +++inst_fifo_sync_ctrl           |           | 43/43         | 29/29         | 64/64         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl                                                         |
-| +inst_clockgen                   |           | 41/47         | 54/54         | 18/24         | 4/10          | 0/0       | 0/0     | 8/8   | 0/0   | 0/0   | 4/4   | mips_sys/inst_clockgen                                                                                         |
-| ++Mshreg_reset_pipe0_19_0        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0                                                                 |
-| ++Mshreg_reset_pipe0_19_1        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1                                                                 |
-| ++Mshreg_reset_pipe1_19_0        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0                                                                 |
-| ++Mshreg_reset_pipe1_19_1        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1                                                                 |
-| ++Mshreg_reset_pipe2_19_0        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0                                                                 |
-| ++Mshreg_reset_pipe2_19_1        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1                                                                 |
-| +inst_flash_port                 |           | 81/81         | 65/65         | 54/54         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_flash_port                                                                                       |
-| +inst_gpio_wb                    |           | 285/285       | 298/298       | 433/433       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_gpio_wb                                                                                          |
-| +inst_mips_top                   |           | 23/2822       | 22/1961       | 12/4222       | 2/611         | 0/27      | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top                                                                                         |
-| ++Mshreg_reset_delay_15          |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/Mshreg_reset_delay_15                                                                   |
-| ++Mshreg_reset_delay_19          |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/Mshreg_reset_delay_19                                                                   |
-| ++Mshreg_reset_delay_30          |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/Mshreg_reset_delay_30                                                                   |
-| ++inst_biu                       |           | 177/800       | 97/570        | 211/936       | 0/350         | 0/27      | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu                                                                                |
-| +++inst_bin_fifo                 |           | 2/100         | 0/62          | 2/107         | 0/74          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo                                                                  |
-| ++++inst_dpram_1w1r              |           | 57/57         | 32/32         | 64/64         | 64/64         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r                                                  |
-| ++++inst_fifo_async_ctrl         |           | 13/41         | 12/30         | 6/41          | 0/10          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl                                             |
-| +++++Mshreg_gcnt2_r_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0                            |
-| +++++Mshreg_gcnt2_r_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1                            |
-| +++++Mshreg_gcnt2_r_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2                            |
-| +++++Mshreg_gcnt2_r_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3                            |
-| +++++Mshreg_gcnt2_r_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4                            |
-| +++++Mshreg_gcnt2_w_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0                            |
-| +++++Mshreg_gcnt2_w_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1                            |
-| +++++Mshreg_gcnt2_w_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2                            |
-| +++++Mshreg_gcnt2_w_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3                            |
-| +++++Mshreg_gcnt2_w_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4                            |
-| +++++inst_gray_counter_r         |           | 10/10         | 9/9           | 13/13         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r                         |
-| +++++inst_gray_counter_w         |           | 8/8           | 9/9           | 12/12         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w                         |
-| +++inst_bout_fifo                |           | 3/146         | 0/97          | 3/179         | 0/144         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo                                                                 |
-| ++++inst_dpram_1w1r              |           | 102/102       | 67/67         | 134/134       | 134/134       | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r                                                 |
-| ++++inst_fifo_async_ctrl         |           | 12/41         | 12/30         | 6/42          | 0/10          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl                                            |
-| +++++Mshreg_gcnt2_r_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0                           |
-| +++++Mshreg_gcnt2_r_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1                           |
-| +++++Mshreg_gcnt2_r_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2                           |
-| +++++Mshreg_gcnt2_r_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3                           |
-| +++++Mshreg_gcnt2_r_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4                           |
-| +++++Mshreg_gcnt2_w_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0                           |
-| +++++Mshreg_gcnt2_w_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1                           |
-| +++++Mshreg_gcnt2_w_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2                           |
-| +++++Mshreg_gcnt2_w_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3                           |
-| +++++Mshreg_gcnt2_w_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4                           |
-| +++++inst_gray_counter_r         |           | 9/9           | 9/9           | 13/13         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r                        |
-| +++++inst_gray_counter_w         |           | 10/10         | 9/9           | 13/13         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w                        |
-| +++inst_dcache                   |           | 172/172       | 156/156       | 155/155       | 0/0           | 0/9       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache                                                                    |
-| ++++gen_data_ram[0].inst_data_ra |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram                                      |
-| ++++gen_data_ram[1].inst_data_ra |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram                                      |
-| ++++gen_data_ram[2].inst_data_ra |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram                                      |
-| ++++gen_data_ram[3].inst_data_ra |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram                                      |
-| ++++inst_tag_ram                 |           | 0/0           | 0/0           | 0/0           | 0/0           | 1/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram                                                       |
-| +++inst_icache                   |           | 117/117       | 81/81         | 123/123       | 0/0           | 0/18      | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_icache                                                                    |
-| ++++inst_data_ram                |           | 0/0           | 0/0           | 0/0           | 0/0           | 16/16     | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram                                                      |
-| ++++inst_tag_ram                 |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram                                                       |
-| +++inst_write_fifo               |           | 2/88          | 0/77          | 2/161         | 0/132         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_write_fifo                                                                |
-| ++++inst_dpram_1w1r              |           | 66/66         | 66/66         | 132/132       | 132/132       | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r                                                |
-| ++++inst_fifo_sync_ctrl          |           | 20/20         | 11/11         | 27/27         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl                                            |
-| ++inst_cop                       |           | 219/219       | 190/190       | 234/234       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_cop                                                                                |
-| ++inst_pipeline                  |           | 880/1777      | 651/1179      | 1380/3037     | 0/256         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline                                                                           |
-| +++inst_alu                      |           | 63/63         | 1/1           | 119/119       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline/inst_alu                                                                  |
-| +++inst_bcu                      |           | 8/8           | 0/0           | 16/16         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline/inst_bcu                                                                  |
-| +++inst_muldiv                   |           | 554/554       | 527/527       | 1028/1028     | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv                                                               |
-| +++inst_reg_dual                 |           | 128/128       | 0/0           | 256/256       | 256/256       | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual                                                             |
-| +++inst_shifter                  |           | 144/144       | 0/0           | 238/238       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_mips_top/inst_pipeline/inst_shifter                                                              |
-| +inst_ps2_phy_0                  |           | 0/10          | 0/10          | 0/18          | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_0                                                                                        |
-| ++Inst_debounce_clk              |           | 5/5           | 5/5           | 9/9           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_0/Inst_debounce_clk                                                                      |
-| ++Inst_debounce_data             |           | 5/5           | 5/5           | 9/9           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_0/Inst_debounce_data                                                                     |
-| +inst_ps2_phy_1                  |           | 0/12          | 0/10          | 0/18          | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_1                                                                                        |
-| ++Inst_debounce_clk              |           | 7/7           | 5/5           | 9/9           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_1/Inst_debounce_clk                                                                      |
-| ++Inst_debounce_data             |           | 5/5           | 5/5           | 9/9           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_phy_1/Inst_debounce_data                                                                     |
-| +inst_ps2_wb_0                   |           | 33/159        | 30/139        | 23/169        | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_wb_0                                                                                         |
-| ++inst_ps2_core                  |           | 126/126       | 109/109       | 146/146       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_wb_0/inst_ps2_core                                                                           |
-| +inst_ps2_wb_1                   |           | 33/146        | 30/139        | 21/167        | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_wb_1                                                                                         |
-| ++inst_ps2_core                  |           | 113/113       | 109/109       | 146/146       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_ps2_wb_1/inst_ps2_core                                                                           |
-| +inst_rom_wb                     |           | 1/77          | 1/99          | 1/53          | 0/2           | 0/4       | 0/0     | 0/2   | 0/0   | 0/0   | 0/0   | mips_sys/inst_rom_wb                                                                                           |
-| ++inst_rom                       |           | 76/76         | 98/98         | 52/52         | 2/2           | 4/4       | 0/0     | 2/2   | 0/0   | 0/0   | 0/0   | mips_sys/inst_rom_wb/inst_rom                                                                                  |
-| +inst_sdram_ctrl_frontend_wb     |           | 100/629       | 0/455         | 145/593       | 0/39          | 0/6       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb                                                                           |
-| ++inst_cat_fifo                  |           | 2/15          | 0/13          | 2/23          | 0/0           | 0/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo                                                             |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 1/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r                                             |
-| +++inst_fifo_sync_ctrl           |           | 13/13         | 13/13         | 21/21         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl                                         |
-| ++inst_read_fifo                 |           | 2/50          | 0/36          | 2/54          | 0/12          | 0/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo                                                            |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r                                            |
-| +++inst_fifo_async_ctrl          |           | 17/48         | 14/36         | 10/52         | 0/12          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl                                       |
-| ++++Mshreg_gcnt2_r_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0                      |
-| ++++Mshreg_gcnt2_r_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1                      |
-| ++++Mshreg_gcnt2_r_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2                      |
-| ++++Mshreg_gcnt2_r_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3                      |
-| ++++Mshreg_gcnt2_r_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4                      |
-| ++++Mshreg_gcnt2_r_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5                      |
-| ++++Mshreg_gcnt2_w_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0                      |
-| ++++Mshreg_gcnt2_w_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1                      |
-| ++++Mshreg_gcnt2_w_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2                      |
-| ++++Mshreg_gcnt2_w_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3                      |
-| ++++Mshreg_gcnt2_w_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4                      |
-| ++++Mshreg_gcnt2_w_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5                      |
-| ++++inst_gray_counter_r          |           | 9/9           | 11/11         | 15/15         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r                   |
-| ++++inst_gray_counter_w          |           | 10/10         | 11/11         | 15/15         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w                   |
-| ++inst_sdram_ctrl                |           | 0/410         | 0/370         | 0/317         | 0/15          | 0/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl                                                           |
-| +++inst_ddr_phy                  |           | 167/168       | 216/216       | 2/3           | 0/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy                                              |
-| ++++Mshreg_u_tag_pipe_4_0        |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0                        |
-| +++inst_sd_cmd_fifo              |           | 4/61          | 0/41          | 6/58          | 0/14          | 0/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo                                          |
-| ++++inst_dpram_1w1r              |           | 0/0           | 0/0           | 0/0           | 0/0           | 1/1       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r                          |
-| ++++inst_fifo_async_ctrl         |           | 19/57         | 17/41         | 9/52          | 0/14          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl                     |
-| +++++Mshreg_gcnt2_r_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0    |
-| +++++Mshreg_gcnt2_r_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1    |
-| +++++Mshreg_gcnt2_r_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2    |
-| +++++Mshreg_gcnt2_r_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4    |
-| +++++Mshreg_gcnt2_r_5            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5    |
-| +++++Mshreg_gcnt2_w_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0    |
-| +++++Mshreg_gcnt2_w_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1    |
-| +++++Mshreg_gcnt2_w_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2    |
-| +++++Mshreg_gcnt2_w_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3    |
-| +++++Mshreg_gcnt2_w_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4    |
-| +++++Mshreg_gcnt2_w_5            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5    |
-| +++++Mshreg_p2_3_BRB0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB0    |
-| +++++Mshreg_p2_3_BRB1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1    |
-| +++++Mshreg_p2_3_BRB2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2    |
-| +++++inst_gray_counter_r         |           | 14/14         | 13/13         | 14/14         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r |
-| +++++inst_gray_counter_w         |           | 10/10         | 11/11         | 15/15         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w |
-| +++inst_sdram_cmd                |           | 47/47         | 13/13         | 65/65         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd                                            |
-| +++inst_sdram_ctrl               |           | 134/134       | 100/100       | 191/191       | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl                                           |
-| ++inst_write_fifo                |           | 3/54          | 0/36          | 3/54          | 0/12          | 0/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo                                                           |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r                                           |
-| +++inst_fifo_async_ctrl          |           | 18/51         | 14/36         | 9/51          | 0/12          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl                                      |
-| ++++Mshreg_gcnt2_r_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0                     |
-| ++++Mshreg_gcnt2_r_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1                     |
-| ++++Mshreg_gcnt2_r_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2                     |
-| ++++Mshreg_gcnt2_r_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3                     |
-| ++++Mshreg_gcnt2_r_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4                     |
-| ++++Mshreg_gcnt2_r_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5                     |
-| ++++Mshreg_gcnt2_w_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0                     |
-| ++++Mshreg_gcnt2_w_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1                     |
-| ++++Mshreg_gcnt2_w_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2                     |
-| ++++Mshreg_gcnt2_w_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3                     |
-| ++++Mshreg_gcnt2_w_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4                     |
-| ++++Mshreg_gcnt2_w_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5                     |
-| ++++inst_gray_counter_r          |           | 10/10         | 11/11         | 15/15         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r                  |
-| ++++inst_gray_counter_w          |           | 11/11         | 11/11         | 15/15         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w                  |
-| +inst_uart_wb_0                  |           | 61/109        | 64/106        | 43/111        | 0/36          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0                                                                                        |
-| ++inst_uart_rx                   |           | 0/30          | 0/28          | 0/38          | 0/27          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_rx                                                                           |
-| +++buf                           |           | 8/8           | 5/5           | 16/16         | 8/8           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_rx/buf                                                                       |
-| +++kcuart                        |           | 22/22         | 23/23         | 22/22         | 19/19         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart                                                                    |
-| ++inst_uart_tx                   |           | 0/18          | 0/14          | 0/30          | 0/9           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_tx                                                                           |
-| +++buf                           |           | 8/8           | 5/5           | 16/16         | 8/8           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_tx/buf                                                                       |
-| +++kcuart                        |           | 10/10         | 9/9           | 14/14         | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart                                                                    |
-| +inst_uart_wb_1                  |           | 60/107        | 64/108        | 42/110        | 0/36          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1                                                                                        |
-| ++inst_uart_rx                   |           | 0/28          | 0/29          | 0/38          | 0/27          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_rx                                                                           |
-| +++buf                           |           | 8/8           | 5/5           | 16/16         | 8/8           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_rx/buf                                                                       |
-| +++kcuart                        |           | 20/20         | 24/24         | 22/22         | 19/19         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart                                                                    |
-| ++inst_uart_tx                   |           | 0/19          | 0/15          | 0/30          | 0/9           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_tx                                                                           |
-| +++buf                           |           | 8/8           | 5/5           | 16/16         | 8/8           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_tx/buf                                                                       |
-| +++kcuart                        |           | 11/11         | 10/10         | 14/14         | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart                                                                    |
-| +inst_usb_port                   |           | 36/36         | 27/27         | 31/31         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_usb_port                                                                                         |
-| +inst_vga_frontend               |           | 762/1384      | 793/1251      | 762/1553      | 0/264         | 0/13      | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend                                                                                     |
-| ++inst_blitfifo                  |           | 4/31          | 0/23          | 4/45          | 0/0           | 0/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_blitfifo                                                                       |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r                                                       |
-| +++inst_fifo_sync_ctrl           |           | 27/27         | 23/23         | 41/41         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl                                                   |
-| ++inst_bus_fifo                  |           | 4/115         | 0/110         | 4/219         | 0/206         | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_bus_fifo                                                                       |
-| +++inst_dpram_1w1r               |           | 103/103       | 103/103       | 206/206       | 206/206       | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r                                                       |
-| +++inst_fifo_sync_ctrl           |           | 8/8           | 7/7           | 9/9           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl                                                   |
-| ++inst_char_gen                  |           | 202/214       | 126/126       | 240/252       | 0/12          | 0/4       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen                                                                       |
-| +++Mshreg_csr_posx_synced_0      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0                                              |
-| +++Mshreg_csr_posx_synced_1      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1                                              |
-| +++Mshreg_csr_posx_synced_2      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2                                              |
-| +++Mshreg_csr_posx_synced_3      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_3                                              |
-| +++Mshreg_csr_posx_synced_4      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_4                                              |
-| +++Mshreg_csr_posx_synced_5      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_5                                              |
-| +++Mshreg_csr_posx_synced_6      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_6                                              |
-| +++Mshreg_csr_posy_synced_0      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_0                                              |
-| +++Mshreg_csr_posy_synced_1      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_1                                              |
-| +++Mshreg_csr_posy_synced_2      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_2                                              |
-| +++Mshreg_csr_posy_synced_3      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_3                                              |
-| +++Mshreg_csr_posy_synced_4      |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4                                              |
-| +++inst_ascii_ram                |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram                                                        |
-| +++inst_char_rom                 |           | 0/0           | 0/0           | 0/0           | 0/0           | 2/2       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom                                                         |
-| ++inst_linefifo                  |           | 2/161         | 0/149         | 2/177         | 0/46          | 0/7       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo                                                                       |
-| +++inst_dpram_1w1r               |           | 0/0           | 0/0           | 0/0           | 0/0           | 7/7       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r                                                       |
-| +++inst_fifo_async_ctrl          |           | 72/159        | 91/149        | 81/175        | 0/46          | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl                                                  |
-| ++++Mshreg_bcnt2_ar_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0                                |
-| ++++Mshreg_bcnt2_ar_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1                                |
-| ++++Mshreg_bcnt2_ar_10           |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10                               |
-| ++++Mshreg_bcnt2_ar_11           |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_11                               |
-| ++++Mshreg_bcnt2_ar_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_2                                |
-| ++++Mshreg_bcnt2_ar_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_3                                |
-| ++++Mshreg_bcnt2_ar_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_4                                |
-| ++++Mshreg_bcnt2_ar_5            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_5                                |
-| ++++Mshreg_bcnt2_ar_6            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_6                                |
-| ++++Mshreg_bcnt2_ar_7            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_7                                |
-| ++++Mshreg_bcnt2_ar_8            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_8                                |
-| ++++Mshreg_bcnt2_ar_9            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_9                                |
-| ++++Mshreg_bcnt2_aw_0            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_0                                |
-| ++++Mshreg_bcnt2_aw_1            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_1                                |
-| ++++Mshreg_bcnt2_aw_10           |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_10                               |
-| ++++Mshreg_bcnt2_aw_11           |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_11                               |
-| ++++Mshreg_bcnt2_aw_2            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_2                                |
-| ++++Mshreg_bcnt2_aw_3            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_3                                |
-| ++++Mshreg_bcnt2_aw_4            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_4                                |
-| ++++Mshreg_bcnt2_aw_5            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_5                                |
-| ++++Mshreg_bcnt2_aw_6            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_6                                |
-| ++++Mshreg_bcnt2_aw_7            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_7                                |
-| ++++Mshreg_bcnt2_aw_8            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_8                                |
-| ++++Mshreg_bcnt2_aw_9            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_9                                |
-| ++++Mshreg_gcnt2_r_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0                                 |
-| ++++Mshreg_gcnt2_r_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1                                 |
-| ++++Mshreg_gcnt2_r_10            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_10                                |
-| ++++Mshreg_gcnt2_r_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2                                 |
-| ++++Mshreg_gcnt2_r_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3                                 |
-| ++++Mshreg_gcnt2_r_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4                                 |
-| ++++Mshreg_gcnt2_r_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5                                 |
-| ++++Mshreg_gcnt2_r_6             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_6                                 |
-| ++++Mshreg_gcnt2_r_7             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_7                                 |
-| ++++Mshreg_gcnt2_r_8             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_8                                 |
-| ++++Mshreg_gcnt2_r_9             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_9                                 |
-| ++++Mshreg_gcnt2_w_0             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0                                 |
-| ++++Mshreg_gcnt2_w_1             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1                                 |
-| ++++Mshreg_gcnt2_w_10            |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_10                                |
-| ++++Mshreg_gcnt2_w_2             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2                                 |
-| ++++Mshreg_gcnt2_w_3             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3                                 |
-| ++++Mshreg_gcnt2_w_4             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4                                 |
-| ++++Mshreg_gcnt2_w_5             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5                                 |
-| ++++Mshreg_gcnt2_w_6             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_6                                 |
-| ++++Mshreg_gcnt2_w_7             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7                                 |
-| ++++Mshreg_gcnt2_w_8             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8                                 |
-| ++++Mshreg_gcnt2_w_9             |           | 1/1           | 0/0           | 1/1           | 1/1           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9                                 |
-| ++++inst_gray_counter_r          |           | 20/20         | 23/23         | 24/24         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r                              |
-| ++++inst_gray_counter_w          |           | 21/21         | 35/35         | 24/24         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w                              |
-| ++inst_vga_backend               |           | 61/101        | 24/50         | 62/98         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_vga_backend                                                                    |
-| +++inst_vga_timing               |           | 0/40          | 0/26          | 0/36          | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing                                                    |
-| ++++inst_vga_sync_h              |           | 21/21         | 13/13         | 18/18         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h                                    |
-| ++++inst_vga_sync_v              |           | 19/19         | 13/13         | 18/18         | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v                                    |
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-* Slices can be packed with basic elements from multiple hierarchies.
-  Therefore, a slice will be counted in every hierarchical module
-  that each of its packed basic elements belong to.
-** For each column, there are two numbers reported <A>/<B>.
-   <A> is the number of elements that belong to that specific hierarchical module.
-   <B> is the total number of elements from that hierarchical module and any lower level
-   hierarchical modules below.
-*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
deleted file mode 100644
index db0d3e8..0000000
--- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+++ /dev/null
@@ -1,47 +0,0 @@
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\ps2_port\src\ps2_core.vhd"
-vhdl work "W:\vhdl\lib\ps2_port\src\debounce.vhd"
-vhdl work "W:\vhdl\lib\misc\async_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
-vhdl work "W:\vhdl\lib\ps2_port\src\ps2_wb.vhd"
-vhdl work "W:\vhdl\lib\ps2_port\src\ps2_phy_virtex.vhd"
-vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf
deleted file mode 100644
index f8198e9..0000000
--- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf
+++ /dev/null
@@ -1,503 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
-
-NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
-TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_ssram_a<24> LOC = T21;
-NET sys_flash_ssram_a<23> LOC = U20;
-NET sys_flash_ssram_a<22> LOC = T19;
-NET sys_flash_ssram_a<21> LOC = AC5;
-NET sys_flash_ssram_a<20> LOC = AB5;
-NET sys_flash_ssram_a<19> LOC = AC4;
-NET sys_flash_ssram_a<18> LOC = AB4;
-NET sys_flash_ssram_a<17> LOC = AB3;
-NET sys_flash_ssram_a<16> LOC = AA4;
-NET sys_flash_ssram_a<15> LOC = AA3;
-NET sys_flash_ssram_a<14> LOC = W5;
-NET sys_flash_ssram_a<13> LOC = W6;
-NET sys_flash_ssram_a<12> LOC = W3;
-NET sys_flash_ssram_a<11> LOC = AF3;
-NET sys_flash_ssram_a<10>  LOC = AE3;
-NET sys_flash_ssram_a<9>  LOC = AD2;
-NET sys_flash_ssram_a<8>  LOC = AD1;
-NET sys_flash_ssram_a<7>  LOC = AC2;
-NET sys_flash_ssram_a<6>  LOC = AC1;
-NET sys_flash_ssram_a<5>  LOC = AB2;
-NET sys_flash_ssram_a<4>  LOC = AB1;
-NET sys_flash_ssram_a<3>  LOC = AA1;
-NET sys_flash_ssram_a<2>  LOC = Y2;
-NET sys_flash_ssram_a<1>  LOC = Y1;
-NET sys_flash_ssram_a<0>  LOC = T20;
-NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_a<*>  SLEW = FAST;
-NET sys_flash_ssram_a<*>  DRIVE = 8;
-
-
-NET sys_flash_ssram_d<31> LOC = F14;
-NET sys_flash_ssram_d<30> LOC = F13;
-NET sys_flash_ssram_d<29> LOC = F12;
-NET sys_flash_ssram_d<28> LOC = F11;
-NET sys_flash_ssram_d<27> LOC = F16;
-NET sys_flash_ssram_d<26> LOC = F15;
-NET sys_flash_ssram_d<25> LOC = D14;
-NET sys_flash_ssram_d<24> LOC = D13;
-NET sys_flash_ssram_d<23> LOC = D15;
-NET sys_flash_ssram_d<22> LOC = E14;
-NET sys_flash_ssram_d<21> LOC = C11;
-NET sys_flash_ssram_d<20> LOC = D11;
-NET sys_flash_ssram_d<19> LOC = D16;
-NET sys_flash_ssram_d<18> LOC = C16;
-NET sys_flash_ssram_d<17> LOC = E13;
-NET sys_flash_ssram_d<16> LOC = D12;
-NET sys_flash_ssram_d<15> LOC = AA14;
-NET sys_flash_ssram_d<14> LOC = AB14;
-NET sys_flash_ssram_d<13> LOC = AC12;
-NET sys_flash_ssram_d<12> LOC = AC11;
-NET sys_flash_ssram_d<11> LOC = AA16;
-NET sys_flash_ssram_d<10> LOC = AA15;
-NET sys_flash_ssram_d<9>  LOC = AB13;
-NET sys_flash_ssram_d<8>  LOC = AA13;
-NET sys_flash_ssram_d<7>  LOC = AC14;
-NET sys_flash_ssram_d<6>  LOC = AD14;
-NET sys_flash_ssram_d<5>  LOC = AA12;
-NET sys_flash_ssram_d<4>  LOC = AA11;
-NET sys_flash_ssram_d<3>  LOC = AC16;
-NET sys_flash_ssram_d<2>  LOC = AC15;
-NET sys_flash_ssram_d<1>  LOC = AC13;
-NET sys_flash_ssram_d<0>  LOC = AD13;
-NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_ssram_d<*> DRIVE = 12;
-NET sys_flash_ssram_d<*> SLEW = FAST;
-NET sys_flash_ssram_d<*> PULLDOWN;
-
-NET sys_flash_ssram_oe_n     LOC = AC6;
-NET sys_flash_ssram_oe_n    IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_oe_n SLEW = FAST;
-NET sys_flash_ssram_oe_n DRIVE = 8;
-
-NET sys_flash_ssram_we_n     LOC = AB6;
-NET sys_flash_ssram_we_n    IOSTANDARD = LVDCI_33;
-NET sys_flash_ssram_we_n SLEW = FAST;
-NET sys_flash_ssram_we_n DRIVE = 8;
-
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_rstn    LOC = AD10;
-NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_rstn    DRIVE = 8;
-NET sys_flash_rstn    SLEW = FAST;
-NET sys_flash_rstn           TIG;
-
-NET sys_flash_byten   LOC = N22;
-NET sys_flash_byten          IOSTANDARD = LVCMOS33;
-NET sys_flash_byten          DRIVE = 8;
-NET sys_flash_byten          SLEW = FAST;
-NET sys_flash_byten          TIG;
-
-# SSRAM
-NET sys_ssram_clk            LOC = AF7;
-NET sys_ssram_clk            IOSTANDARD = LVCMOS33;
-NET sys_ssram_clk            DRIVE = 16;
-NET sys_ssram_clk            SLEW = FAST;
-
-NET "sys_ssram_clk" TNM_NET = "ssram_clk";
-#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
-
-
-NET sys_ssram_clk_fb         LOC = AD17;
-NET sys_ssram_clk_fb         IOSTANDARD = LVCMOS33;
-
-# Timing Constraint for Feedback Clock
-NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
-
-NET sys_ssram_ce_n           LOC = V7;
-NET sys_ssram_ce_n           IOSTANDARD = LVDCI_33;
-NET sys_ssram_ce_n           SLEW = FAST;
-NET sys_ssram_ce_n           DRIVE = 8;
-
-NET sys_ssram_bw_n<3>        LOC = Y3; #Y4; 
-NET sys_ssram_bw_n<2>        LOC = Y4; #Y3;
-NET sys_ssram_bw_n<1>        LOC = Y5; #Y6;
-NET sys_ssram_bw_n<0>        LOC = Y6; #Y5;
-NET sys_ssram_bw_n<*>        IOSTANDARD = LVDCI_33;
-NET sys_ssram_bw_n<*>        SLEW = FAST;
-NET sys_ssram_bw_n<*>        DRIVE = 8;
-
-NET sys_ssram_adv            LOC = W4;
-NET sys_ssram_adv            IOSTANDARD = LVDCI_33;
-NET sys_ssram_adv            SLEW = FAST;
-NET sys_ssram_adv            DRIVE = 8;
-
-NET sys_ssram_mode           LOC = V26;
-NET sys_ssram_mode           IOSTANDARD = LVDCI_33;
-NET sys_ssram_mode           SLEW = FAST;
-NET sys_ssram_mode           DRIVE = 8;
-
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
deleted file mode 100644
index 14e7129..0000000
--- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
+++ /dev/null
@@ -1,629 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "CLK_O" TNM_NET = "sys_clk";
-TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
-
-NET "sdram_clk0" TNM_NET = "sdram_clk";
-TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %;
-TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
-
-NET "vga_clk" TNM_NET = "vga_clk";
-TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
-TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
-
-NET "cpu_clk" TNM_NET = "cpu_clk";
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
-#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "RST_O" TIG;
-
-#NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
-#PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
-
-#NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
-#PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4;
-#INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3;
-
-# ---------------------------------------------------------------------------------
-# Floor planning
-# ---------------------------------------------------------------------------------
-#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ;
-#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ;
-#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ;
-
-#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ;
-#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ;
-
-INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
-# GOOD 1
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
-
-# GOOD 2 (smaller)
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
-
-# GOOD 3 (even smaller)
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
-
-# GOOD 4 (even more smaller)
-AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
-AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
-
-# TEMP 4
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y54:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
-
-# TEMP 4.1
-#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y55:SLICE_X39Y0 ;
-#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_uart0_rx LOC = W2;
-NET sys_uart0_rx IOSTANDARD = LVCMOS33;
-NET sys_uart0_rx TIG;
-NET sys_uart0_tx LOC = W1;
-NET sys_uart0_tx IOSTANDARD = LVCMOS33;
-NET sys_uart0_tx TIG;
-
-NET sys_uart1_rx LOC = AF24;
-NET sys_uart1_rx IOSTANDARD = LVCMOS33;
-NET sys_uart1_rx TIG;
-NET sys_uart1_tx LOC = AE24;
-NET sys_uart1_tx IOSTANDARD = LVCMOS33;
-NET sys_uart1_tx TIG;
-
-NET sys_uart2_rx LOC = AD22;
-NET sys_uart2_rx IOSTANDARD = LVCMOS33;
-NET sys_uart2_rx TIG;
-NET sys_uart2_tx LOC = AB21;
-NET sys_uart2_tx IOSTANDARD = LVCMOS33;
-NET sys_uart2_tx TIG;
-
-NET sys_uart3_rx LOC = W20;
-NET sys_uart3_rx IOSTANDARD = LVCMOS33;
-NET sys_uart3_rx TIG;
-NET sys_uart3_tx LOC = W21;
-NET sys_uart3_tx IOSTANDARD = LVCMOS33;
-NET sys_uart3_tx TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-NET sys_usb_d<*>   IOBDELAY = NONE; 
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_a<24> LOC = T21;
-NET sys_flash_a<23> LOC = U20;
-NET sys_flash_a<22> LOC = T19;
-NET sys_flash_a<21> LOC = AC5;
-NET sys_flash_a<20> LOC = AB5;
-NET sys_flash_a<19> LOC = AC4;
-NET sys_flash_a<18> LOC = AB4;
-NET sys_flash_a<17> LOC = AB3;
-NET sys_flash_a<16> LOC = AA4;
-NET sys_flash_a<15> LOC = AA3;
-NET sys_flash_a<14> LOC = W5;
-NET sys_flash_a<13> LOC = W6;
-NET sys_flash_a<12> LOC = W3;
-NET sys_flash_a<11> LOC = AF3;
-NET sys_flash_a<10>  LOC = AE3;
-NET sys_flash_a<9>  LOC = AD2;
-NET sys_flash_a<8>  LOC = AD1;
-NET sys_flash_a<7>  LOC = AC2;
-NET sys_flash_a<6>  LOC = AC1;
-NET sys_flash_a<5>  LOC = AB2;
-NET sys_flash_a<4>  LOC = AB1;
-NET sys_flash_a<3>  LOC = AA1;
-NET sys_flash_a<2>  LOC = Y2;
-NET sys_flash_a<1>  LOC = Y1;
-NET sys_flash_a<0>  LOC = T20;
-
-NET sys_flash_d<31> LOC = F14;
-NET sys_flash_d<30> LOC = F13;
-NET sys_flash_d<29> LOC = F12;
-NET sys_flash_d<28> LOC = F11;
-NET sys_flash_d<27> LOC = F16;
-NET sys_flash_d<26> LOC = F15;
-NET sys_flash_d<25> LOC = D14;
-NET sys_flash_d<24> LOC = D13;
-NET sys_flash_d<23> LOC = D15;
-NET sys_flash_d<22> LOC = E14;
-NET sys_flash_d<21> LOC = C11;
-NET sys_flash_d<20> LOC = D11;
-NET sys_flash_d<19> LOC = D16;
-NET sys_flash_d<18> LOC = C16;
-NET sys_flash_d<17> LOC = E13;
-NET sys_flash_d<16> LOC = D12;
-NET sys_flash_d<15> LOC = AA14;
-NET sys_flash_d<14> LOC = AB14;
-NET sys_flash_d<13> LOC = AC12;
-NET sys_flash_d<12> LOC = AC11;
-NET sys_flash_d<11> LOC = AA16;
-NET sys_flash_d<10> LOC = AA15;
-NET sys_flash_d<9>  LOC = AB13;
-NET sys_flash_d<8>  LOC = AA13;
-NET sys_flash_d<7>  LOC = AC14;
-NET sys_flash_d<6>  LOC = AD14;
-NET sys_flash_d<5>  LOC = AA12;
-NET sys_flash_d<4>  LOC = AA11;
-NET sys_flash_d<3>  LOC = AC16;
-NET sys_flash_d<2>  LOC = AC15;
-NET sys_flash_d<1>  LOC = AC13;
-NET sys_flash_d<0>  LOC = AD13;
-NET sys_flash_rdn     LOC = AC6;
-NET sys_flash_wrn     LOC = AB6;
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_ac97_rstn    LOC = AD10;
-NET sys_flash_byten   LOC = N22;
-
-NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_a<*>  SLEW = FAST;
-NET sys_flash_a<*>  DRIVE = 8;
-
-NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_d<*> DRIVE = 12;
-NET sys_flash_d<*> SLEW = FAST;
-NET sys_flash_d<*> IOBDELAY = NONE; 
-NET sys_flash_d<*> PULLDOWN;
-
-NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
-NET sys_flash_rdn SLEW = FAST;
-NET sys_flash_rdn DRIVE = 8;
-
-NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
-NET sys_flash_wrn SLEW = FAST;
-NET sys_flash_wrn DRIVE = 8;
-
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_ac97_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_ac97_rstn    DRIVE = 8;
-NET sys_flash_ac97_rstn    SLEW = FAST;
-NET sys_flash_ac97_rstn    TIG;
-
-NET sys_flash_byten    IOSTANDARD = LVCMOS33;
-NET sys_flash_byten    DRIVE = 8;
-NET sys_flash_byten    SLEW = FAST;
-NET sys_flash_byten    TIG;
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for AC97 Sound Controller
-#------------------------------------------------------------------------------
-NET "sys_ac97_bit_clk"  TNM_NET = "ac97_clk";
-TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
-
-NET sys_ac97_bit_clk   LOC = AE10;
-NET sys_ac97_bit_clk   IOSTANDARD = LVCMOS33;
-NET sys_ac97_bit_clk   PERIOD = 80;
-NET sys_ac97_sdata_in  LOC = AD16;
-NET sys_ac97_sdata_in  IOSTANDARD = LVCMOS33;
-NET sys_ac97_sdata_out LOC = C8;
-NET sys_ac97_sdata_out SLEW = FAST;
-NET sys_ac97_ssync     LOC = D9;
-NET sys_ac97_ssync     SLEW = FAST;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for PS/2 Ports
-#------------------------------------------------------------------------------
-
-#Keyboard
-NET sys_ps2_0_clk  LOC = D2;
-NET sys_ps2_0_clk  SLEW = SLOW;
-NET sys_ps2_0_clk  DRIVE = 2;
-NET sys_ps2_0_clk  TIG;
-NET sys_ps2_0_data LOC = G9;
-NET sys_ps2_0_data SLEW = SLOW;
-NET sys_ps2_0_data DRIVE = 2;
-NET sys_ps2_0_data TIG;
-
-#Mouse
-NET sys_ps2_1_clk  LOC = B14;
-NET sys_ps2_1_clk  SLEW = SLOW;
-NET sys_ps2_1_clk  DRIVE = 2;
-NET sys_ps2_1_clk  TIG;
-NET sys_ps2_1_data LOC = C14;
-NET sys_ps2_1_data SLEW = SLOW;
-NET sys_ps2_1_data DRIVE = 2;
-NET sys_ps2_1_data TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for Ethernet PHY
-#------------------------------------------------------------------------------
-# MDC
-Net sys_phy_mdc LOC = D1;
-Net sys_phy_mdc IOSTANDARD = LVCMOS25;
-
-# MDIO
-Net sys_phy_mdio LOC = G4;
-Net sys_phy_mdio IOSTANDARD = LVCMOS25;
-
-# /RST
-Net sys_phy_rstn LOC = D10;
-Net sys_phy_rstn TIG;
-
-# INT
-Net sys_phy_int LOC = H4;
-Net sys_phy_int TIG;
-
-#### Module Ethernet_MAC constraints
-
-NET "sys_phy_tx_clk" TNM_NET = "phy_tx_clk";
-TIMESPEC "TS_phy_tx_clk" = PERIOD "phy_tx_clk" 8.0 ns HIGH 50 %;
-
-NET "sys_phy_rx_clk" TNM_NET = "phy_rx_clk";
-TIMESPEC "TS_phy_rx_clk" = PERIOD "phy_rx_clk" 8.0 ns HIGH 50 %;
-
-Net sys_phy_crs LOC = D5;
-Net sys_phy_col LOC = E3;
-
-Net sys_phy_tx_clk LOC=C15;
-Net sys_phy_tx_en LOC = F4;
-Net sys_phy_tx_er LOC=F3;
-Net sys_phy_gtx_clk LOC=G10;
-
-Net sys_phy_rx_clk LOC=B15;
-Net sys_phy_rx_dv LOC=A9;
-Net sys_phy_rx_er LOC=B9;
-
-Net sys_phy_tx<0> LOC=H1;
-Net sys_phy_tx<1> LOC=H2;
-Net sys_phy_tx<2> LOC=H3;
-Net sys_phy_tx<3> LOC=G1;
-Net sys_phy_tx<4> LOC=G2;
-Net sys_phy_tx<5> LOC=H5;
-Net sys_phy_tx<6> LOC=H6;
-Net sys_phy_tx<7> LOC=G3;
-
-Net sys_phy_rx<0> LOC=F1;
-Net sys_phy_rx<1> LOC=E1;
-Net sys_phy_rx<2> LOC=D4;
-Net sys_phy_rx<3> LOC=C4;
-Net sys_phy_rx<4> LOC=B4;
-Net sys_phy_rx<5> LOC=A4;
-Net sys_phy_rx<6> LOC=B3;
-Net sys_phy_rx<7> LOC=A3;
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
deleted file mode 100644
index 0916a32..0000000
--- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj
+++ /dev/null
@@ -1,43 +0,0 @@
-vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../src/sdram_config.vhd"
-vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
-vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
-vhdl work "../../../../lib/uart/kcuart_tx.vhd"
-vhdl work "../../../../lib/uart/kcuart_rx.vhd"
-vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
-vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
-vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
-vhdl work "../../src/sys_types.vhd"
-vhdl work "../../src/ram_ld.vhd"
-vhdl work "../../src/bootloader.ROM_ld.vhd"
-vhdl work "../../../../lib/uart/uart_tx.vhd"
-vhdl work "../../../../lib/uart/uart_rx.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vhdl work "../../../../lib/uart/uart_wb.vhd"
-vhdl work "../../../../lib/misc/rom_wb.vhd"
-vhdl work "../../../../lib/misc/ram_wb.vhd"
-vhdl work "../../../../lib/misc/lcd_port.vhd"
-vhdl work "../../../../lib/misc/gpio_wb.vhd"
-vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
-vhdl work "../../../../lib/misc/async_port_wb.vhd"
-vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-vhdl work "../../src/mips_sys.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
deleted file mode 100644
index 49db644..0000000
--- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+++ /dev/null
@@ -1,43 +0,0 @@
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
-vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
-vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
-vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
-vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
-vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
-vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf
deleted file mode 100644
index 07b8d92..0000000
--- a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf
+++ /dev/null
@@ -1,469 +0,0 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#
-#     (c) Copyright 2005 Xilinx, Inc.
-#     All rights reserved.
-#
-
-CONFIG STEPPING = "ES";
-
-# Bus clock nets
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
-
-NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
-#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
-TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
-
-NET "sys_clk_in" LOC = "AE14";
-NET sys_clk_in IOSTANDARD = LVCMOS33;
-NET "sys_rst_n_in" LOC = "D6";
-NET sys_rst_n_in PULLUP;
-NET "sys_rst_n_in" TIG;
-NET "rst" TIG;
-
-# Locate DCM/BUFG - Tools can probably figure them out automatically
-#                   but just LOC them down to be safe
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
-#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
-
-# GOOD
-INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
-AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
-AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
-
-////////////////////////////////////////////////////////////////////////////
-// Misc Board Signals
-////////////////////////////////////////////////////////////////////////////
-
-NET sys_error<0> LOC = V6;
-NET sys_error<1> LOC = L24;
-NET sys_error<*> IOSTANDARD = LVCMOS33;
-NET sys_error<*> DRIVE = 2;
-NET sys_error<*> TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// RS-232
-////////////////////////////////////////////////////////////////////////////
-NET sys_rx LOC = W2;
-NET sys_rx IOSTANDARD = LVCMOS33;
-NET sys_rx TIG;
-NET "sys_tx" LOC = "W1";
-NET sys_tx IOSTANDARD = LVCMOS33;
-NET "sys_tx" TIG;
-
-////////////////////////////////////////////////////////////////////////////
-// Buttons, LEDs, and DIP Switches
-////////////////////////////////////////////////////////////////////////////
-# GPLED 0-3
-NET "sys_led<0>" LOC = "G5"; #GPLED0
-NET "sys_led<1>" LOC = "G6"; #GPLED1
-NET "sys_led<2>" LOC = "A11"; #GPLED2
-NET "sys_led<3>" LOC = "A12"; #GPLED3
-# North-East-South-West-Center LEDs
-NET "sys_led<4>" LOC = "F9"; # W LED
-NET "sys_led<5>" LOC = "E2"; # N LED
-NET "sys_led<6>" LOC = "E10"; # E LED
-NET "sys_led<7>" LOC = "A5"; # S LED
-NET "sys_led<8>" LOC = "C6"; # C LED
-NET "sys_led<*>" TIG;
-NET "sys_led<*>" SLEW = SLOW;
-NET "sys_led<*>" DRIVE = 2;
-#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
-# North-East-South-West-Center Buttons
-NET "sys_btn<0>" LOC = "E9"; # W Button
-NET "sys_btn<1>" LOC = "E7"; # N Button
-NET "sys_btn<2>" LOC = "F10"; # E Button
-NET "sys_btn<3>" LOC = "A6"; # S Button
-NET "sys_btn<4>" LOC = "B6"; # C Button
-NET "sys_btn<*>" TIG;
-NET "sys_btn<*>" PULLDOWN;
-#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
-# Dip Switches 1-8
-NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
-NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
-NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
-NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
-NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
-NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
-NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
-NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
-NET "sys_dip<*>" PULLDOWN;
-NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
-NET "sys_dip<*>" TIG;
-////////////////////////////////////////////////////////////////////////////
-// LCD
-////////////////////////////////////////////////////////////////////////////
-NET sys_lcd_e LOC = AE13; # LCD_E
-NET sys_lcd_e IOSTANDARD = LVCMOS33;
-NET sys_lcd_e SLEW = SLOW;
-NET sys_lcd_e DRIVE = 2;
-NET sys_lcd_e TIG;
-NET sys_lcd_rs LOC = AC17; # LCD_RS
-NET sys_lcd_rs IOSTANDARD = LVCMOS33;
-NET sys_lcd_rs SLEW = SLOW;
-NET sys_lcd_rs DRIVE = 2;
-NET sys_lcd_rs TIG;
-NET sys_lcd_rw LOC = AB17; # LCD_RW
-NET sys_lcd_rw IOSTANDARD = LVCMOS33;
-NET sys_lcd_rw SLEW = SLOW;
-NET sys_lcd_rw DRIVE = 2;
-NET sys_lcd_rw TIG;
-NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
-NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
-NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
-NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
-NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
-NET sys_lcd_d<*> SLEW = SLOW;
-NET sys_lcd_d<*> DRIVE = 2;
-NET sys_lcd_d<*> PULLDOWN;
-NET sys_lcd_d<*> TIG;
-
-#------------------------------------------------------------------------------
-# IO Pad Location Constraints / Properties for DDR Controllers
-#------------------------------------------------------------------------------
-
-NET sys_sdr_a_q<0>  	LOC = C26; # DDR_A0
-NET sys_sdr_a_q<1>  	LOC = E17; # DDR_A1
-NET sys_sdr_a_q<2>  	LOC = D18; # DDR_A2
-NET sys_sdr_a_q<3>  	LOC = C19; # DDR_A3
-NET sys_sdr_a_q<4>  	LOC = F17; # DDR_A4
-NET sys_sdr_a_q<5>  	LOC = B18; # DDR_A5
-NET sys_sdr_a_q<6>  	LOC = B20; # DDR_A6
-NET sys_sdr_a_q<7>  	LOC = C20; # DDR_A7
-NET sys_sdr_a_q<8>  	LOC = D20; # DDR_A8
-NET sys_sdr_a_q<9>  	LOC = C21; # DDR_A9
-NET sys_sdr_a_q<10> 	LOC = A18; # DDR_A10
-NET sys_sdr_a_q<11> 	LOC = B21; # DDR_A11
-NET sys_sdr_a_q<12> 	LOC = A24; # DDR_A12
-NET sys_sdr_ba_q<0>  	LOC = B12; # DDR_BA0
-NET sys_sdr_ba_q<1>  	LOC = A16; # DDR_BA1
-NET sys_sdr_cas_qn		LOC = F23; # DDR_CAS_N
-NET sys_sdr_cke_q		LOC = G22; # DDR_CKE
-NET sys_sdr_cs_qn		LOC = G21; # DDR_CS_N
-NET sys_sdr_ras_qn		LOC = F24; # DDR_RAS_N
-NET sys_sdr_we_qn		LOC = A23; # DDR_WE_N
-
-NET sys_sdr_clk_p		LOC = A10; # DDR_CK1_P
-NET sys_sdr_clk_fb	LOC = B13; # DDR_CK1_P (FEEDBACK)
-NET sys_sdr_clk_n		LOC = B10; # DDR_CK1_N
-
-NET sys_sdr_dm_q<0>  	LOC = G19; # DDR_DM0
-NET sys_sdr_dm_q<1>  	LOC = G24; # DDR_DM1
-NET sys_sdr_dm_q<2>  	LOC = G20; # DDR_DM2
-NET sys_sdr_dm_q<3>  	LOC = C22; # DDR_DM3
-
-NET sys_sdr_dqs_q<0> 	LOC = D25; # DDR_DQS0
-NET sys_sdr_dqs_q<1> 	LOC = G18; # DDR_DQS1
-NET sys_sdr_dqs_q<2> 	LOC = G17; # DDR_DQS2
-NET sys_sdr_dqs_q<3> 	LOC = D26; # DDR_DQS3
-
-NET sys_sdr_data<0> 	LOC = H20; # DDR_D0
-NET sys_sdr_data<1> 	LOC = E23; # DDR_D1
-NET sys_sdr_data<2> 	LOC = H26; # DDR_D2
-NET sys_sdr_data<3> 	LOC = H22; # DDR_D3
-NET sys_sdr_data<4> 	LOC = E25; # DDR_D4
-NET sys_sdr_data<5> 	LOC = E26; # DDR_D5
-NET sys_sdr_data<6> 	LOC = F26; # DDR_D6
-NET sys_sdr_data<7> 	LOC = E24; # DDR_D7
-NET sys_sdr_data<8> 	LOC = E20; # DDR_D8
-NET sys_sdr_data<9> 	LOC = A22; # DDR_D9
-NET sys_sdr_data<10>	LOC = C23; # DDR_D10
-NET sys_sdr_data<11>	LOC = C24; # DDR_D11
-NET sys_sdr_data<12>	LOC = A20; # DDR_D12
-NET sys_sdr_data<13>	LOC = A21; # DDR_D13
-NET sys_sdr_data<14>	LOC = D24; # DDR_D14
-NET sys_sdr_data<15>	LOC = E18; # DDR_D15
-NET sys_sdr_data<16>	LOC = F18; # DDR_D16
-NET sys_sdr_data<17>	LOC = A19; # DDR_D17
-NET sys_sdr_data<18>	LOC = F19; # DDR_D18
-NET sys_sdr_data<19>	LOC = B23; # DDR_D19
-NET sys_sdr_data<20>	LOC = E21; # DDR_D20
-NET sys_sdr_data<21>	LOC = D22; # DDR_D21
-NET sys_sdr_data<22>	LOC = D23; # DDR_D22
-NET sys_sdr_data<23>	LOC = B24; # DDR_D23
-NET sys_sdr_data<24>	LOC = E22; # DDR_D24
-NET sys_sdr_data<25>	LOC = F20; # DDR_D25
-NET sys_sdr_data<26>	LOC = H23; # DDR_D26
-NET sys_sdr_data<27>	LOC = G25; # DDR_D27
-NET sys_sdr_data<28>	LOC = G26; # DDR_D28
-NET sys_sdr_data<29>	LOC = H25; # DDR_D29
-NET sys_sdr_data<30>	LOC = H24; # DDR_D30
-NET sys_sdr_data<31>	LOC = H21; # DDR_D31
-
-NET sys_sdr_a_q<*>  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_a_q<*>	FAST; 
-
-NET sys_sdr_ba_q<*> 	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ba_q<*>	FAST; 
-
-NET sys_sdr_cas_qn  	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cke_q   	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cke_q		FAST; 
-
-NET sys_sdr_clk_p		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_p		FAST; 
-NET sys_sdr_clk_fb	IOSTANDARD = LVCMOS25;
-NET sys_sdr_clk_fb	IOBDELAY = NONE; 
-NET sys_sdr_clk_n		IOSTANDARD = SSTL2_I;
-NET sys_sdr_clk_n		FAST; 
-
-NET sys_sdr_cas_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_cas_qn	FAST; 
-
-NET sys_sdr_cs_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_cs_qn		FAST; 
-
-NET sys_sdr_ras_qn	IOSTANDARD = SSTL2_I;
-NET sys_sdr_ras_qn	FAST; 
-
-NET sys_sdr_we_qn		IOSTANDARD = SSTL2_I;
-NET sys_sdr_we_qn		FAST; 
-
-NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
-NET sys_sdr_dqs_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dqs_q<*>	FAST; 
-
-NET sys_sdr_dm_q<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_dm_q<*>	IOBDELAY = NONE; 
-NET sys_sdr_dm_q<*>	FAST; 
-
-NET sys_sdr_data<*>  IOSTANDARD = SSTL2_II;
-NET sys_sdr_data<*>	IOBDELAY = NONE; 
-NET sys_sdr_data<*>	FAST; 
-
-#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
-
-NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
-NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
-
-# Timing Constraint for DDR Feedback Clock
-NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
-
-# USB
-NET sys_usb_a<0>   LOC        = Y10;
-NET sys_usb_a<1>   LOC        = AA10;
-NET sys_usb_a<*>   IOSTANDARD = LVCMOS33;
-
-NET sys_usb_d<0>   LOC        = AB7;
-NET sys_usb_d<1>   LOC        = AC9;
-NET sys_usb_d<2>   LOC        = AB9;
-NET sys_usb_d<3>   LOC        = AE6;
-NET sys_usb_d<4>   LOC        = AD6;
-NET sys_usb_d<5>   LOC        = AF9;
-NET sys_usb_d<6>   LOC        = AE9;
-NET sys_usb_d<7>   LOC        = AD8;
-NET sys_usb_d<8>   LOC        = AC8;
-NET sys_usb_d<9>   LOC        = AF4;
-NET sys_usb_d<10>  LOC        = AE4;
-NET sys_usb_d<11>  LOC        = AD3;
-NET sys_usb_d<12>  LOC        = AC3;
-NET sys_usb_d<13>  LOC        = AF6;
-NET sys_usb_d<14>  LOC        = AF5;
-NET sys_usb_d<15>  LOC        = AA7;
-NET sys_usb_d<*>   IOSTANDARD = LVCMOS33;
-NET sys_usb_d<*>   SLEW       = FAST;
-NET sys_usb_d<*>   DRIVE      = 8;
-NET sys_usb_d<*>   PULLDOWN;
-
-NET sys_usb_rdn    LOC        = AA8;
-NET sys_usb_rdn    IOSTANDARD = LVCMOS33;
-NET sys_usb_rdn    SLEW       = FAST;
-NET sys_usb_rdn    DRIVE      = 8;
-
-NET sys_usb_wrn    LOC        = Y8;
-NET sys_usb_wrn    IOSTANDARD = LVCMOS33;
-NET sys_usb_wrn    SLEW       = FAST;
-NET sys_usb_wrn    DRIVE      = 8;
-
-NET sys_usb_csn    LOC        = AF10;
-NET sys_usb_csn    IOSTANDARD = LVCMOS33;
-NET sys_usb_csn    SLEW       = FAST;
-NET sys_usb_csn    DRIVE      = 8;
-
-NET sys_usb_rstn   LOC        = A7;
-NET sys_usb_rstn   IOSTANDARD = LVCMOS25;
-NET sys_usb_rstn   TIG;
-
-NET sys_usb_int    LOC        = V5;
-NET sys_usb_int    IOSTANDARD = LVCMOS33;
-NET sys_usb_int    PULLDOWN;
-NET sys_usb_int    TIG;
-
-# FLASH
-NET sys_flash_a<24> LOC = T21;
-NET sys_flash_a<23> LOC = U20;
-NET sys_flash_a<22> LOC = T19;
-NET sys_flash_a<21> LOC = AC5;
-NET sys_flash_a<20> LOC = AB5;
-NET sys_flash_a<19> LOC = AC4;
-NET sys_flash_a<18> LOC = AB4;
-NET sys_flash_a<17> LOC = AB3;
-NET sys_flash_a<16> LOC = AA4;
-NET sys_flash_a<15> LOC = AA3;
-NET sys_flash_a<14> LOC = W5;
-NET sys_flash_a<13> LOC = W6;
-NET sys_flash_a<12> LOC = W3;
-NET sys_flash_a<11> LOC = AF3;
-NET sys_flash_a<10>  LOC = AE3;
-NET sys_flash_a<9>  LOC = AD2;
-NET sys_flash_a<8>  LOC = AD1;
-NET sys_flash_a<7>  LOC = AC2;
-NET sys_flash_a<6>  LOC = AC1;
-NET sys_flash_a<5>  LOC = AB2;
-NET sys_flash_a<4>  LOC = AB1;
-NET sys_flash_a<3>  LOC = AA1;
-NET sys_flash_a<2>  LOC = Y2;
-NET sys_flash_a<1>  LOC = Y1;
-NET sys_flash_a<0>  LOC = T20;
-
-NET sys_flash_d<31> LOC = F14;
-NET sys_flash_d<30> LOC = F13;
-NET sys_flash_d<29> LOC = F12;
-NET sys_flash_d<28> LOC = F11;
-NET sys_flash_d<27> LOC = F16;
-NET sys_flash_d<26> LOC = F15;
-NET sys_flash_d<25> LOC = D14;
-NET sys_flash_d<24> LOC = D13;
-NET sys_flash_d<23> LOC = D15;
-NET sys_flash_d<22> LOC = E14;
-NET sys_flash_d<21> LOC = C11;
-NET sys_flash_d<20> LOC = D11;
-NET sys_flash_d<19> LOC = D16;
-NET sys_flash_d<18> LOC = C16;
-NET sys_flash_d<17> LOC = E13;
-NET sys_flash_d<16> LOC = D12;
-NET sys_flash_d<15> LOC = AA14;
-NET sys_flash_d<14> LOC = AB14;
-NET sys_flash_d<13> LOC = AC12;
-NET sys_flash_d<12> LOC = AC11;
-NET sys_flash_d<11> LOC = AA16;
-NET sys_flash_d<10> LOC = AA15;
-NET sys_flash_d<9>  LOC = AB13;
-NET sys_flash_d<8>  LOC = AA13;
-NET sys_flash_d<7>  LOC = AC14;
-NET sys_flash_d<6>  LOC = AD14;
-NET sys_flash_d<5>  LOC = AA12;
-NET sys_flash_d<4>  LOC = AA11;
-NET sys_flash_d<3>  LOC = AC16;
-NET sys_flash_d<2>  LOC = AC15;
-NET sys_flash_d<1>  LOC = AC13;
-NET sys_flash_d<0>  LOC = AD13;
-NET sys_flash_rdn     LOC = AC6;
-NET sys_flash_wrn     LOC = AB6;
-NET sys_flash_ce      LOC = W7;
-NET sys_flash_rstn    LOC = AD10;
-NET sys_flash_byten   LOC = N22;
-
-NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
-NET sys_flash_a<*>  SLEW = FAST;
-NET sys_flash_a<*>  DRIVE = 8;
-
-NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
-NET sys_flash_d<*> DRIVE = 12;
-NET sys_flash_d<*> SLEW = FAST;
-NET sys_flash_d<*> PULLDOWN;
-
-NET sys_flash_rdn    IOSTANDARD = LVDCI_33;
-NET sys_flash_rdn SLEW = FAST;
-NET sys_flash_rdn DRIVE = 8;
-
-NET sys_flash_wrn    IOSTANDARD = LVDCI_33;
-NET sys_flash_wrn SLEW = FAST;
-NET sys_flash_wrn DRIVE = 8;
-
-NET sys_flash_ce           IOSTANDARD = LVDCI_33;
-NET sys_flash_ce SLEW = FAST;
-NET sys_flash_ce DRIVE = 8;
-
-NET sys_flash_rstn    IOSTANDARD = LVCMOS33;
-NET sys_flash_rstn    DRIVE = 8;
-NET sys_flash_rstn    SLEW = FAST;
-NET sys_flash_rstn    TIG;
-
-NET sys_flash_byten    IOSTANDARD = LVCMOS33;
-NET sys_flash_byten    DRIVE = 8;
-NET sys_flash_byten    SLEW = FAST;
-NET sys_flash_byten    TIG;
-
-# VGA
-NET sys_vga_blue<0> LOC = M21; # VGA_B0
-NET sys_vga_blue<1> LOC = M26; # VGA_B1
-NET sys_vga_blue<2> LOC = L26; # VGA_B2
-NET sys_vga_blue<3> LOC = C5;  # VGA_B3
-NET sys_vga_blue<4> LOC = C7;  # VGA_B4
-NET sys_vga_blue<5> LOC = B7;  # VGA_B5
-NET sys_vga_blue<6> LOC = G8;  # VGA_B6
-NET sys_vga_blue<7> LOC = F8;  # VGA_B7
-NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_blue<*> SLEW = FAST;
-NET sys_vga_blue<*> DRIVE = 8;
-
-NET sys_vga_clk  LOC = AF8;
-NET sys_vga_clk  IOSTANDARD = LVDCI_33;
-NET sys_vga_clk  SLEW = FAST;
-NET sys_vga_clk  DRIVE = 8;
-
-NET sys_vga_green<0> LOC = M22; # VGA_G0
-NET sys_vga_green<1> LOC = M23; # VGA_G1
-NET sys_vga_green<2> LOC = M20; # VGA_G2
-NET sys_vga_green<3> LOC = E4;  # VGA_G3
-NET sys_vga_green<4> LOC = D3;  # VGA_G4
-NET sys_vga_green<5> LOC = H7;  # VGA_G5
-NET sys_vga_green<6> LOC = H8;  # VGA_G6
-NET sys_vga_green<7> LOC = C1;  # VGA_G7
-NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_green<*> SLEW = FAST;
-NET sys_vga_green<*> DRIVE = 8;
-
-NET sys_vga_hsync LOC = C10;
-NET sys_vga_hsync SLEW = FAST;
-NET sys_vga_hsync DRIVE = 8;
-#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_red<0> LOC = N23; #VGA_R0
-NET sys_vga_red<1> LOC = N24; #VGA_R1
-NET sys_vga_red<2> LOC = N25; #VGA_R2
-NET sys_vga_red<3> LOC = C2;  #VGA_R3
-NET sys_vga_red<4> LOC = G7;  #VGA_R4
-NET sys_vga_red<5> LOC = F7;  #VGA_R5
-NET sys_vga_red<6> LOC = E5;  #VGA_R6
-NET sys_vga_red<7> LOC = E6;  #VGA_R7
-NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
-NET sys_vga_red<*> SLEW = FAST;
-NET sys_vga_red<*> DRIVE = 8;
-
-NET sys_vga_vsync LOC = A8;
-NET sys_vga_vsync SLEW = FAST;
-NET sys_vga_vsync DRIVE = 8;
-#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
-
-NET sys_vga_blank_n LOC = M24;
-NET sys_vga_blank_n SLEW = FAST;
-NET sys_vga_blank_n DRIVE = 8;
-NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
-
-NET sys_vga_sync_n LOC = L23;
-NET sys_vga_sync_n SLEW = FAST;
-NET sys_vga_sync_n DRIVE = 8;
-NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo
deleted file mode 100644
index 6535215..0000000
--- a/projects/mips_sys/sim/tb_mips_sys.fdo
+++ /dev/null
@@ -1,118 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-# Configs
-vcom -explicit  -93 "../src/sdram_config_sim.vhd"
-
-# Packages
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
-
-# RAMs
-vcom -explicit  -93 "../../../lib/rams/dpram_1w1r2c_ro_sim.vhd"
-vcom -explicit  -93 "../../../lib/rams/dpram_2w2r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../../lib/rams/dpram_1w1r2c_ra_sim.vhd"
-#vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
-
-# FIFOS
-vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
-
-# CPU
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
-
-# VGA
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-
-# UART
-vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
-
-# PS2
-vcom -explicit  -93 "../../../lib/ps2_port/src/debounce.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_core.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
-
-# GPIO
-vcom -explicit  -93 "../../../lib/misc/gpio_wb.vhd"
-
-# LCD
-vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
-
-# Flash and USB
-vcom -explicit  -93 "../../../lib/misc/async_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
-vcom -explicit  -93 "../../../lib/misc/flash_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs_sim.vhd"
-
-# Sync SRAM
-vcom -explicit  -93 "../../../lib/SSRAM/src/package_utility.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
-
-# SDRAM
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-
-# AC-97
-vcom -explicit  -93 "../../../lib/misc/singleshot.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
-
-# Ethernet MAC
-vcom -explicit  -93 "../../../lib/emac/src/emac_types.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/piso.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/sipo.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/crc32.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_rx.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_tx.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_top_jb.vhd"
-
-# Clock Generator
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-
-# Top and TB
-vcom -explicit  -93 "../src/mips_sys_sim.vhd"
-vcom -explicit  -93 "../src/tb_mips_sys.vhd"
-
-vsim -t 1ps   -lib work tb_mips_sys
-do {tb_mips_sys.wdo}
-view wave
-view structure
-view signals
-run 10 ms
diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo
deleted file mode 100644
index e79c1ce..0000000
--- a/projects/mips_sys/sim/tb_mips_sys.wdo
+++ /dev/null
@@ -1,457 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
-add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
-add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
-add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
-add wave -noupdate -format Literal /tb_mips_sys/dip
-add wave -noupdate -format Literal /tb_mips_sys/btn
-add wave -noupdate -format Literal /tb_mips_sys/led
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
-add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
-add wave -noupdate -format Logic /tb_mips_sys/sys_rx
-add wave -noupdate -format Logic /tb_mips_sys/sys_tx
-add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
-add wave -noupdate -format Logic /tb_mips_sys/refresh
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_error
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -divider {Clock Gen}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
-add wave -noupdate -divider Arbiter
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
-add wave -noupdate -divider {Ethernet MAC}
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
-add wave -noupdate -divider AC97
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
-add wave -noupdate -format Logic /tb_mips_sys/ac_synced
-add wave -noupdate -divider {CPU Master}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
-add wave -noupdate -divider {VGA Master}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
-add wave -noupdate -divider BUI
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/read_cycle
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/ack
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/dat
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bout_rdy
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle
-add wave -noupdate -divider VGA-Slave
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/rst_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/clk_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/int_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/cyc_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/srdy_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/mrdy_i
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/sel_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/we_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/stb_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/addr_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/sdat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/ack_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_addr_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_dimx_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_const_color
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_reg_func
-add wave -noupdate -divider <NULL>
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_reset
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_const_color_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_request_set
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_finish_strobe
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_ack
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_complete_int_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_ack
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty_int_en
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_din
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_re
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_empty
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_full
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_bsy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_avail
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_addr_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_0
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_src_1
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_dimx_dst
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_nx
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_ny
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_cc
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/blit_cmd_func
-add wave -noupdate -divider USB
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
-add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
-add wave -noupdate -divider Flash
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
-add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
-add wave -noupdate -divider {Sync SRAM}
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
-add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
-add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
-add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
-add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
-add wave -noupdate -divider {MIPS TOP}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
-add wave -noupdate -divider {CPU DMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -divider {CPU IMEM}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -divider {User ROM}
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
-add wave -noupdate -divider I-Cache
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/rst_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/clk_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ack_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/dat_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/stb_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cyc_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/ctrl
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_en
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_busy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/s
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/sn
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_match_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_index_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_reg_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cache_entry_out_inv
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/data_ram_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/tag_ram_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_count_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rst
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/flush_count_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/request_count_rdy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_all
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_ack
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/invalidate_req
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_cache_index
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/req_word_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_cache_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/fill_word_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_cache_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_icache/cpu_word_index
-add wave -noupdate -divider D-Cache
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/rst_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/clk_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ack_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/srdy_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/mrdy_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/dat_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/stb_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cyc_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/ctrl
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_dout
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_busy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/s
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/sn
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_hit_inv
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_match_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_index_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_reg_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cache_entry_out_inv
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_data_reg
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_be_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_we2
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_din
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/tag_ram_we
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_count_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rst
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/flush_count_rdy
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/request_count_rdy
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_all
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_ack
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/invalidate_req
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/hit_cache_index
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_hit_we
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/instant_raw
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_cache_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/req_word_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_cache_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/fill_word_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_tag
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_cache_index
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_biu/inst_dcache/cpu_word_index
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {9216870000 ps} 0} {{Cursor 100} {98503600 ps} 0} {{Cursor 3} {15592084279 ps} 0}
-configure wave -namecolwidth 187
-configure wave -valuecolwidth 64
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {15591849308 ps} {15592330693 ps}
diff --git a/projects/mips_sys/sim/tb_mips_sys_emac.fdo b/projects/mips_sys/sim/tb_mips_sys_emac.fdo
deleted file mode 100644
index a55a471..0000000
--- a/projects/mips_sys/sim/tb_mips_sys_emac.fdo
+++ /dev/null
@@ -1,116 +0,0 @@
-## NOTE:  Do not edit this file.
-##
-vlib work
-# Configs
-vcom -explicit  -93 "../src/sdram_config_sim.vhd"
-
-# Packages
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
-
-# RAMs
-vcom -explicit  -93 "../../../lib/misc/dpram_2w2r.vhd"
-vcom -explicit  -93 "../../../lib/misc/dpram_1w1r.vhd"
-
-# FIFOS
-vcom -explicit  -93 "../../../lib/FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/FIFO/src/fifo_async.vhd"
-
-# CPU
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
-vcom -explicit  -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
-vcom -explicit  -93 "../src/bootloader.ROM.vhd"
-vcom -explicit  -93 "../../../lib/misc/rom_wb.vhd"
-
-# VGA
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
-vcom -explicit  -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
-
-# UART
-vcom -explicit  -93 "../../../lib/uart/bbfifo_16x8.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/kcuart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_rx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_tx.vhd"
-vcom -explicit  -93 "../../../lib/uart/uart_wb.vhd"
-
-# PS2
-vcom -explicit  -93 "../../../lib/ps2_port/src/debounce.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_core.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_phy_virtex.vhd"
-vcom -explicit  -93 "../../../lib/ps2_port/src/ps2_wb.vhd"
-
-# GPIO
-vcom -explicit  -93 "../../../lib/misc/gpio_wb.vhd"
-
-# LCD
-vcom -explicit  -93 "../../../lib/misc/lcd_port.vhd"
-
-# Flash and USB
-vcom -explicit  -93 "../../../lib/misc/async_types.vhd"
-vcom -explicit  -93 "../../../lib/misc/async_port_wb.vhd"
-vcom -explicit  -93 "../../../lib/misc/flash_port_wb.vhd"
-vcom -explicit  -93 "../src/async_defs_sim.vhd"
-
-# Sync SRAM
-vcom -explicit  -93 "../../../lib/SSRAM/src/package_utility.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
-vcom -explicit  -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
-
-# SDRAM
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
-
-# AC-97
-vcom -explicit  -93 "../../../lib/misc/singleshot.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
-vcom -explicit  -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
-
-# Ethernet MAC
-vcom -explicit  -93 "../../../lib/emac/src/emac_types.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/piso.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/sipo.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/crc32.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_rx.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_tx.vhd"
-vcom -explicit  -93 "../../../lib/emac/src/emac_top_jb.vhd"
-
-# Clock Generator
-vcom -explicit  -93 "../src/clockgen_virtex4.vhd"
-
-# Top and TB
-vcom -explicit  -93 "../src/mips_sys_sim.vhd"
-vcom -explicit  -93 "../src/tb_mips_sys.vhd"
-
-vsim -t 1ps   -lib work tb_mips_sys
-do {tb_mips_sys_emac.wdo}
-view wave
-view structure
-view signals
-run 40 ms
diff --git a/projects/mips_sys/sim/tb_mips_sys_emac.wdo b/projects/mips_sys/sim/tb_mips_sys_emac.wdo
deleted file mode 100644
index 3a549c2..0000000
--- a/projects/mips_sys/sim/tb_mips_sys_emac.wdo
+++ /dev/null
@@ -1,185 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider UUT
-add wave -noupdate -format Logic /tb_mips_sys/uut/rst_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/nmi
-add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in
-add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
-add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
-add wave -noupdate -format Literal /tb_mips_sys/dip
-add wave -noupdate -format Literal /tb_mips_sys/btn
-add wave -noupdate -format Literal /tb_mips_sys/led
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rstn
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdc
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_mdio
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_int
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_dv
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_rx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_rx
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_en
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_tx_er
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_phy_tx
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_gtx_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_crs
-add wave -noupdate -format Logic /tb_mips_sys/sys_phy_col
-add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_clk
-add wave -noupdate -format Logic /tb_mips_sys/sys_ps2_data
-add wave -noupdate -format Logic /tb_mips_sys/sys_rx
-add wave -noupdate -format Logic /tb_mips_sys/sys_tx
-add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
-add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
-add wave -noupdate -format Logic /tb_mips_sys/refresh
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
-add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
-add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
-add wave -noupdate -format Literal /tb_mips_sys/sys_error
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -divider {Clock Gen}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/clk_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_clk_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk_fb_in
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk0_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_clk270_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk0_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_clk270_out
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_rst_out
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_cnt
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe0
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_clockgen/reset_pipe1
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/vga_fx_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sys_fx_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr0_lock
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/sdr1_lock
-add wave -noupdate -divider Arbiter
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
-add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
-add wave -noupdate -divider {Ethernet MAC}
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/eth_tx_reg
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/clk_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rst_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/int_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/cyc_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/stb_i
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_emac_jb/sel_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/we_i
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/ack_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/srdy_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/mrdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/addr_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/dat_o
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/rx_int_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/tx_int_en
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_rx
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/irq_tx
-add wave -noupdate -divider {EMAC TX}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/din
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_tx/ctrl_out
-add wave -noupdate -divider {EMAC RX}
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/dout
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_emac_jb/inst_emac_rx/ctrl_out
-add wave -noupdate -divider {CPU Master}
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
-add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
-add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
-add wave -noupdate -divider Flash
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
-add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
-add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
-add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
-add wave -noupdate -divider {MIPS TOP}
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_addr
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_din
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/dmem_dout
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
-add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o
-add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
-add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
-add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/cpu_clk_out
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {2312967085 ps} 0} {{Cursor 100} {4871595869 ps} 0} {{Cursor 3} {4495154370 ps} 0} {{Cursor 7} {6077658830 ps} 0}
-configure wave -namecolwidth 187
-configure wave -valuecolwidth 64
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {41227735500 ps}
diff --git a/projects/mips_sys/src/.directory_history b/projects/mips_sys/src/.directory_history
deleted file mode 100644
index 2f56f3d..0000000
--- a/projects/mips_sys/src/.directory_history
+++ /dev/null
@@ -1,4 +0,0 @@
-VHDL/projects/mips_sys/src/async_defs.vhd
-
-VHDL/projects/mips_sys/src/sys_types.vhd
-VHDL/projects/mips_sys/src/async_defs.vhd
diff --git a/projects/mips_sys/src/async_defs_sim.vhd b/projects/mips_sys/src/async_defs_sim.vhd
deleted file mode 100644
index 8f58939..0000000
--- a/projects/mips_sys/src/async_defs_sim.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file: 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.async_types.all;
-
-package async_defs is
-
-	constant ts_flash : async_timespec_t :=
-	(
-		T_leadin			=> 10.0,
-		T_pulse_rd			=> 120.0,
-		T_pulse_wr			=> 70.0,
-		T_leadout			=> 10.0,
-		T_release			=> 40.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 30.0,
-		can_page_rd			=> true,
-		nbits_page_rd		=> 4,
-		pol_cs				=> '1',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-	constant ts_usb : async_timespec_t :=
-	(
-		T_leadin			=> 10.0,
-		T_pulse_rd			=> 60.0,
-		T_pulse_wr			=> 60.0,
-		T_leadout			=> 10.0,
-		T_release			=> 80.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 00.0,
-		can_page_rd			=> false,
-		nbits_page_rd		=> 0,
-		pol_cs				=> '0',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-	----------------------------------------------------------------------------------------------
-	
-end async_defs;
diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd
deleted file mode 100644
index 1e0f12d..0000000
--- a/projects/mips_sys/src/bootloader.ROM.vhd
+++ /dev/null
@@ -1,2082 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	constant word_array : word_array_t :=
-	(
-
-		X"3C1D8000", -- 00000000
-		X"27BDEFF0", -- 00000004
-		X"3C1A1040", -- 00000008
-		X"375A000C", -- 0000000C
-		X"409A6000", -- 00000010
-		X"241A0000", -- 00000014
-		X"409A6800", -- 00000018
-		X"401A7800", -- 0000001C
-		X"00000000", -- 00000020
-		X"409AF800", -- 00000024
-		X"42000020", -- 00000028
-		X"42000022", -- 0000002C
-		X"3C1ABFC0", -- 00000030
-		X"275A005C", -- 00000034
-		X"0340F809", -- 00000038
-		X"00000000", -- 0000003C
-		X"3C1ABFC0", -- 00000040
-		X"275A114C", -- 00000044
-		X"0340F809", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"0BF00014", -- 00000054
-		X"00000000", -- 00000058
-		X"3C1AA001", -- 0000005C
-		X"275A0008", -- 00000060
-		X"241B000D", -- 00000064
-		X"AF5B0000", -- 00000068
-		X"03E00008", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BC000", -- 00000184
-		X"001AD082", -- 00000188
-		X"335A000F", -- 0000018C
-		X"035BD025", -- 00000190
-		X"3C1BA000", -- 00000194
-		X"277B0000", -- 00000198
-		X"AF7A0000", -- 0000019C
-		X"401A6800", -- 000001A0
-		X"00000000", -- 000001A4
-		X"001AD202", -- 000001A8
-		X"335A00FF", -- 000001AC
-		X"1740FFFB", -- 000001B0
-		X"00000000", -- 000001B4
-		X"401A7000", -- 000001B8
-		X"00000000", -- 000001BC
-		X"03400008", -- 000001C0
-		X"42000010", -- 000001C4
-		X"40026000", -- 000001C8
-		X"03E00008", -- 000001CC
-		X"00000000", -- 000001D0
-		X"40846000", -- 000001D4
-		X"03E00008", -- 000001D8
-		X"00000000", -- 000001DC
-		X"40026800", -- 000001E0
-		X"03E00008", -- 000001E4
-		X"00000000", -- 000001E8
-		X"40846800", -- 000001EC
-		X"03E00008", -- 000001F0
-		X"00000000", -- 000001F4
-		X"40027800", -- 000001F8
-		X"03E00008", -- 000001FC
-		X"00000000", -- 00000200
-		X"3C02A001", -- 00000204
-		X"34430004", -- 00000208
-		X"8C620000", -- 0000020C
-		X"00000000", -- 00000210
-		X"30420010", -- 00000214
-		X"1040FFFC", -- 00000218
-		X"3C02A001", -- 0000021C
-		X"8C420000", -- 00000220
-		X"00000000", -- 00000224
-		X"00021600", -- 00000228
-		X"03E00008", -- 0000022C
-		X"00021603", -- 00000230
-		X"00042600", -- 00000234
-		X"3C02A001", -- 00000238
-		X"00042603", -- 0000023C
-		X"34430004", -- 00000240
-		X"8C620000", -- 00000244
-		X"00000000", -- 00000248
-		X"30420002", -- 0000024C
-		X"1440FFFC", -- 00000250
-		X"3C02A001", -- 00000254
-		X"AC440000", -- 00000258
-		X"03E00008", -- 0000025C
-		X"00000000", -- 00000260
-		X"00042600", -- 00000264
-		X"00042603", -- 00000268
-		X"2402000A", -- 0000026C
-		X"1482000A", -- 00000270
-		X"3C02A001", -- 00000274
-		X"34430004", -- 00000278
-		X"8C620000", -- 0000027C
-		X"00000000", -- 00000280
-		X"30420002", -- 00000284
-		X"1440FFFC", -- 00000288
-		X"3C02A001", -- 0000028C
-		X"2403000D", -- 00000290
-		X"AC430000", -- 00000294
-		X"3C02A001", -- 00000298
-		X"34430004", -- 0000029C
-		X"8C620000", -- 000002A0
-		X"00000000", -- 000002A4
-		X"30420002", -- 000002A8
-		X"1440FFFC", -- 000002AC
-		X"3C02A001", -- 000002B0
-		X"AC440000", -- 000002B4
-		X"03E00008", -- 000002B8
-		X"00000000", -- 000002BC
-		X"3C02A001", -- 000002C0
-		X"34470004", -- 000002C4
-		X"00802821", -- 000002C8
-		X"2409000A", -- 000002CC
-		X"3C06A001", -- 000002D0
-		X"0BF000C6", -- 000002D4
-		X"2408000D", -- 000002D8
-		X"14690007", -- 000002DC
-		X"00000000", -- 000002E0
-		X"8CE20000", -- 000002E4
-		X"00000000", -- 000002E8
-		X"30420002", -- 000002EC
-		X"1440FFFC", -- 000002F0
-		X"00000000", -- 000002F4
-		X"ACC80000", -- 000002F8
-		X"8CE20000", -- 000002FC
-		X"00000000", -- 00000300
-		X"30420002", -- 00000304
-		X"1440FFFC", -- 00000308
-		X"00000000", -- 0000030C
-		X"ACC30000", -- 00000310
-		X"24A50001", -- 00000314
-		X"80A30000", -- 00000318
-		X"00000000", -- 0000031C
-		X"1460FFEE", -- 00000320
-		X"00A41023", -- 00000324
-		X"03E00008", -- 00000328
-		X"00000000", -- 0000032C
-		X"00042600", -- 00000330
-		X"3C02A001", -- 00000334
-		X"00042603", -- 00000338
-		X"344A0004", -- 0000033C
-		X"00003821", -- 00000340
-		X"3C09A001", -- 00000344
-		X"24080002", -- 00000348
-		X"308200FF", -- 0000034C
-		X"00022902", -- 00000350
-		X"00041100", -- 00000354
-		X"00022600", -- 00000358
-		X"2CA3000A", -- 0000035C
-		X"00042603", -- 00000360
-		X"14600002", -- 00000364
-		X"24A60030", -- 00000368
-		X"24A60037", -- 0000036C
-		X"8D420000", -- 00000370
-		X"00000000", -- 00000374
-		X"30420002", -- 00000378
-		X"1440FFFC", -- 0000037C
-		X"00061600", -- 00000380
-		X"00021603", -- 00000384
-		X"24E70001", -- 00000388
-		X"AD220000", -- 0000038C
-		X"14E8FFEF", -- 00000390
-		X"308200FF", -- 00000394
-		X"03E00008", -- 00000398
-		X"00000000", -- 0000039C
-		X"27BDFFE0", -- 000003A0
-		X"AFB20018", -- 000003A4
-		X"AFB10014", -- 000003A8
-		X"AFB00010", -- 000003AC
-		X"AFBF001C", -- 000003B0
-		X"00808821", -- 000003B4
-		X"00008021", -- 000003B8
-		X"24120004", -- 000003BC
-		X"00112603", -- 000003C0
-		X"0FF000CC", -- 000003C4
-		X"26100001", -- 000003C8
-		X"1612FFFC", -- 000003CC
-		X"00118A00", -- 000003D0
-		X"8FBF001C", -- 000003D4
-		X"8FB20018", -- 000003D8
-		X"8FB10014", -- 000003DC
-		X"8FB00010", -- 000003E0
-		X"03E00008", -- 000003E4
-		X"27BD0020", -- 000003E8
-		X"27BDFFC8", -- 000003EC
-		X"AFB60028", -- 000003F0
-		X"AFBF0034", -- 000003F4
-		X"AFBE0030", -- 000003F8
-		X"AFB7002C", -- 000003FC
-		X"AFB50024", -- 00000400
-		X"AFB40020", -- 00000404
-		X"AFB3001C", -- 00000408
-		X"AFB20018", -- 0000040C
-		X"AFB10014", -- 00000410
-		X"AFB00010", -- 00000414
-		X"00801021", -- 00000418
-		X"10A00002", -- 0000041C
-		X"00C0B021", -- 00000420
-		X"00002021", -- 00000424
-		X"00409821", -- 00000428
-		X"3C02A001", -- 0000042C
-		X"00E09021", -- 00000430
-		X"0080A821", -- 00000434
-		X"345E0004", -- 00000438
-		X"00E0A021", -- 0000043C
-		X"3C17A001", -- 00000440
-		X"0FF000E8", -- 00000444
-		X"02A02021", -- 00000448
-		X"3C04BFC0", -- 0000044C
-		X"0FF000B0", -- 00000450
-		X"24841698", -- 00000454
-		X"02608821", -- 00000458
-		X"0BF00128", -- 0000045C
-		X"00008021", -- 00000460
-		X"12400009", -- 00000464
-		X"00000000", -- 00000468
-		X"82240000", -- 0000046C
-		X"0FF000CC", -- 00000470
-		X"2652FFFF", -- 00000474
-		X"3C04BFC0", -- 00000478
-		X"0FF000B0", -- 0000047C
-		X"24841770", -- 00000480
-		X"0BF00128", -- 00000484
-		X"26310001", -- 00000488
-		X"3C04BFC0", -- 0000048C
-		X"0FF000B0", -- 00000490
-		X"2484169C", -- 00000494
-		X"0BF0012C", -- 00000498
-		X"3C04BFC0", -- 0000049C
-		X"0216102A", -- 000004A0
-		X"1440FFEF", -- 000004A4
-		X"26100001", -- 000004A8
-		X"3C04BFC0", -- 000004AC
-		X"0FF000B0", -- 000004B0
-		X"2484169C", -- 000004B4
-		X"02602821", -- 000004B8
-		X"0BF00155", -- 000004BC
-		X"00002021", -- 000004C0
-		X"1280001E", -- 000004C4
-		X"00000000", -- 000004C8
-		X"90A30000", -- 000004CC
-		X"00000000", -- 000004D0
-		X"2462FFE0", -- 000004D4
-		X"304200FF", -- 000004D8
-		X"2C420060", -- 000004DC
-		X"14400003", -- 000004E0
-		X"00031E00", -- 000004E4
-		X"2403002E", -- 000004E8
-		X"00031E00", -- 000004EC
-		X"00031E03", -- 000004F0
-		X"2402000A", -- 000004F4
-		X"14620007", -- 000004F8
-		X"00000000", -- 000004FC
-		X"8FC20000", -- 00000500
-		X"00000000", -- 00000504
-		X"30420002", -- 00000508
-		X"1440FFFC", -- 0000050C
-		X"2402000D", -- 00000510
-		X"AEE20000", -- 00000514
-		X"8FC20000", -- 00000518
-		X"00000000", -- 0000051C
-		X"30420002", -- 00000520
-		X"1440FFFC", -- 00000524
-		X"00000000", -- 00000528
-		X"AEE30000", -- 0000052C
-		X"2694FFFF", -- 00000530
-		X"24840001", -- 00000534
-		X"0BF00155", -- 00000538
-		X"24A50001", -- 0000053C
-		X"3C04BFC0", -- 00000540
-		X"0FF000B0", -- 00000544
-		X"24841770", -- 00000548
-		X"0BF00159", -- 0000054C
-		X"3C04BFC0", -- 00000550
-		X"0096102A", -- 00000554
-		X"1440FFDA", -- 00000558
-		X"00000000", -- 0000055C
-		X"3C04BFC0", -- 00000560
-		X"0FF000B0", -- 00000564
-		X"248416C4", -- 00000568
-		X"02B6A821", -- 0000056C
-		X"1640FFB4", -- 00000570
-		X"02769821", -- 00000574
-		X"8FBF0034", -- 00000578
-		X"8FBE0030", -- 0000057C
-		X"8FB7002C", -- 00000580
-		X"8FB60028", -- 00000584
-		X"8FB50024", -- 00000588
-		X"8FB40020", -- 0000058C
-		X"8FB3001C", -- 00000590
-		X"8FB20018", -- 00000594
-		X"8FB10014", -- 00000598
-		X"8FB00010", -- 0000059C
-		X"03E00008", -- 000005A0
-		X"27BD0038", -- 000005A4
-		X"00C03821", -- 000005A8
-		X"00A03021", -- 000005AC
-		X"0BF000FB", -- 000005B0
-		X"24050001", -- 000005B4
-		X"8C840000", -- 000005B8
-		X"3C020070", -- 000005BC
-		X"34420070", -- 000005C0
-		X"3C0300FF", -- 000005C4
-		X"AC820000", -- 000005C8
-		X"346300FF", -- 000005CC
-		X"8C820000", -- 000005D0
-		X"AC830000", -- 000005D4
-		X"03E00008", -- 000005D8
-		X"00000000", -- 000005DC
-		X"27BDFFF8", -- 000005E0
-		X"AC850000", -- 000005E4
-		X"24820008", -- 000005E8
-		X"0BF0017F", -- 000005EC
-		X"24830020", -- 000005F0
-		X"A0400000", -- 000005F4
-		X"24420001", -- 000005F8
-		X"1443FFFD", -- 000005FC
-		X"00000000", -- 00000600
-		X"24020001", -- 00000604
-		X"AC820004", -- 00000608
-		X"03E00008", -- 0000060C
-		X"27BD0008", -- 00000610
-		X"8C870000", -- 00000614
-		X"3C020098", -- 00000618
-		X"34420098", -- 0000061C
-		X"ACE20000", -- 00000620
-		X"3C0200FF", -- 00000624
-		X"344200FF", -- 00000628
-		X"ACE20000", -- 0000062C
-		X"3C020090", -- 00000630
-		X"34420090", -- 00000634
-		X"ACE20000", -- 00000638
-		X"00804021", -- 0000063C
-		X"94E4009C", -- 00000640
-		X"24030002", -- 00000644
-		X"24020020", -- 00000648
-		X"AD030008", -- 0000064C
-		X"AD03001C", -- 00000650
-		X"AD020018", -- 00000654
-		X"3084FFFF", -- 00000658
-		X"0BF0019D", -- 0000065C
-		X"00001821", -- 00000660
-		X"8D020008", -- 00000664
-		X"00000000", -- 00000668
-		X"00021040", -- 0000066C
-		X"AD020008", -- 00000670
-		X"0064102B", -- 00000674
-		X"1440FFFA", -- 00000678
-		X"24630001", -- 0000067C
-		X"94E200AC", -- 00000680
-		X"94E300A8", -- 00000684
-		X"3042FFFF", -- 00000688
-		X"8D04001C", -- 0000068C
-		X"3063FFFF", -- 00000690
-		X"00021200", -- 00000694
-		X"00432825", -- 00000698
-		X"AD040014", -- 0000069C
-		X"0BF001AE", -- 000006A0
-		X"00001821", -- 000006A4
-		X"8D020014", -- 000006A8
-		X"00000000", -- 000006AC
-		X"00021040", -- 000006B0
-		X"AD020014", -- 000006B4
-		X"0065102B", -- 000006B8
-		X"1440FFFA", -- 000006BC
-		X"24630001", -- 000006C0
-		X"94E300B8", -- 000006C4
-		X"94E600B4", -- 000006C8
-		X"94E200C0", -- 000006CC
-		X"94E400BC", -- 000006D0
-		X"8D05001C", -- 000006D4
-		X"3042FFFF", -- 000006D8
-		X"3084FFFF", -- 000006DC
-		X"00021200", -- 000006E0
-		X"00441025", -- 000006E4
-		X"00052A00", -- 000006E8
-		X"00A20018", -- 000006EC
-		X"3063FFFF", -- 000006F0
-		X"30C6FFFF", -- 000006F4
-		X"00031A00", -- 000006F8
-		X"00661825", -- 000006FC
-		X"24630001", -- 00000700
-		X"AD030010", -- 00000704
-		X"3C0300FF", -- 00000708
-		X"346300FF", -- 0000070C
-		X"00001021", -- 00000710
-		X"00002812", -- 00000714
-		X"AD05000C", -- 00000718
-		X"ACE30000", -- 0000071C
-		X"03E00008", -- 00000720
-		X"00000000", -- 00000724
-		X"8C820008", -- 00000728
-		X"8C860000", -- 0000072C
-		X"00021082", -- 00000730
-		X"00A2102B", -- 00000734
-		X"14400004", -- 00000738
-		X"3C030090", -- 0000073C
-		X"3C028010", -- 00000740
-		X"03E00008", -- 00000744
-		X"34420002", -- 00000748
-		X"8C820010", -- 0000074C
-		X"00000000", -- 00000750
-		X"2442FFFF", -- 00000754
-		X"00021400", -- 00000758
-		X"00A21024", -- 0000075C
-		X"24420002", -- 00000760
-		X"34630090", -- 00000764
-		X"00021080", -- 00000768
-		X"ACC30000", -- 0000076C
-		X"00C21021", -- 00000770
-		X"8C430000", -- 00000774
-		X"3C020001", -- 00000778
-		X"34420001", -- 0000077C
-		X"00621824", -- 00000780
-		X"3C0200FF", -- 00000784
-		X"344200FF", -- 00000788
-		X"ACC20000", -- 0000078C
-		X"03E00008", -- 00000790
-		X"0003102B", -- 00000794
-		X"8C820008", -- 00000798
-		X"00A01821", -- 0000079C
-		X"00021082", -- 000007A0
-		X"00A2102B", -- 000007A4
-		X"8C850000", -- 000007A8
-		X"14400003", -- 000007AC
-		X"3C028010", -- 000007B0
-		X"0BF0020C", -- 000007B4
-		X"34430002", -- 000007B8
-		X"8C820010", -- 000007BC
-		X"00000000", -- 000007C0
-		X"2442FFFF", -- 000007C4
-		X"00021400", -- 000007C8
-		X"00621024", -- 000007CC
-		X"00021080", -- 000007D0
-		X"00A22021", -- 000007D4
-		X"3C020020", -- 000007D8
-		X"34420020", -- 000007DC
-		X"AC820000", -- 000007E0
-		X"3C0200D0", -- 000007E4
-		X"344200D0", -- 000007E8
-		X"AC820000", -- 000007EC
-		X"3C020080", -- 000007F0
-		X"34430080", -- 000007F4
-		X"8C860000", -- 000007F8
-		X"00000000", -- 000007FC
-		X"00C31024", -- 00000800
-		X"1443FFFC", -- 00000804
-		X"3C02002A", -- 00000808
-		X"3442002A", -- 0000080C
-		X"00C21024", -- 00000810
-		X"10400003", -- 00000814
-		X"00001821", -- 00000818
-		X"3C029010", -- 0000081C
-		X"00C21825", -- 00000820
-		X"3C0200FF", -- 00000824
-		X"344200FF", -- 00000828
-		X"AC820000", -- 0000082C
-		X"03E00008", -- 00000830
-		X"00601021", -- 00000834
-		X"8C820008", -- 00000838
-		X"00A01821", -- 0000083C
-		X"00021082", -- 00000840
-		X"00A2102B", -- 00000844
-		X"8C850000", -- 00000848
-		X"14400003", -- 0000084C
-		X"3C028010", -- 00000850
-		X"0BF00234", -- 00000854
-		X"34430002", -- 00000858
-		X"8C820010", -- 0000085C
-		X"00000000", -- 00000860
-		X"2442FFFF", -- 00000864
-		X"00021400", -- 00000868
-		X"00621024", -- 0000086C
-		X"00021080", -- 00000870
-		X"00A22021", -- 00000874
-		X"3C020060", -- 00000878
-		X"34420060", -- 0000087C
-		X"AC820000", -- 00000880
-		X"3C020001", -- 00000884
-		X"34420001", -- 00000888
-		X"AC820000", -- 0000088C
-		X"3C020080", -- 00000890
-		X"34430080", -- 00000894
-		X"8C860000", -- 00000898
-		X"00000000", -- 0000089C
-		X"00C31024", -- 000008A0
-		X"1443FFFC", -- 000008A4
-		X"3C020038", -- 000008A8
-		X"34420038", -- 000008AC
-		X"00C21024", -- 000008B0
-		X"10400003", -- 000008B4
-		X"00001821", -- 000008B8
-		X"3C029010", -- 000008BC
-		X"00C21825", -- 000008C0
-		X"3C0200FF", -- 000008C4
-		X"344200FF", -- 000008C8
-		X"AC820000", -- 000008CC
-		X"03E00008", -- 000008D0
-		X"00601021", -- 000008D4
-		X"8C820008", -- 000008D8
-		X"00A01821", -- 000008DC
-		X"00021082", -- 000008E0
-		X"00A2102B", -- 000008E4
-		X"8C850000", -- 000008E8
-		X"14400003", -- 000008EC
-		X"3C028010", -- 000008F0
-		X"0BF0025C", -- 000008F4
-		X"34430002", -- 000008F8
-		X"8C820010", -- 000008FC
-		X"00000000", -- 00000900
-		X"2442FFFF", -- 00000904
-		X"00021400", -- 00000908
-		X"00621024", -- 0000090C
-		X"00021080", -- 00000910
-		X"00A22021", -- 00000914
-		X"3C020060", -- 00000918
-		X"34420060", -- 0000091C
-		X"AC820000", -- 00000920
-		X"3C0200D0", -- 00000924
-		X"344200D0", -- 00000928
-		X"AC820000", -- 0000092C
-		X"3C020080", -- 00000930
-		X"34430080", -- 00000934
-		X"8C860000", -- 00000938
-		X"00000000", -- 0000093C
-		X"00C31024", -- 00000940
-		X"1443FFFC", -- 00000944
-		X"3C020038", -- 00000948
-		X"34420038", -- 0000094C
-		X"00C21024", -- 00000950
-		X"10400003", -- 00000954
-		X"00001821", -- 00000958
-		X"3C029010", -- 0000095C
-		X"00C21825", -- 00000960
-		X"3C0200FF", -- 00000964
-		X"344200FF", -- 00000968
-		X"AC820000", -- 0000096C
-		X"03E00008", -- 00000970
-		X"00601021", -- 00000974
-		X"8C820008", -- 00000978
-		X"8C840000", -- 0000097C
-		X"00021082", -- 00000980
-		X"00A2102B", -- 00000984
-		X"14400003", -- 00000988
-		X"3C028010", -- 0000098C
-		X"0BF0027C", -- 00000990
-		X"34430002", -- 00000994
-		X"00051080", -- 00000998
-		X"00822021", -- 0000099C
-		X"3C020040", -- 000009A0
-		X"34420040", -- 000009A4
-		X"AC820000", -- 000009A8
-		X"3C020080", -- 000009AC
-		X"AC860000", -- 000009B0
-		X"34430080", -- 000009B4
-		X"8C860000", -- 000009B8
-		X"00000000", -- 000009BC
-		X"00C31024", -- 000009C0
-		X"1443FFFC", -- 000009C4
-		X"3C02001A", -- 000009C8
-		X"3442001A", -- 000009CC
-		X"00C21024", -- 000009D0
-		X"10400003", -- 000009D4
-		X"00001821", -- 000009D8
-		X"3C029010", -- 000009DC
-		X"00C21825", -- 000009E0
-		X"3C0200FF", -- 000009E4
-		X"344200FF", -- 000009E8
-		X"AC820000", -- 000009EC
-		X"03E00008", -- 000009F0
-		X"00601021", -- 000009F4
-		X"8C820008", -- 000009F8
-		X"27BDFFE8", -- 000009FC
-		X"00021082", -- 00000A00
-		X"00A2102B", -- 00000A04
-		X"AFB40014", -- 00000A08
-		X"AFB30010", -- 00000A0C
-		X"AFB2000C", -- 00000A10
-		X"AFB10008", -- 00000A14
-		X"AFB00004", -- 00000A18
-		X"0080C021", -- 00000A1C
-		X"8C8E0000", -- 00000A20
-		X"14400004", -- 00000A24
-		X"00C0A021", -- 00000A28
-		X"3C028010", -- 00000A2C
-		X"0BF002E3", -- 00000A30
-		X"34440002", -- 00000A34
-		X"8C820010", -- 00000A38
-		X"00006821", -- 00000A3C
-		X"2442FFFF", -- 00000A40
-		X"0002CC00", -- 00000A44
-		X"3C0200E8", -- 00000A48
-		X"345300E8", -- 00000A4C
-		X"3C020080", -- 00000A50
-		X"344F0080", -- 00000A54
-		X"3C02001A", -- 00000A58
-		X"3446001A", -- 00000A5C
-		X"3C0200D0", -- 00000A60
-		X"345200D0", -- 00000A64
-		X"3C0200FF", -- 00000A68
-		X"345100FF", -- 00000A6C
-		X"0BF002E1", -- 00000A70
-		X"3C100001", -- 00000A74
-		X"01851023", -- 00000A78
-		X"00505021", -- 00000A7C
-		X"00EA102B", -- 00000A80
-		X"10400002", -- 00000A84
-		X"000C1080", -- 00000A88
-		X"00E05021", -- 00000A8C
-		X"0BF002D7", -- 00000A90
-		X"01C25821", -- 00000A94
-		X"AD730000", -- 00000A98
-		X"8D630000", -- 00000A9C
-		X"00000000", -- 00000AA0
-		X"006F1024", -- 00000AA4
-		X"144FFFFC", -- 00000AA8
-		X"00661024", -- 00000AAC
-		X"14400026", -- 00000AB0
-		X"3C029010", -- 00000AB4
-		X"8F020014", -- 00000AB8
-		X"00000000", -- 00000ABC
-		X"00021882", -- 00000AC0
-		X"006A102B", -- 00000AC4
-		X"10400002", -- 00000AC8
-		X"01404021", -- 00000ACC
-		X"00604021", -- 00000AD0
-		X"2503FFFF", -- 00000AD4
-		X"00031400", -- 00000AD8
-		X"00431025", -- 00000ADC
-		X"00052080", -- 00000AE0
-		X"000D1880", -- 00000AE4
-		X"02834821", -- 00000AE8
-		X"AD620000", -- 00000AEC
-		X"01C42021", -- 00000AF0
-		X"0BF002C3", -- 00000AF4
-		X"00001821", -- 00000AF8
-		X"8D220000", -- 00000AFC
-		X"25290004", -- 00000B00
-		X"AC820000", -- 00000B04
-		X"24840004", -- 00000B08
-		X"0068102B", -- 00000B0C
-		X"1440FFFA", -- 00000B10
-		X"24630001", -- 00000B14
-		X"01A86821", -- 00000B18
-		X"00A82821", -- 00000B1C
-		X"00E83823", -- 00000B20
-		X"AD720000", -- 00000B24
-		X"8D630000", -- 00000B28
-		X"00000000", -- 00000B2C
-		X"006F1024", -- 00000B30
-		X"144FFFFC", -- 00000B34
-		X"00661024", -- 00000B38
-		X"10400005", -- 00000B3C
-		X"01485023", -- 00000B40
-		X"01485021", -- 00000B44
-		X"3C029010", -- 00000B48
-		X"0BF002D9", -- 00000B4C
-		X"00622025", -- 00000B50
-		X"AD710000", -- 00000B54
-		X"00002021", -- 00000B58
-		X"1540FFCE", -- 00000B5C
-		X"00000000", -- 00000B60
-		X"04810007", -- 00000B64
-		X"000C1880", -- 00000B68
-		X"3C0200FF", -- 00000B6C
-		X"01C31821", -- 00000B70
-		X"344200FF", -- 00000B74
-		X"AC620000", -- 00000B78
-		X"0BF002E4", -- 00000B7C
-		X"00801021", -- 00000B80
-		X"14E0FFBC", -- 00000B84
-		X"00B96024", -- 00000B88
-		X"00801021", -- 00000B8C
-		X"8FB40014", -- 00000B90
-		X"8FB30010", -- 00000B94
-		X"8FB2000C", -- 00000B98
-		X"8FB10008", -- 00000B9C
-		X"8FB00004", -- 00000BA0
-		X"03E00008", -- 00000BA4
-		X"27BD0018", -- 00000BA8
-		X"27BDFFE0", -- 00000BAC
-		X"AFBF001C", -- 00000BB0
-		X"AC850000", -- 00000BB4
-		X"24820008", -- 00000BB8
-		X"0BF002F3", -- 00000BBC
-		X"24830020", -- 00000BC0
-		X"A0400000", -- 00000BC4
-		X"24420001", -- 00000BC8
-		X"1443FFFD", -- 00000BCC
-		X"00000000", -- 00000BD0
-		X"3C021234", -- 00000BD4
-		X"34425678", -- 00000BD8
-		X"00021E02", -- 00000BDC
-		X"AFA20010", -- 00000BE0
-		X"24020012", -- 00000BE4
-		X"14620003", -- 00000BE8
-		X"AC800004", -- 00000BEC
-		X"24020001", -- 00000BF0
-		X"AC820004", -- 00000BF4
-		X"0FF00185", -- 00000BF8
-		X"00000000", -- 00000BFC
-		X"8FBF001C", -- 00000C00
-		X"00000000", -- 00000C04
-		X"03E00008", -- 00000C08
-		X"27BD0020", -- 00000C0C
-		X"27BDFFD8", -- 00000C10
-		X"30C20003", -- 00000C14
-		X"AFB2001C", -- 00000C18
-		X"AFBF0024", -- 00000C1C
-		X"AFB30020", -- 00000C20
-		X"AFB10018", -- 00000C24
-		X"AFB00014", -- 00000C28
-		X"10400004", -- 00000C2C
-		X"00809021", -- 00000C30
-		X"00061082", -- 00000C34
-		X"24420001", -- 00000C38
-		X"00023080", -- 00000C3C
-		X"00C59821", -- 00000C40
-		X"0BF00324", -- 00000C44
-		X"00A08821", -- 00000C48
-		X"0FF001CA", -- 00000C4C
-		X"00000000", -- 00000C50
-		X"02402021", -- 00000C54
-		X"10400005", -- 00000C58
-		X"02002821", -- 00000C5C
-		X"0FF00236", -- 00000C60
-		X"00000000", -- 00000C64
-		X"04400011", -- 00000C68
-		X"00401821", -- 00000C6C
-		X"02002821", -- 00000C70
-		X"0FF001E6", -- 00000C74
-		X"02402021", -- 00000C78
-		X"0440000C", -- 00000C7C
-		X"00401821", -- 00000C80
-		X"8E42000C", -- 00000C84
-		X"00000000", -- 00000C88
-		X"02228821", -- 00000C8C
-		X"001117C3", -- 00000C90
-		X"00021782", -- 00000C94
-		X"00511021", -- 00000C98
-		X"00028083", -- 00000C9C
-		X"0233102B", -- 00000CA0
-		X"02402021", -- 00000CA4
-		X"1440FFE8", -- 00000CA8
-		X"02002821", -- 00000CAC
-		X"8FBF0024", -- 00000CB0
-		X"00601021", -- 00000CB4
-		X"8FB30020", -- 00000CB8
-		X"8FB2001C", -- 00000CBC
-		X"8FB10018", -- 00000CC0
-		X"8FB00014", -- 00000CC4
-		X"03E00008", -- 00000CC8
-		X"27BD0028", -- 00000CCC
-		X"30E20003", -- 00000CD0
-		X"10400003", -- 00000CD4
-		X"00071082", -- 00000CD8
-		X"24420001", -- 00000CDC
-		X"00023880", -- 00000CE0
-		X"00052882", -- 00000CE4
-		X"0BF0027E", -- 00000CE8
-		X"00073882", -- 00000CEC
-		X"8C820000", -- 00000CF0
-		X"00002021", -- 00000CF4
-		X"0BF00347", -- 00000CF8
-		X"00454021", -- 00000CFC
-		X"90630000", -- 00000D00
-		X"90A20000", -- 00000D04
-		X"00000000", -- 00000D08
-		X"10620003", -- 00000D0C
-		X"3C028010", -- 00000D10
-		X"03E00008", -- 00000D14
-		X"34420003", -- 00000D18
-		X"0087102B", -- 00000D1C
-		X"01041821", -- 00000D20
-		X"00C42821", -- 00000D24
-		X"1440FFF5", -- 00000D28
-		X"24840001", -- 00000D2C
-		X"03E00008", -- 00000D30
-		X"00000000", -- 00000D34
-		X"8C82000C", -- 00000D38
-		X"00000000", -- 00000D3C
-		X"14400002", -- 00000D40
-		X"00A2001B", -- 00000D44
-		X"0007000D", -- 00000D48
-		X"00001010", -- 00000D4C
-		X"0002102B", -- 00000D50
-		X"00002812", -- 00000D54
-		X"03E00008", -- 00000D58
-		X"00A21021", -- 00000D5C
-		X"8C830010", -- 00000D60
-		X"00000000", -- 00000D64
-		X"00A3102B", -- 00000D68
-		X"14400002", -- 00000D6C
-		X"00000000", -- 00000D70
-		X"2465FFFF", -- 00000D74
-		X"8C82000C", -- 00000D78
-		X"00000000", -- 00000D7C
-		X"00A20018", -- 00000D80
-		X"00001012", -- 00000D84
-		X"03E00008", -- 00000D88
-		X"00000000", -- 00000D8C
-		X"27BDFFE8", -- 00000D90
-		X"AFBF0014", -- 00000D94
-		X"AFB00010", -- 00000D98
-		X"0FF0034E", -- 00000D9C
-		X"00808021", -- 00000DA0
-		X"8E03000C", -- 00000DA4
-		X"8FBF0014", -- 00000DA8
-		X"00430018", -- 00000DAC
-		X"8FB00010", -- 00000DB0
-		X"00001012", -- 00000DB4
-		X"03E00008", -- 00000DB8
-		X"27BD0018", -- 00000DBC
-		X"90830000", -- 00000DC0
-		X"00000000", -- 00000DC4
-		X"2C620041", -- 00000DC8
-		X"14400002", -- 00000DCC
-		X"2462FFD0", -- 00000DD0
-		X"2462FFC9", -- 00000DD4
-		X"90840001", -- 00000DD8
-		X"304200FF", -- 00000DDC
-		X"304300FF", -- 00000DE0
-		X"2C820041", -- 00000DE4
-		X"14400003", -- 00000DE8
-		X"00000000", -- 00000DEC
-		X"0BF0037F", -- 00000DF0
-		X"2482FFC9", -- 00000DF4
-		X"2482FFD0", -- 00000DF8
-		X"304400FF", -- 00000DFC
-		X"00031100", -- 00000E00
-		X"00821025", -- 00000E04
-		X"03E00008", -- 00000E08
-		X"304200FF", -- 00000E0C
-		X"10C00094", -- 00000E10
-		X"00805021", -- 00000E14
-		X"24020003", -- 00000E18
-		X"AC820008", -- 00000E1C
-		X"90A40001", -- 00000E20
-		X"00000000", -- 00000E24
-		X"2482FFCF", -- 00000E28
-		X"304200FF", -- 00000E2C
-		X"2C420003", -- 00000E30
-		X"10400005", -- 00000E34
-		X"2482FFC9", -- 00000E38
-		X"24020002", -- 00000E3C
-		X"AD420008", -- 00000E40
-		X"0BF003A1", -- 00000E44
-		X"2489FFD1", -- 00000E48
-		X"304200FF", -- 00000E4C
-		X"2C420003", -- 00000E50
-		X"10400006", -- 00000E54
-		X"24020030", -- 00000E58
-		X"2402003B", -- 00000E5C
-		X"00444823", -- 00000E60
-		X"24020004", -- 00000E64
-		X"0BF003A1", -- 00000E68
-		X"AD420008", -- 00000E6C
-		X"14820004", -- 00000E70
-		X"00004821", -- 00000E74
-		X"24020001", -- 00000E78
-		X"AD420008", -- 00000E7C
-		X"24090002", -- 00000E80
-		X"90A30002", -- 00000E84
-		X"00000000", -- 00000E88
-		X"2C620041", -- 00000E8C
-		X"10400003", -- 00000E90
-		X"24A40002", -- 00000E94
-		X"0BF003A9", -- 00000E98
-		X"2462FFD0", -- 00000E9C
-		X"2462FFC9", -- 00000EA0
-		X"90830001", -- 00000EA4
-		X"304200FF", -- 00000EA8
-		X"304400FF", -- 00000EAC
-		X"2C620041", -- 00000EB0
-		X"10400002", -- 00000EB4
-		X"2462FFC9", -- 00000EB8
-		X"2462FFD0", -- 00000EBC
-		X"304300FF", -- 00000EC0
-		X"00041100", -- 00000EC4
-		X"00621025", -- 00000EC8
-		X"304200FF", -- 00000ECC
-		X"AD420004", -- 00000ED0
-		X"AD400000", -- 00000ED4
-		X"00405821", -- 00000ED8
-		X"00A03021", -- 00000EDC
-		X"0BF003D5", -- 00000EE0
-		X"00003821", -- 00000EE4
-		X"90C20004", -- 00000EE8
-		X"00000000", -- 00000EEC
-		X"2443FFC9", -- 00000EF0
-		X"2444FFD0", -- 00000EF4
-		X"2C420041", -- 00000EF8
-		X"10400002", -- 00000EFC
-		X"306300FF", -- 00000F00
-		X"308300FF", -- 00000F04
-		X"90C20005", -- 00000F08
-		X"306800FF", -- 00000F0C
-		X"2444FFC9", -- 00000F10
-		X"2443FFD0", -- 00000F14
-		X"2C420041", -- 00000F18
-		X"10400002", -- 00000F1C
-		X"308400FF", -- 00000F20
-		X"306400FF", -- 00000F24
-		X"8D430000", -- 00000F28
-		X"00081100", -- 00000F2C
-		X"00821025", -- 00000F30
-		X"304200FF", -- 00000F34
-		X"00031A00", -- 00000F38
-		X"004B2021", -- 00000F3C
-		X"00431025", -- 00000F40
-		X"AD420000", -- 00000F44
-		X"308B00FF", -- 00000F48
-		X"24E70001", -- 00000F4C
-		X"24C60002", -- 00000F50
-		X"00E9102A", -- 00000F54
-		X"1440FFE3", -- 00000F58
-		X"25220002", -- 00000F5C
-		X"8D440004", -- 00000F60
-		X"00021040", -- 00000F64
-		X"00091827", -- 00000F68
-		X"00832021", -- 00000F6C
-		X"00A21021", -- 00000F70
-		X"AD440004", -- 00000F74
-		X"AD42000C", -- 00000F78
-		X"0BF003F9", -- 00000F7C
-		X"00003021", -- 00000F80
-		X"90E20000", -- 00000F84
-		X"00000000", -- 00000F88
-		X"2444FFC9", -- 00000F8C
-		X"2445FFD0", -- 00000F90
-		X"2C420041", -- 00000F94
-		X"10400002", -- 00000F98
-		X"308400FF", -- 00000F9C
-		X"30A400FF", -- 00000FA0
-		X"90E20001", -- 00000FA4
-		X"308700FF", -- 00000FA8
-		X"2445FFC9", -- 00000FAC
-		X"2444FFD0", -- 00000FB0
-		X"2C420041", -- 00000FB4
-		X"14400002", -- 00000FB8
-		X"308400FF", -- 00000FBC
-		X"30A400FF", -- 00000FC0
-		X"00071100", -- 00000FC4
-		X"00821025", -- 00000FC8
-		X"304200FF", -- 00000FCC
-		X"00661821", -- 00000FD0
-		X"004B2021", -- 00000FD4
-		X"A0620000", -- 00000FD8
-		X"308B00FF", -- 00000FDC
-		X"24C60001", -- 00000FE0
-		X"8D420004", -- 00000FE4
-		X"8D43000C", -- 00000FE8
-		X"00062040", -- 00000FEC
-		X"00C2102A", -- 00000FF0
-		X"1440FFE3", -- 00000FF4
-		X"00643821", -- 00000FF8
-		X"90E40000", -- 00000FFC
-		X"00000000", -- 00001000
-		X"2C820041", -- 00001004
-		X"10400003", -- 00001008
-		X"00E01821", -- 0000100C
-		X"0BF00407", -- 00001010
-		X"2482FFD0", -- 00001014
-		X"2482FFC9", -- 00001018
-		X"90630001", -- 0000101C
-		X"304200FF", -- 00001020
-		X"304400FF", -- 00001024
-		X"2C620041", -- 00001028
-		X"10400002", -- 0000102C
-		X"2462FFC9", -- 00001030
-		X"2462FFD0", -- 00001034
-		X"304200FF", -- 00001038
-		X"00041900", -- 0000103C
-		X"00431825", -- 00001040
-		X"000B1027", -- 00001044
-		X"304200FF", -- 00001048
-		X"306300FF", -- 0000104C
-		X"14430004", -- 00001050
-		X"00000000", -- 00001054
-		X"8D420008", -- 00001058
-		X"03E00008", -- 0000105C
-		X"00000000", -- 00001060
-		X"03E00008", -- 00001064
-		X"00001021", -- 00001068
-		X"00800008", -- 0000106C
-		X"00000000", -- 00001070
-		X"03E00008", -- 00001074
-		X"00000000", -- 00001078
-		X"3C1A1000", -- 0000107C
-		X"409A6000", -- 00001080
-		X"00800008", -- 00001084
-		X"42000010", -- 00001088
-		X"03E00008", -- 0000108C
-		X"00000000", -- 00001090
-		X"401A6000", -- 00001094
-		X"3C1BFFBF", -- 00001098
-		X"377BFFFF", -- 0000109C
-		X"035BD024", -- 000010A0
-		X"3C1B0200", -- 000010A4
-		X"035BD025", -- 000010A8
-		X"409A6000", -- 000010AC
-		X"00800008", -- 000010B0
-		X"42000010", -- 000010B4
-		X"03E00008", -- 000010B8
-		X"00000000", -- 000010BC
-		X"27BDFFD8", -- 000010C0
-		X"AFB30020", -- 000010C4
-		X"AFB10018", -- 000010C8
-		X"AFB00014", -- 000010CC
-		X"AFBF0024", -- 000010D0
-		X"AFB2001C", -- 000010D4
-		X"00809821", -- 000010D8
-		X"24110073", -- 000010DC
-		X"24100053", -- 000010E0
-		X"0FF00081", -- 000010E4
-		X"00000000", -- 000010E8
-		X"14510005", -- 000010EC
-		X"00000000", -- 000010F0
-		X"00008021", -- 000010F4
-		X"2412000A", -- 000010F8
-		X"0BF00449", -- 000010FC
-		X"2411000D", -- 00001100
-		X"1450FFF7", -- 00001104
-		X"00000000", -- 00001108
-		X"0BF0043E", -- 0000110C
-		X"00008021", -- 00001110
-		X"0FF00081", -- 00001114
-		X"A0620000", -- 00001118
-		X"10510003", -- 0000111C
-		X"26100001", -- 00001120
-		X"1452FFFB", -- 00001124
-		X"02701821", -- 00001128
-		X"8FBF0024", -- 0000112C
-		X"02001021", -- 00001130
-		X"8FB30020", -- 00001134
-		X"8FB2001C", -- 00001138
-		X"8FB10018", -- 0000113C
-		X"8FB00014", -- 00001140
-		X"03E00008", -- 00001144
-		X"27BD0028", -- 00001148
-		X"27BDFD98", -- 0000114C
-		X"27A40140", -- 00001150
-		X"00002821", -- 00001154
-		X"24060100", -- 00001158
-		X"AFB20248", -- 0000115C
-		X"AFB10244", -- 00001160
-		X"AFB00240", -- 00001164
-		X"3C11A000", -- 00001168
-		X"AFBF0264", -- 0000116C
-		X"AFBE0260", -- 00001170
-		X"AFB7025C", -- 00001174
-		X"AFB60258", -- 00001178
-		X"AFB50254", -- 0000117C
-		X"AFB40250", -- 00001180
-		X"0FF0056A", -- 00001184
-		X"AFB3024C", -- 00001188
-		X"3C036000", -- 0000118C
-		X"36220004", -- 00001190
-		X"3463B1FF", -- 00001194
-		X"AC430000", -- 00001198
-		X"3C022000", -- 0000119C
-		X"27B20020", -- 000011A0
-		X"34421000", -- 000011A4
-		X"AE220000", -- 000011A8
-		X"02402021", -- 000011AC
-		X"3C05A400", -- 000011B0
-		X"8E300000", -- 000011B4
-		X"0FF002EB", -- 000011B8
-		X"00000000", -- 000011BC
-		X"04410004", -- 000011C0
-		X"00102C02", -- 000011C4
-		X"3C04BFC0", -- 000011C8
-		X"0BF00493", -- 000011CC
-		X"248416A0", -- 000011D0
-		X"02402021", -- 000011D4
-		X"0FF00358", -- 000011D8
-		X"30A5007F", -- 000011DC
-		X"00409021", -- 000011E0
-		X"8E220000", -- 000011E4
-		X"3C030800", -- 000011E8
-		X"00431024", -- 000011EC
-		X"14400044", -- 000011F0
-		X"3C11BFC0", -- 000011F4
-		X"0FF000B0", -- 000011F8
-		X"26241754", -- 000011FC
-		X"3C02A400", -- 00001200
-		X"02428021", -- 00001204
-		X"8E030000", -- 00001208
-		X"3C023149", -- 0000120C
-		X"3442464A", -- 00001210
-		X"10620011", -- 00001214
-		X"3C024A46", -- 00001218
-		X"34424931", -- 0000121C
-		X"1062000E", -- 00001220
-		X"00000000", -- 00001224
-		X"0FF000B0", -- 00001228
-		X"26241754", -- 0000122C
-		X"3C04BFC0", -- 00001230
-		X"0FF000B0", -- 00001234
-		X"248416C8", -- 00001238
-		X"0FF000E8", -- 0000123C
-		X"02402021", -- 00001240
-		X"3C04BFC0", -- 00001244
-		X"248416E0", -- 00001248
-		X"0FF000B0", -- 0000124C
-		X"00000000", -- 00001250
-		X"0BF0055E", -- 00001254
-		X"24020001", -- 00001258
-		X"3C04BFC0", -- 0000125C
-		X"0FF000B0", -- 00001260
-		X"248416EC", -- 00001264
-		X"0FF000E8", -- 00001268
-		X"02402021", -- 0000126C
-		X"3C04BFC0", -- 00001270
-		X"0FF000B0", -- 00001274
-		X"24841710", -- 00001278
-		X"8E02000C", -- 0000127C
-		X"8E110004", -- 00001280
-		X"00024082", -- 00001284
-		X"8E070008", -- 00001288
-		X"00002021", -- 0000128C
-		X"0BF004A9", -- 00001290
-		X"00001821", -- 00001294
-		X"8CC20000", -- 00001298
-		X"00000000", -- 0000129C
-		X"ACA20000", -- 000012A0
-		X"0088102B", -- 000012A4
-		X"00673021", -- 000012A8
-		X"00712821", -- 000012AC
-		X"24840001", -- 000012B0
-		X"1440FFF8", -- 000012B4
-		X"24630004", -- 000012B8
-		X"3C04BFC0", -- 000012BC
-		X"0FF000B0", -- 000012C0
-		X"24841718", -- 000012C4
-		X"3C04BFC0", -- 000012C8
-		X"0FF000B0", -- 000012CC
-		X"24841720", -- 000012D0
-		X"8E040004", -- 000012D4
-		X"0FF000E8", -- 000012D8
-		X"00000000", -- 000012DC
-		X"3C04BFC0", -- 000012E0
-		X"0FF000B0", -- 000012E4
-		X"24841754", -- 000012E8
-		X"3C1A1000", -- 000012EC
-		X"409A6000", -- 000012F0
-		X"02200008", -- 000012F4
-		X"42000010", -- 000012F8
-		X"0BF0055E", -- 000012FC
-		X"00001021", -- 00001300
-		X"0FF000B0", -- 00001304
-		X"26241754", -- 00001308
-		X"3C04BFC0", -- 0000130C
-		X"0FF000B0", -- 00001310
-		X"2484172C", -- 00001314
-		X"3C024000", -- 00001318
-		X"3C034010", -- 0000131C
-		X"AC400000", -- 00001320
-		X"24420004", -- 00001324
-		X"1443FFFD", -- 00001328
-		X"00009821", -- 0000132C
-		X"3C02BFC0", -- 00001330
-		X"245516C4", -- 00001334
-		X"3C02BFC0", -- 00001338
-		X"24561718", -- 0000133C
-		X"3C02BFC0", -- 00001340
-		X"245E17CC", -- 00001344
-		X"3C02BFC0", -- 00001348
-		X"245717EC", -- 0000134C
-		X"3C04BFC0", -- 00001350
-		X"0FF000B0", -- 00001354
-		X"2484174C", -- 00001358
-		X"3C14BFC0", -- 0000135C
-		X"27B00040", -- 00001360
-		X"0FF00430", -- 00001364
-		X"02002021", -- 00001368
-		X"00403021", -- 0000136C
-		X"02002821", -- 00001370
-		X"27A40010", -- 00001374
-		X"0FF00384", -- 00001378
-		X"00408821", -- 0000137C
-		X"00401821", -- 00001380
-		X"24020002", -- 00001384
-		X"10620005", -- 00001388
-		X"24020004", -- 0000138C
-		X"1462FFEF", -- 00001390
-		X"00000000", -- 00001394
-		X"0BF004FD", -- 00001398
-		X"3C04BFC0", -- 0000139C
-		X"8FA50010", -- 000013A0
-		X"8FA60014", -- 000013A4
-		X"0BF004F2", -- 000013A8
-		X"00001821", -- 000013AC
-		X"8FA2001C", -- 000013B0
-		X"00000000", -- 000013B4
-		X"00431021", -- 000013B8
-		X"90420000", -- 000013BC
-		X"24630001", -- 000013C0
-		X"A0820000", -- 000013C4
-		X"8FA20014", -- 000013C8
-		X"00000000", -- 000013CC
-		X"0062102B", -- 000013D0
-		X"1440FFF6", -- 000013D4
-		X"00652021", -- 000013D8
-		X"00C51821", -- 000013DC
-		X"0263102B", -- 000013E0
-		X"10400060", -- 000013E4
-		X"02208021", -- 000013E8
-		X"0BF0055A", -- 000013EC
-		X"00609821", -- 000013F0
-		X"0FF000B0", -- 000013F4
-		X"24841750", -- 000013F8
-		X"8FA60010", -- 000013FC
-		X"26470100", -- 00001400
-		X"02661823", -- 00001404
-		X"27B10020", -- 00001408
-		X"3C024A46", -- 0000140C
-		X"00E32821", -- 00001410
-		X"02202021", -- 00001414
-		X"34424931", -- 00001418
-		X"AFA60144", -- 0000141C
-		X"AFA3014C", -- 00001420
-		X"AFA70148", -- 00001424
-		X"0FF00364", -- 00001428
-		X"AFA20140", -- 0000142C
-		X"3C04BFC0", -- 00001430
-		X"24841758", -- 00001434
-		X"0FF000B0", -- 00001438
-		X"AFA20150", -- 0000143C
-		X"8FA4014C", -- 00001440
-		X"0FF000E8", -- 00001444
-		X"00000000", -- 00001448
-		X"0FF000B0", -- 0000144C
-		X"02A02021", -- 00001450
-		X"3C04BFC0", -- 00001454
-		X"0FF000B0", -- 00001458
-		X"24841774", -- 0000145C
-		X"0FF000E8", -- 00001460
-		X"02402021", -- 00001464
-		X"0FF000B0", -- 00001468
-		X"02A02021", -- 0000146C
-		X"3C04BFC0", -- 00001470
-		X"0FF000B0", -- 00001474
-		X"24841790", -- 00001478
-		X"8FA40150", -- 0000147C
-		X"0FF000E8", -- 00001480
-		X"00000000", -- 00001484
-		X"0FF000B0", -- 00001488
-		X"02A02021", -- 0000148C
-		X"3C04BFC0", -- 00001490
-		X"0FF000B0", -- 00001494
-		X"248417AC", -- 00001498
-		X"8FA6014C", -- 0000149C
-		X"02202021", -- 000014A0
-		X"24C60100", -- 000014A4
-		X"0FF00304", -- 000014A8
-		X"02402821", -- 000014AC
-		X"0440001F", -- 000014B0
-		X"00408021", -- 000014B4
-		X"0FF000B0", -- 000014B8
-		X"02C02021", -- 000014BC
-		X"0FF000B0", -- 000014C0
-		X"03C02021", -- 000014C4
-		X"02202021", -- 000014C8
-		X"02402821", -- 000014CC
-		X"27A60140", -- 000014D0
-		X"0FF00334", -- 000014D4
-		X"24070100", -- 000014D8
-		X"04400014", -- 000014DC
-		X"00408021", -- 000014E0
-		X"8FA50148", -- 000014E4
-		X"8FA60144", -- 000014E8
-		X"8FA7014C", -- 000014EC
-		X"0FF00334", -- 000014F0
-		X"02202021", -- 000014F4
-		X"0440000D", -- 000014F8
-		X"00408021", -- 000014FC
-		X"0FF000B0", -- 00001500
-		X"02C02021", -- 00001504
-		X"3C04BFC0", -- 00001508
-		X"0FF000B0", -- 0000150C
-		X"248417DC", -- 00001510
-		X"8FA50148", -- 00001514
-		X"8FA60144", -- 00001518
-		X"8FA7014C", -- 0000151C
-		X"0FF0033C", -- 00001520
-		X"02202021", -- 00001524
-		X"0441000A", -- 00001528
-		X"00408021", -- 0000152C
-		X"0FF000B0", -- 00001530
-		X"268417BC", -- 00001534
-		X"0FF000E8", -- 00001538
-		X"02002021", -- 0000153C
-		X"3C04BFC0", -- 00001540
-		X"0FF000B0", -- 00001544
-		X"248417C8", -- 00001548
-		X"0BF0055A", -- 0000154C
-		X"00000000", -- 00001550
-		X"0FF000B0", -- 00001554
-		X"02E02021", -- 00001558
-		X"3C02BFC0", -- 0000155C
-		X"00400008", -- 00001560
-		X"00000000", -- 00001564
-		X"0601FF7E", -- 00001568
-		X"27B00040", -- 0000156C
-		X"0BF004D5", -- 00001570
-		X"3C04BFC0", -- 00001574
-		X"8FBF0264", -- 00001578
-		X"8FBE0260", -- 0000157C
-		X"8FB7025C", -- 00001580
-		X"8FB60258", -- 00001584
-		X"8FB50254", -- 00001588
-		X"8FB40250", -- 0000158C
-		X"8FB3024C", -- 00001590
-		X"8FB20248", -- 00001594
-		X"8FB10244", -- 00001598
-		X"8FB00240", -- 0000159C
-		X"03E00008", -- 000015A0
-		X"27BD0268", -- 000015A4
-		X"2CC20010", -- 000015A8
-		X"00804821", -- 000015AC
-		X"1440002D", -- 000015B0
-		X"00804021", -- 000015B4
-		X"30870003", -- 000015B8
-		X"10E0000E", -- 000015BC
-		X"24820004", -- 000015C0
-		X"00052600", -- 000015C4
-		X"00471023", -- 000015C8
-		X"00042603", -- 000015CC
-		X"01201821", -- 000015D0
-		X"A0640000", -- 000015D4
-		X"24630001", -- 000015D8
-		X"1462FFFD", -- 000015DC
-		X"00000000", -- 000015E0
-		X"00071027", -- 000015E4
-		X"24C3FFFB", -- 000015E8
-		X"24440005", -- 000015EC
-		X"00623023", -- 000015F0
-		X"01244021", -- 000015F4
-		X"30A500FF", -- 000015F8
-		X"01003821", -- 000015FC
-		X"10A00005", -- 00001600
-		X"00A01821", -- 00001604
-		X"00051200", -- 00001608
-		X"00451025", -- 0000160C
-		X"00021C00", -- 00001610
-		X"00621825", -- 00001614
-		X"000610C2", -- 00001618
-		X"1040001C", -- 0000161C
-		X"30C60007", -- 00001620
-		X"01002021", -- 00001624
-		X"00403821", -- 00001628
-		X"24E7FFFF", -- 0000162C
-		X"AC830000", -- 00001630
-		X"AC830004", -- 00001634
-		X"14E0FFFC", -- 00001638
-		X"24840008", -- 0000163C
-		X"000210C0", -- 00001640
-		X"01023821", -- 00001644
-		X"00E02021", -- 00001648
-		X"2CC20004", -- 0000164C
-		X"14400005", -- 00001650
-		X"00804021", -- 00001654
-		X"ACE30000", -- 00001658
-		X"24E40004", -- 0000165C
-		X"24C6FFFC", -- 00001660
-		X"00804021", -- 00001664
-		X"10C00007", -- 00001668
-		X"00000000", -- 0000166C
-		X"00051600", -- 00001670
-		X"00021603", -- 00001674
-		X"24C6FFFF", -- 00001678
-		X"A1020000", -- 0000167C
-		X"14C0FFFD", -- 00001680
-		X"25080001", -- 00001684
-		X"03E00008", -- 00001688
-		X"01201021", -- 0000168C
-		X"0BF00593", -- 00001690
-		X"01002021", -- 00001694
-		X"3A200000", -- 00001698
-		X"20202000", -- 0000169C
-		X"43616E6E", -- 000016A0
-		X"6F742066", -- 000016A4
-		X"696E6420", -- 000016A8
-		X"666C6173", -- 000016AC
-		X"68206465", -- 000016B0
-		X"76696365", -- 000016B4
-		X"2E204578", -- 000016B8
-		X"6974206E", -- 000016BC
-		X"6F77210A", -- 000016C0
-		X"0A000000", -- 000016C4
-		X"496E7661", -- 000016C8
-		X"6C696420", -- 000016CC
-		X"696D6167", -- 000016D0
-		X"6520666F", -- 000016D4
-		X"756E6420", -- 000016D8
-		X"61742000", -- 000016DC
-		X"2E204162", -- 000016E0
-		X"6F72742E", -- 000016E4
-		X"0A000000", -- 000016E8
-		X"426F6F74", -- 000016EC
-		X"696E6720", -- 000016F0
-		X"6170706C", -- 000016F4
-		X"69636174", -- 000016F8
-		X"696F6E20", -- 000016FC
-		X"66726F6D", -- 00001700
-		X"20666C61", -- 00001704
-		X"73682028", -- 00001708
-		X"00000000", -- 0000170C
-		X"292E2E2E", -- 00001710
-		X"00000000", -- 00001714
-		X"646F6E65", -- 00001718
-		X"0A000000", -- 0000171C
-		X"45786563", -- 00001720
-		X"75746520", -- 00001724
-		X"61742000", -- 00001728
-		X"52656164", -- 0000172C
-		X"696E6720", -- 00001730
-		X"4845582D", -- 00001734
-		X"5265636F", -- 00001738
-		X"72642066", -- 0000173C
-		X"726F6D20", -- 00001740
-		X"55415254", -- 00001744
-		X"2E2E0000", -- 00001748
-		X"2E000000", -- 0000174C
-		X"646F6E65", -- 00001750
-		X"0A0A0000", -- 00001754
-		X"53697A65", -- 00001758
-		X"206F6620", -- 0000175C
-		X"6170706C", -- 00001760
-		X"69636174", -- 00001764
-		X"696F6E20", -- 00001768
-		X"2020203A", -- 0000176C
-		X"20000000", -- 00001770
-		X"50726F67", -- 00001774
-		X"72616D6D", -- 00001778
-		X"696E6720", -- 0000177C
-		X"666C6173", -- 00001780
-		X"68206174", -- 00001784
-		X"2020203A", -- 00001788
-		X"20000000", -- 0000178C
-		X"4E657874", -- 00001790
-		X"20667265", -- 00001794
-		X"6520666C", -- 00001798
-		X"61736820", -- 0000179C
-		X"6F666673", -- 000017A0
-		X"6574203A", -- 000017A4
-		X"20000000", -- 000017A8
-		X"466C6173", -- 000017AC
-		X"68206572", -- 000017B0
-		X"6173652E", -- 000017B4
-		X"2E2E0000", -- 000017B8
-		X"6661696C", -- 000017BC
-		X"65642028", -- 000017C0
-		X"00000000", -- 000017C4
-		X"290A0000", -- 000017C8
-		X"466C6173", -- 000017CC
-		X"68207772", -- 000017D0
-		X"6974652E", -- 000017D4
-		X"2E2E0000", -- 000017D8
-		X"466C6173", -- 000017DC
-		X"68207665", -- 000017E0
-		X"72696679", -- 000017E4
-		X"2E2E2E00", -- 000017E8
-		X"70617373", -- 000017EC
-		X"65640A00", -- 000017F0
-		X"00000000", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
-		end if;
-	end process;
-
-end data;
diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd
deleted file mode 100644
index 2785865..0000000
--- a/projects/mips_sys/src/bootloader.ROM_ld.vhd
+++ /dev/null
@@ -1,2174 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY rom IS
-	Port
-	(
-		clk		: in  STD_LOGIC;
-		ce		: in  STD_LOGIC;
-		addr		: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END rom;
-
-ARCHITECTURE data OF rom IS
-
-	subtype word_t is unsigned(31 downto 0);
-	type word_array_t is array (0 to 2047) of word_t;
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: unsigned (15 downto 0);
-	signal jtag_ld_dout		: unsigned (31 downto 0);
-	signal jtag_ld_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-
-	signal word_array : word_array_t :=
-	(
-
-		X"3C1D8000", -- 00000000
-		X"27BDEFF0", -- 00000004
-		X"3C1A1040", -- 00000008
-		X"375A000C", -- 0000000C
-		X"409A6000", -- 00000010
-		X"241A0000", -- 00000014
-		X"409A6800", -- 00000018
-		X"401A7800", -- 0000001C
-		X"00000000", -- 00000020
-		X"409AF800", -- 00000024
-		X"42000020", -- 00000028
-		X"42000022", -- 0000002C
-		X"3C1ABFC0", -- 00000030
-		X"275A005C", -- 00000034
-		X"0340F809", -- 00000038
-		X"00000000", -- 0000003C
-		X"3C1ABFC0", -- 00000040
-		X"275A114C", -- 00000044
-		X"0340F809", -- 00000048
-		X"00000000", -- 0000004C
-		X"00000000", -- 00000050
-		X"0BF00014", -- 00000054
-		X"00000000", -- 00000058
-		X"3C1AA001", -- 0000005C
-		X"275A0008", -- 00000060
-		X"241B000D", -- 00000064
-		X"AF5B0000", -- 00000068
-		X"03E00008", -- 0000006C
-		X"00000000", -- 00000070
-		X"00000000", -- 00000074
-		X"00000000", -- 00000078
-		X"00000000", -- 0000007C
-		X"00000000", -- 00000080
-		X"00000000", -- 00000084
-		X"00000000", -- 00000088
-		X"00000000", -- 0000008C
-		X"00000000", -- 00000090
-		X"00000000", -- 00000094
-		X"00000000", -- 00000098
-		X"00000000", -- 0000009C
-		X"00000000", -- 000000A0
-		X"00000000", -- 000000A4
-		X"00000000", -- 000000A8
-		X"00000000", -- 000000AC
-		X"00000000", -- 000000B0
-		X"00000000", -- 000000B4
-		X"00000000", -- 000000B8
-		X"00000000", -- 000000BC
-		X"00000000", -- 000000C0
-		X"00000000", -- 000000C4
-		X"00000000", -- 000000C8
-		X"00000000", -- 000000CC
-		X"00000000", -- 000000D0
-		X"00000000", -- 000000D4
-		X"00000000", -- 000000D8
-		X"00000000", -- 000000DC
-		X"00000000", -- 000000E0
-		X"00000000", -- 000000E4
-		X"00000000", -- 000000E8
-		X"00000000", -- 000000EC
-		X"00000000", -- 000000F0
-		X"00000000", -- 000000F4
-		X"00000000", -- 000000F8
-		X"00000000", -- 000000FC
-		X"00000000", -- 00000100
-		X"00000000", -- 00000104
-		X"00000000", -- 00000108
-		X"00000000", -- 0000010C
-		X"00000000", -- 00000110
-		X"00000000", -- 00000114
-		X"00000000", -- 00000118
-		X"00000000", -- 0000011C
-		X"00000000", -- 00000120
-		X"00000000", -- 00000124
-		X"00000000", -- 00000128
-		X"00000000", -- 0000012C
-		X"00000000", -- 00000130
-		X"00000000", -- 00000134
-		X"00000000", -- 00000138
-		X"00000000", -- 0000013C
-		X"00000000", -- 00000140
-		X"00000000", -- 00000144
-		X"00000000", -- 00000148
-		X"00000000", -- 0000014C
-		X"00000000", -- 00000150
-		X"00000000", -- 00000154
-		X"00000000", -- 00000158
-		X"00000000", -- 0000015C
-		X"00000000", -- 00000160
-		X"00000000", -- 00000164
-		X"00000000", -- 00000168
-		X"00000000", -- 0000016C
-		X"00000000", -- 00000170
-		X"00000000", -- 00000174
-		X"00000000", -- 00000178
-		X"00000000", -- 0000017C
-		X"401A6800", -- 00000180
-		X"3C1BC000", -- 00000184
-		X"001AD082", -- 00000188
-		X"335A000F", -- 0000018C
-		X"035BD025", -- 00000190
-		X"3C1BA000", -- 00000194
-		X"277B0000", -- 00000198
-		X"AF7A0000", -- 0000019C
-		X"401A6800", -- 000001A0
-		X"00000000", -- 000001A4
-		X"001AD202", -- 000001A8
-		X"335A00FF", -- 000001AC
-		X"1740FFFB", -- 000001B0
-		X"00000000", -- 000001B4
-		X"401A7000", -- 000001B8
-		X"00000000", -- 000001BC
-		X"03400008", -- 000001C0
-		X"42000010", -- 000001C4
-		X"40026000", -- 000001C8
-		X"03E00008", -- 000001CC
-		X"00000000", -- 000001D0
-		X"40846000", -- 000001D4
-		X"03E00008", -- 000001D8
-		X"00000000", -- 000001DC
-		X"40026800", -- 000001E0
-		X"03E00008", -- 000001E4
-		X"00000000", -- 000001E8
-		X"40846800", -- 000001EC
-		X"03E00008", -- 000001F0
-		X"00000000", -- 000001F4
-		X"40027800", -- 000001F8
-		X"03E00008", -- 000001FC
-		X"00000000", -- 00000200
-		X"3C02A001", -- 00000204
-		X"34430004", -- 00000208
-		X"8C620000", -- 0000020C
-		X"00000000", -- 00000210
-		X"30420010", -- 00000214
-		X"1040FFFC", -- 00000218
-		X"3C02A001", -- 0000021C
-		X"8C420000", -- 00000220
-		X"00000000", -- 00000224
-		X"00021600", -- 00000228
-		X"03E00008", -- 0000022C
-		X"00021603", -- 00000230
-		X"00042600", -- 00000234
-		X"3C02A001", -- 00000238
-		X"00042603", -- 0000023C
-		X"34430004", -- 00000240
-		X"8C620000", -- 00000244
-		X"00000000", -- 00000248
-		X"30420002", -- 0000024C
-		X"1440FFFC", -- 00000250
-		X"3C02A001", -- 00000254
-		X"AC440000", -- 00000258
-		X"03E00008", -- 0000025C
-		X"00000000", -- 00000260
-		X"00042600", -- 00000264
-		X"00042603", -- 00000268
-		X"2402000A", -- 0000026C
-		X"1482000A", -- 00000270
-		X"3C02A001", -- 00000274
-		X"34430004", -- 00000278
-		X"8C620000", -- 0000027C
-		X"00000000", -- 00000280
-		X"30420002", -- 00000284
-		X"1440FFFC", -- 00000288
-		X"3C02A001", -- 0000028C
-		X"2403000D", -- 00000290
-		X"AC430000", -- 00000294
-		X"3C02A001", -- 00000298
-		X"34430004", -- 0000029C
-		X"8C620000", -- 000002A0
-		X"00000000", -- 000002A4
-		X"30420002", -- 000002A8
-		X"1440FFFC", -- 000002AC
-		X"3C02A001", -- 000002B0
-		X"AC440000", -- 000002B4
-		X"03E00008", -- 000002B8
-		X"00000000", -- 000002BC
-		X"3C02A001", -- 000002C0
-		X"34470004", -- 000002C4
-		X"00802821", -- 000002C8
-		X"2409000A", -- 000002CC
-		X"3C06A001", -- 000002D0
-		X"0BF000C6", -- 000002D4
-		X"2408000D", -- 000002D8
-		X"14690007", -- 000002DC
-		X"00000000", -- 000002E0
-		X"8CE20000", -- 000002E4
-		X"00000000", -- 000002E8
-		X"30420002", -- 000002EC
-		X"1440FFFC", -- 000002F0
-		X"00000000", -- 000002F4
-		X"ACC80000", -- 000002F8
-		X"8CE20000", -- 000002FC
-		X"00000000", -- 00000300
-		X"30420002", -- 00000304
-		X"1440FFFC", -- 00000308
-		X"00000000", -- 0000030C
-		X"ACC30000", -- 00000310
-		X"24A50001", -- 00000314
-		X"80A30000", -- 00000318
-		X"00000000", -- 0000031C
-		X"1460FFEE", -- 00000320
-		X"00A41023", -- 00000324
-		X"03E00008", -- 00000328
-		X"00000000", -- 0000032C
-		X"00042600", -- 00000330
-		X"3C02A001", -- 00000334
-		X"00042603", -- 00000338
-		X"344A0004", -- 0000033C
-		X"00003821", -- 00000340
-		X"3C09A001", -- 00000344
-		X"24080002", -- 00000348
-		X"308200FF", -- 0000034C
-		X"00022902", -- 00000350
-		X"00041100", -- 00000354
-		X"00022600", -- 00000358
-		X"2CA3000A", -- 0000035C
-		X"00042603", -- 00000360
-		X"14600002", -- 00000364
-		X"24A60030", -- 00000368
-		X"24A60037", -- 0000036C
-		X"8D420000", -- 00000370
-		X"00000000", -- 00000374
-		X"30420002", -- 00000378
-		X"1440FFFC", -- 0000037C
-		X"00061600", -- 00000380
-		X"00021603", -- 00000384
-		X"24E70001", -- 00000388
-		X"AD220000", -- 0000038C
-		X"14E8FFEF", -- 00000390
-		X"308200FF", -- 00000394
-		X"03E00008", -- 00000398
-		X"00000000", -- 0000039C
-		X"27BDFFE0", -- 000003A0
-		X"AFB20018", -- 000003A4
-		X"AFB10014", -- 000003A8
-		X"AFB00010", -- 000003AC
-		X"AFBF001C", -- 000003B0
-		X"00808821", -- 000003B4
-		X"00008021", -- 000003B8
-		X"24120004", -- 000003BC
-		X"00112603", -- 000003C0
-		X"0FF000CC", -- 000003C4
-		X"26100001", -- 000003C8
-		X"1612FFFC", -- 000003CC
-		X"00118A00", -- 000003D0
-		X"8FBF001C", -- 000003D4
-		X"8FB20018", -- 000003D8
-		X"8FB10014", -- 000003DC
-		X"8FB00010", -- 000003E0
-		X"03E00008", -- 000003E4
-		X"27BD0020", -- 000003E8
-		X"27BDFFC8", -- 000003EC
-		X"AFB60028", -- 000003F0
-		X"AFBF0034", -- 000003F4
-		X"AFBE0030", -- 000003F8
-		X"AFB7002C", -- 000003FC
-		X"AFB50024", -- 00000400
-		X"AFB40020", -- 00000404
-		X"AFB3001C", -- 00000408
-		X"AFB20018", -- 0000040C
-		X"AFB10014", -- 00000410
-		X"AFB00010", -- 00000414
-		X"00801021", -- 00000418
-		X"10A00002", -- 0000041C
-		X"00C0B021", -- 00000420
-		X"00002021", -- 00000424
-		X"00409821", -- 00000428
-		X"3C02A001", -- 0000042C
-		X"00E09021", -- 00000430
-		X"0080A821", -- 00000434
-		X"345E0004", -- 00000438
-		X"00E0A021", -- 0000043C
-		X"3C17A001", -- 00000440
-		X"0FF000E8", -- 00000444
-		X"02A02021", -- 00000448
-		X"3C04BFC0", -- 0000044C
-		X"0FF000B0", -- 00000450
-		X"24841698", -- 00000454
-		X"02608821", -- 00000458
-		X"0BF00128", -- 0000045C
-		X"00008021", -- 00000460
-		X"12400009", -- 00000464
-		X"00000000", -- 00000468
-		X"82240000", -- 0000046C
-		X"0FF000CC", -- 00000470
-		X"2652FFFF", -- 00000474
-		X"3C04BFC0", -- 00000478
-		X"0FF000B0", -- 0000047C
-		X"24841770", -- 00000480
-		X"0BF00128", -- 00000484
-		X"26310001", -- 00000488
-		X"3C04BFC0", -- 0000048C
-		X"0FF000B0", -- 00000490
-		X"2484169C", -- 00000494
-		X"0BF0012C", -- 00000498
-		X"3C04BFC0", -- 0000049C
-		X"0216102A", -- 000004A0
-		X"1440FFEF", -- 000004A4
-		X"26100001", -- 000004A8
-		X"3C04BFC0", -- 000004AC
-		X"0FF000B0", -- 000004B0
-		X"2484169C", -- 000004B4
-		X"02602821", -- 000004B8
-		X"0BF00155", -- 000004BC
-		X"00002021", -- 000004C0
-		X"1280001E", -- 000004C4
-		X"00000000", -- 000004C8
-		X"90A30000", -- 000004CC
-		X"00000000", -- 000004D0
-		X"2462FFE0", -- 000004D4
-		X"304200FF", -- 000004D8
-		X"2C420060", -- 000004DC
-		X"14400003", -- 000004E0
-		X"00031E00", -- 000004E4
-		X"2403002E", -- 000004E8
-		X"00031E00", -- 000004EC
-		X"00031E03", -- 000004F0
-		X"2402000A", -- 000004F4
-		X"14620007", -- 000004F8
-		X"00000000", -- 000004FC
-		X"8FC20000", -- 00000500
-		X"00000000", -- 00000504
-		X"30420002", -- 00000508
-		X"1440FFFC", -- 0000050C
-		X"2402000D", -- 00000510
-		X"AEE20000", -- 00000514
-		X"8FC20000", -- 00000518
-		X"00000000", -- 0000051C
-		X"30420002", -- 00000520
-		X"1440FFFC", -- 00000524
-		X"00000000", -- 00000528
-		X"AEE30000", -- 0000052C
-		X"2694FFFF", -- 00000530
-		X"24840001", -- 00000534
-		X"0BF00155", -- 00000538
-		X"24A50001", -- 0000053C
-		X"3C04BFC0", -- 00000540
-		X"0FF000B0", -- 00000544
-		X"24841770", -- 00000548
-		X"0BF00159", -- 0000054C
-		X"3C04BFC0", -- 00000550
-		X"0096102A", -- 00000554
-		X"1440FFDA", -- 00000558
-		X"00000000", -- 0000055C
-		X"3C04BFC0", -- 00000560
-		X"0FF000B0", -- 00000564
-		X"248416C4", -- 00000568
-		X"02B6A821", -- 0000056C
-		X"1640FFB4", -- 00000570
-		X"02769821", -- 00000574
-		X"8FBF0034", -- 00000578
-		X"8FBE0030", -- 0000057C
-		X"8FB7002C", -- 00000580
-		X"8FB60028", -- 00000584
-		X"8FB50024", -- 00000588
-		X"8FB40020", -- 0000058C
-		X"8FB3001C", -- 00000590
-		X"8FB20018", -- 00000594
-		X"8FB10014", -- 00000598
-		X"8FB00010", -- 0000059C
-		X"03E00008", -- 000005A0
-		X"27BD0038", -- 000005A4
-		X"00C03821", -- 000005A8
-		X"00A03021", -- 000005AC
-		X"0BF000FB", -- 000005B0
-		X"24050001", -- 000005B4
-		X"8C840000", -- 000005B8
-		X"3C020070", -- 000005BC
-		X"34420070", -- 000005C0
-		X"3C0300FF", -- 000005C4
-		X"AC820000", -- 000005C8
-		X"346300FF", -- 000005CC
-		X"8C820000", -- 000005D0
-		X"AC830000", -- 000005D4
-		X"03E00008", -- 000005D8
-		X"00000000", -- 000005DC
-		X"27BDFFF8", -- 000005E0
-		X"AC850000", -- 000005E4
-		X"24820008", -- 000005E8
-		X"0BF0017F", -- 000005EC
-		X"24830020", -- 000005F0
-		X"A0400000", -- 000005F4
-		X"24420001", -- 000005F8
-		X"1443FFFD", -- 000005FC
-		X"00000000", -- 00000600
-		X"24020001", -- 00000604
-		X"AC820004", -- 00000608
-		X"03E00008", -- 0000060C
-		X"27BD0008", -- 00000610
-		X"8C870000", -- 00000614
-		X"3C020098", -- 00000618
-		X"34420098", -- 0000061C
-		X"ACE20000", -- 00000620
-		X"3C0200FF", -- 00000624
-		X"344200FF", -- 00000628
-		X"ACE20000", -- 0000062C
-		X"3C020090", -- 00000630
-		X"34420090", -- 00000634
-		X"ACE20000", -- 00000638
-		X"00804021", -- 0000063C
-		X"94E4009C", -- 00000640
-		X"24030002", -- 00000644
-		X"24020020", -- 00000648
-		X"AD030008", -- 0000064C
-		X"AD03001C", -- 00000650
-		X"AD020018", -- 00000654
-		X"3084FFFF", -- 00000658
-		X"0BF0019D", -- 0000065C
-		X"00001821", -- 00000660
-		X"8D020008", -- 00000664
-		X"00000000", -- 00000668
-		X"00021040", -- 0000066C
-		X"AD020008", -- 00000670
-		X"0064102B", -- 00000674
-		X"1440FFFA", -- 00000678
-		X"24630001", -- 0000067C
-		X"94E200AC", -- 00000680
-		X"94E300A8", -- 00000684
-		X"3042FFFF", -- 00000688
-		X"8D04001C", -- 0000068C
-		X"3063FFFF", -- 00000690
-		X"00021200", -- 00000694
-		X"00432825", -- 00000698
-		X"AD040014", -- 0000069C
-		X"0BF001AE", -- 000006A0
-		X"00001821", -- 000006A4
-		X"8D020014", -- 000006A8
-		X"00000000", -- 000006AC
-		X"00021040", -- 000006B0
-		X"AD020014", -- 000006B4
-		X"0065102B", -- 000006B8
-		X"1440FFFA", -- 000006BC
-		X"24630001", -- 000006C0
-		X"94E300B8", -- 000006C4
-		X"94E600B4", -- 000006C8
-		X"94E200C0", -- 000006CC
-		X"94E400BC", -- 000006D0
-		X"8D05001C", -- 000006D4
-		X"3042FFFF", -- 000006D8
-		X"3084FFFF", -- 000006DC
-		X"00021200", -- 000006E0
-		X"00441025", -- 000006E4
-		X"00052A00", -- 000006E8
-		X"00A20018", -- 000006EC
-		X"3063FFFF", -- 000006F0
-		X"30C6FFFF", -- 000006F4
-		X"00031A00", -- 000006F8
-		X"00661825", -- 000006FC
-		X"24630001", -- 00000700
-		X"AD030010", -- 00000704
-		X"3C0300FF", -- 00000708
-		X"346300FF", -- 0000070C
-		X"00001021", -- 00000710
-		X"00002812", -- 00000714
-		X"AD05000C", -- 00000718
-		X"ACE30000", -- 0000071C
-		X"03E00008", -- 00000720
-		X"00000000", -- 00000724
-		X"8C820008", -- 00000728
-		X"8C860000", -- 0000072C
-		X"00021082", -- 00000730
-		X"00A2102B", -- 00000734
-		X"14400004", -- 00000738
-		X"3C030090", -- 0000073C
-		X"3C028010", -- 00000740
-		X"03E00008", -- 00000744
-		X"34420002", -- 00000748
-		X"8C820010", -- 0000074C
-		X"00000000", -- 00000750
-		X"2442FFFF", -- 00000754
-		X"00021400", -- 00000758
-		X"00A21024", -- 0000075C
-		X"24420002", -- 00000760
-		X"34630090", -- 00000764
-		X"00021080", -- 00000768
-		X"ACC30000", -- 0000076C
-		X"00C21021", -- 00000770
-		X"8C430000", -- 00000774
-		X"3C020001", -- 00000778
-		X"34420001", -- 0000077C
-		X"00621824", -- 00000780
-		X"3C0200FF", -- 00000784
-		X"344200FF", -- 00000788
-		X"ACC20000", -- 0000078C
-		X"03E00008", -- 00000790
-		X"0003102B", -- 00000794
-		X"8C820008", -- 00000798
-		X"00A01821", -- 0000079C
-		X"00021082", -- 000007A0
-		X"00A2102B", -- 000007A4
-		X"8C850000", -- 000007A8
-		X"14400003", -- 000007AC
-		X"3C028010", -- 000007B0
-		X"0BF0020C", -- 000007B4
-		X"34430002", -- 000007B8
-		X"8C820010", -- 000007BC
-		X"00000000", -- 000007C0
-		X"2442FFFF", -- 000007C4
-		X"00021400", -- 000007C8
-		X"00621024", -- 000007CC
-		X"00021080", -- 000007D0
-		X"00A22021", -- 000007D4
-		X"3C020020", -- 000007D8
-		X"34420020", -- 000007DC
-		X"AC820000", -- 000007E0
-		X"3C0200D0", -- 000007E4
-		X"344200D0", -- 000007E8
-		X"AC820000", -- 000007EC
-		X"3C020080", -- 000007F0
-		X"34430080", -- 000007F4
-		X"8C860000", -- 000007F8
-		X"00000000", -- 000007FC
-		X"00C31024", -- 00000800
-		X"1443FFFC", -- 00000804
-		X"3C02002A", -- 00000808
-		X"3442002A", -- 0000080C
-		X"00C21024", -- 00000810
-		X"10400003", -- 00000814
-		X"00001821", -- 00000818
-		X"3C029010", -- 0000081C
-		X"00C21825", -- 00000820
-		X"3C0200FF", -- 00000824
-		X"344200FF", -- 00000828
-		X"AC820000", -- 0000082C
-		X"03E00008", -- 00000830
-		X"00601021", -- 00000834
-		X"8C820008", -- 00000838
-		X"00A01821", -- 0000083C
-		X"00021082", -- 00000840
-		X"00A2102B", -- 00000844
-		X"8C850000", -- 00000848
-		X"14400003", -- 0000084C
-		X"3C028010", -- 00000850
-		X"0BF00234", -- 00000854
-		X"34430002", -- 00000858
-		X"8C820010", -- 0000085C
-		X"00000000", -- 00000860
-		X"2442FFFF", -- 00000864
-		X"00021400", -- 00000868
-		X"00621024", -- 0000086C
-		X"00021080", -- 00000870
-		X"00A22021", -- 00000874
-		X"3C020060", -- 00000878
-		X"34420060", -- 0000087C
-		X"AC820000", -- 00000880
-		X"3C020001", -- 00000884
-		X"34420001", -- 00000888
-		X"AC820000", -- 0000088C
-		X"3C020080", -- 00000890
-		X"34430080", -- 00000894
-		X"8C860000", -- 00000898
-		X"00000000", -- 0000089C
-		X"00C31024", -- 000008A0
-		X"1443FFFC", -- 000008A4
-		X"3C020038", -- 000008A8
-		X"34420038", -- 000008AC
-		X"00C21024", -- 000008B0
-		X"10400003", -- 000008B4
-		X"00001821", -- 000008B8
-		X"3C029010", -- 000008BC
-		X"00C21825", -- 000008C0
-		X"3C0200FF", -- 000008C4
-		X"344200FF", -- 000008C8
-		X"AC820000", -- 000008CC
-		X"03E00008", -- 000008D0
-		X"00601021", -- 000008D4
-		X"8C820008", -- 000008D8
-		X"00A01821", -- 000008DC
-		X"00021082", -- 000008E0
-		X"00A2102B", -- 000008E4
-		X"8C850000", -- 000008E8
-		X"14400003", -- 000008EC
-		X"3C028010", -- 000008F0
-		X"0BF0025C", -- 000008F4
-		X"34430002", -- 000008F8
-		X"8C820010", -- 000008FC
-		X"00000000", -- 00000900
-		X"2442FFFF", -- 00000904
-		X"00021400", -- 00000908
-		X"00621024", -- 0000090C
-		X"00021080", -- 00000910
-		X"00A22021", -- 00000914
-		X"3C020060", -- 00000918
-		X"34420060", -- 0000091C
-		X"AC820000", -- 00000920
-		X"3C0200D0", -- 00000924
-		X"344200D0", -- 00000928
-		X"AC820000", -- 0000092C
-		X"3C020080", -- 00000930
-		X"34430080", -- 00000934
-		X"8C860000", -- 00000938
-		X"00000000", -- 0000093C
-		X"00C31024", -- 00000940
-		X"1443FFFC", -- 00000944
-		X"3C020038", -- 00000948
-		X"34420038", -- 0000094C
-		X"00C21024", -- 00000950
-		X"10400003", -- 00000954
-		X"00001821", -- 00000958
-		X"3C029010", -- 0000095C
-		X"00C21825", -- 00000960
-		X"3C0200FF", -- 00000964
-		X"344200FF", -- 00000968
-		X"AC820000", -- 0000096C
-		X"03E00008", -- 00000970
-		X"00601021", -- 00000974
-		X"8C820008", -- 00000978
-		X"8C840000", -- 0000097C
-		X"00021082", -- 00000980
-		X"00A2102B", -- 00000984
-		X"14400003", -- 00000988
-		X"3C028010", -- 0000098C
-		X"0BF0027C", -- 00000990
-		X"34430002", -- 00000994
-		X"00051080", -- 00000998
-		X"00822021", -- 0000099C
-		X"3C020040", -- 000009A0
-		X"34420040", -- 000009A4
-		X"AC820000", -- 000009A8
-		X"3C020080", -- 000009AC
-		X"AC860000", -- 000009B0
-		X"34430080", -- 000009B4
-		X"8C860000", -- 000009B8
-		X"00000000", -- 000009BC
-		X"00C31024", -- 000009C0
-		X"1443FFFC", -- 000009C4
-		X"3C02001A", -- 000009C8
-		X"3442001A", -- 000009CC
-		X"00C21024", -- 000009D0
-		X"10400003", -- 000009D4
-		X"00001821", -- 000009D8
-		X"3C029010", -- 000009DC
-		X"00C21825", -- 000009E0
-		X"3C0200FF", -- 000009E4
-		X"344200FF", -- 000009E8
-		X"AC820000", -- 000009EC
-		X"03E00008", -- 000009F0
-		X"00601021", -- 000009F4
-		X"8C820008", -- 000009F8
-		X"27BDFFE8", -- 000009FC
-		X"00021082", -- 00000A00
-		X"00A2102B", -- 00000A04
-		X"AFB40014", -- 00000A08
-		X"AFB30010", -- 00000A0C
-		X"AFB2000C", -- 00000A10
-		X"AFB10008", -- 00000A14
-		X"AFB00004", -- 00000A18
-		X"0080C021", -- 00000A1C
-		X"8C8E0000", -- 00000A20
-		X"14400004", -- 00000A24
-		X"00C0A021", -- 00000A28
-		X"3C028010", -- 00000A2C
-		X"0BF002E3", -- 00000A30
-		X"34440002", -- 00000A34
-		X"8C820010", -- 00000A38
-		X"00006821", -- 00000A3C
-		X"2442FFFF", -- 00000A40
-		X"0002CC00", -- 00000A44
-		X"3C0200E8", -- 00000A48
-		X"345300E8", -- 00000A4C
-		X"3C020080", -- 00000A50
-		X"344F0080", -- 00000A54
-		X"3C02001A", -- 00000A58
-		X"3446001A", -- 00000A5C
-		X"3C0200D0", -- 00000A60
-		X"345200D0", -- 00000A64
-		X"3C0200FF", -- 00000A68
-		X"345100FF", -- 00000A6C
-		X"0BF002E1", -- 00000A70
-		X"3C100001", -- 00000A74
-		X"01851023", -- 00000A78
-		X"00505021", -- 00000A7C
-		X"00EA102B", -- 00000A80
-		X"10400002", -- 00000A84
-		X"000C1080", -- 00000A88
-		X"00E05021", -- 00000A8C
-		X"0BF002D7", -- 00000A90
-		X"01C25821", -- 00000A94
-		X"AD730000", -- 00000A98
-		X"8D630000", -- 00000A9C
-		X"00000000", -- 00000AA0
-		X"006F1024", -- 00000AA4
-		X"144FFFFC", -- 00000AA8
-		X"00661024", -- 00000AAC
-		X"14400026", -- 00000AB0
-		X"3C029010", -- 00000AB4
-		X"8F020014", -- 00000AB8
-		X"00000000", -- 00000ABC
-		X"00021882", -- 00000AC0
-		X"006A102B", -- 00000AC4
-		X"10400002", -- 00000AC8
-		X"01404021", -- 00000ACC
-		X"00604021", -- 00000AD0
-		X"2503FFFF", -- 00000AD4
-		X"00031400", -- 00000AD8
-		X"00431025", -- 00000ADC
-		X"00052080", -- 00000AE0
-		X"000D1880", -- 00000AE4
-		X"02834821", -- 00000AE8
-		X"AD620000", -- 00000AEC
-		X"01C42021", -- 00000AF0
-		X"0BF002C3", -- 00000AF4
-		X"00001821", -- 00000AF8
-		X"8D220000", -- 00000AFC
-		X"25290004", -- 00000B00
-		X"AC820000", -- 00000B04
-		X"24840004", -- 00000B08
-		X"0068102B", -- 00000B0C
-		X"1440FFFA", -- 00000B10
-		X"24630001", -- 00000B14
-		X"01A86821", -- 00000B18
-		X"00A82821", -- 00000B1C
-		X"00E83823", -- 00000B20
-		X"AD720000", -- 00000B24
-		X"8D630000", -- 00000B28
-		X"00000000", -- 00000B2C
-		X"006F1024", -- 00000B30
-		X"144FFFFC", -- 00000B34
-		X"00661024", -- 00000B38
-		X"10400005", -- 00000B3C
-		X"01485023", -- 00000B40
-		X"01485021", -- 00000B44
-		X"3C029010", -- 00000B48
-		X"0BF002D9", -- 00000B4C
-		X"00622025", -- 00000B50
-		X"AD710000", -- 00000B54
-		X"00002021", -- 00000B58
-		X"1540FFCE", -- 00000B5C
-		X"00000000", -- 00000B60
-		X"04810007", -- 00000B64
-		X"000C1880", -- 00000B68
-		X"3C0200FF", -- 00000B6C
-		X"01C31821", -- 00000B70
-		X"344200FF", -- 00000B74
-		X"AC620000", -- 00000B78
-		X"0BF002E4", -- 00000B7C
-		X"00801021", -- 00000B80
-		X"14E0FFBC", -- 00000B84
-		X"00B96024", -- 00000B88
-		X"00801021", -- 00000B8C
-		X"8FB40014", -- 00000B90
-		X"8FB30010", -- 00000B94
-		X"8FB2000C", -- 00000B98
-		X"8FB10008", -- 00000B9C
-		X"8FB00004", -- 00000BA0
-		X"03E00008", -- 00000BA4
-		X"27BD0018", -- 00000BA8
-		X"27BDFFE0", -- 00000BAC
-		X"AFBF001C", -- 00000BB0
-		X"AC850000", -- 00000BB4
-		X"24820008", -- 00000BB8
-		X"0BF002F3", -- 00000BBC
-		X"24830020", -- 00000BC0
-		X"A0400000", -- 00000BC4
-		X"24420001", -- 00000BC8
-		X"1443FFFD", -- 00000BCC
-		X"00000000", -- 00000BD0
-		X"3C021234", -- 00000BD4
-		X"34425678", -- 00000BD8
-		X"00021E02", -- 00000BDC
-		X"AFA20010", -- 00000BE0
-		X"24020012", -- 00000BE4
-		X"14620003", -- 00000BE8
-		X"AC800004", -- 00000BEC
-		X"24020001", -- 00000BF0
-		X"AC820004", -- 00000BF4
-		X"0FF00185", -- 00000BF8
-		X"00000000", -- 00000BFC
-		X"8FBF001C", -- 00000C00
-		X"00000000", -- 00000C04
-		X"03E00008", -- 00000C08
-		X"27BD0020", -- 00000C0C
-		X"27BDFFD8", -- 00000C10
-		X"30C20003", -- 00000C14
-		X"AFB2001C", -- 00000C18
-		X"AFBF0024", -- 00000C1C
-		X"AFB30020", -- 00000C20
-		X"AFB10018", -- 00000C24
-		X"AFB00014", -- 00000C28
-		X"10400004", -- 00000C2C
-		X"00809021", -- 00000C30
-		X"00061082", -- 00000C34
-		X"24420001", -- 00000C38
-		X"00023080", -- 00000C3C
-		X"00C59821", -- 00000C40
-		X"0BF00324", -- 00000C44
-		X"00A08821", -- 00000C48
-		X"0FF001CA", -- 00000C4C
-		X"00000000", -- 00000C50
-		X"02402021", -- 00000C54
-		X"10400005", -- 00000C58
-		X"02002821", -- 00000C5C
-		X"0FF00236", -- 00000C60
-		X"00000000", -- 00000C64
-		X"04400011", -- 00000C68
-		X"00401821", -- 00000C6C
-		X"02002821", -- 00000C70
-		X"0FF001E6", -- 00000C74
-		X"02402021", -- 00000C78
-		X"0440000C", -- 00000C7C
-		X"00401821", -- 00000C80
-		X"8E42000C", -- 00000C84
-		X"00000000", -- 00000C88
-		X"02228821", -- 00000C8C
-		X"001117C3", -- 00000C90
-		X"00021782", -- 00000C94
-		X"00511021", -- 00000C98
-		X"00028083", -- 00000C9C
-		X"0233102B", -- 00000CA0
-		X"02402021", -- 00000CA4
-		X"1440FFE8", -- 00000CA8
-		X"02002821", -- 00000CAC
-		X"8FBF0024", -- 00000CB0
-		X"00601021", -- 00000CB4
-		X"8FB30020", -- 00000CB8
-		X"8FB2001C", -- 00000CBC
-		X"8FB10018", -- 00000CC0
-		X"8FB00014", -- 00000CC4
-		X"03E00008", -- 00000CC8
-		X"27BD0028", -- 00000CCC
-		X"30E20003", -- 00000CD0
-		X"10400003", -- 00000CD4
-		X"00071082", -- 00000CD8
-		X"24420001", -- 00000CDC
-		X"00023880", -- 00000CE0
-		X"00052882", -- 00000CE4
-		X"0BF0027E", -- 00000CE8
-		X"00073882", -- 00000CEC
-		X"8C820000", -- 00000CF0
-		X"00002021", -- 00000CF4
-		X"0BF00347", -- 00000CF8
-		X"00454021", -- 00000CFC
-		X"90630000", -- 00000D00
-		X"90A20000", -- 00000D04
-		X"00000000", -- 00000D08
-		X"10620003", -- 00000D0C
-		X"3C028010", -- 00000D10
-		X"03E00008", -- 00000D14
-		X"34420003", -- 00000D18
-		X"0087102B", -- 00000D1C
-		X"01041821", -- 00000D20
-		X"00C42821", -- 00000D24
-		X"1440FFF5", -- 00000D28
-		X"24840001", -- 00000D2C
-		X"03E00008", -- 00000D30
-		X"00000000", -- 00000D34
-		X"8C82000C", -- 00000D38
-		X"00000000", -- 00000D3C
-		X"14400002", -- 00000D40
-		X"00A2001B", -- 00000D44
-		X"0007000D", -- 00000D48
-		X"00001010", -- 00000D4C
-		X"0002102B", -- 00000D50
-		X"00002812", -- 00000D54
-		X"03E00008", -- 00000D58
-		X"00A21021", -- 00000D5C
-		X"8C830010", -- 00000D60
-		X"00000000", -- 00000D64
-		X"00A3102B", -- 00000D68
-		X"14400002", -- 00000D6C
-		X"00000000", -- 00000D70
-		X"2465FFFF", -- 00000D74
-		X"8C82000C", -- 00000D78
-		X"00000000", -- 00000D7C
-		X"00A20018", -- 00000D80
-		X"00001012", -- 00000D84
-		X"03E00008", -- 00000D88
-		X"00000000", -- 00000D8C
-		X"27BDFFE8", -- 00000D90
-		X"AFBF0014", -- 00000D94
-		X"AFB00010", -- 00000D98
-		X"0FF0034E", -- 00000D9C
-		X"00808021", -- 00000DA0
-		X"8E03000C", -- 00000DA4
-		X"8FBF0014", -- 00000DA8
-		X"00430018", -- 00000DAC
-		X"8FB00010", -- 00000DB0
-		X"00001012", -- 00000DB4
-		X"03E00008", -- 00000DB8
-		X"27BD0018", -- 00000DBC
-		X"90830000", -- 00000DC0
-		X"00000000", -- 00000DC4
-		X"2C620041", -- 00000DC8
-		X"14400002", -- 00000DCC
-		X"2462FFD0", -- 00000DD0
-		X"2462FFC9", -- 00000DD4
-		X"90840001", -- 00000DD8
-		X"304200FF", -- 00000DDC
-		X"304300FF", -- 00000DE0
-		X"2C820041", -- 00000DE4
-		X"14400003", -- 00000DE8
-		X"00000000", -- 00000DEC
-		X"0BF0037F", -- 00000DF0
-		X"2482FFC9", -- 00000DF4
-		X"2482FFD0", -- 00000DF8
-		X"304400FF", -- 00000DFC
-		X"00031100", -- 00000E00
-		X"00821025", -- 00000E04
-		X"03E00008", -- 00000E08
-		X"304200FF", -- 00000E0C
-		X"10C00094", -- 00000E10
-		X"00805021", -- 00000E14
-		X"24020003", -- 00000E18
-		X"AC820008", -- 00000E1C
-		X"90A40001", -- 00000E20
-		X"00000000", -- 00000E24
-		X"2482FFCF", -- 00000E28
-		X"304200FF", -- 00000E2C
-		X"2C420003", -- 00000E30
-		X"10400005", -- 00000E34
-		X"2482FFC9", -- 00000E38
-		X"24020002", -- 00000E3C
-		X"AD420008", -- 00000E40
-		X"0BF003A1", -- 00000E44
-		X"2489FFD1", -- 00000E48
-		X"304200FF", -- 00000E4C
-		X"2C420003", -- 00000E50
-		X"10400006", -- 00000E54
-		X"24020030", -- 00000E58
-		X"2402003B", -- 00000E5C
-		X"00444823", -- 00000E60
-		X"24020004", -- 00000E64
-		X"0BF003A1", -- 00000E68
-		X"AD420008", -- 00000E6C
-		X"14820004", -- 00000E70
-		X"00004821", -- 00000E74
-		X"24020001", -- 00000E78
-		X"AD420008", -- 00000E7C
-		X"24090002", -- 00000E80
-		X"90A30002", -- 00000E84
-		X"00000000", -- 00000E88
-		X"2C620041", -- 00000E8C
-		X"10400003", -- 00000E90
-		X"24A40002", -- 00000E94
-		X"0BF003A9", -- 00000E98
-		X"2462FFD0", -- 00000E9C
-		X"2462FFC9", -- 00000EA0
-		X"90830001", -- 00000EA4
-		X"304200FF", -- 00000EA8
-		X"304400FF", -- 00000EAC
-		X"2C620041", -- 00000EB0
-		X"10400002", -- 00000EB4
-		X"2462FFC9", -- 00000EB8
-		X"2462FFD0", -- 00000EBC
-		X"304300FF", -- 00000EC0
-		X"00041100", -- 00000EC4
-		X"00621025", -- 00000EC8
-		X"304200FF", -- 00000ECC
-		X"AD420004", -- 00000ED0
-		X"AD400000", -- 00000ED4
-		X"00405821", -- 00000ED8
-		X"00A03021", -- 00000EDC
-		X"0BF003D5", -- 00000EE0
-		X"00003821", -- 00000EE4
-		X"90C20004", -- 00000EE8
-		X"00000000", -- 00000EEC
-		X"2443FFC9", -- 00000EF0
-		X"2444FFD0", -- 00000EF4
-		X"2C420041", -- 00000EF8
-		X"10400002", -- 00000EFC
-		X"306300FF", -- 00000F00
-		X"308300FF", -- 00000F04
-		X"90C20005", -- 00000F08
-		X"306800FF", -- 00000F0C
-		X"2444FFC9", -- 00000F10
-		X"2443FFD0", -- 00000F14
-		X"2C420041", -- 00000F18
-		X"10400002", -- 00000F1C
-		X"308400FF", -- 00000F20
-		X"306400FF", -- 00000F24
-		X"8D430000", -- 00000F28
-		X"00081100", -- 00000F2C
-		X"00821025", -- 00000F30
-		X"304200FF", -- 00000F34
-		X"00031A00", -- 00000F38
-		X"004B2021", -- 00000F3C
-		X"00431025", -- 00000F40
-		X"AD420000", -- 00000F44
-		X"308B00FF", -- 00000F48
-		X"24E70001", -- 00000F4C
-		X"24C60002", -- 00000F50
-		X"00E9102A", -- 00000F54
-		X"1440FFE3", -- 00000F58
-		X"25220002", -- 00000F5C
-		X"8D440004", -- 00000F60
-		X"00021040", -- 00000F64
-		X"00091827", -- 00000F68
-		X"00832021", -- 00000F6C
-		X"00A21021", -- 00000F70
-		X"AD440004", -- 00000F74
-		X"AD42000C", -- 00000F78
-		X"0BF003F9", -- 00000F7C
-		X"00003021", -- 00000F80
-		X"90E20000", -- 00000F84
-		X"00000000", -- 00000F88
-		X"2444FFC9", -- 00000F8C
-		X"2445FFD0", -- 00000F90
-		X"2C420041", -- 00000F94
-		X"10400002", -- 00000F98
-		X"308400FF", -- 00000F9C
-		X"30A400FF", -- 00000FA0
-		X"90E20001", -- 00000FA4
-		X"308700FF", -- 00000FA8
-		X"2445FFC9", -- 00000FAC
-		X"2444FFD0", -- 00000FB0
-		X"2C420041", -- 00000FB4
-		X"14400002", -- 00000FB8
-		X"308400FF", -- 00000FBC
-		X"30A400FF", -- 00000FC0
-		X"00071100", -- 00000FC4
-		X"00821025", -- 00000FC8
-		X"304200FF", -- 00000FCC
-		X"00661821", -- 00000FD0
-		X"004B2021", -- 00000FD4
-		X"A0620000", -- 00000FD8
-		X"308B00FF", -- 00000FDC
-		X"24C60001", -- 00000FE0
-		X"8D420004", -- 00000FE4
-		X"8D43000C", -- 00000FE8
-		X"00062040", -- 00000FEC
-		X"00C2102A", -- 00000FF0
-		X"1440FFE3", -- 00000FF4
-		X"00643821", -- 00000FF8
-		X"90E40000", -- 00000FFC
-		X"00000000", -- 00001000
-		X"2C820041", -- 00001004
-		X"10400003", -- 00001008
-		X"00E01821", -- 0000100C
-		X"0BF00407", -- 00001010
-		X"2482FFD0", -- 00001014
-		X"2482FFC9", -- 00001018
-		X"90630001", -- 0000101C
-		X"304200FF", -- 00001020
-		X"304400FF", -- 00001024
-		X"2C620041", -- 00001028
-		X"10400002", -- 0000102C
-		X"2462FFC9", -- 00001030
-		X"2462FFD0", -- 00001034
-		X"304200FF", -- 00001038
-		X"00041900", -- 0000103C
-		X"00431825", -- 00001040
-		X"000B1027", -- 00001044
-		X"304200FF", -- 00001048
-		X"306300FF", -- 0000104C
-		X"14430004", -- 00001050
-		X"00000000", -- 00001054
-		X"8D420008", -- 00001058
-		X"03E00008", -- 0000105C
-		X"00000000", -- 00001060
-		X"03E00008", -- 00001064
-		X"00001021", -- 00001068
-		X"00800008", -- 0000106C
-		X"00000000", -- 00001070
-		X"03E00008", -- 00001074
-		X"00000000", -- 00001078
-		X"3C1A1000", -- 0000107C
-		X"409A6000", -- 00001080
-		X"00800008", -- 00001084
-		X"42000010", -- 00001088
-		X"03E00008", -- 0000108C
-		X"00000000", -- 00001090
-		X"401A6000", -- 00001094
-		X"3C1BFFBF", -- 00001098
-		X"377BFFFF", -- 0000109C
-		X"035BD024", -- 000010A0
-		X"3C1B0200", -- 000010A4
-		X"035BD025", -- 000010A8
-		X"409A6000", -- 000010AC
-		X"00800008", -- 000010B0
-		X"42000010", -- 000010B4
-		X"03E00008", -- 000010B8
-		X"00000000", -- 000010BC
-		X"27BDFFD8", -- 000010C0
-		X"AFB30020", -- 000010C4
-		X"AFB10018", -- 000010C8
-		X"AFB00014", -- 000010CC
-		X"AFBF0024", -- 000010D0
-		X"AFB2001C", -- 000010D4
-		X"00809821", -- 000010D8
-		X"24110073", -- 000010DC
-		X"24100053", -- 000010E0
-		X"0FF00081", -- 000010E4
-		X"00000000", -- 000010E8
-		X"14510005", -- 000010EC
-		X"00000000", -- 000010F0
-		X"00008021", -- 000010F4
-		X"2412000A", -- 000010F8
-		X"0BF00449", -- 000010FC
-		X"2411000D", -- 00001100
-		X"1450FFF7", -- 00001104
-		X"00000000", -- 00001108
-		X"0BF0043E", -- 0000110C
-		X"00008021", -- 00001110
-		X"0FF00081", -- 00001114
-		X"A0620000", -- 00001118
-		X"10510003", -- 0000111C
-		X"26100001", -- 00001120
-		X"1452FFFB", -- 00001124
-		X"02701821", -- 00001128
-		X"8FBF0024", -- 0000112C
-		X"02001021", -- 00001130
-		X"8FB30020", -- 00001134
-		X"8FB2001C", -- 00001138
-		X"8FB10018", -- 0000113C
-		X"8FB00014", -- 00001140
-		X"03E00008", -- 00001144
-		X"27BD0028", -- 00001148
-		X"27BDFD98", -- 0000114C
-		X"27A40140", -- 00001150
-		X"00002821", -- 00001154
-		X"24060100", -- 00001158
-		X"AFB20248", -- 0000115C
-		X"AFB10244", -- 00001160
-		X"AFB00240", -- 00001164
-		X"3C11A000", -- 00001168
-		X"AFBF0264", -- 0000116C
-		X"AFBE0260", -- 00001170
-		X"AFB7025C", -- 00001174
-		X"AFB60258", -- 00001178
-		X"AFB50254", -- 0000117C
-		X"AFB40250", -- 00001180
-		X"0FF0056A", -- 00001184
-		X"AFB3024C", -- 00001188
-		X"3C036000", -- 0000118C
-		X"36220004", -- 00001190
-		X"3463B1FF", -- 00001194
-		X"AC430000", -- 00001198
-		X"3C022000", -- 0000119C
-		X"27B20020", -- 000011A0
-		X"34421000", -- 000011A4
-		X"AE220000", -- 000011A8
-		X"02402021", -- 000011AC
-		X"3C05A400", -- 000011B0
-		X"8E300000", -- 000011B4
-		X"0FF002EB", -- 000011B8
-		X"00000000", -- 000011BC
-		X"04410004", -- 000011C0
-		X"00102C02", -- 000011C4
-		X"3C04BFC0", -- 000011C8
-		X"0BF00493", -- 000011CC
-		X"248416A0", -- 000011D0
-		X"02402021", -- 000011D4
-		X"0FF00358", -- 000011D8
-		X"30A5007F", -- 000011DC
-		X"00409021", -- 000011E0
-		X"8E220000", -- 000011E4
-		X"3C030800", -- 000011E8
-		X"00431024", -- 000011EC
-		X"14400044", -- 000011F0
-		X"3C11BFC0", -- 000011F4
-		X"0FF000B0", -- 000011F8
-		X"26241754", -- 000011FC
-		X"3C02A400", -- 00001200
-		X"02428021", -- 00001204
-		X"8E030000", -- 00001208
-		X"3C023149", -- 0000120C
-		X"3442464A", -- 00001210
-		X"10620011", -- 00001214
-		X"3C024A46", -- 00001218
-		X"34424931", -- 0000121C
-		X"1062000E", -- 00001220
-		X"00000000", -- 00001224
-		X"0FF000B0", -- 00001228
-		X"26241754", -- 0000122C
-		X"3C04BFC0", -- 00001230
-		X"0FF000B0", -- 00001234
-		X"248416C8", -- 00001238
-		X"0FF000E8", -- 0000123C
-		X"02402021", -- 00001240
-		X"3C04BFC0", -- 00001244
-		X"248416E0", -- 00001248
-		X"0FF000B0", -- 0000124C
-		X"00000000", -- 00001250
-		X"0BF0055E", -- 00001254
-		X"24020001", -- 00001258
-		X"3C04BFC0", -- 0000125C
-		X"0FF000B0", -- 00001260
-		X"248416EC", -- 00001264
-		X"0FF000E8", -- 00001268
-		X"02402021", -- 0000126C
-		X"3C04BFC0", -- 00001270
-		X"0FF000B0", -- 00001274
-		X"24841710", -- 00001278
-		X"8E02000C", -- 0000127C
-		X"8E110004", -- 00001280
-		X"00024082", -- 00001284
-		X"8E070008", -- 00001288
-		X"00002021", -- 0000128C
-		X"0BF004A9", -- 00001290
-		X"00001821", -- 00001294
-		X"8CC20000", -- 00001298
-		X"00000000", -- 0000129C
-		X"ACA20000", -- 000012A0
-		X"0088102B", -- 000012A4
-		X"00673021", -- 000012A8
-		X"00712821", -- 000012AC
-		X"24840001", -- 000012B0
-		X"1440FFF8", -- 000012B4
-		X"24630004", -- 000012B8
-		X"3C04BFC0", -- 000012BC
-		X"0FF000B0", -- 000012C0
-		X"24841718", -- 000012C4
-		X"3C04BFC0", -- 000012C8
-		X"0FF000B0", -- 000012CC
-		X"24841720", -- 000012D0
-		X"8E040004", -- 000012D4
-		X"0FF000E8", -- 000012D8
-		X"00000000", -- 000012DC
-		X"3C04BFC0", -- 000012E0
-		X"0FF000B0", -- 000012E4
-		X"24841754", -- 000012E8
-		X"3C1A1000", -- 000012EC
-		X"409A6000", -- 000012F0
-		X"02200008", -- 000012F4
-		X"42000010", -- 000012F8
-		X"0BF0055E", -- 000012FC
-		X"00001021", -- 00001300
-		X"0FF000B0", -- 00001304
-		X"26241754", -- 00001308
-		X"3C04BFC0", -- 0000130C
-		X"0FF000B0", -- 00001310
-		X"2484172C", -- 00001314
-		X"3C024000", -- 00001318
-		X"3C034010", -- 0000131C
-		X"AC400000", -- 00001320
-		X"24420004", -- 00001324
-		X"1443FFFD", -- 00001328
-		X"00009821", -- 0000132C
-		X"3C02BFC0", -- 00001330
-		X"245516C4", -- 00001334
-		X"3C02BFC0", -- 00001338
-		X"24561718", -- 0000133C
-		X"3C02BFC0", -- 00001340
-		X"245E17CC", -- 00001344
-		X"3C02BFC0", -- 00001348
-		X"245717EC", -- 0000134C
-		X"3C04BFC0", -- 00001350
-		X"0FF000B0", -- 00001354
-		X"2484174C", -- 00001358
-		X"3C14BFC0", -- 0000135C
-		X"27B00040", -- 00001360
-		X"0FF00430", -- 00001364
-		X"02002021", -- 00001368
-		X"00403021", -- 0000136C
-		X"02002821", -- 00001370
-		X"27A40010", -- 00001374
-		X"0FF00384", -- 00001378
-		X"00408821", -- 0000137C
-		X"00401821", -- 00001380
-		X"24020002", -- 00001384
-		X"10620005", -- 00001388
-		X"24020004", -- 0000138C
-		X"1462FFEF", -- 00001390
-		X"00000000", -- 00001394
-		X"0BF004FD", -- 00001398
-		X"3C04BFC0", -- 0000139C
-		X"8FA50010", -- 000013A0
-		X"8FA60014", -- 000013A4
-		X"0BF004F2", -- 000013A8
-		X"00001821", -- 000013AC
-		X"8FA2001C", -- 000013B0
-		X"00000000", -- 000013B4
-		X"00431021", -- 000013B8
-		X"90420000", -- 000013BC
-		X"24630001", -- 000013C0
-		X"A0820000", -- 000013C4
-		X"8FA20014", -- 000013C8
-		X"00000000", -- 000013CC
-		X"0062102B", -- 000013D0
-		X"1440FFF6", -- 000013D4
-		X"00652021", -- 000013D8
-		X"00C51821", -- 000013DC
-		X"0263102B", -- 000013E0
-		X"10400060", -- 000013E4
-		X"02208021", -- 000013E8
-		X"0BF0055A", -- 000013EC
-		X"00609821", -- 000013F0
-		X"0FF000B0", -- 000013F4
-		X"24841750", -- 000013F8
-		X"8FA60010", -- 000013FC
-		X"26470100", -- 00001400
-		X"02661823", -- 00001404
-		X"27B10020", -- 00001408
-		X"3C024A46", -- 0000140C
-		X"00E32821", -- 00001410
-		X"02202021", -- 00001414
-		X"34424931", -- 00001418
-		X"AFA60144", -- 0000141C
-		X"AFA3014C", -- 00001420
-		X"AFA70148", -- 00001424
-		X"0FF00364", -- 00001428
-		X"AFA20140", -- 0000142C
-		X"3C04BFC0", -- 00001430
-		X"24841758", -- 00001434
-		X"0FF000B0", -- 00001438
-		X"AFA20150", -- 0000143C
-		X"8FA4014C", -- 00001440
-		X"0FF000E8", -- 00001444
-		X"00000000", -- 00001448
-		X"0FF000B0", -- 0000144C
-		X"02A02021", -- 00001450
-		X"3C04BFC0", -- 00001454
-		X"0FF000B0", -- 00001458
-		X"24841774", -- 0000145C
-		X"0FF000E8", -- 00001460
-		X"02402021", -- 00001464
-		X"0FF000B0", -- 00001468
-		X"02A02021", -- 0000146C
-		X"3C04BFC0", -- 00001470
-		X"0FF000B0", -- 00001474
-		X"24841790", -- 00001478
-		X"8FA40150", -- 0000147C
-		X"0FF000E8", -- 00001480
-		X"00000000", -- 00001484
-		X"0FF000B0", -- 00001488
-		X"02A02021", -- 0000148C
-		X"3C04BFC0", -- 00001490
-		X"0FF000B0", -- 00001494
-		X"248417AC", -- 00001498
-		X"8FA6014C", -- 0000149C
-		X"02202021", -- 000014A0
-		X"24C60100", -- 000014A4
-		X"0FF00304", -- 000014A8
-		X"02402821", -- 000014AC
-		X"0440001F", -- 000014B0
-		X"00408021", -- 000014B4
-		X"0FF000B0", -- 000014B8
-		X"02C02021", -- 000014BC
-		X"0FF000B0", -- 000014C0
-		X"03C02021", -- 000014C4
-		X"02202021", -- 000014C8
-		X"02402821", -- 000014CC
-		X"27A60140", -- 000014D0
-		X"0FF00334", -- 000014D4
-		X"24070100", -- 000014D8
-		X"04400014", -- 000014DC
-		X"00408021", -- 000014E0
-		X"8FA50148", -- 000014E4
-		X"8FA60144", -- 000014E8
-		X"8FA7014C", -- 000014EC
-		X"0FF00334", -- 000014F0
-		X"02202021", -- 000014F4
-		X"0440000D", -- 000014F8
-		X"00408021", -- 000014FC
-		X"0FF000B0", -- 00001500
-		X"02C02021", -- 00001504
-		X"3C04BFC0", -- 00001508
-		X"0FF000B0", -- 0000150C
-		X"248417DC", -- 00001510
-		X"8FA50148", -- 00001514
-		X"8FA60144", -- 00001518
-		X"8FA7014C", -- 0000151C
-		X"0FF0033C", -- 00001520
-		X"02202021", -- 00001524
-		X"0441000A", -- 00001528
-		X"00408021", -- 0000152C
-		X"0FF000B0", -- 00001530
-		X"268417BC", -- 00001534
-		X"0FF000E8", -- 00001538
-		X"02002021", -- 0000153C
-		X"3C04BFC0", -- 00001540
-		X"0FF000B0", -- 00001544
-		X"248417C8", -- 00001548
-		X"0BF0055A", -- 0000154C
-		X"00000000", -- 00001550
-		X"0FF000B0", -- 00001554
-		X"02E02021", -- 00001558
-		X"3C02BFC0", -- 0000155C
-		X"00400008", -- 00001560
-		X"00000000", -- 00001564
-		X"0601FF7E", -- 00001568
-		X"27B00040", -- 0000156C
-		X"0BF004D5", -- 00001570
-		X"3C04BFC0", -- 00001574
-		X"8FBF0264", -- 00001578
-		X"8FBE0260", -- 0000157C
-		X"8FB7025C", -- 00001580
-		X"8FB60258", -- 00001584
-		X"8FB50254", -- 00001588
-		X"8FB40250", -- 0000158C
-		X"8FB3024C", -- 00001590
-		X"8FB20248", -- 00001594
-		X"8FB10244", -- 00001598
-		X"8FB00240", -- 0000159C
-		X"03E00008", -- 000015A0
-		X"27BD0268", -- 000015A4
-		X"2CC20010", -- 000015A8
-		X"00804821", -- 000015AC
-		X"1440002D", -- 000015B0
-		X"00804021", -- 000015B4
-		X"30870003", -- 000015B8
-		X"10E0000E", -- 000015BC
-		X"24820004", -- 000015C0
-		X"00052600", -- 000015C4
-		X"00471023", -- 000015C8
-		X"00042603", -- 000015CC
-		X"01201821", -- 000015D0
-		X"A0640000", -- 000015D4
-		X"24630001", -- 000015D8
-		X"1462FFFD", -- 000015DC
-		X"00000000", -- 000015E0
-		X"00071027", -- 000015E4
-		X"24C3FFFB", -- 000015E8
-		X"24440005", -- 000015EC
-		X"00623023", -- 000015F0
-		X"01244021", -- 000015F4
-		X"30A500FF", -- 000015F8
-		X"01003821", -- 000015FC
-		X"10A00005", -- 00001600
-		X"00A01821", -- 00001604
-		X"00051200", -- 00001608
-		X"00451025", -- 0000160C
-		X"00021C00", -- 00001610
-		X"00621825", -- 00001614
-		X"000610C2", -- 00001618
-		X"1040001C", -- 0000161C
-		X"30C60007", -- 00001620
-		X"01002021", -- 00001624
-		X"00403821", -- 00001628
-		X"24E7FFFF", -- 0000162C
-		X"AC830000", -- 00001630
-		X"AC830004", -- 00001634
-		X"14E0FFFC", -- 00001638
-		X"24840008", -- 0000163C
-		X"000210C0", -- 00001640
-		X"01023821", -- 00001644
-		X"00E02021", -- 00001648
-		X"2CC20004", -- 0000164C
-		X"14400005", -- 00001650
-		X"00804021", -- 00001654
-		X"ACE30000", -- 00001658
-		X"24E40004", -- 0000165C
-		X"24C6FFFC", -- 00001660
-		X"00804021", -- 00001664
-		X"10C00007", -- 00001668
-		X"00000000", -- 0000166C
-		X"00051600", -- 00001670
-		X"00021603", -- 00001674
-		X"24C6FFFF", -- 00001678
-		X"A1020000", -- 0000167C
-		X"14C0FFFD", -- 00001680
-		X"25080001", -- 00001684
-		X"03E00008", -- 00001688
-		X"01201021", -- 0000168C
-		X"0BF00593", -- 00001690
-		X"01002021", -- 00001694
-		X"3A200000", -- 00001698
-		X"20202000", -- 0000169C
-		X"43616E6E", -- 000016A0
-		X"6F742066", -- 000016A4
-		X"696E6420", -- 000016A8
-		X"666C6173", -- 000016AC
-		X"68206465", -- 000016B0
-		X"76696365", -- 000016B4
-		X"2E204578", -- 000016B8
-		X"6974206E", -- 000016BC
-		X"6F77210A", -- 000016C0
-		X"0A000000", -- 000016C4
-		X"496E7661", -- 000016C8
-		X"6C696420", -- 000016CC
-		X"696D6167", -- 000016D0
-		X"6520666F", -- 000016D4
-		X"756E6420", -- 000016D8
-		X"61742000", -- 000016DC
-		X"2E204162", -- 000016E0
-		X"6F72742E", -- 000016E4
-		X"0A000000", -- 000016E8
-		X"426F6F74", -- 000016EC
-		X"696E6720", -- 000016F0
-		X"6170706C", -- 000016F4
-		X"69636174", -- 000016F8
-		X"696F6E20", -- 000016FC
-		X"66726F6D", -- 00001700
-		X"20666C61", -- 00001704
-		X"73682028", -- 00001708
-		X"00000000", -- 0000170C
-		X"292E2E2E", -- 00001710
-		X"00000000", -- 00001714
-		X"646F6E65", -- 00001718
-		X"0A000000", -- 0000171C
-		X"45786563", -- 00001720
-		X"75746520", -- 00001724
-		X"61742000", -- 00001728
-		X"52656164", -- 0000172C
-		X"696E6720", -- 00001730
-		X"4845582D", -- 00001734
-		X"5265636F", -- 00001738
-		X"72642066", -- 0000173C
-		X"726F6D20", -- 00001740
-		X"55415254", -- 00001744
-		X"2E2E0000", -- 00001748
-		X"2E000000", -- 0000174C
-		X"646F6E65", -- 00001750
-		X"0A0A0000", -- 00001754
-		X"53697A65", -- 00001758
-		X"206F6620", -- 0000175C
-		X"6170706C", -- 00001760
-		X"69636174", -- 00001764
-		X"696F6E20", -- 00001768
-		X"2020203A", -- 0000176C
-		X"20000000", -- 00001770
-		X"50726F67", -- 00001774
-		X"72616D6D", -- 00001778
-		X"696E6720", -- 0000177C
-		X"666C6173", -- 00001780
-		X"68206174", -- 00001784
-		X"2020203A", -- 00001788
-		X"20000000", -- 0000178C
-		X"4E657874", -- 00001790
-		X"20667265", -- 00001794
-		X"6520666C", -- 00001798
-		X"61736820", -- 0000179C
-		X"6F666673", -- 000017A0
-		X"6574203A", -- 000017A4
-		X"20000000", -- 000017A8
-		X"466C6173", -- 000017AC
-		X"68206572", -- 000017B0
-		X"6173652E", -- 000017B4
-		X"2E2E0000", -- 000017B8
-		X"6661696C", -- 000017BC
-		X"65642028", -- 000017C0
-		X"00000000", -- 000017C4
-		X"290A0000", -- 000017C8
-		X"466C6173", -- 000017CC
-		X"68207772", -- 000017D0
-		X"6974652E", -- 000017D4
-		X"2E2E0000", -- 000017D8
-		X"466C6173", -- 000017DC
-		X"68207665", -- 000017E0
-		X"72696679", -- 000017E4
-		X"2E2E2E00", -- 000017E8
-		X"70617373", -- 000017EC
-		X"65640A00", -- 000017F0
-		X"00000000", -- 000017F4
-		X"00000000", -- 000017F8
-		X"00000000", -- 000017FC
-		X"00000000", -- 00001800
-		X"00000000", -- 00001804
-		X"00000000", -- 00001808
-		X"00000000", -- 0000180C
-		X"00000000", -- 00001810
-		X"00000000", -- 00001814
-		X"00000000", -- 00001818
-		X"00000000", -- 0000181C
-		X"00000000", -- 00001820
-		X"00000000", -- 00001824
-		X"00000000", -- 00001828
-		X"00000000", -- 0000182C
-		X"00000000", -- 00001830
-		X"00000000", -- 00001834
-		X"00000000", -- 00001838
-		X"00000000", -- 0000183C
-		X"00000000", -- 00001840
-		X"00000000", -- 00001844
-		X"00000000", -- 00001848
-		X"00000000", -- 0000184C
-		X"00000000", -- 00001850
-		X"00000000", -- 00001854
-		X"00000000", -- 00001858
-		X"00000000", -- 0000185C
-		X"00000000", -- 00001860
-		X"00000000", -- 00001864
-		X"00000000", -- 00001868
-		X"00000000", -- 0000186C
-		X"00000000", -- 00001870
-		X"00000000", -- 00001874
-		X"00000000", -- 00001878
-		X"00000000", -- 0000187C
-		X"00000000", -- 00001880
-		X"00000000", -- 00001884
-		X"00000000", -- 00001888
-		X"00000000", -- 0000188C
-		X"00000000", -- 00001890
-		X"00000000", -- 00001894
-		X"00000000", -- 00001898
-		X"00000000", -- 0000189C
-		X"00000000", -- 000018A0
-		X"00000000", -- 000018A4
-		X"00000000", -- 000018A8
-		X"00000000", -- 000018AC
-		X"00000000", -- 000018B0
-		X"00000000", -- 000018B4
-		X"00000000", -- 000018B8
-		X"00000000", -- 000018BC
-		X"00000000", -- 000018C0
-		X"00000000", -- 000018C4
-		X"00000000", -- 000018C8
-		X"00000000", -- 000018CC
-		X"00000000", -- 000018D0
-		X"00000000", -- 000018D4
-		X"00000000", -- 000018D8
-		X"00000000", -- 000018DC
-		X"00000000", -- 000018E0
-		X"00000000", -- 000018E4
-		X"00000000", -- 000018E8
-		X"00000000", -- 000018EC
-		X"00000000", -- 000018F0
-		X"00000000", -- 000018F4
-		X"00000000", -- 000018F8
-		X"00000000", -- 000018FC
-		X"00000000", -- 00001900
-		X"00000000", -- 00001904
-		X"00000000", -- 00001908
-		X"00000000", -- 0000190C
-		X"00000000", -- 00001910
-		X"00000000", -- 00001914
-		X"00000000", -- 00001918
-		X"00000000", -- 0000191C
-		X"00000000", -- 00001920
-		X"00000000", -- 00001924
-		X"00000000", -- 00001928
-		X"00000000", -- 0000192C
-		X"00000000", -- 00001930
-		X"00000000", -- 00001934
-		X"00000000", -- 00001938
-		X"00000000", -- 0000193C
-		X"00000000", -- 00001940
-		X"00000000", -- 00001944
-		X"00000000", -- 00001948
-		X"00000000", -- 0000194C
-		X"00000000", -- 00001950
-		X"00000000", -- 00001954
-		X"00000000", -- 00001958
-		X"00000000", -- 0000195C
-		X"00000000", -- 00001960
-		X"00000000", -- 00001964
-		X"00000000", -- 00001968
-		X"00000000", -- 0000196C
-		X"00000000", -- 00001970
-		X"00000000", -- 00001974
-		X"00000000", -- 00001978
-		X"00000000", -- 0000197C
-		X"00000000", -- 00001980
-		X"00000000", -- 00001984
-		X"00000000", -- 00001988
-		X"00000000", -- 0000198C
-		X"00000000", -- 00001990
-		X"00000000", -- 00001994
-		X"00000000", -- 00001998
-		X"00000000", -- 0000199C
-		X"00000000", -- 000019A0
-		X"00000000", -- 000019A4
-		X"00000000", -- 000019A8
-		X"00000000", -- 000019AC
-		X"00000000", -- 000019B0
-		X"00000000", -- 000019B4
-		X"00000000", -- 000019B8
-		X"00000000", -- 000019BC
-		X"00000000", -- 000019C0
-		X"00000000", -- 000019C4
-		X"00000000", -- 000019C8
-		X"00000000", -- 000019CC
-		X"00000000", -- 000019D0
-		X"00000000", -- 000019D4
-		X"00000000", -- 000019D8
-		X"00000000", -- 000019DC
-		X"00000000", -- 000019E0
-		X"00000000", -- 000019E4
-		X"00000000", -- 000019E8
-		X"00000000", -- 000019EC
-		X"00000000", -- 000019F0
-		X"00000000", -- 000019F4
-		X"00000000", -- 000019F8
-		X"00000000", -- 000019FC
-		X"00000000", -- 00001A00
-		X"00000000", -- 00001A04
-		X"00000000", -- 00001A08
-		X"00000000", -- 00001A0C
-		X"00000000", -- 00001A10
-		X"00000000", -- 00001A14
-		X"00000000", -- 00001A18
-		X"00000000", -- 00001A1C
-		X"00000000", -- 00001A20
-		X"00000000", -- 00001A24
-		X"00000000", -- 00001A28
-		X"00000000", -- 00001A2C
-		X"00000000", -- 00001A30
-		X"00000000", -- 00001A34
-		X"00000000", -- 00001A38
-		X"00000000", -- 00001A3C
-		X"00000000", -- 00001A40
-		X"00000000", -- 00001A44
-		X"00000000", -- 00001A48
-		X"00000000", -- 00001A4C
-		X"00000000", -- 00001A50
-		X"00000000", -- 00001A54
-		X"00000000", -- 00001A58
-		X"00000000", -- 00001A5C
-		X"00000000", -- 00001A60
-		X"00000000", -- 00001A64
-		X"00000000", -- 00001A68
-		X"00000000", -- 00001A6C
-		X"00000000", -- 00001A70
-		X"00000000", -- 00001A74
-		X"00000000", -- 00001A78
-		X"00000000", -- 00001A7C
-		X"00000000", -- 00001A80
-		X"00000000", -- 00001A84
-		X"00000000", -- 00001A88
-		X"00000000", -- 00001A8C
-		X"00000000", -- 00001A90
-		X"00000000", -- 00001A94
-		X"00000000", -- 00001A98
-		X"00000000", -- 00001A9C
-		X"00000000", -- 00001AA0
-		X"00000000", -- 00001AA4
-		X"00000000", -- 00001AA8
-		X"00000000", -- 00001AAC
-		X"00000000", -- 00001AB0
-		X"00000000", -- 00001AB4
-		X"00000000", -- 00001AB8
-		X"00000000", -- 00001ABC
-		X"00000000", -- 00001AC0
-		X"00000000", -- 00001AC4
-		X"00000000", -- 00001AC8
-		X"00000000", -- 00001ACC
-		X"00000000", -- 00001AD0
-		X"00000000", -- 00001AD4
-		X"00000000", -- 00001AD8
-		X"00000000", -- 00001ADC
-		X"00000000", -- 00001AE0
-		X"00000000", -- 00001AE4
-		X"00000000", -- 00001AE8
-		X"00000000", -- 00001AEC
-		X"00000000", -- 00001AF0
-		X"00000000", -- 00001AF4
-		X"00000000", -- 00001AF8
-		X"00000000", -- 00001AFC
-		X"00000000", -- 00001B00
-		X"00000000", -- 00001B04
-		X"00000000", -- 00001B08
-		X"00000000", -- 00001B0C
-		X"00000000", -- 00001B10
-		X"00000000", -- 00001B14
-		X"00000000", -- 00001B18
-		X"00000000", -- 00001B1C
-		X"00000000", -- 00001B20
-		X"00000000", -- 00001B24
-		X"00000000", -- 00001B28
-		X"00000000", -- 00001B2C
-		X"00000000", -- 00001B30
-		X"00000000", -- 00001B34
-		X"00000000", -- 00001B38
-		X"00000000", -- 00001B3C
-		X"00000000", -- 00001B40
-		X"00000000", -- 00001B44
-		X"00000000", -- 00001B48
-		X"00000000", -- 00001B4C
-		X"00000000", -- 00001B50
-		X"00000000", -- 00001B54
-		X"00000000", -- 00001B58
-		X"00000000", -- 00001B5C
-		X"00000000", -- 00001B60
-		X"00000000", -- 00001B64
-		X"00000000", -- 00001B68
-		X"00000000", -- 00001B6C
-		X"00000000", -- 00001B70
-		X"00000000", -- 00001B74
-		X"00000000", -- 00001B78
-		X"00000000", -- 00001B7C
-		X"00000000", -- 00001B80
-		X"00000000", -- 00001B84
-		X"00000000", -- 00001B88
-		X"00000000", -- 00001B8C
-		X"00000000", -- 00001B90
-		X"00000000", -- 00001B94
-		X"00000000", -- 00001B98
-		X"00000000", -- 00001B9C
-		X"00000000", -- 00001BA0
-		X"00000000", -- 00001BA4
-		X"00000000", -- 00001BA8
-		X"00000000", -- 00001BAC
-		X"00000000", -- 00001BB0
-		X"00000000", -- 00001BB4
-		X"00000000", -- 00001BB8
-		X"00000000", -- 00001BBC
-		X"00000000", -- 00001BC0
-		X"00000000", -- 00001BC4
-		X"00000000", -- 00001BC8
-		X"00000000", -- 00001BCC
-		X"00000000", -- 00001BD0
-		X"00000000", -- 00001BD4
-		X"00000000", -- 00001BD8
-		X"00000000", -- 00001BDC
-		X"00000000", -- 00001BE0
-		X"00000000", -- 00001BE4
-		X"00000000", -- 00001BE8
-		X"00000000", -- 00001BEC
-		X"00000000", -- 00001BF0
-		X"00000000", -- 00001BF4
-		X"00000000", -- 00001BF8
-		X"00000000", -- 00001BFC
-		X"00000000", -- 00001C00
-		X"00000000", -- 00001C04
-		X"00000000", -- 00001C08
-		X"00000000", -- 00001C0C
-		X"00000000", -- 00001C10
-		X"00000000", -- 00001C14
-		X"00000000", -- 00001C18
-		X"00000000", -- 00001C1C
-		X"00000000", -- 00001C20
-		X"00000000", -- 00001C24
-		X"00000000", -- 00001C28
-		X"00000000", -- 00001C2C
-		X"00000000", -- 00001C30
-		X"00000000", -- 00001C34
-		X"00000000", -- 00001C38
-		X"00000000", -- 00001C3C
-		X"00000000", -- 00001C40
-		X"00000000", -- 00001C44
-		X"00000000", -- 00001C48
-		X"00000000", -- 00001C4C
-		X"00000000", -- 00001C50
-		X"00000000", -- 00001C54
-		X"00000000", -- 00001C58
-		X"00000000", -- 00001C5C
-		X"00000000", -- 00001C60
-		X"00000000", -- 00001C64
-		X"00000000", -- 00001C68
-		X"00000000", -- 00001C6C
-		X"00000000", -- 00001C70
-		X"00000000", -- 00001C74
-		X"00000000", -- 00001C78
-		X"00000000", -- 00001C7C
-		X"00000000", -- 00001C80
-		X"00000000", -- 00001C84
-		X"00000000", -- 00001C88
-		X"00000000", -- 00001C8C
-		X"00000000", -- 00001C90
-		X"00000000", -- 00001C94
-		X"00000000", -- 00001C98
-		X"00000000", -- 00001C9C
-		X"00000000", -- 00001CA0
-		X"00000000", -- 00001CA4
-		X"00000000", -- 00001CA8
-		X"00000000", -- 00001CAC
-		X"00000000", -- 00001CB0
-		X"00000000", -- 00001CB4
-		X"00000000", -- 00001CB8
-		X"00000000", -- 00001CBC
-		X"00000000", -- 00001CC0
-		X"00000000", -- 00001CC4
-		X"00000000", -- 00001CC8
-		X"00000000", -- 00001CCC
-		X"00000000", -- 00001CD0
-		X"00000000", -- 00001CD4
-		X"00000000", -- 00001CD8
-		X"00000000", -- 00001CDC
-		X"00000000", -- 00001CE0
-		X"00000000", -- 00001CE4
-		X"00000000", -- 00001CE8
-		X"00000000", -- 00001CEC
-		X"00000000", -- 00001CF0
-		X"00000000", -- 00001CF4
-		X"00000000", -- 00001CF8
-		X"00000000", -- 00001CFC
-		X"00000000", -- 00001D00
-		X"00000000", -- 00001D04
-		X"00000000", -- 00001D08
-		X"00000000", -- 00001D0C
-		X"00000000", -- 00001D10
-		X"00000000", -- 00001D14
-		X"00000000", -- 00001D18
-		X"00000000", -- 00001D1C
-		X"00000000", -- 00001D20
-		X"00000000", -- 00001D24
-		X"00000000", -- 00001D28
-		X"00000000", -- 00001D2C
-		X"00000000", -- 00001D30
-		X"00000000", -- 00001D34
-		X"00000000", -- 00001D38
-		X"00000000", -- 00001D3C
-		X"00000000", -- 00001D40
-		X"00000000", -- 00001D44
-		X"00000000", -- 00001D48
-		X"00000000", -- 00001D4C
-		X"00000000", -- 00001D50
-		X"00000000", -- 00001D54
-		X"00000000", -- 00001D58
-		X"00000000", -- 00001D5C
-		X"00000000", -- 00001D60
-		X"00000000", -- 00001D64
-		X"00000000", -- 00001D68
-		X"00000000", -- 00001D6C
-		X"00000000", -- 00001D70
-		X"00000000", -- 00001D74
-		X"00000000", -- 00001D78
-		X"00000000", -- 00001D7C
-		X"00000000", -- 00001D80
-		X"00000000", -- 00001D84
-		X"00000000", -- 00001D88
-		X"00000000", -- 00001D8C
-		X"00000000", -- 00001D90
-		X"00000000", -- 00001D94
-		X"00000000", -- 00001D98
-		X"00000000", -- 00001D9C
-		X"00000000", -- 00001DA0
-		X"00000000", -- 00001DA4
-		X"00000000", -- 00001DA8
-		X"00000000", -- 00001DAC
-		X"00000000", -- 00001DB0
-		X"00000000", -- 00001DB4
-		X"00000000", -- 00001DB8
-		X"00000000", -- 00001DBC
-		X"00000000", -- 00001DC0
-		X"00000000", -- 00001DC4
-		X"00000000", -- 00001DC8
-		X"00000000", -- 00001DCC
-		X"00000000", -- 00001DD0
-		X"00000000", -- 00001DD4
-		X"00000000", -- 00001DD8
-		X"00000000", -- 00001DDC
-		X"00000000", -- 00001DE0
-		X"00000000", -- 00001DE4
-		X"00000000", -- 00001DE8
-		X"00000000", -- 00001DEC
-		X"00000000", -- 00001DF0
-		X"00000000", -- 00001DF4
-		X"00000000", -- 00001DF8
-		X"00000000", -- 00001DFC
-		X"00000000", -- 00001E00
-		X"00000000", -- 00001E04
-		X"00000000", -- 00001E08
-		X"00000000", -- 00001E0C
-		X"00000000", -- 00001E10
-		X"00000000", -- 00001E14
-		X"00000000", -- 00001E18
-		X"00000000", -- 00001E1C
-		X"00000000", -- 00001E20
-		X"00000000", -- 00001E24
-		X"00000000", -- 00001E28
-		X"00000000", -- 00001E2C
-		X"00000000", -- 00001E30
-		X"00000000", -- 00001E34
-		X"00000000", -- 00001E38
-		X"00000000", -- 00001E3C
-		X"00000000", -- 00001E40
-		X"00000000", -- 00001E44
-		X"00000000", -- 00001E48
-		X"00000000", -- 00001E4C
-		X"00000000", -- 00001E50
-		X"00000000", -- 00001E54
-		X"00000000", -- 00001E58
-		X"00000000", -- 00001E5C
-		X"00000000", -- 00001E60
-		X"00000000", -- 00001E64
-		X"00000000", -- 00001E68
-		X"00000000", -- 00001E6C
-		X"00000000", -- 00001E70
-		X"00000000", -- 00001E74
-		X"00000000", -- 00001E78
-		X"00000000", -- 00001E7C
-		X"00000000", -- 00001E80
-		X"00000000", -- 00001E84
-		X"00000000", -- 00001E88
-		X"00000000", -- 00001E8C
-		X"00000000", -- 00001E90
-		X"00000000", -- 00001E94
-		X"00000000", -- 00001E98
-		X"00000000", -- 00001E9C
-		X"00000000", -- 00001EA0
-		X"00000000", -- 00001EA4
-		X"00000000", -- 00001EA8
-		X"00000000", -- 00001EAC
-		X"00000000", -- 00001EB0
-		X"00000000", -- 00001EB4
-		X"00000000", -- 00001EB8
-		X"00000000", -- 00001EBC
-		X"00000000", -- 00001EC0
-		X"00000000", -- 00001EC4
-		X"00000000", -- 00001EC8
-		X"00000000", -- 00001ECC
-		X"00000000", -- 00001ED0
-		X"00000000", -- 00001ED4
-		X"00000000", -- 00001ED8
-		X"00000000", -- 00001EDC
-		X"00000000", -- 00001EE0
-		X"00000000", -- 00001EE4
-		X"00000000", -- 00001EE8
-		X"00000000", -- 00001EEC
-		X"00000000", -- 00001EF0
-		X"00000000", -- 00001EF4
-		X"00000000", -- 00001EF8
-		X"00000000", -- 00001EFC
-		X"00000000", -- 00001F00
-		X"00000000", -- 00001F04
-		X"00000000", -- 00001F08
-		X"00000000", -- 00001F0C
-		X"00000000", -- 00001F10
-		X"00000000", -- 00001F14
-		X"00000000", -- 00001F18
-		X"00000000", -- 00001F1C
-		X"00000000", -- 00001F20
-		X"00000000", -- 00001F24
-		X"00000000", -- 00001F28
-		X"00000000", -- 00001F2C
-		X"00000000", -- 00001F30
-		X"00000000", -- 00001F34
-		X"00000000", -- 00001F38
-		X"00000000", -- 00001F3C
-		X"00000000", -- 00001F40
-		X"00000000", -- 00001F44
-		X"00000000", -- 00001F48
-		X"00000000", -- 00001F4C
-		X"00000000", -- 00001F50
-		X"00000000", -- 00001F54
-		X"00000000", -- 00001F58
-		X"00000000", -- 00001F5C
-		X"00000000", -- 00001F60
-		X"00000000", -- 00001F64
-		X"00000000", -- 00001F68
-		X"00000000", -- 00001F6C
-		X"00000000", -- 00001F70
-		X"00000000", -- 00001F74
-		X"00000000", -- 00001F78
-		X"00000000", -- 00001F7C
-		X"00000000", -- 00001F80
-		X"00000000", -- 00001F84
-		X"00000000", -- 00001F88
-		X"00000000", -- 00001F8C
-		X"00000000", -- 00001F90
-		X"00000000", -- 00001F94
-		X"00000000", -- 00001F98
-		X"00000000", -- 00001F9C
-		X"00000000", -- 00001FA0
-		X"00000000", -- 00001FA4
-		X"00000000", -- 00001FA8
-		X"00000000", -- 00001FAC
-		X"00000000", -- 00001FB0
-		X"00000000", -- 00001FB4
-		X"00000000", -- 00001FB8
-		X"00000000", -- 00001FBC
-		X"00000000", -- 00001FC0
-		X"00000000", -- 00001FC4
-		X"00000000", -- 00001FC8
-		X"00000000", -- 00001FCC
-		X"00000000", -- 00001FD0
-		X"00000000", -- 00001FD4
-		X"00000000", -- 00001FD8
-		X"00000000", -- 00001FDC
-		X"00000000", -- 00001FE0
-		X"00000000", -- 00001FE4
-		X"00000000", -- 00001FE8
-		X"00000000", -- 00001FEC
-		X"00000000", -- 00001FF0
-		X"00000000", -- 00001FF4
-		X"00000000", -- 00001FF8
-		X"00000000"  -- 00001FFC
-	);
-
-begin
-
-PROM_READ:
-	process(clk)
-	begin
-		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
-		end if;
-	end process;
-
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
-	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
-	
-			end if;
-		end if;
-	end process;
-
-PROM_WRITE:
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din;
-			else
-				jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0)));
-			end if;
-		end if;
-	end process;
-
-end data;
diff --git a/projects/mips_sys/src/bootloader.dis b/projects/mips_sys/src/bootloader.dis
deleted file mode 100644
index 04b259d..0000000
--- a/projects/mips_sys/src/bootloader.dis
+++ /dev/null
@@ -1,1466 +0,0 @@
-
-bootloader.elf:     file format elf32-bigmips
-
-
-Disassembly of section .init:
-
-bfc00000 <__entry>:
-bfc00000:	3c1d8000 	lui	sp,0x8000
-bfc00004:	27bdeff0 	addiu	sp,sp,-4112
-bfc00008:	3c1a1040 	lui	k0,0x1040
-bfc0000c:	375a000c 	ori	k0,k0,0xc
-bfc00010:	409a6000 	mtc0	k0,c0_sr
-bfc00014:	241a0000 	li	k0,0
-bfc00018:	409a6800 	mtc0	k0,c0_cause
-bfc0001c:	401a7800 	mfc0	k0,c0_prid
-bfc00020:	00000000 	nop
-bfc00024:	409af800 	mtc0	k0,$31
-bfc00028:	42000020 	c0	0x20
-bfc0002c:	42000022 	c0	0x22
-bfc00030:	3c1abfc0 	lui	k0,0xbfc0
-bfc00034:	275a005c 	addiu	k0,k0,92
-bfc00038:	0340f809 	jalr	k0
-bfc0003c:	00000000 	nop
-bfc00040:	3c1abfc0 	lui	k0,0xbfc0
-bfc00044:	275a114c 	addiu	k0,k0,4428
-bfc00048:	0340f809 	jalr	k0
-bfc0004c:	00000000 	nop
-
-bfc00050 <_terminate>:
-bfc00050:	00000000 	nop
-bfc00054:	0bf00014 	j	bfc00050 <_terminate>
-bfc00058:	00000000 	nop
-
-bfc0005c <_init>:
-bfc0005c:	3c1aa001 275a0008 241b000d af5b0000     <...'Z..$....[..
-bfc0006c:	03e00008                                ....
-
-Disassembly of section .ktext:
-
-bfc00180 <_exc_handler>:
-bfc00180:	401a6800 	mfc0	k0,c0_cause
-bfc00184:	3c1bc000 	lui	k1,0xc000
-bfc00188:	001ad082 	srl	k0,k0,0x2
-bfc0018c:	335a000f 	andi	k0,k0,0xf
-bfc00190:	035bd025 	or	k0,k0,k1
-bfc00194:	3c1ba000 	lui	k1,0xa000
-bfc00198:	277b0000 	addiu	k1,k1,0
-bfc0019c:	af7a0000 	sw	k0,0(k1)
-bfc001a0:	401a6800 	mfc0	k0,c0_cause
-bfc001a4:	00000000 	nop
-bfc001a8:	001ad202 	srl	k0,k0,0x8
-bfc001ac:	335a00ff 	andi	k0,k0,0xff
-bfc001b0:	1740fffb 	bnez	k0,bfc001a0 <_exc_handler+0x20>
-bfc001b4:	00000000 	nop
-bfc001b8:	401a7000 	mfc0	k0,c0_epc
-bfc001bc:	00000000 	nop
-bfc001c0:	03400008 	jr	k0
-bfc001c4:	42000010 	rfe
-
-Disassembly of section .text:
-
-bfc001c8 <CP0_SR_read>:
-bfc001c8:	40026000 	mfc0	v0,c0_sr
-bfc001cc:	03e00008 	jr	ra
-bfc001d0:	00000000 	nop
-
-bfc001d4 <CP0_SR_write>:
-bfc001d4:	40846000 	mtc0	a0,c0_sr
-bfc001d8:	03e00008 	jr	ra
-bfc001dc:	00000000 	nop
-
-bfc001e0 <CP0_CR_read>:
-bfc001e0:	40026800 	mfc0	v0,c0_cause
-bfc001e4:	03e00008 	jr	ra
-bfc001e8:	00000000 	nop
-
-bfc001ec <CP0_CR_write>:
-bfc001ec:	40846800 	mtc0	a0,c0_cause
-bfc001f0:	03e00008 	jr	ra
-bfc001f4:	00000000 	nop
-
-bfc001f8 <CP0_PRID_read>:
-bfc001f8:	40027800 	mfc0	v0,c0_prid
-bfc001fc:	03e00008 	jr	ra
-bfc00200:	00000000 	nop
-
-bfc00204 <readchar>:
-bfc00204:	3c02a001 	lui	v0,0xa001
-bfc00208:	34430004 	ori	v1,v0,0x4
-bfc0020c:	8c620000 	lw	v0,0(v1)
-bfc00210:	00000000 	nop
-bfc00214:	30420010 	andi	v0,v0,0x10
-bfc00218:	1040fffc 	beqz	v0,bfc0020c <readchar+0x8>
-bfc0021c:	3c02a001 	lui	v0,0xa001
-bfc00220:	8c420000 	lw	v0,0(v0)
-bfc00224:	00000000 	nop
-bfc00228:	00021600 	sll	v0,v0,0x18
-bfc0022c:	03e00008 	jr	ra
-bfc00230:	00021603 	sra	v0,v0,0x18
-
-bfc00234 <writechar>:
-bfc00234:	00042600 	sll	a0,a0,0x18
-bfc00238:	3c02a001 	lui	v0,0xa001
-bfc0023c:	00042603 	sra	a0,a0,0x18
-bfc00240:	34430004 	ori	v1,v0,0x4
-bfc00244:	8c620000 	lw	v0,0(v1)
-bfc00248:	00000000 	nop
-bfc0024c:	30420002 	andi	v0,v0,0x2
-bfc00250:	1440fffc 	bnez	v0,bfc00244 <writechar+0x10>
-bfc00254:	3c02a001 	lui	v0,0xa001
-bfc00258:	ac440000 	sw	a0,0(v0)
-bfc0025c:	03e00008 	jr	ra
-bfc00260:	00000000 	nop
-
-bfc00264 <_putchar>:
-bfc00264:	00042600 	sll	a0,a0,0x18
-bfc00268:	00042603 	sra	a0,a0,0x18
-bfc0026c:	2402000a 	li	v0,10
-bfc00270:	1482000a 	bne	a0,v0,bfc0029c <_putchar+0x38>
-bfc00274:	3c02a001 	lui	v0,0xa001
-bfc00278:	34430004 	ori	v1,v0,0x4
-bfc0027c:	8c620000 	lw	v0,0(v1)
-bfc00280:	00000000 	nop
-bfc00284:	30420002 	andi	v0,v0,0x2
-bfc00288:	1440fffc 	bnez	v0,bfc0027c <_putchar+0x18>
-bfc0028c:	3c02a001 	lui	v0,0xa001
-bfc00290:	2403000d 	li	v1,13
-bfc00294:	ac430000 	sw	v1,0(v0)
-bfc00298:	3c02a001 	lui	v0,0xa001
-bfc0029c:	34430004 	ori	v1,v0,0x4
-bfc002a0:	8c620000 	lw	v0,0(v1)
-bfc002a4:	00000000 	nop
-bfc002a8:	30420002 	andi	v0,v0,0x2
-bfc002ac:	1440fffc 	bnez	v0,bfc002a0 <_putchar+0x3c>
-bfc002b0:	3c02a001 	lui	v0,0xa001
-bfc002b4:	ac440000 	sw	a0,0(v0)
-bfc002b8:	03e00008 	jr	ra
-bfc002bc:	00000000 	nop
-
-bfc002c0 <sputs>:
-bfc002c0:	3c02a001 	lui	v0,0xa001
-bfc002c4:	34470004 	ori	a3,v0,0x4
-bfc002c8:	00802821 	move	a1,a0
-bfc002cc:	2409000a 	li	t1,10
-bfc002d0:	3c06a001 	lui	a2,0xa001
-bfc002d4:	0bf000c6 	j	bfc00318 <sputs+0x58>
-bfc002d8:	2408000d 	li	t0,13
-bfc002dc:	14690007 	bne	v1,t1,bfc002fc <sputs+0x3c>
-bfc002e0:	00000000 	nop
-bfc002e4:	8ce20000 	lw	v0,0(a3)
-bfc002e8:	00000000 	nop
-bfc002ec:	30420002 	andi	v0,v0,0x2
-bfc002f0:	1440fffc 	bnez	v0,bfc002e4 <sputs+0x24>
-bfc002f4:	00000000 	nop
-bfc002f8:	acc80000 	sw	t0,0(a2)
-bfc002fc:	8ce20000 	lw	v0,0(a3)
-bfc00300:	00000000 	nop
-bfc00304:	30420002 	andi	v0,v0,0x2
-bfc00308:	1440fffc 	bnez	v0,bfc002fc <sputs+0x3c>
-bfc0030c:	00000000 	nop
-bfc00310:	acc30000 	sw	v1,0(a2)
-bfc00314:	24a50001 	addiu	a1,a1,1
-bfc00318:	80a30000 	lb	v1,0(a1)
-bfc0031c:	00000000 	nop
-bfc00320:	1460ffee 	bnez	v1,bfc002dc <sputs+0x1c>
-bfc00324:	00a41023 	subu	v0,a1,a0
-bfc00328:	03e00008 	jr	ra
-bfc0032c:	00000000 	nop
-
-bfc00330 <print_byte>:
-bfc00330:	00042600 	sll	a0,a0,0x18
-bfc00334:	3c02a001 	lui	v0,0xa001
-bfc00338:	00042603 	sra	a0,a0,0x18
-bfc0033c:	344a0004 	ori	t2,v0,0x4
-bfc00340:	00003821 	move	a3,zero
-bfc00344:	3c09a001 	lui	t1,0xa001
-bfc00348:	24080002 	li	t0,2
-bfc0034c:	308200ff 	andi	v0,a0,0xff
-bfc00350:	00022902 	srl	a1,v0,0x4
-bfc00354:	00041100 	sll	v0,a0,0x4
-bfc00358:	00022600 	sll	a0,v0,0x18
-bfc0035c:	2ca3000a 	sltiu	v1,a1,10
-bfc00360:	00042603 	sra	a0,a0,0x18
-bfc00364:	14600002 	bnez	v1,bfc00370 <print_byte+0x40>
-bfc00368:	24a60030 	addiu	a2,a1,48
-bfc0036c:	24a60037 	addiu	a2,a1,55
-bfc00370:	8d420000 	lw	v0,0(t2)
-bfc00374:	00000000 	nop
-bfc00378:	30420002 	andi	v0,v0,0x2
-bfc0037c:	1440fffc 	bnez	v0,bfc00370 <print_byte+0x40>
-bfc00380:	00061600 	sll	v0,a2,0x18
-bfc00384:	00021603 	sra	v0,v0,0x18
-bfc00388:	24e70001 	addiu	a3,a3,1
-bfc0038c:	ad220000 	sw	v0,0(t1)
-bfc00390:	14e8ffef 	bne	a3,t0,bfc00350 <print_byte+0x20>
-bfc00394:	308200ff 	andi	v0,a0,0xff
-bfc00398:	03e00008 	jr	ra
-bfc0039c:	00000000 	nop
-
-bfc003a0 <print_word>:
-bfc003a0:	27bdffe0 	addiu	sp,sp,-32
-bfc003a4:	afb20018 	sw	s2,24(sp)
-bfc003a8:	afb10014 	sw	s1,20(sp)
-bfc003ac:	afb00010 	sw	s0,16(sp)
-bfc003b0:	afbf001c 	sw	ra,28(sp)
-bfc003b4:	00808821 	move	s1,a0
-bfc003b8:	00008021 	move	s0,zero
-bfc003bc:	24120004 	li	s2,4
-bfc003c0:	00112603 	sra	a0,s1,0x18
-bfc003c4:	0ff000cc 	jal	bfc00330 <print_byte>
-bfc003c8:	26100001 	addiu	s0,s0,1
-bfc003cc:	1612fffc 	bne	s0,s2,bfc003c0 <print_word+0x20>
-bfc003d0:	00118a00 	sll	s1,s1,0x8
-bfc003d4:	8fbf001c 	lw	ra,28(sp)
-bfc003d8:	8fb20018 	lw	s2,24(sp)
-bfc003dc:	8fb10014 	lw	s1,20(sp)
-bfc003e0:	8fb00010 	lw	s0,16(sp)
-bfc003e4:	03e00008 	jr	ra
-bfc003e8:	27bd0020 	addiu	sp,sp,32
-
-bfc003ec <memdump>:
-bfc003ec:	27bdffc8 	addiu	sp,sp,-56
-bfc003f0:	afb60028 	sw	s6,40(sp)
-bfc003f4:	afbf0034 	sw	ra,52(sp)
-bfc003f8:	afbe0030 	sw	s8,48(sp)
-bfc003fc:	afb7002c 	sw	s7,44(sp)
-bfc00400:	afb50024 	sw	s5,36(sp)
-bfc00404:	afb40020 	sw	s4,32(sp)
-bfc00408:	afb3001c 	sw	s3,28(sp)
-bfc0040c:	afb20018 	sw	s2,24(sp)
-bfc00410:	afb10014 	sw	s1,20(sp)
-bfc00414:	afb00010 	sw	s0,16(sp)
-bfc00418:	00801021 	move	v0,a0
-bfc0041c:	10a00002 	beqz	a1,bfc00428 <memdump+0x3c>
-bfc00420:	00c0b021 	move	s6,a2
-bfc00424:	00002021 	move	a0,zero
-bfc00428:	00409821 	move	s3,v0
-bfc0042c:	3c02a001 	lui	v0,0xa001
-bfc00430:	00e09021 	move	s2,a3
-bfc00434:	0080a821 	move	s5,a0
-bfc00438:	345e0004 	ori	s8,v0,0x4
-bfc0043c:	00e0a021 	move	s4,a3
-bfc00440:	3c17a001 	lui	s7,0xa001
-bfc00444:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc00448:	02a02021 	move	a0,s5
-bfc0044c:	3c04bfc0 	lui	a0,0xbfc0
-bfc00450:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00454:	24841698 	addiu	a0,a0,5784
-bfc00458:	02608821 	move	s1,s3
-bfc0045c:	0bf00128 	j	bfc004a0 <memdump+0xb4>
-bfc00460:	00008021 	move	s0,zero
-bfc00464:	12400009 	beqz	s2,bfc0048c <memdump+0xa0>
-bfc00468:	00000000 	nop
-bfc0046c:	82240000 	lb	a0,0(s1)
-bfc00470:	0ff000cc 	jal	bfc00330 <print_byte>
-bfc00474:	2652ffff 	addiu	s2,s2,-1
-bfc00478:	3c04bfc0 	lui	a0,0xbfc0
-bfc0047c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00480:	24841770 	addiu	a0,a0,6000
-bfc00484:	0bf00128 	j	bfc004a0 <memdump+0xb4>
-bfc00488:	26310001 	addiu	s1,s1,1
-bfc0048c:	3c04bfc0 	lui	a0,0xbfc0
-bfc00490:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00494:	2484169c 	addiu	a0,a0,5788
-bfc00498:	0bf0012c 	j	bfc004b0 <memdump+0xc4>
-bfc0049c:	3c04bfc0 	lui	a0,0xbfc0
-bfc004a0:	0216102a 	slt	v0,s0,s6
-bfc004a4:	1440ffef 	bnez	v0,bfc00464 <memdump+0x78>
-bfc004a8:	26100001 	addiu	s0,s0,1
-bfc004ac:	3c04bfc0 	lui	a0,0xbfc0
-bfc004b0:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc004b4:	2484169c 	addiu	a0,a0,5788
-bfc004b8:	02602821 	move	a1,s3
-bfc004bc:	0bf00155 	j	bfc00554 <memdump+0x168>
-bfc004c0:	00002021 	move	a0,zero
-bfc004c4:	1280001e 	beqz	s4,bfc00540 <memdump+0x154>
-bfc004c8:	00000000 	nop
-bfc004cc:	90a30000 	lbu	v1,0(a1)
-bfc004d0:	00000000 	nop
-bfc004d4:	2462ffe0 	addiu	v0,v1,-32
-bfc004d8:	304200ff 	andi	v0,v0,0xff
-bfc004dc:	2c420060 	sltiu	v0,v0,96
-bfc004e0:	14400003 	bnez	v0,bfc004f0 <memdump+0x104>
-bfc004e4:	00031e00 	sll	v1,v1,0x18
-bfc004e8:	2403002e 	li	v1,46
-bfc004ec:	00031e00 	sll	v1,v1,0x18
-bfc004f0:	00031e03 	sra	v1,v1,0x18
-bfc004f4:	2402000a 	li	v0,10
-bfc004f8:	14620007 	bne	v1,v0,bfc00518 <memdump+0x12c>
-bfc004fc:	00000000 	nop
-bfc00500:	8fc20000 	lw	v0,0(s8)
-bfc00504:	00000000 	nop
-bfc00508:	30420002 	andi	v0,v0,0x2
-bfc0050c:	1440fffc 	bnez	v0,bfc00500 <memdump+0x114>
-bfc00510:	2402000d 	li	v0,13
-bfc00514:	aee20000 	sw	v0,0(s7)
-bfc00518:	8fc20000 	lw	v0,0(s8)
-bfc0051c:	00000000 	nop
-bfc00520:	30420002 	andi	v0,v0,0x2
-bfc00524:	1440fffc 	bnez	v0,bfc00518 <memdump+0x12c>
-bfc00528:	00000000 	nop
-bfc0052c:	aee30000 	sw	v1,0(s7)
-bfc00530:	2694ffff 	addiu	s4,s4,-1
-bfc00534:	24840001 	addiu	a0,a0,1
-bfc00538:	0bf00155 	j	bfc00554 <memdump+0x168>
-bfc0053c:	24a50001 	addiu	a1,a1,1
-bfc00540:	3c04bfc0 	lui	a0,0xbfc0
-bfc00544:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00548:	24841770 	addiu	a0,a0,6000
-bfc0054c:	0bf00159 	j	bfc00564 <memdump+0x178>
-bfc00550:	3c04bfc0 	lui	a0,0xbfc0
-bfc00554:	0096102a 	slt	v0,a0,s6
-bfc00558:	1440ffda 	bnez	v0,bfc004c4 <memdump+0xd8>
-bfc0055c:	00000000 	nop
-bfc00560:	3c04bfc0 	lui	a0,0xbfc0
-bfc00564:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc00568:	248416c4 	addiu	a0,a0,5828
-bfc0056c:	02b6a821 	addu	s5,s5,s6
-bfc00570:	1640ffb4 	bnez	s2,bfc00444 <memdump+0x58>
-bfc00574:	02769821 	addu	s3,s3,s6
-bfc00578:	8fbf0034 	lw	ra,52(sp)
-bfc0057c:	8fbe0030 	lw	s8,48(sp)
-bfc00580:	8fb7002c 	lw	s7,44(sp)
-bfc00584:	8fb60028 	lw	s6,40(sp)
-bfc00588:	8fb50024 	lw	s5,36(sp)
-bfc0058c:	8fb40020 	lw	s4,32(sp)
-bfc00590:	8fb3001c 	lw	s3,28(sp)
-bfc00594:	8fb20018 	lw	s2,24(sp)
-bfc00598:	8fb10014 	lw	s1,20(sp)
-bfc0059c:	8fb00010 	lw	s0,16(sp)
-bfc005a0:	03e00008 	jr	ra
-bfc005a4:	27bd0038 	addiu	sp,sp,56
-
-bfc005a8 <PrintBuffer8>:
-bfc005a8:	00c03821 	move	a3,a2
-bfc005ac:	00a03021 	move	a2,a1
-bfc005b0:	0bf000fb 	j	bfc003ec <memdump>
-bfc005b4:	24050001 	li	a1,1
-
-bfc005b8 <cfi_get_status>:
-bfc005b8:	8c840000 	lw	a0,0(a0)
-bfc005bc:	3c020070 	lui	v0,0x70
-bfc005c0:	34420070 	ori	v0,v0,0x70
-bfc005c4:	3c0300ff 	lui	v1,0xff
-bfc005c8:	ac820000 	sw	v0,0(a0)
-bfc005cc:	346300ff 	ori	v1,v1,0xff
-bfc005d0:	8c820000 	lw	v0,0(a0)
-bfc005d4:	ac830000 	sw	v1,0(a0)
-bfc005d8:	03e00008 	jr	ra
-bfc005dc:	00000000 	nop
-
-bfc005e0 <cfi_init>:
-bfc005e0:	27bdfff8 	addiu	sp,sp,-8
-bfc005e4:	ac850000 	sw	a1,0(a0)
-bfc005e8:	24820008 	addiu	v0,a0,8
-bfc005ec:	0bf0017f 	j	bfc005fc <cfi_init+0x1c>
-bfc005f0:	24830020 	addiu	v1,a0,32
-bfc005f4:	a0400000 	sb	zero,0(v0)
-bfc005f8:	24420001 	addiu	v0,v0,1
-bfc005fc:	1443fffd 	bne	v0,v1,bfc005f4 <cfi_init+0x14>
-bfc00600:	00000000 	nop
-bfc00604:	24020001 	li	v0,1
-bfc00608:	ac820004 	sw	v0,4(a0)
-bfc0060c:	03e00008 	jr	ra
-bfc00610:	27bd0008 	addiu	sp,sp,8
-
-bfc00614 <cfi_find>:
-bfc00614:	8c870000 	lw	a3,0(a0)
-bfc00618:	3c020098 	lui	v0,0x98
-bfc0061c:	34420098 	ori	v0,v0,0x98
-bfc00620:	ace20000 	sw	v0,0(a3)
-bfc00624:	3c0200ff 	lui	v0,0xff
-bfc00628:	344200ff 	ori	v0,v0,0xff
-bfc0062c:	ace20000 	sw	v0,0(a3)
-bfc00630:	3c020090 	lui	v0,0x90
-bfc00634:	34420090 	ori	v0,v0,0x90
-bfc00638:	ace20000 	sw	v0,0(a3)
-bfc0063c:	00804021 	move	t0,a0
-bfc00640:	94e4009c 	lhu	a0,156(a3)
-bfc00644:	24030002 	li	v1,2
-bfc00648:	24020020 	li	v0,32
-bfc0064c:	ad030008 	sw	v1,8(t0)
-bfc00650:	ad03001c 	sw	v1,28(t0)
-bfc00654:	ad020018 	sw	v0,24(t0)
-bfc00658:	3084ffff 	andi	a0,a0,0xffff
-bfc0065c:	0bf0019d 	j	bfc00674 <cfi_find+0x60>
-bfc00660:	00001821 	move	v1,zero
-bfc00664:	8d020008 	lw	v0,8(t0)
-bfc00668:	00000000 	nop
-bfc0066c:	00021040 	sll	v0,v0,0x1
-bfc00670:	ad020008 	sw	v0,8(t0)
-bfc00674:	0064102b 	sltu	v0,v1,a0
-bfc00678:	1440fffa 	bnez	v0,bfc00664 <cfi_find+0x50>
-bfc0067c:	24630001 	addiu	v1,v1,1
-bfc00680:	94e200ac 	lhu	v0,172(a3)
-bfc00684:	94e300a8 	lhu	v1,168(a3)
-bfc00688:	3042ffff 	andi	v0,v0,0xffff
-bfc0068c:	8d04001c 	lw	a0,28(t0)
-bfc00690:	3063ffff 	andi	v1,v1,0xffff
-bfc00694:	00021200 	sll	v0,v0,0x8
-bfc00698:	00432825 	or	a1,v0,v1
-bfc0069c:	ad040014 	sw	a0,20(t0)
-bfc006a0:	0bf001ae 	j	bfc006b8 <cfi_find+0xa4>
-bfc006a4:	00001821 	move	v1,zero
-bfc006a8:	8d020014 	lw	v0,20(t0)
-bfc006ac:	00000000 	nop
-bfc006b0:	00021040 	sll	v0,v0,0x1
-bfc006b4:	ad020014 	sw	v0,20(t0)
-bfc006b8:	0065102b 	sltu	v0,v1,a1
-bfc006bc:	1440fffa 	bnez	v0,bfc006a8 <cfi_find+0x94>
-bfc006c0:	24630001 	addiu	v1,v1,1
-bfc006c4:	94e300b8 	lhu	v1,184(a3)
-bfc006c8:	94e600b4 	lhu	a2,180(a3)
-bfc006cc:	94e200c0 	lhu	v0,192(a3)
-bfc006d0:	94e400bc 	lhu	a0,188(a3)
-bfc006d4:	8d05001c 	lw	a1,28(t0)
-bfc006d8:	3042ffff 	andi	v0,v0,0xffff
-bfc006dc:	3084ffff 	andi	a0,a0,0xffff
-bfc006e0:	00021200 	sll	v0,v0,0x8
-bfc006e4:	00441025 	or	v0,v0,a0
-bfc006e8:	00052a00 	sll	a1,a1,0x8
-bfc006ec:	00a20018 	mult	a1,v0
-bfc006f0:	3063ffff 	andi	v1,v1,0xffff
-bfc006f4:	30c6ffff 	andi	a2,a2,0xffff
-bfc006f8:	00031a00 	sll	v1,v1,0x8
-bfc006fc:	00661825 	or	v1,v1,a2
-bfc00700:	24630001 	addiu	v1,v1,1
-bfc00704:	ad030010 	sw	v1,16(t0)
-bfc00708:	3c0300ff 	lui	v1,0xff
-bfc0070c:	346300ff 	ori	v1,v1,0xff
-bfc00710:	00001021 	move	v0,zero
-bfc00714:	00002812 	mflo	a1
-bfc00718:	ad05000c 	sw	a1,12(t0)
-bfc0071c:	ace30000 	sw	v1,0(a3)
-bfc00720:	03e00008 	jr	ra
-bfc00724:	00000000 	nop
-
-bfc00728 <cfi_block_is_locked>:
-bfc00728:	8c820008 	lw	v0,8(a0)
-bfc0072c:	8c860000 	lw	a2,0(a0)
-bfc00730:	00021082 	srl	v0,v0,0x2
-bfc00734:	00a2102b 	sltu	v0,a1,v0
-bfc00738:	14400004 	bnez	v0,bfc0074c <cfi_block_is_locked+0x24>
-bfc0073c:	3c030090 	lui	v1,0x90
-bfc00740:	3c028010 	lui	v0,0x8010
-bfc00744:	03e00008 	jr	ra
-bfc00748:	34420002 	ori	v0,v0,0x2
-bfc0074c:	8c820010 	lw	v0,16(a0)
-bfc00750:	00000000 	nop
-bfc00754:	2442ffff 	addiu	v0,v0,-1
-bfc00758:	00021400 	sll	v0,v0,0x10
-bfc0075c:	00a21024 	and	v0,a1,v0
-bfc00760:	24420002 	addiu	v0,v0,2
-bfc00764:	34630090 	ori	v1,v1,0x90
-bfc00768:	00021080 	sll	v0,v0,0x2
-bfc0076c:	acc30000 	sw	v1,0(a2)
-bfc00770:	00c21021 	addu	v0,a2,v0
-bfc00774:	8c430000 	lw	v1,0(v0)
-bfc00778:	3c020001 	lui	v0,0x1
-bfc0077c:	34420001 	ori	v0,v0,0x1
-bfc00780:	00621824 	and	v1,v1,v0
-bfc00784:	3c0200ff 	lui	v0,0xff
-bfc00788:	344200ff 	ori	v0,v0,0xff
-bfc0078c:	acc20000 	sw	v0,0(a2)
-bfc00790:	03e00008 	jr	ra
-bfc00794:	0003102b 	sltu	v0,zero,v1
-
-bfc00798 <cfi_block_erase>:
-bfc00798:	8c820008 	lw	v0,8(a0)
-bfc0079c:	00a01821 	move	v1,a1
-bfc007a0:	00021082 	srl	v0,v0,0x2
-bfc007a4:	00a2102b 	sltu	v0,a1,v0
-bfc007a8:	8c850000 	lw	a1,0(a0)
-bfc007ac:	14400003 	bnez	v0,bfc007bc <cfi_block_erase+0x24>
-bfc007b0:	3c028010 	lui	v0,0x8010
-bfc007b4:	0bf0020c 	j	bfc00830 <cfi_block_erase+0x98>
-bfc007b8:	34430002 	ori	v1,v0,0x2
-bfc007bc:	8c820010 	lw	v0,16(a0)
-bfc007c0:	00000000 	nop
-bfc007c4:	2442ffff 	addiu	v0,v0,-1
-bfc007c8:	00021400 	sll	v0,v0,0x10
-bfc007cc:	00621024 	and	v0,v1,v0
-bfc007d0:	00021080 	sll	v0,v0,0x2
-bfc007d4:	00a22021 	addu	a0,a1,v0
-bfc007d8:	3c020020 	lui	v0,0x20
-bfc007dc:	34420020 	ori	v0,v0,0x20
-bfc007e0:	ac820000 	sw	v0,0(a0)
-bfc007e4:	3c0200d0 	lui	v0,0xd0
-bfc007e8:	344200d0 	ori	v0,v0,0xd0
-bfc007ec:	ac820000 	sw	v0,0(a0)
-bfc007f0:	3c020080 	lui	v0,0x80
-bfc007f4:	34430080 	ori	v1,v0,0x80
-bfc007f8:	8c860000 	lw	a2,0(a0)
-bfc007fc:	00000000 	nop
-bfc00800:	00c31024 	and	v0,a2,v1
-bfc00804:	1443fffc 	bne	v0,v1,bfc007f8 <cfi_block_erase+0x60>
-bfc00808:	3c02002a 	lui	v0,0x2a
-bfc0080c:	3442002a 	ori	v0,v0,0x2a
-bfc00810:	00c21024 	and	v0,a2,v0
-bfc00814:	10400003 	beqz	v0,bfc00824 <cfi_block_erase+0x8c>
-bfc00818:	00001821 	move	v1,zero
-bfc0081c:	3c029010 	lui	v0,0x9010
-bfc00820:	00c21825 	or	v1,a2,v0
-bfc00824:	3c0200ff 	lui	v0,0xff
-bfc00828:	344200ff 	ori	v0,v0,0xff
-bfc0082c:	ac820000 	sw	v0,0(a0)
-bfc00830:	03e00008 	jr	ra
-bfc00834:	00601021 	move	v0,v1
-
-bfc00838 <cfi_block_lock>:
-bfc00838:	8c820008 	lw	v0,8(a0)
-bfc0083c:	00a01821 	move	v1,a1
-bfc00840:	00021082 	srl	v0,v0,0x2
-bfc00844:	00a2102b 	sltu	v0,a1,v0
-bfc00848:	8c850000 	lw	a1,0(a0)
-bfc0084c:	14400003 	bnez	v0,bfc0085c <cfi_block_lock+0x24>
-bfc00850:	3c028010 	lui	v0,0x8010
-bfc00854:	0bf00234 	j	bfc008d0 <cfi_block_lock+0x98>
-bfc00858:	34430002 	ori	v1,v0,0x2
-bfc0085c:	8c820010 	lw	v0,16(a0)
-bfc00860:	00000000 	nop
-bfc00864:	2442ffff 	addiu	v0,v0,-1
-bfc00868:	00021400 	sll	v0,v0,0x10
-bfc0086c:	00621024 	and	v0,v1,v0
-bfc00870:	00021080 	sll	v0,v0,0x2
-bfc00874:	00a22021 	addu	a0,a1,v0
-bfc00878:	3c020060 	lui	v0,0x60
-bfc0087c:	34420060 	ori	v0,v0,0x60
-bfc00880:	ac820000 	sw	v0,0(a0)
-bfc00884:	3c020001 	lui	v0,0x1
-bfc00888:	34420001 	ori	v0,v0,0x1
-bfc0088c:	ac820000 	sw	v0,0(a0)
-bfc00890:	3c020080 	lui	v0,0x80
-bfc00894:	34430080 	ori	v1,v0,0x80
-bfc00898:	8c860000 	lw	a2,0(a0)
-bfc0089c:	00000000 	nop
-bfc008a0:	00c31024 	and	v0,a2,v1
-bfc008a4:	1443fffc 	bne	v0,v1,bfc00898 <cfi_block_lock+0x60>
-bfc008a8:	3c020038 	lui	v0,0x38
-bfc008ac:	34420038 	ori	v0,v0,0x38
-bfc008b0:	00c21024 	and	v0,a2,v0
-bfc008b4:	10400003 	beqz	v0,bfc008c4 <cfi_block_lock+0x8c>
-bfc008b8:	00001821 	move	v1,zero
-bfc008bc:	3c029010 	lui	v0,0x9010
-bfc008c0:	00c21825 	or	v1,a2,v0
-bfc008c4:	3c0200ff 	lui	v0,0xff
-bfc008c8:	344200ff 	ori	v0,v0,0xff
-bfc008cc:	ac820000 	sw	v0,0(a0)
-bfc008d0:	03e00008 	jr	ra
-bfc008d4:	00601021 	move	v0,v1
-
-bfc008d8 <cfi_block_unlock>:
-bfc008d8:	8c820008 	lw	v0,8(a0)
-bfc008dc:	00a01821 	move	v1,a1
-bfc008e0:	00021082 	srl	v0,v0,0x2
-bfc008e4:	00a2102b 	sltu	v0,a1,v0
-bfc008e8:	8c850000 	lw	a1,0(a0)
-bfc008ec:	14400003 	bnez	v0,bfc008fc <cfi_block_unlock+0x24>
-bfc008f0:	3c028010 	lui	v0,0x8010
-bfc008f4:	0bf0025c 	j	bfc00970 <cfi_block_unlock+0x98>
-bfc008f8:	34430002 	ori	v1,v0,0x2
-bfc008fc:	8c820010 	lw	v0,16(a0)
-bfc00900:	00000000 	nop
-bfc00904:	2442ffff 	addiu	v0,v0,-1
-bfc00908:	00021400 	sll	v0,v0,0x10
-bfc0090c:	00621024 	and	v0,v1,v0
-bfc00910:	00021080 	sll	v0,v0,0x2
-bfc00914:	00a22021 	addu	a0,a1,v0
-bfc00918:	3c020060 	lui	v0,0x60
-bfc0091c:	34420060 	ori	v0,v0,0x60
-bfc00920:	ac820000 	sw	v0,0(a0)
-bfc00924:	3c0200d0 	lui	v0,0xd0
-bfc00928:	344200d0 	ori	v0,v0,0xd0
-bfc0092c:	ac820000 	sw	v0,0(a0)
-bfc00930:	3c020080 	lui	v0,0x80
-bfc00934:	34430080 	ori	v1,v0,0x80
-bfc00938:	8c860000 	lw	a2,0(a0)
-bfc0093c:	00000000 	nop
-bfc00940:	00c31024 	and	v0,a2,v1
-bfc00944:	1443fffc 	bne	v0,v1,bfc00938 <cfi_block_unlock+0x60>
-bfc00948:	3c020038 	lui	v0,0x38
-bfc0094c:	34420038 	ori	v0,v0,0x38
-bfc00950:	00c21024 	and	v0,a2,v0
-bfc00954:	10400003 	beqz	v0,bfc00964 <cfi_block_unlock+0x8c>
-bfc00958:	00001821 	move	v1,zero
-bfc0095c:	3c029010 	lui	v0,0x9010
-bfc00960:	00c21825 	or	v1,a2,v0
-bfc00964:	3c0200ff 	lui	v0,0xff
-bfc00968:	344200ff 	ori	v0,v0,0xff
-bfc0096c:	ac820000 	sw	v0,0(a0)
-bfc00970:	03e00008 	jr	ra
-bfc00974:	00601021 	move	v0,v1
-
-bfc00978 <cfi_program_single>:
-bfc00978:	8c820008 	lw	v0,8(a0)
-bfc0097c:	8c840000 	lw	a0,0(a0)
-bfc00980:	00021082 	srl	v0,v0,0x2
-bfc00984:	00a2102b 	sltu	v0,a1,v0
-bfc00988:	14400003 	bnez	v0,bfc00998 <cfi_program_single+0x20>
-bfc0098c:	3c028010 	lui	v0,0x8010
-bfc00990:	0bf0027c 	j	bfc009f0 <cfi_program_single+0x78>
-bfc00994:	34430002 	ori	v1,v0,0x2
-bfc00998:	00051080 	sll	v0,a1,0x2
-bfc0099c:	00822021 	addu	a0,a0,v0
-bfc009a0:	3c020040 	lui	v0,0x40
-bfc009a4:	34420040 	ori	v0,v0,0x40
-bfc009a8:	ac820000 	sw	v0,0(a0)
-bfc009ac:	3c020080 	lui	v0,0x80
-bfc009b0:	ac860000 	sw	a2,0(a0)
-bfc009b4:	34430080 	ori	v1,v0,0x80
-bfc009b8:	8c860000 	lw	a2,0(a0)
-bfc009bc:	00000000 	nop
-bfc009c0:	00c31024 	and	v0,a2,v1
-bfc009c4:	1443fffc 	bne	v0,v1,bfc009b8 <cfi_program_single+0x40>
-bfc009c8:	3c02001a 	lui	v0,0x1a
-bfc009cc:	3442001a 	ori	v0,v0,0x1a
-bfc009d0:	00c21024 	and	v0,a2,v0
-bfc009d4:	10400003 	beqz	v0,bfc009e4 <cfi_program_single+0x6c>
-bfc009d8:	00001821 	move	v1,zero
-bfc009dc:	3c029010 	lui	v0,0x9010
-bfc009e0:	00c21825 	or	v1,a2,v0
-bfc009e4:	3c0200ff 	lui	v0,0xff
-bfc009e8:	344200ff 	ori	v0,v0,0xff
-bfc009ec:	ac820000 	sw	v0,0(a0)
-bfc009f0:	03e00008 	jr	ra
-bfc009f4:	00601021 	move	v0,v1
-
-bfc009f8 <cfi_program_multi>:
-bfc009f8:	8c820008 	lw	v0,8(a0)
-bfc009fc:	27bdffe8 	addiu	sp,sp,-24
-bfc00a00:	00021082 	srl	v0,v0,0x2
-bfc00a04:	00a2102b 	sltu	v0,a1,v0
-bfc00a08:	afb40014 	sw	s4,20(sp)
-bfc00a0c:	afb30010 	sw	s3,16(sp)
-bfc00a10:	afb2000c 	sw	s2,12(sp)
-bfc00a14:	afb10008 	sw	s1,8(sp)
-bfc00a18:	afb00004 	sw	s0,4(sp)
-bfc00a1c:	0080c021 	move	t8,a0
-bfc00a20:	8c8e0000 	lw	t6,0(a0)
-bfc00a24:	14400004 	bnez	v0,bfc00a38 <cfi_program_multi+0x40>
-bfc00a28:	00c0a021 	move	s4,a2
-bfc00a2c:	3c028010 	lui	v0,0x8010
-bfc00a30:	0bf002e3 	j	bfc00b8c <cfi_program_multi+0x194>
-bfc00a34:	34440002 	ori	a0,v0,0x2
-bfc00a38:	8c820010 	lw	v0,16(a0)
-bfc00a3c:	00006821 	move	t5,zero
-bfc00a40:	2442ffff 	addiu	v0,v0,-1
-bfc00a44:	0002cc00 	sll	t9,v0,0x10
-bfc00a48:	3c0200e8 	lui	v0,0xe8
-bfc00a4c:	345300e8 	ori	s3,v0,0xe8
-bfc00a50:	3c020080 	lui	v0,0x80
-bfc00a54:	344f0080 	ori	t7,v0,0x80
-bfc00a58:	3c02001a 	lui	v0,0x1a
-bfc00a5c:	3446001a 	ori	a2,v0,0x1a
-bfc00a60:	3c0200d0 	lui	v0,0xd0
-bfc00a64:	345200d0 	ori	s2,v0,0xd0
-bfc00a68:	3c0200ff 	lui	v0,0xff
-bfc00a6c:	345100ff 	ori	s1,v0,0xff
-bfc00a70:	0bf002e1 	j	bfc00b84 <cfi_program_multi+0x18c>
-bfc00a74:	3c100001 	lui	s0,0x1
-bfc00a78:	01851023 	subu	v0,t4,a1
-bfc00a7c:	00505021 	addu	t2,v0,s0
-bfc00a80:	00ea102b 	sltu	v0,a3,t2
-bfc00a84:	10400002 	beqz	v0,bfc00a90 <cfi_program_multi+0x98>
-bfc00a88:	000c1080 	sll	v0,t4,0x2
-bfc00a8c:	00e05021 	move	t2,a3
-bfc00a90:	0bf002d7 	j	bfc00b5c <cfi_program_multi+0x164>
-bfc00a94:	01c25821 	addu	t3,t6,v0
-bfc00a98:	ad730000 	sw	s3,0(t3)
-bfc00a9c:	8d630000 	lw	v1,0(t3)
-bfc00aa0:	00000000 	nop
-bfc00aa4:	006f1024 	and	v0,v1,t7
-bfc00aa8:	144ffffc 	bne	v0,t7,bfc00a9c <cfi_program_multi+0xa4>
-bfc00aac:	00661024 	and	v0,v1,a2
-bfc00ab0:	14400026 	bnez	v0,bfc00b4c <cfi_program_multi+0x154>
-bfc00ab4:	3c029010 	lui	v0,0x9010
-bfc00ab8:	8f020014 	lw	v0,20(t8)
-bfc00abc:	00000000 	nop
-bfc00ac0:	00021882 	srl	v1,v0,0x2
-bfc00ac4:	006a102b 	sltu	v0,v1,t2
-bfc00ac8:	10400002 	beqz	v0,bfc00ad4 <cfi_program_multi+0xdc>
-bfc00acc:	01404021 	move	t0,t2
-bfc00ad0:	00604021 	move	t0,v1
-bfc00ad4:	2503ffff 	addiu	v1,t0,-1
-bfc00ad8:	00031400 	sll	v0,v1,0x10
-bfc00adc:	00431025 	or	v0,v0,v1
-bfc00ae0:	00052080 	sll	a0,a1,0x2
-bfc00ae4:	000d1880 	sll	v1,t5,0x2
-bfc00ae8:	02834821 	addu	t1,s4,v1
-bfc00aec:	ad620000 	sw	v0,0(t3)
-bfc00af0:	01c42021 	addu	a0,t6,a0
-bfc00af4:	0bf002c3 	j	bfc00b0c <cfi_program_multi+0x114>
-bfc00af8:	00001821 	move	v1,zero
-bfc00afc:	8d220000 	lw	v0,0(t1)
-bfc00b00:	25290004 	addiu	t1,t1,4
-bfc00b04:	ac820000 	sw	v0,0(a0)
-bfc00b08:	24840004 	addiu	a0,a0,4
-bfc00b0c:	0068102b 	sltu	v0,v1,t0
-bfc00b10:	1440fffa 	bnez	v0,bfc00afc <cfi_program_multi+0x104>
-bfc00b14:	24630001 	addiu	v1,v1,1
-bfc00b18:	01a86821 	addu	t5,t5,t0
-bfc00b1c:	00a82821 	addu	a1,a1,t0
-bfc00b20:	00e83823 	subu	a3,a3,t0
-bfc00b24:	ad720000 	sw	s2,0(t3)
-bfc00b28:	8d630000 	lw	v1,0(t3)
-bfc00b2c:	00000000 	nop
-bfc00b30:	006f1024 	and	v0,v1,t7
-bfc00b34:	144ffffc 	bne	v0,t7,bfc00b28 <cfi_program_multi+0x130>
-bfc00b38:	00661024 	and	v0,v1,a2
-bfc00b3c:	10400005 	beqz	v0,bfc00b54 <cfi_program_multi+0x15c>
-bfc00b40:	01485023 	subu	t2,t2,t0
-bfc00b44:	01485021 	addu	t2,t2,t0
-bfc00b48:	3c029010 	lui	v0,0x9010
-bfc00b4c:	0bf002d9 	j	bfc00b64 <cfi_program_multi+0x16c>
-bfc00b50:	00622025 	or	a0,v1,v0
-bfc00b54:	ad710000 	sw	s1,0(t3)
-bfc00b58:	00002021 	move	a0,zero
-bfc00b5c:	1540ffce 	bnez	t2,bfc00a98 <cfi_program_multi+0xa0>
-bfc00b60:	00000000 	nop
-bfc00b64:	04810007 	bgez	a0,bfc00b84 <cfi_program_multi+0x18c>
-bfc00b68:	000c1880 	sll	v1,t4,0x2
-bfc00b6c:	3c0200ff 	lui	v0,0xff
-bfc00b70:	01c31821 	addu	v1,t6,v1
-bfc00b74:	344200ff 	ori	v0,v0,0xff
-bfc00b78:	ac620000 	sw	v0,0(v1)
-bfc00b7c:	0bf002e4 	j	bfc00b90 <cfi_program_multi+0x198>
-bfc00b80:	00801021 	move	v0,a0
-bfc00b84:	14e0ffbc 	bnez	a3,bfc00a78 <cfi_program_multi+0x80>
-bfc00b88:	00b96024 	and	t4,a1,t9
-bfc00b8c:	00801021 	move	v0,a0
-bfc00b90:	8fb40014 	lw	s4,20(sp)
-bfc00b94:	8fb30010 	lw	s3,16(sp)
-bfc00b98:	8fb2000c 	lw	s2,12(sp)
-bfc00b9c:	8fb10008 	lw	s1,8(sp)
-bfc00ba0:	8fb00004 	lw	s0,4(sp)
-bfc00ba4:	03e00008 	jr	ra
-bfc00ba8:	27bd0018 	addiu	sp,sp,24
-
-bfc00bac <flash_find>:
-bfc00bac:	27bdffe0 	addiu	sp,sp,-32
-bfc00bb0:	afbf001c 	sw	ra,28(sp)
-bfc00bb4:	ac850000 	sw	a1,0(a0)
-bfc00bb8:	24820008 	addiu	v0,a0,8
-bfc00bbc:	0bf002f3 	j	bfc00bcc <flash_find+0x20>
-bfc00bc0:	24830020 	addiu	v1,a0,32
-bfc00bc4:	a0400000 	sb	zero,0(v0)
-bfc00bc8:	24420001 	addiu	v0,v0,1
-bfc00bcc:	1443fffd 	bne	v0,v1,bfc00bc4 <flash_find+0x18>
-bfc00bd0:	00000000 	nop
-bfc00bd4:	3c021234 	lui	v0,0x1234
-bfc00bd8:	34425678 	ori	v0,v0,0x5678
-bfc00bdc:	00021e02 	srl	v1,v0,0x18
-bfc00be0:	afa20010 	sw	v0,16(sp)
-bfc00be4:	24020012 	li	v0,18
-bfc00be8:	14620003 	bne	v1,v0,bfc00bf8 <flash_find+0x4c>
-bfc00bec:	ac800004 	sw	zero,4(a0)
-bfc00bf0:	24020001 	li	v0,1
-bfc00bf4:	ac820004 	sw	v0,4(a0)
-bfc00bf8:	0ff00185 	jal	bfc00614 <cfi_find>
-bfc00bfc:	00000000 	nop
-bfc00c00:	8fbf001c 	lw	ra,28(sp)
-bfc00c04:	00000000 	nop
-bfc00c08:	03e00008 	jr	ra
-bfc00c0c:	27bd0020 	addiu	sp,sp,32
-
-bfc00c10 <flash_erase>:
-bfc00c10:	27bdffd8 	addiu	sp,sp,-40
-bfc00c14:	30c20003 	andi	v0,a2,0x3
-bfc00c18:	afb2001c 	sw	s2,28(sp)
-bfc00c1c:	afbf0024 	sw	ra,36(sp)
-bfc00c20:	afb30020 	sw	s3,32(sp)
-bfc00c24:	afb10018 	sw	s1,24(sp)
-bfc00c28:	afb00014 	sw	s0,20(sp)
-bfc00c2c:	10400004 	beqz	v0,bfc00c40 <flash_erase+0x30>
-bfc00c30:	00809021 	move	s2,a0
-bfc00c34:	00061082 	srl	v0,a2,0x2
-bfc00c38:	24420001 	addiu	v0,v0,1
-bfc00c3c:	00023080 	sll	a2,v0,0x2
-bfc00c40:	00c59821 	addu	s3,a2,a1
-bfc00c44:	0bf00324 	j	bfc00c90 <flash_erase+0x80>
-bfc00c48:	00a08821 	move	s1,a1
-bfc00c4c:	0ff001ca 	jal	bfc00728 <cfi_block_is_locked>
-bfc00c50:	00000000 	nop
-bfc00c54:	02402021 	move	a0,s2
-bfc00c58:	10400005 	beqz	v0,bfc00c70 <flash_erase+0x60>
-bfc00c5c:	02002821 	move	a1,s0
-bfc00c60:	0ff00236 	jal	bfc008d8 <cfi_block_unlock>
-bfc00c64:	00000000 	nop
-bfc00c68:	04400011 	bltz	v0,bfc00cb0 <flash_erase+0xa0>
-bfc00c6c:	00401821 	move	v1,v0
-bfc00c70:	02002821 	move	a1,s0
-bfc00c74:	0ff001e6 	jal	bfc00798 <cfi_block_erase>
-bfc00c78:	02402021 	move	a0,s2
-bfc00c7c:	0440000c 	bltz	v0,bfc00cb0 <flash_erase+0xa0>
-bfc00c80:	00401821 	move	v1,v0
-bfc00c84:	8e42000c 	lw	v0,12(s2)
-bfc00c88:	00000000 	nop
-bfc00c8c:	02228821 	addu	s1,s1,v0
-bfc00c90:	001117c3 	sra	v0,s1,0x1f
-bfc00c94:	00021782 	srl	v0,v0,0x1e
-bfc00c98:	00511021 	addu	v0,v0,s1
-bfc00c9c:	00028083 	sra	s0,v0,0x2
-bfc00ca0:	0233102b 	sltu	v0,s1,s3
-bfc00ca4:	02402021 	move	a0,s2
-bfc00ca8:	1440ffe8 	bnez	v0,bfc00c4c <flash_erase+0x3c>
-bfc00cac:	02002821 	move	a1,s0
-bfc00cb0:	8fbf0024 	lw	ra,36(sp)
-bfc00cb4:	00601021 	move	v0,v1
-bfc00cb8:	8fb30020 	lw	s3,32(sp)
-bfc00cbc:	8fb2001c 	lw	s2,28(sp)
-bfc00cc0:	8fb10018 	lw	s1,24(sp)
-bfc00cc4:	8fb00014 	lw	s0,20(sp)
-bfc00cc8:	03e00008 	jr	ra
-bfc00ccc:	27bd0028 	addiu	sp,sp,40
-
-bfc00cd0 <flash_program>:
-bfc00cd0:	30e20003 	andi	v0,a3,0x3
-bfc00cd4:	10400003 	beqz	v0,bfc00ce4 <flash_program+0x14>
-bfc00cd8:	00071082 	srl	v0,a3,0x2
-bfc00cdc:	24420001 	addiu	v0,v0,1
-bfc00ce0:	00023880 	sll	a3,v0,0x2
-bfc00ce4:	00052882 	srl	a1,a1,0x2
-bfc00ce8:	0bf0027e 	j	bfc009f8 <cfi_program_multi>
-bfc00cec:	00073882 	srl	a3,a3,0x2
-
-bfc00cf0 <flash_verify>:
-bfc00cf0:	8c820000 	lw	v0,0(a0)
-bfc00cf4:	00002021 	move	a0,zero
-bfc00cf8:	0bf00347 	j	bfc00d1c <flash_verify+0x2c>
-bfc00cfc:	00454021 	addu	t0,v0,a1
-bfc00d00:	90630000 	lbu	v1,0(v1)
-bfc00d04:	90a20000 	lbu	v0,0(a1)
-bfc00d08:	00000000 	nop
-bfc00d0c:	10620003 	beq	v1,v0,bfc00d1c <flash_verify+0x2c>
-bfc00d10:	3c028010 	lui	v0,0x8010
-bfc00d14:	03e00008 	jr	ra
-bfc00d18:	34420003 	ori	v0,v0,0x3
-bfc00d1c:	0087102b 	sltu	v0,a0,a3
-bfc00d20:	01041821 	addu	v1,t0,a0
-bfc00d24:	00c42821 	addu	a1,a2,a0
-bfc00d28:	1440fff5 	bnez	v0,bfc00d00 <flash_verify+0x10>
-bfc00d2c:	24840001 	addiu	a0,a0,1
-bfc00d30:	03e00008 	jr	ra
-bfc00d34:	00000000 	nop
-
-bfc00d38 <flash_get_blocknum_by_offset>:
-bfc00d38:	8c82000c 	lw	v0,12(a0)
-bfc00d3c:	00000000 	nop
-bfc00d40:	14400002 	bnez	v0,bfc00d4c <flash_get_blocknum_by_offset+0x14>
-bfc00d44:	00a2001b 	divu	zero,a1,v0
-bfc00d48:	0007000d 	break	0x7
-bfc00d4c:	00001010 	mfhi	v0
-bfc00d50:	0002102b 	sltu	v0,zero,v0
-bfc00d54:	00002812 	mflo	a1
-bfc00d58:	03e00008 	jr	ra
-bfc00d5c:	00a21021 	addu	v0,a1,v0
-
-bfc00d60 <flash_get_offset_by_blocknum>:
-bfc00d60:	8c830010 	lw	v1,16(a0)
-bfc00d64:	00000000 	nop
-bfc00d68:	00a3102b 	sltu	v0,a1,v1
-bfc00d6c:	14400002 	bnez	v0,bfc00d78 <flash_get_offset_by_blocknum+0x18>
-bfc00d70:	00000000 	nop
-bfc00d74:	2465ffff 	addiu	a1,v1,-1
-bfc00d78:	8c82000c 	lw	v0,12(a0)
-bfc00d7c:	00000000 	nop
-bfc00d80:	00a20018 	mult	a1,v0
-bfc00d84:	00001012 	mflo	v0
-bfc00d88:	03e00008 	jr	ra
-bfc00d8c:	00000000 	nop
-
-bfc00d90 <flash_get_offset_blockaligned>:
-bfc00d90:	27bdffe8 	addiu	sp,sp,-24
-bfc00d94:	afbf0014 	sw	ra,20(sp)
-bfc00d98:	afb00010 	sw	s0,16(sp)
-bfc00d9c:	0ff0034e 	jal	bfc00d38 <flash_get_blocknum_by_offset>
-bfc00da0:	00808021 	move	s0,a0
-bfc00da4:	8e03000c 	lw	v1,12(s0)
-bfc00da8:	8fbf0014 	lw	ra,20(sp)
-bfc00dac:	00430018 	mult	v0,v1
-bfc00db0:	8fb00010 	lw	s0,16(sp)
-bfc00db4:	00001012 	mflo	v0
-bfc00db8:	03e00008 	jr	ra
-bfc00dbc:	27bd0018 	addiu	sp,sp,24
-
-bfc00dc0 <h2i>:
-bfc00dc0:	90830000 	lbu	v1,0(a0)
-bfc00dc4:	00000000 	nop
-bfc00dc8:	2c620041 	sltiu	v0,v1,65
-bfc00dcc:	14400002 	bnez	v0,bfc00dd8 <h2i+0x18>
-bfc00dd0:	2462ffd0 	addiu	v0,v1,-48
-bfc00dd4:	2462ffc9 	addiu	v0,v1,-55
-bfc00dd8:	90840001 	lbu	a0,1(a0)
-bfc00ddc:	304200ff 	andi	v0,v0,0xff
-bfc00de0:	304300ff 	andi	v1,v0,0xff
-bfc00de4:	2c820041 	sltiu	v0,a0,65
-bfc00de8:	14400003 	bnez	v0,bfc00df8 <h2i+0x38>
-bfc00dec:	00000000 	nop
-bfc00df0:	0bf0037f 	j	bfc00dfc <h2i+0x3c>
-bfc00df4:	2482ffc9 	addiu	v0,a0,-55
-bfc00df8:	2482ffd0 	addiu	v0,a0,-48
-bfc00dfc:	304400ff 	andi	a0,v0,0xff
-bfc00e00:	00031100 	sll	v0,v1,0x4
-bfc00e04:	00821025 	or	v0,a0,v0
-bfc00e08:	03e00008 	jr	ra
-bfc00e0c:	304200ff 	andi	v0,v0,0xff
-
-bfc00e10 <decode_srec>:
-bfc00e10:	10c00094 	beqz	a2,bfc01064 <decode_srec+0x254>
-bfc00e14:	00805021 	move	t2,a0
-bfc00e18:	24020003 	li	v0,3
-bfc00e1c:	ac820008 	sw	v0,8(a0)
-bfc00e20:	90a40001 	lbu	a0,1(a1)
-bfc00e24:	00000000 	nop
-bfc00e28:	2482ffcf 	addiu	v0,a0,-49
-bfc00e2c:	304200ff 	andi	v0,v0,0xff
-bfc00e30:	2c420003 	sltiu	v0,v0,3
-bfc00e34:	10400005 	beqz	v0,bfc00e4c <decode_srec+0x3c>
-bfc00e38:	2482ffc9 	addiu	v0,a0,-55
-bfc00e3c:	24020002 	li	v0,2
-bfc00e40:	ad420008 	sw	v0,8(t2)
-bfc00e44:	0bf003a1 	j	bfc00e84 <decode_srec+0x74>
-bfc00e48:	2489ffd1 	addiu	t1,a0,-47
-bfc00e4c:	304200ff 	andi	v0,v0,0xff
-bfc00e50:	2c420003 	sltiu	v0,v0,3
-bfc00e54:	10400006 	beqz	v0,bfc00e70 <decode_srec+0x60>
-bfc00e58:	24020030 	li	v0,48
-bfc00e5c:	2402003b 	li	v0,59
-bfc00e60:	00444823 	subu	t1,v0,a0
-bfc00e64:	24020004 	li	v0,4
-bfc00e68:	0bf003a1 	j	bfc00e84 <decode_srec+0x74>
-bfc00e6c:	ad420008 	sw	v0,8(t2)
-bfc00e70:	14820004 	bne	a0,v0,bfc00e84 <decode_srec+0x74>
-bfc00e74:	00004821 	move	t1,zero
-bfc00e78:	24020001 	li	v0,1
-bfc00e7c:	ad420008 	sw	v0,8(t2)
-bfc00e80:	24090002 	li	t1,2
-bfc00e84:	90a30002 	lbu	v1,2(a1)
-bfc00e88:	00000000 	nop
-bfc00e8c:	2c620041 	sltiu	v0,v1,65
-bfc00e90:	10400003 	beqz	v0,bfc00ea0 <decode_srec+0x90>
-bfc00e94:	24a40002 	addiu	a0,a1,2
-bfc00e98:	0bf003a9 	j	bfc00ea4 <decode_srec+0x94>
-bfc00e9c:	2462ffd0 	addiu	v0,v1,-48
-bfc00ea0:	2462ffc9 	addiu	v0,v1,-55
-bfc00ea4:	90830001 	lbu	v1,1(a0)
-bfc00ea8:	304200ff 	andi	v0,v0,0xff
-bfc00eac:	304400ff 	andi	a0,v0,0xff
-bfc00eb0:	2c620041 	sltiu	v0,v1,65
-bfc00eb4:	10400002 	beqz	v0,bfc00ec0 <decode_srec+0xb0>
-bfc00eb8:	2462ffc9 	addiu	v0,v1,-55
-bfc00ebc:	2462ffd0 	addiu	v0,v1,-48
-bfc00ec0:	304300ff 	andi	v1,v0,0xff
-bfc00ec4:	00041100 	sll	v0,a0,0x4
-bfc00ec8:	00621025 	or	v0,v1,v0
-bfc00ecc:	304200ff 	andi	v0,v0,0xff
-bfc00ed0:	ad420004 	sw	v0,4(t2)
-bfc00ed4:	ad400000 	sw	zero,0(t2)
-bfc00ed8:	00405821 	move	t3,v0
-bfc00edc:	00a03021 	move	a2,a1
-bfc00ee0:	0bf003d5 	j	bfc00f54 <decode_srec+0x144>
-bfc00ee4:	00003821 	move	a3,zero
-bfc00ee8:	90c20004 	lbu	v0,4(a2)
-bfc00eec:	00000000 	nop
-bfc00ef0:	2443ffc9 	addiu	v1,v0,-55
-bfc00ef4:	2444ffd0 	addiu	a0,v0,-48
-bfc00ef8:	2c420041 	sltiu	v0,v0,65
-bfc00efc:	10400002 	beqz	v0,bfc00f08 <decode_srec+0xf8>
-bfc00f00:	306300ff 	andi	v1,v1,0xff
-bfc00f04:	308300ff 	andi	v1,a0,0xff
-bfc00f08:	90c20005 	lbu	v0,5(a2)
-bfc00f0c:	306800ff 	andi	t0,v1,0xff
-bfc00f10:	2444ffc9 	addiu	a0,v0,-55
-bfc00f14:	2443ffd0 	addiu	v1,v0,-48
-bfc00f18:	2c420041 	sltiu	v0,v0,65
-bfc00f1c:	10400002 	beqz	v0,bfc00f28 <decode_srec+0x118>
-bfc00f20:	308400ff 	andi	a0,a0,0xff
-bfc00f24:	306400ff 	andi	a0,v1,0xff
-bfc00f28:	8d430000 	lw	v1,0(t2)
-bfc00f2c:	00081100 	sll	v0,t0,0x4
-bfc00f30:	00821025 	or	v0,a0,v0
-bfc00f34:	304200ff 	andi	v0,v0,0xff
-bfc00f38:	00031a00 	sll	v1,v1,0x8
-bfc00f3c:	004b2021 	addu	a0,v0,t3
-bfc00f40:	00431025 	or	v0,v0,v1
-bfc00f44:	ad420000 	sw	v0,0(t2)
-bfc00f48:	308b00ff 	andi	t3,a0,0xff
-bfc00f4c:	24e70001 	addiu	a3,a3,1
-bfc00f50:	24c60002 	addiu	a2,a2,2
-bfc00f54:	00e9102a 	slt	v0,a3,t1
-bfc00f58:	1440ffe3 	bnez	v0,bfc00ee8 <decode_srec+0xd8>
-bfc00f5c:	25220002 	addiu	v0,t1,2
-bfc00f60:	8d440004 	lw	a0,4(t2)
-bfc00f64:	00021040 	sll	v0,v0,0x1
-bfc00f68:	00091827 	nor	v1,zero,t1
-bfc00f6c:	00832021 	addu	a0,a0,v1
-bfc00f70:	00a21021 	addu	v0,a1,v0
-bfc00f74:	ad440004 	sw	a0,4(t2)
-bfc00f78:	ad42000c 	sw	v0,12(t2)
-bfc00f7c:	0bf003f9 	j	bfc00fe4 <decode_srec+0x1d4>
-bfc00f80:	00003021 	move	a2,zero
-bfc00f84:	90e20000 	lbu	v0,0(a3)
-bfc00f88:	00000000 	nop
-bfc00f8c:	2444ffc9 	addiu	a0,v0,-55
-bfc00f90:	2445ffd0 	addiu	a1,v0,-48
-bfc00f94:	2c420041 	sltiu	v0,v0,65
-bfc00f98:	10400002 	beqz	v0,bfc00fa4 <decode_srec+0x194>
-bfc00f9c:	308400ff 	andi	a0,a0,0xff
-bfc00fa0:	30a400ff 	andi	a0,a1,0xff
-bfc00fa4:	90e20001 	lbu	v0,1(a3)
-bfc00fa8:	308700ff 	andi	a3,a0,0xff
-bfc00fac:	2445ffc9 	addiu	a1,v0,-55
-bfc00fb0:	2444ffd0 	addiu	a0,v0,-48
-bfc00fb4:	2c420041 	sltiu	v0,v0,65
-bfc00fb8:	14400002 	bnez	v0,bfc00fc4 <decode_srec+0x1b4>
-bfc00fbc:	308400ff 	andi	a0,a0,0xff
-bfc00fc0:	30a400ff 	andi	a0,a1,0xff
-bfc00fc4:	00071100 	sll	v0,a3,0x4
-bfc00fc8:	00821025 	or	v0,a0,v0
-bfc00fcc:	304200ff 	andi	v0,v0,0xff
-bfc00fd0:	00661821 	addu	v1,v1,a2
-bfc00fd4:	004b2021 	addu	a0,v0,t3
-bfc00fd8:	a0620000 	sb	v0,0(v1)
-bfc00fdc:	308b00ff 	andi	t3,a0,0xff
-bfc00fe0:	24c60001 	addiu	a2,a2,1
-bfc00fe4:	8d420004 	lw	v0,4(t2)
-bfc00fe8:	8d43000c 	lw	v1,12(t2)
-bfc00fec:	00062040 	sll	a0,a2,0x1
-bfc00ff0:	00c2102a 	slt	v0,a2,v0
-bfc00ff4:	1440ffe3 	bnez	v0,bfc00f84 <decode_srec+0x174>
-bfc00ff8:	00643821 	addu	a3,v1,a0
-bfc00ffc:	90e40000 	lbu	a0,0(a3)
-bfc01000:	00000000 	nop
-bfc01004:	2c820041 	sltiu	v0,a0,65
-bfc01008:	10400003 	beqz	v0,bfc01018 <decode_srec+0x208>
-bfc0100c:	00e01821 	move	v1,a3
-bfc01010:	0bf00407 	j	bfc0101c <decode_srec+0x20c>
-bfc01014:	2482ffd0 	addiu	v0,a0,-48
-bfc01018:	2482ffc9 	addiu	v0,a0,-55
-bfc0101c:	90630001 	lbu	v1,1(v1)
-bfc01020:	304200ff 	andi	v0,v0,0xff
-bfc01024:	304400ff 	andi	a0,v0,0xff
-bfc01028:	2c620041 	sltiu	v0,v1,65
-bfc0102c:	10400002 	beqz	v0,bfc01038 <decode_srec+0x228>
-bfc01030:	2462ffc9 	addiu	v0,v1,-55
-bfc01034:	2462ffd0 	addiu	v0,v1,-48
-bfc01038:	304200ff 	andi	v0,v0,0xff
-bfc0103c:	00041900 	sll	v1,a0,0x4
-bfc01040:	00431825 	or	v1,v0,v1
-bfc01044:	000b1027 	nor	v0,zero,t3
-bfc01048:	304200ff 	andi	v0,v0,0xff
-bfc0104c:	306300ff 	andi	v1,v1,0xff
-bfc01050:	14430004 	bne	v0,v1,bfc01064 <decode_srec+0x254>
-bfc01054:	00000000 	nop
-bfc01058:	8d420008 	lw	v0,8(t2)
-bfc0105c:	03e00008 	jr	ra
-bfc01060:	00000000 	nop
-bfc01064:	03e00008 	jr	ra
-bfc01068:	00001021 	move	v0,zero
-
-bfc0106c <Jump_to>:
-bfc0106c:	00800008 	jr	a0
-bfc01070:	00000000 	nop
-bfc01074:	03e00008 	jr	ra
-bfc01078:	00000000 	nop
-
-bfc0107c <Exec_at>:
-bfc0107c:	3c1a1000 	lui	k0,0x1000
-bfc01080:	409a6000 	mtc0	k0,c0_sr
-bfc01084:	00800008 	jr	a0
-bfc01088:	42000010 	rfe
-bfc0108c:	03e00008 	jr	ra
-bfc01090:	00000000 	nop
-
-bfc01094 <Exec_RE_at>:
-bfc01094:	401a6000 	mfc0	k0,c0_sr
-bfc01098:	3c1bffbf 	lui	k1,0xffbf
-bfc0109c:	377bffff 	ori	k1,k1,0xffff
-bfc010a0:	035bd024 	and	k0,k0,k1
-bfc010a4:	3c1b0200 	lui	k1,0x200
-bfc010a8:	035bd025 	or	k0,k0,k1
-bfc010ac:	409a6000 	mtc0	k0,c0_sr
-bfc010b0:	00800008 	jr	a0
-bfc010b4:	42000010 	rfe
-bfc010b8:	03e00008 	jr	ra
-bfc010bc:	00000000 	nop
-
-bfc010c0 <srec_getline>:
-bfc010c0:	27bdffd8 	addiu	sp,sp,-40
-bfc010c4:	afb30020 	sw	s3,32(sp)
-bfc010c8:	afb10018 	sw	s1,24(sp)
-bfc010cc:	afb00014 	sw	s0,20(sp)
-bfc010d0:	afbf0024 	sw	ra,36(sp)
-bfc010d4:	afb2001c 	sw	s2,28(sp)
-bfc010d8:	00809821 	move	s3,a0
-bfc010dc:	24110073 	li	s1,115
-bfc010e0:	24100053 	li	s0,83
-bfc010e4:	0ff00081 	jal	bfc00204 <readchar>
-bfc010e8:	00000000 	nop
-bfc010ec:	14510005 	bne	v0,s1,bfc01104 <srec_getline+0x44>
-bfc010f0:	00000000 	nop
-bfc010f4:	00008021 	move	s0,zero
-bfc010f8:	2412000a 	li	s2,10
-bfc010fc:	0bf00449 	j	bfc01124 <srec_getline+0x64>
-bfc01100:	2411000d 	li	s1,13
-bfc01104:	1450fff7 	bne	v0,s0,bfc010e4 <srec_getline+0x24>
-bfc01108:	00000000 	nop
-bfc0110c:	0bf0043e 	j	bfc010f8 <srec_getline+0x38>
-bfc01110:	00008021 	move	s0,zero
-bfc01114:	0ff00081 	jal	bfc00204 <readchar>
-bfc01118:	a0620000 	sb	v0,0(v1)
-bfc0111c:	10510003 	beq	v0,s1,bfc0112c <srec_getline+0x6c>
-bfc01120:	26100001 	addiu	s0,s0,1
-bfc01124:	1452fffb 	bne	v0,s2,bfc01114 <srec_getline+0x54>
-bfc01128:	02701821 	addu	v1,s3,s0
-bfc0112c:	8fbf0024 	lw	ra,36(sp)
-bfc01130:	02001021 	move	v0,s0
-bfc01134:	8fb30020 	lw	s3,32(sp)
-bfc01138:	8fb2001c 	lw	s2,28(sp)
-bfc0113c:	8fb10018 	lw	s1,24(sp)
-bfc01140:	8fb00014 	lw	s0,20(sp)
-bfc01144:	03e00008 	jr	ra
-bfc01148:	27bd0028 	addiu	sp,sp,40
-
-bfc0114c <main>:
-bfc0114c:	27bdfd98 	addiu	sp,sp,-616
-bfc01150:	27a40140 	addiu	a0,sp,320
-bfc01154:	00002821 	move	a1,zero
-bfc01158:	24060100 	li	a2,256
-bfc0115c:	afb20248 	sw	s2,584(sp)
-bfc01160:	afb10244 	sw	s1,580(sp)
-bfc01164:	afb00240 	sw	s0,576(sp)
-bfc01168:	3c11a000 	lui	s1,0xa000
-bfc0116c:	afbf0264 	sw	ra,612(sp)
-bfc01170:	afbe0260 	sw	s8,608(sp)
-bfc01174:	afb7025c 	sw	s7,604(sp)
-bfc01178:	afb60258 	sw	s6,600(sp)
-bfc0117c:	afb50254 	sw	s5,596(sp)
-bfc01180:	afb40250 	sw	s4,592(sp)
-bfc01184:	0ff0056a 	jal	bfc015a8 <memset>
-bfc01188:	afb3024c 	sw	s3,588(sp)
-bfc0118c:	3c036000 	lui	v1,0x6000
-bfc01190:	36220004 	ori	v0,s1,0x4
-bfc01194:	3463b1ff 	ori	v1,v1,0xb1ff
-bfc01198:	ac430000 	sw	v1,0(v0)
-bfc0119c:	3c022000 	lui	v0,0x2000
-bfc011a0:	27b20020 	addiu	s2,sp,32
-bfc011a4:	34421000 	ori	v0,v0,0x1000
-bfc011a8:	ae220000 	sw	v0,0(s1)
-bfc011ac:	02402021 	move	a0,s2
-bfc011b0:	3c05a400 	lui	a1,0xa400
-bfc011b4:	8e300000 	lw	s0,0(s1)
-bfc011b8:	0ff002eb 	jal	bfc00bac <flash_find>
-bfc011bc:	00000000 	nop
-bfc011c0:	04410004 	bgez	v0,bfc011d4 <main+0x88>
-bfc011c4:	00102c02 	srl	a1,s0,0x10
-bfc011c8:	3c04bfc0 	lui	a0,0xbfc0
-bfc011cc:	0bf00493 	j	bfc0124c <main+0x100>
-bfc011d0:	248416a0 	addiu	a0,a0,5792
-bfc011d4:	02402021 	move	a0,s2
-bfc011d8:	0ff00358 	jal	bfc00d60 <flash_get_offset_by_blocknum>
-bfc011dc:	30a5007f 	andi	a1,a1,0x7f
-bfc011e0:	00409021 	move	s2,v0
-bfc011e4:	8e220000 	lw	v0,0(s1)
-bfc011e8:	3c030800 	lui	v1,0x800
-bfc011ec:	00431024 	and	v0,v0,v1
-bfc011f0:	14400044 	bnez	v0,bfc01304 <main+0x1b8>
-bfc011f4:	3c11bfc0 	lui	s1,0xbfc0
-bfc011f8:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc011fc:	26241754 	addiu	a0,s1,5972
-bfc01200:	3c02a400 	lui	v0,0xa400
-bfc01204:	02428021 	addu	s0,s2,v0
-bfc01208:	8e030000 	lw	v1,0(s0)
-bfc0120c:	3c023149 	lui	v0,0x3149
-bfc01210:	3442464a 	ori	v0,v0,0x464a
-bfc01214:	10620011 	beq	v1,v0,bfc0125c <main+0x110>
-bfc01218:	3c024a46 	lui	v0,0x4a46
-bfc0121c:	34424931 	ori	v0,v0,0x4931
-bfc01220:	1062000e 	beq	v1,v0,bfc0125c <main+0x110>
-bfc01224:	00000000 	nop
-bfc01228:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0122c:	26241754 	addiu	a0,s1,5972
-bfc01230:	3c04bfc0 	lui	a0,0xbfc0
-bfc01234:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01238:	248416c8 	addiu	a0,a0,5832
-bfc0123c:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01240:	02402021 	move	a0,s2
-bfc01244:	3c04bfc0 	lui	a0,0xbfc0
-bfc01248:	248416e0 	addiu	a0,a0,5856
-bfc0124c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01250:	00000000 	nop
-bfc01254:	0bf0055e 	j	bfc01578 <main+0x42c>
-bfc01258:	24020001 	li	v0,1
-bfc0125c:	3c04bfc0 	lui	a0,0xbfc0
-bfc01260:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01264:	248416ec 	addiu	a0,a0,5868
-bfc01268:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc0126c:	02402021 	move	a0,s2
-bfc01270:	3c04bfc0 	lui	a0,0xbfc0
-bfc01274:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01278:	24841710 	addiu	a0,a0,5904
-bfc0127c:	8e02000c 	lw	v0,12(s0)
-bfc01280:	8e110004 	lw	s1,4(s0)
-bfc01284:	00024082 	srl	t0,v0,0x2
-bfc01288:	8e070008 	lw	a3,8(s0)
-bfc0128c:	00002021 	move	a0,zero
-bfc01290:	0bf004a9 	j	bfc012a4 <main+0x158>
-bfc01294:	00001821 	move	v1,zero
-bfc01298:	8cc20000 	lw	v0,0(a2)
-bfc0129c:	00000000 	nop
-bfc012a0:	aca20000 	sw	v0,0(a1)
-bfc012a4:	0088102b 	sltu	v0,a0,t0
-bfc012a8:	00673021 	addu	a2,v1,a3
-bfc012ac:	00712821 	addu	a1,v1,s1
-bfc012b0:	24840001 	addiu	a0,a0,1
-bfc012b4:	1440fff8 	bnez	v0,bfc01298 <main+0x14c>
-bfc012b8:	24630004 	addiu	v1,v1,4
-bfc012bc:	3c04bfc0 	lui	a0,0xbfc0
-bfc012c0:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012c4:	24841718 	addiu	a0,a0,5912
-bfc012c8:	3c04bfc0 	lui	a0,0xbfc0
-bfc012cc:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012d0:	24841720 	addiu	a0,a0,5920
-bfc012d4:	8e040004 	lw	a0,4(s0)
-bfc012d8:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc012dc:	00000000 	nop
-bfc012e0:	3c04bfc0 	lui	a0,0xbfc0
-bfc012e4:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc012e8:	24841754 	addiu	a0,a0,5972
-bfc012ec:	3c1a1000 	lui	k0,0x1000
-bfc012f0:	409a6000 	mtc0	k0,c0_sr
-bfc012f4:	02200008 	jr	s1
-bfc012f8:	42000010 	rfe
-bfc012fc:	0bf0055e 	j	bfc01578 <main+0x42c>
-bfc01300:	00001021 	move	v0,zero
-bfc01304:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01308:	26241754 	addiu	a0,s1,5972
-bfc0130c:	3c04bfc0 	lui	a0,0xbfc0
-bfc01310:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01314:	2484172c 	addiu	a0,a0,5932
-bfc01318:	3c024000 	lui	v0,0x4000
-bfc0131c:	3c034010 	lui	v1,0x4010
-bfc01320:	ac400000 	sw	zero,0(v0)
-bfc01324:	24420004 	addiu	v0,v0,4
-bfc01328:	1443fffd 	bne	v0,v1,bfc01320 <main+0x1d4>
-bfc0132c:	00009821 	move	s3,zero
-bfc01330:	3c02bfc0 	lui	v0,0xbfc0
-bfc01334:	245516c4 	addiu	s5,v0,5828
-bfc01338:	3c02bfc0 	lui	v0,0xbfc0
-bfc0133c:	24561718 	addiu	s6,v0,5912
-bfc01340:	3c02bfc0 	lui	v0,0xbfc0
-bfc01344:	245e17cc 	addiu	s8,v0,6092
-bfc01348:	3c02bfc0 	lui	v0,0xbfc0
-bfc0134c:	245717ec 	addiu	s7,v0,6124
-bfc01350:	3c04bfc0 	lui	a0,0xbfc0
-bfc01354:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01358:	2484174c 	addiu	a0,a0,5964
-bfc0135c:	3c14bfc0 	lui	s4,0xbfc0
-bfc01360:	27b00040 	addiu	s0,sp,64
-bfc01364:	0ff00430 	jal	bfc010c0 <srec_getline>
-bfc01368:	02002021 	move	a0,s0
-bfc0136c:	00403021 	move	a2,v0
-bfc01370:	02002821 	move	a1,s0
-bfc01374:	27a40010 	addiu	a0,sp,16
-bfc01378:	0ff00384 	jal	bfc00e10 <decode_srec>
-bfc0137c:	00408821 	move	s1,v0
-bfc01380:	00401821 	move	v1,v0
-bfc01384:	24020002 	li	v0,2
-bfc01388:	10620005 	beq	v1,v0,bfc013a0 <main+0x254>
-bfc0138c:	24020004 	li	v0,4
-bfc01390:	1462ffef 	bne	v1,v0,bfc01350 <main+0x204>
-bfc01394:	00000000 	nop
-bfc01398:	0bf004fd 	j	bfc013f4 <main+0x2a8>
-bfc0139c:	3c04bfc0 	lui	a0,0xbfc0
-bfc013a0:	8fa50010 	lw	a1,16(sp)
-bfc013a4:	8fa60014 	lw	a2,20(sp)
-bfc013a8:	0bf004f2 	j	bfc013c8 <main+0x27c>
-bfc013ac:	00001821 	move	v1,zero
-bfc013b0:	8fa2001c 	lw	v0,28(sp)
-bfc013b4:	00000000 	nop
-bfc013b8:	00431021 	addu	v0,v0,v1
-bfc013bc:	90420000 	lbu	v0,0(v0)
-bfc013c0:	24630001 	addiu	v1,v1,1
-bfc013c4:	a0820000 	sb	v0,0(a0)
-bfc013c8:	8fa20014 	lw	v0,20(sp)
-bfc013cc:	00000000 	nop
-bfc013d0:	0062102b 	sltu	v0,v1,v0
-bfc013d4:	1440fff6 	bnez	v0,bfc013b0 <main+0x264>
-bfc013d8:	00652021 	addu	a0,v1,a1
-bfc013dc:	00c51821 	addu	v1,a2,a1
-bfc013e0:	0263102b 	sltu	v0,s3,v1
-bfc013e4:	10400060 	beqz	v0,bfc01568 <main+0x41c>
-bfc013e8:	02208021 	move	s0,s1
-bfc013ec:	0bf0055a 	j	bfc01568 <main+0x41c>
-bfc013f0:	00609821 	move	s3,v1
-bfc013f4:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc013f8:	24841750 	addiu	a0,a0,5968
-bfc013fc:	8fa60010 	lw	a2,16(sp)
-bfc01400:	26470100 	addiu	a3,s2,256
-bfc01404:	02661823 	subu	v1,s3,a2
-bfc01408:	27b10020 	addiu	s1,sp,32
-bfc0140c:	3c024a46 	lui	v0,0x4a46
-bfc01410:	00e32821 	addu	a1,a3,v1
-bfc01414:	02202021 	move	a0,s1
-bfc01418:	34424931 	ori	v0,v0,0x4931
-bfc0141c:	afa60144 	sw	a2,324(sp)
-bfc01420:	afa3014c 	sw	v1,332(sp)
-bfc01424:	afa70148 	sw	a3,328(sp)
-bfc01428:	0ff00364 	jal	bfc00d90 <flash_get_offset_blockaligned>
-bfc0142c:	afa20140 	sw	v0,320(sp)
-bfc01430:	3c04bfc0 	lui	a0,0xbfc0
-bfc01434:	24841758 	addiu	a0,a0,5976
-bfc01438:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0143c:	afa20150 	sw	v0,336(sp)
-bfc01440:	8fa4014c 	lw	a0,332(sp)
-bfc01444:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01448:	00000000 	nop
-bfc0144c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01450:	02a02021 	move	a0,s5
-bfc01454:	3c04bfc0 	lui	a0,0xbfc0
-bfc01458:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0145c:	24841774 	addiu	a0,a0,6004
-bfc01460:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01464:	02402021 	move	a0,s2
-bfc01468:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0146c:	02a02021 	move	a0,s5
-bfc01470:	3c04bfc0 	lui	a0,0xbfc0
-bfc01474:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01478:	24841790 	addiu	a0,a0,6032
-bfc0147c:	8fa40150 	lw	a0,336(sp)
-bfc01480:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc01484:	00000000 	nop
-bfc01488:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc0148c:	02a02021 	move	a0,s5
-bfc01490:	3c04bfc0 	lui	a0,0xbfc0
-bfc01494:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01498:	248417ac 	addiu	a0,a0,6060
-bfc0149c:	8fa6014c 	lw	a2,332(sp)
-bfc014a0:	02202021 	move	a0,s1
-bfc014a4:	24c60100 	addiu	a2,a2,256
-bfc014a8:	0ff00304 	jal	bfc00c10 <flash_erase>
-bfc014ac:	02402821 	move	a1,s2
-bfc014b0:	0440001f 	bltz	v0,bfc01530 <main+0x3e4>
-bfc014b4:	00408021 	move	s0,v0
-bfc014b8:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc014bc:	02c02021 	move	a0,s6
-bfc014c0:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc014c4:	03c02021 	move	a0,s8
-bfc014c8:	02202021 	move	a0,s1
-bfc014cc:	02402821 	move	a1,s2
-bfc014d0:	27a60140 	addiu	a2,sp,320
-bfc014d4:	0ff00334 	jal	bfc00cd0 <flash_program>
-bfc014d8:	24070100 	li	a3,256
-bfc014dc:	04400014 	bltz	v0,bfc01530 <main+0x3e4>
-bfc014e0:	00408021 	move	s0,v0
-bfc014e4:	8fa50148 	lw	a1,328(sp)
-bfc014e8:	8fa60144 	lw	a2,324(sp)
-bfc014ec:	8fa7014c 	lw	a3,332(sp)
-bfc014f0:	0ff00334 	jal	bfc00cd0 <flash_program>
-bfc014f4:	02202021 	move	a0,s1
-bfc014f8:	0440000d 	bltz	v0,bfc01530 <main+0x3e4>
-bfc014fc:	00408021 	move	s0,v0
-bfc01500:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01504:	02c02021 	move	a0,s6
-bfc01508:	3c04bfc0 	lui	a0,0xbfc0
-bfc0150c:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01510:	248417dc 	addiu	a0,a0,6108
-bfc01514:	8fa50148 	lw	a1,328(sp)
-bfc01518:	8fa60144 	lw	a2,324(sp)
-bfc0151c:	8fa7014c 	lw	a3,332(sp)
-bfc01520:	0ff0033c 	jal	bfc00cf0 <flash_verify>
-bfc01524:	02202021 	move	a0,s1
-bfc01528:	0441000a 	bgez	v0,bfc01554 <main+0x408>
-bfc0152c:	00408021 	move	s0,v0
-bfc01530:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01534:	268417bc 	addiu	a0,s4,6076
-bfc01538:	0ff000e8 	jal	bfc003a0 <print_word>
-bfc0153c:	02002021 	move	a0,s0
-bfc01540:	3c04bfc0 	lui	a0,0xbfc0
-bfc01544:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01548:	248417c8 	addiu	a0,a0,6088
-bfc0154c:	0bf0055a 	j	bfc01568 <main+0x41c>
-bfc01550:	00000000 	nop
-bfc01554:	0ff000b0 	jal	bfc002c0 <sputs>
-bfc01558:	02e02021 	move	a0,s7
-bfc0155c:	3c02bfc0 	lui	v0,0xbfc0
-bfc01560:	00400008 	jr	v0
-bfc01564:	00000000 	nop
-bfc01568:	0601ff7e 	bgez	s0,bfc01364 <main+0x218>
-bfc0156c:	27b00040 	addiu	s0,sp,64
-bfc01570:	0bf004d5 	j	bfc01354 <main+0x208>
-bfc01574:	3c04bfc0 	lui	a0,0xbfc0
-bfc01578:	8fbf0264 	lw	ra,612(sp)
-bfc0157c:	8fbe0260 	lw	s8,608(sp)
-bfc01580:	8fb7025c 	lw	s7,604(sp)
-bfc01584:	8fb60258 	lw	s6,600(sp)
-bfc01588:	8fb50254 	lw	s5,596(sp)
-bfc0158c:	8fb40250 	lw	s4,592(sp)
-bfc01590:	8fb3024c 	lw	s3,588(sp)
-bfc01594:	8fb20248 	lw	s2,584(sp)
-bfc01598:	8fb10244 	lw	s1,580(sp)
-bfc0159c:	8fb00240 	lw	s0,576(sp)
-bfc015a0:	03e00008 	jr	ra
-bfc015a4:	27bd0268 	addiu	sp,sp,616
-
-bfc015a8 <memset>:
-bfc015a8:	2cc20010 	sltiu	v0,a2,16
-bfc015ac:	00804821 	move	t1,a0
-bfc015b0:	1440002d 	bnez	v0,bfc01668 <memset+0xc0>
-bfc015b4:	00804021 	move	t0,a0
-bfc015b8:	30870003 	andi	a3,a0,0x3
-bfc015bc:	10e0000e 	beqz	a3,bfc015f8 <memset+0x50>
-bfc015c0:	24820004 	addiu	v0,a0,4
-bfc015c4:	00052600 	sll	a0,a1,0x18
-bfc015c8:	00471023 	subu	v0,v0,a3
-bfc015cc:	00042603 	sra	a0,a0,0x18
-bfc015d0:	01201821 	move	v1,t1
-bfc015d4:	a0640000 	sb	a0,0(v1)
-bfc015d8:	24630001 	addiu	v1,v1,1
-bfc015dc:	1462fffd 	bne	v1,v0,bfc015d4 <memset+0x2c>
-bfc015e0:	00000000 	nop
-bfc015e4:	00071027 	nor	v0,zero,a3
-bfc015e8:	24c3fffb 	addiu	v1,a2,-5
-bfc015ec:	24440005 	addiu	a0,v0,5
-bfc015f0:	00623023 	subu	a2,v1,v0
-bfc015f4:	01244021 	addu	t0,t1,a0
-bfc015f8:	30a500ff 	andi	a1,a1,0xff
-bfc015fc:	01003821 	move	a3,t0
-bfc01600:	10a00005 	beqz	a1,bfc01618 <memset+0x70>
-bfc01604:	00a01821 	move	v1,a1
-bfc01608:	00051200 	sll	v0,a1,0x8
-bfc0160c:	00451025 	or	v0,v0,a1
-bfc01610:	00021c00 	sll	v1,v0,0x10
-bfc01614:	00621825 	or	v1,v1,v0
-bfc01618:	000610c2 	srl	v0,a2,0x3
-bfc0161c:	1040001c 	beqz	v0,bfc01690 <memset+0xe8>
-bfc01620:	30c60007 	andi	a2,a2,0x7
-bfc01624:	01002021 	move	a0,t0
-bfc01628:	00403821 	move	a3,v0
-bfc0162c:	24e7ffff 	addiu	a3,a3,-1
-bfc01630:	ac830000 	sw	v1,0(a0)
-bfc01634:	ac830004 	sw	v1,4(a0)
-bfc01638:	14e0fffc 	bnez	a3,bfc0162c <memset+0x84>
-bfc0163c:	24840008 	addiu	a0,a0,8
-bfc01640:	000210c0 	sll	v0,v0,0x3
-bfc01644:	01023821 	addu	a3,t0,v0
-bfc01648:	00e02021 	move	a0,a3
-bfc0164c:	2cc20004 	sltiu	v0,a2,4
-bfc01650:	14400005 	bnez	v0,bfc01668 <memset+0xc0>
-bfc01654:	00804021 	move	t0,a0
-bfc01658:	ace30000 	sw	v1,0(a3)
-bfc0165c:	24e40004 	addiu	a0,a3,4
-bfc01660:	24c6fffc 	addiu	a2,a2,-4
-bfc01664:	00804021 	move	t0,a0
-bfc01668:	10c00007 	beqz	a2,bfc01688 <memset+0xe0>
-bfc0166c:	00000000 	nop
-bfc01670:	00051600 	sll	v0,a1,0x18
-bfc01674:	00021603 	sra	v0,v0,0x18
-bfc01678:	24c6ffff 	addiu	a2,a2,-1
-bfc0167c:	a1020000 	sb	v0,0(t0)
-bfc01680:	14c0fffd 	bnez	a2,bfc01678 <memset+0xd0>
-bfc01684:	25080001 	addiu	t0,t0,1
-bfc01688:	03e00008 	jr	ra
-bfc0168c:	01201021 	move	v0,t1
-bfc01690:	0bf00593 	j	bfc0164c <memset+0xa4>
-bfc01694:	01002021 	move	a0,t0
diff --git a/projects/mips_sys/src/clockgen_virtex4.vhd b/projects/mips_sys/src/clockgen_virtex4.vhd
deleted file mode 100644
index d8bebfd..0000000
--- a/projects/mips_sys/src/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,363 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library ieee, work;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-USE WORK.utils_pkg.ALL;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity clockgen is
-	generic
-	(
-		clk_in_freq				: real	:= 100.0;
-		cpu_clk_out_freq		: real	:= 100.0;
-		vga_clk_out_freq		: real	:= 100.0;
-		sdr0_clk_out_phaseshift	: integer := 0;
-		sdr1_clk_out_phaseshift	: integer := 0
-	);
-	port 
-	(
-		-- Clocks and Reset
-		rst_in				: in std_logic;   -- external async reset, low active
-		clk_in				: in std_logic;   -- system clock (e.g. 100MHz), from board
-		sys_clk_out			: out std_logic;
-		cpu_clk_out			: out std_logic;
-		vga_clk_out			: out std_logic;
-		sdr0_clk_fb_in		: in std_logic;   -- feedback clock
-		sdr0_clk0_out		: out std_logic;  -- System clock #0, dcm#0 output 0°
-		sdr0_clk270_out		: out std_logic;  -- System clock #0, dcm#0 output 270°
-		sdr1_clk0_out		: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		sdr1_clk270_out		: out std_logic;  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-		sys_rst_out			: out std_logic  -- DCM locked status
-	);
-end;
-
-architecture tech of clockgen is
-
-	signal dcm_rst					: unsigned(2 downto 0);
-	signal vga_clk0               	: std_logic;
-	signal vga_clkfx	           	: std_logic;
-	signal vga_clk0_bufg			: std_logic;
-	signal sys_clk0               	: std_logic;
-	signal sys_clk0_bufg			: std_logic;
-	signal cpu_clkfx	           	: std_logic;
-	signal cpu_clkfx_bufg			: std_logic;
-	signal sdr0_clk0				: std_logic;
-	signal sdr0_clk270				: std_logic;
-	signal sdr1_clk0				: std_logic;
-	signal sdr1_clk270				: std_logic;
-	signal sdr1_clk0_bufg			: std_logic;
-	signal reset_cnt 				: unsigned(4 downto 0);
-	signal reset_pipe0 				: unsigned(19 downto 0);
-	signal reset_pipe1 				: unsigned(19 downto 0);
-	signal reset_pipe2 				: unsigned(19 downto 0);
-	signal vga_fx_lock				: std_logic;
-	signal sys_fx_lock				: std_logic;
-	signal sdr0_lock				: std_logic;
-	signal sdr1_lock				: std_logic;
-
-
-begin 
-
-	-------------------------------------------------------------------------------------------------------
-	-- Clock generation
-	-------------------------------------------------------------------------------------------------------
-   
-	-- Compnent instantiation
-	inst_DCM_VGA_FX : DCM_BASE
-	generic map 
-	(
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, vga_clk_out_freq),   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, vga_clk_out_freq), -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-											 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	)
-	port map
-	(
-		CLK0 => vga_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => open,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => vga_clkfx,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => vga_fx_lock,     -- DCM LOCK status output
-		CLKFB => vga_clk0_bufg,       -- DCM clock feedback
-		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(0)            -- DCM asynchronous reset input
-	);
-
-BUFG_vga_clk0 : BUFG
-	port map
-	(
-		O => vga_clk0_bufg,     -- Clock buffer output
-		I => vga_clk0        -- Clock buffer input
-	);
-
-BUFG_vga_clkfx : BUFG
-	port map
-	(
-		O => vga_clk_out,     -- Clock buffer output
-		I => vga_clkfx     -- Clock buffer input
-	);
-
-	-- Compnent instantiation
-	inst_DCM_CPU_FX : DCM_BASE
-	generic map 
-	(
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-						   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq, cpu_clk_out_freq),   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq, cpu_clk_out_freq), -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-											 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	)
-	port map
-	(
-		CLK0 => sys_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => open,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => cpu_clkfx,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => sys_fx_lock,     -- DCM LOCK status output
-		CLKFB => sys_clk0_bufg,       -- DCM clock feedback
-		CLKIN => clk_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(0)            -- DCM asynchronous reset input
-	);
-
-BUFG_sys_clk0 : BUFG
-	port map
-	(
-		O => sys_clk0_bufg,     -- Clock buffer output
-		I => sys_clk0        -- Clock buffer input
-	);
-
-BUFG_sys_clkfx : BUFG
-	port map
-	(
-		O => cpu_clkfx_bufg,     -- Clock buffer output
-		I => cpu_clkfx     -- Clock buffer input
-	);
-
-	sys_clk_out	<= sys_clk0_bufg;
-	cpu_clk_out	<= cpu_clkfx_bufg;
-
-inst_DCM_SDRCLK_0 : DCM_BASE
-	generic map 
-	(
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	)
-	port map 
-	(
-		CLK0 => sdr0_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => sdr0_clk270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => sdr0_lock,     -- DCM LOCK status output
-		CLKFB => sdr0_clk_fb_in,       -- DCM clock feedback
-		CLKIN => sys_clk0_bufg,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(1)            -- DCM asynchronous reset input
-	);
-
-bufg_sdr0_clk0: bufg
-	port map
-	(
-		o  => sdr0_clk0_out,  
-		i  => sdr0_clk0
-	);
-
-bufg_sdr0_clk270: bufg
-	port map (
-		o  => sdr0_clk270_out,  
-		i  => sdr0_clk270
-	);
-
-	inst_DCM_SDRCLK_1 : DCM_BASE
-	generic map 
-	(
-		CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-				   --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
-		CLKFX_DIVIDE => 1,   -- Can be any interger from 1 to 32
-		CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
-		CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
-		CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq), -- Specify period of input clock in ns from 1.25 to 1000.00
-		CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
-		CLK_FEEDBACK => "1X",         -- Specify clock feedback of NONE or 1X
-		DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
-		DCM_PERFORMANCE_MODE => "MAX_SPEED",   -- Can be MAX_SPEED or MAX_RANGE
-		DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-									 --   an integer from 0 to 15
-		DFS_FREQUENCY_MODE => "LOW",   -- LOW or HIGH frequency mode for frequency synthesis
-		DLL_FREQUENCY_MODE => "LOW",   -- LOW, HIGH, or HIGH_SER frequency mode for DLL
-		DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
-		FACTORY_JF => X"F0F0",          -- FACTORY JF Values Suggested to be set to X"F0F0" 
-		PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
-		STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
-	)
-	port map 
-	(
-		CLK0 => sdr1_clk0,         -- 0 degree DCM CLK ouptput
-		CLK180 => open,     -- 180 degree DCM CLK output
-		CLK270 => sdr1_clk270,     -- 270 degree DCM CLK output
-		CLK2X => open,       -- 2X DCM CLK output
-		CLK2X180 => open, -- 2X, 180 degree DCM CLK out
-		CLK90 => open,       -- 90 degree DCM CLK output
-		CLKDV => open,       -- Divided DCM CLK out (CLKDV_DIVIDE)
-		CLKFX => open,       -- DCM CLK synthesis out (M/D)
-		CLKFX180 => open, -- 180 degree CLK synthesis out
-		LOCKED => sdr1_lock,     -- DCM LOCK status output
-		CLKFB => sdr1_clk0_bufg,       -- DCM clock feedback
-		CLKIN => sdr0_clk_fb_in,       -- Clock input (from IBUFG, BUFG or DCM)
-		RST => dcm_rst(2)            -- DCM asynchronous reset input
-	);
-
-	sdr1_clk0_out	<= sdr1_clk0_bufg;
-	
-bufg_sdr1_clk0: bufg
-	port map
-	(
-		o  => sdr1_clk0_bufg,  
-		i  => sdr1_clk0
-	);
-
-
-bufg_sdr1_clk270: bufg
-	port map (
-		o  => sdr1_clk270_out,  
-		i  => sdr1_clk270
-	);
-
-	dcm_rst(0)	<= reset_pipe0(reset_pipe0'left);
-
-dcm_reset0:
-	process(rst_in, clk_in)
-	begin
-		if rst_in = '1' then
-			reset_pipe0	<= (others => '1');
-		elsif rising_edge(clk_in) then
-			reset_pipe0	<= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
-		end if;
-
-	end process;
-
-	dcm_rst(1)	<= reset_pipe1(reset_pipe1'left);
-
-dcm_reset1:
-	process(vga_fx_lock, clk_in)
-	begin
-		if vga_fx_lock = '0' then
-			reset_pipe1	<= (others => '1');
-		elsif rising_edge(clk_in) then
-			reset_pipe1	<= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
-		end if;
-		
-	end process;
-
-	dcm_rst(2) 	<= reset_pipe2(reset_pipe2'left);
-
-dcm_reset2:
-	process(sdr0_lock, clk_in)
-	begin
-		if sdr0_lock = '0' then
-			reset_pipe2	<= (others => '1');
-		elsif rising_edge(clk_in) then
-			reset_pipe2	<= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
-		end if;
-		
-	end process;
-
-reset_out_logic:
-	process(rst_in, clk_in, sdr0_lock, sdr1_lock, sys_fx_lock, vga_fx_lock)
-	begin
-		if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
-			sys_rst_out	<= '1';
-			reset_cnt	<= (reset_cnt'left downto reset_cnt'right => '1');
-		elsif rising_edge(clk_in) then
-			if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
-				reset_cnt	<= reset_cnt - 1;
-			else
-				sys_rst_out	<= '0';
-			end if;
-		end if;
-
-	end process;
-
-end architecture tech;
-
-
diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
deleted file mode 100644
index 19dd2da..0000000
--- a/projects/mips_sys/src/mips_sys.vhd
+++ /dev/null
@@ -1,1169 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-library work;
-use work.mips_types.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.vga_types.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-
-ENTITY mips_sys IS
-GENERIC
-(
-	sys_freq_in			: real				:= 100.0;
-	cpu_freq			: real				:= 100.0;
-	sdram_phaseshift	: integer			:= 0;
-	tsvga				: vga_timespec_t 	:= ts_vga_800_600_60
-
-);
-PORT
-(
-	sys_rst_n_in		: in std_logic;
-	sys_clk_in			: in std_logic;
-
-	-- Buttons and LEDs
-	sys_btn				: in unsigned(4 downto 0);
-	sys_dip				: in unsigned(7 downto 0);
-	sys_led				: out unsigned(8 downto 0);
-
-	-- UART
-	sys_uart0_rx		: in std_logic;
-	sys_uart0_tx		: out std_logic;
-	sys_uart1_rx		: in std_logic;
-	sys_uart1_tx		: out std_logic;
-	sys_uart2_rx		: in std_logic;
-	sys_uart2_tx		: out std_logic;
-	sys_uart3_rx		: in std_logic;
-	sys_uart3_tx		: out std_logic;
-
-	-- LCD
-	sys_lcd_d			: inout unsigned(3 downto 0);
-	sys_lcd_e			: out std_logic;
-	sys_lcd_rs			: out std_logic;
-	sys_lcd_rw			: out std_logic;
-
-	-- DDR SDRAM
-	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
-	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
-	sys_sdr_cke_q		: out std_logic;    -- clock enable
-	sys_sdr_cs_qn		: out std_logic;    -- /chip select
-	sys_sdr_ras_qn		: out std_logic;    -- /ras
-	sys_sdr_cas_qn		: out std_logic;    -- /cas
-	sys_sdr_we_qn		: out std_logic;    -- /write enable
-	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-	sys_sdr_clk_fb		: in std_logic;
-	
-	-- VGA
-	sys_vga_clk			: out std_logic;
-	sys_vga_red			: out unsigned(7 downto 0);
-	sys_vga_green		: out unsigned(7 downto 0);
-	sys_vga_blue		: out unsigned(7 downto 0);
-	sys_vga_blank_n		: out std_logic;
-	sys_vga_sync_n		: out std_logic;
-	sys_vga_hsync		: out std_logic;
-	sys_vga_vsync		: out std_logic;
-
-	sys_usb_d			: inout unsigned(15 downto 0);
-	sys_usb_a			: out unsigned(1 downto 0);
-	sys_usb_csn			: out std_logic;
-	sys_usb_wrn			: out std_logic;
-	sys_usb_rdn			: out std_logic;
-	sys_usb_rstn		: out std_logic;
-	sys_usb_int			: in std_logic;
-
-	sys_flash_d			: inout unsigned(31 downto 0);
-	sys_flash_a			: out unsigned(24 downto 0);
-	sys_flash_ce		: out std_logic;
-	sys_flash_wrn		: out std_logic;
-	sys_flash_rdn		: out std_logic;
-	sys_flash_ac97_rstn	: out std_logic;
-	sys_flash_byten		: out std_logic;	
-
-	sys_ac97_sdata_in	: in  std_logic;
-	sys_ac97_bit_clk	: in  std_logic;
-	sys_ac97_sdata_out	: out std_logic;
-	sys_ac97_ssync		: out std_logic;
-
-	sys_ps2_0_clk		: inout std_logic;
-	sys_ps2_0_data		: inout std_logic;
-
-	sys_ps2_1_clk		: inout std_logic;
-	sys_ps2_1_data		: inout std_logic;
-
-	sys_phy_rstn		: out std_logic;
-	sys_phy_mdc			: out std_logic;
-	sys_phy_mdio		: inout std_logic;
-	sys_phy_int			: in  std_logic;
-
-	sys_phy_rx_clk		: in  STD_LOGIC;
-	sys_phy_rx_dv		: in  STD_LOGIC;
-	sys_phy_rx_er		: in  STD_LOGIC;
-	sys_phy_rx			: in unsigned(7 downto 0);
-	sys_phy_tx_clk		: in  STD_LOGIC;
-	sys_phy_tx_en		: out STD_LOGIC;
-	sys_phy_tx_er		: out STD_LOGIC;
-	sys_phy_tx			: out unsigned(7 downto 0);
-	sys_phy_gtx_clk		: out STD_LOGIC;
-	sys_phy_crs			: in  STD_LOGIC;
-	sys_phy_col			: in  STD_LOGIC;
-
-	sys_error			: out unsigned(1 downto 0) -- indicates Errors
-	
-);
---	attribute BUFFER_TYPE : string;
---	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
---	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
-
-END mips_sys;
-
-ARCHITECTURE behavior OF mips_sys IS 
-
-	COMPONENT mips_top
-	Port 
-	(
-		debug			: out unsigned(1 downto 0);
-		eb				: in  STD_LOGIC;
-		nmi				: in  STD_LOGIC;
-		cpu_clk			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		ADDR_O			: out word_t;
-		DAT_I			: in  word_t;
-		DAT_O			: out word_t;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(3 downto 0);
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		INT				: in  unsigned (5 downto 0)
-		
-	);
-	END COMPONENT;
-	
-	COMPONENT rom_wb
-	PORT
-	(
-		CLK_I			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		ACK_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT lcd_port
-	PORT 
-	(
-		rst				: in std_logic;
-		clk				: in std_logic;
-		we				: in std_logic;
-		din				: in unsigned(7 downto 0);
-		dout			: out unsigned(7 downto 0);
-		lcd_d			: inout unsigned(3 downto 0);
-		lcd_e			: out std_logic;
-		lcd_rs			: out std_logic;
-		lcd_rw			: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT async_port_wb
-	GENERIC
-	(
-		f_sysclk		: real		:= sys_freq_in;
-		addr_width		: natural	:= 32;
-		data_width		: natural	:= 32;
-		byte_sel_width	: natural	:= 4;
-		async_timespec	: async_timespec_t
-	);
-	PORT
-	(
-		CLK_I			: in  STD_LOGIC;
-		RST_I			: in  STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ADDR_I			: in  unsigned(31 downto 0);
-		DAT_I			: in  unsigned(31 downto 0);
-		DAT_O			: out unsigned(31 downto 0);
-		page_mode_en	: in  STD_LOGIC;
-		async_a			: out unsigned(addr_width-1 downto 0);
-		async_d			: inout unsigned(data_width-1 downto 0);
-		async_cs		: out std_logic;
-		async_wr		: out std_logic;
-		async_rd		: out std_logic;
-		async_be		: out unsigned(byte_sel_width-1 downto 0);
-		async_rst		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT uart_wb
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_O		: out STD_LOGIC;
-		ser_rx		: in std_logic;
-		ser_tx		: out std_logic
-	);
-	END COMPONENT;
-
-	COMPONENT gpio_wb
-	Generic
-	(
-		f_sysclk	: real := sys_freq_in
-	);
-	PORT
-	(
-		CLK_I		: in  STD_LOGIC;
-		RST_I		: in  STD_LOGIC;
-		CYC_I		: in  STD_LOGIC;
-		STB_I		: in  STD_LOGIC;
-		SEL_I		: in  unsigned(3 downto 0);
-		WE_I		: in  STD_LOGIC;
-		ACK_O		: out STD_LOGIC;
-		SRDY_O		: out STD_LOGIC;
-		MRDY_I		: in  STD_LOGIC;
-		ADDR_I		: in  unsigned(31 downto 0);
-		DAT_I		: in  unsigned(31 downto 0);
-		DAT_O		: out unsigned(31 downto 0);
-		INT_TIM_O	: out STD_LOGIC;
-
-		sys_gpi_0	: in  unsigned(31 downto 0);
-		sys_gpo_0	: out  unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
-	COMPONENT vga_frontend64
-	GENERIC
-	(
-		fifo_depth					: integer;
-		fifo_almost_full_thresh		: natural;
-		fifo_almost_empty_thresh	: natural;
-		tsvga						: vga_timespec_t
-	);
-	PORT
-	(
-		-- System signals
-		RST_I			: in  STD_LOGIC;
-		CLK_I			: in  STD_LOGIC;
-
-		-- JBUS Master signals
-		CYC_O			: out STD_LOGIC;
-		STB_O			: out STD_LOGIC;
-		WE_O			: out STD_LOGIC;
-		SEL_O			: out unsigned(7 downto 0);
-		ACK_I			: in  STD_LOGIC;
-		SRDY_I			: in  STD_LOGIC;
-		MRDY_O			: out STD_LOGIC;
-		ADDR_O			: out unsigned(31 downto 0);
-		MDAT_I			: in  unsigned(63 downto 0);
-		MDAT_O			: out unsigned(63 downto 0);
-		
-		-- JBUS Slave signals
-		INT_O			: out STD_LOGIC;
-		CYC_I			: in  STD_LOGIC;
-		STB_I			: in  STD_LOGIC;
-		WE_I			: in  STD_LOGIC;
-		SEL_I			: in  unsigned(3 downto 0);
-		ACK_O			: out STD_LOGIC;
-		SRDY_O			: out STD_LOGIC;
-		MRDY_I			: in  STD_LOGIC;
-		ADDR_I			: in  unsigned(31 downto 0);
-		SDAT_I			: in  unsigned(31 downto 0);
-		SDAT_O			: out unsigned(31 downto 0);
-		
-		-- VGA signals
-		vga_clk_in		: in  std_logic;
-		vga_clk_ce		: in  std_logic;
-		vga_red			: out unsigned(7 downto 0);
-		vga_green		: out unsigned(7 downto 0);
-		vga_blue		: out unsigned(7 downto 0);
-		vga_blank_n		: out std_logic;
-		vga_sync_n		: out std_logic;
-		vga_hsync		: out std_logic;
-		vga_vsync		: out std_logic
-	);
-	END COMPONENT;
-
-	signal cpu_clk				: std_logic;
-	signal nmi					: std_logic;
-	signal eb					: std_logic;
-	signal sdram_clk0			: std_logic;
-	signal sdram_clk270			: std_logic;
-	signal sdram_clk270var		: std_logic;
-	signal vga_clk				: std_logic;
-	signal vga_ce				: std_logic;
-	signal rst_in				: std_logic;
-	signal int_timer			: std_logic;
-	signal int_uart0			: std_logic;
-	signal int_uart1			: std_logic;
-	signal uart1_tx				: std_logic;
-	signal uart1_rx				: std_logic;
-	signal usb_addr 			: unsigned(3 downto 0);
-	signal ac97_rstn			: std_logic;
-	signal mem_mapped_io		: std_logic;
-	signal flash_rstn			: std_logic;
-	signal flash_page_mode_en	: std_logic;
-	signal flash_addr			: unsigned(24 downto 0);
-	signal ps2_0_clk_rx			: std_logic;
-	signal ps2_0_data_rx		: std_logic;
-	signal ps2_0_clk_tx			: std_logic;
-	signal ps2_0_data_tx		: std_logic;
-	signal ps2_1_clk_rx			: std_logic;
-	signal ps2_1_data_rx		: std_logic;
-	signal ps2_1_clk_tx			: std_logic;
-	signal ps2_1_data_tx		: std_logic;
-
-	-- Arbiter
-	constant ARB_MAX_MASTER		: natural := 2;
-	signal	arb_idx				: natural range 0 to ARB_MAX_MASTER-1;
-	signal	arb_req				: unsigned (ARB_MAX_MASTER-1 downto 0);
-	signal	arb_gnt				: unsigned (ARB_MAX_MASTER-1 downto 0);
-
-	-- J-Bus signals
-	signal CLK_O				: std_logic;
-	signal RST_O				: std_logic;
-	signal INT	 				: unsigned(5 downto 0);
-	signal MDAT_I				: word_t;
-	signal MDAT_O 				: unsigned(63 downto 0);
-	signal ADDR_O 				: word_t;
-	signal SEL_O 				: unsigned(7 downto 0);
-	signal WE_O 				: std_logic;
-	signal CYC_O 				: std_logic;
-	signal STB_O 				: std_logic;
-	signal ACK_I				: std_logic;
-	signal SRDY_I				: std_logic;
-	signal MRDY_O				: std_logic;
-
-	-- CPU Master
-	signal MRDY_O_cpu			: std_logic;
-	signal MDAT_O_cpu			: word_t;
-	signal ADDR_O_cpu			: word_t;
-	signal SEL_O_cpu			: unsigned(3 downto 0);
-	signal WE_O_cpu				: std_logic;
-	signal CYC_O_cpu			: std_logic;
-	signal STB_O_cpu			: std_logic;
-	signal SRDY_I_cpu			: std_logic;
-	signal ACK_I_cpu			: std_logic;
-
-	-- VGA Master
-	signal MRDY_O_vga			: std_logic;
-	signal ADDR_O_vga			: word_t;
-	signal SEL_O_vga			: unsigned(7 downto 0);
-	signal WE_O_vga				: std_logic;
-	signal CYC_O_vga			: std_logic;
-	signal STB_O_vga			: std_logic;
-	signal SRDY_I_vga			: std_logic;
-	signal ACK_I_vga			: std_logic;
-	signal MDAT_I_vga			: unsigned(63 downto 0);
-	signal MDAT_O_vga			: unsigned(63 downto 0);
-
-	-- Slaves
-	signal CYC_I_flash			: std_logic;
-	signal ACK_O_flash			: std_logic;
-	signal SRDY_O_flash			: std_logic;
-	signal SDAT_O_flash			: unsigned(31 downto 0);
-
-	signal CYC_I_usb			: std_logic;
-	signal ACK_O_usb			: std_logic;
-	signal SRDY_O_usb			: std_logic;
-	signal SDAT_O_usb			: unsigned(31 downto 0);
-
-	signal CYC_I_sdram			: std_logic;
-	signal ACK_O_sdram			: std_logic;
-	signal SRDY_O_sdram			: std_logic;
-	signal SDAT_O_sdram			: unsigned(63 downto 0);
-
-	signal CYC_I_rom			: std_logic;
-	signal ACK_O_rom			: std_logic;
-	signal SRDY_O_rom			: std_logic;
-	signal SDAT_O_rom			: unsigned(31 downto 0);
-
-	signal CYC_I_gpio			: std_logic;
-	signal ACK_O_gpio			: std_logic;
-	signal SRDY_O_gpio			: std_logic;
-	signal SDAT_O_gpio			: unsigned(31 downto 0);
-
-	signal CYC_I_uart0			: std_logic;
-	signal ACK_O_uart0			: std_logic;
-	signal SRDY_O_uart0			: std_logic;
-	signal SDAT_O_uart0			: unsigned(31 downto 0);
-	signal CYC_I_uart1			: std_logic;
-	signal ACK_O_uart1			: std_logic;
-	signal SRDY_O_uart1			: std_logic;
-	signal SDAT_O_uart1			: unsigned(31 downto 0);
-
-	signal INT_O_vga			: std_logic;
-	signal CYC_I_vga			: std_logic;
-	signal ACK_O_vga			: std_logic;
-	signal SRDY_O_vga			: std_logic;
-	signal SDAT_O_vga			: unsigned(31 downto 0);
-
-	signal INT_O_ac97			: std_logic;
-	signal CYC_I_ac97			: std_logic;
-	signal ACK_O_ac97			: std_logic;
-	signal SRDY_O_ac97			: std_logic;
-	signal SDAT_O_ac97			: unsigned(31 downto 0);
-
-	signal INT_O_ps2_0			: std_logic;
-	signal CYC_I_ps2_0			: std_logic;
-	signal ACK_O_ps2_0			: std_logic;
-	signal SRDY_O_ps2_0			: std_logic;
-	signal SDAT_O_ps2_0			: unsigned(31 downto 0);
-
-	signal INT_O_ps2_1			: std_logic;
-	signal CYC_I_ps2_1			: std_logic;
-	signal ACK_O_ps2_1			: std_logic;
-	signal SRDY_O_ps2_1			: std_logic;
-	signal SDAT_O_ps2_1			: unsigned(31 downto 0);
-
-	signal INT_O_emac			: std_logic;
-	signal CYC_I_emac			: std_logic;
-	signal ACK_O_emac			: std_logic;
-	signal SRDY_O_emac			: std_logic;
-	signal SDAT_O_emac			: unsigned(31 downto 0);
-
-	signal gpi_0				: unsigned(31 downto 0);
-	signal gpo_0				: unsigned(31 downto 0);
-
-	signal ac97_inten			: std_logic;
-	signal usb_inten			: std_logic;
-	signal phy_inten			: std_logic;
-
-	signal debug				: unsigned(1 downto 0);
-
-	-- DDR SDRAM
-	constant BURST_LEN			: natural := 2;
-	constant vga_freq			: real := real(tsvga.f_pxl_clk)/1.0E6;
-
-	
---	attribute rom_style: string;
---	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
-
-	type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_ps2_0, mem_ps2_1, mem_sdram, mem_vga, mem_ac97, mem_emac);
-	signal mem_area : mem_area_t;
-
-	attribute KEEP : string;
-	attribute KEEP of vga_clk		: signal is "TRUE";
-	attribute KEEP of sdram_clk0	: signal is "TRUE";
-	attribute KEEP of cpu_clk		: signal is "TRUE";
-	attribute KEEP of CLK_O			: signal is "TRUE";
-	attribute KEEP of RST_O			: signal is "TRUE";
-
-BEGIN
-
-	------------------------------------
-	-- GPIO_0 bits used for
-	--  8.. 0	= O: LED 8..0
-	-- 11.. 9	= free    
-	-- 12		= O: USB RST
-	-- 13		= O: USB INTEN
-	-- 14		= free
-	-- 15		= O: AC97 INTEN
-	-- 32..16	= I: DIP 7..0
-	-- 28..24	= I: BTN 4..0
-	-- 29		= O: PHY RESET
-	-- 30		= O: PHY MDC
-	-- 31		= IO: PHY MDIO
-	------------------------------------
-	gpi_0(28 downto 24)		<= sys_btn;
-	gpi_0(23 downto 16)		<= sys_dip;
-	gpi_0(31)				<= sys_phy_mdio;
-	
-	sys_led					<= gpo_0(8 downto 0);
-	sys_usb_rstn			<= not gpo_0(12);
-	usb_inten				<= gpo_0(13);
-	phy_inten				<= gpo_0(14);
-	ac97_inten				<= gpo_0(15);
-	sys_phy_rstn			<= not gpo_0(29);
-	sys_phy_mdc				<= gpo_0(30);
-	sys_phy_mdio			<= gpo_0(31);
-	
-	eb						<= sys_dip(7);
-	sys_error				<= debug;
-	nmi						<= not sys_rst_n_in;
-	rst_in 					<= not sys_rst_n_in and sys_btn(0);
-	sys_flash_byten			<= '1';
-	sys_usb_a				<= usb_Addr(3 downto 2);
-	sys_flash_a				<= '0' & flash_addr(24 downto 2) & '0';
-	flash_page_mode_en		<= not mem_mapped_io;
-
-	sys_flash_ac97_rstn		<= ac97_rstn and flash_rstn;
-	sys_uart1_tx			<= uart1_tx;
-	sys_uart2_tx			<= uart1_tx;
-	uart1_rx				<= sys_uart1_rx and sys_uart2_rx;
-	sys_uart3_tx 			<= sys_uart3_rx;
-	
-	sys_vga_clk				<= vga_clk;
-	vga_ce					<= not RST_O;
-	
-	---------------------------------------------------------------
-	-- Arbiter
-	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
-	MDAT_O		<= (MDAT_O_cpu & MDAT_O_cpu) when arb_gnt(0) = '1' else MDAT_O_vga when arb_gnt(1) = '1' else (others => '0');
-	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
-	SEL_O		<= ("0000" & SEL_O_cpu) when arb_gnt(0) = '1' else SEL_O_vga when arb_gnt(1) = '1' else (others => '0');
-	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
-	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
-	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
-	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
-	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
-	ACK_I_cpu	<= ACK_I and arb_gnt(0);
-	ACK_I_vga	<= ACK_I and arb_gnt(1);
-	
-	arb_req(0)	<= CYC_O_cpu;
-	arb_req(1)	<= CYC_O_vga;
-	
-	MDAT_I_vga	<= SDAT_O_sdram;
-	
-arbiter_proc:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				arb_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif arb_req(arb_idx) = '0' then
-				if arb_idx /= ARB_MAX_MASTER-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				arb_gnt	<= (others => '0');
-				arb_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-	
-int_sample:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1 or INT_O_emac) & (INT_O_vga or (ac97_inten and INT_O_ac97)) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
-		end if;
-	end process;
-	
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area			<= mem_dead;
-		mem_mapped_io		<= '0';
-		if ADDR_O(31 downto 28) = X"0" then
-			mem_area			<= mem_flash;
-		elsif ADDR_O(31 downto 28) = X"1" then
-			mem_area	<= mem_emac;
-		elsif ADDR_O(31 downto 28) = X"A" then
-			mem_mapped_io	<= '1';
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					if ADDR_O(9 downto 8) = "00" then
-						mem_area	<= mem_uart0;
-					elsif ADDR_O(9 downto 8) = "01" then
-						mem_area	<= mem_uart1;
-					elsif ADDR_O(9 downto 8) = "10" then
-						mem_area	<= mem_ps2_0;
-					elsif ADDR_O(9 downto 8) = "11" then
-						mem_area	<= mem_ps2_1;
-					end if;						
-				elsif ADDR_O(18 downto 16) = "010" then
-					mem_area	<= mem_usb;
-				elsif ADDR_O(18 downto 16) = "011" then
-					mem_area	<= mem_vga;
-				elsif ADDR_O(18 downto 16) = "100" then
-					mem_area	<= mem_ac97;
-				elsif ADDR_O(18 downto 16) = "101" then
-					mem_area	<= mem_emac;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sdram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart0		<= '0';
-		CYC_I_uart1		<= '0';
-		CYC_I_ps2_0		<= '0';
-		CYC_I_ps2_1		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_usb		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sdram		<= '0';
-		CYC_I_vga		<= '0';
-		CYC_I_ac97		<= '0';
-		CYC_I_emac		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart0 =>
-			CYC_I_uart0		<= CYC_O;
-
-		when mem_uart1 =>
-			CYC_I_uart1		<= CYC_O;
-
-		when mem_ps2_0 =>
-			CYC_I_ps2_0		<= CYC_O;
-
-		when mem_ps2_1 =>
-			CYC_I_ps2_1		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_usb =>
-			CYC_I_usb		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sdram =>
-			CYC_I_sdram		<= CYC_O;
-		
-		when mem_vga =>
-			CYC_I_vga		<= CYC_O;
-
-		when mem_ac97 =>
-			CYC_I_ac97		<= CYC_O;
-
-		when mem_emac =>
-			CYC_I_emac		<= CYC_O;
-
-		when others => null;
-		
-		end case;
-		
-	end process;
-
-------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac;
- 	MDAT_I		<=	SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
-					SDAT_O_rom when CYC_I_rom = '1' else
-					SDAT_O_flash when CYC_I_flash = '1' else
-					SDAT_O_usb when CYC_I_usb = '1' else
-					SDAT_O_uart0 when CYC_I_uart0 = '1' else
-					SDAT_O_uart1 when CYC_I_uart1 = '1' else
-					SDAT_O_ps2_0 when CYC_I_ps2_0 = '1' else
-					SDAT_O_ps2_1 when CYC_I_ps2_1 = '1' else
-					SDAT_O_vga when CYC_I_vga = '1' else
-					SDAT_O_ac97 when CYC_I_ac97 = '1' else
-					SDAT_O_emac when CYC_I_emac = '1' else
-					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-------------------------------------------------------------------
-inst_mips_top: mips_top
-	PORT MAP
-	(
-		debug			=> debug,
-		eb				=> eb,
-		nmi				=> nmi,
-		cpu_clk			=> cpu_clk,
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-		ACK_I			=> ACK_I_cpu,
-		SRDY_I			=> SRDY_I_cpu,
-		MRDY_O			=> MRDY_O_cpu,
-		CYC_O			=> CYC_O_cpu,
-		STB_O			=> STB_O_cpu,
-		WE_O			=> WE_O_cpu,
-		SEL_O			=> SEL_O_cpu,
-		DAT_I			=> MDAT_I,
-		DAT_O			=> MDAT_O_cpu,
-		ADDR_O			=> ADDR_O_cpu,
-		INT				=> INT
-	);
-
-inst_rom_wb : rom_wb
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_rom,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_rom,
-		MRDY_I			=> MRDY_O,
-		SRDY_O			=> SRDY_O_rom,
-		ADDR_I			=> ADDR_O,
-		DAT_O			=> SDAT_O_rom
-	);
-
-
-inst_lcd_port: lcd_port
-	PORT MAP
-	(
-		clk 			=> CLK_O,
-		rst 			=> RST_O,
-		we				=> '0',
-		din				=> X"00",
-		dout			=> open,
-		lcd_d			=> sys_lcd_d,
-		lcd_e			=> sys_lcd_e,
-		lcd_rs			=> sys_lcd_rs,
-		lcd_rw			=> sys_lcd_rw
-	);
-	
-inst_gpio_wb : gpio_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> sys_freq_in
-	)
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_gpio,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_gpio,
-		SRDY_O			=> SRDY_O_gpio,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_gpio,
-		INT_TIM_O		=> int_timer,
-
-		sys_gpi_0		=> gpi_0,
-		sys_gpo_0		=> gpo_0
-	);
-
-inst_flash_port : async_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> sys_freq_in,
-		addr_width		=> 25,
-		data_width		=> 32,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_flash,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_flash,
-		SRDY_O			=> SRDY_O_flash,
-		MRDY_I			=> MRDY_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_flash,
-		page_mode_en	=> flash_page_mode_en,
-		async_a			=> flash_addr,
-		async_d			=> sys_flash_d,
-		async_cs		=> sys_flash_ce,
-		async_wr		=> sys_flash_wrn,
-		async_rd		=> sys_flash_rdn,
-		async_be		=> open,
-		async_rst		=> flash_rstn
-	);
-
-inst_usb_port : async_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> sys_freq_in,
-		addr_width		=> 4,
-		data_width		=> 16,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_usb
-	)
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_usb,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_usb,
-		SRDY_O			=> SRDY_O_usb,
-		MRDY_I			=> MRDY_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_usb,
-		page_mode_en	=> '0',
-		async_a			=> usb_addr,
-		async_d			=> sys_usb_d,
-		async_cs		=> sys_usb_csn,
-		async_wr		=> sys_usb_wrn,
-		async_rd		=> sys_usb_rdn,
-		async_be		=> open,
-		async_rst		=> open
-	);
-
-inst_uart_wb_0 : uart_wb
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_uart0,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_uart0,
-		SRDY_O			=> SRDY_O_uart0,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_uart0,
-		INT_O			=> int_uart0,
-		ser_rx			=> sys_uart0_rx,
-		ser_tx			=> sys_uart0_tx
-	);
-
-inst_uart_wb_1 : uart_wb
-	PORT MAP
-	(
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_uart1,
-		STB_I			=> STB_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_uart1,
-		SRDY_O			=> SRDY_O_uart1,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_uart1,
-		INT_O			=> int_uart1,
-		ser_rx			=> uart1_rx,
-		ser_tx			=> uart1_tx
-	);
-
-
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		clk_in_freq				=> sys_freq_in,
-		cpu_clk_out_freq		=> cpu_freq,
-		vga_clk_out_freq		=> vga_freq,
-		sdr0_clk_out_phaseshift	=> 0,
-		sdr1_clk_out_phaseshift	=> 0
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst_in				=> rst_in,   -- external async reset, low active
-		clk_in				=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
-		sys_rst_out			=> RST_O,  
-		sys_clk_out			=> CLK_O,
-		vga_clk_out			=> vga_clk,
-		cpu_clk_out			=> cpu_clk,
-		sdr0_clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
-		sdr0_clk0_out		=> sdram_clk0,  -- System clock #0, dcm#0 output 0°
-		sdr0_clk270_out		=> sdram_clk270,  -- System clock #0, dcm#0 output 270°
-		sdr1_clk0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		sdr1_clk270_out		=> sdram_clk270var  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-	);
-
-inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
-	GENERIC MAP
-	(
-		BL					=> BURST_LEN,
-		f_sysclk			=> sys_freq_in,
-		f_sdrclk			=> sys_freq_in,
-		fifo_depth			=> 5
-	)
-	PORT MAP
-	(
-		RST_I				=> RST_O,
-		CLK_I				=> CLK_O,
-
-		SDRAM_CLK0_I		=> sdram_clk0,
-		SDRAM_CLK270_I		=> sdram_clk270,
-		SDRAM_CLK270VAR_I	=> sdram_clk270var,
-		
-		CYC_I				=> CYC_I_sdram,
-		STB_I				=> STB_O,
-		SEL_I				=> SEL_O,
-		WE_I				=> WE_O,
-		ACK_O				=> ACK_O_sdram,
-		MRDY_I				=> MRDY_O,
-		SRDY_O				=> SRDY_O_sdram,
-		ADDR_I				=> ADDR_O,
-		DAT_I				=> MDAT_O,
-		DAT_O				=> SDAT_O_sdram,
-
-		-- SDRAM signals
-		sd_clk_p			=> sys_sdr_clk_p,
-		sd_clk_n			=> sys_sdr_clk_n,
-		sd_cke				=> sys_sdr_cke_q,
-		sd_cs_n				=> sys_sdr_cs_qn,
-		sd_cas_n			=> sys_sdr_cas_qn,
-		sd_ras_n			=> sys_sdr_ras_qn,
-		sd_we_n				=> sys_sdr_we_qn,
-		sd_addr				=> sys_sdr_a_q,
-		sd_ba				=> sys_sdr_ba_q,
-		sd_dm				=> sys_sdr_dm_q,
-		sd_dqs				=> sys_sdr_dqs_q,
-		sd_data				=> sys_sdr_data
-		
-	);
-
-inst_vga_frontend : vga_frontend64
-	GENERIC MAP
-	(
-		fifo_depth					=> 4096,
-		fifo_almost_full_thresh		=> 4000,
-		fifo_almost_empty_thresh	=> 800,
-		tsvga						=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_O_vga,
-		STB_O			=> STB_O_vga,
-		WE_O			=> WE_O_vga,
-		SEL_O			=> SEL_O_vga,
-		ACK_I			=> ACK_I_vga,
-		SRDY_I			=> SRDY_I_vga,
-		MRDY_O			=> MRDY_O_vga,
-		ADDR_O			=> ADDR_O_vga,
-		MDAT_I			=> MDAT_I_vga,
-		MDAT_O			=> MDAT_O_vga,
-
-		-- JBUS Slave signals
-		INT_O			=> INT_O_vga,
-		CYC_I			=> CYC_I_vga,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O(3 downto 0),
-		ACK_O			=> ACK_O_vga,
-		SRDY_O			=> SRDY_O_vga,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> MDAT_O(31 downto 0),
-		SDAT_O			=> SDAT_O_vga,
-		
-		-- VGA signals
-		vga_clk_in		=> vga_clk,
-		vga_clk_ce		=> vga_ce,
-		vga_red			=> sys_vga_red,
-		vga_green		=> sys_vga_green,
-		vga_blue		=> sys_vga_blue,
-		vga_blank_n		=> sys_vga_blank_n,
-		vga_sync_n		=> sys_vga_sync_n,
-		vga_hsync		=> sys_vga_hsync,
-		vga_vsync		=> sys_vga_vsync	
-	);
-
-inst_ac97_wb : entity work.ac97_wb
-	GENERIC MAP
-	(
-		fifo_depth		=> 8
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_ac97,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_ac97,
-		SRDY_O			=> SRDY_O_ac97,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O(31 downto 0),
-		DAT_O			=> SDAT_O_ac97,
-		INT_O			=> INT_O_ac97,
-
-		-- AC97 domain
-		ac97_sdata_in	=> sys_ac97_sdata_in,
-		ac97_bit_clk	=> sys_ac97_bit_clk,          
-		ac97_reset_n	=> ac97_rstn,
-		ac97_sdata_out	=> sys_ac97_sdata_out,
-		ac97_ssync		=> sys_ac97_ssync		
-	);
-
-inst_ps2_wb_0: entity work.ps2_wb
-	GENERIC MAP
-	(
-		f_sys_clk	=> sys_freq_in
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_ps2_0,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O(3 downto 0),
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_ps2_0,
-		SRDY_O		=> SRDY_O_ps2_0,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O(31 downto 0),
-		DAT_O		=> SDAT_O_ps2_0,
-		INT_O		=> INT_O_ps2_0,
-		clk_rx		=> ps2_0_clk_rx,
-		data_rx		=> ps2_0_data_rx,
-		clk_tx		=> ps2_0_clk_tx,
-		data_tx		=> ps2_0_data_tx
-	);
-
-inst_ps2_phy_0: entity work.ps2_phy
-	PORT MAP
-	(
-		rst => RST_O,
-		clk => CLK_O,
-		ps2_clk => sys_ps2_0_clk,
-		ps2_data => sys_ps2_0_data,
-		rx_clk => ps2_0_clk_rx,
-		rx_data => ps2_0_data_rx,
-		tx_clk => ps2_0_clk_tx,
-		tx_data => ps2_0_data_tx
-	);
-
-inst_ps2_wb_1: entity work.ps2_wb
-	GENERIC MAP
-	(
-		f_sys_clk	=> sys_freq_in
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_ps2_1,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O(3 downto 0),
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_ps2_1,
-		SRDY_O		=> SRDY_O_ps2_1,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O(31 downto 0),
-		DAT_O		=> SDAT_O_ps2_1,
-		INT_O		=> INT_O_ps2_1,
-		clk_rx		=> ps2_1_clk_rx,
-		data_rx		=> ps2_1_data_rx,
-		clk_tx		=> ps2_1_clk_tx,
-		data_tx		=> ps2_1_data_tx
-	);
-
-inst_ps2_phy_1: entity work.ps2_phy
-	PORT MAP
-	(
-		rst => RST_O,
-		clk => CLK_O,
-		ps2_clk => sys_ps2_1_clk,
-		ps2_data => sys_ps2_1_data,
-		rx_clk => ps2_1_clk_rx,
-		rx_data => ps2_1_data_rx,
-		tx_clk => ps2_1_clk_tx,
-		tx_data => ps2_1_data_tx
-	);
-
-inst_emac_top_jb : entity work.emac_top_jb
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		INT_O		=> INT_O_emac,
-		CYC_I		=> CYC_I_emac,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O(3 downto 0),
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_emac,
-		SRDY_O		=> SRDY_O_emac,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O(31 downto 0),
-		DAT_O		=> SDAT_O_emac,
-		mii_rx_clk	=> sys_phy_rx_clk,
-		mii_rx_dv	=> sys_phy_rx_dv,
-		mii_rx_er	=> sys_phy_rx_er,
-		mii_rx		=> sys_phy_rx,
-		mii_tx_clk	=> sys_phy_tx_clk,
-		mii_tx_en	=> sys_phy_tx_en,
-		mii_tx_er	=> sys_phy_tx_er,
-		mii_tx		=> sys_phy_tx,
-		mii_gtx_clk	=> sys_phy_gtx_clk,
-		mii_crs		=> sys_phy_crs,
-		mii_col		=> sys_phy_col
-		
-	);
-
-	------------------------------------------------------------------
-END;
diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd
deleted file mode 100644
index 20c75fd..0000000
--- a/projects/mips_sys/src/mips_sys_sim.vhd
+++ /dev/null
@@ -1,1048 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-library work;
-use work.mips_types.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.vga_types.all;
-use work.async_types.all;
-use work.async_defs.all;
-
-
-ENTITY mips_sys IS
-GENERIC
-(
-	sys_freq_in			: real		    	:= 100.0;
-	cpu_freq			: real				:= 100.0;
-	sdram_phaseshift	: integer			:= 0;
-	tsvga				: vga_timespec_t 	:= ts_vga_800_600_72
-
-);
-PORT
-(
-	sys_rst_n_in		: in std_logic;
-	sys_clk_in			: in std_logic;
-
-	-- Buttons and LEDs
-	sys_btn				: in unsigned(4 downto 0);
-	sys_dip				: in unsigned(7 downto 0);
-	sys_led				: out unsigned(8 downto 0);
-
-	-- UART
-	sys_uart0_rx		: in std_logic;
-	sys_uart0_tx		: out std_logic;
-	sys_uart1_rx		: in std_logic;
-	sys_uart1_tx		: out std_logic;
-	sys_uart2_rx		: in std_logic;
-	sys_uart2_tx		: out std_logic;
-
-	-- LCD
-	sys_lcd_d			: inout unsigned(3 downto 0);
-	sys_lcd_e			: out std_logic;
-	sys_lcd_rs			: out std_logic;
-	sys_lcd_rw			: out std_logic;
-
-	-- DDR SDRAM
-	sys_sdr_clk_p		: out std_logic;    -- ddr_sdram_clock
-	sys_sdr_clk_n		: out std_logic;    -- /ddr_sdram_clock
-	sys_sdr_cke_q		: out std_logic;    -- clock enable
-	sys_sdr_cs_qn		: out std_logic;    -- /chip select
-	sys_sdr_ras_qn		: out std_logic;    -- /ras
-	sys_sdr_cas_qn		: out std_logic;    -- /cas
-	sys_sdr_we_qn		: out std_logic;    -- /write enable
-	sys_sdr_dm_q		: out unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	sys_sdr_dqs_q		: inout unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	sys_sdr_ba_q		: out unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	sys_sdr_a_q			: out unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	sys_sdr_data		: inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-	sys_sdr_clk_fb		: in std_logic;
-	
-	-- VGA
-	sys_vga_clk			: out std_logic;
-	sys_vga_red			: out unsigned(7 downto 0);
-	sys_vga_green		: out unsigned(7 downto 0);
-	sys_vga_blue		: out unsigned(7 downto 0);
-	sys_vga_blank_n		: out std_logic;
-	sys_vga_sync_n		: out std_logic;
-	sys_vga_hsync		: out std_logic;
-	sys_vga_vsync		: out std_logic;
-
-	sys_usb_d			: inout unsigned(15 downto 0);
-	sys_usb_a			: out unsigned(1 downto 0);
-	sys_usb_csn			: out std_logic;
-	sys_usb_wrn			: out std_logic;
-	sys_usb_rdn			: out std_logic;
-	sys_usb_rstn		: out std_logic;
-	sys_usb_int			: in std_logic;
-
-	sys_flash_ssram_d		: inout unsigned(31 downto 0);
-	sys_flash_ssram_a		: out unsigned(24 downto 0);
-	sys_flash_ce			: out std_logic;
-	sys_flash_ssram_we_n	: out std_logic;
-	sys_flash_ssram_oe_n	: out std_logic;
-	sys_flash_ac97_rstn		: out std_logic;
-	sys_flash_byten			: out std_logic;	
-	
-	sys_ssram_clk			: out std_logic;
-	sys_ssram_clk_fb		: in std_logic;
-	sys_ssram_cke_n			: out std_logic;
-	sys_ssram_ce_n			: out std_logic;
-	sys_ssram_bw_n			: out unsigned(3 downto 0);
-	sys_ssram_dp			: inout unsigned(3 downto 0);
-	sys_ssram_adv			: out std_logic;
-	sys_ssram_mode			: out std_logic;
-	sys_ssram_zz			: out std_logic;
-
-	sys_ac97_sdata_in		: in  std_logic;
-	sys_ac97_bit_clk		: in  std_logic;
-	sys_ac97_sdata_out		: out std_logic;
-	sys_ac97_ssync			: out std_logic;
-
-	sys_ps2_clk				: inout std_logic;
-	sys_ps2_data			: inout std_logic;
-
-	sys_phy_rstn			: out std_logic;
-	sys_phy_mdc				: out std_logic;
-	sys_phy_mdio			: inout std_logic;
-	sys_phy_int				: in  std_logic;
-
-	sys_phy_rx_clk			: in  STD_LOGIC;
-	sys_phy_rx_dv			: in  STD_LOGIC;
-	sys_phy_rx_er			: in  STD_LOGIC;
-	sys_phy_rx				: in unsigned(7 downto 0);
-	sys_phy_tx_clk			: in  STD_LOGIC;
-	sys_phy_tx_en			: out STD_LOGIC;
-	sys_phy_tx_er			: out STD_LOGIC;
-	sys_phy_tx				: out unsigned(7 downto 0);
-	sys_phy_gtx_clk			: out STD_LOGIC;
-	sys_phy_crs				: in  STD_LOGIC;
-	sys_phy_col				: in  STD_LOGIC;
-
-	sys_error				: out unsigned(1 downto 0) -- indicates Errors
-	
-);
---	attribute BUFFER_TYPE : string;
---	attribute BUFFER_TYPE of sys_clk_in			: signal is "BUFG";
---	attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb	: signal is "BUFG";
-
-END mips_sys;
-
-ARCHITECTURE behavior OF mips_sys IS 
-
-	signal cpu_clk		: std_logic;
-	signal nmi			: std_logic;
-	signal eb			: std_logic;
-	signal sdram_clk0			: std_logic;
-	signal sdram_clk270			: std_logic;
-	signal sdram_clk270var		: std_logic;
-	signal vga_clk				: std_logic;
-	signal vga_ce				: std_logic;
-	signal rst_in		: std_logic;
-	signal int_timer	: std_logic;
-	signal int_uart0	: std_logic;
-	signal int_uart1	: std_logic;
-	signal int_uart2	: std_logic;
-	signal locked		: std_logic;
-	signal ac97_rstn	: std_logic;
-	signal flash_rstn	: std_logic;
-	signal ADDR_I_usb 	: unsigned(31 downto 0);
-	signal ADDR_I_ssram	: unsigned(31 downto 0);
-	signal ssram_clk	: std_logic;
-	signal ssram_a		: unsigned(24 downto 0);
-	signal ssram_do		: unsigned(31 downto 0);
-	signal ssram_oe_n	: std_logic;
-	signal ssram_we_n	: std_logic;
-	signal ssram_d_drv	: std_logic;
-	signal ssram_bsy	: std_logic;
-	signal flash_a		: unsigned(24 downto 0);
-	signal flash_do		: unsigned(31 downto 0);
-	signal flash_oe_n	: std_logic;
-	signal flash_we_n	: std_logic;
-	signal flash_d_drv	: std_logic;
-	signal flash_bsy	: std_logic;
-	signal flash_page_mode_en	: std_logic;
-
-	signal ps2_clk_rx	: std_logic;
-	signal ps2_data_rx	: std_logic;
-	signal ps2_clk_tx	: std_logic;
-	signal ps2_data_tx	: std_logic;
-	
-	-- Arbiter
-	constant ARB_MAX_MASTER	: natural := 2;
-	signal arb_idx		: natural range 0 to ARB_MAX_MASTER-1;
-	signal arb_req		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	signal arb_gnt		: unsigned (ARB_MAX_MASTER-1 downto 0);
-	
-	-- J-Bus signals
-	signal CLK_O		: std_logic;
-	signal RST_O		: std_logic;
-	signal INT	 		: unsigned(5 downto 0);
-	signal MDAT_I		: word_t;
-	signal MDAT_O 		: word_t;
-	signal ADDR_O 		: word_t;
-	signal SEL_O 		: unsigned(3 downto 0);
-	signal WE_O 		: std_logic;
-	signal CYC_O 		: std_logic;
-	signal STB_O 		: std_logic;
-	signal ACK_I		: std_logic;
-	signal SRDY_I		: std_logic;
-	signal MRDY_O		: std_logic;
-
-	-- CPU Master
-	signal MRDY_O_cpu	: std_logic;
-	signal MDAT_O_cpu	: word_t;
-	signal ADDR_O_cpu	: word_t;
-	signal SEL_O_cpu	: unsigned(3 downto 0);
-	signal WE_O_cpu		: std_logic;
-	signal CYC_O_cpu	: std_logic;
-	signal STB_O_cpu	: std_logic;
-	signal SRDY_I_cpu	: std_logic;
-	signal ACK_I_cpu	: std_logic;
-
-	-- VGA Master
-	signal MRDY_O_vga	: std_logic;
-	signal ADDR_O_vga	: word_t;
-	signal SEL_O_vga	: unsigned(7 downto 0);
-	signal WE_O_vga		: std_logic;
-	signal CYC_O_vga	: std_logic;
-	signal STB_O_vga	: std_logic;
-	signal SRDY_I_vga	: std_logic;
-	signal ACK_I_vga	: std_logic;
-	signal MDAT_I_vga	: unsigned(63 downto 0);
-	signal MDAT_O_vga	: unsigned(63 downto 0);
-
-	-- Slaves
-	signal CYC_I_flash	: std_logic;
-	signal ACK_O_flash	: std_logic;
-	signal SRDY_O_flash	: std_logic;
-	signal SDAT_O_flash	: unsigned(31 downto 0);
-
-	signal CYC_I_usb	: std_logic;
-	signal ACK_O_usb	: std_logic;
-	signal SRDY_O_usb	: std_logic;
-	signal SDAT_O_usb	: unsigned(31 downto 0);
-
-	signal CYC_I_sdram	: std_logic;
-	signal ACK_O_sdram	: std_logic;
-	signal SRDY_O_sdram	: std_logic;
-	signal SDAT_O_sdram	: unsigned(63 downto 0);
-	signal SDAT_I_sdram	: unsigned(63 downto 0);
-	signal SEL_I_sdram	: unsigned(7 downto 0);
-
-	signal CYC_I_rom	: std_logic;
-	signal ACK_O_rom	: std_logic;
-	signal SRDY_O_rom	: std_logic;
-	signal SDAT_O_rom	: unsigned(31 downto 0);
-
-	signal CYC_I_gpio	: std_logic;
-	signal ACK_O_gpio	: std_logic;
-	signal SRDY_O_gpio	: std_logic;
-	signal SDAT_O_gpio	: unsigned(31 downto 0);
-
-	signal CYC_I_uart0	: std_logic;
-	signal ACK_O_uart0	: std_logic;
-	signal SRDY_O_uart0	: std_logic;
-	signal SDAT_O_uart0	: unsigned(31 downto 0);
-	signal CYC_I_uart1	: std_logic;
-	signal ACK_O_uart1	: std_logic;
-	signal SRDY_O_uart1	: std_logic;
-	signal SDAT_O_uart1	: unsigned(31 downto 0);
-	signal CYC_I_uart2	: std_logic;
-	signal ACK_O_uart2	: std_logic;
-	signal SRDY_O_uart2	: std_logic;
-	signal SDAT_O_uart2	: unsigned(31 downto 0);
-
-	signal CYC_I_vga	: std_logic;
-	signal ACK_O_vga	: std_logic;
-	signal SRDY_O_vga	: std_logic;
-	signal SDAT_O_vga	: unsigned(31 downto 0);
-
-	signal CYC_I_ssram	: std_logic;
-	signal ACK_O_ssram	: std_logic;
-	signal SRDY_O_ssram	: std_logic;
-	signal SDAT_O_ssram	: unsigned(31 downto 0);
-
-	signal INT_O_ac97	: std_logic;
-	signal CYC_I_ac97	: std_logic;
-	signal ACK_O_ac97	: std_logic;
-	signal SRDY_O_ac97	: std_logic;
-	signal SDAT_O_ac97	: unsigned(31 downto 0);
-
-	signal INT_O_ps2	: std_logic;
-	signal CYC_I_ps2	: std_logic;
-	signal ACK_O_ps2	: std_logic;
-	signal SRDY_O_ps2	: std_logic;
-	signal SDAT_O_ps2	: unsigned(31 downto 0);
-
-	signal INT_O_emac	: std_logic;
-	signal CYC_I_emac	: std_logic;
-	signal ACK_O_emac	: std_logic;
-	signal SRDY_O_emac	: std_logic;
-	signal SDAT_O_emac	: unsigned(31 downto 0);
-
-	signal gpi_0		: unsigned(31 downto 0);
-	signal gpo_0		: unsigned(31 downto 0);
-
-	signal ac97_inten	: std_logic;
-	signal usb_inten	: std_logic;
-	signal phy_inten	: std_logic;
-
-	signal debug		: unsigned(1 downto 0);
-
-	-- DDR SDRAM
-	constant BURST_LEN	: natural := 2;
-	constant topad		: time := 3 ns;
-	constant vga_freq	: real := real(tsvga.f_pxl_clk)/1.0E6;
-	
---	attribute rom_style: string;
---	attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
---	attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
-
-	type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97, mem_emac);
-	signal mem_area : mem_area_t;
-
-BEGIN
-
-	------------------------------------
-	-- GPIO_0 bits used for
-	--  8.. 0	= O: LED 8..0
-	-- 11.. 9	= free    
-	-- 12		= O: USB RST
-	-- 13		= O: USB INTEN
-	-- 14		= free
-	-- 15		= O: AC97 INTEN
-	-- 32..16	= I: DIP 7..0
-	-- 28..24	= I: BTN 4..0
-	-- 29		= O: PHY RESET
-	-- 30		= O: PHY MDC
-	-- 31		= IO: PHY MDIO
-	------------------------------------
-	gpi_0(28 downto 24)		<= sys_btn;
-	gpi_0(23 downto 16)		<= sys_dip;
-	gpi_0(31)				<= sys_phy_mdio;
-	
-	sys_led					<= gpo_0(8 downto 0);
-	sys_usb_rstn			<= not gpo_0(12);
-	usb_inten				<= gpo_0(13);
-	phy_inten				<= gpo_0(14);
-	ac97_inten				<= gpo_0(15);
-	sys_phy_rstn			<= not gpo_0(29);
-	sys_phy_mdc				<= gpo_0(30);
-	sys_phy_mdio			<= gpo_0(31);
-
-	eb						<= sys_dip(7);
-	sys_error				<= debug;
-	nmi						<= not sys_rst_n_in;
-	rst_in 					<= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
-	sys_flash_byten			<= '1';
-	ADDR_I_usb				<= X"0000000" & "00" & ADDR_O(3 downto 2);
-	ADDR_I_ssram			<= ("0000000000000" & ADDR_O(19 downto 2)) & '0';
-
-	SDAT_I_sdram			<= MDAT_O & MDAT_O;
-	SEL_I_sdram				<= "0000" & SEL_O;
-
-	sys_flash_ac97_rstn		<= ac97_rstn and flash_rstn;
-	vga_ce					<= not RST_O;
-	
-sys_flash_ssram_out:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			sys_flash_ssram_d		<= (others => 'Z') after topad;
-			sys_flash_ssram_oe_n	<= '1';
-			sys_flash_ssram_we_n	<= '1';
-			if flash_bsy = '1' then
-				sys_flash_ssram_oe_n	<= flash_oe_n;
-				sys_flash_ssram_we_n	<= flash_we_n;
-				sys_flash_ssram_a 		<= ('0' & flash_a(24 downto 2) & '0') after topad;
-				if flash_d_drv = '1' then
-					sys_flash_ssram_d	<= flash_do after topad;
-				end if;
-			elsif ssram_bsy = '1' then
-				sys_flash_ssram_oe_n	<= ssram_oe_n;
-				sys_flash_ssram_we_n	<= ssram_we_n;
-				sys_flash_ssram_a 		<= ssram_a after topad;
-				if ssram_d_drv = '1' then
-					sys_flash_ssram_d	<= ssram_do after topad;
-				end if;
-			end if;	
-		end if;
-	end process;
-	
-	---------------------------------------------------------------
-	-- Arbiter
-	MRDY_O		<= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
-	MDAT_O		<= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	ADDR_O		<= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
-	SEL_O		<= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
-	WE_O		<= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
-	CYC_O		<= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
-	STB_O		<= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
-	SRDY_I_cpu	<= SRDY_I and arb_gnt(0);
-	SRDY_I_vga	<= SRDY_I and arb_gnt(1);
-	ACK_I_cpu	<= ACK_I and arb_gnt(0);
-	ACK_I_vga	<= ACK_I and arb_gnt(1);
-	
-	arb_req(0)	<= CYC_O_cpu;
-	arb_req(1)	<= CYC_O_vga;
-	
-	MDAT_I_vga	<= SDAT_O_sdram(63 downto 32) & MDAT_I;
-	
-arbiter_proc:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			if RST_O = '1' then
-				arb_gnt	<= (others => '0');
-				arb_idx	<= 0;
-			elsif arb_req(arb_idx) = '0' then
-				if arb_idx /= ARB_MAX_MASTER-1 then
-					arb_idx	<= arb_idx + 1;
-				else
-					arb_idx	<= 0;
-				end if;
-			else	
-				arb_gnt	<= (others => '0');
-				arb_gnt(arb_idx)	<= '1';
-			end if;	
-		end if;
-	end process;
-	
-int_sample:
-	process(CLK_O)
-	begin
-		if rising_edge(CLK_O) then
-			INT <= int_timer & (INT_O_ps2 or INT_O_emac) & (ac97_inten and INT_O_ac97) & (usb_inten and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4);
-		end if;
-	end process;
-	
-mem_mux:
-	process(ADDR_O)
-	begin
-		mem_area	<= mem_dead;
-		flash_page_mode_en	<= '0';
-		if ADDR_O(31 downto 28) = X"0" then
-			mem_area	<= mem_flash;
-			flash_page_mode_en	<= '1';
-		elsif ADDR_O(31 downto 28) = X"1" then
-			mem_area	<= mem_emac;
-		elsif ADDR_O(31 downto 28) = X"A" then
-			if ADDR_O(27 downto 26) = "00" then
-				if ADDR_O(18 downto 16) = "000" then
-					mem_area	<= mem_gpio;
-				elsif ADDR_O(18 downto 16) = "001" then
-					if ADDR_O(9 downto 8) = "00" then
-						mem_area	<= mem_uart0;
-					elsif ADDR_O(9 downto 8) = "01" then
-						mem_area	<= mem_uart1;
-					elsif ADDR_O(9 downto 8) = "10" then
-						mem_area	<= mem_uart2;
-					end if;						
-				elsif ADDR_O(18 downto 16) = "010" then
-					mem_area	<= mem_usb;
-				elsif ADDR_O(18 downto 16) = "011" then
-					mem_area	<= mem_vga;
-				elsif ADDR_O(18 downto 16) = "100" then
-					mem_area	<= mem_ac97;
-				elsif ADDR_O(18 downto 16) = "101" then
-					mem_area	<= mem_emac;
-				end if;	
-			elsif ADDR_O(27 downto 26) = "01" then
-				mem_area	<= mem_flash;
-			elsif ADDR_O(27 downto 26) = "10" then
-				mem_area	<= mem_ssram;
-			end if;	
-		elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
-			mem_area	<= mem_rom;
-		elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
-			mem_area	<= mem_sdram;
-		end if;
-	end process;	
-
-signal_mux:
-	process(mem_area, CYC_O)
-	begin
-	
-		CYC_I_uart0		<= '0';
-		CYC_I_uart1		<= '0';
-		CYC_I_uart2		<= '0';
-		CYC_I_gpio		<= '0';
-		CYC_I_flash		<= '0';
-		CYC_I_usb		<= '0';
-		CYC_I_rom		<= '0';
-		CYC_I_sdram		<= '0';
-		CYC_I_vga		<= '0';
-		CYC_I_ssram		<= '0';
-		CYC_I_ac97		<= '0';
-		CYC_I_emac		<= '0';
-		
-		case mem_area is
-
-		when mem_gpio =>
-			CYC_I_gpio		<= CYC_O;
-
-		when mem_uart0 =>
-			CYC_I_uart0		<= CYC_O;
-
-		when mem_uart1 =>
-			CYC_I_uart1		<= CYC_O;
-
-		when mem_uart2 =>
-			CYC_I_uart2		<= CYC_O;
-
-		when mem_flash =>
-			CYC_I_flash		<= CYC_O;
-
-		when mem_usb =>
-			CYC_I_usb		<= CYC_O;
-
-		when mem_rom =>
-			CYC_I_rom		<= CYC_O;
-
-		when mem_sdram =>
-			CYC_I_sdram		<= CYC_O;
-		
-		when mem_vga =>
-			CYC_I_vga		<= CYC_O;
-
-		when mem_ac97 =>
-			CYC_I_ac97		<= CYC_O;
-
-		when mem_emac =>
-			CYC_I_emac		<= CYC_O;
-
-		when mem_ssram =>
-			CYC_I_ssram		<= CYC_O;
-
-		when others => null;
-		
-		end case;
-		
-	end process;
-
-------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97 or SRDY_O_emac;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97 or ACK_O_emac;
- 	MDAT_I		<=	SDAT_O_ssram when CYC_I_ssram = '1' else
- 					SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
-					SDAT_O_rom when CYC_I_rom = '1' else
-					SDAT_O_flash when CYC_I_flash = '1' else
-					SDAT_O_usb when CYC_I_usb = '1' else
-					SDAT_O_uart0 when CYC_I_uart0 = '1' else
-					SDAT_O_uart1 when CYC_I_uart1 = '1' else
-					SDAT_O_uart2 when CYC_I_uart2 = '1' else
-					SDAT_O_vga when CYC_I_vga = '1' else
-					SDAT_O_ac97 when CYC_I_ac97 = '1' else
-					SDAT_O_emac when CYC_I_emac = '1' else
-					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
-
-------------------------------------------------------------------
-inst_mips_top: entity work.mips_top
-	PORT MAP
-	(
-		debug			=> debug,
-		eb				=> eb,
-		nmi				=> nmi,
-		cpu_clk			=> cpu_clk,
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-		ACK_I			=> ACK_I_cpu,
-		SRDY_I			=> SRDY_I_cpu,
-		MRDY_O			=> MRDY_O_cpu,
-		CYC_O			=> CYC_O_cpu,
-		STB_O			=> STB_O_cpu,
-		WE_O			=> WE_O_cpu,
-		SEL_O			=> SEL_O_cpu,
-		DAT_I			=> MDAT_I,
-		DAT_O			=> MDAT_O_cpu,
-		ADDR_O			=> ADDR_O_cpu,
-		INT				=> INT
-	);
-
-inst_rom_wb : entity work.rom_wb
-	PORT MAP
-	(
-		CLK_I	=> CLK_O,
-		RST_I	=> RST_O,
-		CYC_I	=> CYC_I_rom,
-		STB_I	=> STB_O,
-		WE_I	=> WE_O,
-		ACK_O	=> ACK_O_rom,
-		MRDY_I	=> MRDY_O,
-		SRDY_O	=> SRDY_O_rom,
-		ADDR_I	=> ADDR_O,
-		DAT_O	=> SDAT_O_rom
-	);
-
-
-inst_lcd_port: entity work.lcd_port
-	PORT MAP
-	(
-		clk => CLK_O,
-		rst => RST_O,
-		we => '0',
-		din => X"00",
-		dout => open,
-		lcd_d => sys_lcd_d,
-		lcd_e => sys_lcd_e,
-		lcd_rs => sys_lcd_rs,
-		lcd_rw => sys_lcd_rw
-	);
-	
-inst_gpio_wb : entity work.gpio_wb
-	GENERIC MAP
-	(
-		f_sysclk	=> sys_freq_in
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_gpio,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_gpio,
-		SRDY_O		=> SRDY_O_gpio,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_gpio,
-		INT_TIM_O	=> int_timer,
-
-		sys_gpi_0	=> gpi_0,
-		sys_gpo_0	=> gpo_0
-	);
-
-inst_flash_port : entity work.flash_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> sys_freq_in,
-		addr_width		=> 25,
-		data_width		=> 32,
-		async_timespec	=> ts_flash
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_flash,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_flash,
-		SRDY_O		=> SRDY_O_flash,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_flash,
-		port_bsyo	=> flash_bsy,
-		port_bsyi	=> ssram_bsy,
-		port_a		=> flash_a,
-		port_di		=> sys_flash_ssram_d,
-		port_do		=> flash_do,
-		port_d_drv	=> flash_d_drv,
-		port_wr		=> flash_we_n,
-		port_rd		=> flash_oe_n,
-		flash_cs	=> sys_flash_ce,
-		flash_rst	=> flash_rstn
-	);
-
-inst_usb_port : entity work.async_port_wb
-	GENERIC MAP
-	(
-		f_sysclk		=> sys_freq_in,
-		addr_width		=> 2,
-		data_width		=> 16,
-		byte_sel_width	=> 1,
-		async_timespec	=> ts_usb
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_usb,
-		STB_I		=> STB_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_usb,
-		SRDY_O		=> SRDY_O_usb,
-		MRDY_I		=> MRDY_O,
-		SEL_I		=> SEL_O,
-		ADDR_I		=> ADDR_I_usb,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_usb,
-		page_mode_en	=> '0',
-		async_a		=> sys_usb_a,
-		async_d		=> sys_usb_d,
-		async_cs	=> sys_usb_csn,
-		async_wr	=> sys_usb_wrn,
-		async_rd	=> sys_usb_rdn,
-		async_be	=> open,
-		async_rst	=> open
-	);
-
-inst_uart_wb_0 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_uart0,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart0,
-		SRDY_O		=> SRDY_O_uart0,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_uart0,
-		INT_O		=> int_uart0,
-		ser_rx		=> sys_uart0_rx,
-		ser_tx		=> sys_uart0_tx
-	);
-
-inst_uart_wb_1 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_uart1,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart1,
-		SRDY_O		=> SRDY_O_uart1,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_uart1,
-		INT_O		=> int_uart1,
-		ser_rx		=> sys_uart1_rx,
-		ser_tx		=> sys_uart1_tx
-	);
-
-inst_uart_wb_2 : entity work.uart_wb
-	GENERIC MAP
-	(
-		simulate_tx		=> true
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_uart2,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_uart2,
-		SRDY_O		=> SRDY_O_uart2,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_uart2,
-		INT_O		=> int_uart2,
-		ser_rx		=> sys_uart2_rx,
-		ser_tx		=> sys_uart2_tx
-	);
-inst_ssram_port_wb : entity work.ssram_port_wb
-	GENERIC MAP
-	(
-		addr_width		=> 25,
-		data_width		=> 32,
-		parity_width	=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		RST_I		=> RST_O,
-		CLK_I		=> CLK_O,
-		CYC_I		=> CYC_I_ssram,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_ssram,
-		SRDY_O		=> SRDY_O_ssram,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_I_ssram,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_ssram,
-		
-		-- Sync SRAM domain
-		ssram_clk_o		=> sys_ssram_clk,
-		ssram_clk_fb	=> sys_ssram_clk_fb,
-		ssram_cke_n		=> sys_ssram_cke_n,
-		ssram_ce_n		=> sys_ssram_ce_n,
-		port_bsyo		=> ssram_bsy,
-		port_bsyi		=> flash_bsy,
-		port_di			=> sys_flash_ssram_d,
-		port_do			=> ssram_do,
-		port_d_drv		=> ssram_d_drv,
-		port_wr			=> ssram_we_n,
-		port_rd			=> ssram_oe_n,
-		port_a			=> ssram_a,
-		ssram_adv		=> sys_ssram_adv,
-		ssram_mode		=> sys_ssram_mode,
-		ssram_zz		=> sys_ssram_zz,
-		ssram_dp		=> sys_ssram_dp,
-		ssram_bw_n		=> sys_ssram_bw_n
-	);
-
-inst_clockgen : entity work.clockgen
-	GENERIC MAP
-	(
-		clk_in_freq				=> sys_freq_in,
-		cpu_clk_out_freq		=> cpu_freq,
-		vga_clk_out_freq		=> vga_freq,
-		sdr0_clk_out_phaseshift	=> 0,
-		sdr1_clk_out_phaseshift	=> 0
-	)
-	PORT MAP 
-	(
-		-- Clocks and Reset
-		rst_in				=> rst_in,   -- external async reset, low active
-		clk_in				=> sys_clk_in,   -- system clock (e.g. 100MHz), from board
-		sys_rst_out			=> RST_O,  
-		sys_clk_out			=> CLK_O,
-		vga_clk_out			=> vga_clk,
-		cpu_clk_out			=> cpu_clk,
-		sdr0_clk_fb_in		=> sys_sdr_clk_fb,   -- feedback clock
-		sdr0_clk0_out		=> sdram_clk0,  -- System clock #0, dcm#0 output 0°
-		sdr0_clk270_out		=> sdram_clk270,  -- System clock #0, dcm#0 output 270°
-		sdr1_clk0_out		=> open,  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
-		sdr1_clk270_out		=> sdram_clk270var  -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
-	);
-
-
-inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
-	GENERIC MAP
-	(
-		BL				=> BURST_LEN,
-		f_sysclk		=> sys_freq_in,
-		f_sdrclk		=> sys_freq_in,
-		fifo_depth		=> 5
-	)
-	PORT MAP
-	(
-		RST_I				=> RST_O,
-		CLK_I				=> CLK_O,
-
-		SDRAM_CLK0_I		=> sdram_clk0,
-		SDRAM_CLK270_I		=> sdram_clk270,
-		SDRAM_CLK270VAR_I	=> sdram_clk270var,
-		
-		CYC_I				=> CYC_I_sdram,
-		STB_I				=> STB_O,
-		SEL_I				=> SEL_I_sdram,
-		WE_I				=> WE_O,
-		ACK_O				=> ACK_O_sdram,
-		MRDY_I				=> MRDY_O,
-		SRDY_O				=> SRDY_O_sdram,
-		ADDR_I				=> ADDR_O,
-		DAT_I				=> SDAT_I_sdram,
-		DAT_O				=> SDAT_O_sdram,
-
-		-- SDRAM signals
-		sd_clk_p			=> sys_sdr_clk_p,
-		sd_clk_n			=> sys_sdr_clk_n,
-		sd_cke				=> sys_sdr_cke_q,
-		sd_cs_n				=> sys_sdr_cs_qn,
-		sd_cas_n			=> sys_sdr_cas_qn,
-		sd_ras_n			=> sys_sdr_ras_qn,
-		sd_we_n				=> sys_sdr_we_qn,
-		sd_addr				=> sys_sdr_a_q,
-		sd_ba				=> sys_sdr_ba_q,
-		sd_dm				=> sys_sdr_dm_q,
-		sd_dqs				=> sys_sdr_dqs_q,
-		sd_data				=> sys_sdr_data
-		
-	);
-
-inst_vga_frontend : entity work.vga_frontend64
-	GENERIC MAP
-	(
-		fifo_depth					=> 2048,
-		fifo_almost_full_thresh		=> 1860,
-		fifo_almost_empty_thresh	=> 256,
-		tsvga						=> tsvga
-	)
-	PORT MAP
-	(
-		-- System signals
-		RST_I			=> RST_O,
-		CLK_I			=> CLK_O,
-
-		-- JBUS Master signals
-		CYC_O			=> CYC_O_vga,
-		STB_O			=> STB_O_vga,
-		WE_O			=> WE_O_vga,
-		SEL_O			=> SEL_O_vga,
-		ACK_I			=> ACK_I_vga,
-		SRDY_I			=> SRDY_I_vga,
-		MRDY_O			=> MRDY_O_vga,
-		ADDR_O			=> ADDR_O_vga,
-		MDAT_I			=> MDAT_I_vga,
-		MDAT_O			=> MDAT_O_vga,
-
-		-- JBUS Slave signals
-		CYC_I			=> CYC_I_vga,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		SEL_I			=> SEL_O,
-		ACK_O			=> ACK_O_vga,
-		SRDY_O			=> SRDY_O_vga,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		SDAT_I			=> MDAT_O,
-		SDAT_O			=> SDAT_O_vga,
-
-		-- VGA signals
-		vga_clk_in		=> vga_clk,
-		vga_clk_ce		=> vga_ce,
-		vga_red			=> sys_vga_red,
-		vga_green		=> sys_vga_green,
-		vga_blue		=> sys_vga_blue,
-		vga_blank_n		=> sys_vga_blank_n,
-		vga_sync_n		=> sys_vga_sync_n,
-		vga_hsync		=> sys_vga_hsync,
-		vga_vsync		=> sys_vga_vsync	
-	);
-
-inst_ac97_wb : entity work.ac97_wb
-	GENERIC MAP
-	(
-		fifo_depth		=> 4
-	)
-	PORT MAP
-	(
-		-- J-Bus domain
-		CLK_I			=> CLK_O,
-		RST_I			=> RST_O,
-		CYC_I			=> CYC_I_ac97,
-		STB_I			=> STB_O,
-		WE_I			=> WE_O,
-		ACK_O			=> ACK_O_ac97,
-		SRDY_O			=> SRDY_O_ac97,
-		MRDY_I			=> MRDY_O,
-		ADDR_I			=> ADDR_O,
-		DAT_I			=> MDAT_O,
-		DAT_O			=> SDAT_O_ac97,
-		INT_O			=> INT_O_ac97,
-
-		-- AC97 domain
-		ac97_sdata_in	=> sys_ac97_sdata_in,
-		ac97_bit_clk	=> sys_ac97_bit_clk,          
-		ac97_reset_n	=> ac97_rstn,
-		ac97_sdata_out	=> sys_ac97_sdata_out,
-		ac97_ssync		=> sys_ac97_ssync		
-	);
-
-inst_ps2_wb: entity work.ps2_wb
-	GENERIC MAP
-	(
-		f_sys_clk	=> sys_freq_in
-	)
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		CYC_I		=> CYC_I_ps2,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_ps2,
-		SRDY_O		=> SRDY_O_ps2,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_ps2,
-		INT_O		=> INT_O_ps2,
-		clk_rx		=> ps2_clk_rx,
-		data_rx		=> ps2_data_rx,
-		clk_tx		=> ps2_clk_tx,
-		data_tx		=> ps2_data_tx
-	);
-
-inst_ps2_phy: entity work.ps2_phy
-	PORT MAP
-	(
-		rst => RST_O,
-		clk => CLK_O,
-		ps2_clk => sys_ps2_clk,
-		ps2_data => sys_ps2_data,
-		rx_clk => ps2_clk_rx,
-		rx_data => ps2_data_rx,
-		tx_clk => ps2_clk_tx,
-		tx_data => ps2_data_tx
-	);
-
-inst_emac_jb : entity work.emac_top_jb
-	PORT MAP
-	(
-		CLK_I		=> CLK_O,
-		RST_I		=> RST_O,
-		INT_O		=> INT_O_emac,
-		CYC_I		=> CYC_I_emac,
-		STB_I		=> STB_O,
-		SEL_I		=> SEL_O,
-		WE_I		=> WE_O,
-		ACK_O		=> ACK_O_emac,
-		SRDY_O		=> SRDY_O_emac,
-		MRDY_I		=> MRDY_O,
-		ADDR_I		=> ADDR_O,
-		DAT_I		=> MDAT_O,
-		DAT_O		=> SDAT_O_emac,
-		mii_rx_clk	=> sys_phy_rx_clk,
-		mii_rx_dv	=> sys_phy_rx_dv,
-		mii_rx_er	=> sys_phy_rx_er,
-		mii_rx		=> sys_phy_rx,
-		mii_tx_clk	=> sys_phy_tx_clk,
-		mii_tx_en	=> sys_phy_tx_en,
-		mii_tx_er	=> sys_phy_tx_er,
-		mii_tx		=> sys_phy_tx,
-		mii_gtx_clk	=> sys_phy_gtx_clk,
-		mii_crs		=> sys_phy_crs,
-		mii_col		=> sys_phy_col
-		
-	);
-
-
-	------------------------------------------------------------------
-END;
diff --git a/projects/mips_sys/src/ram_ld.vhd b/projects/mips_sys/src/ram_ld.vhd
deleted file mode 100644
index 17879e1..0000000
--- a/projects/mips_sys/src/ram_ld.vhd
+++ /dev/null
@@ -1,173 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY ram IS
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	COMPONENT dpram_2w2r
-	Generic 
-	(
-		addr_width : integer;
-		data_width : integer
-	);
-	Port
-	(
-		clk_a		: in  STD_LOGIC;
-		clk_b		: in  STD_LOGIC;
-		en_a		: in  STD_LOGIC;
-		en_b		: in  STD_LOGIC;
-		we_a		: in  STD_LOGIC;
-		we_b		: in  STD_LOGIC;
-		addr_a		: in  unsigned (addr_width-1 downto 0);
-		addr_b		: in  unsigned (addr_width-1 downto 0);
-		din_a		: in  unsigned (data_width-1 downto 0);
-		din_b		: in  unsigned (data_width-1 downto 0);
-		dout_a		: out unsigned (data_width-1 downto 0);
-		dout_b		: out unsigned (data_width-1 downto 0)
-	);
-	END COMPONENT;
-	
-	signal jtag_clk		: STD_LOGIC;
-	signal jtag_we		: unsigned(3 downto 0);
-	signal jtag_addr	: unsigned (15 downto 0);
-	signal jtag_dout	: unsigned (31 downto 0);
-	signal jtag_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-	
-BEGIN
-
-gen_sram:
-	for i in 0 to 3 generate
-	begin
-	inst_dpram_2w2r : dpram_2w2r
-		GENERIC MAP
-		(
-			addr_width	=> 11,
-			data_width	=> 8
-		)
-		PORT MAP
-		(
-			clk_a		=> clk,
-			en_a		=> ce,
-			we_a		=> we(i),
-			addr_a		=> addr(12 downto 2),
-			din_a		=> din((i+1)*8-1 downto i*8),
-			dout_a		=> dout((i+1)*8-1 downto i*8),
-
-			clk_b		=> jtag_clk,
-			en_b		=> jtag_we(i),
-			we_b		=> jtag_we(i),
-			addr_b		=> jtag_addr(10 downto 0),
-			din_b		=> jtag_din((i+1)*8-1 downto i*8),
-			dout_b		=> jtag_dout((i+1)*8-1 downto i*8)
-		);
-	end generate;
-	
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_addr	<= user_regi(user_regi'left downto jtag_dout'length);
-	jtag_din	<= user_regi(jtag_dout'length-1 downto 0);
-	jtag_clk	<= bs_update1;
-	jtag_we		<= (3 downto 0 => bs_sel);
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;	
-			end if;
-		end if;
-	end process;	
-	
---------------------------------------------------------------------------
-end behavior;
diff --git a/projects/mips_sys/src/ram_sim.vhd b/projects/mips_sys/src/ram_sim.vhd
deleted file mode 100644
index 6d26672..0000000
--- a/projects/mips_sys/src/ram_sim.vhd
+++ /dev/null
@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-ENTITY ram IS
-	Generic 
-	(
-		word_addr_width 	: integer := 6
-	);
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	constant depth : natural := 2**word_addr_width;
-	
-	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
-
-	function sram_clear return sram_t is
-
-	variable result : sram_t;
-	begin
-		for i in 0 to sram_t'length-1 loop
-			result(i) := (others => '0');
-		end loop;
-		return result;
-	end sram_clear;
-
-	signal sram : sram_t := sram_clear;
-	
-BEGIN
-
-
-SRAM_RW:
-	process(clk)
-	variable index : natural range 0 to depth-1;
-	begin
-		if rising_edge(clk) and ce = '1' then
-			index := to_integer(addr(word_addr_width+1 downto 2));
-			if we(0) = '1' then
-				sram(index)(7 downto 0)		<= din(7 downto 0);
-			end if;	
-			if we(1) = '1' then
-				sram(index)(15 downto 8)	<= din(15 downto 8);
-			end if;	
-			if we(2) = '1' then
-				sram(index)(23 downto 16)	<= din(23 downto 16);
-			end if;	
-			if we(3) = '1' then
-				sram(index)(31 downto 24)	<= din(31 downto 24);
-			end if;	
-			dout <= sram(index);
-		end if;	
-	end process;
-	
-end behavior;
diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd
deleted file mode 100644
index c964e6b..0000000
--- a/projects/mips_sys/src/sdram_config.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-	
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-	
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-	
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive	:= 2;		   -- CAS latency [clocks]
-	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
-	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
-	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
-	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
-	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
-
-	constant PWR_UP_WAIT		: real := 220.0E3; -- [ns]
-
-	subtype user_tag_t is unsigned(3 downto 0);
-
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd
deleted file mode 100644
index 5067520..0000000
--- a/projects/mips_sys/src/sdram_config_sim.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: User SDRAM component adjustments
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-package sdram_config is
-
-	constant DDR_DATA_WIDTH 	: positive := 32;  -- External DDR-SDRAM Module data bus width
-	constant DDR_ADDR_WIDTH 	: positive := 13;  -- number of address lines to DDR-SDRAM Device/Module
-	constant DDR_BANK_WIDTH 	: positive := 2;   -- Number of BANK address lines of external DDR-SDRAM
-	constant DDR_ROW_ADDR_WIDTH	: positive := 13;  -- 
-	constant DDR_COL_ADDR_WIDTH	: positive := 9;  -- 
-	
-	constant LMR_REG_BASE		: natural := 0;
-	constant LMR_REG_EXTENDED	: natural := 1;
-	constant LMR_OP_NORMAL		: natural := 0;
-	constant LMR_OP_RES_DLL		: natural := 2;
-	constant LMR_BT_SEQ			: natural := 0;
-	constant LMR_BT_ILVD		: natural := 1;
-	constant LMR_BL2			: natural := 1;
-	constant LMR_BL4			: natural := 2;
-	constant LMR_BL8			: natural := 3;
-	constant LMR_CL2			: natural := 2;
-	constant LMR_CL3			: natural := 3;
-	constant LMR_CL2_5			: natural := 6;
-	
-	-- DDR SDRAM Hardware defined constants
-	constant BIT_AUTO_PRE		: positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
-	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
-	constant ENABLE_PRE_ALL		: std_logic := '1';
-	constant ENABLE_AUTO_PRE	: std_logic := '0';
-	
-	-- DDR-SDR TIMING constants ------------------------------------------------------------------
-	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
-
-	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive	:= 2;   		-- CAS latency [clocks]
-	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
-	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
-	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
-	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
-	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
-
-	constant PWR_UP_WAIT		: real := 22.0E3; -- [ns]
-
-	subtype user_tag_t is unsigned(3 downto 0);
-
-	----------------------------------------------------------------------------------------------
-	
-end sdram_config;
diff --git a/projects/mips_sys/src/sys_types.vhd b/projects/mips_sys/src/sys_types.vhd
deleted file mode 100644
index 2ff4570..0000000
--- a/projects/mips_sys/src/sys_types.vhd
+++ /dev/null
@@ -1,70 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file: 
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-library IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-
-use work.async_types.all;
-
-package async_defs is
-
-	constant ts_flash : async_timespec_t :=
-	(
-		T_leadin			=> 00.0,
-		T_pulse_rd			=> 120.0,
-		T_pulse_wr			=> 70.0,
-		T_leadout			=> 00.0,
-		T_release			=> 40.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 30.0,
-		can_page_rd			=> true,
-		nbits_page_rd		=> 4,
-		pol_cs				=> '1',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-	constant ts_usb : async_timespec_t :=
-	(
-		T_leadin			=> 10.0,
-		T_pulse_rd			=> 60.0,
-		T_pulse_wr			=> 60.0,
-		T_leadout			=> 10.0,
-		T_release			=> 80.0,
-		T_pulse_rst			=> 80.0,
-		T_pulse_page_rd		=> 00.0,
-		can_page_rd			=> false,
-		nbits_page_rd		=> 0,
-		pol_cs				=> '0',
-		pol_oe				=> '0',
-		pol_we				=> '0',
-		pol_be				=> '0',
-		pol_rst				=> '0'
-	);
-
-	----------------------------------------------------------------------------------------------
-	
-end async_defs;
diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd
deleted file mode 100644
index c3a0bca..0000000
--- a/projects/mips_sys/src/tb_mips_sys.vhd
+++ /dev/null
@@ -1,420 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: testbench for system test using Xilinx ML-402
-
--- Copyright (C) 2007 J. Ahrensfeld
-
--- This library is free software; you can redistribute it and/or
--- modify it under the terms of the GNU Lesser General Public
--- License as published by the Free Software Foundation; either
--- version 2.1 of the License, or (at your option) any later version.
-
--- This library is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--- Lesser General Public License for more details.
-
--- You should have received a copy of the GNU Lesser General Public
--- License along with this library; if not, write to the Free Software
--- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
--- For questions and ideas, please contact the author at jens@jayfield.org
-
------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; --  Imports the standard textio package.
-
-library work;
-use work.mips_types.all;
-use work.sdram_config.all;
-use work.sdram_types.all;
-use work.vga_types.all;
-
-ENTITY tb_mips_sys IS
-END tb_mips_sys;
-
-ARCHITECTURE behavior OF tb_mips_sys IS 
-
-	constant CLK_PERIOD			: time := 10 ns;
-	constant AC97_CLK_PERIOD	: time := 83 ns;
-	constant ETH_CLK_PERIOD		: time := 7.7 ns;
-	constant LOOP_BACK_EN		: std_logic := '1';
-	signal sys_rst_n_in : std_logic := '0';
-	signal sys_clk_in : std_logic := '1';
-	signal dip  : unsigned(7 downto 0) := (others => '0');
-	signal btn  : unsigned(4 downto 0) := (others => '0');
-	signal led : unsigned(8 downto 0);
-	signal sys_rx : std_logic := '1';
-	signal sys_tx : std_logic;
-	signal sys_rx1 : std_logic := '1';
-	signal sys_tx1 : std_logic;
-	signal sys_rx2 : std_logic := '1';
-	signal sys_tx2 : std_logic;
-	
-	signal sys_lcd_d			: unsigned(3 downto 0);
-	signal sys_lcd_e			: std_logic;
-	signal sys_lcd_rs			: std_logic;
-	signal sys_lcd_rw			: std_logic;
-
-	signal refresh        : boolean:= true;
-
-	signal sys_sdr_clk_p		: std_logic;    -- ddr_sdram_clock
-	signal sys_sdr_clk_n		: std_logic;    -- /ddr_sdram_clock
-	signal sys_sdr_cke_q		: std_logic;    -- clock enable
-	signal sys_sdr_cs_qn		: std_logic;    -- /chip select
-	signal sys_sdr_ras_qn		: std_logic;    -- /ras
-	signal sys_sdr_cas_qn		: std_logic;    -- /cas
-	signal sys_sdr_we_qn		: std_logic;    -- /write enable
-	signal sys_sdr_dm_q			: unsigned(DDR_DM_WIDTH-1 downto 0);     -- data mask bits, set to "00"
-	signal sys_sdr_dqs_q		: unsigned(DDR_DQS_WIDTH-1 downto 0);    -- data strobe, only for write
-	signal sys_sdr_ba_q			: unsigned(DDR_BANK_WIDTH-1 downto 0);   -- bank select
-	signal sys_sdr_a_q			: unsigned(DDR_ADDR_WIDTH-1 downto 0);   -- address bus 
-	signal sys_sdr_data			: unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
-
-	signal sys_error			: unsigned(1 downto 0); -- indicates DCM Errors
-	signal sys_sdr_clk_fb		: std_logic;
-
-	signal sys_usb_d			: unsigned(15 downto 0) := (others => '0');
-	signal sys_usb_a			: unsigned(1 downto 0);
-	signal sys_usb_csn			: std_logic;
-	signal sys_usb_wrn			: std_logic;
-	signal sys_usb_rdn			: std_logic;
-	signal sys_usb_rstn			: std_logic;
-	signal sys_usb_int			: std_logic := '0';
-	
-	signal sys_flash_ssram_d	: word_t;
-	signal sys_flash_ssram_a	: unsigned(24 downto 0);
-	signal sys_flash_ssram_we_n	: std_logic;
-	signal sys_flash_ssram_oe_n	: std_logic;
-
-	signal sys_flash_ce			: std_logic;
-	signal sys_flash_ac97_rstn	: std_logic;
-	signal sys_flash_byten		: std_logic;
-
-	signal sys_ssram_clk_fb		: std_logic;
-	signal sys_ssram_clk		: std_logic;
-	signal sys_ssram_cke_n		: std_logic;
-	signal sys_ssram_ce_n		: std_logic;
-	signal sys_ssram_bw_n		: unsigned(3 downto 0);
-	signal sys_ssram_dp			: unsigned(3 downto 0);
-	signal sys_ssram_adv		: std_logic;
-	signal sys_ssram_mode		: std_logic;
-	signal sys_ssram_zz			: std_logic;
-
-	SIGNAL sys_ac97_bit_clk		:  std_logic := '0';
-	SIGNAL sys_ac97_sdata_out	:  std_logic;
-	SIGNAL sys_ac97_ssync		:  std_logic;
-	SIGNAL sys_ac97_sdata_in	:  std_logic;
-
-	SIGNAL sys_ps2_clk			:  std_logic := 'H';
-	SIGNAL sys_ps2_data			:  std_logic := 'H';
-
-	SIGNAL sys_phy_rstn			:  std_logic;
-	SIGNAL sys_phy_mdc			:  std_logic;
-	SIGNAL sys_phy_mdio			:  std_logic := 'H';
-	SIGNAL sys_phy_int			:  std_logic := '0';
-
-	SIGNAL sys_phy_rx_clk		: STD_LOGIC := '0';
-	SIGNAL sys_phy_rx_dv		: STD_LOGIC	:= '0';
-	SIGNAL sys_phy_rx_er		: STD_LOGIC := '0';
-	SIGNAL sys_phy_rx			: unsigned(7 downto 0) := (others => '0');
-	SIGNAL sys_phy_tx_clk		: STD_LOGIC := '0';
-	SIGNAL sys_phy_tx_en		: STD_LOGIC;
-	SIGNAL sys_phy_tx_er		: STD_LOGIC;
-	SIGNAL sys_phy_tx			: unsigned(7 downto 0);
-	SIGNAL sys_phy_gtx_clk		: STD_LOGIC;
-	SIGNAL sys_phy_crs			: STD_LOGIC := '0';
-	SIGNAL sys_phy_col			: STD_LOGIC := '0';
-
-	signal flash_reg			: word_t;
-	signal eth_tx_reg			: unsigned(7 downto 0);
-	
-	type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
-	signal flash_data : flash_data_t;
-
-	signal	ac_frame_reg		: unsigned(255 downto 0) := (others => '0');
-	signal	ac_left				: unsigned(17 downto 0) := X"0000" & "00";
-	signal	ac_right			: unsigned(17 downto 0) := X"0000" & "01";
-	signal  ac_synced			:  std_logic;
-	
-BEGIN
-
-uut: entity work.mips_sys
-	GENERIC MAP
-	(
-		sys_freq_in			=> 100.000,
-		cpu_freq			=> 100.000,
-		sdram_phaseshift	=> 0,
-		tsvga				=> ts_vga_800_600_72
-	)
-	PORT MAP
-	(
-		sys_rst_n_in			=> sys_rst_n_in,
-		sys_clk_in				=> sys_clk_in,
-		sys_btn					=> btn,
-		sys_dip					=> dip,
-		sys_led					=> led,
-
-		sys_uart0_rx			=> sys_rx,
-		sys_uart0_tx			=> sys_tx,
-		sys_uart1_rx			=> sys_rx1,
-		sys_uart1_tx			=> sys_tx1,
-		sys_uart2_rx			=> sys_rx2,
-		sys_uart2_tx			=> sys_tx2,
-
-		sys_lcd_d				=> sys_lcd_d,
-		sys_lcd_e				=> sys_lcd_e,
-		sys_lcd_rs				=> sys_lcd_rs,
-		sys_lcd_rw				=> sys_lcd_rw,
-
-		sys_sdr_clk_p			=> sys_sdr_clk_p,
-		sys_sdr_clk_n			=> sys_sdr_clk_n,
-		sys_sdr_cke_q			=> sys_sdr_cke_q,
-		sys_sdr_clk_fb			=> sys_sdr_clk_fb,
-		sys_sdr_cs_qn			=> sys_sdr_cs_qn,
-		sys_sdr_ras_qn			=> sys_sdr_ras_qn,
-		sys_sdr_cas_qn			=> sys_sdr_cas_qn,
-		sys_sdr_we_qn			=> sys_sdr_we_qn,
-		sys_sdr_dm_q			=> sys_sdr_dm_q,
-		sys_sdr_dqs_q			=> sys_sdr_dqs_q,
-		sys_sdr_ba_q			=> sys_sdr_ba_q,
-		sys_sdr_a_q				=> sys_sdr_a_q,
-		sys_sdr_data			=> sys_sdr_data,
-
-		sys_usb_d				=> sys_usb_d,
-		sys_usb_a				=> sys_usb_a,
-		sys_usb_csn				=> sys_usb_csn,
-		sys_usb_wrn				=> sys_usb_wrn,
-		sys_usb_rdn				=> sys_usb_rdn,
-		sys_usb_rstn			=> sys_usb_rstn,
-		sys_usb_int				=> sys_usb_int,
-
-		sys_flash_ssram_d		=> sys_flash_ssram_d,
-		sys_flash_ssram_a		=> sys_flash_ssram_a,
-		sys_flash_ssram_we_n	=> sys_flash_ssram_we_n,
-		sys_flash_ssram_oe_n	=> sys_flash_ssram_oe_n,
-		sys_flash_ce			=> sys_flash_ce,
-		sys_flash_ac97_rstn		=> sys_flash_ac97_rstn,
-		sys_flash_byten			=> sys_flash_byten,
-
-		sys_ssram_clk_fb		=> sys_ssram_clk_fb,
-		sys_ssram_clk			=> sys_ssram_clk,
-		sys_ssram_cke_n			=> sys_ssram_cke_n,
-		sys_ssram_ce_n			=> sys_ssram_ce_n,
-		sys_ssram_bw_n			=> sys_ssram_bw_n,
-		sys_ssram_dp			=> sys_ssram_dp,
-		sys_ssram_adv			=> sys_ssram_adv,
-		sys_ssram_mode			=> sys_ssram_mode,
-		sys_ssram_zz			=> sys_ssram_zz,
-
-		sys_ac97_bit_clk		=> sys_ac97_bit_clk,
-		sys_ac97_sdata_out		=> sys_ac97_sdata_out,
-		sys_ac97_ssync			=> sys_ac97_ssync,
-		sys_ac97_sdata_in		=> sys_ac97_sdata_in,
-
-		sys_ps2_clk				=> sys_ps2_clk,
-		sys_ps2_data			=> sys_ps2_data,
-		
-		sys_phy_rstn			=> sys_phy_rstn,
-		sys_phy_mdc				=> sys_phy_mdc,
-		sys_phy_mdio			=> sys_phy_mdio,
-		sys_phy_int				=> sys_phy_int,
-
-		sys_phy_rx_clk			=> sys_phy_rx_clk,
-		sys_phy_rx_dv			=> sys_phy_rx_dv,
-		sys_phy_rx_er			=> sys_phy_rx_er,
-		sys_phy_rx				=> sys_phy_rx,
-		sys_phy_tx_clk			=> sys_phy_tx_clk,
-		sys_phy_tx_en			=> sys_phy_tx_en,
-		sys_phy_tx_er			=> sys_phy_tx_er,
-		sys_phy_tx				=> sys_phy_tx,
-		sys_phy_gtx_clk			=> sys_phy_gtx_clk,
-		sys_phy_crs				=> sys_phy_crs,
-		sys_phy_col				=> sys_phy_col,
-
-		sys_error 				=> sys_error
-	);
-
-	sys_phy_rx		<= sys_phy_tx when LOOP_BACK_EN = '1' else X"00";
-	sys_phy_rx_dv	<= sys_phy_tx_en when LOOP_BACK_EN = '1' else '0';
-	sys_phy_rx_er	<= sys_phy_tx_er when LOOP_BACK_EN = '1' else '0';
-	sys_phy_crs		<= '0';
-	sys_phy_col		<= '0';
-
-inst_ssram : entity work.cy7c1354
-    PORT MAP 
-    (
-		Dq		=> STD_LOGIC_VECTOR(sys_flash_ssram_d),   	-- Data I/O
-		Dpq		=> STD_LOGIC_VECTOR(sys_ssram_dp),   	-- Data I/O
-		Addr	=> STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)),   	-- Address
-		Mode	=> sys_ssram_mode, 	-- Burst Mode
-		Clk		=> sys_ssram_clk,      -- Clk
-		CEN_n	=> sys_ssram_cke_n,                                   -- CEN#
-		AdvLd_n	=> sys_ssram_adv,                                   -- Adv/Ld#
-		Bwa_n	=> sys_ssram_bw_n(0),                                   -- Bwa#
-		Bwb_n	=> sys_ssram_bw_n(1),                                   -- BWb#
-		Bwc_n	=> sys_ssram_bw_n(2),                                   -- Bwc#
-		Bwd_n	=> sys_ssram_bw_n(3),                                   -- BWd#
-		Rw_n	=> sys_flash_ssram_we_n,                                   -- RW#
-		Oe_n	=> sys_flash_ssram_oe_n,                                   -- OE#
-		Ce1_n	=> sys_ssram_ce_n,                                   -- CE1#
-		Ce2		=> '1',                                   -- CE2
-		Ce3_n	=> '0',                                   -- CE3#
-		Zz		=> sys_ssram_zz
-    );
-    
--- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_0 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(sys_sdr_data(15 downto 0)),
-         dqs   => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
-         addr  => std_logic_vector(sys_sdr_a_q),
-         ba    => std_logic_vector(sys_sdr_ba_q),
-         clk   => sys_sdr_clk_p,
-         clk_n => sys_sdr_clk_n,
-         cke   => sys_sdr_cke_q,
-         cs_n  => sys_sdr_cs_qn,
-         ras_n => sys_sdr_ras_qn,
-         cas_n => sys_sdr_cas_qn,
-         we_n  => sys_sdr_we_qn,
-         dm    => std_logic_vector(sys_sdr_dm_q(1 downto 0))
-         );
-
--- MICRON DDR SDRAM Simulation Model
-i_mt46v16m16_1 : entity work.mt46v16m16 
-      port map (
-         dq    => std_logic_vector(sys_sdr_data(31 downto 16)),
-         dqs   => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
-         addr  => std_logic_vector(sys_sdr_a_q),
-         ba    => std_logic_vector(sys_sdr_ba_q),
-         clk   => sys_sdr_clk_p,
-         clk_n => sys_sdr_clk_n,
-         cke   => sys_sdr_cke_q,
-         cs_n  => sys_sdr_cs_qn,
-         ras_n => sys_sdr_ras_qn,
-         cas_n => sys_sdr_cas_qn,
-         we_n  => sys_sdr_we_qn,
-         dm    => std_logic_vector(sys_sdr_dm_q(3 downto 2))
-         );
-
-	sys_sdr_clk_fb		<= sys_sdr_clk_p after 1300 ps;
-	sys_ssram_clk_fb	<= sys_ssram_clk after 0.5 ns;
-	
-	refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
-
-	sys_usb_d	<= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
-	
-CLK_GEN: process
-	begin
-		wait for CLK_PERIOD/2;
-		sys_clk_in <= not sys_clk_in;
-	end process;
-
-ETH_CLK_GEN: process
-	begin
-		wait for ETH_CLK_PERIOD/2;
-		sys_phy_rx_clk <= not sys_phy_rx_clk;
-		sys_phy_tx_clk <= not sys_phy_tx_clk;
-	end process;
-
-ETH_TX_REGISTER: 
-	PROCESS(sys_phy_tx_clk)
-	begin
-		if rising_edge(sys_phy_tx_clk) then
-			if (sys_phy_tx_en = '1') then
-				eth_tx_reg <= sys_phy_tx;
-			end if;
-		end if;
-	end process;
-
-	sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
-
-ac97_data_gen :
-	PROCESS(sys_ac97_bit_clk)
-	begin
-		if rising_edge(sys_ac97_bit_clk) then
-			ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
-			if sys_flash_ac97_rstn = '0' then
-				ac_synced	<= '0';
-			elsif sys_ac97_ssync = '1' then
-				if ac_synced = '0' then
-					ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
-					ac_left <= ac_left + 2;
-					ac_right <= ac_right + 2;
-					ac_synced	<= '1';
-				end if;	
-			else	
-				ac_synced	<= '0';
-			end if;
-		end if;	
-	END PROCESS;
-
-ac97_clk_gen : PROCESS
-	begin
-		if (sys_flash_ac97_rstn = '0') then
-			sys_ac97_bit_clk <= '0';
-			wait until sys_flash_ac97_rstn = '1';
-			wait for 150 us;
-		end if;	
-		wait for AC97_CLK_PERIOD/2;
-		sys_ac97_bit_clk <= not sys_ac97_bit_clk;
-	END PROCESS;
-
-FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
-	type file_t is file of integer;
-	file load_flash : file_t open read_mode is "blittertest_tb.elf.flash.bin";
-	variable instr : integer;
-	variable index : natural;
-	variable temp : signed(31 downto 0);
-	begin
-		if sys_rst_n_in = '0' then
-			index := 0;
-			while not endfile(load_flash) loop
-				read(load_flash, instr);
-				temp	:= to_signed(instr, word_t'length);
-				flash_data(index) <= unsigned(temp);
-				index := index + 1;
-			end loop;
-		else
-	 		sys_flash_ssram_d <= (others => 'Z') after 10 ns;
-			if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
-				index := to_integer(sys_flash_ssram_a(24 downto 1));
-				sys_flash_ssram_d <= flash_data(index) after 10 ns;
-			end if;	
-		end if;	
-	end process;
-
-FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
-	begin
-		if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
-			flash_reg <= sys_flash_ssram_d;
-		end if;
-	end process;
-		
-STIMULUS: process
-
-	begin
-
-		dip(7) <= '1';			-- EB
-		btn(0) <= '1';
-		btn(2) <= '1';
-		wait for 3*CLK_PERIOD;
-		sys_rst_n_in <= '1';
-		btn(0) <= '0';
-		btn(2) <= '0';
-		wait for 20000000*CLK_PERIOD;
-		
-		loop
-		wait for 251*CLK_PERIOD;
-		btn(4)		<= '1';			
-		wait for 311*CLK_PERIOD;
-		btn(4)		<= '0';			
-		end loop;
-		wait; 
-	
-	end process;
-	
-END;
diff --git a/projects/mips_sys/tools/insrom.rb b/projects/mips_sys/tools/insrom.rb
deleted file mode 100644
index fdbf1ed..0000000
--- a/projects/mips_sys/tools/insrom.rb
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/env ruby
-
-# ----------------------------------------------------------------------
-# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-# This file: Insertion of code fragments into templates
-#
-# Copyright (C) 2008 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-arg = $*
-rom_filename = arg[0].to_s
-tpl_filename = arg[1].to_s
-
-subst_pattern = "ROM_INSERT_HERE"
-
-# --------------------------------------------------------
-# Open file
-# --------------------------------------------------------
-romfile = File.open(rom_filename, "r")
-tplfile = File.open(tpl_filename, "r")
-re = Regexp.new(subst_pattern)
-
-while (line = tplfile.gets)
-	puts line
-	line.scan(re).each do |word|
-		romfile.each do |raw_line|
-			puts raw_line
-		end	
-	end
-end
diff --git a/projects/mips_sys/tools/irom.vhd.tpl b/projects/mips_sys/tools/irom.vhd.tpl
deleted file mode 100644
index 5ffd6d7..0000000
--- a/projects/mips_sys/tools/irom.vhd.tpl
+++ /dev/null
@@ -1,29 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
--- ROM_INSERT_HERE
-
diff --git a/projects/mips_sys/tools/irom_ld.vhd.tpl b/projects/mips_sys/tools/irom_ld.vhd.tpl
deleted file mode 100644
index 3bd3afb..0000000
--- a/projects/mips_sys/tools/irom_ld.vhd.tpl
+++ /dev/null
@@ -1,147 +0,0 @@
--------------------------------------------------------------------------
--- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
--- This file: loadable ROM
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
-
-ENTITY irom IS
-	Port (
-		clk			: in  STD_LOGIC;
-		addr		: in  inst_addr_t;
-		dout		: out inst_t
-	);
-	
-END irom;
-
-ARCHITECTURE loadable OF irom IS 
-
-	-- JASM_ROM_INSERT_HERE
-
-	signal jtag_ld_clk		: STD_LOGIC;
-	signal jtag_ld_we		: STD_LOGIC;
-	signal jtag_ld_addr		: unsigned (15 downto 0);
-	signal jtag_ld_dout		: unsigned (31 downto 0);
-	signal jtag_ld_din		: unsigned (31 downto 0);
-	signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
-	signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
-	signal user_regi, user_rego : unsigned (47 downto 0);
-	constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
-
-begin
-
---------------------------------------------------------------------------
--- Virtex-4: JTAG Loader
---------------------------------------------------------------------------
-	i00_BUFG : BUFG
-	port map
-	(
-		O => bs_clk1,
-        I => bs_clk0
-	);
-	
-	i01_BUFG : BUFG
-	port map
-	(
-		O => bs_update1,
-        I => bs_update0
-	);
-
-	BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 
-	generic map
-	(
-		JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
-	)
-	port map 
-	(
-		CAPTURE => bs_capture, -- CAPTURE output from TAP controller
-		DRCK => bs_clk0,       -- Data register output for USER functions
-		RESET => bs_rst,       -- Reset output from TAP controller
-		SEL => bs_sel,         -- USER active output
-		SHIFT => bs_shift,     -- SHIFT output from TAP controller
-		TDI => bs_tdi,        -- TDI output from TAP controller
-		UPDATE => bs_update0,   -- UPDATE output from TAP controller
-		TDO => bs_tdo         -- Data input for USER function
-	);
-
-	jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
-	jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
-	jtag_ld_clk <= bs_update1;
-	jtag_ld_we <= bs_sel;
-	
-sipo:
-	process (bs_rst, bs_clk1, bs_tdi, bs_shift)
-	begin
-		if bs_rst = '1' then
-			user_regi <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
-			end if;
-		end if;
-	end process;	
-
-piso:
-	process (bs_rst, bs_clk1, bs_shift, user_rego)
-	begin
-		bs_tdo <= user_rego(0);
-		if bs_rst = '1' then
-			user_rego <= (others => '0');
-		elsif rising_edge(bs_clk1) then
-			if bs_shift = '1' then
-				user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
-			else
-				user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;	
---				user_rego <= id;	
-			end if;
-		end if;
-	end process;	
-	
-PROM_WRITE: 
-	process(jtag_ld_clk, jtag_ld_we)
-	begin
-		if rising_edge(jtag_ld_clk) then
-			if jtag_ld_we = '1' then
-				imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
-			else	
-				jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
-			end if;
-		end if;	
-	end process;
-
---------------------------------------------------------------------------
--- ROM Read/Write
---------------------------------------------------------------------------
-PROM_READ: 
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			dout <= imem_rom(to_integer(addr));
-		end if;
-	end process;
-
---------------------------------------------------------------------------
-end loadable;
diff --git a/projects/mips_sys/tools/make b/projects/mips_sys/tools/make
deleted file mode 100644
index e7f598f..0000000
--- a/projects/mips_sys/tools/make
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/bin/sh
-
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: rom-file generation for cpu_core
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-TARGET=$2
-DSTDIR=$1
-
-JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
-
-$JASM_HOME/jasm.rb $TARGET.jsm
-
-irom_tcl_snippet="$TARGET.irom.tcl.snip"
-irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
-irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
-xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
-xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
-xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
-
-$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
-$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
-
-$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
-$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
-
-cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
-cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
-$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
-
-rm -f *.snip
diff --git a/projects/mips_sys/tools/rom.tcl.tpl b/projects/mips_sys/tools/rom.tcl.tpl
deleted file mode 100644
index 9f5c0dc..0000000
--- a/projects/mips_sys/tools/rom.tcl.tpl
+++ /dev/null
@@ -1,61 +0,0 @@
-# ----------------------------------------------------------------------
-# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
-# This file: The ROM file for upload to target over JTAG 
-#
-# Copyright (C) 2007 J. Ahrensfeld
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program.  If not, see <http://www.gnu.org/licenses/>.
-# 
-# For questions and ideas, please contact the author at jens@jayfield.org
-#
-# ---------------------------------------------------------------------
-
-# ---------------------------------------------------------------------
-# For Chipscope 9.1
-# ---------------------------------------------------------------------
-# Source JTAG/TCL frame work
-cd $env(CHIPSCOPE)\\bin\\nt
-source csejtag.tcl
-
-namespace import ::chipscope::*
-
-# Platform USB Cable
-set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
-# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
-
-# Create session
-set handle [::chipscope::csejtag_session create 0]
-
-# Open JTAG and lock
-set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
-set lock_result [::chipscope::csejtag_target lock $handle 1000]
-
-set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
-
-# Get Device ID
-set devtype "Virtex-4SX"
-set devid 2
-set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
-set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
-
-set CSE_OP $CSEJTAG_SHIFT_READWRITE
-set CSE_ES $CSEJTAG_RUN_TEST_IDLE
-
-# Write Program
-# JASM_ROM_INSERT_HERE
-
-::chipscope::csejtag_target unlock $handle
-::chipscope::csejtag_target close $handle
-::chipscope::csejtag_session destroy $handle
-exit
diff --git a/projects/mips_sys/tools/src/flashgen.c b/projects/mips_sys/tools/src/flashgen.c
deleted file mode 100644
index 4b75814..0000000
--- a/projects/mips_sys/tools/src/flashgen.c
+++ /dev/null
@@ -1,117 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define INT8    char
-#define INT16   short
-#define INT32   long
-#define UINT8   unsigned char
-#define UINT16  unsigned short
-#define UINT32  unsigned long
-#define INT     int
-#define UINT    unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define SDRAM_BASE			0x40000000
-#define	FLASH_OFFSET		0x00000000
-
-// --------------------------------------------------------------
-typedef struct _sflash_img_hdr_t
-{
-	UINT8 magic[4];
-	UINT32 target_addr;
-	UINT32 img_offset;
-	UINT32 img_size;
-	UINT32 hdr_next;
-	UINT8 img_name[128];
-	UINT8 res[108];
-
-} flash_img_hdr_t;
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-// --------------------------------------------------------------
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_flash[1024];
-	char name_prj[1024];
-	char *pBuf;
-	flash_img_hdr_t img_hdr = {0};
-
-	FILE *pFile;
-	int filesize;
-	long start, end;
-	int i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: flashgen <input file>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	pFile = fopen(pFilenameIn, "rb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_flash, "%s.flash.bin", name_prj);
-
-	// determine filesize
-	fseek(pFile, 0, SEEK_SET);
-	start = ftell(pFile);
-	fseek(pFile, 0, SEEK_END);
-	end = ftell(pFile);
-	fseek(pFile, 0, SEEK_SET);
-	filesize = (end-start);
-
-	pBuf = (char*)malloc(filesize);
-	fread(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	pFile = fopen(name_flash, "wb");
-	if (!pFile)
-	{
-		fprintf(stderr, "Error opening file %s\n", name_flash);
-		return 1;
-	}
-
-	img_hdr.magic[0] = 'J';
-	img_hdr.magic[1] = 'F';
-	img_hdr.magic[2] = 'I';
-	img_hdr.magic[3] = '1';
-	img_hdr.target_addr = SDRAM_BASE;
-	img_hdr.img_size = filesize;
-	img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
-	img_hdr.hdr_next = FLASH_OFFSET;
-
-	fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
-	fwrite(pBuf, 1, filesize, pFile);
-
-	fclose(pFile);
-
-	return 0;
-}
-
diff --git a/projects/mips_sys/tools/src/ramgen.c b/projects/mips_sys/tools/src/ramgen.c
deleted file mode 100644
index 8f61118..0000000
--- a/projects/mips_sys/tools/src/ramgen.c
+++ /dev/null
@@ -1,385 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"ram"
-#define JTAG_ADDR_WIDTH		16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\twe\t\t: in  unsigned(%d downto 0);\n", nbits_data/8-1);
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdin\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 2\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom_tcl[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	if (argc == 3)
-		nbits_addr = atoi(argv[2]);
-
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-//	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-
diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c
deleted file mode 100644
index a59e705..0000000
--- a/projects/mips_sys/tools/src/romgen.c
+++ /dev/null
@@ -1,368 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <math.h>
-
-#define ARCH_NAME			"data"
-#define ENT_NAME			"rom"
-#define JTAG_ADDR_WIDTH		16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
-	int i, size;
-
-	size = strlen(pSrc);
-
-	while(pSrc[size] != '.')
-		size--;
-
-	for (i=0; i < size; i++)
-		pDst[i] = pSrc[i];
-
-	pDst[i] = 0;
-
-}
-
-int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
-	return 0;
-}
-
-int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, filesize, romsize;
-
-	char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n        I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n        I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0,       -- Data register output for USER functions\n\t\tRESET => bs_rst,       -- Reset output from TAP controller\n\t\tSEL => bs_sel,         -- USER active output\n\t\tSHIFT => bs_shift,     -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi,        -- TDI output from TAP controller\n\t\tUPDATE => bs_update0,   -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo         -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "LIBRARY IEEE;\n");
-	fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
-	fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "library UNISIM;\n");
-	fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
-	fprintf(pFileOut, "\tPort\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\t\tclk\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\tce\t\t: in  STD_LOGIC;\n");
-	fprintf(pFileOut, "\t\taddr\t\t: in  unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "END %s;\n", ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-
-	fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
-	fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
-	fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
-	fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
-	fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
-	fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
-	fprintf(pFileOut, "\t(\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	word = 0;
-	for (; i < romsize; i += sizeof(int))
-	{
-		fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
-		if (i < (romsize-sizeof(int)))
-			fprintf(pFileOut, ", -- %8.8X\n", i);
-		else
-			fprintf(pFileOut, "  -- %8.8X\n", i);
-	}
-	fprintf(pFileOut, "\t);\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "begin\n", ARCH_NAME);
-
-	fprintf(pFileOut, "\n");
-	fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(clk)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
-	fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "\n");
-	fputs(tpl, pFileOut);
-
-	fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
-	fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
-	fprintf(pFileOut, "\tbegin\n");
-	fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
-	fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
-	fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\telse\n");
-	fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
-	fprintf(pFileOut, "\t\t\tend if;\n");
-	fprintf(pFileOut, "\t\tend if;\n");
-	fprintf(pFileOut, "\tend process;\n");
-	fprintf(pFileOut, "\n");
-
-	fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-	return 0;
-}
-
-int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
-	FILE *pFileIn, *pFileOut;
-	long start, end;
-	int i, word, word_addr, filesize, romsize;
-	char binstr_addr[33];
-	char binstr_data[33];
-
-	char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
-	pFileIn = fopen(pFilenameIn, "rb");
-	if (!pFileIn)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameIn);
-		return 1;
-	}
-
-	pFileOut = fopen(pFilenameOut, "wb");
-	if (!pFileOut)
-	{
-		fprintf(stderr, "Error opening file %s\n", pFilenameOut);
-		return 1;
-	}
-
-	fseek(pFileIn, 0, SEEK_SET);
-	start = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_END);
-	end = ftell(pFileIn);
-	fseek(pFileIn, 0, SEEK_SET);
-
-	filesize = (end-start);
-	romsize = (int)pow(2, nbits_addr+2);
-
-	// -------------------------------------------------------------------------
-	// Header
-
-	// -------------------------------------------------------------------------
-	fputs(tpl, pFileOut);
-
-	// -------------------------------------------------------------------------
-	// ROM part
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
-	fprintf(pFileOut, "# ---------------------------------------------------------------\n");
-	fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
-	fprintf(pFileOut, "# User 1\n");
-	fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
-
-	word_addr = 0;
-	for (i=0; i < filesize; i += sizeof(int))
-	{
-		fread(&word, 1, sizeof(int), pFileIn);
-		fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
-		word_addr++;
-	}
-	fprintf(pFileOut, "\n");
-
-	// -------------------------------------------------------------------------
-	// Trailer
-	// -------------------------------------------------------------------------
-	fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
-	fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
-	fprintf(pFileOut, "exit\n");
-
-	return 0;
-}
-
-int main(int argc, char *argv[])
-{
-	char *pFilenameIn;
-	char name_prj[1024];
-	char name_rom[1024];
-	char name_rom_v4ld[1024];
-	char name_rom_tcl[1024];
-
-	FILE *pFileIn;
-	int filesize, romsize, nbits_addr, nbits_data;
-	long start, end;
-	int word, i;
-
-	if (argc < 2)
-	{
-		fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
-		return 1;
-	}
-
-	pFilenameIn = argv[1];
-	if (argc == 3)
-		nbits_addr = atoi(argv[2]);
-
-
-	basename(pFilenameIn, name_prj);
-	sprintf(name_rom, "%s.vhd", name_prj);
-	sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
-	sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
-	SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-	SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
-	return 0;
-}
-