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git-svn-id: http://moon:8086/svn/vhdl/trunk@46 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-10 21:33:10 +00:00
parent 25a276d19b
commit b6309838f1
2 changed files with 17 additions and 3 deletions
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projects/mips_sys/src/mips_sys.vhd
+5 -1
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@@ -119,6 +119,7 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT mips_top
Port
(
debug : out unsigned(1 downto 0);
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC;
@@ -326,6 +327,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal gpi0 : unsigned(31 downto 0);
signal gpi1 : unsigned(31 downto 0);
signal debug : unsigned(1 downto 0);
-- DDR SDRAM
constant BURST_LEN : natural := 2;
@@ -343,7 +346,7 @@ BEGIN
gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0);
sys_error <= gpo0(31 downto 30);
sys_error <= debug;
rst_in <= not sys_rst_n_in;
rst <= not locked;
sys_usb_rstn <= not gpo1(0);
@@ -459,6 +462,7 @@ urom_ack_register:
inst_mips_top: mips_top
PORT MAP
(
debug => debug,
RST_I => rst,
CLK_I => clk,
ACK_I => ACK_I,