From b5e1d45b206fca9102e2b2260c4aa591eed7de82 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 1 May 2009 19:26:43 +0000 Subject: [PATCH] - added test color register base + 0x80 - control signals derived from register file are noe registered for better timing - mem_offset updated from vga_mem_offset wehn new frame begins Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@459 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/vga_frontend64.vhd | 35 +++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd index 1e2b564..5276869 100644 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend64.vhd @@ -117,10 +117,12 @@ architecture Behavioral of vga_frontend64 is signal cg_ascii_data_we : std_logic; signal cg_ascii_posy_we : std_logic; signal cg_ascii_posx_we : std_logic; + signal cg_color : color_t; -- Bus master signals constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; + signal mem_offset : unsigned(31 downto 0); signal vga_mem_offset : unsigned(31 downto 0); signal vga_scan_rdy : std_logic; signal vga_master_en : std_logic; @@ -188,7 +190,7 @@ inst_vga_backend : entity work.vga_backend color_en(0) <= not fifo_empty; color_en(1) <= cg_draw; color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32)); - color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque + color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque color_op <= op_over; vga_scan_rdy <= stat_hready and stat_vready; @@ -330,14 +332,16 @@ pixel_counter: if rising_edge(CLK_I) then if pixel_cnt_rst = '1' then pixel_cnt := 0; + mem_offset <= vga_mem_offset; elsif request_cnt_en = '1' and SRDY_I = '1' then if pixel_cnt /= MAX_REQUEST_CNT/2-1 then pixel_cnt := pixel_cnt + 1; else pixel_cnt := 0; + mem_offset <= vga_mem_offset; end if; end if; - ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cnt, 29) & "000"); + ADDR_O <= mem_offset + (to_unsigned(pixel_cnt, 29) & "000"); end if; end process; @@ -375,12 +379,6 @@ inst_char_gen : entity work.char_gen char_draw_en => cg_draw ); SRDY_O <= CYC_I; -- and cg_rdy; - cg_ascii_data <= SDAT_I(7 downto 0); - cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I; - cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I; - cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I; - cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I; - cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I; SDAT_O <= X"0000000" & "000" & cg_rdy; scan_rdy <= stat_hready and stat_vready; cg_en <= stat_scan; @@ -401,11 +399,30 @@ data_valid_register: process(CLK_I) begin if rising_edge(CLK_I) then + cg_ascii_data_we <= '0'; + cg_ascii_posy_we <= '0'; + cg_ascii_posx_we <= '0'; + cg_clr_screen <= '0'; + cg_clr_line <= '0'; if RST_I = '1' then vga_master_en <= '0'; vga_mem_offset <= X"40000000"; + cg_color <= (X"FF", X"FF", X"FF", X"FF"); elsif (CYC_I and STB_I and WE_I) = '1' then - if ADDR_I(8) = '1' then + if ADDR_I(2) = '1' then + cg_ascii_data_we <= '1'; + cg_ascii_data <= SDAT_I(7 downto 0); + elsif ADDR_I(3) = '1' then + cg_ascii_posy_we <= '1'; + elsif ADDR_I(4) = '1' then + cg_ascii_posx_we <= '1'; + elsif ADDR_I(5) = '1' then + cg_clr_screen <= '1'; + elsif ADDR_I(6) = '1' then + cg_clr_line <= '1'; + elsif ADDR_I(7) = '1' then + cg_color <= to_color_t(SDAT_I(31 downto 0)); + elsif ADDR_I(8) = '1' then vga_master_en <= SDAT_I(0); elsif ADDR_I(9) = '1' then vga_mem_offset <= SDAT_I(31 downto 2) & "00";