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Cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@49 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-10-12 11:01:40 +00:00
parent 14489d80e9
commit b47d55d61f
1 changed files with 25 additions and 27 deletions
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lib/CPUs/MIPS/src/core/dcache.vhd
+25 -27
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@@ -24,8 +24,8 @@ ENTITY dcache IS
CYC_O : out STD_LOGIC; CYC_O : out STD_LOGIC;
en : in STD_LOGIC; en : in STD_LOGIC;
cpu_en : in STD_LOGIC; cpu_en : in STD_LOGIC;
cpu_r_wn : in STD_LOGIC; cpu_we : in STD_LOGIC;
cpu_we : in unsigned(3 downto 0); cpu_be : in unsigned(3 downto 0);
cpu_addr : in word_t; cpu_addr : in word_t;
cpu_din : in word_t; cpu_din : in word_t;
cpu_dout : out word_t; cpu_dout : out word_t;
@@ -134,8 +134,7 @@ END COMPONENT;
signal s, sn : cache_state_t; signal s, sn : cache_state_t;
signal cache_busy : std_logic; signal cache_busy : std_logic;
signal cache_read_miss : std_logic; signal cache_miss : std_logic;
signal cache_write_miss : std_logic;
signal tag_match : std_logic; signal tag_match : std_logic;
signal word_index_reg : unsigned(word_index_width-1 downto 0); signal word_index_reg : unsigned(word_index_width-1 downto 0);
signal cache_index_reg : unsigned(cache_index_width-1 downto 0); signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
@@ -147,15 +146,16 @@ END COMPONENT;
signal cpu_dram_dout : word_t; signal cpu_dram_dout : word_t;
signal cpu_dram_din : word_t; signal cpu_dram_din : word_t;
signal cpu_data_reg : word_t; signal cpu_data_reg : word_t;
signal cpu_we_reg : unsigned(3 downto 0); signal cpu_be_reg : unsigned(3 downto 0);
signal ctrl_force_we : unsigned(3 downto 0); signal ctrl_force_be : unsigned(3 downto 0);
signal cpu_was_write : std_logic; signal cpu_we_reg : std_logic;
signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0); signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
signal ctrl_dram_din : word_t; signal ctrl_dram_din : word_t;
signal ctrl_dram_we : unsigned(3 downto 0); signal ctrl_dram_we : unsigned(3 downto 0);
signal cpu_dram_we : unsigned(3 downto 0); signal cpu_dram_we : unsigned(3 downto 0);
signal dram_en : std_logic; signal dram_en : std_logic;
signal cpu_was_en : std_logic; signal cpu_en2 : std_logic;
signal cpu_we2 : std_logic;
signal tram_addr_rd : unsigned(cache_index_width-1 downto 0); signal tram_addr_rd : unsigned(cache_index_width-1 downto 0);
signal tram_dout : tram_data_t; signal tram_dout : tram_data_t;
@@ -174,13 +174,12 @@ END COMPONENT;
signal cpu_reg_en : std_logic; signal cpu_reg_en : std_logic;
signal was_miss : std_logic; signal was_miss : std_logic;
signal data_write : std_logic; signal data_write : std_logic;
signal cpu_we2 : std_logic;
signal cpu_hit_we : std_logic; signal cpu_hit_we : std_logic;
signal instant_raw : std_logic; signal instant_raw : std_logic;
begin begin
cpu_hit_we <= cpu_we2 and not cache_write_miss; cpu_hit_we <= cpu_we2 and not cache_miss;
cpu_index_register: cpu_index_register:
process(CLK_I) process(CLK_I)
@@ -202,11 +201,11 @@ cpu_data_register:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if RST_I = '1' then if RST_I = '1' then
cpu_was_write <= '0'; cpu_we_reg <= '0';
elsif cpu_reg_en = '1' and en = '1' then elsif cpu_reg_en = '1' and en = '1' then
cpu_data_reg <= cpu_din; cpu_data_reg <= cpu_din;
cpu_be_reg <= cpu_be;
cpu_we_reg <= cpu_we; cpu_we_reg <= cpu_we;
cpu_was_write <= not cpu_r_wn;
end if; end if;
end if; end if;
end process; end process;
@@ -215,11 +214,11 @@ cpu_was_wr_register:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
cpu_was_en <= '0'; cpu_en2 <= '0';
cpu_we2 <= '0'; cpu_we2 <= '0';
if cpu_en = '1' and en = '1' then if cpu_en = '1' and en = '1' then
cpu_we2 <= not cpu_r_wn; cpu_we2 <= cpu_we;
cpu_was_en <= '1'; cpu_en2 <= '1';
cpu_dram_din <= cpu_din; cpu_dram_din <= cpu_din;
end if; end if;
end if; end if;
@@ -229,7 +228,7 @@ instant_raw_logic:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
instant_raw <= cpu_hit_we and cpu_en and en and cpu_r_wn; instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we;
end if; end if;
end process; end process;
@@ -291,8 +290,7 @@ cache_state_next:
cpu_dout <= cpu_dram_dout; cpu_dout <= cpu_dram_dout;
tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0';
cache_read_miss <= not (tag_match and cache_entry_out.valid) and not cpu_was_write; cache_miss <= not (tag_match and cache_entry_out.valid);
cache_write_miss <= not (tag_match and cache_entry_out.valid and cpu_was_write);
tram_din <= to_tram_data(cache_entry_in); tram_din <= to_tram_data(cache_entry_in);
tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
cache_entry_out <= to_dcache_entry(tram_dout); cache_entry_out <= to_dcache_entry(tram_dout);
@@ -300,11 +298,11 @@ cache_state_next:
ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
ctrl_dram_din <= DAT_I; ctrl_dram_din <= DAT_I;
ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_we; ctrl_dram_we <= (3 downto 0 => (data_write and ACK_I)) or ctrl_force_be;
cpu_dram_we <= cpu_we_reg when (cpu_hit_we = '1') else (others => '0'); cpu_dram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
cache_state: cache_state:
process(s, instant_raw, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, cpu_r_wn, SRDY_I, cpu_was_en, cpu_was_write, cpu_we_reg) process(s, instant_raw, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg, cpu_be_reg)
begin begin
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
@@ -324,7 +322,7 @@ cache_state:
cache_entry_in.tag <= tag_index_reg; cache_entry_in.tag <= tag_index_reg;
cache_entry_in.valid <= '0'; cache_entry_in.valid <= '0';
cache_entry_in.dirty <= '0'; cache_entry_in.dirty <= '0';
ctrl_force_we <= (others => '0'); ctrl_force_be <= (others => '0');
sn <= s; sn <= s;
case s is case s is
@@ -333,10 +331,10 @@ cache_state:
when ready => when ready =>
cache_busy <= '0'; cache_busy <= '0';
cpu_reg_en <= '1'; cpu_reg_en <= '1';
dram_en <= cpu_en or cpu_was_en; dram_en <= cpu_en or cpu_en2;
tram_re <= cpu_en; tram_re <= cpu_en;
if cpu_was_en = '1' then if cpu_en2 = '1' then
if cache_read_miss = '1' then if cache_miss = '1' and cpu_we_reg = '0' then
sn <= mem_request; sn <= mem_request;
cpu_reg_en <= '0'; cpu_reg_en <= '0';
cache_busy <= '1'; cache_busy <= '1';
@@ -387,7 +385,7 @@ cache_state:
tram_addr_wr <= cache_index_reg; tram_addr_wr <= cache_index_reg;
tram_we <= '1'; tram_we <= '1';
cache_entry_in.valid <= '1'; cache_entry_in.valid <= '1';
if cpu_was_write = '1' then if cpu_we_reg = '1' then
sn <= wr_cache; sn <= wr_cache;
else else
sn <= rd_cache; sn <= rd_cache;
@@ -401,7 +399,7 @@ cache_state:
when wr_cache => when wr_cache =>
tram_re <= '1'; tram_re <= '1';
ctrl_force_we <= cpu_we_reg; ctrl_force_be <= cpu_be_reg;
sn <= ready; sn <= ready;
when others => when others =>
sn <= ready; sn <= ready;