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Unified RAM memory content signals

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jens
2022-09-08 11:27:39 +02:00
parent 08e1a114c4
commit b21e3c580b
13 changed files with 62 additions and 62 deletions
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lib/rams/xilinx/src/dpram_2w2r2c_ra.vhd
+6 -6
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@@ -56,19 +56,19 @@ architecture Behavioral of dpram_2w2r2c_ra is
constant depth : integer := 2**addr_width;
signal addr_a_r : unsigned (addr_width-1 downto 0);
signal addr_b_r : unsigned (addr_width-1 downto 0);
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable memory_content : memory_type;
begin
dout_a <= RAM(to_integer(addr_a_r));
dout_b <= RAM(to_integer(addr_b_r));
dout_a <= memory_content(to_integer(addr_a_r));
dout_b <= memory_content(to_integer(addr_b_r));
process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
-- if re_a = '1' then
addr_a_r <= addr_a;
@@ -81,7 +81,7 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
-- if re_b = '1' then
addr_b_r <= addr_b;