jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Unified RAM memory content signals

Browse Source
This commit is contained in:
jens
2022-09-08 11:27:39 +02:00
parent 08e1a114c4
commit b21e3c580b
13 changed files with 62 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rams/sim/src/dpram_2w2r2c_ro.vhd
+6 -6
View File
@@ -54,8 +54,8 @@ end dpram_2w2r2c_ro;
architecture Behavioral of dpram_2w2r2c_ro is
constant depth : integer := 2**addr_width;
type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable RAM : RAMtype;
type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
shared variable memory_content : memory_type;
begin
@@ -63,10 +63,10 @@ process (clk_a)
begin
if clk_a'event and clk_a = '1' then
if we_a = '1' then
RAM(to_integer(addr_a)) := din_a;
memory_content(to_integer(addr_a)) := din_a;
end if;
if re_a = '1' then
dout_a <= RAM(to_integer(addr_a));
dout_a <= memory_content(to_integer(addr_a));
end if;
end if;
end process;
@@ -75,10 +75,10 @@ process (clk_b)
begin
if clk_b'event and clk_b = '1' then
if we_b = '1' then
RAM(to_integer(addr_b)) := din_b;
memory_content(to_integer(addr_b)) := din_b;
end if;
if re_b = '1' then
dout_b <= RAM(to_integer(addr_b));
dout_b <= memory_content(to_integer(addr_b));
end if;
end if;
end process;