From aef8406ae867594b819d9b6c2db7c0cb9c9412d1 Mon Sep 17 00:00:00 2001 From: jens Date: Sat, 10 Sep 2022 10:40:58 +0200 Subject: [PATCH] Improved templ --- lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ | 4 +-- lib/CPUs/MIPS/src/tb_mips_top.vhd | 30 +++++++++++------------ 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ b/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ index 832ae5a..786daae 100644 --- a/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ +++ b/lib/CPUs/MIPS/ghdl/tb_mips_top.wopt.templ @@ -59,8 +59,8 @@ $ version 1.1 /tb_mips_top/rx /tb_mips_top/tx /tb_mips_top/mem_area -/tb_mips_top/sram_data -/tb_mips_top/flash_data +/tb_mips_top/sram_memory_content +/tb_mips_top/flash_memory_content /tb_mips_top/uut/debug /tb_mips_top/uut/eb /tb_mips_top/uut/nmi diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd index 65b1d3c..54148f4 100644 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd @@ -118,8 +118,8 @@ ARCHITECTURE behavior OF tb_mips_top IS signal mem_area : mem_area_t; type word_array_t is array (natural range <>) of unsigned(31 downto 0); - signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); - signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); + signal sram_memory_content : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); + signal flash_memory_content : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); BEGIN @@ -361,16 +361,16 @@ SRAM_READ: if sram_oe_n = '0' then if sram_cs_n = '0' then if sram_be_n(0) = '0' then - sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns; + sram_d(7 downto 0) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns; end if; if sram_be_n(1) = '0' then - sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns; + sram_d(15 downto 8) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns; end if; if sram_be_n(2) = '0' then - sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns; + sram_d(23 downto 16) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns; end if; if sram_be_n(3) = '0' then - sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns; + sram_d(31 downto 24) <= sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns; end if; end if; end if; @@ -382,16 +382,16 @@ SRAM_WRITE: if rising_edge(sram_wr_n) then if sram_cs_n = '0' then if sram_be_n(0) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); + sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); end if; if sram_be_n(1) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); + sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); end if; if sram_be_n(2) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); + sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); end if; if sram_be_n(3) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); + sram_memory_content(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); end if; end if; end if; @@ -412,7 +412,7 @@ FLASH_READ: while not endfile(load_flash) loop read(load_flash, instr); temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); + flash_memory_content(index) <= unsigned(temp); index := index + 1; end loop; else @@ -421,16 +421,16 @@ FLASH_READ: if flash_oe_n = '0' then if flash_cs_n = '0' then if flash_be_n(0) = '0' then - flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after tpd; + flash_d(7 downto 0) <= flash_memory_content(index)(7 downto 0) after tpd; end if; if flash_be_n(1) = '0' then - flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after tpd; + flash_d(15 downto 8) <= flash_memory_content(index)(15 downto 8) after tpd; end if; if flash_be_n(2) = '0' then - flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after tpd; + flash_d(23 downto 16) <= flash_memory_content(index)(23 downto 16) after tpd; end if; if flash_be_n(3) = '0' then - flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after tpd; + flash_d(31 downto 24) <= flash_memory_content(index)(31 downto 24) after tpd; end if; end if; end if;