diff --git a/lib/misc/rom_sim.vhd b/lib/misc/rom_sim.vhd
index 98c0484..409a50c 100644
--- a/lib/misc/rom_sim.vhd
+++ b/lib/misc/rom_sim.vhd
@@ -14,6 +14,8 @@ END rom;
 
 ARCHITECTURE data OF rom IS
 
+	signal addr_r		: unsigned(31 downto 0);
+
 	subtype word_t is unsigned(31 downto 0);
 	type word_array_t is array (0 to 2047) of word_t;
 	constant word_array : word_array_t :=
@@ -2071,11 +2073,13 @@ ARCHITECTURE data OF rom IS
 
 begin
 
+	dout <= word_array(to_integer(addr_r(12 downto 2)));
+
 PROM_READ:
 	process(clk)
 	begin
 		if rising_edge(clk) and ce = '1' then
-			dout <= word_array(to_integer(addr(12 downto 2)));
+			addr_r	<= addr;
 		end if;
 	end process;
 
diff --git a/lib/misc/rom_wb.vhd b/lib/misc/rom_wb.vhd
index 9fa3715..41b25ec 100644
--- a/lib/misc/rom_wb.vhd
+++ b/lib/misc/rom_wb.vhd
@@ -8,6 +8,7 @@ ENTITY rom_wb IS
 		CLK_I		: in  STD_LOGIC;
 		RST_I		: in  STD_LOGIC;
 		CYC_I		: in  STD_LOGIC;
+		WE_I		: in  STD_LOGIC;
 		STB_I		: in  STD_LOGIC;
 		ACK_O		: out STD_LOGIC;
 		MRDY_I		: in  STD_LOGIC;
@@ -43,7 +44,7 @@ data_valid_register:
 			if RST_I = '1' then
 				ACK_O	<= '0';
 			else
-				ACK_O	<= data_en; -- and not WE_I;
+				ACK_O	<= data_en and not WE_I;
 			end if;
 		end if;
 	end process;