diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index d509dea..ad6eff1 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -35,6 +35,10 @@ END uart_wb;
 ARCHITECTURE rtl OF uart_wb IS
 
 	COMPONENT uart
+	Generic 
+	(
+		fifo_depth_bits	: integer
+	);
 	Port
 	(
 		clk			: in  STD_LOGIC;
@@ -71,6 +75,10 @@ begin
 	ctrl.baudrate	<= reg_uart_baud;
 	
 inst_uart : uart
+	GENERIC MAP 
+	(
+		fifo_depth_bits	=> fifo_depth_bits
+	)
 	PORT MAP
 	(
 		clk			=> CLK_I,