From aad1f852b54649d7ed0ab6307308179d67e0a25d Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 11 Mar 2010 11:36:10 +0000 Subject: [PATCH] - improved instant_raw logic. Less false alarms Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@769 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/dcache.vhd | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd index 55d6c76..e2c335d 100644 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ b/lib/CPUs/MIPS/src/core/dcache.vhd @@ -191,6 +191,7 @@ END COMPONENT; signal invalidate_req : std_logic; signal cpu_hit_we : std_logic; signal instant_raw : std_logic; + signal hit_cache_index : unsigned(cache_index_width-1 downto 0); alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); @@ -253,6 +254,9 @@ cpu_request_register: cpu_data_reg <= cpu_din; cpu_be_reg <= cpu_be; cpu_we_reg <= cpu_we; + if cpu_we = '1' then + hit_cache_index <= cpu_cache_index; + end if; end if; elsif cache_ack = '1' then cache_req <= '0'; @@ -266,7 +270,7 @@ instant_raw_logic: begin if rising_edge(CLK_I) then instant_raw <= '0'; - if cpu_word_index = fill_word_index then + if cpu_word_index = fill_word_index and cpu_cache_index = hit_cache_index then instant_raw <= cpu_hit_we and cpu_en and not cpu_we; end if; end if;