From aacb0c448b9809e870bb06c20a3e395b804f5af3 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 28 Oct 2009 23:25:03 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create tag 'JCPU_R4'. git-svn-id: http://moon:8086/svn/vhdl/tags/JCPU_R4@559 cc03376c-175c-47c8-b038-4cd826a8556b --- Common/sim/ModelSim SE .lnk | Bin 1441 -> 0 bytes Common/sim/compile_simprim.do | 8 - Common/sim/compile_unisim.do | 8 - Common/ucf/ml402.ucf | 675 --- lib/CPUs/MIPS/bsp/examples/Bessel.c | 87 - lib/CPUs/MIPS/bsp/examples/Makefile | 200 - .../MIPS/bsp/examples/bootloader/Makefile | 47 - .../MIPS/bsp/examples/bootloader/bootloader.c | 247 - .../bsp/examples/bootloader/bootloader.ld | 53 - .../bootloader/bootloader_with_flash.c | 391 -- .../MIPS/bsp/examples/bootloader/init_boot.S | 19 - .../bsp/examples/bootloader/kernel_boot.S | 46 - .../bsp/examples/bootloader/libsys_boot.c | 214 - .../bsp/examples/bootloader/libsys_boot.h | 54 - .../bsp/examples/bootloader/startup_boot.S | 43 - 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b/Common/sim/ModelSim SE .lnk deleted file mode 100644 index ecadd026618ef9dc683b411377dc4b08753d4bac..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1441 zcmds1YeLW4jesvk-rQE8%Gq#se#^M0FO7rOlES7)5}ocCOwbKdj4@5%sZ z^f6q4ab-pEd2S8V1WLPnP_2OAk%^^D$bIM6NV1~WHJxXqfAH+Bsn{IzXATB z$J-S0`Ayz-wrEzfKQa5%4bg>P?IJ`RKkIwZuAC=@UJqGFFi)>{w<|N-tR9#SL%uS)2~vs1s~4IHuCrVjM6TWrqw5bv0g^8FI3{j(DW&{seZ@jNdb}{w~N#q<% zDF`1T8fVd89Yt+C((G&Xwx~4@S9HH=+`74RU^Yho=;+l;ZMBc@B&N?KoP2=wL!R#U QfAfo1y^8qTD1%YdufjzO<^TWy diff --git a/Common/sim/compile_simprim.do b/Common/sim/compile_simprim.do deleted file mode 100644 index 0d97d06..0000000 --- a/Common/sim/compile_simprim.do +++ /dev/null @@ -1,8 +0,0 @@ -vlib simprim - -set XILINX C:/Programme/Xilinx101/ISE - -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/Common/sim/compile_unisim.do b/Common/sim/compile_unisim.do deleted file mode 100644 index 6e91db1..0000000 --- a/Common/sim/compile_unisim.do +++ /dev/null @@ -1,8 +0,0 @@ -vlib unisim - -set XILINX C:/Programme/Xilinx101/ISE - -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd diff --git a/Common/ucf/ml402.ucf b/Common/ucf/ml402.ucf deleted file mode 100644 index 318e778..0000000 --- a/Common/ucf/ml402.ucf +++ /dev/null @@ -1,675 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -# Bus clock nets -NET "sys_clk" TNM_NET = "sys_clk"; -NET "tft_clk" TNM_NET = "tft_clk"; -NET sys_clk_in TNM_NET = "sys_clk_in"; -TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; - -NET sys_clk_in LOC = AE14; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET sys_rst_in LOC = D6; -NET sys_rst_in PULLUP; -NET sys_rst_in TIG; - -NET uart_RX LOC = W2; -NET uart_RX IOSTANDARD = LVCMOS33; -NET uart_RX TIG; -NET uart_TX LOC = W1; -NET uart_TX IOSTANDARD = LVCMOS33; -NET uart_TX TIG; - -NET ext_irq TIG; - -# Reset timing ignore - treat as async paths -NET sys_rst TIG; -NET opb_v20_0_OPB_Rst TIG; -NET lmb_v10_1_OPB_Rst TIG; -NET lmb_v10_0_OPB_Rst TIG; -NET opb_v20_0_Debug_SYS_Rst TIG; -NET Debug_Rst TIG; -NET plb_v34_0_PLB_Rst TIG; -NET dcm_locked TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2; -INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4; -INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1; - -INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0; -INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1; -INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2; - -INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31; -INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// - -# GPLED 0-3 -NET gpio<0> LOC = G5; #GPLED0 -NET gpio<1> LOC = G6; #GPLED1 -NET gpio<2> LOC = A11; #GPLED2 -NET gpio<3> LOC = A12; #GPLED3 -# North-East-South-West-Center LEDs -NET gpio<4> LOC = C6; # C LED -NET gpio<5> LOC = F9; # W LED -NET gpio<6> LOC = A5; # S LED -NET gpio<7> LOC = E10; # E LED -NET gpio<8> LOC = E2; # N LED -# North-East-South-West-Center Buttons -NET gpio<9> LOC = B6; # C Button -NET gpio<10> LOC = E9; # W Button -NET gpio<11> LOC = A6; # S Button -NET gpio<12> LOC = F10; # E Button -NET gpio<13> LOC = E7; # N Button -# Dip Switches 1-8 -NET gpio<14> LOC = U24; # DIP SW 8 -NET gpio<15> LOC = U25; # DIP SW 7 -NET gpio<16> LOC = V23; # DIP SW 6 -NET gpio<17> LOC = U23; # DIP SW 5 -NET gpio<18> LOC = U26; # DIP SW 4 -NET gpio<19> LOC = T26; # DIP SW 3 -NET gpio<20> LOC = R19; # DIP SW 2 -NET gpio<21> LOC = R20; # DIP SW 1 -NET gpio<14> IOSTANDARD = LVCMOS33; -NET gpio<15> IOSTANDARD = LVCMOS33; -NET gpio<16> IOSTANDARD = LVCMOS33; -NET gpio<17> IOSTANDARD = LVCMOS33; -NET gpio<18> IOSTANDARD = LVCMOS33; -NET gpio<19> IOSTANDARD = LVCMOS33; -NET gpio<20> IOSTANDARD = LVCMOS33; -NET gpio<21> IOSTANDARD = LVCMOS33; -#SMA Connectors -NET gpio<22> LOC = C12; # SMA_IN_N -NET gpio<23> LOC = C13; # SMA_IN_P -NET gpio<24> LOC = D7; # SMA_OUT_N -NET gpio<25> LOC = D8; # SMA_OUT_P -NET gpio<26> LOC = AD12;# USERCLK -NET gpio<26> IOSTANDARD = LVCMOS33; - -NET "gpio<*>" PULLDOWN; -NET "gpio<*>" TIG; -NET "gpio<*>" SLEW = SLOW; -NET "gpio<*>" DRIVE = 2; - -NET "gpio<22>" SLEW = FAST; -NET "gpio<22>" DRIVE = 12; -NET "gpio<23>" SLEW = FAST; -NET "gpio<23>" DRIVE = 12; -NET "gpio<24>" SLEW = FAST; -NET "gpio<24>" DRIVE = 12; -NET "gpio<25>" SLEW = FAST; -NET "gpio<25>" DRIVE = 12; - -NET "gpio2_d_out<*>" TIG; -NET "gpio2_t_out<*>" TIG; -NET "gpio2_in<*>" TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for PS/2 Ports -#------------------------------------------------------------------------------ - -#Keyboard -NET ps2_keyb_clk LOC = D2; -NET ps2_keyb_clk SLEW = SLOW; -NET ps2_keyb_clk DRIVE = 2; -NET ps2_keyb_clk TIG; -NET ps2_keyb_data LOC = G9; -NET ps2_keyb_data SLEW = SLOW; -NET ps2_keyb_data DRIVE = 2; -NET ps2_keyb_data TIG; - -#Mouse -NET ps2_mouse_clk LOC = B14; -NET ps2_mouse_clk SLEW = SLOW; -NET ps2_mouse_clk DRIVE = 2; -NET ps2_mouse_clk TIG; -NET ps2_mouse_data LOC = C14; -NET ps2_mouse_data SLEW = SLOW; -NET ps2_mouse_data DRIVE = 2; -NET ps2_mouse_data TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for IIC Controller -#------------------------------------------------------------------------------ - -NET iic_scl LOC = A17; -NET iic_sda LOC = B17; -NET iic_scl SLEW = SLOW; -NET iic_scl DRIVE = 6; -NET iic_scl TIG; -NET iic_sda SLEW = SLOW; -NET iic_sda DRIVE = 6; -NET iic_sda TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for AC97 Sound Controller -#------------------------------------------------------------------------------ - -NET ac97_bit_clk LOC = AE10; -NET ac97_bit_clk IOSTANDARD = LVCMOS33; -NET ac97_bit_clk PERIOD = 80; -NET ac97_sdata_in LOC = AD16; -NET ac97_sdata_in IOSTANDARD = LVCMOS33; -NET ac97_reset_n LOC = AD10; -NET ac97_reset_n IOSTANDARD = LVCMOS33; -NET ac97_reset_n TIG; -NET ac97_sdata_out LOC = C8; -NET ac97_sync LOC = D9; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for System ACE MPU / USB -#------------------------------------------------------------------------------ - -NET sysace_clk_in LOC = AF11; -NET sysace_clk_in IOSTANDARD = LVCMOS33; -NET sysace_clk_in TNM_NET = "sysace_clk_in"; -# Leave 1 ns margin -TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns; - -NET sace_usb_a<0> LOC = U22; -NET sace_usb_a<1> LOC = Y10; -NET sace_usb_a<2> LOC = AA10; -NET sace_usb_a<3> LOC = AC7; -NET sace_usb_a<4> LOC = Y7; -NET sace_usb_a<5> LOC = AA9; -NET sace_usb_a<6> LOC = Y9; -NET sace_usb_a<*> IOSTANDARD = LVCMOS33; -NET sace_usb_a<*> SLEW = FAST; -NET sace_usb_a<*> DRIVE = 8; -NET sace_mpce LOC = AD5; -NET sace_mpce IOSTANDARD = LVCMOS33; -NET sace_mpce SLEW = FAST; -NET sace_mpce DRIVE = 8; -NET sace_usb_d<0> LOC = AB7; -NET sace_usb_d<1> LOC = AC9; -NET sace_usb_d<2> LOC = AB9; -NET sace_usb_d<3> LOC = AE6; -NET sace_usb_d<4> LOC = AD6; -NET sace_usb_d<5> LOC = AF9; -NET sace_usb_d<6> LOC = AE9; -NET sace_usb_d<7> LOC = AD8; -NET sace_usb_d<8> LOC = AC8; -NET sace_usb_d<9> LOC = AF4; -NET sace_usb_d<10> LOC = AE4; -NET sace_usb_d<11> LOC = AD3; -NET sace_usb_d<12> LOC = AC3; -NET sace_usb_d<13> LOC = AF6; -NET sace_usb_d<14> LOC = AF5; -NET sace_usb_d<15> LOC = AA7; -NET sace_usb_d<*> IOSTANDARD = LVCMOS33; -NET sace_usb_d<*> SLEW = FAST; -NET sace_usb_d<*> DRIVE = 8; -NET sace_usb_d<*> PULLDOWN; -NET sace_usb_oen LOC = AA8; -NET sace_usb_oen IOSTANDARD = LVCMOS33; -NET sace_usb_oen SLEW = FAST; -NET sace_usb_oen DRIVE = 8; -NET sace_usb_wen LOC = Y8; -NET sace_usb_wen IOSTANDARD = LVCMOS33; -NET sace_usb_wen SLEW = FAST; -NET sace_usb_wen DRIVE = 8; -NET sysace_mpirq LOC = AD4; -NET sysace_mpirq IOSTANDARD = LVCMOS33; -NET sysace_mpirq TIG; -NET sysace_mpirq PULLDOWN; - -NET usb_csn LOC = AF10; -NET usb_csn IOSTANDARD = LVCMOS33; -NET usb_csn SLEW = FAST; -NET usb_csn DRIVE = 8; -NET usb_hpi_reset_n LOC = A7; -NET usb_hpi_reset_n IOSTANDARD = LVCMOS25; -NET usb_hpi_reset_n TIG; -NET usb_hpi_int LOC = V5; -NET usb_hpi_int IOSTANDARD = LVCMOS33; -NET usb_hpi_int TIG; -NET usb_hpi_int PULLDOWN; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET ddr_ad<0> LOC = C26; # DDR_A0 -NET ddr_ad<1> LOC = E17; # DDR_A1 -NET ddr_ad<2> LOC = D18; # DDR_A2 -NET ddr_ad<3> LOC = C19; # DDR_A3 -NET ddr_ad<4> LOC = F17; # DDR_A4 -NET ddr_ad<5> LOC = B18; # DDR_A5 -NET ddr_ad<6> LOC = B20; # DDR_A6 -NET ddr_ad<7> LOC = C20; # DDR_A7 -NET ddr_ad<8> LOC = D20; # DDR_A8 -NET ddr_ad<9> LOC = C21; # DDR_A9 -NET ddr_ad<10> LOC = A18; # DDR_A10 -NET ddr_ad<11> LOC = B21; # DDR_A11 -NET ddr_ad<12> LOC = A24; # DDR_A12 -NET ddr_ba<0> LOC = B12; # DDR_BA0 -NET ddr_ba<1> LOC = A16; # DDR_BA1 -NET ddr_casb LOC = F23; # DDR_CAS_N -NET ddr_cke LOC = G22; # DDR_CKE -NET ddr_csb LOC = G21; # DDR_CS_N -NET ddr_rasb LOC = F24; # DDR_RAS_N -NET ddr_web LOC = A23; # DDR_WE_N - -NET ddr_clk LOC = A10; # DDR_CK1_P -NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET ddr_clkb LOC = B10; # DDR_CK1_N - -NET ddr_dm<0> LOC = G19; # DDR_DM0 -NET ddr_dm<1> LOC = G24; # DDR_DM1 -NET ddr_dm<2> LOC = G20; # DDR_DM2 -NET ddr_dm<3> LOC = C22; # DDR_DM3 - -NET ddr_dqs<0> LOC = D25; # DDR_DQS0 -NET ddr_dqs<1> LOC = G18; # DDR_DQS1 -NET ddr_dqs<2> LOC = G17; # DDR_DQS2 -NET ddr_dqs<3> LOC = D26; # DDR_DQS3 - -NET ddr_dq<0> LOC = H20; # DDR_D0 -NET ddr_dq<1> LOC = E23; # DDR_D1 -NET ddr_dq<2> LOC = H26; # DDR_D2 -NET ddr_dq<3> LOC = H22; # DDR_D3 -NET ddr_dq<4> LOC = E25; # DDR_D4 -NET ddr_dq<5> LOC = E26; # DDR_D5 -NET ddr_dq<6> LOC = F26; # DDR_D6 -NET ddr_dq<7> LOC = E24; # DDR_D7 -NET ddr_dq<8> LOC = E20; # DDR_D8 -NET ddr_dq<9> LOC = A22; # DDR_D9 -NET ddr_dq<10> LOC = C23; # DDR_D10 -NET ddr_dq<11> LOC = C24; # DDR_D11 -NET ddr_dq<12> LOC = A20; # DDR_D12 -NET ddr_dq<13> LOC = A21; # DDR_D13 -NET ddr_dq<14> LOC = D24; # DDR_D14 -NET ddr_dq<15> LOC = E18; # DDR_D15 -NET ddr_dq<16> LOC = F18; # DDR_D16 -NET ddr_dq<17> LOC = A19; # DDR_D17 -NET ddr_dq<18> LOC = F19; # DDR_D18 -NET ddr_dq<19> LOC = B23; # DDR_D19 -NET ddr_dq<20> LOC = E21; # DDR_D20 -NET ddr_dq<21> LOC = D22; # DDR_D21 -NET ddr_dq<22> LOC = D23; # DDR_D22 -NET ddr_dq<23> LOC = B24; # DDR_D23 -NET ddr_dq<24> LOC = E22; # DDR_D24 -NET ddr_dq<25> LOC = F20; # DDR_D25 -NET ddr_dq<26> LOC = H23; # DDR_D26 -NET ddr_dq<27> LOC = G25; # DDR_D27 -NET ddr_dq<28> LOC = G26; # DDR_D28 -NET ddr_dq<29> LOC = H25; # DDR_D29 -NET ddr_dq<30> LOC = H24; # DDR_D30 -NET ddr_dq<31> LOC = H21; # DDR_D31 - -NET ddr_ad<*> IOSTANDARD = SSTL2_I; -NET ddr_ba<*> IOSTANDARD = SSTL2_I; -NET ddr_casb IOSTANDARD = SSTL2_I; -NET ddr_cke IOSTANDARD = SSTL2_I; -NET ddr_clk IOSTANDARD = SSTL2_I; -NET ddr_clk_fb IOSTANDARD = LVCMOS25; -NET ddr_clkb IOSTANDARD = SSTL2_I; -NET ddr_casb IOSTANDARD = SSTL2_I; -NET ddr_csb IOSTANDARD = SSTL2_I; -NET ddr_rasb IOSTANDARD = SSTL2_I; -NET ddr_web IOSTANDARD = SSTL2_I; - -NET ddr_dqs<*> IOSTANDARD = SSTL2_II; -NET ddr_dm<*> IOSTANDARD = SSTL2_II; -NET ddr_dq<*> IOSTANDARD = SSTL2_II; - -// Timing Constraint for DDR Feedback Clock -NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb"; -TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for TFT VGA LCD Controller -#------------------------------------------------------------------------------ - -NET tft_lcd_b<0> LOC = L26; # VGA_B2 -NET tft_lcd_b<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_b<1> LOC = C5; # VGA_B3 -NET tft_lcd_b<2> LOC = C7; # VGA_B4 -NET tft_lcd_b<3> LOC = B7; # VGA_B5 -NET tft_lcd_b<4> LOC = G8; # VGA_B6 -NET tft_lcd_b<5> LOC = F8; # VGA_B7 -NET tft_lcd_b<*> SLEW = FAST; -NET tft_lcd_b<*> DRIVE = 8; - -NET tft_lcd_clk LOC = AF8; -NET tft_lcd_clk IOSTANDARD = LVDCI_33; -NET tft_lcd_clk SLEW = FAST; -NET tft_lcd_clk DRIVE = 8; - -NET tft_lcd_g<0> LOC = M20; # VGA_G2 -NET tft_lcd_g<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_g<1> LOC = E4; # VGA_G3 -NET tft_lcd_g<2> LOC = D3; # VGA_G4 -NET tft_lcd_g<3> LOC = H7; # VGA_G5 -NET tft_lcd_g<4> LOC = H8; # VGA_G6 -NET tft_lcd_g<5> LOC = C1; # VGA_G7 -NET tft_lcd_g<*> SLEW = FAST; -NET tft_lcd_g<*> DRIVE = 8; - -NET tft_lcd_hsync LOC = C10; -NET tft_lcd_hsync SLEW = FAST; -NET tft_lcd_hsync DRIVE = 8; - -NET tft_lcd_r<0> LOC = N25; #VGA_R2 -NET tft_lcd_r<0> IOSTANDARD = LVCMOS33; -NET tft_lcd_r<1> LOC = C2; #VGA_R3 -NET tft_lcd_r<2> LOC = G7; #VGA_R4 -NET tft_lcd_r<3> LOC = F7; #VGA_R5 -NET tft_lcd_r<4> LOC = E5; #VGA_R6 -NET tft_lcd_r<5> LOC = E6; #VGA_R7 -NET tft_lcd_r<*> SLEW = FAST; -NET tft_lcd_r<*> DRIVE = 8; - -NET tft_lcd_vsync LOC = A8; -NET tft_lcd_vsync SLEW = FAST; -NET tft_lcd_vsync DRIVE = 8; - -TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG; -TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET plb_error LOC = L24; -NET plb_error IOSTANDARD = LVCMOS33; -NET plb_error TIG; -NET opb_error LOC = V6; -NET opb_error IOSTANDARD = LVCMOS33; -NET opb_error TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Ethernet -#------------------------------------------------------------------------------ - -NET phy_col LOC = E3; -NET phy_crs LOC = D5; -NET phy_dv LOC = A9; -NET phy_rx_clk LOC = B15; -NET phy_rx_data<3> LOC = C4; -NET phy_rx_data<2> LOC = D4; -NET phy_rx_data<1> LOC = E1; -NET phy_rx_data<0> LOC = F1; - -NET phy_rx_er LOC = B9; -NET phy_tx_clk LOC = C15; -NET phy_mii_clk LOC = D1; -NET phy_mii_int_n LOC = H4; -NET phy_rst_n LOC = D10; -NET phy_tx_data<3> LOC = G1; -NET phy_tx_data<2> LOC = H3; -NET phy_tx_data<1> LOC = H2; -NET phy_tx_data<0> LOC = H1; -NET phy_tx_en LOC = F4; -NET phy_tx_er LOC = F3; -NET phy_mii_data LOC = G4; - -NET phy_mii_int_n PULLUP; - -NET phy_mii_int_n TIG; -NET phy_rst_n TIG; - -# Timing Constraints (these are recommended in documentation and -# are unaltered except for the TIG) -NET "phy_rx_clk" TNM_NET = "RXCLK_GRP"; -NET "phy_tx_clk" TNM_NET = "TXCLK_GRP"; -TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns; -TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns; - -NET "phy_tx_clk" MAXSKEW= 1.0 ns; -NET "phy_rx_clk" MAXSKEW= 1.0 ns; -NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns; -NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns; - -NET "phy_rx_data<3>" IOBDELAY=NONE; -NET "phy_rx_data<2>" IOBDELAY=NONE; -NET "phy_rx_data<1>" IOBDELAY=NONE; -NET "phy_rx_data<0>" IOBDELAY=NONE; -NET "phy_dv" IOBDELAY=NONE; -NET "phy_rx_er" IOBDELAY=NONE; -NET "phy_crs" IOBDELAY=NONE; -NET "phy_col" IOBDELAY=NONE; - -# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/DVD_FF" IOB=FALSE; -INST "opb_ethernet_0/opb_ethernet_0/RER_FF" IOB=FALSE; - -# Timing ignores (to specify unconstrained paths) -TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; -TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; -TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; -TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for SRAM/FLASH -#------------------------------------------------------------------------------ - -NET sram_clk LOC = AF7; -NET sram_clk_fb LOC = AD17; -NET flash_a23 LOC = T21; -NET sram_flash_addr<22> LOC = U20; -NET sram_flash_addr<21> LOC = T19; -NET sram_flash_addr<20> LOC = AC5; -NET sram_flash_addr<19> LOC = AB5; -NET sram_flash_addr<18> LOC = AC4; -NET sram_flash_addr<17> LOC = AB4; - -NET sram_flash_addr<16> LOC = AB3; -NET sram_flash_addr<15> LOC = AA4; -NET sram_flash_addr<14> LOC = AA3; -NET sram_flash_addr<13> LOC = W5; -NET sram_flash_addr<12> LOC = W6; -NET sram_flash_addr<11> LOC = W3; -NET sram_flash_addr<10> LOC = AF3; -NET sram_flash_addr<9> LOC = AE3; -NET sram_flash_addr<8> LOC = AD2; -NET sram_flash_addr<7> LOC = AD1; -NET sram_flash_addr<6> LOC = AC2; -NET sram_flash_addr<5> LOC = AC1; -NET sram_flash_addr<4> LOC = AB2; -NET sram_flash_addr<3> LOC = AB1; -NET sram_flash_addr<2> LOC = AA1; -NET sram_flash_addr<1> LOC = Y2; -NET sram_flash_addr<0> LOC = Y1; -NET sram_flash_data<31> LOC = F14; -NET sram_flash_data<30> LOC = F13; -NET sram_flash_data<29> LOC = F12; -NET sram_flash_data<28> LOC = F11; -NET sram_flash_data<27> LOC = F16; -NET sram_flash_data<26> LOC = F15; -NET sram_flash_data<25> LOC = D14; -NET sram_flash_data<24> LOC = D13; -NET sram_flash_data<23> LOC = D15; -NET sram_flash_data<22> LOC = E14; -NET sram_flash_data<21> LOC = C11; -NET sram_flash_data<20> LOC = D11; -NET sram_flash_data<19> LOC = D16; -NET sram_flash_data<18> LOC = C16; -NET sram_flash_data<17> LOC = E13; -NET sram_flash_data<16> LOC = D12; -NET sram_flash_data<15> LOC = AA14; -NET sram_flash_data<14> LOC = AB14; -NET sram_flash_data<13> LOC = AC12; -NET sram_flash_data<12> LOC = AC11; -NET sram_flash_data<11> LOC = AA16; -NET sram_flash_data<10> LOC = AA15; -NET sram_flash_data<9> LOC = AB13; -NET sram_flash_data<8> LOC = AA13; -NET sram_flash_data<7> LOC = AC14; -NET sram_flash_data<6> LOC = AD14; -NET sram_flash_data<5> LOC = AA12; -NET sram_flash_data<4> LOC = AA11; -NET sram_flash_data<3> LOC = AC16; -NET sram_flash_data<2> LOC = AC15; -NET sram_flash_data<1> LOC = AC13; -NET sram_flash_data<0> LOC = AD13; -NET sram_cen LOC = V7; -NET sram_flash_oe_n LOC = AC6; -NET sram_flash_we_n LOC = AB6; -NET sram_bw<3> LOC = Y3; #Y4; -NET sram_bw<2> LOC = Y4; #Y3; -NET sram_bw<1> LOC = Y5; #Y6; -NET sram_bw<0> LOC = Y6; #Y5; -NET flash_ce LOC = W7; -NET sram_adv_ld_n LOC = W4; -NET sram_mode LOC = V26; - -NET sram_clk IOSTANDARD = LVCMOS33; -NET sram_clk DRIVE = 16; -NET sram_clk SLEW = FAST; -NET sram_clk_fb IOSTANDARD = LVCMOS33; - -NET flash_a23 IOSTANDARD = LVDCI_33; -NET flash_a23 SLEW = FAST; -NET flash_a23 DRIVE = 8; - -NET sram_mode IOSTANDARD = LVDCI_33; -NET sram_mode SLEW = FAST; -NET sram_mode DRIVE = 8; - -NET sram_flash_addr<*> IOSTANDARD = LVDCI_33; -NET sram_flash_addr<*> SLEW = FAST; -NET sram_flash_addr<*> DRIVE = 8; - -NET sram_flash_data<*> IOSTANDARD = LVCMOS33; -NET sram_flash_data<*> DRIVE = 12; -NET sram_flash_data<*> SLEW = FAST; -NET sram_flash_data<*> PULLDOWN; - -NET sram_flash_oe_n IOSTANDARD = LVDCI_33; -NET sram_flash_oe_n SLEW = FAST; -NET sram_flash_oe_n DRIVE = 8; - -NET sram_flash_we_n IOSTANDARD = LVDCI_33; -NET sram_flash_we_n SLEW = FAST; -NET sram_flash_we_n DRIVE = 8; - -NET sram_bw<*> IOSTANDARD = LVDCI_33; -NET sram_bw<*> SLEW = FAST; -NET sram_bw<*> DRIVE = 8; - -NET flash_ce IOSTANDARD = LVDCI_33; -NET flash_ce SLEW = FAST; -NET flash_ce DRIVE = 8; - -NET sram_cen IOSTANDARD = LVDCI_33; -NET sram_cen SLEW = FAST; -NET sram_cen DRIVE = 8; - -NET sram_adv_ld_n IOSTANDARD = LVDCI_33; -NET sram_adv_ld_n SLEW = FAST; -NET sram_adv_ld_n DRIVE = 8; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Expansion Header GPIO -#------------------------------------------------------------------------------ - -NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64 -NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62 -NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8 -NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58 -NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44 -NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48 -NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14 -NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20 -NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46 -NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56 -NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54 -NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16 -NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18 -NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34 -NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6 -NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30 -NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4 -NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24 -NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60 -NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10 -NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22 -NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40 -NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38 -NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50 -NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12 -NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26 -NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32 -NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52 -NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2 -NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36 -NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42 -NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28 -NET gpio_exp_hdr1<*> TIG; -NET gpio_exp_hdr1<*> PULLDOWN; - -NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40 -NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38 -NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32 -NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30 -NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44 -NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42 -NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24 -NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22 -NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48 -NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46 -NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64 -NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62 -NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16 -NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14 -NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36 -NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34 -NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52 -NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50 -NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56 -NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54 -NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60 -NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58 -NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8 -NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6 -NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12 -NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10 -NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20 -NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18 -NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28 -NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26 -NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4 -NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2 -NET gpio_exp_hdr2<*> TIG; -NET gpio_exp_hdr2<*> PULLDOWN; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for Character LCD GPIO -#------------------------------------------------------------------------------ - -NET gpio_char_lcd<6> LOC = AE13; # LCD_E -NET gpio_char_lcd<5> LOC = AC17; # LCD_RS -NET gpio_char_lcd<4> LOC = AB17; # LCD_RW -NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7 -NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6 -NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5 -NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4 -NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33; -NET gpio_char_lcd<*> TIG; -NET gpio_char_lcd<*> PULLDOWN; diff --git a/lib/CPUs/MIPS/bsp/examples/Bessel.c b/lib/CPUs/MIPS/bsp/examples/Bessel.c deleted file mode 100644 index 080fe17..0000000 --- a/lib/CPUs/MIPS/bsp/examples/Bessel.c +++ /dev/null @@ -1,87 +0,0 @@ -/************************************************************************/ -/* Ein Programm zur Berechnung der Bessel-Koeffizienten Jn -/* Dateiname : Bessel.cpp -/* Autoren : T. Burr, J. Ahrensfeld -/* Datum : 28.10.1999 -/* letzte Änderung : 28.01.2000 -/* Version : 1.0 -/************************************************************************/ - -#include "stdio.h" -#include "math.h" -#include "stdlib.h" - - -#define MAX_SUM 25 -#define VERSION "1.0" - -/************************************************************************/ -/* Funktionsdeklarationen */ -/************************************************************************/ -// Fakultätsberechnung -double fak (int N) -{ - int index; - double erg=1; - - for (index = 1; index <= N; index++) - erg = erg * index; - - return erg; -} - -// Bessel() -// Berechnung von Jn von mfm -double bessel(int n, double mfm) -{ - int m; - double Jn=0; - - for (m=0; m < MAX_SUM; m++) - { - Jn = Jn + (pow(-1.0,m)/(fak(m)*fak(m+n))*pow(mfm/2.0,(2*m+n))); - } - return Jn; -} - - -/************************************************************************/ -/* Das Hauptprogramm -/************************************************************************/ -void main() -{ - - int N, Nmax; - double erg; - float mfm; - - printf("\n\t Besselfunktion Version %s",VERSION); - printf("\n\t ~~~~~~~~~~~~~~~~~~~~~~~~~~\n"); - printf("\n\tCopyright by J. Ahrensfeld & T. Burr\n\n"); - -// --------------------------------------------------------------------------------- - // Benutzereingaben - printf("\nBerechnungen fuer J = 0..."); - if(scanf("%d",&Nmax)==0) - exit (-1); - - printf("Bitte Modulationsindex eingeben : "); - if(scanf("%f",&mfm)==0) - exit(-1); - - printf("\n"); - -// --------------------------------------------------------------------------------- - // Berechnung - for (N=0; N <= Nmax; N++) - { - erg = bessel(N,(double)mfm); - printf("J(%d) = %10.8f\n",N,erg); - } - - printf("FERTIG.\n"); - - } - -/************************************************************************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/Makefile b/lib/CPUs/MIPS/bsp/examples/Makefile deleted file mode 100644 index dddd447..0000000 --- a/lib/CPUs/MIPS/bsp/examples/Makefile +++ /dev/null @@ -1,200 +0,0 @@ -ENDIAN_FLAGS=-EB -CFLAGS=$(ENDIAN_FLAGS) -msoft-float -O2 -march=r3000 -I. -Wl,-M -LIBS=-lc -lm - - -AS=mipsel-elf-as -AR=mipsel-elf-ar -CC=mipsel-elf-gcc -LD=mipsel-elf-ld -OBJDUMP=mipsel-elf-objdump -OBJCOPY=mipsel-elf-objcopy -FLASHGEN=flashgen - -PROG = hello testbench test_irq dhry queens stanford paranoia rmd160_test Bessel whet phrasen dttl richards_benchmark test_exception life r3 gunzip basic_math jman_patches jman_patchmeshes jman_polys - -all: $(PROG) - -libsys: startup.S kernel.S libsys.c xcpt.c irq.c - $(CC) $(CFLAGS) -G 0 -c startup.S -o startup.o - $(CC) $(CFLAGS) -G 0 -c kernel.S -o kernel.o - $(CC) $(CFLAGS) -G 0 -DSTDERR_FUNCTION=_ser_putchar -DSTDOUT_FUNCTION=_ser_putchar -D_putchar=_ser_putchar -c libsys.c -o libsys.o - $(CC) $(CFLAGS) -G 0 -c xcpt.c -o xcpt.o - $(CC) $(CFLAGS) -G 0 -c irq.c -o irq.o - $(CC) $(CFLAGS) -G 0 -c dbg.c -o dbg.o - $(CC) $(CFLAGS) -G 0 -c mipsdis.c -o mipsdis.o - $(AR) -r libsys.a libsys.o xcpt.o irq.o dbg.o mipsdis.o - -hello: hello.c - $(CC) $(CFLAGS) -o $@.elf -Os hello.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -testbench: testbench.c - $(CC) $(CFLAGS) -O3 -o $@.elf -DNOSIGNAL -DBATCHMODE -DNOMAIN -Os -g testbench.c paranoia.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -test_irq: test_irq.c - $(CC) $(CFLAGS) -o $@.elf test_irq.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -dhry: dhry_1.c dhry_2.c dhry.h - $(CC) $(CFLAGS) -o $@.elf -DHZ=1000 dhry_1.c dhry_2.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -queens: queens.c - $(CC) $(CFLAGS) -o $@.elf -DUNIX_Old -DHZ=1000 queens.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -stanford: stanford.c - $(CC) $(CFLAGS) -O3 -o $@.elf -DHZ=1000 stanford.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -paranoia: paranoia.c - $(CC) $(CFLAGS) -O3 -o $@.elf -DNOSIGNAL -DBATCHMODE paranoia.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -rmd160_test: rmd160_test.c rmd160.c rmd160.h - $(CC) $(CFLAGS) -O2 -o $@.elf -DNOSIGNAL -DBATCHMODE rmd160.c rmd160_test.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -Bessel: Bessel.c - $(CC) $(CFLAGS) -o $@.elf Bessel.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -whet: whet.c - $(CC) $(CFLAGS) -o $@.elf whet.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -phrasen: phrasen.c - $(CC) $(CFLAGS) -o $@.elf phrasen.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -dttl: dttl.c random.c - $(CC) $(CFLAGS) -o $@.elf dttl.c random.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -richards_benchmark: richards_benchmark.c - $(CC) $(CFLAGS) -o $@.elf richards_benchmark.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -test_exception: test_exception.c - $(CC) $(CFLAGS) -o $@.elf -O1 test_exception.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -life: life.c - $(CC) $(CFLAGS) -o $@.elf -g life.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -r3: r3.c - $(CC) $(CFLAGS) -O3 -o $@.elf -DJMIPS_VGA -O2 r3.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -gunzip: gunzip.c inflate.c crc32.c - $(CC) $(CFLAGS) -o $@.elf -o $@.elf gunzip.c inflate.c crc32.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -basic_math: basicmath_small.c rad2deg.c cubic.c isqrt.c - $(CC) $(CFLAGS) -o $@.elf -o $@.elf basicmath_small.c rad2deg.c cubic.c isqrt.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -JMAN_SRC= \ - jman/bintree.c \ - jman/camset.c \ - jman/engine.c \ - jman/graph_state.c \ - jman/grid.c \ - jman/imageio.c \ - jman/linklist.c \ - jman/matrix.c \ - jman/object.c \ - jman/render.c \ - jman/ri.c \ - jman/ribgen.c \ - jman/stack.c \ - jman/vars.c - -jman_patches: $(JMAN_SRC) jman/main_patches.c - $(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_patches.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -jman_patchmeshes: $(JMAN_SRC) jman/main_patchmeshes.c jman/patches2.c - $(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_patchmeshes.c jman/patches2.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -jman_polys: $(JMAN_SRC) jman/main_polypin.c jman/polys.c - $(CC) $(CFLAGS) -I../ -o $@.elf -o $@.elf jman/main_polypin.c jman/polys.c $(JMAN_SRC) $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - -serdump: serdump.c - $(CC) $(CFLAGS) -O3 -o $@.elf -O2 serdump.c $(LIBS) >$@.map - $(OBJDUMP) -d $@.elf > $@.dis - $(OBJCOPY) $@.elf -O binary $@.bin - $(OBJCOPY) -O srec $@.elf $@.srec - $(FLASHGEN) $@.bin $(ENDIAN_FLAGS) - - -clean: - rm -rf *.a *.o *.bin *.map *.dis *.srec *.elf $(PROG) > /dev/null diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile b/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile deleted file mode 100644 index 4344e93..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/Makefile +++ /dev/null @@ -1,47 +0,0 @@ -ENDIAN='big' - -ifeq ($(ENDIAN), 'big') - ENDIAN_FLAGS=-EB - LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib/eb -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER)/eb -else - ENDIAN_FLAGS=-EL - LIB_DIRS=-L $(MIPS_TOOLS_PREFIX)/mipsel-elf/lib -L $(MIPS_TOOLS_PREFIX)/lib/gcc/mipsel-elf/$(MIPS_GCC_VER) -endif - -CFLAGS=$(ENDIAN_FLAGS) -Os -I. -I../ -msoft-float -march=r3000 -LFLAGS=$(ENDIAN_FLAGS) -M -T bootloader.ld - -LIBS=-lc -lgcc - -CC=mipsel-elf-gcc -LD=mipsel-elf-ld -OBJDUMP=mipsel-elf-objdump -OBJCOPY=mipsel-elf-objcopy - -all: bootloader_flash - -libsys: startup_boot.S init_boot.S kernel_boot.S libsys_boot.c - $(CC) $(CFLAGS) -c startup_boot.S -o startup.o - $(CC) $(CFLAGS) -c init_boot.S -o init.o - $(CC) $(CFLAGS) -c kernel_boot.S -o kernel.o - $(CC) $(CFLAGS) -c libsys_boot.c -o libsys.o - -bootloader: libsys bootloader.c - $(CC) $(CFLAGS) -g -c bootloader.c - $(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o bootloader.o -o bootloader.elf $(LIBS) >bootloader.map - $(OBJDUMP) -d bootloader.elf > bootloader.dis - $(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin - $(OBJCOPY) -O srec bootloader.elf bootloader.srec - romgen bootloader.ROM.bin 10 $(ENDIAN_FLAGS) - -bootloader_flash: libsys bootloader_with_flash.c - $(CC) $(CFLAGS) -g -c bootloader_with_flash.c - $(CC) $(CFLAGS) -g -c ../cfiflash.c - $(LD) $(LFLAGS) $(LIB_DIRS) startup.o init.o kernel.o libsys.o cfiflash.o bootloader_with_flash.o -o bootloader.elf $(LIBS) >bootloader.map - $(OBJDUMP) -d bootloader.elf > bootloader.dis - $(OBJCOPY) bootloader.elf -O binary bootloader.ROM.bin - $(OBJCOPY) -O srec bootloader.elf bootloader.srec - romgen bootloader.ROM.bin 11 $(ENDIAN_FLAGS) - -clean: - rm -rf *.o *.bin *.map *.dis *.srec *.elf *.vhd* *.tcl bootloader > /dev/null diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c deleted file mode 100644 index 7ade222..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.c +++ /dev/null @@ -1,247 +0,0 @@ -#include "libsys_boot.h" - -typedef struct _ssrec_t -{ - UINT32 addr; - UINT32 size; - UINT32 type; - UINT8 *data; - -} srec_t; - -enum srec_type -{ - srec_err, srec_sob, srec_data, srec_rec, srec_eob -}; - -UINT8 h2i(UINT8 *c) -{ - int i; - UINT8 t, b = 0; - - for (i=0; i < 2; i++) - { - t = c[i]; - if (t >= 'A') - t = t - 'A' + 10; - else - t -= '0'; - - b = (b << 4) | t; - } - return b; -} - -int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen) -{ - UINT8 chksum, byte; - int alen, i; - - if (!buflen) - return srec_err; - - pRec->type = srec_rec; - alen = 0; - if ((pBuf[1] > '0') && (pBuf[1] < '4')) - { - alen = pBuf[1] - '0' + 1; - pRec->type = srec_data; - } - else if ((pBuf[1] >= '7') && (pBuf[1] <= '9')) - { - alen = 11 - (pBuf[1] - '0'); - pRec->type = srec_eob; - } - else if (pBuf[1] == '0') - { - alen = 2; - pRec->type = srec_sob; - } - - byte = h2i(&pBuf[2]); - pRec->size = byte; - chksum = byte; - - pRec->addr = 0; - for (i=0; i < alen; i++) - { - byte = h2i(&pBuf[4+2*i]); - pRec->addr = pRec->addr << 8 | byte; - chksum += byte; - } - pRec->size -= (alen+1); - - pRec->data = (UINT8*) &pBuf[4 + 2*alen]; - for (i=0; i < (int)pRec->size; i++) - { - byte = h2i(&pRec->data[2*i]); - pRec->data[i] = byte; - chksum += byte; - } - chksum = ~chksum; - byte = h2i(&pRec->data[2*i]); - if (chksum != byte) - return 0; - - return pRec->type; -} - -int srec_getline(UINT8 *pLine) -{ - char c; - int i = 0; - - do - { - c = readchar(); - - } while ((c != 's') && (c != 'S')); - - while(((c != 0x0D) && (c != 0x0A))) - { - pLine[i++] = c; - c = readchar(); - }; - - return i; -} - -void Jump_to(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - __asm - ( - "nop\n" - ); - __asm - ( - ".set reorder\n" - ); -} - -void Exec_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "mfc0 $26, $12\n" // change exception vector - "li $27, 0xFFBFFFFF\n" - "and $26, $27\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "lw $v0, 16($sp)\n" - "nop\n" - "jr $v0\n" // jump entry - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} -void PrintCPUinfo(void) -{ - int result, rev_id; - - char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"}; - - // Print Status register - result = CP0_SR_read(); - - sputs("Status : "); - print_word(result); - sputs("\n"); - - // Print Revision - result = CP0_PRID_read(); - rev_id = (result >> 8) & 0xFF; - sputs("CPU type: "); - if ((rev_id > 0) && (rev_id < 0x07)) - { - sputs(cpu_type_str[rev_id]); - sputs(" Rev."); - rev_id = result & 0xFF; - print_byte((char)rev_id); - } - else - sputs("Unknown"); - - sputs("\n"); - -} - -#define MAX_IMG_SIZE (1024*1024) // bytes - -int main(int argc, char *argv[]) -{ - UINT8 buf[256]; - srec_t srec; - int result, srec_state, i; - UINT32 haddr; - volatile UINT8 *pMem; - haddr = 0; - - // ---------------------------------------------------------- - sputs("\n\n"); - PrintCPUinfo(); - sputs("Booting from UART.."); - - while(1) - { - sputs("."); - while(1) - { - result = srec_getline(buf); - srec_state = decode_srec(&srec, buf, result); - switch (srec_state) - { - case srec_data: - if ((srec.addr + srec.size) > haddr) - haddr = srec.addr + srec.size; - - pMem = (UINT8*)srec.addr; - for (i=0; i < srec.size; i++) - *pMem++ = srec.data[i]; - - break; - - case srec_eob: - sputs("done\n\n"); - sputs("Execute program at "); - print_word(srec.addr); - sputs("\n\n"); - - Exec_at((void*)srec.addr); - break; - - default: - result = -1; - break; - } - if (result < 0) - { - break; - } - - }; - } - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld deleted file mode 100644 index c3cd35e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader.ld +++ /dev/null @@ -1,53 +0,0 @@ -MEMORY -{ - rom : ORIGIN = 0xBFC00000, LENGTH = 0x00002000 /* 8K */ - ram : ORIGIN = 0x40000000, LENGTH = 0x00002000 /* 8K */ -} - -OUTPUT_ARCH(mips) -SEARCH_DIR("."); -SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb"); -SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb"); - -stack_ptr = 0x7FFFEFF0; -baudrate = 0x0D; -sys_led_port = 0xA0000000; -sys_uart_data = 0xA0010000; -sys_uart_stat = 0xA0010004; -sys_uart_baud = 0xA0010008; -sys_timer_usec = 0xA000008; -sys_timer_sec = 0xA000000C; - - -SECTIONS -{ - .init ORIGIN(rom) : - { - start = ALIGN(4); - entry = ALIGN(4); - _entry = ALIGN(4); - __entry = ALIGN(4); - *(.stext) - } > rom - - .ktext ORIGIN(rom) + 0x180 : - { - *(.ktext) - } > rom - - .text . : - { - *(.text) - } > rom - - .rodata . : - { - *(.rodata*) - } > rom - - .data ORIGIN(ram) : - { - *(.*data) *(.*bss) *(.*common) - } > ram - -} diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c b/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c deleted file mode 100644 index bbad186..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/bootloader_with_flash.c +++ /dev/null @@ -1,391 +0,0 @@ -#include "libsys_boot.h" -#include "cfiflash.h" - -#define MAGIC_EB 0x4A464931 // "JFI1" in big-endian; -#define MAGIC_EL 0x3149464A // "JFI1" in little-endian; - -typedef struct _ssrec_t -{ - UINT32 addr; - UINT32 size; - UINT32 type; - UINT8 *data; - -} srec_t; -typedef struct _sflash_alloc_tbl_t -{ - UINT32 images[16]; - -} flash_alloc_tbl_t; - -typedef struct _sflash_img_hdr_t -{ - UINT32 magic; - UINT32 target_base; - UINT32 img_base; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -enum srec_type -{ - srec_err, srec_sob, srec_data, srec_rec, srec_eob -}; - -UINT8 h2i(UINT8 *c) -{ - int i; - UINT8 t, b = 0; - - for (i=0; i < 2; i++) - { - t = c[i]; - if (t >= 'A') - t = t - 'A' + 10; - else - t -= '0'; - - b = (b << 4) | t; - } - return b; -} - -int decode_srec(srec_t *pRec, UINT8 *pBuf, int buflen) -{ - UINT8 chksum, byte; - int alen, i; - - if (!buflen) - return srec_err; - - pRec->type = srec_rec; - alen = 0; - if ((pBuf[1] > '0') && (pBuf[1] < '4')) - { - alen = pBuf[1] - '0' + 1; - pRec->type = srec_data; - } - else if ((pBuf[1] >= '7') && (pBuf[1] <= '9')) - { - alen = 11 - (pBuf[1] - '0'); - pRec->type = srec_eob; - } - else if (pBuf[1] == '0') - { - alen = 2; - pRec->type = srec_sob; - } - - byte = h2i(&pBuf[2]); - pRec->size = byte; - chksum = byte; - - pRec->addr = 0; - for (i=0; i < alen; i++) - { - byte = h2i(&pBuf[4+2*i]); - pRec->addr = pRec->addr << 8 | byte; - chksum += byte; - } - pRec->size -= (alen+1); - - pRec->data = (UINT8*) &pBuf[4 + 2*alen]; - for (i=0; i < (int)pRec->size; i++) - { - byte = h2i(&pRec->data[2*i]); - pRec->data[i] = byte; - chksum += byte; - } - chksum = ~chksum; - byte = h2i(&pRec->data[2*i]); - if (chksum != byte) - return 0; - - return pRec->type; -} - -int srec_getline(UINT8 *pLine) -{ - char c; - int i = 0; - - do - { - c = readchar(); - - } while ((c != 's') && (c != 'S')); - - while(((c != 0x0D) && (c != 0x0A))) - { - pLine[i++] = c; - c = readchar(); - }; - - return i; -} - -void Jump_to(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - __asm - ( - "nop\n" - ); - __asm - ( - ".set reorder\n" - ); -} - -void Exec_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "li $26, 0x10000000\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - - __asm - ( - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} - -void Exec_RE_at(void *pEntry) -{ - __asm - ( - ".set noreorder\n" - ); - - __asm - ( - "mfc0 $26, $12\n" // change exception vector - "li $27, 0xFFBFFFFF\n" - "and $26, $27\n" - "li $27, 0x02000000\n" // Reverse Endianess - "or $26, $27\n" - "mtc0 $26, $12\n" - ); - - __asm - ( - "jr %[pEntry]\n" // jump entry - : - : [pEntry] "r" (pEntry) - ); - - __asm - ( - "rfe\n" - ); - - __asm - ( - ".set reorder\n" - ); -} - -#define MAX_IMG_SIZE (1024*1024) // bytes -#define SDRAM_BASE 0x40000000 -#define FLASH_USE_BLOCK 1 - -int main(int argc, char *argv[]) -{ - UINT8 buf[256]; - srec_t srec; - int srec_state, i; - UINT32 haddr, result; - flash_t flash; - flash_img_hdr_t img_hdr = {0}; - flash_img_hdr_t *pImg_hdr; - UINT32 img_size, block_sel; - - volatile UINT32 *pReg = (UINT32*)sys_led_port; - volatile UINT32 *pBtn = (UINT32*)sys_gpio0; - volatile UINT32 *pDip = (UINT32*)sys_gpio1; - volatile UINT8 *pMem; - volatile UINT32 *pROM32; - volatile UINT32 *pMem32; - volatile UINT32 *pFlashIO = (UINT32*)sys_flash_io; // Flash in uncached area - volatile UINT32 *pFlashMem = (UINT32*)sys_flash_mem; // Flash in cached area - volatile UINT32 *pUSB = (UINT32*)sys_usb_data; - - volatile UINT8 *ram8 = (UINT8*)SDRAM_BASE; - volatile UINT16 *ram16 = (UINT16*)SDRAM_BASE; - volatile UINT32 *ram32 = (UINT32*)SDRAM_BASE; - UINT32 flash_offset; - - *pReg = 0; - haddr = 0; - block_sel = 0x7F & (UINT32)*pDip; - - // ---------------------------------------------------------- - if (IS_ERROR(flash_find(&flash, sys_flash_io))) - { - sputs("Cannot find flash device. Exit now!\n\n"); - return 1; - } - - // Get flash offset by value of DIP-switch - flash_offset = flash_get_offset_by_blocknum(&flash, block_sel); - - ram32 = (UINT32*)(SDRAM_BASE); - pFlashIO = (UINT32*)(sys_flash_io + flash_offset); - - if (!(*pBtn & 8)) - { - sputs("\n\n"); - pImg_hdr = (flash_img_hdr_t*)pFlashIO; - if ((pImg_hdr->magic != MAGIC_EL) && (pImg_hdr->magic != MAGIC_EB)) - { - sputs("\n\n"); - sputs("Invalid image found at ");print_word(flash_offset); sputs(". Abort.\n"); - return 1; - } - - sputs("Booting application from flash (");print_word(flash_offset);sputs(")..."); - - ram32 = (UINT32*)pImg_hdr->target_base; - img_size = pImg_hdr->img_size; - - // It's safe to use cached Flash, - // because D-Cache was invalidated during execution of start code -// pFlashIO = (UINT32*)(sys_flash_io + pImg_hdr->img_base); - pFlashMem = (UINT32*)(sys_flash_mem + pImg_hdr->img_base); - - for (i=0; i < img_size/4; i++) -// ram32[i] = pFlashIO[i]; - ram32[i] = pFlashMem[i]; - - sputs("done\n"); - - sputs("Execute at ");print_word(pImg_hdr->target_base); sputs("\n\n"); - Exec_at((void*)ram32); - } - else - { - - sputs("\n\n"); - - sputs("Reading HEX-Record from UART.."); - - // Erase SDRAM - for (i=0; i < MAX_IMG_SIZE/4; i++) - ram32[i] = 0; - - - while(1) - { - sputs("."); - while(1) - { - result = srec_getline(buf); - srec_state = decode_srec(&srec, buf, result); - *pReg = 0; - switch (srec_state) - { - case srec_data: - if ((srec.addr + srec.size) > haddr) - haddr = srec.addr + srec.size; - - pMem = (UINT8*)srec.addr; - for (i=0; i < srec.size; i++) - *pMem++ = srec.data[i]; - - break; - - case srec_eob: - sputs("done\n\n"); - img_hdr.magic = MAGIC_EB; - img_hdr.target_base = srec.addr; - img_hdr.img_size = haddr - srec.addr; - img_hdr.img_base = flash_offset + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = flash_get_offset_blockaligned(&flash, img_hdr.img_base + img_hdr.img_size); - sputs("Size of application : ");print_word(img_hdr.img_size); sputs("\n"); - sputs("Programming flash at : ");print_word(flash_offset); sputs("\n"); - sputs("Next free flash offset : ");print_word(img_hdr.hdr_next); sputs("\n"); - - sputs("Flash erase..."); - result = flash_erase(&flash, flash_offset, img_hdr.img_size + sizeof(flash_img_hdr_t)); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("done\n"); - - sputs("Flash write..."); - result = flash_program(&flash, flash_offset, (UINT8*)&img_hdr, sizeof(flash_img_hdr_t)); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - result = flash_program(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("done\n"); - - sputs("Flash verify..."); - result = flash_verify(&flash, img_hdr.img_base, (UINT8*)img_hdr.target_base, img_hdr.img_size); - if (IS_ERROR(result)) - { - sputs("failed (");print_word(result);sputs(")\n"); - break; - } - sputs("passed\n"); - - // Jump to reset vector - Jump_to((void*)0xBFC00000); - - break; - - default: - result = -1; - break; - } - if (IS_ERROR(result)) - { - *pReg = 0x40000000; - break; - } - - }; - } - } - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S deleted file mode 100644 index 84a8d9d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/init_boot.S +++ /dev/null @@ -1,19 +0,0 @@ - .file "init.S" - - .text - .section .init,"ax" - .align 2 - .globl _init - .extern end - -_init: - .set noreorder - - # set uart - la $26, sys_uart_baud - addiu $27, $0, baudrate - sw $27, 0($26) - - jr $ra - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S deleted file mode 100644 index b4a8694..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/kernel_boot.S +++ /dev/null @@ -1,46 +0,0 @@ - .file "kernel.S" - - .section .ktext,"ax" - .align 2 - - .macro kpush reg - addiu $sp, 4 - sw \reg, 0($sp) - .endm - - .macro kpop reg - lw \reg, 0($sp) - addiu $sp, -4 - .endm - -_exc_handler: - - .set noreorder - - # Set Error LED and ExcCode LEDs - # Get Cause - mfc0 $26, $13 - li $27, 0xC0000000 - srl $26, 2 - andi $26, 0x000F - or $26, $27 - la $27, sys_led_port - sw $26, 0($27) - - # wait for all interrupts = 0 -$w4x: mfc0 $26, $13 - nop - srl $26, 8 - andi $26, 0xFF - bnez $26, $w4x - nop - - # Get return address - mfc0 $26, $14 - - # Return - nop - jr $26 - rfe - .set reorder - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c deleted file mode 100644 index cf3ef5e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.c +++ /dev/null @@ -1,214 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include "libsys_boot.h" - -// --------------------------------------------------------------------------------- -// MIPS specific -UINT32 CP0_SR_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $12\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_SR_write(UINT32 val) -{ - __asm - ( - "mtc0 %[val], $12\n" - : /* no output */ - : [val] "r" (val) - ); -} - -UINT32 CP0_CR_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $13\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_CR_write(UINT32 val) -{ - __asm - ( - "mtc0 %[val], $13\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_PRID_read(void) -{ - UINT32 result; - - __asm - ( - "mfc0 %[val], $15\n" - : [val] "=r" (result) - ); - - return result; -} - -// --------------------------------------------------------------------------------- -char readchar(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart_data; - - while(!(0x10 & *pUART_stat)); - - return (char)*pUART_data; -} - -void writechar(char c) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart_data; - - while((0x02 & *pUART_stat) != 0); - - *pUART_data = (UINT32)c; -} - -void _putchar(char c) -{ - if (c == 0x0A) - { - writechar(0x0D); - } - writechar(c); -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - _putchar(*(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - _putchar(c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - -// --------------------------------------------------------------------------------- -// PrintBuffer8() -// Prints byte buffer as hex and ascii interpretation -// --------------------------------------------------------------------------------- -// _Parameters : -// pBuf: : IN: Buffer to display -// nbpr : Number of bytes per row to display -// len : Length of input buffer -// _Return: none -// -// --------------------------------------------------------------------------- -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len) -{ - memdump(pBuf, 1, nbpr, len); -} - -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len) -{ - int i, j, cnt_hex, cnt_asc, base; - unsigned char c; - - i = j = 0; - cnt_hex = len; - cnt_asc = len; - base = 0; - if (!print_offset_only) - base = (int)pBuf; - - do - { - print_word(base + i); - sputs(": "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_hex) - { - print_byte(pBuf[i+j]); - sputs(" "); - cnt_hex--; - } - else - { - sputs(" "); - break; - } - - } - - sputs(" "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_asc) - { - c = pBuf[i+j]; - if((c < 0x20) || (c > 0x7F)) - c = '.'; - - _putchar(c); - cnt_asc--; - } - else - { - sputs(" "); - break; - } - } - sputs("\n"); - i += num_bytes_per_row; - - } while (cnt_hex); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h b/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h deleted file mode 100644 index c5645cc..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/libsys_boot.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef LIBSYS_H -#define LIBSYS_H - -// --------------------------------------------------------- -// Types -// --------------------------------------------------------- -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define IS_ERROR(e) ((e & 0x80000000) == 0x80000000) - -#define sys_gpio0 0xA0000000 -#define sys_gpio1 0xA0000004 -#define sys_led_port sys_gpio0 -#define sys_usb_ctrl sys_gpio1 -#define sys_timer_usec 0xA0000008 -#define sys_timer_sec 0xA000000C -#define sys_uart_data 0xA0010000 -#define sys_uart_stat 0xA0010004 -#define sys_uart_baud 0xA0010008 -#define sys_usb_data 0xA0020000 -#define sys_usb_mbx 0xA0020004 -#define sys_usb_addr 0xA0020008 -#define sys_usb_status 0xA002000C -#define sys_flash_io 0xA4000000 -#define sys_flash_mem 0x00000000 - -// MIPS specific -UINT32 CP0_SR_read(void); -void CP0_SR_write(UINT32 val); -UINT32 CP0_CR_read(void); -void CP0_CR_write(UINT32 val); -UINT32 CP0_PRID_read(void); - -// General -char readchar(void); -void writechar(char c); -int write(int file, char *ptr, int len); -int sputs(char *pStr); -void print_byte(char byte); -void print_word(int word); -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len); -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len); - -#endif // LIBSYS_H - diff --git a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S b/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S deleted file mode 100644 index 8da9ee0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/bootloader/startup_boot.S +++ /dev/null @@ -1,43 +0,0 @@ - .file "startup.S" - - .text - .section .init,"ax" - .extern _init - .align 2 - -_start: - .set noreorder - - # set stack pointer - la $sp, stack_ptr - - # Set Kernel mode - li $26, 0x1040000C - mtc0 $26, $12 - li $26, 0x00000000 - mtc0 $26, $13 - - mfc0 $26, $15 - nop - mtc0 $26, $31 - - # Invalidate I-Cache - cop0 32 - - # Invalidate D-Cache - cop0 34 - - # jump init - la $26, _init - jalr $26 - nop - - la $26, main - jalr $26 - nop -_terminate: - nop - j _terminate - nop - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.c b/lib/CPUs/MIPS/bsp/examples/cfiflash.c deleted file mode 100644 index bbfbe43..0000000 --- a/lib/CPUs/MIPS/bsp/examples/cfiflash.c +++ /dev/null @@ -1,415 +0,0 @@ -#include -#include -#include "libsys.h" -#include "cfiflash.h" - -UINT32 cfi_get_status(flash_t *pObj) -{ - volatile UINT32 *pF; - UINT32 status; - - pF = (UINT32*)pObj->pBase; - - *pF = 0x00700070; - - status = *pF; - - *pF = 0x00FF00FF; - - return status; - -} - -void cfi_init(flash_t *pObj, UINT32 base_addr) -{ - int i; - UINT8 *pInfo; - UINT32 endian; - UINT8 *pEndian; - - pObj->pBase = (void*)base_addr; - - pInfo = (UINT8*)&pObj->info; - for (i=0; i < sizeof(flash_info_t); i++) - { - pInfo[i] = 0; - } - pObj->eb = 0; - endian = 0x12345678; - pEndian = (UINT8*)&endian; - if (*pEndian == 0x12) - { - pObj->eb = 1; - } - -} - -UINT32 cfi_find(flash_t *pObj) -{ - int i; - volatile UINT32 *pF; - volatile UINT16 *pF16; -// UINT8 qry_ref[12] = {0x51, 0x00, 0x51, 0x00, 0x52, 0x00, 0x52, 0x00, 0x59, 0x00, 0x59, 0x00}; - UINT32 size; - - pF = (UINT32*)pObj->pBase; - pF16 = (UINT16*)pObj->pBase; - - // Look for flash - *pF = 0x00980098; -// for (i=0; i < sizeof(qry_ref); i++) -// if (((UINT8*)(&pF[0x10]))[i] != qry_ref[i]) -// return (UINT32)-1; - - *pF = 0x00FF00FF; - *pF = 0x00900090; - -/* - printf("ManID : %8.8X\n", (UINT32)pF[0]); - printf("Device code : %8.8X\n", (UINT32)pF[1]); - printf("Block info : %8.8X\n", (UINT32)pF[2]); - - printf("VCC(min) : %8.8X\n", (UINT32)pF[0x1B]); - printf("VCC(max) : %8.8X\n", (UINT32)pF[0x1C]); - printf("VPP(min) : %8.8X\n", (UINT32)pF[0x1D]); - printf("VPP(max) : %8.8X\n", (UINT32)pF[0x1E]); - printf("Device Layout : %8.8X\n", (UINT32)pF[0x27]); - printf("Interface type : %8.8X %8.8X\n", (UINT32)pF[0x28], (UINT32)pF[0x29]); - printf("Write buffer size : %8.8X %8.8X\n", (UINT32)pF[0x2A], (UINT32)pF[0x2B]); - printf("Num. erase blocks : %8.8X\n", (UINT32)pF[0x2C]); - printf("Erase block info : %8.8X %8.8X %8.8X %8.8X\n", (UINT32)pF[0x2D], (UINT32)pF[0x2E], (UINT32)pF[0x2F], (UINT32)pF[0x30]); -*/ - pObj->info.num_flash = 2; - pObj->info.if_width = 32; - size = (UINT32)pF16[2*0x27]; - pObj->info.flashsize = pObj->info.num_flash; - for (i=0; i < size; i++) - pObj->info.flashsize *= 2; - - size = (UINT32)(pF16[2*0x2B] << 8 | pF16[2*0x2A]); - pObj->info.wbuf_size = pObj->info.num_flash; - for (i=0; i < size; i++) - pObj->info.wbuf_size *= 2; - - pObj->info.nblocks = (UINT32)(pF16[2*0x2E] << 8 | pF16[2*0x2D]) + 1; - pObj->info.blocksize = pObj->info.num_flash * ((UINT32)(pF16[2*0x30] << 8 | pF16[2*0x2F]) * 256); - - *pF = 0x00FF00FF; - - return 0; -} - -UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - *pF = 0x00900090; - - error = ((UINT32)pF[block_index+2] & 0x00010001) != 0; - *pF = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00200020; - pF[block_index] = 0x00D000D0; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_ECLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00600060; - pF[block_index] = 0x00010001; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index) -{ - volatile UINT32 *pF; - UINT32 status, block_index, block_mask; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - block_index = word_index & block_mask; - - pF[block_index] = 0x00600060; - pF[block_index] = 0x00D000D0; - - error = 0; - do - { - status = pF[block_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_ECLBS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[block_index] = 0x00FF00FF; - - return error; -} - -UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word) -{ - volatile UINT32 *pF; - UINT32 status, error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - pF[word_index] = 0x00400040; - pF[word_index] = word; - - error = 0; - do - { - status = pF[word_index]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - } - - pF[word_index] = 0x00FF00FF; - - return error; - -} - -UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words) -{ - int i, j, k; - volatile UINT32 *pF; - UINT32 status, bcurr, bnext, block_mask, nblock_write, nbuf_write; - UINT32 error; - - pF = (UINT32*)pObj->pBase; - - if (word_index >= (pObj->info.flashsize/4)) - return CFI_ERR_INVPARAM; - - block_mask = ((pObj->info.nblocks-1) << 16); - - k = 0; - while(num_words) - { - - bcurr = word_index & block_mask; - bnext = bcurr + (1 << 16); - nblock_write = bnext - word_index; - if (nblock_write > num_words) - nblock_write = num_words; - - while(nblock_write) - { - error = 0; - pF[bcurr] = 0x00E800E8; - do - { - status = pF[bcurr]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - break; - } - - nbuf_write = nblock_write; - if (nblock_write > pObj->info.wbuf_size/4) - nbuf_write = pObj->info.wbuf_size/4; - - pF[bcurr] = (nbuf_write-1) << 16 | (nbuf_write-1); - - for (j=0; j < nbuf_write; j++) - pF[word_index+j] = pWords[k++]; - - word_index += j; - nblock_write -= j; - num_words -= j; - - error = 0; - pF[bcurr] = 0x00D000D0; - do - { - status = pF[bcurr]; - - } while((status & SR_BIT_ISMS) != SR_BIT_ISMS); - if (status & (SR_BIT_PSLBS | SR_BIT_VPENS | SR_BIT_DPS)) - { - error = CFI_ERR_DEV_FAIL | status; - break; - } - - pF[bcurr] = 0x00FF00FF; - } - - if (IS_ERROR(error)) - { - pF[bcurr] = 0x00FF00FF; - break; - } - bcurr = bnext; - } - - return error; - -} - -UINT32 flash_find(flash_t *pObj, UINT32 base_addr) -{ - cfi_init(pObj, base_addr); - return cfi_find(pObj); -} - -UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size) -{ - int i; - UINT32 offset_end, error; - - if (size % 4) - size = 4*(size/4 + 1); - - offset_end = offset + size; - - for (i=offset; i < offset_end; i += pObj->info.blocksize) - { - if (cfi_block_is_locked(pObj, i/4)) - { - error = cfi_block_unlock(pObj, i/4); - if (IS_ERROR(error)) - break; - } - error = cfi_block_erase(pObj, i/4); - if (IS_ERROR(error)) - break; - } - - return error; - -} - -UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size) -{ - if (size % 4) - size = 4*(size/4 + 1); - - return cfi_program_multi(pObj, offset/4, (UINT32*)pData, size/4); -} - -UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size) -{ - int i; - UINT8 *pF; - - pF = (UINT8*)(pObj->pBase + offset); - - for (i=0; i < size; i++) - if (pF[i] != pData[i]) - return CFI_ERR_VFY_FAIL; - - return 0; -} - -UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset) -{ - UINT32 blocknum; - - blocknum = offset/pObj->info.blocksize; - if (offset%pObj->info.blocksize) - blocknum++; - - return blocknum; -} - -UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum) -{ - if (blocknum >= pObj->info.nblocks) - blocknum = pObj->info.nblocks - 1; - - return blocknum*pObj->info.blocksize; -} - -UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset) -{ - return flash_get_blocknum_by_offset(pObj, offset) * pObj->info.blocksize; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/cfiflash.h b/lib/CPUs/MIPS/bsp/examples/cfiflash.h deleted file mode 100644 index 1233642..0000000 --- a/lib/CPUs/MIPS/bsp/examples/cfiflash.h +++ /dev/null @@ -1,58 +0,0 @@ -/************************************************************************/ -#ifndef CFIFLASH_H -#define CFIFLASH_H - -#include "libsys.h" - -#define SR_BIT_DPS 0x00020002 -#define SR_BIT_PSS 0x00040004 -#define SR_BIT_VPENS 0x00080008 -#define SR_BIT_PSLBS 0x00100010 -#define SR_BIT_ECLBS 0x00200020 -#define SR_BIT_ESS 0x00400040 -#define SR_BIT_ISMS 0x00800080 - -#define CFI_ERR_BASE (LSYS_ERR_BASE + 0x00100000) -#define CFI_ERR_GENERAL (CFI_ERR_BASE + 0) -#define CFI_ERR_NOTFOUND (CFI_ERR_BASE + 1) -#define CFI_ERR_INVPARAM (CFI_ERR_BASE + 2) -#define CFI_ERR_VFY_FAIL (CFI_ERR_BASE + 3) -#define CFI_ERR_DEV_FAIL (CFI_ERR_BASE + 0x10000000) - -typedef struct _sflash_info_t -{ - UINT32 flashsize; - UINT32 blocksize; - UINT32 nblocks; - UINT32 wbuf_size; - UINT32 if_width; - UINT32 num_flash; - -} flash_info_t; - -typedef struct _sflash_t -{ - void *pBase; - UINT32 eb; - flash_info_t info; - -} flash_t; - -void cfi_init(flash_t *pObj, UINT32 base_addr); -UINT32 cfi_find(flash_t *pObj); -UINT32 cfi_block_is_locked(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_erase(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_lock(flash_t *pObj, UINT32 word_index); -UINT32 cfi_block_unlock(flash_t *pObj, UINT32 word_index); -UINT32 cfi_program_single(flash_t *pObj, UINT32 word_index, UINT32 word); -UINT32 cfi_program_multi(flash_t *pObj, UINT32 word_index, UINT32 *pWords, UINT32 num_words); - -UINT32 flash_get_offset_by_blocknum(flash_t *pObj, UINT32 blocknum); -UINT32 flash_get_blocknum_by_offset(flash_t *pObj, UINT32 offset); -UINT32 flash_get_offset_blockaligned(flash_t *pObj, UINT32 offset); -UINT32 flash_find(flash_t *pObj, UINT32 base_addr); -UINT32 flash_erase(flash_t *pObj, UINT32 offset, UINT32 size); -UINT32 flash_program(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size); -UINT32 flash_verify(flash_t *pObj, UINT32 offset, UINT8 *pData, UINT32 size); - -#endif // CFIFLASH_H diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.c b/lib/CPUs/MIPS/bsp/examples/crc32.c deleted file mode 100644 index 6f63429..0000000 --- a/lib/CPUs/MIPS/bsp/examples/crc32.c +++ /dev/null @@ -1,54 +0,0 @@ -#include - -unsigned long MakeCRC32(char *data, unsigned int len, unsigned int CRC) -{ - /* ======================================================================== - * Table of CRC-32's of all single-byte values (made by makecrc.c) - */ - unsigned long crc_32_tab[] = { - 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, 0x706af48fL, 0xe963a535L, 0x9e6495a3L, - 0x0edb8832L, 0x79dcb8a4L, 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, 0x90bf1d91L, - 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, - 0x136c9856L, 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, 0xfa0f3d63L, 0x8d080df5L, - 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, - 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, - 0x26d930acL, 0x51de003aL, 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, 0xb8bda50fL, - 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, - 0x76dc4190L, 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, 0x9fbfe4a5L, 0xe8b8d433L, - 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, - 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, - 0x65b0d9c6L, 0x12b7e950L, 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, 0xfbd44c65L, - 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, - 0x4369e96aL, 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, 0xaa0a4c5fL, 0xdd0d7cc9L, - 0x5005713cL, 0x270241aaL, 0xbe0b1010L, 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, - 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, - 0xedb88320L, 0x9abfb3b6L, 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, 0x73dc1683L, - 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, - 0xf00f9344L, 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, 0x196c3671L, 0x6e6b06e7L, - 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, - 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, - 0xd80d2bdaL, 0xaf0a1b4cL, 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, 0x4669be79L, - 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, - 0xc5ba3bbeL, 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, 0x2cd99e8bL, 0x5bdeae1dL, - 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, - 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, - 0x86d3d2d4L, 0xf1d4e242L, 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, 0x18b74777L, - 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, - 0xa00ae278L, 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, 0x4969474dL, 0x3e6e77dbL, - 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, - 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, 0xcdd70693L, 0x54de5729L, 0x23d967bfL, - 0xb3667a2eL, 0xc4614ab8L, 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, 0x2d02ef8dL - }; - - if (data == NULL) - return 0; - - CRC = ~CRC; - while (len --) - { - CRC = crc_32_tab[((unsigned char) CRC ^ *data) & 0xFF] ^ (CRC >> 8); - data ++; - } - - return ~CRC; -} diff --git a/lib/CPUs/MIPS/bsp/examples/crc32.h b/lib/CPUs/MIPS/bsp/examples/crc32.h deleted file mode 100644 index 04687b0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/crc32.h +++ /dev/null @@ -1,13 +0,0 @@ -// CRC32 function -// To create a CRC from a new buffer, use this: -// crc = MakeCRC32(mydata, data_len, 0); -// If you need to continue the CRC (e.g. your data is in multiple buffers), -// continue like this: -// crc = MakeCRC32(moredata, more_len, crc); -// -// Your desired CRC should be the complement of the CRC generated by -// MakeCRC32: -// desired = crc -// desired - crc = 0 - -unsigned long MakeCRC32(char *data, unsigned int len, unsigned long CRC); diff --git a/lib/CPUs/MIPS/bsp/examples/dbg.c b/lib/CPUs/MIPS/bsp/examples/dbg.c deleted file mode 100644 index 5f038e9..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dbg.c +++ /dev/null @@ -1,341 +0,0 @@ -#include -#include -#include -#include "irq.h" -#include "libsys.h" -#include "mipsdis.h" - -#define MAX_USER_BP 16 -#define BP_MASK_ID 0x00FFF -#define BP_MASK_TYPE 0xFF000 - -#define BP_GET_ID(bp) ((bp >> 6) & 0xFFF) - -#define BP_USER_BASE 0x10000 -#define BP_USER(id) (((BP_USER_BASE + id) << 6) | 0x0D) - -#define BP_MGMT_BASE_SS 0x20000 -#define BP_MGMT_SS(id) (((BP_MGMT_BASE_SS + id) << 6) | 0x0D) - -#define BP_MGMT_BASE_RU 0x30000 -#define BP_MGMT_RU(id) (((BP_MGMT_BASE_RU + id) << 6) | 0x0D) - -static char g_buf[80]; - -typedef struct _sbp_t -{ - UINT32 *pAddr; - UINT32 instr; -} bp_t; - -static bp_t user_bp[MAX_USER_BP]; -static bp_t mgmt_bp_ss[2]; -static bp_t mgmt_bp_ru[2]; -static int g_is_ss; -static int g_bp_index; - -int IsBreak(UINT32 instr) -{ - return ((instr & 0xFC00003F) == 0x0000000D); -} - -UINT32 BreakGetType(UINT32 instr) -{ - return (instr >> 6) & BP_MASK_TYPE; -} - -void dbg_handler(struct xcptcontext * xcp) -{ - - UINT32 bp_addr, bp_index = 0, branch_addr, reg, result, bp_type; - int junk, i, leave_isr, is_branch_shadow, is_user_bp; - UINT32 volatile *pBtn = (UINT32*)sys_gpio0; - UINT32 *pInstr, *pAddr_curr, *pAddr_prev, *pAddr_next; - - sputs("\n"); - PRINT_REG(" Status : ", xcp->sr); - PRINT_REG(" Cause : ", xcp->cr); - PRINT_REG(" EPC : ", xcp->epc); - PRINT_REG("BadAddr : ", xcp->baddr); - sputs("\n"); - PRINT_REG(" MDLO : ", xcp->mdlo); - PRINT_REG(" MDHI : ", xcp->mdhi); - - sputs("\n"); - - sputs("Registers:\n"); - PRINT_REG(" 0 (ze) : ", xcp->regs[0]); - PRINT_REG(" 1 (at) : ", xcp->regs[1]); - PRINT_REG(" 2 (v0) : ", xcp->regs[2]); - PRINT_REG(" 3 (v1) : ", xcp->regs[3]); - sputs("\n"); - PRINT_REG(" 4 (a0) : ", xcp->regs[4]); - PRINT_REG(" 5 (a1) : ", xcp->regs[5]); - PRINT_REG(" 6 (a2) : ", xcp->regs[6]); - PRINT_REG(" 7 (a3) : ", xcp->regs[7]); - sputs("\n"); - PRINT_REG(" 8 (t0) : ", xcp->regs[8]); - PRINT_REG(" 9 (t1) : ", xcp->regs[9]); - PRINT_REG("10 (t2) : ", xcp->regs[10]); - PRINT_REG("11 (t3) : ", xcp->regs[11]); - sputs("\n"); - PRINT_REG("12 (t4) : ", xcp->regs[12]); - PRINT_REG("13 (t5) : ", xcp->regs[13]); - PRINT_REG("14 (t6) : ", xcp->regs[14]); - PRINT_REG("15 (t7) : ", xcp->regs[15]); - sputs("\n"); - PRINT_REG("16 (s0) : ", xcp->regs[16]); - PRINT_REG("17 (s1) : ", xcp->regs[17]); - PRINT_REG("18 (s2) : ", xcp->regs[18]); - PRINT_REG("19 (s3) : ", xcp->regs[19]); - sputs("\n"); - PRINT_REG("20 (s4) : ", xcp->regs[20]); - PRINT_REG("21 (s5) : ", xcp->regs[21]); - PRINT_REG("22 (s6) : ", xcp->regs[22]); - PRINT_REG("23 (s7) : ", xcp->regs[23]); - sputs("\n"); - PRINT_REG("24 (t8) : ", xcp->regs[24]); - PRINT_REG("25 (t9) : ", xcp->regs[25]); - PRINT_REG("26 (k0) : ", xcp->regs[26]); - PRINT_REG("27 (k1) : ", xcp->regs[27]); - sputs("\n"); - PRINT_REG("28 (gp) : ", xcp->regs[28]); - PRINT_REG("29 (sp) : ", xcp->regs[29]); - PRINT_REG("30 (fp) : ", xcp->regs[30]); - PRINT_REG("31 (ra) : ", xcp->regs[31]); - sputs("\n"); - sputs("\n"); - - is_user_bp = 0; - pAddr_curr = (UINT32*)xcp->epc; - is_branch_shadow = ((xcp->cr & 0x80000000) == 0x80000000); - if (is_branch_shadow) - pAddr_curr++; - - pAddr_prev = pAddr_curr - 1; - pAddr_next = pAddr_curr + 1; - - if (IsBreak(*pAddr_curr)) - { - bp_type = BreakGetType(*pAddr_curr); - - switch (bp_type) - { - case BP_MGMT_BASE_SS: - - // Restore original instructions after single-step - sputs("1. Restore after single-step at ");print_word((long)mgmt_bp_ss[0].pAddr);sputs("\n"); - *(mgmt_bp_ss[0].pAddr) = mgmt_bp_ss[0].instr; - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - if (mgmt_bp_ss[1].pAddr) - { - sputs("2. Restore after single-step at ");print_word((long)mgmt_bp_ss[1].pAddr);sputs("\n"); - *(mgmt_bp_ss[1].pAddr) = mgmt_bp_ss[1].instr; - ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr); - } - - break; - - case BP_MGMT_BASE_RU: - - bp_index = BP_GET_ID(*pAddr_curr); - sputs("Restore user break at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n"); - - *(user_bp[bp_index].pAddr) = BP_USER(bp_index); - ICACHE_invalidate_at(user_bp[bp_index].pAddr); - - *(mgmt_bp_ru[0].pAddr) = mgmt_bp_ru[0].instr; - ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr); - sputs("1. Restore after RU at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n"); - if (mgmt_bp_ru[1].pAddr) - { - *(mgmt_bp_ru[1].pAddr) = mgmt_bp_ru[1].instr; - ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr); - sputs("2. Restore after RU at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n"); - } - if (!g_is_ss) - return; - - break; - - case BP_USER_BASE: - - is_user_bp = 1; - bp_index = BP_GET_ID(*pAddr_curr); - sputs("Restore instruction at ");print_word((long)user_bp[bp_index].pAddr);sputs("\n"); - *(user_bp[bp_index].pAddr) = user_bp[bp_index].instr; - ICACHE_invalidate_at(user_bp[bp_index].pAddr); - break; - - default: - break; - - } - } - - pInstr = pAddr_prev; - // Disassemble instructions - for (i=0; i < 3; i++) - { - print_word((long)pInstr); - if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE)) - { - tdisasm(g_buf, (long)user_bp[BP_GET_ID(*pInstr)].pAddr, user_bp[BP_GET_ID(*pInstr)].instr, 0, &junk, &junk, &junk); - sputs(": b "); - } - else - { - tdisasm(g_buf, (long)pInstr, *pInstr, 0, &junk, &junk, &junk); - if (pInstr == pAddr_curr) - if (is_user_bp == 1) - sputs(": b-> "); - else - sputs(": -> "); - else - sputs(": "); - } - sputs(g_buf); - sputs("\n"); - pInstr++; - } - - if (is_user_bp) - { - // Save original instruction - mgmt_bp_ru[0].pAddr = pAddr_next; - mgmt_bp_ru[0].instr = *(mgmt_bp_ru[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ru[0].pAddr) = BP_MGMT_RU(bp_index); - ICACHE_invalidate_at(mgmt_bp_ru[0].pAddr); - mgmt_bp_ru[1].pAddr = NULL; - mgmt_bp_ru[1].pAddr = 0; - sputs("1. Insert RU-break at ");print_word((long)mgmt_bp_ru[0].pAddr);sputs("\n"); - - // We have two possible management breaks, if previous instruction was branch or jump - if (is_branch_shadow) - { - result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, ®); - // Is jump target stored in register - if (result == 3) - { - branch_addr = xcp->regs[reg&0x1F]; - } - // Save original instruction - mgmt_bp_ru[1].pAddr = (UINT32*)branch_addr; - mgmt_bp_ru[1].instr = *(mgmt_bp_ru[1].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ru[1].pAddr) = BP_MGMT_RU(bp_index); - ICACHE_invalidate_at(mgmt_bp_ru[1].pAddr); - sputs("2. Insert RU-break at ");print_word((long)mgmt_bp_ru[1].pAddr);sputs("\n"); - } - } - - do - { - leave_isr = 0; - switch(readchar()) - { - case 'g': - leave_isr = 1; - g_is_ss = 0; - break; - - case 'b': - printf("Enter breakpoint: "); - scanf("%x", &bp_addr); - printf("Insert breakpoint at %.8X\n", bp_addr); - user_bp[g_bp_index].pAddr = (UINT32*)bp_addr; - user_bp[g_bp_index].instr = *(user_bp[g_bp_index].pAddr); - *(user_bp[g_bp_index].pAddr) = BP_USER(g_bp_index); - - tdisasm(g_buf, (long)user_bp[g_bp_index].pAddr, user_bp[g_bp_index].instr, 0, &junk, &junk, &junk); - print_word((long)user_bp[g_bp_index].pAddr);sputs(": b ");sputs(g_buf);sputs("\n"); - ICACHE_invalidate_at(user_bp[g_bp_index].pAddr); - g_bp_index++; - break; - - case 's': - g_is_ss = 1; - leave_isr = 1; - // Don't overwrite RU breaks - if (is_user_bp) - break; - // Don't overwrite user breaks - if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE)) - break; - - // Save original instruction - mgmt_bp_ss[0].pAddr = pAddr_next; - mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1); - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - mgmt_bp_ss[1].pAddr = NULL; - mgmt_bp_ss[1].pAddr = 0; - // We have two possible management breaks, if previous instruction was branch or jump - if (is_branch_shadow) - { - result = tdisasm(g_buf, (long)pAddr_prev, *pAddr_prev, 0, &junk, &branch_addr, ®); - // Is jump target stored in register - if (result == 3) - { - branch_addr = xcp->regs[reg&0x1F]; - } - // Save original instruction - mgmt_bp_ss[1].pAddr = (UINT32*)branch_addr; - mgmt_bp_ss[1].instr = *(mgmt_bp_ss[1].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[1].pAddr) = BP_MGMT_SS(2); - ICACHE_invalidate_at(mgmt_bp_ss[1].pAddr); - } - break; - - case 'P': - g_is_ss = 1; - leave_isr = 1; - // Don't overwrite RU breaks - if (is_user_bp) - break; - // Don't overwrite user breaks - if (IsBreak(*pInstr) && (BreakGetType(*pInstr) == BP_USER_BASE)) - break; - - // Save original instruction - mgmt_bp_ss[0].pAddr = (UINT32*)xcp->regs[0x1F]; - mgmt_bp_ss[0].instr = *(mgmt_bp_ss[0].pAddr); - // Replace instruction with managment breakpoint - *(mgmt_bp_ss[0].pAddr) = BP_MGMT_SS(1); - ICACHE_invalidate_at(mgmt_bp_ss[0].pAddr); - mgmt_bp_ss[1].pAddr = NULL; - mgmt_bp_ss[1].pAddr = 0; - break; - - default: - break; - } - } while (!leave_isr); - -} - -void debug_int(struct xcptcontext * xcp) -{ - dbg_handler(xcp); - -} - -int debug_break(struct xcptcontext * xcp) -{ - dbg_handler(xcp); - return 0; - -} - -void dbg_init(void) -{ - - interrupt_register(2, debug_int); - interrupt_enable(2); - - xcpt_register(Bp, debug_break); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/dhry.h b/lib/CPUs/MIPS/bsp/examples/dhry.h deleted file mode 100644 index c8d8f0a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry.h (part 1 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * Siemens AG, E STE 35 - * Postfach 3240 - * 8520 Erlangen - * Germany (West) - * Phone: [xxx-49]-9131-7-20330 - * (8-17 Central European Time) - * Usenet: ..!mcvax!unido!estevax!weicker - * - * Original Version (in Ada) published in - * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), - * pp. 1013 - 1030, together with the statistics - * on which the distribution of statements etc. is based. - * - * In this C version, the following C library functions are used: - * - strcpy, strcmp (inside the measurement loop) - * - printf, scanf (outside the measurement loop) - * In addition, Berkeley UNIX system calls "times ()" or "time ()" - * are used for execution time measurement. For measurements - * on other systems, these calls have to be changed. - * - * Collection of Results: - * Reinhold Weicker (address see above) and - * - * Rick Richardson - * PC Research. Inc. - * 94 Apple Orchard Drive - * Tinton Falls, NJ 07724 - * Phone: (201) 389-8963 (9-17 EST) - * Usenet: ...!uunet!pcrat!rick - * - * Please send results to Rick Richardson and/or Reinhold Weicker. - * Complete information should be given on hardware and software used. - * Hardware information includes: Machine type, CPU, type and size - * of caches; for microprocessors: clock frequency, memory speed - * (number of wait states). - * Software information includes: Compiler (and runtime library) - * manufacturer and version, compilation switches, OS version. - * The Operating System version may give an indication about the - * compiler; Dhrystone itself performs no OS calls in the measurement loop. - * - * The complete output generated by the program should be mailed - * such that at least some checks for correctness can be made. - * - *************************************************************************** - * - * History: This version C/2.1 has been made for two reasons: - * - * 1) There is an obvious need for a common C version of - * Dhrystone, since C is at present the most popular system - * programming language for the class of processors - * (microcomputers, minicomputers) where Dhrystone is used most. - * There should be, as far as possible, only one C version of - * Dhrystone such that results can be compared without - * restrictions. In the past, the C versions distributed - * by Rick Richardson (Version 1.1) and by Reinhold Weicker - * had small (though not significant) differences. - * - * 2) As far as it is possible without changes to the Dhrystone - * statistics, optimizing compilers should be prevented from - * removing significant statements. - * - * This C version has been developed in cooperation with - * Rick Richardson (Tinton Falls, NJ), it incorporates many - * ideas from the "Version 1.1" distributed previously by - * him over the UNIX network Usenet. - * I also thank Chaim Benedelac (National Semiconductor), - * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), - * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) - * for their help with comments on earlier versions of the - * benchmark. - * - * Changes: In the initialization part, this version follows mostly - * Rick Richardson's version distributed via Usenet, not the - * version distributed earlier via floppy disk by Reinhold Weicker. - * As a concession to older compilers, names have been made - * unique within the first 8 characters. - * Inside the measurement loop, this version follows the - * version previously distributed by Reinhold Weicker. - * - * At several places in the benchmark, code has been added, - * but within the measurement loop only in branches that - * are not executed. The intention is that optimizing compilers - * should be prevented from moving code out of the measurement - * loop, or from removing code altogether. Since the statements - * that are executed within the measurement loop have NOT been - * changed, the numbers defining the "Dhrystone distribution" - * (distribution of statements, operand types and locality) - * still hold. Except for sophisticated optimizing compilers, - * execution times for this version should be the same as - * for previous versions. - * - * Since it has proven difficult to subtract the time for the - * measurement loop overhead in a correct way, the loop check - * has been made a part of the benchmark. This does have - * an impact - though a very minor one - on the distribution - * statistics which have been updated for this version. - * - * All changes within the measurement loop are described - * and discussed in the companion paper "Rationale for - * Dhrystone version 2". - * - * Because of the self-imposed limitation that the order and - * distribution of the executed statements should not be - * changed, there are still cases where optimizing compilers - * may not generate code for some statements. To a certain - * degree, this is unavoidable for small synthetic benchmarks. - * Users of the benchmark are advised to check code listings - * whether code is generated for all statements of Dhrystone. - * - * Version 2.1 is identical to version 2.0 distributed via - * the UNIX network Usenet in March 1988 except that it corrects - * some minor deficiencies that were found by users of version 2.0. - * The only change within the measurement loop is that a - * non-executed "else" part was added to the "if" statement in - * Func_3, and a non-executed "else" part removed from Proc_3. - * - *************************************************************************** - * - * Defines: The following "Defines" are possible: - * -DREG=register (default: Not defined) - * As an approximation to what an average C programmer - * might do, the "register" storage class is applied - * (if enabled by -DREG=register) - * - for local variables, if they are used (dynamically) - * five or more times - * - for parameters if they are used (dynamically) - * six or more times - * Note that an optimal "register" strategy is - * compiler-dependent, and that "register" declarations - * do not necessarily lead to faster execution. - * -DNOSTRUCTASSIGN (default: Not defined) - * Define if the C compiler does not support - * assignment of structures. - * -DNOENUMS (default: Not defined) - * Define if the C compiler does not support - * enumeration types. - * -DTIMES (default) - * -DTIME - * The "times" function of UNIX (returning process times) - * or the "time" function (returning wallclock time) - * is used for measurement. - * For single user machines, "time ()" is adequate. For - * multi-user machines where you cannot get single-user - * access, use the "times ()" function. If you have - * neither, use a stopwatch in the dead of night. - * "printf"s are provided marking the points "Start Timer" - * and "Stop Timer". DO NOT use the UNIX "time(1)" - * command, as this will measure the total time to - * run this program, which will (erroneously) include - * the time to allocate storage (malloc) and to perform - * the initialization. - * -DHZ=nnn - * In Berkeley UNIX, the function "times" returns process - * time in 1/HZ seconds, with HZ = 60 for most systems. - * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY - * A VALUE. - * - *************************************************************************** - * - * Compilation model and measurement (IMPORTANT): - * - * This C version of Dhrystone consists of three files: - * - dhry.h (this file, containing global definitions and comments) - * - dhry_1.c (containing the code corresponding to Ada package Pack_1) - * - dhry_2.c (containing the code corresponding to Ada package Pack_2) - * - * The following "ground rules" apply for measurements: - * - Separate compilation - * - No procedure merging - * - Otherwise, compiler optimizations are allowed but should be indicated - * - Default results are those without register declarations - * See the companion paper "Rationale for Dhrystone Version 2" for a more - * detailed discussion of these ground rules. - * - * For 16-Bit processors (e.g. 80186, 80286), times for all compilation - * models ("small", "medium", "large" etc.) should be given if possible, - * together with a definition of these models for the compiler system used. - * - ************************************************************************** - * - * Dhrystone (C version) statistics: - * - * [Comment from the first distribution, updated for version 2. - * Note that because of language differences, the numbers are slightly - * different from the Ada version.] - * - * The following program contains statements of a high level programming - * language (here: C) in a distribution considered representative: - * - * assignments 52 (51.0 %) - * control statements 33 (32.4 %) - * procedure, function calls 17 (16.7 %) - * - * 103 statements are dynamically executed. The program is balanced with - * respect to the three aspects: - * - * - statement type - * - operand type - * - operand locality - * operand global, local, parameter, or constant. - * - * The combination of these three aspects is balanced only approximately. - * - * 1. Statement Type: - * ----------------- number - * - * V1 = V2 9 - * (incl. V1 = F(..) - * V = Constant 12 - * Assignment, 7 - * with array element - * Assignment, 6 - * with record component - * -- - * 34 34 - * - * X = Y +|-|"&&"|"|" Z 5 - * X = Y +|-|"==" Constant 6 - * X = X +|- 1 3 - * X = Y *|/ Z 2 - * X = Expression, 1 - * two operators - * X = Expression, 1 - * three operators - * -- - * 18 18 - * - * if .... 14 - * with "else" 7 - * without "else" 7 - * executed 3 - * not executed 4 - * for ... 7 | counted every time - * while ... 4 | the loop condition - * do ... while 1 | is evaluated - * switch ... 1 - * break 1 - * declaration with 1 - * initialization - * -- - * 34 34 - * - * P (...) procedure call 11 - * user procedure 10 - * library procedure 1 - * X = F (...) - * function call 6 - * user function 5 - * library function 1 - * -- - * 17 17 - * --- - * 103 - * - * The average number of parameters in procedure or function calls - * is 1.82 (not counting the function values aX * - * - * 2. Operators - * ------------ - * number approximate - * percentage - * - * Arithmetic 32 50.8 - * - * + 21 33.3 - * - 7 11.1 - * * 3 4.8 - * / (int div) 1 1.6 - * - * Comparison 27 42.8 - * - * == 9 14.3 - * /= 4 6.3 - * > 1 1.6 - * < 3 4.8 - * >= 1 1.6 - * <= 9 14.3 - * - * Logic 4 6.3 - * - * && (AND-THEN) 1 1.6 - * | (OR) 1 1.6 - * ! (NOT) 2 3.2 - * - * -- ----- - * 63 100.1 - * - * - * 3. Operand Type (counted once per operand reference): - * --------------- - * number approximate - * percentage - * - * Integer 175 72.3 % - * Character 45 18.6 % - * Pointer 12 5.0 % - * String30 6 2.5 % - * Array 2 0.8 % - * Record 2 0.8 % - * --- ------- - * 242 100.0 % - * - * When there is an access path leading to the final operand (e.g. a record - * component), only the final data type on the access path is counted. - * - * - * 4. Operand Locality: - * ------------------- - * number approximate - * percentage - * - * local variable 114 47.1 % - * global variable 22 9.1 % - * parameter 45 18.6 % - * value 23 9.5 % - * reference 22 9.1 % - * function result 6 2.5 % - * constant 55 22.7 % - * --- ------- - * 242 100.0 % - * - * - * The program does not compute anything meaningful, but it is syntactically - * and semantically correct. All variables have a value assigned to them - * before they are used as a source operand. - * - * There has been no explicit effort to account for the effects of a - * cache, or to balance the use of long or short displacements for code or - * data. - * - *************************************************************************** - */ - -/* Compiler and system dependent definitions: */ - -#ifndef TIME -#undef TIMES -#define TIMES -#endif - /* Use times(2) time function unless */ - /* explicitly defined otherwise */ -#ifdef MSC_CLOCK -#undef HZ -#undef TIMES -#include -#define HZ CLK_TCK -#endif - /* Use Microsoft C hi-res clock */ - -#ifdef TIMES -#include -#include - /* for "times" */ -#endif - -#define Mic_secs_Per_Second 1000000.0 - /* Berkeley UNIX C returns process times in seconds/HZ */ - -#ifdef NOSTRUCTASSIGN -#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) -#else -#define structassign(d, s) d = s -#endif - -#ifdef NOENUM -#define Ident_1 0 -#define Ident_2 1 -#define Ident_3 2 -#define Ident_4 3 -#define Ident_5 4 - typedef int Enumeration; -#else - typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} - Enumeration; -#endif - /* for boolean and enumeration types in Ada, Pascal */ - -/* General definitions: */ - -#include - /* for strcpy, strcmp */ - -#define Null 0 - /* Value of a Null pointer */ -#define true 1 -#define false 0 - -typedef int One_Thirty; -typedef int One_Fifty; -typedef char Capital_Letter; -typedef int Boolean; -typedef char Str_30 [31]; -typedef int Arr_1_Dim [50]; -typedef int Arr_2_Dim [50] [50]; - -typedef struct record - { - struct record *Ptr_Comp; - Enumeration Discr; - union { - struct { - Enumeration Enum_Comp; - int Int_Comp; - char Str_Comp [31]; - } var_1; - struct { - Enumeration E_Comp_2; - char Str_2_Comp [31]; - } var_2; - struct { - char Ch_1_Comp; - char Ch_2_Comp; - } var_3; - } variant; - } Rec_Type, *Rec_Pointer; - - diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_1.c b/lib/CPUs/MIPS/bsp/examples/dhry_1.c deleted file mode 100644 index f7b8373..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry_1.c +++ /dev/null @@ -1,402 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_1.c (part 2 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#include "dhry.h" - -/* Global Variables: */ - -Rec_Pointer Ptr_Glob, - Next_Ptr_Glob; -int Int_Glob; -Boolean Bool_Glob; -char Ch_1_Glob, - Ch_2_Glob; -int Arr_1_Glob [50]; -int Arr_2_Glob [50] [50]; - -extern char *malloc (); -Enumeration Func_1 (); - /* forward declaration necessary since Enumeration may not simply be int */ - -#ifndef REG - Boolean Reg = false; -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#else - Boolean Reg = true; -#endif - -/* variables for time measurement: */ - -#ifdef TIMES -struct tms time_info; - /* see library function "times" */ -#define Too_Small_Time (2*HZ) - /* Measurements should last at least about 2 seconds */ -#endif -#ifdef TIME -extern long time(); - /* see library function "time" */ -#define Too_Small_Time 2 - /* Measurements should last at least 2 seconds */ -#endif -#ifdef MSC_CLOCK -extern clock_t clock(); -#define Too_Small_Time (2*HZ) -#endif - -long Begin_Time, - End_Time, - User_Time; -float Microseconds, - Dhrystones_Per_Second; - -/* end of variables for time measurement */ - - -main () -/*****/ - - /* main program, corresponds to procedures */ - /* Main and Proc_0 in the Ada version */ -{ - One_Fifty Int_1_Loc; - REG One_Fifty Int_2_Loc; - One_Fifty Int_3_Loc; - REG char Ch_Index; - Enumeration Enum_Loc; - Str_30 Str_1_Loc; - Str_30 Str_2_Loc; - REG int Run_Index; - REG int Number_Of_Runs; - - /* Initializations */ - - Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); - Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); - - Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; - Ptr_Glob->Discr = Ident_1; - Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; - Ptr_Glob->variant.var_1.Int_Comp = 40; - strcpy (Ptr_Glob->variant.var_1.Str_Comp, - "DHRYSTONE PROGRAM, SOME STRING"); - strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); - - Arr_2_Glob [8][7] = 10; - /* Was missing in published program. Without this statement, */ - /* Arr_2_Glob [8][7] would have an undefined value. */ - /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ - /* overflow may occur for this array element. */ - - /* - printf ("\n"); - printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); - printf ("\n"); - if (Reg) - { - printf ("Program compiled with 'register' attribute\n"); - printf ("\n"); - } - else - { - printf ("Program compiled without 'register' attribute\n"); - printf ("\n"); - } - printf ("Please give the number of runs through the benchmark: "); - { - int n; - scanf ("%d", &n); - Number_Of_Runs = n; - } - printf ("\n"); - */ -#ifdef NRUNS - Number_Of_Runs = NRUNS; -#else - Number_Of_Runs = 2000000; -#endif - printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); - - /***************/ - /* Start timer */ - /***************/ - -#ifdef TIMES - times (&time_info); - Begin_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - Begin_Time = time ( (long *) 0); -#endif -#ifdef MSC_CLOCK - Begin_Time = clock(); -#endif - - for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) - { - - Proc_5(); - Proc_4(); - /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ - Int_1_Loc = 2; - Int_2_Loc = 3; - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); - Enum_Loc = Ident_2; - Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); - /* Bool_Glob == 1 */ - while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ - { - Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; - /* Int_3_Loc == 7 */ - Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); - /* Int_3_Loc == 7 */ - Int_1_Loc += 1; - } /* while */ - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); - /* Int_Glob == 5 */ - Proc_1 (Ptr_Glob); - for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) - /* loop body executed twice */ - { - if (Enum_Loc == Func_1 (Ch_Index, 'C')) - /* then, not executed */ - { - Proc_6 (Ident_1, &Enum_Loc); - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); - Int_2_Loc = Run_Index; - Int_Glob = Run_Index; - } - } - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Int_2_Loc = Int_2_Loc * Int_1_Loc; - Int_1_Loc = Int_2_Loc / Int_3_Loc; - Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; - /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ - Proc_2 (&Int_1_Loc); - /* Int_1_Loc == 5 */ - - } /* loop "for Run_Index" */ - - /**************/ - /* Stop timer */ - /**************/ - -#ifdef TIMES - times (&time_info); - End_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - End_Time = time ( (long *) 0); -#endif -#ifdef MSC_CLOCK - End_Time = clock(); -#endif - /* - printf ("Execution ends\n"); - printf ("\n"); - printf ("Final values of the variables used in the benchmark:\n"); - printf ("\n"); - printf ("Int_Glob: %d\n", Int_Glob); - printf (" should be: %d\n", 5); - printf ("Bool_Glob: %d\n", Bool_Glob); - printf (" should be: %d\n", 1); - printf ("Ch_1_Glob: %c\n", Ch_1_Glob); - printf (" should be: %c\n", 'A'); - printf ("Ch_2_Glob: %c\n", Ch_2_Glob); - printf (" should be: %c\n", 'B'); - printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); - printf (" should be: %d\n", 7); - printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); - printf (" should be: Number_Of_Runs + 10\n"); - printf ("Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent)\n"); - printf (" Discr: %d\n", Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 2); - printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 17); - printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Next_Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent), same as above\n"); - printf (" Discr: %d\n", Next_Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 1); - printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 18); - printf (" Str_Comp: %s\n", - Next_Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Int_1_Loc: %d\n", Int_1_Loc); - printf (" should be: %d\n", 5); - printf ("Int_2_Loc: %d\n", Int_2_Loc); - printf (" should be: %d\n", 13); - printf ("Int_3_Loc: %d\n", Int_3_Loc); - printf (" should be: %d\n", 7); - printf ("Enum_Loc: %d\n", Enum_Loc); - printf (" should be: %d\n", 1); - printf ("Str_1_Loc: %s\n", Str_1_Loc); - printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); - printf ("Str_2_Loc: %s\n", Str_2_Loc); - printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); - printf ("\n"); - -*/ - User_Time = End_Time - Begin_Time; - - if (User_Time < Too_Small_Time) - { - printf ("Measured time too small to obtain meaningful results\n"); - printf ("Please increase number of runs\n"); - printf ("\n"); - } - else - { -#ifdef TIME - Microseconds = (float) User_Time * Mic_secs_Per_Second - / (float) Number_Of_Runs; - Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; -#else - Microseconds = (float) User_Time * Mic_secs_Per_Second - / ((float) HZ * ((float) Number_Of_Runs)); - Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) - / (float) User_Time; -#endif - printf ("Microseconds for one run through Dhrystone: "); - printf ("%6.1f \n", Microseconds); - printf ("Dhrystones per Second: "); - printf ("%6.1f \n", Dhrystones_Per_Second); - printf ("\n"); - printf ("This equals to %6.1f DMIPS\n", Dhrystones_Per_Second/1757); - } - -} - - -Proc_1 (Ptr_Val_Par) -/******************/ - -REG Rec_Pointer Ptr_Val_Par; - /* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3 (&Next_Record->Ptr_Comp); - /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp - == Ptr_Glob->Ptr_Comp */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } - else /* not executed */ - structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); -} /* Proc_1 */ - - -Proc_2 (Int_Par_Ref) -/******************/ - /* executed once */ - /* *Int_Par_Ref == 1, becomes 4 */ - -One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc; - - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1); /* true */ -} /* Proc_2 */ - - -Proc_3 (Ptr_Ref_Par) -/******************/ - /* executed once */ - /* Ptr_Ref_Par becomes Ptr_Glob */ - -Rec_Pointer *Ptr_Ref_Par; - -{ - if (Ptr_Glob != Null) - /* then, executed */ - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ - - -Proc_4 () /* without parameters */ -/*******/ - /* executed once */ -{ - Boolean Bool_Loc; - - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ - - -Proc_5 () /* without parameters */ -/*******/ - /* executed once */ -{ - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - - - /* Procedure for the assignment of structures, */ - /* if the C compiler doesn't support this feature */ -#ifdef NOSTRUCTASSIGN -memcpy (d, s, l) -register char *d; -register char *s; -register int l; -{ - while (l--) *d++ = *s++; -} -#endif - - diff --git a/lib/CPUs/MIPS/bsp/examples/dhry_2.c b/lib/CPUs/MIPS/bsp/examples/dhry_2.c deleted file mode 100644 index 63a3d3e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dhry_2.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - **************************************************************************** - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_2.c (part 3 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - **************************************************************************** - */ - -#include "dhry.h" - -#ifndef REG -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#endif - -extern int Int_Glob; -extern char Ch_1_Glob; - - -Proc_6 (Enum_Val_Par, Enum_Ref_Par) -/*********************************/ - /* executed once */ - /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ - -Enumeration Enum_Val_Par; -Enumeration *Enum_Ref_Par; -{ - *Enum_Ref_Par = Enum_Val_Par; - if (! Func_3 (Enum_Val_Par)) - /* then, not executed */ - *Enum_Ref_Par = Ident_4; - switch (Enum_Val_Par) - { - case Ident_1: - *Enum_Ref_Par = Ident_1; - break; - case Ident_2: - if (Int_Glob > 100) - /* then */ - *Enum_Ref_Par = Ident_1; - else *Enum_Ref_Par = Ident_4; - break; - case Ident_3: /* executed */ - *Enum_Ref_Par = Ident_2; - break; - case Ident_4: break; - case Ident_5: - *Enum_Ref_Par = Ident_3; - break; - } /* switch */ -} /* Proc_6 */ - - -Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) -/**********************************************/ - /* executed three times */ - /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ - /* Int_Par_Ref becomes 7 */ - /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ - /* Int_Par_Ref becomes 17 */ - /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ - /* Int_Par_Ref becomes 18 */ -One_Fifty Int_1_Par_Val; -One_Fifty Int_2_Par_Val; -One_Fifty *Int_Par_Ref; -{ - One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 2; - *Int_Par_Ref = Int_2_Par_Val + Int_Loc; -} /* Proc_7 */ - - -Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) -/*********************************************************************/ - /* executed once */ - /* Int_Par_Val_1 == 3 */ - /* Int_Par_Val_2 == 7 */ -Arr_1_Dim Arr_1_Par_Ref; -Arr_2_Dim Arr_2_Par_Ref; -int Int_1_Par_Val; -int Int_2_Par_Val; -{ - REG One_Fifty Int_Index; - REG One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 5; - Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; - Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; - Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; - for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) - Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; - Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; - Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; - Int_Glob = 5; -} /* Proc_8 */ - - -Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val) -/*************************************************/ - /* executed three times */ - /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ - /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ - /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ - -Capital_Letter Ch_1_Par_Val; -Capital_Letter Ch_2_Par_Val; -{ - Capital_Letter Ch_1_Loc; - Capital_Letter Ch_2_Loc; - - Ch_1_Loc = Ch_1_Par_Val; - Ch_2_Loc = Ch_1_Loc; - if (Ch_2_Loc != Ch_2_Par_Val) - /* then, executed */ - return (Ident_1); - else /* not executed */ - { - Ch_1_Glob = Ch_1_Loc; - return (Ident_2); - } -} /* Func_1 */ - - -Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) -/*************************************************/ - /* executed once */ - /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ - /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ - -Str_30 Str_1_Par_Ref; -Str_30 Str_2_Par_Ref; -{ - REG One_Thirty Int_Loc; - Capital_Letter Ch_Loc; - - Int_Loc = 2; - while (Int_Loc <= 2) /* loop body executed once */ - if (Func_1 (Str_1_Par_Ref[Int_Loc], - Str_2_Par_Ref[Int_Loc+1]) == Ident_1) - /* then, executed */ - { - Ch_Loc = 'A'; - Int_Loc += 1; - } /* if, while */ - if (Ch_Loc >= 'W' && Ch_Loc < 'Z') - /* then, not executed */ - Int_Loc = 7; - if (Ch_Loc == 'R') - /* then, not executed */ - return (true); - else /* executed */ - { - if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) - /* then, not executed */ - { - Int_Loc += 7; - Int_Glob = Int_Loc; - return (true); - } - else /* executed */ - return (false); - } /* if Ch_Loc */ -} /* Func_2 */ - - -Boolean Func_3 (Enum_Par_Val) -/***************************/ - /* executed once */ - /* Enum_Par_Val == Ident_3 */ -Enumeration Enum_Par_Val; -{ - Enumeration Enum_Loc; - - Enum_Loc = Enum_Par_Val; - if (Enum_Loc == Ident_3) - /* then, executed */ - return (true); - else /* not executed */ - return (false); -} /* Func_3 */ - diff --git a/lib/CPUs/MIPS/bsp/examples/dttl.c b/lib/CPUs/MIPS/bsp/examples/dttl.c deleted file mode 100644 index 8efffa2..0000000 --- a/lib/CPUs/MIPS/bsp/examples/dttl.c +++ /dev/null @@ -1,261 +0,0 @@ -/* dttl.c -- simulation of Cassini/Huygens symbol synchronizer loop - * - * Author: Lorenzo Simone's (matlab script) - * Modifications by: Jon Hamkins (conversion to C, support routines, - * memory requirement reductions) - * Last Revised: Wed Jan 31 10:47:52 PST 2001 - */ -#define M_PI 3.1415926535897932384626433832795 - -#include -#include -#include "random.h" - -/* global variables */ -int delay, - L; /* samples per symbol */ -double Pt, /* transition density */ - sigma; /* noise standard deviation */ -long seed=-123; - -/* This function simulates a large 1-dimensional array without requiring - * storage for the whole array. This is possible because the array is - * accessed in roughly increasing indices. Thus, we only need to - * store a few symbols worth of samples in the array, and we can reuse - * the array indices as time goes on. */ -int drint(double v) -{ - return (int)(v+0.5); -} - -double -rec(int idx) -{ - static int firsttime = 1, - max, /* maximum index containing data */ - mod, /* length of ring buffer */ - b; /* value of last transmitted bit */ - static double r[2000]; /* need several symbols worth of samples */ - int i,j,k; - - /* First time, store samples for random delay and first few symbols */ - if (firsttime==1) { - firsttime=0; - for (i=0; i0.5) ? 1 : -1; /* first random symbol */ - for (j=0; j<3; j++) { /* 3 binary symbols with transition Pt */ - b = (ran1(&seed)>Pt) ? b : -b; /* next symbol value */ - for (k=0; kmax) /* check if we need to create another sample */ - { - b = (ran1(&seed)>Pt) ? b : -b; /* next symbol value */ - /* generate samples for one symbol and store in ring buffer */ - for (i=1; i<=L; i++) r[(int)(fmod(max+i,mod))] = b+sigma*gaussian(&seed); - max += L; /* maximum index for which samples exist */ - } - /* return appropriate sample from ring buffer */ - return(r[(int)(fmod(idx,mod))]); -} - -main() -{ - double - detout, /* detector output */ - I, old_I, /* in-phase accumulations */ - Q, old_Q, /* quadrature accumulations */ - T, /* transition detection */ - theta, /* baseband NCO output (radians) */ - lambda, /* normalized timing error (symbols) */ - A, alfa, Ampl, Bl, Df, - DR, Es_No, Es_No_lin, Fc1, Fc2, Fvco, Fs, Kd, Kv, - lambda_ss_sim = 0., lambda_ss_th, No, P, P_No, - sigma_lambda_sim = 0., sigma_lambda_th, SNR_sim, SNR_th, tau, Tc1, Tc2, - time, Ts, x1, Y, bit_I, bit_Q, bit; - int i, j, k, N, offset, k1, k2, EOB; - FILE *p1, *p2, *p3, *p4, *p5; - - /* Data settings */ - Fc1 = 48000; /* sample rate at DTTL input (F1/2 = 8.215MHz/2) */ - Tc1 = 1./Fc1; - - DR = 4800; /* data rate (symb/sec) */ - - Fc2 = DR; /* sampling rate pre-detection */ - Tc2 = 1./Fc2; - - L = drint(Tc2/Tc1); /* samples per symbol in the arm filters */ - offset = drint(L/2.); - - Es_No = 600.; /* dB */ - P_No = Es_No+10.*log10(DR); /* data power-over-noise spectral density */ - /* ratio (dBHz) */ - - N = 2500; /* number of symbols to simulate */ - Pt=.5; /* Transition density */ - - Bl=0.01*DR; /* loop bandwidth (Hz) */ - Df=0.001*DR; /* frequency offset */ - Fvco=DR+Df; - - tau=ran1(&seed)-.5; /* set symbol timing offset, -.5 to .5 */ - delay=drint(2.*L+tau*L+1); /* channel delay */ - - P=1.; /* data power */ - Ampl=sqrt(P); - - No=10.*log10(P*Tc2)-Es_No; /* noise spectral density (dBW/Hz) */ - sigma=sqrt(pow(10.,0.1*No)/(2.*Tc1)); - printf("sigma=%f\n",sigma); - - /* DPLL settings */ - Fs=DR; /* loop sampling frequency (Hz) */ - Ts=1./Fs; /* loop sampling time (s) */ - - /* Loop gain */ - Kd=2.*Ampl*Pt; /* phase detector gain (quants/rad) */ - /* @ high Es/No */ - Kv=1.; /* VCO gain (rad/quants) */ - - /* Analog loop filter components */ - alfa=4.*Bl/(Kd*Kv); - - /* Digital loop filter components */ - A=alfa*Ts; - - /* Initial condition */ - theta = 0; - old_I=1; - old_Q=1; - x1=0; - Y=0; - - /* Plot data files */ -// p1 = fopen("plot1.dat","w"); /* theta */ -// p2 = fopen("plot2.dat","w"); /* lambda */ -// p3 = fopen("plot3.dat","w"); /* detout */ -// p4 = fopen("plot4.dat","w"); /* I-Data */ -// p5 = fopen("plot5.dat","w"); /* Q-Data */ - - k1 = drint(0.5*N); - k2 = N; - - printf("Data rate: %.0f symbols/sec\n",DR); - printf("Sample rate at DTTL input: %.0f samples/sec\n",Fc1); - printf("Samples per symbol: %d\n",L); - printf("Random delay set to: %f symbols (%d samples)\n",tau,delay); - printf("Transition density used in random bit generation: %f\n",Pt); - printf("Es/No: %f dB\n",Es_No); - printf("Loop bandwidth: %f Hz\n",Bl); - printf("Doppler: %f Hz\n",Df); - printf("Simulation length: %d symbols (%d samples)\n\n",N,N*L+delay); - - /* Simulation Loop */ - for (i=2; i<=N; i++) - { - /* loop over symbols */ - /* find start of in-phase integration */ - for (j=1; j < L; j++) - { - if (fmod(theta + 2*M_PI * Fvco*(j+1+(i-1)*(Fc1/DR))/Fc1, 2*M_PI) - < fmod(theta + 2*M_PI * Fvco*(j +(i-1)*(Fc1/DR))/Fc1, 2*M_PI)) - break; - /* one could replace loop above with a direct calculation such as: */ - /* j=ceil((1.-modulo(theta/(2*M_PI),1.))/(Fvco*Tc1))-1.; */ - /* j+1 is the first index in the block */ - EOB=j+(i-1)*L; /* End of Block */ - } - /* In-phase integrator */ - bit_I = 0.; - printf("Symbol # %d\n", i); - printf("I[%d:%d] :\n", EOB-L+1, EOB); - for (j=EOB-L+1; j<=EOB; j++) - { - bit = rec(j); - if (bit > 0) - printf("-"); - else - printf("_"); - - bit_I += bit; - } - printf("\n"); - I = bit_I; - - /* Mid-Phase integrator */ - bit_Q = 0.; - printf("Q[%d:%d] :\n", EOB-L+offset+1, EOB+offset); - for (j=EOB-L+offset+1; j<=EOB+offset; j++) - { - bit = rec(j); - if (bit > 0) - printf("-"); - else - printf("_"); - - bit_Q += bit; - } - printf("\n\n"); - Q = bit_Q; - - Q *= 2.*M_PI/(Tc2/Tc1); - - /* Transition Detector */ - I = (I > 0) ? 1. : -1.; /* hard limiter */ - T = 0.5*(I - old_I); - - /* Detector Output */ - detout = fmod(old_Q*T,2*M_PI); - - /* Save accumulations for next time through loop */ - old_I = I; - old_Q = Q; - if (fabs(detout)>M_PI) - detout = -detout+2*M_PI*((detout>0) ? 1. : -1.); - - /* NCO */ - Y += detout*A; /* Loop filter */ - theta=Kv*Y; /* phase */ -// lambda = theta/(2.*M_PI)+(i*Tc2*Df+tau); /* normalized error */ - lambda = theta/(2.*M_PI)+(i*(Fvco/DR -1) + tau); /* normalized error */ - - /* error mean and variance calculation */ - lambda_ss_sim += lambda; /* partial sum */ - sigma_lambda_sim += lambda*lambda; /* partial sum of squares */ - - /* store phase and normalized error to data files */ -// fprintf(p1,"%f %f\n",(double)i,theta); -// fprintf(p2,"%f %f\n",(double)i,lambda); -// fprintf(p3,"%f %f\n",(double)i,detout); -// fprintf(p4,"%f %f\n",(double)i,I); -// fprintf(p5,"%f %f\n",(double)i,Q); - } -// fclose(p1); -// fclose(p2); -// fclose(p3); -// fclose(p4); -// fclose(p5); - - /* Statistics Analysis */ - /* ------------------- */ - /* complete the mean and variance calculation */ - lambda_ss_sim /= N; - sigma_lambda_sim = sigma_lambda_sim/N - lambda_ss_sim*lambda_ss_sim; - Es_No_lin = pow(10.,0.1*Es_No); -// sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*pow(erf(sqrt(Es_No_lin)),2.)); - sigma_lambda_th = Bl*Tc2/(4.*Pt*Es_No_lin*Es_No_lin); - SNR_sim = -10*log10(sigma_lambda_sim); - SNR_th = -10*log10(sigma_lambda_th); - /* Steady-State error */ - lambda_ss_th=Df/(4.*Bl); - printf("Simulation: var: %f rad^2 loop SNR: %f dB ss error: %f%%\n", - sigma_lambda_sim, SNR_sim, 100.*lambda_ss_sim); - printf("Theory: var: %f rad^2 loop SNR: %f dB ss error: %f%%\n", - sigma_lambda_th, SNR_th, 100.*lambda_ss_th); -// system("gnuplot < plot1.gp"); -// system("gnuplot < plot2.gp"); - printf("Done.\n"); -} diff --git a/lib/CPUs/MIPS/bsp/examples/gunzip.c b/lib/CPUs/MIPS/bsp/examples/gunzip.c deleted file mode 100644 index 550cf88..0000000 --- a/lib/CPUs/MIPS/bsp/examples/gunzip.c +++ /dev/null @@ -1,198 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#define CPU_FREQ_HZ 100000000 -#include "libsys.h" - -#include "crc32.h" -#include "inflate.h" - -char buffer[1024*1024]; -char * volatile pPtr_r; -char * volatile pPtr_w; -volatile int timeout_cnt; -volatile int file_len; - -void handler3(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart0_data; - - while(0x200 & *pUART_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[sizeof(buffer)-1]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART_data; - timeout_cnt = 100; - file_len++; - } - -} - -int READBYTE(z_stream *zs) { - if (zs->avail_in <= 0) - return -1; - - zs->avail_in --; - return *(zs->next_in ++); -} - -#define MAX_BUFOUT 16*1024*1024 -int main(int argc, char **argv) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat; - unsigned char outData[MAX_BUFOUT]; - FILE *infp; - int i, gpflags, tmp[4]; - unsigned long size, crc; - unsigned char *fileData; - unsigned long bytes, InflatedSize, InflatedCRC, speed_count; - z_stream zs; - time_t start_time, work_time; - - UART0_setbaud(460800); - - printf("Reading gzipped stream..\n"); - - pPtr_r = buffer; - pPtr_w = buffer; - *pUART_stat = (1 << 6); - interrupt_register(3, handler3); - interrupt_enable(3); - - file_len = 0; - timeout_cnt = 1000000; - while(timeout_cnt--) - { - sleep(1); - } - - printf("file_len: %d\n", file_len); - bytes = file_len; - fileData = pPtr_r; - - zs.next_in = fileData; - zs.avail_in = (unsigned int) bytes; - zs.next_out = outData; - zs.avail_out = MAX_BUFOUT; - - tmp[0] = READBYTE(&zs); - if (tmp[0] == -1) - { - // error reading from file - printf("error reading data from file\n"); - return 0; - } - tmp[1] = READBYTE(&zs); - - if (tmp[0] != 0x1f || tmp[1] != 0x8b) { -// fprintf(stderr, "Magic number mismatch 0x%02x%02x\n", -// tmp[0], tmp[1]); - return 20; - } - - tmp[0] = READBYTE(&zs); - if(tmp[0] != 8) { -// fprintf(stderr, "Unknown compression method: 0x%02x\n", tmp[0]); - return 20; - } - - gpflags = READBYTE(&zs); - if ((gpflags & ~0x1f)) { - printf("Unknown flags set!\n"); - } - - /* Skip file modification time (4 bytes) */ - READBYTE(&zs); - READBYTE(&zs); - READBYTE(&zs); - READBYTE(&zs); - /* Skip extra flags and operating system fields (2 bytes) */ - READBYTE(&zs); - READBYTE(&zs); - - if ((gpflags & 4)) { - /* Skip extra field */ - tmp[0] = READBYTE(&zs); - tmp[1] = READBYTE(&zs); - i = tmp[0] + 256*tmp[1]; - while (i--) - { - READBYTE(&zs); - } - } - if((gpflags & 8)) { - while((READBYTE(&zs))) { - } - } - if((gpflags & 16)) { - while((READBYTE(&zs))) { - } - } - if((gpflags & 2)) { - /* Skip CRC16 */ - READBYTE(&zs); - READBYTE(&zs); - } - - printf("Go\n"); - // normal test - start_time = clock(); - if (InflateData(&zs)) - { - printf("Problem during decompression!\n"); - return 0; - } - work_time = clock() - start_time; - - -/* - // speed test - fprintf(stdout, "SPEED TEST!\n"); - speed_count = 0; - while (time(NULL) - start_time < 20) - { - zs_speed.next_in = zs.next_in; - zs_speed.next_out = zs.next_out; - zs_speed.avail_in = zs.avail_in; - zs_speed.avail_out = zs.avail_out; - if (InflateData(&zs_speed)) - { - fprintf(stdout, "Problem during decompression!\n"); - return 0; - } - speed_count ++; - } - fprintf(stdout, "speed count %ld\n", speed_count); - zs.next_in = zs_speed.next_in; - zs.next_out = zs_speed.next_out; - zs.avail_in = zs_speed.avail_in; - zs.avail_out = zs_speed.avail_out; -*/ - - crc = READBYTE(&zs); - crc |= (READBYTE(&zs)<<8); - crc |= (READBYTE(&zs)<<16); - crc |= (READBYTE(&zs)<<24); - - size = READBYTE(&zs); - size |= (READBYTE(&zs)<<8); - size |= (READBYTE(&zs)<<16); - size |= (READBYTE(&zs)<<24); - - InflatedSize = MAX_BUFOUT - zs.avail_out; - InflatedCRC = MakeCRC32(outData, InflatedSize, 0); - -// write(1, outData, InflatedSize); - fprintf(stdout, "CRC: %08lx %08lx %s\n", crc, InflatedCRC, (crc != InflatedCRC)?"**error**":""); - fprintf(stdout, "Size: %08lx %08lx %s\n", size, InflatedSize, (size != InflatedSize)?"**error**":""); - fprintf(stdout, "Time for decompression was %.2f seconds\n", (float)work_time/1000); - fprintf(stdout, "Throughput is %d kByte/s\n", InflatedSize/work_time); - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/hello.c b/lib/CPUs/MIPS/bsp/examples/hello.c deleted file mode 100644 index e655913..0000000 --- a/lib/CPUs/MIPS/bsp/examples/hello.c +++ /dev/null @@ -1,19 +0,0 @@ -#include -#define A 0.5 -#define B 0.55 - -_Sat long _Fract sat_add3 (_Sat long _Fract a, _Sat long _Fract b) -{ - return a + b; -} - -long _Fract mul3 (long _Fract a, long _Fract b) -{ - return a * b; -} - -int main() -{ - printf("hello %X + %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, sat_add3(A, B)); - printf("hello %X * %X = %X\n", (_Sat long _Fract)A, (_Sat long _Fract)B, mul3(A, B)); -} diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.c b/lib/CPUs/MIPS/bsp/examples/inflate.c deleted file mode 100644 index b50581d..0000000 --- a/lib/CPUs/MIPS/bsp/examples/inflate.c +++ /dev/null @@ -1,504 +0,0 @@ -/* inflate routines for Palm OS (to inflate a deflated stream) - * - * Based heavily upon gunzip.c by Pasi Ojala - * http://www.cs.tut.fi/~albert/Dev/gunzip/ - * Many, many thanks for that code! - * - * Changes: - * 2002-12-30 - Added #defines to use zlib's struct instead of mine, just - * in case you want to compile it that way. - * 2002-12-29 - Found out that this is VERY slow. ZLib is 3x faster. - * Worked on speeding it up. Partially successful. Profiled - * code and marked critical areas. 1932 bytes added to a - * Palm program by linking in the .o file. Schweet! - * 2002-12-21 - Finished surgery. Only one function to inflate dynamic and - * fixed data. Rewrote table generation to be iterative. - * Hacked and slashed my way through unnecessary code. - * The size is now down to 3512 bytes. - * 2002-12-20 - Started major surgery - * 2002-12-19 - Looked at the code a bit more - * 2002-12-17 - Continued work. Down to about 6k for the .o file - * 2002-12-09 - Continued work, added z_stream_fid instead of globals - * 2002-12-08 - Started work so that it decompresses up to 64k (one memory - * chunk on the Palm. - * 2002-12-07 - Removed bit reverse table. Removed unzip code. - */ -#include "libsys.h" -#include "inflate.h" -#ifdef VERBOSE -#include // Just in case you put a printf() function back in -#endif - -void Status(char *, int); - -typedef struct HufNode_struct { - // b0 and b1 are either values in the tree array to jump to (branches) - // or are literal values. - // if (bX & 0x8000) - // value = bX ^ 0x8000; - // else - // link_to_array_element = bX; - unsigned int b0; // Bigger than 1 byte (2 is ideal) - unsigned int b1; // Bigger than 1 byte (2 is ideal) -} HufNode; - - -// Not that rhobust anymore -- If out of data, this will -// return a whole lot of 1 bits. -// -// This function consumes a large percentage of time (#1) -char READBIT(z_stream *zs) -{ - char carry; - - if (zs->reserved == 1) - { - if (zs->avail_in == 0) - return 1; - zs->reserved = *(zs->next_in ++) | 0x0100; - zs->avail_in --; - } - - carry = zs->reserved & 1; - zs->reserved >>= 1; - - return carry; -} - - -// Make sure that [a] is <= 16 -// If there are endian problems, force [a] to be <= 8 -// Might be faster if all (up to [a] bits) of zs->reserved was read into res -// right away. -// -// This function consumes a large percentage of time (#4) -int READBITS(z_stream *zs, int a) -{ - int res = 0, pos = 0; - - while (a --) - { - if (zs->reserved == 1) - { - if (zs->avail_in == 0) - return 1; - zs->reserved = *(zs->next_in ++) | 0x0100; - zs->avail_in --; - } - - res += (zs->reserved & 1) << pos; - zs->reserved >>= 1; - pos ++; - } - - return res; -} - - -// Huffman tree structures, variables and related routines -// -// These routines are one-bit-at-a-time decode routines. They -// are not as fast as multi-bit routines, but maybe a bit easier -// to understand and use a lot less memory. -// -// The tree is created in an array -// -// currentTree = where to put the tree (in an array) -// numval = Number of elements in the lengths array -// lengths = array of lengths -// -// -// This function consumes a large percentage of time (#5) -int CreateTree(HufNode *currentTree, int numval, unsigned char *lengths) { - int i, j, len; // basically scratch values - int BlankNode; // Where is the next blank array index - int this_code, mask, *bitData; // used in tree generation - int bl_count[16] = { 0, }; // Counter of code lengths - int next_code[16] = { 0, }; // Code for a specific length - // 16 = (15 is max length of a code when inflating) + (1 for zero) - - // Step 1: Count the code lengths - for (i = 0; i < numval; i ++) - { - j = lengths[i]; - if (j > 15) - return 1; - bl_count[j] ++; - } - - // Step 2: Find numerical value of the smallest code of each length - // Also note that I've inserted some weak validation code here. I'm - // not 100% sure that it is up to RFC specs, but it seems to work fine - // in my tests - // - // The validation theory is that at the root node, you have 2 branches or - // values possible. If you branch, you get 2 more potentials. If you - // get a value, you lose one potential. So, if the root node has one of - // each, the number of potentials at the next level is still two. If that - // node just has branches, the number of potentials is four. If both of - // the nodes on the following level just have values, the number of - // potentials is 0, leaving us with a complete tree. - // - // If I don't validate and if an invalid tree gets generated, an - // infinite loop is possible - bl_count[0] = 0; - j = 0; - len = 2; - for (i = 1; i < 16; i ++) - { - len -= bl_count[i]; - len *= 2; - j = (j + bl_count[i - 1]) << 1; - next_code[i] = j; - } - if (len) - return 1; - - // Step 3: Assign numerical values to all codes - BlankNode = 1; - currentTree[0].b0 = 0x0000; - currentTree[0].b1 = 0x0000; - for (i = 0; i < numval; i ++) - { - len = lengths[i]; - if (len != 0) - { - this_code = next_code[len]; - next_code[len] ++; - mask = 1 << (len - 1); - j = 0; - while (mask > 1) - { - if (this_code & mask) - bitData = &(currentTree[j].b1); - else - bitData = &(currentTree[j].b0); - - if (*bitData == 0x0000) - { - *bitData = BlankNode; - j = BlankNode; - BlankNode ++; - currentTree[j].b0 = 0x0000; - currentTree[j].b1 = 0x0000; - } - else - j = *bitData; - - mask >>= 1; - } - if (this_code & 0x01) - currentTree[j].b1 = 0x8000 | i; - else - currentTree[j].b0 = 0x8000 | i; - } - } - -#ifdef VERBOSE - fprintf(stderr, "%d table entries used\n", - BlankNode); - if (numval < 20) { - for (i = 0; i < BlankNode; i ++) - { - fprintf(stderr, "0x%03x - ", i); - if (currentTree[i].b0 & 0x8000) - fprintf(stderr, "value: 0x%03x ", currentTree[i].b0 ^ 0x8000); - else - fprintf(stderr, " link: 0x%03x ", currentTree[i].b0); - - if (currentTree[i].b1 & 0x8000) - fprintf(stderr, "value: 0x%03x\n", currentTree[i].b1 ^ 0x8000); - else - fprintf(stderr, " link: 0x%03x\n", currentTree[i].b1); - } - } -#endif - - return 0; -} - - -// Using the tree passed in, read bits from the data stream until we arrive -// at the proper value -// -// This function consumes a large percentage of time (#2) -int DecodeValue(z_stream *zs, HufNode *currentTree) -{ - unsigned int i = 0; - - // decode one symbol of the data per iteration - // Infinite loop detection code could go here. Maximum - // bits to read is 15. - while (i < 0x8000) - { - if (READBIT(zs)) - i = currentTree[i].b1; - else - i = currentTree[i].b0; - } - return i & 0x7FFF; -} - - -int Decompress_Stored(z_stream *zs) -{ - int blockLen, cSum; - -#ifdef VERBOSE - fprintf(stderr, "Stored\n"); -#endif - - zs->reserved = 1;; - if (zs->avail_in < 4) - return -1; - - zs->avail_in -= 4; - blockLen = *(zs->next_in ++); - blockLen |= *(zs->next_in ++) << 8; - - cSum = *(zs->next_in ++); - cSum |= (*(zs->next_in ++) << 8); - - if ((blockLen + cSum) ^ 0xFFFF) - return 1; - if (zs->avail_in < blockLen || zs->avail_out < blockLen) - return -1; - zs->avail_in -= blockLen; - zs->avail_out -= blockLen; - - while (blockLen --) - { - *(zs->next_out) = *(zs->next_in); - zs->next_out ++; - zs->next_in ++; - } - - return 0; -} - - -int MakeTrees(z_stream *zs, char is_fixed, HufNode *literalTree, - HufNode *distanceTree) -{ - // Order of the bit length code lengths - static const unsigned border[] = { - 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 }; - unsigned char ll[288+32]; - int i, j, n, l, literalCodes, distCodes; - - if (is_fixed) - { - literalCodes = 288; - - // Set a large range to 8 - for (i = 0; i < 288; i ++) - ll[i] = 8; - // In that range, set some to 9 and others to 7 - // (smaller code, but slightly slower table generation) - for (i = 144; i < 256; i ++) - ll[i] = 9; - for (; i < 280; i ++) - ll[i] = 7; - - distCodes = 32; - - for (i = 288; i < 320; i ++) - ll[i] = 5; - } - else - { - literalCodes = 257 + READBITS(zs, 5); - distCodes = 1 + READBITS(zs, 5); - l = 4 + READBITS(zs, 4); - - for (j = 0; j < 19; j ++) - ll[j] = 0; - - // Get the decode tree code lengths - // The decode tree is Huffman encoded - - for (j = 0; j < l; j++) - { - ll[border[j]] = READBITS(zs, 3); - } - if (CreateTree(distanceTree, 19, ll)) - return 1; - - // read in literal and distance code lengths - n = literalCodes + distCodes; - i = 0; - while (i < n) - { - j = DecodeValue(zs, distanceTree); - if (j < 16) // length of code in bits (0..15) - ll[i++] = j; - else if (j == 16) - { // repeat last length 3 to 6 times - j = 3 + READBITS(zs, 2); - - if (i + j > n) - return 1; - - l = i ? ll[i-1] : 0; - while (j --) - ll[i++] = l; - } - else - { - if (j == 17) // 3 to 10 zero length codes - j = 3 + READBITS(zs, 3); - else // j == 18: 11 to 138 zero length codes - j = 11 + READBITS(zs, 7); - - if (i + j > n) - return 1; - - while (j --) - ll[i++] = 0; - } - } - } - - - // Can overwrite tree decode tree as it is not used anymore - if (CreateTree(literalTree, literalCodes, &ll[0])) - return 1; - - if(CreateTree(distanceTree, distCodes, &ll[literalCodes])) - return 1; - - return 0; -} - - -// This function consumes a large percentage of time (#3) -// Most output produced by gzip/zlib/etc is dynamic. -int Decompress_DynamicOrFixed(z_stream *zs, char is_fixed) -{ - // Copy lengths for literal codes 257..285 - static const unsigned short cplens[] = { - 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, - 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0 }; - // Extra bits for literal codes 257..285 - static const unsigned short cplext[] = { - 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, - 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0, 99, 99 }; // 99==invalid - // Copy offsets for distance codes 0..29 - static const unsigned short cpdist[] = { - 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0007, 0x0009, 0x000d, - 0x0011, 0x0019, 0x0021, 0x0031, 0x0041, 0x0061, 0x0081, 0x00c1, - 0x0101, 0x0181, 0x0201, 0x0301, 0x0401, 0x0601, 0x0801, 0x0c01, - 0x1001, 0x1801, 0x2001, 0x3001, 0x4001, 0x6001 }; - // Extra bits for distance codes - static const unsigned short cpdext[] = { - 0, 0, 0, 0, 1, 1, 2, 2, - 3, 3, 4, 4, 5, 5, 6, 6, - 7, 7, 8, 8, 9, 9, 10, 10, - 11, 11, 12, 12, 13, 13 }; - HufNode literalTree[288]; - HufNode distanceTree[32]; - int j, l, dist; - -#ifdef VERBOSE - if (is_fixed) - fprintf(stderr, "Fixed Huffman codes\n"); - else - fprintf(stderr, "Dynamic Huffman codes\n"); -#endif - - if (MakeTrees(zs, is_fixed, literalTree, distanceTree)) - return 1; - - while (1) - { - j = DecodeValue(zs, literalTree); - if (j >= 256) - { - if (j == 256) // EOF - break; - - //printf("%04x ", j); - j -= 256 + 1; // bytes + EOF - - l = READBITS(zs, cplext[j]) + cplens[j]; - //printf("%04x ", l); - - j = DecodeValue(zs, distanceTree); - //printf("%02x ", j); - - dist = READBITS(zs, cpdext[j]) + cpdist[j]; - //printf("%04x ", dist); - - //printf("LZ77 len %d dist %d @%04x\n", l, dist, bIdx); - while(l--) - { - //printf("%02x ", c); - if (! zs->avail_out --) - return -1; - - *(zs->next_out ++) = *(zs->next_out - dist); - } - //printf("\n"); - } - else - { - //printf("%02x\n", j); - if (! zs->avail_out --) - return -1; - *(zs->next_out ++) = (unsigned char) j; - } - } - return 0; -} - - -// Returns 0 if success -int InflateData(z_stream *zs) { - int last, type; - - zs->reserved = 1;; - - do - { - last = READBIT(zs); -#ifdef VERBOSE - if (last) - fprintf(stderr, "Last Block: "); - else - fprintf(stderr, "Not Last Block: "); -#endif - - type = READBITS(zs, 2); - - if (type == 0) - { -#ifdef VERBOSE - fprintf(stderr, "Decompress_Stored.."); -#endif - if (Decompress_Stored(zs)) - return 1; - } - else if (type > 2) - { -#ifdef VERBOSE - if (type == 3) - fprintf(stderr, "Reserved block type!!\n"); - else // the "else" should never happen - fprintf(stderr, "Unexpected value %d!\n", type); -#endif - zs->reserved = 1;; - return 1; - } - else - { -#ifdef VERBOSE - fprintf(stderr, "Decompress_DynamicOrFixed.."); -#endif - if (Decompress_DynamicOrFixed(zs, type & 0x01)) - return 1; - } - } while(!last); - - zs->reserved = 1;; - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/inflate.h b/lib/CPUs/MIPS/bsp/examples/inflate.h deleted file mode 100644 index 1f6fd38..0000000 --- a/lib/CPUs/MIPS/bsp/examples/inflate.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifdef USE_ZLIB_STRUCT -#include "SysZLib.h" // For PalmOS. Change to your liking. -#else -typedef struct z_stream_s -{ - unsigned char *next_in; // Next input byte (CHANGES) - unsigned int avail_in; // number of bytes left at next_in - unsigned char *next_out; // Next output byte goes here (CHANGES) - unsigned int avail_out; // number of bytes left at next_out - unsigned int reserved; // For the readbit() and readbits() functions - // Bigger than 1 byte -} z_stream; -#endif - -int InflateData(z_stream *zs); diff --git a/lib/CPUs/MIPS/bsp/examples/irq.c b/lib/CPUs/MIPS/bsp/examples/irq.c deleted file mode 100644 index 85e1320..0000000 --- a/lib/CPUs/MIPS/bsp/examples/irq.c +++ /dev/null @@ -1,92 +0,0 @@ -#include -#include -#include -#include -#include -#include "libsys.h" -#include "regdef.h" -#include "xcpt.h" -#include "irq.h" - -static fp_irq_t g_irq_handler[MAX_NUM_IRQ] = {NULL}; - -int _irq_dispatch(struct xcptcontext * xcp) -{ - int i, ip, cause; - - cause = xcp->cr & xcp->sr; - ip = (cause >> 8) & 0xFF; - - for (i=0; i < MAX_NUM_IRQ; i++) - { - if (ip & 1) - if (g_irq_handler[i]) - (g_irq_handler[i])(xcp); - - ip >>= 1; - } - - return 0; -} - -void interrupt_register(int irq_num, fp_irq_t fp) -{ - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - g_irq_handler[irq_num] = fp; - -} - -void interrupt_enable(int irq_num) -{ - reg_t reg, im; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - im = 1 << irq_num; - reg = CP0_SR_read(); - reg |= (SR_MASK_IM & (im << 8)); - CP0_SR_write(reg); - } - -} - -void interrupt_disable(int irq_num) -{ - reg_t reg, im; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - im = 1 << irq_num; - reg = CP0_SR_read(); - reg &= ~(SR_MASK_IM & (im << 8)); - CP0_SR_write(reg); - } -} - -void interrupt_set(int irq_num) -{ - reg_t reg, ip; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - ip = 1 << irq_num; - reg = CP0_CR_read(); - reg |= (CR_MASK_IP & (ip << 8)); - CP0_CR_write(reg); - } -} - -void interrupt_clr(int irq_num) -{ - reg_t reg, ip; - - if ((irq_num >= 0) && (irq_num < MAX_NUM_IRQ)) - { - ip = 1 << irq_num; - reg = CP0_CR_read(); - reg &= ~(CR_MASK_IP & (ip << 8)); - CP0_CR_write(reg); - } -} - - diff --git a/lib/CPUs/MIPS/bsp/examples/irq.h b/lib/CPUs/MIPS/bsp/examples/irq.h deleted file mode 100644 index d6c343c..0000000 --- a/lib/CPUs/MIPS/bsp/examples/irq.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef IRQ_H -#define IRQ_H - -#include "xcpt.h" - -#define MAX_NUM_IRQ 8 - -typedef void (*fp_irq_t)(struct xcptcontext * xcp); - -int _irq_dispatch(struct xcptcontext * xcp); -void interrupt_register(int irq_num, fp_irq_t fp); -void interrupt_enable(int irq_num); -void interrupt_disable(int irq_num); - -#endif // IRQ_H diff --git a/lib/CPUs/MIPS/bsp/examples/kernel.S b/lib/CPUs/MIPS/bsp/examples/kernel.S deleted file mode 100644 index aa0648b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/kernel.S +++ /dev/null @@ -1,184 +0,0 @@ -#include -#include - - .section .exc_vect -_xcpt_vector_tbl: - .fill 16, 4, 0 - - .text - -LEAF(_xcpt_handler) - .set noreorder - .set noat - /* Note: exceptions do not save and restore registers k0 and k1. - * on entry, k1 = exception class. - */ - - /* allocate exception stack frame (on 8-byte boundary) */ - subu k1, sp, XCP_SIZE - srl k1, 3 /* shift right/left -> alligned on boundary */ - sll k1, 3 - - /* save enough registers to get by */ - sw AT, XCP_AT(k1) - sw v0, XCP_V0(k1) - sw v1, XCP_V1(k1) - sw a0, XCP_A0(k1) - sw a1, XCP_A1(k1) - sw a2, XCP_A2(k1) - sw a3, XCP_A3(k1) - sw sp, XCP_SP(k1) - sw ra, XCP_RA(k1) - - /* get coprocessor 0 exception state */ - mfc0 a0, CP0_CR - mfc0 a1, CP0_SR - mfc0 a2, CP0_BADDR - mfc0 a3, CP0_EPC - - /* we can safely use AT now */ - .set at - - /* switch to using sp to point at exception frame */ - move sp, k1 - - /* nothing sensible to store for k0/k1, store zero */ - sw zero, XCP_K0(sp) - sw zero, XCP_K1(sp) - - /* we are now interruptible: dump all remaining state - * into the exception stack frame. - */ - /* coprocessor exception state */ - sw a0, XCP_CR(sp) - sw a1, XCP_SR(sp) - sw a2, XCP_BADDR(sp) - sw a3, XCP_EPC(sp) - - /* mdhi and mdlo */ - mfhi v0 - mflo v1 - sw v0, XCP_MDHI(sp) - sw v1, XCP_MDLO(sp) - - /* Save all the other general registers. - * We save zero, s0-s7 and s8 as well, as instruction emulators (e.g. FP - * operations) and debuggers rely on all registers stored together in - * well-defined structure. - */ - sw zero, XCP_ZERO(sp) - sw t0, XCP_T0(sp) - sw t1, XCP_T1(sp) - sw t2, XCP_T2(sp) - sw t3, XCP_T3(sp) - sw t4, XCP_T4(sp) - sw t5, XCP_T5(sp) - sw t6, XCP_T6(sp) - sw t7, XCP_T7(sp) - sw s0, XCP_S0(sp) - sw s1, XCP_S1(sp) - sw s2, XCP_S2(sp) - sw s3, XCP_S3(sp) - sw s4, XCP_S4(sp) - sw s5, XCP_S5(sp) - sw s6, XCP_S6(sp) - sw s7, XCP_S7(sp) - sw t8, XCP_T8(sp) - sw t9, XCP_T9(sp) - sw gp, XCP_GP(sp) - sw s8, XCP_S8(sp) - - /* I don't know what the following does. [rb] */ - /* load our _gp pointer */ -# la gp, _gp - - /* and call the C exception handler */ - move a0, sp # arg1 = &xcp - subu sp, 16 # (arg save area) - j _xcpt_call - move ra, zero # fake return address - - /* This strange call to _xcpt_call with zero return address is to - * help exception-aware debuggers to trace back over the exception event. - * We are basically interposing a bogus stackframe (with a zero return - * address) between the C exception handler and the actual machine - * exception. - */ -$xcptrest: - .set noat - add AT, sp, 16 - - /* at points to exception frame */ -$xcptrestother: - /* restore all state */ - /* restore most general registers */ - lw t0, XCP_T0(AT) - lw t1, XCP_T1(AT) - lw t2, XCP_T2(AT) - lw t3, XCP_T3(AT) - lw t4, XCP_T4(AT) - lw t5, XCP_T5(AT) - lw t6, XCP_T6(AT) - lw t7, XCP_T7(AT) - lw s0, XCP_S0(AT) - lw s1, XCP_S1(AT) - lw s2, XCP_S2(AT) - lw s3, XCP_S3(AT) - lw s4, XCP_S4(AT) - lw s5, XCP_S5(AT) - lw s6, XCP_S6(AT) - lw s7, XCP_S7(AT) - lw t8, XCP_T8(AT) - lw t9, XCP_T9(AT) - lw gp, XCP_GP(AT) - lw s8, XCP_S8(AT) - - /* mdhi and mdlo */ - lw v0, XCP_MDHI(AT) - lw v1, XCP_MDLO(AT) - mthi v0 - mtlo v1 - - /* remaining general registers */ - lw a0, XCP_A0(AT) - lw a1, XCP_A1(AT) - lw a2, XCP_A2(AT) - lw a3, XCP_A3(AT) - lw ra, XCP_RA(AT) - - /* restore the exception-time status register */ - .set noreorder - lw v0, XCP_SR(AT) - nop - mtc0 v0, CP0_SR - lw v1, XCP_V1(AT) - lw v0, XCP_V0(AT) - lw sp, XCP_SP(AT) - - /* we are not uninterruptible and can use k1 safely */ - lw k1, XCP_EPC(AT) - lw AT, XCP_AT(AT) - mtc0 k1, CP0_EPC - j k1 - rfe - - .set reorder - .set at -END(_xcpt_handler) - - -LEAF(_xcpt_call) - /* on entry: a0 == &xcp */ - subu sp, 24 - sw ra, 16(sp) - - /* punt out to _xcpt_deliver */ - jal _xcpt_deliver - nop - lw ra, 16(sp) - addu sp, 24 - beqz ra, $xcptrest - nop - j ra - nop -END(_xcpt_call) diff --git a/lib/CPUs/MIPS/bsp/examples/kernel_sim.S b/lib/CPUs/MIPS/bsp/examples/kernel_sim.S deleted file mode 100644 index 4231004..0000000 --- a/lib/CPUs/MIPS/bsp/examples/kernel_sim.S +++ /dev/null @@ -1,260 +0,0 @@ - .file "kernel.s" - - .equ stack_ptr, 0x7FFFEFFC - .equ baudrate, 0x0D - .equ sys_led_port, 0xA0000000 - .equ sys_uart_baud, 0xA0000009 - .equ sys_uart_stat, 0xA0000008 - .equ sys_uart_data, 0xA0000004 - .equ sys_timer_sec, 0xA0000014 - .equ sys_timer_usec, 0xA0000010 - - .section .kdata,"a" - .align 2 -_k_stack: .space 256, 0 -_k_msg1: .asciiz "Exception at " -_k_msg2: .asciiz "EPC : " -_k_msg3: .asciiz "Cause : " -_k_msg4: .asciiz "Status : " -_k_msg5: .asciiz "BadVAddr : " -_k_crlf: .asciiz "\r\n" -_k_hextbl: .ascii "0123456789ABCDEF" - - .section .ktext,"ax" - .align 2 - .globl _kputs - - .macro kpush reg - addiu $sp, 4 - sw \reg, 0($sp) - .endm - - .macro kpop reg - lw \reg, 0($sp) - addiu $sp, -4 - .endm - -_exc_handler: - - sw $sp, _k_stack - la $sp, _k_stack - kpush $8 - kpush $9 - kpush $10 - kpush $11 - kpush $12 - kpush $31 - - .set noreorder -# # Get BadVAddr -# mfc0 $10, $8 -# kpush $10 -# # Get Status -# mfc0 $10, $12 -# kpush $10 -# # Get Cause -# mfc0 $10, $13 -# kpush $10 -# srl $10, 29 -# andi $11, $10, 4 -# # Get EPC -# mfc0 $10, $14 -# kpush $10 -# -# # Get real EPC -# addu $10, $11 -# kpush $10 -# -# # set uart -# la $26, sys_uart_baud -# addiu $27, $0, baudrate -# sb $27, 0($26) -# -# # Print CRLF -# la $11, _k_crlf -# jal _kputs -# nop -# -# # Print real EPC -# la $11, _k_msg1 -# jal _kputs -# nop -# kpop $10 -# jal _kprint_word -# nop -# la $11, _k_crlf -# jal _kputs -# nop -# -# # Print EPC -# la $11, _k_msg2 -# jal _kputs -# nop -# kpop $10 -# jal _kprint_word -# nop -# la $11, _k_crlf -# jal _kputs -# nop -# -# # Print Cause -# la $11, _k_msg3 -# jal _kputs -# nop -# kpop $10 -# jal _kprint_word -# nop -# la $11, _k_crlf -# jal _kputs -# nop -# -# # Print Status -# la $11, _k_msg4 -# jal _kputs -# nop -# kpop $10 -# jal _kprint_word -# nop -# la $11, _k_crlf -# jal _kputs -# nop -# -# # Print BadVAddr -# la $11, _k_msg5 -# jal _kputs -# nop -# kpop $10 -# jal _kprint_word -# nop -# la $11, _k_crlf -# jal _kputs -# nop -# - # Set Error LED and ExcCode LEDs - # Get Cause -# mfc0 $26, $13 -# la $27, sys_led_port -# srl $26, 2 -# andi $26, 0x000F -# or $26, $27 -# sw $26, 0($27) - - # wait for all interrupts = 0 -#$w4x: mfc0 $26, $13 -# mfc0 $27, $12 -# srl $26, 8 -# srl $27, 8 -# and $26, $27 -# bnez $26, $w4x - - # Get return address - mfc0 $26, $14 - -$no_int: kpop $31 - kpop $12 - kpop $11 - kpop $10 - kpop $9 - kpop $8 - lw $sp, _k_stack - - # Return - jr $26 - rfe - .set reorder - -# word = $10 -_kprint_word: - .set noreorder - kpush $31 - kpush $10 - srl $10, 16 - jal _kprint_halfword - nop - kpop $10 - jal _kprint_halfword - nop - kpop $31 - jr $31 - nop - .set noreorder - -# halfword = $10 -_kprint_halfword: - .set noreorder - kpush $31 - kpush $10 - srl $10, 8 - jal _kprint_byte - nop - kpop $10 - jal _kprint_byte - nop - kpop $31 - jr $31 - nop - .set noreorder - -# byte = $10 -_kprint_byte: - .set noreorder - kpush $31 - kpush $10 - srl $10, 4 - jal _kprint_nibble - nop - kpop $10 - jal _kprint_nibble - nop - kpop $31 - jr $31 - nop - .set noreorder - -_kprint_nibble: - .set noreorder - kpush $31 - kpush $10 - la $12, _k_hextbl - andi $10, 0xF - addu $12, $10 - lbu $10, 0($12) - jal _ksaus - nop - kpop $10 - kpop $31 - jr $31 - nop - .set noreorder - -# char = $10 -_ksaus: - .set noreorder - la $8, sys_uart_stat - lbu $8, 0($8) - la $9, sys_uart_data - andi $8, 0x02 - bnez $8, _ksaus - nop - j $31 - sb $10, 0($9) - .set reorder - -_kputs: - .set noreorder - kpush $11 - kpush $31 -$kpl: lbu $10, 0($11) - addiu $11, 1 - blez $10, $kpex - nop - jal _ksaus - nop - j $kpl - nop -$kpex: kpop $31 - kpop $11 - jr $31 - nop - .set reorder - diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.c b/lib/CPUs/MIPS/bsp/examples/libsys.c deleted file mode 100644 index baaebd9..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys.c +++ /dev/null @@ -1,577 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "libsys.h" - -// --------------------------------------------------------------------------------- -// MIPS specific -UINT32 CP0_SR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $12\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_SR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $12\n" - : /* no output */ - : [val] "r" (val) - ); -} - -UINT32 CP0_CR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $13\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_CR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $13\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_TR_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $31\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_TR_write(UINT32 val) -{ - __asm__ - ( - "mtc0 %[val], $31\n" - : - : [val] "r" (val) - ); -} - -UINT32 CP0_PRID_read(void) -{ - UINT32 result; - - __asm__ - ( - "mfc0 %[val], $15\n" - : [val] "=r" (result) - ); - - return result; -} - -void CP0_TR_write_ptr(UINT32* pPtr) -{ - __asm__ - ( - "swc0 $31, 0(%[pPtr])\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void CP0_TR_read_ptr(UINT32* pPtr) -{ - __asm__ - ( - "lwc0 $31, 0(%[pPtr])\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void ICACHE_invalidate_all(void) -{ - __asm__ - ( - "cop0 32\n" - ); -} - -void ICACHE_invalidate_at(UINT32* pPtr) -{ - __asm__ - ( - "mtc0 %[pPtr], $31\n" - "cop0 33\n" - : - : [pPtr] "r" (pPtr) - ); -} - -void DCACHE_invalidate_all(void) -{ - __asm__ - ( - "cop0 34\n" - ); -} - -void DCACHE_invalidate_at(UINT32* pPtr) -{ - __asm__ - ( - "mtc0 %[pPtr], $31\n" - "cop0 35\n" - : - : [pPtr] "r" (pPtr) - ); -} - -// --------------------------------------------------------------------------------- -int UART0_readchar(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart0_data; - - if (0x10 & *pUART_stat) - return (*pUART_data & 0xFF); - - return -1; -} - -void UART0_writechar(char c) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart0_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart0_data; - - while((0x01 & *pUART_stat) != 0); - - *pUART_data = (UINT32)c; -} - -int UART1_readchar(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart1_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart1_data; - - if (0x10 & *pUART_stat) - return (*pUART_data & 0xFF); - - return -1; -} - -void UART1_writechar(char c) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart1_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart1_data; - - while((0x01 & *pUART_stat) != 0); - - *pUART_data = (UINT32)c; -} - -int UART2_readchar(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart2_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart2_data; - - if (0x10 & *pUART_stat) - return (*pUART_data & 0xFF); - - return -1; -} - -void UART2_writechar(char c) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart2_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart2_data; - - while((0x01 & *pUART_stat) != 0); - - *pUART_data = (UINT32)c; -} - -char readchar(void) -{ - int c; - - do - { - c = UART0_readchar(); - - } while(c < 0); - - return (char)c; -} - -void writechar(char c) -{ - UART0_writechar(c); -} - -void _ser_putchar(char c) -{ - if (c == 0x0A) - { - writechar(0x0D); - } - writechar(c); -} - -void cg_writechar(char c) -{ - volatile UINT32 *pCG_data = (UINT32*)sys_vga_data; - - while (!(*pCG_data & 1)); - *pCG_data = (UINT32)c; -} - -void cg_clr_line(void) -{ - volatile UINT32 *pCG_clrline = (UINT32*)sys_vga_clrline; - - while (!(*pCG_clrline & 1)); - *pCG_clrline = 1; -} - -void _cg_putchar(char c) -{ - if (c == 0x0A) - { - cg_writechar(0x0D); - } - cg_writechar(c); - if (c == 0x0A) - cg_clr_line(); - -} - -void _exit (int exitcode) -{ - fflush(stdout); - fflush(stderr); - while(1); -} - -void sleep(unsigned ms) -{ - unsigned stop; - struct tms t; - - times(&t); - stop = t.tms_utime + ms; - - do - { - times(&t); - } while (t.tms_utime < stop); - -} - - -int getrusage(int who, struct rusage *usage) -{ - volatile long *pReg_usec = (long*)sys_timer_usec; - volatile long *pReg_sec = (long*)sys_timer_sec; - - // who: RUSAGE_SELF or RUSAGE_CHILDREN - usage->ru_utime.tv_usec = *pReg_usec; - usage->ru_utime.tv_sec = *pReg_sec; - usage->ru_stime.tv_usec = *pReg_usec; - usage->ru_stime.tv_sec = *pReg_sec; -} - -clock_t times(struct tms *buffer) -{ - volatile long *pReg_usec = (long*)sys_timer_usec; - volatile long *pReg_sec = (long*)sys_timer_sec; - long sec; - long usec; - - sec = *pReg_sec; - usec = *pReg_usec; - - if (buffer) - { - buffer->tms_utime = sec*1000 + usec/1000; - buffer->tms_stime = 0; - buffer->tms_cutime = 0; - buffer->tms_cstime = 0; - } - - return (clock_t)sec; -} - -int gettimeofday(struct timeval *tp, void *tzp) -{ - volatile long *pReg_usec = (long*)sys_timer_usec; - volatile long *pReg_sec = (long*)sys_timer_sec; - - if (tp) - { - tp->tv_sec = *pReg_sec; - tp->tv_usec = *pReg_usec; - } - - return 0; -} - -int settimeofday(const struct timeval *tp, const struct timezone *tzp) -{ - volatile long *pReg_usec = (long*)sys_timer_usec; - volatile long *pReg_sec = (long*)sys_timer_sec; - div_t res; - - res = div(tp->tv_usec, 1E6); - - if (tp) - { - *pReg_usec = res.rem; - *pReg_sec = tp->tv_sec + res.quot; - } - - return 0; -} - -caddr_t sbrk(int incr) -{ - extern char end; - extern char stack_ptr; - static char *heap_end; - char *prev_heap_end; - - if (heap_end == 0) - { - heap_end = &end; - } - - prev_heap_end = heap_end; - if (heap_end + incr > &stack_ptr) - { -// sputs("Heap and stack collision\n"); -// sputs("Stack Ptr = ");print_word(&stack_ptr);sputs("\n"); -// sputs("Heap end = ");print_word(heap_end);sputs("\n"); -// sputs("Increment = ");print_word(incr);sputs("\n"); - exit(1); - } - heap_end += incr; - return (caddr_t) prev_heap_end; -} - -int fstat(int file, struct stat *st) -{ -// sputs("fstat\n"); - st->st_mode = S_IFCHR; - st->st_blksize = 0; - return 0; -} - -int lseek(int file, int ptr, int dir) -{ -// sputs("lseek\n"); - errno = ESPIPE; - return -1; -} - -int open(const char *name, int flags, int mode) -{ -// sputs("open\n"); - errno = EIO; - return -1; -} - -int close(int file) -{ -// sputs("close\n"); - return 0; -} - -int read(int file, char *ptr, int len) -{ - int i; - char c; - -// sputs("read\n"); - i = 0; - while (i < len) - { - c = readchar(); - if ((c == 0x0D) || (c == 0x0A)) - { - writechar(0x0D); - writechar(0x0A); - if (i==0) - continue; - - ptr[i++] = c; - break; - } - else - { - ptr[i++] = c; - writechar(c); - } - } - return i; -} - -int write(int file, char *ptr, int len) -{ - int i = 0; - - if (file == 1) - { - for (i=0; i < len; i++) - STDOUT_FUNCTION(*ptr++); - } - if (file == 2) - { - for (i=0; i < len; i++) - STDERR_FUNCTION(*ptr++); - } - return i; -} - -int isatty(int file) -{ -// sputs("Isatty()\n"); - return 1; -} - -int sputs(char *pStr) -{ - char *start; - start = pStr; - - while(*pStr) - _putchar(*(pStr++)); - - return pStr - start; -} - -void print_byte(char byte) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 2; i++) - { - nibble = (char)((byte >> 4) & 0xF); - byte <<= 4; - - if (nibble < 10) - c = nibble + '0'; - else - c = nibble + 'A' - 10; - - _putchar(c); - } -} - -void print_word(int word) -{ - int i; - unsigned char c, nibble; - - for (i=0; i < 4; i++) - { - c = (char) (word >> 24); - print_byte(c); - word <<= 8; - } -} - -// --------------------------------------------------------------------------------- -// PrintBuffer8() -// Prints byte buffer as hex and ascii interpretation -// --------------------------------------------------------------------------------- -// _Parameters : -// pBuf: : IN: Buffer to display -// nbpr : Number of bytes per row to display -// len : Length of input buffer -// _Return: none -// -// --------------------------------------------------------------------------- -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len) -{ - memdump(pBuf, 1, nbpr, len); -} - -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len) -{ - int i, j, cnt_hex, cnt_asc, base; - unsigned char c; - - i = j = 0; - cnt_hex = len; - cnt_asc = len; - base = 0; - if (!print_offset_only) - base = (int)pBuf; - - do - { - print_word(base + i); - sputs(": "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_hex) - { - print_byte(pBuf[i+j]); - sputs(" "); - cnt_hex--; - } - else - { - sputs(" "); - break; - } - - } - - sputs(" "); - for (j=0; j < num_bytes_per_row; j++) - { - if (cnt_asc) - { - c = pBuf[i+j]; - if((c < 0x20) || (c > 0x7F)) - c = '.'; - - _putchar(c); - cnt_asc--; - } - else - { - sputs(" "); - break; - } - } - sputs("\n"); - i += num_bytes_per_row; - - } while (cnt_hex); -} - diff --git a/lib/CPUs/MIPS/bsp/examples/libsys.h b/lib/CPUs/MIPS/bsp/examples/libsys.h deleted file mode 100644 index 8079df6..0000000 --- a/lib/CPUs/MIPS/bsp/examples/libsys.h +++ /dev/null @@ -1,134 +0,0 @@ -#ifndef LIBSYS_H -#define LIBSYS_H - -// --------------------------------------------------------- -// Types -// --------------------------------------------------------- -#define INT8 signed char -#define INT16 signed short -#define INT32 signed int -#define INT64 signed long long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned int -#define UINT64 unsigned long long -#define INT INT32 -#define UINT UINT32 -#define FLOAT32 float -#define FLOAT64 double - -#define NO_ERROR LSYS_SUCCESS -#define ERROR LSYS_ERR_BASE -#define LSYS_SUCCESS 0 -#define LSYS_ERR_BASE 0x80000000 - -#define IS_ERROR(e) ((e & LSYS_ERR_BASE) == LSYS_ERR_BASE) - -#define sys_gpio0 0xA0000000 -#define sys_gpio1 0xA0000004 -#define sys_led_port sys_gpio0 -#define sys_usb_ctrl sys_gpio1 -#define sys_timer_usec 0xA0000008 -#define sys_timer_sec 0xA000000C - -#define sys_itim_ctrl 0xA0000018 -#define sys_itim_stat 0xA000001C -#define sys_itim0_cnt 0xA0000020 -#define sys_itim1_cnt 0xA0000024 -#define sys_itim2_cnt 0xA0000028 -#define sys_itim3_cnt 0xA000002C -#define sys_itim0_cmp 0xA0000030 -#define sys_itim1_cmp 0xA0000034 -#define sys_itim2_cmp 0xA0000038 -#define sys_itim3_cmp 0xA000003C - -#define sys_uart_data sys_uart0_data -#define sys_uart_stat sys_uart0_stat -#define sys_uart_baud sys_uart0_baud -#define sys_uart0_data 0xA0010000 -#define sys_uart0_stat 0xA0010004 -#define sys_uart0_baud 0xA0010008 -#define sys_uart1_data 0xA0010100 -#define sys_uart1_stat 0xA0010104 -#define sys_uart1_baud 0xA0010108 -#define sys_uart2_data 0xA0010200 -#define sys_uart2_stat 0xA0010204 -#define sys_uart2_baud 0xA0010208 -#define sys_usb_data 0xA0020000 -#define sys_usb_mbx 0xA0020004 -#define sys_usb_addr 0xA0020008 -#define sys_usb_status 0xA002000C -#define sys_vga_data 0xA0030004 -#define sys_vga_posx 0xA0030008 -#define sys_vga_posy 0xA0030010 -#define sys_vga_clrscr 0xA0030020 -#define sys_vga_clrline 0xA0030040 -#define sys_vga_cgcol 0xA0030080 -#define sys_vga_mctrl 0xA0030100 -#define sys_vga_moffs 0xA0030200 -#define sys_ac97_stat 0xA0040000 -#define sys_ac97_ctrl 0xA0040000 -#define sys_ac97_acstat 0xA0040400 -#define sys_ac97_acctrl 0xA0040600 -#define sys_ac97_pcm 0xA0040800 -#define sys_ac97_wavin sys_ac97_pcm -#define sys_ac97_wavout sys_ac97_pcm -#define sys_flash_io 0xA4000000 -#define sys_flash_mem 0x00000000 -#define sys_ssram_io 0xA8000000 - -//#define STDOUT_FUNCTION _cg_putchar // Video character -//#define STDERR_FUNCTION _putchar // Serial output - -#ifndef _putchar -#define _putchar _ser_putchar // Serial output -#endif - -#ifndef STDOUT_FUNCTION -#define STDOUT_FUNCTION _ser_putchar // Serial output -#endif -#ifndef STDERR_FUNCTION -#define STDERR_FUNCTION _ser_putchar // Serial output -#endif - - -UINT32 CP0_SR_read(void); -void CP0_SR_write(UINT32 val); -UINT32 CP0_CR_read(void); -void CP0_CR_write(UINT32 val); -UINT32 CP0_PRID_read(void); -UINT32 CP0_TR_read(void); -void CP0_TR_write(UINT32 val); -void CP0_TR_write_ptr(UINT32* pPtr); -void CP0_TR_read_ptr(UINT32* pPtr); -void ICACHE_invalidate_all(void); -void ICACHE_invalidate_at(UINT32* pPtr); -void DCACHE_invalidate_all(void); -void DCACHE_invalidate_at(UINT32* pPtr); - -#define CALC_BAUD(b) \ - ((UINT32)((float)CPU_FREQ_HZ/(16*b) + 0.5f) - 1); - -#define UART0_setbaud(b) \ - *((UINT32*)sys_uart0_baud) = CALC_BAUD(b); - -#define UART1_setbaud(b) \ - *((UINT32*)sys_uart1_baud) = CALC_BAUD(b); - -#define UART2_setbaud(b) \ - *((UINT32*)sys_uart2_baud) = CALC_BAUD(b); - -char readchar(void); -void writechar(char c); -int write(int file, char *ptr, int len); -int sputs(char *pStr); -void print_byte(char byte); -void print_word(int word); -void _exit (int exitcode); -void sleep(unsigned ms); - -void PrintBuffer8(UINT8 *pBuf, int nbpr, int len); -void memdump(UINT8 *pBuf, int print_offset_only, int num_bytes_per_row, int len); - -#endif // LIBSYS_H - diff --git a/lib/CPUs/MIPS/bsp/examples/life.c b/lib/CPUs/MIPS/bsp/examples/life.c deleted file mode 100644 index 4da1708..0000000 --- a/lib/CPUs/MIPS/bsp/examples/life.c +++ /dev/null @@ -1,249 +0,0 @@ -/* life.c - demonstrator for later Mips+LCD game of life - * - * 23.03.06 - MACRO-based version - * 22.02.06 - new file - */ - -//#include "ks0108.h" - -#include -#include -#include -#include "libsys.h" - - -#define NX 200 // 70 // 128 // 48 // 128 -#define NY 150 // 31 // 64 // 27 // 64 - -#define SCREEN_X 800 -#define SCREEN_Y 600 - -#define SCALE_X (4) -#define SCALE_Y (4) -#define OFFSET_X ((SCREEN_X-(SCALE_X*NX))/2) -#define OFFSET_Y ((SCREEN_Y-(SCALE_Y*NY))/2) - -// OCCUPIED must be uneven, EMPTY even. -#define OCCUPIED 0x77771111 -#define EMPTY 0xeeee0000 - -#define MATRIX( row, col ) (*(matrix + (NX*col) + row )) -#define FUTURE( row, col ) (*(future + (NX*col) + row )) - -UINT32 *g_gx_buff; - -int clock_lfsr32() -{ - return rand(); -} - - -/* return a pseudo-random integer in the range 0..1023 */ -int random1023() { - int tmp; - - tmp = clock_lfsr32(); - return tmp & 0x000003ff; -} - -typedef struct _scolor_t -{ - UINT8 r, g, b, a; -} __attribute__ ((__packed__)) color_t; - - -void DrawPixel(UINT32 x, UINT32 y, color_t *pColor) -{ - int i, j; - for (i=0; i < SCALE_Y; i++) - for (j=0; j < SCALE_X; j++) - g_gx_buff[(OFFSET_X+SCALE_X*x+j) + SCREEN_X*(OFFSET_Y+SCALE_Y*y+i)] = *((UINT32*)pColor); -} - - -/* MSB/LSB in y-Richtung vertauscht */ -void displayBoard1( int* matrix ) -{ - int x, y; - int mask, accu; - UINT32 color; - - for( x=0; x < NX; x++ ) - { - mask = 0x80; - accu = 0x00; - for( y=0; y < NY; y++ ) - { - color = (UINT32)-(MATRIX(x,y) & 0x1); - DrawPixel(x, y, (color_t*)&color); -// if (MATRIX( x, y ) != OCCUPIED) -// { -// accu |= mask; -// } -// mask = mask >> 1; - -// color = 0; -// DrawPixel(x, (y>>3), (color_t*)&color); -// if (mask == 0) -// { -// color = accu; -// DrawPixel(x, (y>>3), (color_t*)&color); -// mask = 0x80; -// accu = 0x00; -// } - } -// color = accu; -// DrawPixel(x, (y>>3), (color_t*)&color); - - } -// *(matrix-15) = 0xdead0000; -// *(matrix-16) = *(matrix-16) + 1; -} - -void initializeBoard( int* matrix ) { - int x, y; - for( x=0; x < NX; x++ ) { - for( y=0; y < NY; y++ ) { - int d = random1023(); - if (d > 920) MATRIX( x, y ) = OCCUPIED; - else MATRIX( x, y ) = EMPTY; - } - } -} - - -int countNeighbors( int* matrix, int i, int j ) { - int im = i-1; - int ip = i+1; - - int jm = j-1; - int jp = j+1; - - int n = 0; - // wrap-around - if (ip >= NX) ip = 0; - if (jp >= NY) jp = 0; - - if (im < 0) im = NX-1; - if (jm < 0) jm = NY-1; - - // check eight neighbors - n += MATRIX(im, jm ) & 0x1; // nw - n += MATRIX(im, j ) & 0x1; // west - n += MATRIX(im, jp ) & 0x1; // sw - - n += MATRIX(i, jm ) & 0x1; // north - // n += MATRIX(i, j ) & 0x1; // center - n += MATRIX(i, jp ) & 0x1; // south - - n += MATRIX(ip, jm ) & 0x1; // ne - n += MATRIX(ip, j ) & 0x1; // east - n += MATRIX(ip, jp ) & 0x1; // se - - return n; -} - - -/** - * the actual game of life algorithm: cell is born when three neighbors, - * survives when exactly two live neighbors, dies otherwise. - */ -void nextGeneration( int* matrix, int* future ) { - int i, j; - int lifes = 0; - - for( i=0; i < NX; i++ ) { - for( j=0; j < NY; j++ ) { - // count neighbors - int n = countNeighbors( matrix, i, j ); - - //if ((n != 0) && (random1023() > 990)) { // some slight random offset - // if (random1023() > 500) FUTURE(i,j) = OCCUPIED; - // else FUTURE(i,j) = EMPTY; - //} - // else if (n == 3) FUTURE(i,j) = OCCUPIED; - - if (n == 3) FUTURE(i,j) = OCCUPIED; - else if ((n == 2) && (MATRIX(i,j) == OCCUPIED)) FUTURE(i,j) = OCCUPIED; - else FUTURE(i,j) = EMPTY; - - if (FUTURE(i,j) == OCCUPIED) lifes++; - } - } - // generation ++; - - // avoid extinction :-) - if (lifes < 10) { - // printf( "CREATING A NEW POPULATION\n\n\n" ); - initializeBoard( matrix ); - } - else { // swap buffers: C PROHIBITS ASSIGNING TO ARRAY TYPES - for( i=0; i < NX; i++ ) { - for( j=0; j < NY; j++ ) { - MATRIX(i,j) = FUTURE(i,j); - } - } - } -} - -void gx_init(void) -{ - volatile UINT32 *pVGA_mctrl = (UINT32*)sys_vga_mctrl; - volatile UINT32 *pVGA_moffs = (UINT32*)sys_vga_moffs; - - sleep(500); - - g_gx_buff = (UINT32*)malloc(SCREEN_X*SCREEN_Y*sizeof(UINT32)); - memset(g_gx_buff, 0, SCREEN_X*SCREEN_Y*sizeof(UINT32)); - printf("g_gx_buff : %8.8X\n", (UINT32)g_gx_buff); - - *pVGA_mctrl = 1; - *pVGA_moffs = (UINT32)g_gx_buff; - -} - -int main( int argc, char* argv[] ) { - - int* ptr, cnt = 0; - - int* matrix; - int* future; - volatile UINT32 *pBtn = (UINT32*)sys_gpio0; - - // lcdEnableDisplay( 1 ); - // lcdSetColor( 1 ); - // lcdSetPixel( 0, 0 ); - // lcdSetPixel( 3, 5 ); - - // if we have stdlib: - matrix = (void*) malloc( NX*NY*sizeof(int) ); - future = (void*) malloc( NX*NY*sizeof(int) ); - - - gx_init(); - -// matrix = (void *) 0x00004000; -// future = (void *) 0x00014000; - - // init_lfsr32( 0xcafebabe ); - // init_lfsr32( 0x13 ); - - srand(clock()); - initializeBoard( matrix ); - - while( 1 ) - { - - if (*pBtn) - { - srand(clock()); - initializeBoard( matrix ); - cnt = 0; - } - sputs("Generation #"); print_word(cnt++); sputs("\n"); - displayBoard1( matrix ); - nextGeneration( matrix, future ); - } - - // return 0 -} diff --git a/lib/CPUs/MIPS/bsp/examples/link.ld b/lib/CPUs/MIPS/bsp/examples/link.ld deleted file mode 100644 index 44b93b3..0000000 --- a/lib/CPUs/MIPS/bsp/examples/link.ld +++ /dev/null @@ -1,224 +0,0 @@ -/* Script for -z combreloc: combine and sort reloc sections */ -OUTPUT_FORMAT("elf32-littlemips", "elf32-bigmips", - "elf32-littlemips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SEARCH_DIR("."); -SEARCH_DIR("/usr/local/mipsel-elf/lib:/usr/local/mipsel-elf/lib/eb"); -SEARCH_DIR("/usr/local/lib/gcc/mipsel-elf/4.3.3:/usr/local/lib/gcc/mipsel-elf/4.3.3/eb"); - -stack_ptr = 0x7FFFEFF0; -baudrate = 0x0D; -sys_led_port = 0xA0000000; -sys_uart_data = 0xA0010000; -sys_uart_stat = 0xA0010004; -sys_uart_baud = 0xA0010008; -sys_timer_usec = 0xA000008; -sys_timer_sec = 0xA000000C; - -STARTUP(startup.o) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - PROVIDE (__executable_start = 0x40000000); . = 0x40000000; - .start __executable_start : - { - start = ALIGN(2); - entry = ALIGN(2); - _entry = ALIGN(2); - __entry = ALIGN(2); - *(.start) - } - /* Kernel text with low-level exception handler */ - .exc_vector __executable_start + 0x080 : - { - _exc_vect_start = .; - *(.exc_vect) - _exc_vect_end = .; - } - .init : - { - KEEP (*(.init)) - } =0 - .plt : { *(.plt) } - .text : - { - _ftext = . ; - *(.text .stub .text.* .gnu.linkonce.t.*) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - *(.mips16.fn.*) *(.mips16.call.*) - } =0 - .fini : - { - KEEP (*(.fini)) - } =0 - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } - .rodata1 : { *(.rodata1) } - .sdata2 : - { - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - } - .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } - .eh_frame_hdr : { *(.eh_frame_hdr) } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } - /* Adjust the address for the data segment. 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Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. 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Align after .bss to ensure correct alignment even if the - .bss section disappears because there are no input sections. - FIXME: Why do we need it? When there is no .bss section, we don't - pad the .data section. */ - . = ALIGN(. != 0 ? 32 / 8 : 1); - } - . = ALIGN(32 / 8); - . = ALIGN(32 / 8); - _end = .; PROVIDE (end = .); - . = DATA_SEGMENT_END (.); - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - /* DWARF 3 */ - .debug_pubtypes 0 : { *(.debug_pubtypes) } - .debug_ranges 0 : { *(.debug_ranges) } - .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } - .mdebug.abiN32 : { KEEP(*(.mdebug.abiN32)) } - .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } - .mdebug.abiO64 : { KEEP(*(.mdebug.abiO64)) } - .mdebug.eabi32 : { KEEP(*(.mdebug.eabi32)) } - .mdebug.eabi64 : { KEEP(*(.mdebug.eabi64)) } - .gcc_compiled_long32 : { KEEP(*(.gcc_compiled_long32)) } - .gcc_compiled_long64 : { KEEP(*(.gcc_compiled_long64)) } - /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) } -} diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.c b/lib/CPUs/MIPS/bsp/examples/mipsdis.c deleted file mode 100644 index 2dceda3..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mipsdis.c +++ /dev/null @@ -1,625 +0,0 @@ -/* +----------------------------------------------------------------+ */ -/* | Copyright (c) 1994 Stanford University. | */ -/* | All Rights Reserved. | */ -/* | | */ -/* | This software is distributed with *ABSOLUTELY NO SUPPORT* | */ -/* | and *NO WARRANTY*. Use or reproduction of this code for | */ -/* | commerical gains is strictly prohibited. Otherwise, you | */ -/* | are given permission to use or modify this code as long | */ -/* | as you do not remove this notice. | */ -/* +----------------------------------------------------------------+ */ -/* --------------------------------------------------- */ -/* | Copyright (c) 1986 MIPS Computer Systems, Inc. | */ -/* | All Rights Reserved. | */ -/* --------------------------------------------------- */ - -/* - * Copyright 1985 by MIPS Computer Systems, Inc. - */ - -/* TORCH disassembler */ -/* derived from MIPS instruction dissassembler by PGL October 91 */ - -#include -#include -#include "mipsdis.h" - -#define false 0 -#define true 1 -typedef int boolean; -char *strcat(); - -#define ZERO 0 - -#define COMPILER_NAMES tdis_reg_names[0] -#define HARDWARE_NAMES tdis_reg_names[1] -#define ASSEMBLER_NAMES tdis_reg_names[2] -#define DIS_REG_NAMES(x) tdis_reg_names[x] - -union extension_byte { - unsigned char byte; - struct { /* extension byte bits in little-endian order */ -#if (defined __MIPSEB || defined _MIPSEB || defined MIPSEB) - unsigned reserved:1; - unsigned dyn_nop:1; - unsigned rs_boost:2; - unsigned rt_boost:2; - unsigned rd_boost:2; -#elif (defined __MIPSEL || defined _MIPSEL || defined MIPSEL) - unsigned rd_boost:2; - unsigned rt_boost:2; - unsigned rs_boost:2; - unsigned dyn_nop:1; - unsigned reserved:1; -#endif /*MIPSEB*/ - } e; -}; - -#define blez_op_T blez_op -#define blez_op_N (blez_op | 0x10) -#define bgtz_op_T bgtz_op -#define bgtz_op_N (bgtz_op | 0x10) -#define beq_op_T beq_op -#define beq_op_N (beq_op | 0x10) -#define bne_op_T bne_op -#define bne_op_N (bne_op | 0x10) -#define bc_op_T bc_op -#define bc_op_N (bc_op | 0x02) - -static char *op_name[64] = { -/* 0 */ "special", "regimm","j", "jal", "beq", "bne", "blez", "bgtz", -/* 8 */ "addi", "addiu","slti", "sltiu","andi", "ori", "xori", "lui", -/*16 */ "cop0", "cop1", "cop2", "cop3", "beql","bnel","blezl","bgtzl", -/*24 */ "op60", "op64", "op68", "op6c", "op70", "op74", "op78", "op7c", -/*32 */ "lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "ld", -/*40 */ "sb", "sh", "swl", "sw", "opb0", "opb4", "swr", "sd", -/*48 */ "lwc0", "lwc1", "lwc2", "lwc3", "ldc0", "ldc1", "ldc2", "ldc3", -/*56 */ "swc0", "swc1", "swc2", "swc3", "sdc0", "sdc1", "sdc2", "sdc3" -}; - -static char *spec_name[64] = { -/* 0*/ "sll", "spec01","srl", "sra", "sllv", "spec05","srlv","srav", -/* 8*/ "jr", "jalr", "spec12","spec13","syscall","break","vcall","spec17", -/*16*/ "mfhi", "mthi", "mflo", "mtlo", "spec24","spec25","spec26","spec27", -/*24*/ "mult", "multu","div", "divu", "spec34","spec35","spec36","spec37", -/*32*/ "add", "addu", "sub", "subu", "and", "or", "xor", "nor", -/*40*/ "spec50","spec51","slt","sltu", "spec54","spec55","spec56","spec57", -/*48*/ "spec60","spec61","spec62","spec63","spec64","spec65","spec66","spec67", -/*56*/ "spec70","spec71","spec72","spec73","spec74","spec75","spec76","spec77" -}; - -static char *bcond_name[32] = { - "bltz", - "bgez", - "bltzl", - "bgezl", - "bcond04", - "bcond05", - "bcond06", - "bcond07", - "tgei", - "tgeiu", - "tlti", - "tltiu", - "teqi", - "bcond0d", - "tnei", - "bcond0f", - "bltzal", - "bgezal", - "bltzall", - "bgezall", - "bcond14", - "bcond15", - "bcond16", - "bcond17", - "bcond18", - "bcond19", - "bcond1a", - "bcond1b", - "bcond1c", - "bcond1d", - "bcond1e", - "bcond1f" -}; - -static char *cop1_name[64] = { -/* 0 */ "add", "sub", "mul", "div", "sqrt", "abs", "mov", "neg", -/* 8 */ "fop08","fop09","fop0a","fop0b","fop0c","fop0d","fop0e","fop0f", -/*16 */ "fop10","fop11","fop12","fop13","fop14","fop15","fop16","fop17", -/*24 */ "fop18","fop19","fop1a","fop1b","fop1c","fop1d","fop1e","fop1f", -/*32 */ "cvt.s","cvt.d","cvt.e","fop23","cvt.w","fop25","fop26","fop27", -/*40 */ "fop28","fop29","fop2a","fop2b","fop2c","fop2d","fop2e","fop2f", -/*48 */ "c.f", "c.un","c.eq","c.ueq","c.olt","c.ult","c.ole","c.ule", -/*56 */ "c.sf","c.ngle","c.seq","c.ngl","c.lt","c.nge","c.le","c.ngt" -}; - -static char *fmt_name[16] = { - "s", "d", "e", "q", - "w", "fmt5", "fmt6", "fmt7", - "fmt8", "fmt9", "fmta", "fmtb", - "fmtc", "fmtd", "fmte", "fmtf" -}; - -/* public */ -/* Three sets of commonly used register names */ -const char *tdis_reg_names[3][64] = { - { /* compiler names */ - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", - "zero.B","at.B","v0.B", "v1.B", "a0.B", "a1.B", "a2.B", "a3.B", - "t0.B", "t1.B", "t2.B", "t3.B", "t4.B", "t5.B", "t6.B", "t7.B", - "s0.B", "s1.B", "s2.B", "s3.B", "s4.B", "s5.B", "s6.B", "s7.B", - "t8.B", "t9.B", "k0.B", "k1.B", "gp.B", "sp.B", "s8.B", "ra.B" - }, - { /* hardware names */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "gp", "sp", "r30", "r31", - "r0.B", "r1.B", "r2.B", "r3.B", "r4.B", "r5.B", "r6.B", "r7.B", - "r8.B", "r9.B", "r10.B","r11.B","r12.B","r13.B","r14.B","r15.B", - "r16.B","r17.B","r18.B","r19.B","r20.B","r21.B","r22.B","r23.B", - "r24.B","r25.B","r26.B","r27.B","gp.B", "sp.B", "r30.B","r31.B" - }, - { /* assembler names */ - "$0", "$at", "$2", "$3", "$4", "$5", "$6", "$7", - "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", - "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", - "$24", "$25", "$26", "$27", "$gp", "$sp", "$30", "$31", - "$0.B", "$at.B","$2.B", "$3.B", "$4.B", "$5.B", "$6.B", "$7.B", - "$8.B", "$9.B", "$10.B","$11.B","$12.B","$13.B","$14.B","$15.B", - "$16.B","$17.B","$18.B","$19.B","$20.B","$21.B","$22.B","$23.B", - "$24.B","$25.B","$26.B","$27.B","$gp.B","$sp.B","$30.B","$31.B" - } -}; - -static char *c0_opname[64] = { - "c0op0","tlbr","tlbwi","c0op3","c0op4","c0op5","tlbwr","c0op7", - "tlbp","c0op9","c0op10","c0op11","c0op12","c0op13","c0op14","c0op15", - "rfe","c0op17","c0op18","c0op19","c0op20","c0op21","c0op22","c0op23", - "c0op24","c0op25","c0op26","c0op27","c0op28","c0op29","c0op30","c0op31", - "c0op32","c0op33","c0op34","c0op35","c0op36","c0op37","c0op38","c0op39", - "c0op40","c0op41","c0op42","c0op43","c0op44","c0op45","c0op46","c0op47", - "c0op48","c0op49","c0op50","c0op51","c0op52","c0op53","c0op54","c0op55", - "c0op56","c0op57","c0op58","c0op59","c0op60","c0op61","c0op62","c0op63" -}; - -static char *c0_reg[32] = { - "index","random","tlblo","c0r3","context","c0r5","c0r6","c0r7", - "badvaddr","c0r9","tlbhi","epcn","sr", "cause","epc", "c0r15", - "c0r16","c0r17","c0r18","c0r19","c0r20","c0r21","c0r22","c0r23", - "c0r24","c0r25","c0r26","c0r27","c0r28","c0r29","c0r30","c0r31" -}; - -/* Remember the options set by dis_init */ -//#define ADDR_DEFAULT "%#010x:\t" -#define ADDR_DEFAULT 0 -//#define VALUE_DEFAULT "%#010x\t" -#define VALUE_DEFAULT 0 -#define NAME_DEFAULT COMPILER_NAMES -static struct { - char *addr_format; - char *value_format; - const char **reg_names; - int print_jal_targets; -} save = { - ADDR_DEFAULT, - VALUE_DEFAULT, - NAME_DEFAULT, - true -}; - -/* Update regmask to reflect the use of this general-purpose (not fp) - register, and return its name */ -static const char * -register_name(ireg, boosted, regmask) -unsigned ireg, *regmask; -int boosted; -{ - if (!boosted) - *regmask |= (1 << ireg); - return save.reg_names[boosted ? ireg + 32 : ireg]; -} - -/* public -- see dissassembler.h */ -int -tdisasm(buffer, address, iword, ext, regmask, symbol_value, ls_register) -char *buffer; -unsigned char ext; /* extension byte */ -unsigned address, iword, *regmask, *symbol_value, *ls_register; -{ - int return_value = 0; - char *bufptr = buffer; - boolean do_b_displacement = false; - boolean do_loadstore = false; - union mips_instruction i; - union extension_byte e; - - *bufptr = 0; - i.word = iword; - e.byte = ext; - *regmask = *symbol_value = *ls_register = 0; - - /* Put out the address and hex value of the instruction, - leaving bufptr set at the end */ - if (save.addr_format) { - sprintf(bufptr, save.addr_format, address); - bufptr += strlen(bufptr); - } - if (save.value_format) { - sprintf(bufptr, save.value_format, iword); - bufptr += strlen(bufptr); - } - - /* check for dynamic NOP */ - if (e.e.dyn_nop) { - strcat(bufptr, "D."); - bufptr += 2; - } - - /* decode the instruction */ - switch (i.j_format.opcode) { - - case spec_op: - - if (i.word == 0x20) { - strcat(bufptr, "nop"); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - break; - } else if (i.r_format.func == addu_op && i.r_format.rt == ZERO) { - sprintf(bufptr, "move%s\t%s,%s", - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - bufptr += strlen(bufptr); - break; - } - strcat(bufptr, spec_name[i.r_format.func]); - if (e.e.rd_boost) - strcat(bufptr, ".B"); - bufptr += strlen(bufptr); - - switch (i.r_format.func) { - case sll_op: - case srl_op: - case sra_op: - sprintf(bufptr, "\t%s,%s,%d", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - i.r_format.re); - break; - case sllv_op: - case srlv_op: - case srav_op: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mfhi_op: - case mflo_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask)); - break; - case jalr_op: - return_value = 3; - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - *ls_register = i.r_format.rs; - break; - case jr_op: - return_value = 3; - *ls_register = i.r_format.rs; - /* fall through */ - case mtlo_op: - case mthi_op: - sprintf(bufptr, "\t%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask)); - break; - case mult_op: - case multu_op: - case div_op: - case divu_op: - sprintf(bufptr, "\t%s,%s", - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - case syscall_op: - break; - case break_op: - case vcall_op: - { - char *format = "\t%d"; - unsigned op2 = i.r_format.rd * 32 + i.r_format.re; - - if (op2) - format = "\t%d,%d"; - sprintf(bufptr, format, i.r_format.rs*32+i.r_format.rt, - op2); - } - break; - default: - sprintf(bufptr, "\t%s,%s,%s", - register_name(i.r_format.rd, e.e.rd_boost, regmask), - register_name(i.r_format.rs, e.e.rs_boost, regmask), - register_name(i.r_format.rt, e.e.rt_boost, regmask)); - break; - }; - break; - - case bcond_op: - sprintf(bufptr, "%s%s\t%s,", - bcond_name[i.i_format.rt], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - - case blez_op_T: - case bgtz_op_T: - case blez_op_N: - case bgtz_op_N: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - do_b_displacement = true; - break; - case beq_op_T: - case beq_op_N: - if (i.i_format.rs == ZERO && i.i_format.rt == ZERO) { - strcat(bufptr, "b"); - if (i.j_format.opcode == beq_op_T) - strcat(bufptr, ".T"); - else - strcat(bufptr, ".N"); - if (e.e.rd_boost) - strcat(bufptr, ".B\t"); - else - strcat(bufptr, "\t"); - do_b_displacement = true; - break; - } - /* fall through */ - case bne_op_T: - case bne_op_N: - sprintf(bufptr, "%s%s\t%s,%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rs, e.e.rs_boost, regmask), - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_b_displacement = true; - break; - - case cop0_op: - case cop1_op: - case cop2_op: - case cop3_op: - { - unsigned which_cop = i.j_format.opcode - cop0_op; - char *f_or_r = "rf"; - - switch (i.r_format.rs) { - case bc_op_T: - sprintf(bufptr, "bc%d%c.T%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case bc_op_N: - sprintf(bufptr, "bc%d%c.N%s\t", which_cop, - "ft"[i.r_format.rt], - e.e.rd_boost ? ".B" : ""); - do_b_displacement = true; - break; - case mtc_op: - if (which_cop == 0) - sprintf(bufptr, "mtc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mtc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case mfc_op: - if (which_cop == 0) - sprintf(bufptr, "mfc%d%s\t%s,%s", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - c0_reg[i.f_format.rd]); - else - sprintf(bufptr, "mfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost,regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case cfc_op: - sprintf(bufptr, "cfc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - case ctc_op: - sprintf(bufptr, "ctc%d%s\t%s,%c%d", which_cop, - e.e.rd_boost ? ".B" : "", - register_name(i.r_format.rt, e.e.rt_boost, regmask), - f_or_r[(which_cop == 1)], - i.f_format.rd); - break; - default: - if (which_cop != 1) - sprintf(bufptr, "c0%s\t%s", e.e.rd_boost ? ".B" : "", - c0_opname[i.f_format.func]); - else - { - sprintf(bufptr, "%s.%s%s\t", - cop1_name[i.f_format.func], - fmt_name[i.f_format.fmt], - e.e.rd_boost ? ".B" : ""); - bufptr += strlen(bufptr); - switch (i.f_format.func) { - case fsqrt_op: - case fabs_op: - case fmov_op: - case fcvts_op: - case fcvtd_op: - case fcvte_op: - case fcvtw_op: - sprintf(bufptr, "f%d,f%d", - i.f_format.re, - i.f_format.rd); - break; - case fcmp_op+0x0: - case fcmp_op+0x1: - case fcmp_op+0x2: - case fcmp_op+0x3: - case fcmp_op+0x4: - case fcmp_op+0x5: - case fcmp_op+0x6: - case fcmp_op+0x7: - case fcmp_op+0x8: - case fcmp_op+0x9: - case fcmp_op+0xa: - case fcmp_op+0xb: - case fcmp_op+0xc: - case fcmp_op+0xd: - case fcmp_op+0xe: - case fcmp_op+0xf: - sprintf(bufptr, "f%d,f%d", - i.f_format.rd, - i.f_format.rt); - break; - default: - sprintf(bufptr, "f%d,f%d,f%d", - i.f_format.re, - i.f_format.rd, - i.f_format.rt); - break; - } /* switch on func */ - } - break; /* End of default */ - } /* switch on rs */ - } - break; /* End of cop0, cop1, cop2, cop3 */ - - case jal_op: - case j_op: - sprintf(bufptr, "%s%s\t", op_name[i.j_format.opcode], - e.e.rd_boost ? ".B" : ""); - *symbol_value = (address & 0xF0000000) | i.j_format.target << 2; - if (save.print_jal_targets) - { - bufptr += strlen(bufptr); - sprintf(bufptr, "%#x", *symbol_value); - } - return_value = 1; - break; - - case swc1_op: - case sdc1_op: - case lwc1_op: - case ldc1_op: - sprintf(bufptr, "%s%s\tf%d,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - i.i_format.rt); - do_loadstore = true; - break; - - case lb_op: - case lh_op: - case lw_op: - case ld_op: - case lbu_op: - case lhu_op: - case sb_op: - case sh_op: - case sw_op: - case sd_op: - case lwl_op: - case lwr_op: - sprintf(bufptr, "%s%s\t%s,", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask)); - do_loadstore = true; - break; - - case ori_op: - case xori_op: - if (i.u_format.rs == ZERO) { - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - } - /* fall through */ - case andi_op: - sprintf(bufptr, "%s%s\t%s,%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - register_name(i.u_format.rs, e.e.rs_boost, regmask), - i.u_format.uimmediate); - break; - case lui_op: - sprintf(bufptr, "%s%s\t%s,%#x", op_name[i.u_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.u_format.rt, e.e.rt_boost, regmask), - i.u_format.uimmediate); - break; - case addi_op: - case addiu_op: - if (i.i_format.rs == ZERO) { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "li%s\t%s,%d", - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - sign_extender); - break; - } - /* fall through */ - default: - { - short sign_extender = i.i_format.simmediate; - sprintf(bufptr, "%s%s\t%s,%s,%d", op_name[i.i_format.opcode], - e.e.rd_boost ? ".B" : "", - register_name(i.i_format.rt, e.e.rt_boost, regmask), - register_name(i.i_format.rs, e.e.rs_boost, regmask), - sign_extender); - } - break; - } - - /* Some instructions require more than just registers */ - - if (do_loadstore) - { - short sign_extender = i.i_format.simmediate; - *symbol_value = sign_extender; - *ls_register = i.i_format.rs; - bufptr += strlen(bufptr); - sprintf(bufptr, "%d(%s)", sign_extender, - register_name(i.i_format.rs, e.e.rs_boost, regmask)); - return_value = -1; - } - else if (do_b_displacement) - { - short sign_extender = i.i_format.simmediate; - bufptr += strlen(bufptr); - *symbol_value = 4 + address + ((((long)sign_extender & 0xFFFD0000) | (0x3FFFF & (sign_extender << 2)))); - sprintf(bufptr, "%#x", *symbol_value); - return_value = 2; - } - - return return_value; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/mipsdis.h b/lib/CPUs/MIPS/bsp/examples/mipsdis.h deleted file mode 100644 index 2e9aca4..0000000 --- a/lib/CPUs/MIPS/bsp/examples/mipsdis.h +++ /dev/null @@ -1,450 +0,0 @@ -/* ------------------------------------------------------------------ */ -/* | Copyright Unpublished, MIPS Computer Systems, Inc. All Rights | */ -/* | Reserved. This software contains proprietary and confidential | */ -/* | information of MIPS and its suppliers. Use, disclosure or | */ -/* | reproduction is prohibited without the prior express written | */ -/* | consent of MIPS. | */ -/* ------------------------------------------------------------------ */ -/* inst.h 4.2 */ -/* - * inst.h -- instruction format defines - */ - -/** - ** UPDATE - 19 Sept 89 by Michael Smith - ** - ** Removed signed type to remove obnoxious C++ warning message. - **/ - -#ifdef LANGUAGE_C -#ifdef MIPSEB -union mips_instruction { - unsigned word; - unsigned char byte[4]; - struct { - unsigned opcode : 6; - unsigned target : 26; - } j_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned simmediate : 16; - } i_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned uimmediate : 16; - } u_format; - struct { - unsigned opcode : 6; - unsigned rs : 5; - unsigned rt : 5; - unsigned rd : 5; - unsigned re : 5; - unsigned func : 6; - } r_format; - struct { - unsigned opcode : 6; - unsigned : 1; - unsigned fmt : 4; - unsigned rt : 5; - unsigned rd : 5; - unsigned re : 5; - unsigned func : 6; - } f_format; -}; -#endif - -#ifdef MIPSEL -union mips_instruction { - unsigned word; - unsigned char byte[4]; - struct { - unsigned target : 26; - unsigned opcode : 6; - } j_format; - struct { - unsigned simmediate : 16; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } i_format; - struct { - unsigned uimmediate : 16; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } u_format; - struct { - unsigned func : 6; - unsigned re : 5; - unsigned rd : 5; - unsigned rt : 5; - unsigned rs : 5; - unsigned opcode : 6; - } r_format; - struct { - unsigned func : 6; - unsigned re : 5; - unsigned rd : 5; - unsigned rt : 5; - unsigned fmt : 4; - unsigned : 1; - unsigned opcode : 6; - } f_format; -}; -#endif - -#define spec_op 0x00 -#define bcond_op 0x01 -#define j_op 0x02 -#define jal_op 0x03 - -#define beq_op 0x04 -#define bne_op 0x05 -#define blez_op 0x06 -#define bgtz_op 0x07 - -#define addi_op 0x08 -#define addiu_op 0x09 -#define slti_op 0x0A -#define sltiu_op 0x0B - -#define andi_op 0x0C -#define ori_op 0x0D -#define xori_op 0x0E -#define lui_op 0x0F - -#define lb_op 0x20 -#define lh_op 0x21 -#define lw_op 0x23 -#define lbu_op 0x24 -#define lhu_op 0x25 -#define ld_op 0x27 -#define sb_op 0x28 -#define sh_op 0x29 -#define sw_op 0x2B -#define sd_op 0x2F -#define lwl_op 0x22 -#define lwr_op 0x26 -#define swl_op 0x2a -#define swr_op 0x2e - -/* Co-processor sub-opcodes */ -#define bc_op 0x08 -#define mfc_op 0x00 -#define cfc_op 0x02 -#define mtc_op 0x04 -#define ctc_op 0x06 - -/* Co-processor 0 opcodes */ -#define cop0_op 0x10 -#define lwc0_op 0x30 -#define ldc0_op 0x34 -#define swc0_op 0x38 -#define sdc0_op 0x3c - -/* Co-processor 0 sub-opcodes */ -#define tlbr_op 0x1 -#define tlbwi_op 0x2 -#define tlbwr_op 0x6 -#define tlbp_op 0x8 -#define rfe_op 0x10 - -/* Co-processor 1 opcodes */ -#define cop1_op 0x11 -#define lwc1_op 0x31 -#define ldc1_op 0x35 -#define swc1_op 0x39 -#define sdc1_op 0x3D - -/* Co-processor 1 sub-opcodes */ -#define fadd_op 0x00 -#define fsub_op 0x01 -#define fmpy_op 0x02 -#define fdiv_op 0x03 -#define fsqrt_op 0x04 -#define fabs_op 0x05 -#define fmov_op 0x06 -#define fneg_op 0x07 -#define fcvts_op 0x20 -#define fcvtd_op 0x21 -#define fcvte_op 0x22 -#define fcvtw_op 0x24 -#define fcmp_op 0x30 -#define s_fmt 0 -#define d_fmt 1 -#define e_fmt 2 -#define w_fmt 4 - -/* Other coprocessor opcodes */ -#define cop2_op 0x12 -#define lwc2_op 0x32 -#define ldc2_op 0x36 -#define swc2_op 0x3a -#define sdc2_op 0x3e - -#define cop3_op 0x13 -#define lwc3_op 0x33 -#define ldc3_op 0x37 -#define swc3_op 0x3b -#define sdc3_op 0x3f - - -/* bcond subopcodes */ -#define bltz_op 0x00 -#define bgez_op 0x01 -#define bltzal_op 0x10 -#define bgezal_op 0x11 - -/* special subopcodes */ -#define sll_op 0x00 -#define srl_op 0x02 -#define sra_op 0x03 -#define sllv_op 0x04 -#define srlv_op 0x06 -#define srav_op 0x07 -#define jr_op 0x08 -#define jalr_op 0x09 -#define syscall_op 0x0C -#define break_op 0x0D -#define vcall_op 0x0E - -#define mfhi_op 0x10 -#define mthi_op 0x11 -#define mflo_op 0x12 -#define mtlo_op 0x13 -#define mult_op 0x18 -#define multu_op 0x19 -#define div_op 0x1A -#define divu_op 0x1B - -#define add_op 0x20 -#define addu_op 0x21 -#define and_op 0x24 -#define or_op 0x25 -#define xor_op 0x26 -#define nor_op 0x27 -#define sub_op 0x22 -#define subu_op 0x23 -#define slt_op 0x2A -#define sltu_op 0x2B - -#endif /* LANGUAGE_C */ - -#ifdef LANGUAGE_PASCAL - -#ifdef MIPSEB -type - mips_instruction = - packed record - case cardinal of - 0: ( - word: cardinal; - ); - 1: ( - byte: packed array[0..3] of 0..255; - ); - 2: ( - opcode: 0..63; - target: 0..67108863; - ); - 3: ( - opcode3: 0..63; - rs: 0..31; - rt: 0..31; - simmediate: -32768..32767; - ); - 4: ( - opcode4: 0..63; - rs4: 0..63; - rt4: 0..63; - uimmediate: 0..65535; - ); - 5: ( - opcode5: 0..63; - rs5: 0..63; - rt5: 0..63; - rd5: 0..63; - re5: 0..63; - func: 0..63; - ); - end {record}; -#endif - -#ifdef MIPSEL -type - mips_instruction = - packed record - case cardinal of - 0: ( - word: cardinal; - ); - 1: ( - byte: packed array[0..3] of 0..255; - ); - 2: ( - target: 0..67108863; - opcode: 0..63; - ); - 3: ( - simmediate: -32768..32767; - rt: 0..31; - rs: 0..31; - opcode3: 0..63; - ); - 4: ( - uimmediate: 0..65535; - rt4: 0..63; - rs4: 0..63; - opcode4: 0..63; - ); - 5: ( - func: 0..63; - re5: 0..63; - rd5: 0..63; - rt5: 0..63; - rs5: 0..63; - opcode5: 0..63; - ); - end {record}; -#endif - -#define spec_op 16#00 -#define bcond_op 16#01 -#define j_op 16#02 -#define jal_op 16#03 - -#define beq_op 16#04 -#define bne_op 16#05 -#define blez_op 16#06 -#define bgtz_op 16#07 - -#define addi_op 16#08 -#define addiu_op 16#09 -#define slti_op 16#0A -#define sltiu_op 16#0B - -#define andi_op 16#0C -#define ori_op 16#0D -#define xori_op 16#0E -#define lui_op 16#0F - -#define lb_op 16#20 -#define lh_op 16#21 -#define lw_op 16#23 -#define lbu_op 16#24 -#define lhu_op 16#25 -#define ld_op 16#27 -#define sb_op 16#28 -#define sh_op 16#29 -#define sw_op 16#2B -#define sd_op 16#2F -#define lwl_op 16#22 -#define lwr_op 16#26 -#define swl_op 16#2a -#define swr_op 16#2e - -/* Co-processor sub-opcodes */ -#define bc_op 16#08 -#define mfc_op 16#00 -#define cfc_op 16#02 -#define mtc_op 16#04 -#define ctc_op 16#06 - -/* Co-processor 0 opcodes */ -#define cop0_op 16#10 -#define lwc0_op 16#30 -#define ldc0_op 16#34 -#define swc0_op 16#38 -#define sdc0_op 16#3c - -/* Co-processor 0 sub-opcodes */ -#define tlbr_op 16#1 -#define tlbwi_op 16#2 -#define tlbwr_op 16#6 -#define tlbp_op 16#8 -#define rfe_op 16#10 - -/* Co-processor 1 opcodes */ -#define cop1_op 16#11 -#define lwc1_op 16#31 -#define ldc1_op 16#35 -#define swc1_op 16#39 -#define sdc1_op 16#3D - -/* Co-processor 1 sub-opcodes */ -#define fadd_op 16#00 -#define fsub_op 16#01 -#define fmpy_op 16#02 -#define fdiv_op 16#03 -#define fsqrt_op 16#04 -#define fabs_op 16#05 -#define fmov_op 16#06 -#define fneg_op 16#07 -#define fcvts_op 16#20 -#define fcvtd_op 16#21 -#define fcvte_op 16#22 -#define fcvtw_op 16#24 -#define fcmp_op 16#30 -#define s_fmt 0 -#define d_fmt 1 -#define e_fmt 2 -#define w_fmt 4 - -/* Other coprocessor opcodes */ -#define cop2_op 16#12 -#define lwc2_op 16#32 -#define ldc2_op 16#36 -#define swc2_op 16#3a -#define sdc2_op 16#3e - -#define cop3_op 16#13 -#define lwc3_op 16#33 -#define ldc3_op 16#37 -#define swc3_op 16#3b -#define sdc3_op 16#3f - - -/* bcond subopcodes */ -#define bltz_op 16#00 -#define bgez_op 16#01 -#define bltzal_op 16#10 -#define bgezal_op 16#11 - -/* special subopcodes */ -#define sll_op 16#00 -#define srl_op 16#02 -#define sra_op 16#03 -#define sllv_op 16#04 -#define srlv_op 16#06 -#define srav_op 16#07 -#define jr_op 16#08 -#define jalr_op 16#09 -#define syscall_op 16#0C -#define break_op 16#0D -#define vcall_op 16#0E - -#define mfhi_op 16#10 -#define mthi_op 16#11 -#define mflo_op 16#12 -#define mtlo_op 16#13 -#define mult_op 16#18 -#define multu_op 16#19 -#define div_op 16#1A -#define divu_op 16#1B - -#define add_op 16#20 -#define addu_op 16#21 -#define and_op 16#24 -#define or_op 16#25 -#define xor_op 16#26 -#define nor_op 16#27 -#define sub_op 16#22 -#define subu_op 16#23 -#define slt_op 16#2A -#define sltu_op 16#2B - -#endif /* LANGUAGE_PASCAL */ diff --git a/lib/CPUs/MIPS/bsp/examples/paranoia.c b/lib/CPUs/MIPS/bsp/examples/paranoia.c deleted file mode 100644 index 38f08e1..0000000 --- a/lib/CPUs/MIPS/bsp/examples/paranoia.c +++ /dev/null @@ -1,2302 +0,0 @@ -/* - * paranoia.c,v 1.4 1995/08/23 19:26:32 joel Exp - * - * A C version of Kahan's Floating Point Test "Paranoia" - * - * Thos Sumner, UCSF, Feb. 1985 - * David Gay, BTL, Jan. 1986 - * - * This is a rewrite from the Pascal version by - * - * B. A. Wichmann, 18 Jan. 1985 - * - * (and does NOT exhibit good C programming style). - * - * Sun May 16 18:21:51 MDT 1993 Jeffrey Wheat (cassidy@cygnus.com) - * Removed KR_headers defines, removed ANSI prototyping - * Cleaned up and reformated code. Added special CYGNUS - * "verbose" mode type messages (-DCYGNUS). - * Note: This code is VERY NASTY. - * - * Adjusted to use Standard C headers 19 Jan. 1992 (dmg); - * compile with -DKR_headers or insert - * #define KR_headers - * at the beginning if you have an old-style C compiler. - * - * (C) Apr 19 1983 in BASIC version by: - * Professor W. M. Kahan, - * 567 Evans Hall - * Electrical Engineering & Computer Science Dept. - * University of California - * Berkeley, California 94720 - * USA - * - * converted to Pascal by: - * B. A. Wichmann - * National Physical Laboratory - * Teddington Middx - * TW11 OLW - * UK - * - * converted to C by: - * - * David M. Gay and Thos Sumner - * AT&T Bell Labs Computer Center, Rm. U-76 - * 600 Mountain Avenue University of California - * Murray Hill, NJ 07974 San Francisco, CA 94143 - * USA USA - * - * with simultaneous corrections to the Pascal source (reflected - * in the Pascal source available over netlib). - * [A couple of bug fixes from dgh = sun!dhough incorporated 31 July 1986.] - * - * Reports of results on various systems from all the versions - * of Paranoia are being collected by Richard Karpinski at the - * same address as Thos Sumner. This includes sample outputs, - * bug reports, and criticisms. - * - * You may copy this program freely if you acknowledge its source. - * Comments on the Pascal version to NPL, please. - * - * - * The C version catches signals from floating-point exceptions. - * If signal(SIGFPE,...) is unavailable in your environment, you may - * #define NOSIGNAL to comment out the invocations of signal. - * - * This source file is too big for some C compilers, but may be split - * into pieces. Comments containing "SPLIT" suggest convenient places - * for this splitting. At the end of these comments is an "ed script" - * (for the UNIX(tm) editor ed) that will do this splitting. - * - * By #defining SINGLE_PRECISION when you compile this source, you may - * obtain a single-precision C version of Paranoia. - * - * The following is from the introductory commentary from Wichmann's work: - * - * The BASIC program of Kahan is written in Microsoft BASIC using many - * facilities which have no exact analogy in Pascal. The Pascal - * version below cannot therefore be exactly the same. Rather than be - * a minimal transcription of the BASIC program, the Pascal coding - * follows the conventional style of block-structured languages. Hence - * the Pascal version could be useful in producing versions in other - * structured languages. - * - * Rather than use identifiers of minimal length (which therefore have - * little mnemonic significance), the Pascal version uses meaningful - * identifiers as follows [Note: A few changes have been made for C]: - * - * - * BASIC C BASIC C BASIC C - * - * A J S StickyBit - * A1 AInverse J0 NoErrors T - * B Radix [Failure] T0 Underflow - * B1 BInverse J1 NoErrors T2 ThirtyTwo - * B2 RadixD2 [SeriousDefect] T5 OneAndHalf - * B9 BMinusU2 J2 NoErrors T7 TwentySeven - * C [Defect] T8 TwoForty - * C1 CInverse J3 NoErrors U OneUlp - * D [Flaw] U0 UnderflowThreshold - * D4 FourD K PageNo U1 - * E0 L Milestone U2 - * E1 M V - * E2 Exp2 N V0 - * E3 N1 V8 - * E5 MinSqEr O Zero V9 - * E6 SqEr O1 One W - * E7 MaxSqEr O2 Two X - * E8 O3 Three X1 - * E9 O4 Four X8 - * F1 MinusOne O5 Five X9 Random1 - * F2 Half O8 Eight Y - * F3 Third O9 Nine Y1 - * F6 P Precision Y2 - * F9 Q Y9 Random2 - * G1 GMult Q8 Z - * G2 GDiv Q9 Z0 PseudoZero - * G3 GAddSub R Z1 - * H R1 RMult Z2 - * H1 HInverse R2 RDiv Z9 - * I R3 RAddSub - * IO NoTrials R4 RSqrt - * I3 IEEE R9 Random9 - * - * SqRWrng - * - * All the variables in BASIC are true variables and in consequence, - * the program is more difficult to follow since the "constants" must - * be determined (the glossary is very helpful). The Pascal version - * uses Real constants, but checks are added to ensure that the values - * are correctly converted by the compiler. - * - * The major textual change to the Pascal version apart from the - * identifiersis that named procedures are used, inserting parameters - * wherehelpful. New procedures are also introduced. The - * correspondence is as follows: - * - * - * BASIC Pascal - * lines - * - * 90- 140 Pause - * 170- 250 Instructions - * 380- 460 Heading - * 480- 670 Characteristics - * 690- 870 History - * 2940-2950 Random - * 3710-3740 NewD - * 4040-4080 DoesYequalX - * 4090-4110 PrintIfNPositive - * 4640-4850 TestPartialUnderflow - * -*/ - -#include -#include - -/* - * To compile this on host using only libm from newlib (and using host libc) - * do: - * gcc -g -DNEED_REENT -DCYGNUS paranoia.c .../newlib-1.6/newlib/libm.a - */ - -#ifdef NEED_REENT -#include -struct _reent libm_reent = _REENT_INIT(libm_reent); -struct _reent *_impure_ptr = &libm_reent; -#endif - -#ifndef NOSIGNAL -#include -#include -#else /* NOSIGNAL */ -#define longjmp(e,v) -#define setjmp(e) 0 -#define jmp_buf int -#endif /* NOSIGNAL */ - -#ifdef SINGLE_PRECISION -#define FLOAT float -#define FABS(x) (float)fabs((double)(x)) -#define FLOOR(x) (float)floor((double)(x)) -#define LOG(x) (float)log((double)(x)) -#define POW(x,y) (float)pow((double)(x),(double)(y)) -#define SQRT(x) (float)sqrt((double)(x)) -#else /* !SINGLE_PRECISION */ -#define FLOAT double -#define FABS(x) fabs(x) -#define FLOOR(x) floor(x) -#define LOG(x) log(x) -#define POW(x,y) pow(x,y) -#define SQRT(x) sqrt(x) -#endif /* SINGLE_PRECISION */ - -jmp_buf ovfl_buf; -extern double fabs (), floor (), log (), pow (), sqrt (); -extern void exit (); -typedef void (*Sig_type) (); -FLOAT Sign (), Random (); -extern void BadCond (); -extern void SqXMinX (); -extern void TstCond (); -extern void notify (); -extern int read (); -extern void Characteristics (); -extern void Heading (); -extern void History (); -extern void Instructions (); -extern void IsYeqX (); -extern void NewD (); -extern void Pause (); -extern void PrintIfNPositive (); -extern void SR3750 (); -extern void SR3980 (); -extern void TstPtUf (); - -Sig_type sigsave; - -#define KEYBOARD 0 - -FLOAT Radix, BInvrse, RadixD2, BMinusU2; - -/*Small floating point constants.*/ -FLOAT Zero = 0.0; -FLOAT Half = 0.5; -FLOAT One = 1.0; -FLOAT Two = 2.0; -FLOAT Three = 3.0; -FLOAT Four = 4.0; -FLOAT Five = 5.0; -FLOAT Eight = 8.0; -FLOAT Nine = 9.0; -FLOAT TwentySeven = 27.0; -FLOAT ThirtyTwo = 32.0; -FLOAT TwoForty = 240.0; -FLOAT MinusOne = -1.0; -FLOAT OneAndHalf = 1.5; - -/*Integer constants*/ -int NoTrials = 20; /*Number of tests for commutativity. */ -#define False 0 -#define True 1 - -/* - * Definitions for declared types - * Guard == (Yes, No); - * Rounding == (Chopped, Rounded, Other); - * Message == packed array [1..40] of char; - * Class == (Flaw, Defect, Serious, Failure); - */ -#define Yes 1 -#define No 0 -#define Chopped 2 -#define Rounded 1 -#define Other 0 -#define Flaw 3 -#define Defect 2 -#define Serious 1 -#define Failure 0 -typedef int Guard, Rounding, Class; -typedef char Message; - -/* Declarations of Variables */ -int Indx; -char ch[8]; -FLOAT AInvrse, A1; -FLOAT C, CInvrse; -FLOAT D, FourD; -FLOAT E0, E1, Exp2, E3, MinSqEr; -FLOAT SqEr, MaxSqEr, E9; -FLOAT Third; -FLOAT F6, F9; -FLOAT H, HInvrse; -int I; -FLOAT StickyBit, J; -FLOAT MyZero; -FLOAT Precision; -FLOAT Q, Q9; -FLOAT R, Random9; -FLOAT T, Underflow, S; -FLOAT OneUlp, UfThold, U1, U2; -FLOAT V, V0, V9; -FLOAT W; -FLOAT X, X1, X2, X8, Random1; -FLOAT Y, Y1, Y2, Random2; -FLOAT Z, PseudoZero, Z1, Z2, Z9; -int ErrCnt[4]; -int fpecount; -int Milestone; -int PageNo; -int M, N, N1; -Guard GMult, GDiv, GAddSub; -Rounding RMult, RDiv, RAddSub, RSqrt; -int Break, Done, NotMonot, Monot, Anomaly, IEEE, SqRWrng, UfNGrad; - -/* Computed constants. - * U1 gap below 1.0, i.e, 1.0 - U1 is next number below 1.0 - * U2 gap above 1.0, i.e, 1.0 + U2 is next number above 1.0 - */ - -int batchmode; /* global batchmode test */ - -/* program name and version variables and macro */ -char *temp; -char *program_name; -char *program_vers; - -#ifndef VERSION -#define VERSION "1.1 [cygnus]" -#endif /* VERSION */ - -#define basename(cp) ((temp=(char *)strrchr((cp), '/')) ? temp+1 : (cp)) - -#ifndef BATCHMODE -# ifdef CYGNUS -# define BATCHMODE -# endif -#endif - -/* floating point exception receiver */ -void -_sigfpe (x) -int x; -{ - fpecount++; - printf ("\n* * * FLOATING-POINT ERROR %d * * *\n", x); - fflush (stdout); - if (sigsave) { -#ifndef NOSIGNAL - signal (SIGFPE, sigsave); -#endif /* NOSIGNAL */ - sigsave = 0; - longjmp (ovfl_buf, 1); - } - exit (1); -} - -#ifdef NOMAIN -#define main paranoia -#endif - -int -main (argc, argv) -int argc; -char **argv; -{ - /* First two assignments use integer right-hand sides. */ - Zero = 0; - One = 1; - Two = One + One; - Three = Two + One; - Four = Three + One; - Five = Four + One; - Eight = Four + Four; - Nine = Three * Three; - TwentySeven = Nine * Three; - ThirtyTwo = Four * Eight; - TwoForty = Four * Five * Three * Four; - MinusOne = -One; - Half = One / Two; - OneAndHalf = One + Half; - ErrCnt[Failure] = 0; - ErrCnt[Serious] = 0; - ErrCnt[Defect] = 0; - ErrCnt[Flaw] = 0; - PageNo = 1; - -#ifdef BATCHMODE - batchmode = 1; /* run test in batchmode? */ -#else /* !BATCHMODE */ - batchmode = 0; /* run test interactively */ -#endif /* BATCHMODE */ - -/* - program_name = basename (argv[0]); -*/ - program_vers = VERSION; - - printf ("%s version %s\n", "Paranoia", program_vers); - - /*=============================================*/ - Milestone = 0; - /*=============================================*/ -#ifndef NOSIGNAL - signal (SIGFPE, _sigfpe); -#endif - - if (!batchmode) { - Instructions (); - Pause (); - Heading (); - Instructions (); - Pause (); - Heading (); - Pause (); - Characteristics (); - Pause (); - History (); - Pause (); - } - - /*=============================================*/ - Milestone = 7; - /*=============================================*/ - printf ("Program is now RUNNING tests on small integers:\n"); - TstCond (Failure, (Zero + Zero == Zero) && (One - One == Zero) - && (One > Zero) && (One + One == Two), - "0+0 != 0, 1-1 != 0, 1 <= 0, or 1+1 != 2"); - Z = -Zero; - if (Z != 0.0) { - ErrCnt[Failure] = ErrCnt[Failure] + 1; - printf ("Comparison alleges that -0.0 is Non-zero!\n"); - U1 = 0.001; - Radix = 1; - TstPtUf (); - } - TstCond (Failure, (Three == Two + One) && (Four == Three + One) - && (Four + Two * (-Two) == Zero) - && (Four - Three - One == Zero), - "3 != 2+1, 4 != 3+1, 4+2*(-2) != 0, or 4-3-1 != 0"); - TstCond (Failure, (MinusOne == (0 - One)) - && (MinusOne + One == Zero) && (One + MinusOne == Zero) - && (MinusOne + FABS (One) == Zero) - && (MinusOne + MinusOne * MinusOne == Zero), - "-1+1 != 0, (-1)+abs(1) != 0, or -1+(-1)*(-1) != 0"); - TstCond (Failure, Half + MinusOne + Half == Zero, - "1/2 + (-1) + 1/2 != 0"); - /*=============================================*/ - Milestone = 10; - /*=============================================*/ - TstCond (Failure, (Nine == Three * Three) - && (TwentySeven == Nine * Three) && (Eight == Four + Four) - && (ThirtyTwo == Eight * Four) - && (ThirtyTwo - TwentySeven - Four - One == Zero), - "9 != 3*3, 27 != 9*3, 32 != 8*4, or 32-27-4-1 != 0"); - TstCond (Failure, (Five == Four + One) && - (TwoForty == Four * Five * Three * Four) - && (TwoForty / Three - Four * Four * Five == Zero) - && (TwoForty / Four - Five * Three * Four == Zero) - && (TwoForty / Five - Four * Three * Four == Zero), - "5 != 4+1, 240/3 != 80, 240/4 != 60, or 240/5 != 48"); - if (ErrCnt[Failure] == 0) { - printf ("-1, 0, 1/2, 1, 2, 3, 4, 5, 9, 27, 32 & 240 are O.K.\n"); - printf ("\n"); - } - printf ("Searching for Radix and Precision.\n"); - W = One; - do { - W = W + W; - Y = W + One; - Z = Y - W; - Y = Z - One; - } - while (MinusOne + FABS (Y) < Zero); - /*.. now W is just big enough that |((W+1)-W)-1| >= 1 ...*/ - Precision = Zero; - Y = One; - do { - Radix = W + Y; - Y = Y + Y; - Radix = Radix - W; - } - while (Radix == Zero); - if (Radix < Two) - Radix = One; - printf ("Radix = %f .\n", Radix); - if (Radix != 1) { - W = One; - do { - Precision = Precision + One; - W = W * Radix; - Y = W + One; - } - while ((Y - W) == One); - } - /*... now W == Radix^Precision is barely too big to satisfy (W+1)-W == 1 - ...*/ - U1 = One / W; - U2 = Radix * U1; - printf ("Closest relative separation found is U1 = %.7e .\n\n", U1); - printf ("Recalculating radix and precision\n "); - - /*save old values*/ - E0 = Radix; - E1 = U1; - E9 = U2; - E3 = Precision; - - X = Four / Three; - Third = X - One; - F6 = Half - Third; - X = F6 + F6; - X = FABS (X - Third); - if (X < U2) - X = U2; - - /*... now X = (unknown no.) ulps of 1+...*/ - do { - U2 = X; - Y = Half * U2 + ThirtyTwo * U2 * U2; - Y = One + Y; - X = Y - One; - } - while (!((U2 <= X) || (X <= Zero))); - - /*... now U2 == 1 ulp of 1 + ... */ - X = Two / Three; - F6 = X - Half; - Third = F6 + F6; - X = Third - Half; - X = FABS (X + F6); - if (X < U1) - X = U1; - - /*... now X == (unknown no.) ulps of 1 -... */ - do { - U1 = X; - Y = Half * U1 + ThirtyTwo * U1 * U1; - Y = Half - Y; - X = Half + Y; - Y = Half - X; - X = Half + Y; - } - while (!((U1 <= X) || (X <= Zero))); - /*... now U1 == 1 ulp of 1 - ... */ - if (U1 == E1) - printf ("confirms closest relative separation U1 .\n"); - else - printf ("gets better closest relative separation U1 = %.7e .\n", U1); - W = One / U1; - F9 = (Half - U1) + Half; - Radix = FLOOR (0.01 + U2 / U1); - if (Radix == E0) - printf ("Radix confirmed.\n"); - else - printf ("MYSTERY: recalculated Radix = %.7e .\n", Radix); - TstCond (Defect, Radix <= Eight + Eight, - "Radix is too big: roundoff problems"); - TstCond (Flaw, (Radix == Two) || (Radix == 10) - || (Radix == One), "Radix is not as good as 2 or 10"); - /*=============================================*/ - Milestone = 20; - /*=============================================*/ - TstCond (Failure, F9 - Half < Half, - "(1-U1)-1/2 < 1/2 is FALSE, prog. fails?"); - X = F9; - I = 1; - Y = X - Half; - Z = Y - Half; - TstCond (Failure, (X != One) - || (Z == Zero), "Comparison is fuzzy,X=1 but X-1/2-1/2 != 0"); - X = One + U2; - I = 0; - /*=============================================*/ - Milestone = 25; - /*=============================================*/ - /*... BMinusU2 = nextafter(Radix, 0) */ - BMinusU2 = Radix - One; - BMinusU2 = (BMinusU2 - U2) + One; - /* Purify Integers */ - if (Radix != One) { - X = -TwoForty * LOG (U1) / LOG (Radix); - Y = FLOOR (Half + X); - if (FABS (X - Y) * Four < One) - X = Y; - Precision = X / TwoForty; - Y = FLOOR (Half + Precision); - if (FABS (Precision - Y) * TwoForty < Half) - Precision = Y; - } - if ((Precision != FLOOR (Precision)) || (Radix == One)) { - printf ("Precision cannot be characterized by an Integer number\n"); - printf ("of significant digits but, by itself, this is a minor flaw.\n"); - } - if (Radix == One) - printf ("logarithmic encoding has precision characterized solely by U1.\n"); - else - printf ("The number of significant digits of the Radix is %f .\n", - Precision); - TstCond (Serious, U2 * Nine * Nine * TwoForty < One, - "Precision worse than 5 decimal figures "); - /*=============================================*/ - Milestone = 30; - /*=============================================*/ - /* Test for extra-precise subepressions */ - X = FABS (((Four / Three - One) - One / Four) * Three - One / Four); - do { - Z2 = X; - X = (One + (Half * Z2 + ThirtyTwo * Z2 * Z2)) - One; - } - while (!((Z2 <= X) || (X <= Zero))); - X = Y = Z = FABS ((Three / Four - Two / Three) * Three - One / Four); - do { - Z1 = Z; - Z = (One / Two - ((One / Two - (Half * Z1 + ThirtyTwo * Z1 * Z1)) - + One / Two)) + One / Two; - } - while (!((Z1 <= Z) || (Z <= Zero))); - do { - do { - Y1 = Y; - Y = (Half - ((Half - (Half * Y1 + ThirtyTwo * Y1 * Y1)) + Half - )) + Half; - } - while (!((Y1 <= Y) || (Y <= Zero))); - X1 = X; - X = ((Half * X1 + ThirtyTwo * X1 * X1) - F9) + F9; - } - while (!((X1 <= X) || (X <= Zero))); - if ((X1 != Y1) || (X1 != Z1)) { - BadCond (Serious, "Disagreements among the values X1, Y1, Z1,\n"); - printf ("respectively %.7e, %.7e, %.7e,\n", X1, Y1, Z1); - printf ("are symptoms of inconsistencies introduced\n"); - printf ("by extra-precise evaluation of arithmetic subexpressions.\n"); - notify ("Possibly some part of this"); - if ((X1 == U1) || (Y1 == U1) || (Z1 == U1)) - printf ( - "That feature is not tested further by this program.\n"); - } else { - if ((Z1 != U1) || (Z2 != U2)) { - if ((Z1 >= U1) || (Z2 >= U2)) { - BadCond (Failure, ""); - notify ("Precision"); - printf ("\tU1 = %.7e, Z1 - U1 = %.7e\n", U1, Z1 - U1); - printf ("\tU2 = %.7e, Z2 - U2 = %.7e\n", U2, Z2 - U2); - } else { - if ((Z1 <= Zero) || (Z2 <= Zero)) { - printf ("Because of unusual Radix = %f", Radix); - printf (", or exact rational arithmetic a result\n"); - printf ("Z1 = %.7e, or Z2 = %.7e ", Z1, Z2); - notify ("of an\nextra-precision"); - } - if (Z1 != Z2 || Z1 > Zero) { - X = Z1 / U1; - Y = Z2 / U2; - if (Y > X) - X = Y; - Q = -LOG (X); - printf ("Some subexpressions appear to be calculated extra\n"); - printf ("precisely with about %g extra B-digits, i.e.\n", - (Q / LOG (Radix))); - printf ("roughly %g extra significant decimals.\n", - Q / LOG (10.)); - } - printf ("That feature is not tested further by this program.\n"); - } - } - } - Pause (); - /*=============================================*/ - Milestone = 35; - /*=============================================*/ - if (Radix >= Two) { - X = W / (Radix * Radix); - Y = X + One; - Z = Y - X; - T = Z + U2; - X = T - Z; - TstCond (Failure, X == U2, - "Subtraction is not normalized X=Y,X+Z != Y+Z!"); - if (X == U2) - printf ( - "Subtraction appears to be normalized, as it should be."); - } - printf ("\nChecking for guard digit in *, /, and -.\n"); - Y = F9 * One; - Z = One * F9; - X = F9 - Half; - Y = (Y - Half) - X; - Z = (Z - Half) - X; - X = One + U2; - T = X * Radix; - R = Radix * X; - X = T - Radix; - X = X - Radix * U2; - T = R - Radix; - T = T - Radix * U2; - X = X * (Radix - One); - T = T * (Radix - One); - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero)) - GMult = Yes; - else { - GMult = No; - TstCond (Serious, False, - "* lacks a Guard Digit, so 1*X != X"); - } - Z = Radix * U2; - X = One + Z; - Y = FABS ((X + Z) - X * X) - U2; - X = One - U2; - Z = FABS ((X - U2) - X * X) - U1; - TstCond (Failure, (Y <= Zero) - && (Z <= Zero), "* gets too many final digits wrong.\n"); - Y = One - U2; - X = One + U2; - Z = One / Y; - Y = Z - X; - X = One / Three; - Z = Three / Nine; - X = X - Z; - T = Nine / TwentySeven; - Z = Z - T; - TstCond (Defect, X == Zero && Y == Zero && Z == Zero, - "Division lacks a Guard Digit, so error can exceed 1 ulp\n\ -or 1/3 and 3/9 and 9/27 may disagree"); - Y = F9 / One; - X = F9 - Half; - Y = (Y - Half) - X; - X = One + U2; - T = X / One; - X = T - X; - if ((X == Zero) && (Y == Zero) && (Z == Zero)) - GDiv = Yes; - else { - GDiv = No; - TstCond (Serious, False, - "Division lacks a Guard Digit, so X/1 != X"); - } - X = One / (One + U2); - Y = X - Half - Half; - TstCond (Serious, Y < Zero, - "Computed value of 1/1.000..1 >= 1"); - X = One - U2; - Y = One + Radix * U2; - Z = X * Radix; - T = Y * Radix; - R = Z / Radix; - StickyBit = T / Radix; - X = R - X; - Y = StickyBit - Y; - TstCond (Failure, X == Zero && Y == Zero, - "* and/or / gets too many last digits wrong"); - Y = One - U1; - X = One - F9; - Y = One - Y; - T = Radix - U2; - Z = Radix - BMinusU2; - T = Radix - T; - if ((X == U1) && (Y == U1) && (Z == U2) && (T == U2)) - GAddSub = Yes; - else { - GAddSub = No; - TstCond (Serious, False, - "- lacks Guard Digit, so cancellation is obscured"); - } - if (F9 != One && F9 - One >= Zero) { - BadCond (Serious, "comparison alleges (1-U1) < 1 although\n"); - printf (" subtraction yields (1-U1) - 1 = 0 , thereby vitiating\n"); - printf (" such precautions against division by zero as\n"); - printf (" ... if (X == 1.0) {.....} else {.../(X-1.0)...}\n"); - } - if (GMult == Yes && GDiv == Yes && GAddSub == Yes) - printf ( - " *, /, and - appear to have guard digits, as they should.\n"); - /*=============================================*/ - Milestone = 40; - /*=============================================*/ - Pause (); - printf ("Checking rounding on multiply, divide and add/subtract.\n"); - RMult = Other; - RDiv = Other; - RAddSub = Other; - RadixD2 = Radix / Two; - A1 = Two; - Done = False; - do { - AInvrse = Radix; - do { - X = AInvrse; - AInvrse = AInvrse / A1; - } - while (!(FLOOR (AInvrse) != AInvrse)); - Done = (X == One) || (A1 > Three); - if (!Done) - A1 = Nine + One; - } - while (!(Done)); - if (X == One) - A1 = Radix; - AInvrse = One / A1; - X = A1; - Y = AInvrse; - Done = False; - do { - Z = X * Y - Half; - TstCond (Failure, Z == Half, - "X * (1/X) differs from 1"); - Done = X == Radix; - X = Radix; - Y = One / X; - } - while (!(Done)); - Y2 = One + U2; - Y1 = One - U2; - X = OneAndHalf - U2; - Y = OneAndHalf + U2; - Z = (X - U2) * Y2; - T = Y * Y1; - Z = Z - X; - T = T - X; - X = X * Y2; - Y = (Y + U2) * Y1; - X = X - OneAndHalf; - Y = Y - OneAndHalf; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T <= Zero)) { - X = (OneAndHalf + U2) * Y2; - Y = OneAndHalf - U2 - U2; - Z = OneAndHalf + U2 + U2; - T = (OneAndHalf - U2) * Y1; - X = X - (Z + U2); - StickyBit = Y * Y1; - S = Z * Y2; - T = T - Y; - Y = (U2 - Y) + StickyBit; - Z = S - (Z + U2 + U2); - StickyBit = (Y2 + U2) * Y1; - Y1 = Y2 * Y1; - StickyBit = StickyBit - Y2; - Y1 = Y1 - Half; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero) - && (StickyBit == Zero) && (Y1 == Half)) { - RMult = Rounded; - printf ("Multiplication appears to round correctly.\n"); - } else if ((X + U2 == Zero) && (Y < Zero) && (Z + U2 == Zero) - && (T < Zero) && (StickyBit + U2 == Zero) - && (Y1 < Half)) { - RMult = Chopped; - printf ("Multiplication appears to chop.\n"); - } else - printf ("* is neither chopped nor correctly rounded.\n"); - if ((RMult == Rounded) && (GMult == No)) - notify ("Multiplication"); - } else - printf ("* is neither chopped nor correctly rounded.\n"); - /*=============================================*/ - Milestone = 45; - /*=============================================*/ - Y2 = One + U2; - Y1 = One - U2; - Z = OneAndHalf + U2 + U2; - X = Z / Y2; - T = OneAndHalf - U2 - U2; - Y = (T - U2) / Y1; - Z = (Z + U2) / Y2; - X = X - OneAndHalf; - Y = Y - T; - T = T / Y1; - Z = Z - (OneAndHalf + U2); - T = (U2 - OneAndHalf) + T; - if (!((X > Zero) || (Y > Zero) || (Z > Zero) || (T > Zero))) { - X = OneAndHalf / Y2; - Y = OneAndHalf - U2; - Z = OneAndHalf + U2; - X = X - Y; - T = OneAndHalf / Y1; - Y = Y / Y1; - T = T - (Z + U2); - Y = Y - Z; - Z = Z / Y2; - Y1 = (Y2 + U2) / Y2; - Z = Z - OneAndHalf; - Y2 = Y1 - Y2; - Y1 = (F9 - U1) / F9; - if ((X == Zero) && (Y == Zero) && (Z == Zero) && (T == Zero) - && (Y2 == Zero) && (Y2 == Zero) - && (Y1 - Half == F9 - Half)) { - RDiv = Rounded; - printf ("Division appears to round correctly.\n"); - if (GDiv == No) - notify ("Division"); - } else if ((X < Zero) && (Y < Zero) && (Z < Zero) && (T < Zero) - && (Y2 < Zero) && (Y1 - Half < F9 - Half)) { - RDiv = Chopped; - printf ("Division appears to chop.\n"); - } - } - if (RDiv == Other) - printf ("/ is neither chopped nor correctly rounded.\n"); - BInvrse = One / Radix; - TstCond (Failure, (BInvrse * Radix - Half == Half), - "Radix * ( 1 / Radix ) differs from 1"); - /*=============================================*/ - Milestone = 50; - /*=============================================*/ - TstCond (Failure, ((F9 + U1) - Half == Half) - && ((BMinusU2 + U2) - One == Radix - One), - "Incomplete carry-propagation in Addition"); - X = One - U1 * U1; - Y = One + U2 * (One - U2); - Z = F9 - Half; - X = (X - Half) - Z; - Y = Y - One; - if ((X == Zero) && (Y == Zero)) { - RAddSub = Chopped; - printf ("Add/Subtract appears to be chopped.\n"); - } - if (GAddSub == Yes) { - X = (Half + U2) * U2; - Y = (Half - U2) * U2; - X = One + X; - Y = One + Y; - X = (One + U2) - X; - Y = One - Y; - if ((X == Zero) && (Y == Zero)) { - X = (Half + U2) * U1; - Y = (Half - U2) * U1; - X = One - X; - Y = One - Y; - X = F9 - X; - Y = One - Y; - if ((X == Zero) && (Y == Zero)) { - RAddSub = Rounded; - printf ("Addition/Subtraction appears to round correctly.\n"); - if (GAddSub == No) - notify ("Add/Subtract"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - } else - printf ("Addition/Subtraction neither rounds nor chops.\n"); - S = One; - X = One + Half * (One + Half); - Y = (One + U2) * Half; - Z = X - Y; - T = Y - X; - StickyBit = Z + T; - if (StickyBit != Zero) { - S = Zero; - BadCond (Flaw, "(X - Y) + (Y - X) is non zero!\n"); - } - StickyBit = Zero; - if ((GMult == Yes) && (GDiv == Yes) && (GAddSub == Yes) - && (RMult == Rounded) && (RDiv == Rounded) - && (RAddSub == Rounded) && (FLOOR (RadixD2) == RadixD2)) { - printf ("Checking for sticky bit.\n"); - X = (Half + U1) * U2; - Y = Half * U2; - Z = One + Y; - T = One + X; - if ((Z - One <= Zero) && (T - One >= U2)) { - Z = T + Y; - Y = Z - X; - if ((Z - T >= U2) && (Y - T == Zero)) { - X = (Half + U1) * U1; - Y = Half * U1; - Z = One - Y; - T = One - X; - if ((Z - One == Zero) && (T - F9 == Zero)) { - Z = (Half - U1) * U1; - T = F9 - Z; - Q = F9 - Y; - if ((T - F9 == Zero) && (F9 - U1 - Q == Zero)) { - Z = (One + U2) * OneAndHalf; - T = (OneAndHalf + U2) - Z + U2; - X = One + Half / Radix; - Y = One + Radix * U2; - Z = X * Y; - if (T == Zero && X + Radix * U2 - Z == Zero) { - if (Radix != Two) { - X = Two + U2; - Y = X / Two; - if ((Y - One == Zero)) - StickyBit = S; - } else - StickyBit = S; - } - } - } - } - } - } - if (StickyBit == One) - printf ("Sticky bit apparently used correctly.\n"); - else - printf ("Sticky bit used incorrectly or not at all.\n"); - TstCond (Flaw, !(GMult == No || GDiv == No || GAddSub == No || - RMult == Other || RDiv == Other || RAddSub == Other), - "lack(s) of guard digits or failure(s) to correctly round or chop\n\ -(noted above) count as one flaw in the final tally below"); - /*=============================================*/ - Milestone = 60; - /*=============================================*/ - printf ("\n"); - printf ("Does Multiplication commute? "); - printf ("Testing on %d random pairs.\n", NoTrials); - Random9 = SQRT (3.0); - Random1 = Third; - I = 1; - do { - X = Random (); - Y = Random (); - Z9 = Y * X; - Z = X * Y; - Z9 = Z - Z9; - I = I + 1; - } - while (!((I > NoTrials) || (Z9 != Zero))); - if (I == NoTrials) { - Random1 = One + Half / Three; - Random2 = (U2 + U1) + One; - Z = Random1 * Random2; - Y = Random2 * Random1; - Z9 = (One + Half / Three) * ((U2 + U1) + One) - (One + Half / - Three) * ((U2 + U1) + One); - } - if (!((I == NoTrials) || (Z9 == Zero))) - BadCond (Defect, "X * Y == Y * X trial fails.\n"); - else - printf (" No failures found in %d integer pairs.\n", NoTrials); - /*=============================================*/ - Milestone = 70; - /*=============================================*/ - printf ("\nRunning test of square root(x).\n"); - TstCond (Failure, (Zero == SQRT (Zero)) - && (-Zero == SQRT (-Zero)) - && (One == SQRT (One)), "Square root of 0.0, -0.0 or 1.0 wrong"); - MinSqEr = Zero; - MaxSqEr = Zero; - J = Zero; - X = Radix; - OneUlp = U2; - SqXMinX (Serious); - X = BInvrse; - OneUlp = BInvrse * U1; - SqXMinX (Serious); - X = U1; - OneUlp = U1 * U1; - SqXMinX (Serious); - if (J != Zero) - Pause (); - printf ("Testing if sqrt(X * X) == X for %d Integers X.\n", NoTrials); - J = Zero; - X = Two; - Y = Radix; - if ((Radix != One)) - do { - X = Y; - Y = Radix * Y; - } - while (!((Y - X >= NoTrials))); - OneUlp = X * U2; - I = 1; - while (I <= NoTrials) { - X = X + One; - SqXMinX (Defect); - if (J > Zero) - break; - I = I + 1; - } - printf ("Test for sqrt monotonicity.\n"); - I = -1; - X = BMinusU2; - Y = Radix; - Z = Radix + Radix * U2; - NotMonot = False; - Monot = False; - while (!(NotMonot || Monot)) { - I = I + 1; - X = SQRT (X); - Q = SQRT (Y); - Z = SQRT (Z); - if ((X > Q) || (Q > Z)) - NotMonot = True; - else { - Q = FLOOR (Q + Half); - if ((I > 0) || (Radix == Q * Q)) - Monot = True; - else if (I > 0) { - if (I > 1) - Monot = True; - else { - Y = Y * BInvrse; - X = Y - U1; - Z = Y + U1; - } - } else { - Y = Q; - X = Y - U2; - Z = Y + U2; - } - } - } - if (Monot) - printf ("sqrt has passed a test for Monotonicity.\n"); - else { - BadCond (Defect, ""); - printf ("sqrt(X) is non-monotonic for X near %.7e .\n", Y); - } - /*=============================================*/ - Milestone = 80; - /*=============================================*/ - MinSqEr = MinSqEr + Half; - MaxSqEr = MaxSqEr - Half; - Y = (SQRT (One + U2) - One) / U2; - SqEr = (Y - One) + U2 / Eight; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - SqEr = Y + U2 / Eight; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - Y = ((SQRT (F9) - U2) - (One - U2)) / U1; - SqEr = Y + U1 / Eight; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - SqEr = (Y + One) + U1 / Eight; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - OneUlp = U2; - X = OneUlp; - for (Indx = 1; Indx <= 3; ++Indx) { - Y = SQRT ((X + U1 + X) + F9); - Y = ((Y - U2) - ((One - U2) + X)) / OneUlp; - Z = ((U1 - X) + F9) * Half * X * X / OneUlp; - SqEr = (Y + Half) + Z; - if (SqEr < MinSqEr) - MinSqEr = SqEr; - SqEr = (Y - Half) + Z; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - if (((Indx == 1) || (Indx == 3))) - X = OneUlp * Sign (X) * FLOOR (Eight / (Nine * SQRT (OneUlp))); - else { - OneUlp = U1; - X = -OneUlp; - } - } - /*=============================================*/ - Milestone = 85; - /*=============================================*/ - SqRWrng = False; - Anomaly = False; - RSqrt = Other; /* ~dgh */ - if (Radix != One) { - printf ("Testing whether sqrt is rounded or chopped.\n"); - D = FLOOR (Half + POW (Radix, One + Precision - FLOOR (Precision))); - /* ... == Radix^(1 + fract) if (Precision == Integer + fract. */ - X = D / Radix; - Y = D / A1; - if ((X != FLOOR (X)) || (Y != FLOOR (Y))) { - Anomaly = True; - } else { - X = Zero; - Z2 = X; - Y = One; - Y2 = Y; - Z1 = Radix - One; - FourD = Four * D; - do { - if (Y2 > Z2) { - Q = Radix; - Y1 = Y; - do { - X1 = FABS (Q + FLOOR (Half - Q / Y1) * Y1); - Q = Y1; - Y1 = X1; - } - while (!(X1 <= Zero)); - if (Q <= One) { - Z2 = Y2; - Z = Y; - } - } - Y = Y + Two; - X = X + Eight; - Y2 = Y2 + X; - if (Y2 >= FourD) - Y2 = Y2 - FourD; - } - while (!(Y >= D)); - X8 = FourD - Z2; - Q = (X8 + Z * Z) / FourD; - X8 = X8 / Eight; - if (Q != FLOOR (Q)) - Anomaly = True; - else { - Break = False; - do { - X = Z1 * Z; - X = X - FLOOR (X / Radix) * Radix; - if (X == One) - Break = True; - else - Z1 = Z1 - One; - } - while (!(Break || (Z1 <= Zero))); - if ((Z1 <= Zero) && (!Break)) - Anomaly = True; - else { - if (Z1 > RadixD2) - Z1 = Z1 - Radix; - do { - NewD (); - } - while (!(U2 * D >= F9)); - if (D * Radix - D != W - D) - Anomaly = True; - else { - Z2 = D; - I = 0; - Y = D + (One + Z) * Half; - X = D + Z + Q; - SR3750 (); - Y = D + (One - Z) * Half + D; - X = D - Z + D; - X = X + Q + X; - SR3750 (); - NewD (); - if (D - Z2 != W - Z2) - Anomaly = True; - else { - Y = (D - Z2) + (Z2 + (One - Z) * Half); - X = (D - Z2) + (Z2 - Z + Q); - SR3750 (); - Y = (One + Z) * Half; - X = Q; - SR3750 (); - if (I == 0) - Anomaly = True; - } - } - } - } - } - if ((I == 0) || Anomaly) { - BadCond (Failure, "Anomalous arithmetic with Integer < "); - printf ("Radix^Precision = %.7e\n", W); - printf (" fails test whether sqrt rounds or chops.\n"); - SqRWrng = True; - } - } - if (!Anomaly) { - if (!((MinSqEr < Zero) || (MaxSqEr > Zero))) { - RSqrt = Rounded; - printf ("Square root appears to be correctly rounded.\n"); - } else { - if ((MaxSqEr + U2 > U2 - Half) || (MinSqEr > Half) - || (MinSqEr + Radix < Half)) - SqRWrng = True; - else { - RSqrt = Chopped; - printf ("Square root appears to be chopped.\n"); - } - } - } - if (SqRWrng) { - printf ("Square root is neither chopped nor correctly rounded.\n"); - printf ("Observed errors run from %.7e ", MinSqEr - Half); - printf ("to %.7e ulps.\n", Half + MaxSqEr); - TstCond (Serious, MaxSqEr - MinSqEr < Radix * Radix, - "sqrt gets too many last digits wrong"); - } - /*=============================================*/ - Milestone = 90; - /*=============================================*/ - Pause (); - printf ("Testing powers Z^i for small Integers Z and i.\n"); - N = 0; - /* ... test powers of zero. */ - I = 0; - Z = -Zero; - M = 3; - Break = False; - do { - X = One; - SR3980 (); - if (I <= 10) { - I = 1023; - SR3980 (); - } - if (Z == MinusOne) - Break = True; - else { - Z = MinusOne; - /* .. if(-1)^N is invalid, replace MinusOne by One. */ - I = -4; - } - } - while (!Break); - PrintIfNPositive (); - N1 = N; - N = 0; - Z = A1; - M = (int) FLOOR (Two * LOG (W) / LOG (A1)); - Break = False; - do { - X = Z; - I = 1; - SR3980 (); - if (Z == AInvrse) - Break = True; - else - Z = AInvrse; - } - while (!(Break)); - /*=============================================*/ - Milestone = 100; - /*=============================================*/ - /* Powers of Radix have been tested, */ - /* next try a few primes */ - M = NoTrials; - Z = Three; - do { - X = Z; - I = 1; - SR3980 (); - do { - Z = Z + Two; - } - while (Three * FLOOR (Z / Three) == Z); - } - while (Z < Eight * Three); - if (N > 0) { - printf ("Errors like this may invalidate financial calculations\n"); - printf ("\tinvolving interest rates.\n"); - } - PrintIfNPositive (); - N += N1; - if (N == 0) - printf ("... no discrepancies found.\n"); - if (N > 0) - Pause (); - else - printf ("\n"); - /*=============================================*/ - Milestone = 110; - /*=============================================*/ - printf ("Seeking Underflow thresholds UfThold and E0.\n"); - D = U1; - if (Precision != FLOOR (Precision)) { - D = BInvrse; - X = Precision; - do { - D = D * BInvrse; - X = X - One; - } - while (X > Zero); - } - Y = One; - Z = D; - /* ... D is power of 1/Radix < 1. */ - do { - C = Y; - Y = Z; - Z = Y * Y; - } - while ((Y > Z) && (Z + Z > Z)); - Y = C; - Z = Y * D; - do { - C = Y; - Y = Z; - Z = Y * D; - } - while ((Y > Z) && (Z + Z > Z)); - if (Radix < Two) - HInvrse = Two; - else - HInvrse = Radix; - H = One / HInvrse; - /* ... 1/HInvrse == H == Min(1/Radix, 1/2) */ - CInvrse = One / C; - E0 = C; - Z = E0 * H; - /* ...1/Radix^(BIG Integer) << 1 << CInvrse == 1/C */ - do { - Y = E0; - E0 = Z; - Z = E0 * H; - } - while ((E0 > Z) && (Z + Z > Z)); - UfThold = E0; - E1 = Zero; - Q = Zero; - E9 = U2; - S = One + E9; - D = C * S; - if (D <= C) { - E9 = Radix * U2; - S = One + E9; - D = C * S; - if (D <= C) { - BadCond (Failure, "multiplication gets too many last digits wrong.\n"); - Underflow = E0; - Y1 = Zero; - PseudoZero = Z; - Pause (); - } - } else { - Underflow = D; - PseudoZero = Underflow * H; - UfThold = Zero; - do { - Y1 = Underflow; - Underflow = PseudoZero; - if (E1 + E1 <= E1) { - Y2 = Underflow * HInvrse; - E1 = FABS (Y1 - Y2); - Q = Y1; - if ((UfThold == Zero) && (Y1 != Y2)) - UfThold = Y1; - } - PseudoZero = PseudoZero * H; - } - while ((Underflow > PseudoZero) - && (PseudoZero + PseudoZero > PseudoZero)); - } - /* Comment line 4530 .. 4560 */ - if (PseudoZero != Zero) { - printf ("\n"); - Z = PseudoZero; - /* ... Test PseudoZero for "phoney- zero" violates */ - /* ... PseudoZero < Underflow or PseudoZero < PseudoZero + PseudoZero - ... */ - if (PseudoZero <= Zero) { - BadCond (Failure, "Positive expressions can underflow to an\n"); - printf ("allegedly negative value\n"); - printf ("PseudoZero that prints out as: %g .\n", PseudoZero); - X = -PseudoZero; - if (X <= Zero) { - printf ("But -PseudoZero, which should be\n"); - printf ("positive, isn't; it prints out as %g .\n", X); - } - } else { - BadCond (Flaw, "Underflow can stick at an allegedly positive\n"); - printf ("value PseudoZero that prints out as %g .\n", PseudoZero); - } - TstPtUf (); - } - /*=============================================*/ - Milestone = 120; - /*=============================================*/ - if (CInvrse * Y > CInvrse * Y1) { - S = H * S; - E0 = Underflow; - } - if (!((E1 == Zero) || (E1 == E0))) { - BadCond (Defect, ""); - if (E1 < E0) { - printf ("Products underflow at a higher"); - printf (" threshold than differences.\n"); - if (PseudoZero == Zero) - E0 = E1; - } else { - printf ("Difference underflows at a higher"); - printf (" threshold than products.\n"); - } - } - printf ("Smallest strictly positive number found is E0 = %g .\n", E0); - Z = E0; - TstPtUf (); - Underflow = E0; - if (N == 1) - Underflow = Y; - I = 4; - if (E1 == Zero) - I = 3; - if (UfThold == Zero) - I = I - 2; - UfNGrad = True; - switch (I) { - case 1: - UfThold = Underflow; - if ((CInvrse * Q) != ((CInvrse * Y) * S)) { - UfThold = Y; - BadCond (Failure, "Either accuracy deteriorates as numbers\n"); - printf ("approach a threshold = %.17e\n", UfThold);; - printf (" coming down from %.17e\n", C); - printf (" or else multiplication gets too many last digits wrong.\n"); - } - Pause (); - break; - - case 2: - BadCond (Failure, "Underflow confuses Comparison, which alleges that\n"); - printf ("Q == Y while denying that |Q - Y| == 0; these values\n"); - printf ("print out as Q = %.17e, Y = %.17e .\n", Q, Y2); - printf ("|Q - Y| = %.17e .\n", FABS (Q - Y2)); - UfThold = Q; - break; - - case 3: - X = X; - break; - - case 4: - if ((Q == UfThold) && (E1 == E0) - && (FABS (UfThold - E1 / E9) <= E1)) { - UfNGrad = False; - printf ("Underflow is gradual; it incurs Absolute Error =\n"); - printf ("(roundoff in UfThold) < E0.\n"); - Y = E0 * CInvrse; - Y = Y * (OneAndHalf + U2); - X = CInvrse * (One + U2); - Y = Y / X; - IEEE = (Y == E0); - } - } - if (UfNGrad) { - printf ("\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) { - printf ("Underflow / UfThold failed!\n"); - R = H + H; - } else - R = SQRT (Underflow / UfThold); - sigsave = 0; - if (R <= H) { - Z = R * UfThold; - X = Z * (One + R * H * (One + H)); - } else { - Z = UfThold; - X = Z * (One + H * H * (One + H)); - } - if (!((X == Z) || (X - Z != Zero))) { - BadCond (Flaw, ""); - printf ("X = %.17e\n\tis not equal to Z = %.17e .\n", X, Z); - Z9 = X - Z; - printf ("yet X - Z yields %.17e .\n", Z9); - printf (" Should this NOT signal Underflow, "); - printf ("this is a SERIOUS DEFECT\nthat causes "); - printf ("confusion when innocent statements like\n");; - printf (" if (X == Z) ... else"); - printf (" ... (f(X) - f(Z)) / (X - Z) ...\n"); - printf ("encounter Division by Zero although actually\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - printf ("X / Z fails!\n"); - else - printf ("X / Z = 1 + %g .\n", (X / Z - Half) - Half); - sigsave = 0; - } - } - printf ("The Underflow threshold is %.17e, %s\n", UfThold, - " below which"); - printf ("calculation may suffer larger Relative error than "); - printf ("merely roundoff.\n"); - Y2 = U1 * U1; - Y = Y2 * Y2; - Y2 = Y * U1; - if (Y2 <= UfThold) { - if (Y > E0) { - BadCond (Defect, ""); - I = 5; - } else { - BadCond (Serious, ""); - I = 4; - } - printf ("Range is too narrow; U1^%d Underflows.\n", I); - } - /*=============================================*/ - Milestone = 130; - /*=============================================*/ - Y = -FLOOR (Half - TwoForty * LOG (UfThold) / LOG (HInvrse)) / TwoForty; - Y2 = Y + Y; - printf ("Since underflow occurs below the threshold\n"); - printf ("UfThold = (%.17e) ^ (%.17e)\nonly underflow ", HInvrse, Y); - printf ("should afflict the expression\n\t(%.17e) ^ (%.17e);\n", - HInvrse, Y2); - printf ("actually calculating yields:"); - if (setjmp (ovfl_buf)) { - sigsave = 0; - BadCond (Serious, "trap on underflow.\n"); - } else { - sigsave = _sigfpe; - V9 = POW (HInvrse, Y2); - sigsave = 0; - printf (" %.17e .\n", V9); - if (!((V9 >= Zero) && (V9 <= (Radix + Radix + E9) * UfThold))) { - BadCond (Serious, "this is not between 0 and underflow\n"); - printf (" threshold = %.17e .\n", UfThold); - } else if (!(V9 > UfThold * (One + E9))) - printf ("This computed value is O.K.\n"); - else { - BadCond (Defect, "this is not between 0 and underflow\n"); - printf (" threshold = %.17e .\n", UfThold); - } - } - /*=============================================*/ - Milestone = 140; - /*=============================================*/ - printf ("\n"); - /* ...calculate Exp2 == exp(2) == 7.389056099... */ - X = Zero; - I = 2; - Y = Two * Three; - Q = Zero; - N = 0; - do { - Z = X; - I = I + 1; - Y = Y / (I + I); - R = Y + Q; - X = Z + R; - Q = (Z - X) + R; - } - while (X > Z); - Z = (OneAndHalf + One / Eight) + X / (OneAndHalf * ThirtyTwo); - X = Z * Z; - Exp2 = X * X; - X = F9; - Y = X - U1; - printf ("Testing X^((X + 1) / (X - 1)) vs. exp(2) = %.17e as X -> 1.\n", - Exp2); - for (I = 1;;) { - Z = X - BInvrse; - Z = (X + One) / (Z - (One - BInvrse)); - Q = POW (X, Z) - Exp2; - if (FABS (Q) > TwoForty * U2) { - N = 1; - V9 = (X - BInvrse) - (One - BInvrse); - BadCond (Defect, "Calculated"); - printf (" %.17e for\n", POW (X, Z)); - printf ("\t(1 + (%.17e) ^ (%.17e);\n", V9, Z); - printf ("\tdiffers from correct value by %.17e .\n", Q); - printf ("\tThis much error may spoil financial\n"); - printf ("\tcalculations involving tiny interest rates.\n"); - break; - } else { - Z = (Y - X) * Two + Y; - X = Y; - Y = Z; - Z = One + (X - F9) * (X - F9); - if (Z > One && I < NoTrials) - I++; - else { - if (X > One) { - if (N == 0) - printf ("Accuracy seems adequate.\n"); - break; - } else { - X = One + U2; - Y = U2 + U2; - Y += X; - I = 1; - } - } - } - } - /*=============================================*/ - Milestone = 150; - /*=============================================*/ - printf ("Testing powers Z^Q at four nearly extreme values.\n"); - N = 0; - Z = A1; - Q = FLOOR (Half - LOG (C) / LOG (A1)); - Break = False; - do { - X = CInvrse; - Y = POW (Z, Q); - IsYeqX (); - Q = -Q; - X = C; - Y = POW (Z, Q); - IsYeqX (); - if (Z < One) - Break = True; - else - Z = AInvrse; - } - while (!(Break)); - PrintIfNPositive (); - if (N == 0) - printf (" ... no discrepancies found.\n"); - printf ("\n"); - - /*=============================================*/ - Milestone = 160; - /*=============================================*/ - Pause (); - printf ("Searching for Overflow threshold:\n"); - printf ("This may generate an error.\n"); - Y = -CInvrse; - V9 = HInvrse * Y; - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) { - I = 0; - V9 = Y; - goto overflow; - } - do { - V = Y; - Y = V9; - V9 = HInvrse * Y; - } - while (V9 < Y); - I = 1; - overflow: - sigsave = 0; - Z = V9; - printf ("Can `Z = -Y' overflow?\n"); - printf ("Trying it on Y = %.17e .\n", Y); - V9 = -Y; - V0 = V9; - if (V - Y == V + V0) - printf ("Seems O.K.\n"); - else { - printf ("finds a "); - BadCond (Flaw, "-(-Y) differs from Y.\n"); - } - if (Z != Y) { - BadCond (Serious, ""); - printf ("overflow past %.17e\n\tshrinks to %.17e .\n", Y, Z); - } - if (I) { - Y = V * (HInvrse * U2 - HInvrse); - Z = Y + ((One - HInvrse) * U2) * V; - if (Z < V0) - Y = Z; - if (Y < V0) - V = Y; - if (V0 - V < V0) - V = V0; - } else { - V = Y * (HInvrse * U2 - HInvrse); - V = V + ((One - HInvrse) * U2) * Y; - } - printf ("Overflow threshold is V = %.17e .\n", V); - if (I) - printf ("Overflow saturates at V0 = %.17e .\n", V0); - else - printf ("There is no saturation value because \ -the system traps on overflow.\n"); - V9 = V * One; - printf ("No Overflow should be signaled for V * 1 = %.17e\n", V9); - V9 = V / One; - printf (" nor for V / 1 = %.17e .\n", V9); - printf ("Any overflow signal separating this * from the one\n"); - printf ("above is a DEFECT.\n"); - /*=============================================*/ - Milestone = 170; - /*=============================================*/ - if (!(-V < V && -V0 < V0 && -UfThold < V && UfThold < V)) { - BadCond (Failure, "Comparisons involving "); - printf ("+-%g, +-%g\nand +-%g are confused by Overflow.", - V, V0, UfThold); - } - /*=============================================*/ - Milestone = 175; - /*=============================================*/ - printf ("\n"); - for (Indx = 1; Indx <= 3; ++Indx) { - switch (Indx) { - case 1: - Z = UfThold; - break; - case 2: - Z = E0; - break; - case 3: - Z = PseudoZero; - break; - } - if (Z != Zero) { - V9 = SQRT (Z); - Y = V9 * V9; - if (Y / (One - Radix * E9) < Z - || Y > (One + Radix * E9) * Z) { /* dgh: + E9 --> * E9 */ - if (V9 > U1) - BadCond (Serious, ""); - else - BadCond (Defect, ""); - printf ("Comparison alleges that what prints as Z = %.17e\n", Z); - printf (" is too far from sqrt(Z) ^ 2 = %.17e .\n", Y); - } - } - } - /*=============================================*/ - Milestone = 180; - /*=============================================*/ - for (Indx = 1; Indx <= 2; ++Indx) { - if (Indx == 1) - Z = V; - else - Z = V0; - V9 = SQRT (Z); - X = (One - Radix * E9) * V9; - V9 = V9 * X; - if (((V9 < (One - Two * Radix * E9) * Z) || (V9 > Z))) { - Y = V9; - if (X < W) - BadCond (Serious, ""); - else - BadCond (Defect, ""); - printf ("Comparison alleges that Z = %17e\n", Z); - printf (" is too far from sqrt(Z) ^ 2 (%.17e) .\n", Y); - } - } - /*=============================================*/ - Milestone = 190; - /*=============================================*/ - Pause (); - X = UfThold * V; - Y = Radix * Radix; - if (X * Y < One || X > Y) { - if (X * Y < U1 || X > Y / U1) - BadCond (Defect, "Badly"); - else - BadCond (Flaw, ""); - - printf (" unbalanced range; UfThold * V = %.17e\n\t%s\n", - X, "is too far from 1.\n"); - } - /*=============================================*/ - Milestone = 200; - /*=============================================*/ - for (Indx = 1; Indx <= 5; ++Indx) { - X = F9; - switch (Indx) { - case 2: - X = One + U2; - break; - case 3: - X = V; - break; - case 4: - X = UfThold; - break; - case 5: - X = Radix; - } - Y = X; - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - printf (" X / X traps when X = %g\n", X); - else { - V9 = (Y / X - Half) - Half; - if (V9 == Zero) - continue; - if (V9 == -U1 && Indx < 5) - BadCond (Flaw, ""); - else - BadCond (Serious, ""); - printf (" X / X differs from 1 when X = %.17e\n", X); - printf (" instead, X / X - 1/2 - 1/2 = %.17e .\n", V9); - } - sigsave = 0; - } - /*=============================================*/ - Milestone = 210; - /*=============================================*/ - MyZero = Zero; - printf ("\n"); - printf ("What message and/or values does Division by Zero produce?\n"); -#ifndef BATCHMODE - printf ("This can interupt your program. You can "); - printf ("skip this part if you wish.\n"); - printf ("Do you wish to compute 1 / 0? "); - fflush (stdout); - read (KEYBOARD, ch, 8); - if ((ch[0] == 'Y') || (ch[0] == 'y')) { -#endif /* !BATCHMODE */ - sigsave = _sigfpe; - printf (" Trying to compute 1 / 0 produces ..."); - if (!setjmp (ovfl_buf)) - printf (" %.7e .\n", One / MyZero); - sigsave = 0; -#ifndef BATCHMODE - } else - printf ("O.K.\n"); - printf ("\nDo you wish to compute 0 / 0? "); - fflush (stdout); - read (KEYBOARD, ch, 80); - if ((ch[0] == 'Y') || (ch[0] == 'y')) { -#endif /* !BATCHMODE */ - sigsave = _sigfpe; - printf ("\n Trying to compute 0 / 0 produces ..."); - if (!setjmp (ovfl_buf)) - printf (" %.7e .\n", Zero / MyZero); - sigsave = 0; -#ifndef BATCHMODE - } else - printf ("O.K.\n"); -#endif /* !BATCHMODE */ - /*=============================================*/ - Milestone = 220; - /*=============================================*/ - - Pause (); - printf ("\n"); - { - static char *msg[] = - { - "FAILUREs encountered =", - "SERIOUS DEFECTs discovered =", - "DEFECTs discovered =", - "FLAWs discovered ="}; - int i; - for (i = 0; i < 4; i++) - if (ErrCnt[i]) - printf ("The number of %-29s %d.\n", - msg[i], ErrCnt[i]); - } - - printf ("\n"); - if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[Defect] - + ErrCnt[Flaw]) > 0) { - if ((ErrCnt[Failure] + ErrCnt[Serious] + ErrCnt[ - Defect] == 0) && (ErrCnt[Flaw] > 0)) { - printf ("The arithmetic diagnosed seems "); - printf ("Satisfactory though flawed.\n"); - } - if ((ErrCnt[Failure] + ErrCnt[Serious] == 0) - && (ErrCnt[Defect] > 0)) { - printf ("The arithmetic diagnosed may be Acceptable\n"); - printf ("despite inconvenient Defects.\n"); - } - if ((ErrCnt[Failure] + ErrCnt[Serious]) > 0) { - printf ("The arithmetic diagnosed has "); - printf ("unacceptable Serious Defects.\n"); - } - if (ErrCnt[Failure] > 0) { - printf ("Potentially fatal FAILURE may have spoiled this"); - printf (" program's subsequent diagnoses.\n"); - } - } else { - - printf ("No failures, defects nor flaws have been discovered.\n"); - if (!((RMult == Rounded) && (RDiv == Rounded) - && (RAddSub == Rounded) && (RSqrt == Rounded))) - printf ("The arithmetic diagnosed seems Satisfactory.\n"); - else { - if (StickyBit >= One && - (Radix - Two) * (Radix - Nine - One) == Zero) { - printf ("Rounding appears to conform to "); - printf ("the proposed IEEE standard P"); - if ((Radix == Two) && - ((Precision - Four * Three * Two) * - (Precision - TwentySeven - - TwentySeven + One) == Zero)) - printf ("754"); - else - printf ("854"); - if (IEEE) - printf (".\n"); - else { - printf (",\nexcept for possibly Double Rounding"); - printf (" during Gradual Underflow.\n"); - } - } - printf ("The arithmetic diagnosed appears to be Excellent!\n"); - } - } - - if (fpecount) - printf ("\nA total of %d floating point exceptions were registered.\n", - fpecount); - printf ("END OF TEST.\n"); - return 0; -} - -FLOAT -Sign (X) - FLOAT X; -{ - return X >= 0. ? 1.0 : -1.0; -} - -void -Pause () -{ -#ifndef BATCHMODE - char ch[8]; - - printf ("\nTo continue, press RETURN"); - fflush (stdout); - read (KEYBOARD, ch, 8); -#endif /* !BATCHMODE */ -#ifndef CYGNUS - printf ("\nDiagnosis resumes after milestone Number %d", Milestone); - printf (" Page: %d\n\n", PageNo); - ++Milestone; - ++PageNo; -#endif /* !CYGNUS */ -} - -void -TstCond (K, Valid, T) - int K, Valid; - char *T; -{ -#ifdef CYGNUS - printf ("TEST: %s\n", T); -#endif /* CYGNUS */ - if (!Valid) { - BadCond (K, T); - printf (".\n"); - } -#ifdef CYGNUS - printf ("PASS: %s\n", T); -#endif /* CYGNUS */ -} - -void -BadCond (K, T) - int K; - char *T; -{ - static char *msg[] = - {"FAILURE", "SERIOUS DEFECT", "DEFECT", "FLAW"}; - - ErrCnt[K] = ErrCnt[K] + 1; -#ifndef CYGNUS - printf ("%s: %s", msg[K], T); -#else - printf ("ERROR: Severity: %s: %s", msg[K], T); -#endif /* CYGNUS */ -} - -/* - * Random computes - * X = (Random1 + Random9)^5 - * Random1 = X - FLOOR(X) + 0.000005 * X; - * and returns the new value of Random1 -*/ -FLOAT -Random () -{ - FLOAT X, Y; - - X = Random1 + Random9; - Y = X * X; - Y = Y * Y; - X = X * Y; - Y = X - FLOOR (X); - Random1 = Y + X * 0.000005; - return (Random1); -} - -void -SqXMinX (ErrKind) - int ErrKind; -{ - FLOAT XA, XB; - - XB = X * BInvrse; - XA = X - XB; - SqEr = ((SQRT (X * X) - XB) - XA) / OneUlp; - if (SqEr != Zero) { - if (SqEr < MinSqEr) - MinSqEr = SqEr; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - J = J + 1.0; - BadCond (ErrKind, "\n"); - printf ("sqrt( %.17e) - %.17e = %.17e\n", X * X, X, OneUlp * SqEr); - printf ("\tinstead of correct value 0 .\n"); - } -} - -void -NewD () -{ - X = Z1 * Q; - X = FLOOR (Half - X / Radix) * Radix + X; - Q = (Q - X * Z) / Radix + X * X * (D / Radix); - Z = Z - Two * X * D; - if (Z <= Zero) { - Z = -Z; - Z1 = -Z1; - } - D = Radix * D; -} - -void -SR3750 () -{ - if (!((X - Radix < Z2 - Radix) || (X - Z2 > W - Z2))) { - I = I + 1; - X2 = SQRT (X * D); - Y2 = (X2 - Z2) - (Y - Z2); - X2 = X8 / (Y - Half); - X2 = X2 - Half * X2 * X2; - SqEr = (Y2 + Half) + (Half - X2); - if (SqEr < MinSqEr) - MinSqEr = SqEr; - SqEr = Y2 - X2; - if (SqEr > MaxSqEr) - MaxSqEr = SqEr; - } -} - -void -IsYeqX () -{ - if (Y != X) { - if (N <= 0) { - if (Z == Zero && Q <= Zero) - printf ("WARNING: computing\n"); - else - BadCond (Defect, "computing\n"); - printf ("\t(%.17e) ^ (%.17e)\n", Z, Q); - printf ("\tyielded %.17e;\n", Y); - printf ("\twhich compared unequal to correct %.17e ;\n", - X); - printf ("\t\tthey differ by %.17e .\n", Y - X); - } - N = N + 1; /* ... count discrepancies. */ - } -} - -void -SR3980 () -{ - do { - Q = (FLOAT) I; - Y = POW (Z, Q); - IsYeqX (); - if (++I > M) - break; - X = Z * X; - } - while (X < W); -} - -void -PrintIfNPositive () -{ - if (N > 0) - printf ("Similar discrepancies have occurred %d times.\n", N); -} - -void -TstPtUf () -{ - N = 0; - if (Z != Zero) { - printf ("Since comparison denies Z = 0, evaluating "); - printf ("(Z + Z) / Z should be safe.\n"); - sigsave = _sigfpe; - if (setjmp (ovfl_buf)) - goto very_serious; - Q9 = (Z + Z) / Z; - printf ("What the machine gets for (Z + Z) / Z is %.17e .\n", - Q9); - if (FABS (Q9 - Two) < Radix * U2) { - printf ("This is O.K., provided Over/Underflow"); - printf (" has NOT just been signaled.\n"); - } else { - if ((Q9 < One) || (Q9 > Two)) { - very_serious: - N = 1; - ErrCnt[Serious] = ErrCnt[Serious] + 1; - printf ("This is a VERY SERIOUS DEFECT!\n"); - } else { - N = 1; - ErrCnt[Defect] = ErrCnt[Defect] + 1; - printf ("This is a DEFECT!\n"); - } - } - sigsave = 0; - V9 = Z * One; - Random1 = V9; - V9 = One * Z; - Random2 = V9; - V9 = Z / One; - if ((Z == Random1) && (Z == Random2) && (Z == V9)) { - if (N > 0) - Pause (); - } else { - N = 1; - BadCond (Defect, "What prints as Z = "); - printf ("%.17e\n\tcompares different from ", Z); - if (Z != Random1) - printf ("Z * 1 = %.17e ", Random1); - if (!((Z == Random2) - || (Random2 == Random1))) - printf ("1 * Z == %g\n", Random2); - if (!(Z == V9)) - printf ("Z / 1 = %.17e\n", V9); - if (Random2 != Random1) { - ErrCnt[Defect] = ErrCnt[Defect] + 1; - BadCond (Defect, "Multiplication does not commute!\n"); - printf ("\tComparison alleges that 1 * Z = %.17e\n", - Random2); - printf ("\tdiffers from Z * 1 = %.17e\n", Random1); - } - Pause (); - } - } -} - -void -notify (s) - char *s; -{ - printf ("%s test appears to be inconsistent...\n", s); - printf (" PLEASE NOTIFY KARPINKSI!\n"); -} - -void -msglist (s) - char **s; -{ - while (*s) - printf ("%s\n", *s++); -} - -void -Instructions () -{ - static char *instr[] = - { - "Lest this program stop prematurely, i.e. before displaying\n", - " `END OF TEST',\n", - "try to persuade the computer NOT to terminate execution when an", - "error like Over/Underflow or Division by Zero occurs, but rather", - "to persevere with a surrogate value after, perhaps, displaying some", - "warning. If persuasion avails naught, don't despair but run this", - "program anyway to see how many milestones it passes, and then", - "amend it to make further progress.\n", - "Answer questions with Y, y, N or n (unless otherwise indicated).\n", - 0}; - - msglist (instr); -} - -void -Heading () -{ - static char *head[] = - { - "Users are invited to help debug and augment this program so it will", - "cope with unanticipated and newly uncovered arithmetic pathologies.\n", - "Please send suggestions and interesting results to", - "\tRichard Karpinski", - "\tComputer Center U-76", - "\tUniversity of California", - "\tSan Francisco, CA 94143-0704, USA\n", - "In doing so, please include the following information:", -#ifdef SINGLE_PRECISION - "\tPrecision:\tsingle;", -#else /* !SINGLE_PRECISION */ - "\tPrecision:\tdouble;", -#endif /* SINGLE_PRECISION */ - "\tVersion:\t10 February 1989;", - "\tComputer:\n", - "\tCompiler:\n", - "\tOptimization level:\n", - "\tOther relevant compiler options:", - 0}; - - msglist (head); -} - -void -Characteristics () -{ - static char *chars[] = - { - "Running this program should reveal these characteristics:", - " Radix = 1, 2, 4, 8, 10, 16, 100, 256 ...", - " Precision = number of significant digits carried.", - " U2 = Radix/Radix^Precision = One Ulp", - "\t(OneUlpnit in the Last Place) of 1.000xxx .", - " U1 = 1/Radix^Precision = One Ulp of numbers a little less than 1.0 .", - " Adequacy of guard digits for Mult., Div. and Subt.", - " Whether arithmetic is chopped, correctly rounded, or something else", - "\tfor Mult., Div., Add/Subt. and Sqrt.", - " Whether a Sticky Bit used correctly for rounding.", - " UnderflowThreshold = an underflow threshold.", - " E0 and PseudoZero tell whether underflow is abrupt, gradual, or fuzzy.", - " V = an overflow threshold, roughly.", - " V0 tells, roughly, whether Infinity is represented.", - " Comparisions are checked for consistency with subtraction", - "\tand for contamination with pseudo-zeros.", - " Sqrt is tested. Y^X is not tested.", - " Extra-precise subexpressions are revealed but NOT YET tested.", - " Decimal-Binary conversion is NOT YET tested for accuracy.", - 0}; - - msglist (chars); -} - -void -History () -{ /* History */ - /* Converted from Brian Wichmann's Pascal version to C by Thos Sumner, - with further massaging by David M. Gay. */ - - static char *hist[] = - { - "The program attempts to discriminate among", - " FLAWs, like lack of a sticky bit,", - " Serious DEFECTs, like lack of a guard digit, and", - " FAILUREs, like 2+2 == 5 .", - "Failures may confound subsequent diagnoses.\n", - "The diagnostic capabilities of this program go beyond an earlier", - "program called `MACHAR', which can be found at the end of the", - "book `Software Manual for the Elementary Functions' (1980) by", - "W. J. Cody and W. Waite. Although both programs try to discover", - "the Radix, Precision and range (over/underflow thresholds)", - "of the arithmetic, this program tries to cope with a wider variety", - "of pathologies, and to say how well the arithmetic is implemented.", - "\nThe program is based upon a conventional radix representation for", - "floating-point numbers, but also allows logarithmic encoding", - "as used by certain early WANG machines.\n", - "BASIC version of this program (C) 1983 by Prof. W. M. Kahan;", - "see source comments for more history.", - 0}; - - msglist (hist); -} diff --git a/lib/CPUs/MIPS/bsp/examples/phrasen.c b/lib/CPUs/MIPS/bsp/examples/phrasen.c deleted file mode 100644 index 8066ebd..0000000 --- a/lib/CPUs/MIPS/bsp/examples/phrasen.c +++ /dev/null @@ -1,298 +0,0 @@ -#include -#include -#include "libsys.h" - -struct substantive -{ - char *subst; - int sex; -}; - -struct verben -{ - char *verb_k; - char *verb_gr; - int art; -}; - -struct adjektive -{ - char *adj; -}; - - char *art[4]={"er","ie","as","en"}; - -char getch(void) -{ - return readchar(); -} - -void randomize(void) -{ - srand(clock()); -} - -struct substantive namen[]= -{ - {"Gerhard Schröder",1},{"Helmut Kohl",1},{"Rudolf Scharping",1}, - {"Claudia Nolte",2}, {"Johannes Rau",1},{"Wolfgang Schäuble",1}, - {"Joschka Fischer",1},{"Toni Blair",1},{"Kleopatra",2}, - {"Claudia Schiffer",2},{"Hannelore Kohl",2},{"Konrad Adenauer",1}, - {"Michael Jackson",1},{"Karl Marx",1}, {"Helmut Kohl",1},{"Heino",1}, - {"Gerhard Schröder",1},{"Donald Duck",1},{"Madonna",2},{"Jesus",1}, - {"Gott",1},{"Sheryl Crow",2},{"Verona Feldbusch",2},{"Pipi Langstrumpf",2}, - {"Bill Gates",1},{"Bill Clinton",1},{"Cleopatra",2},{"Winnetou",1}, - {"Käpt'n Blaubär",1},{"Rita Süssmuth",2},{"Boris Becker",1}, - {"Lilo Wanders",2},{"Queen Elizabeth",2},{"Lady Di",2},{"Steffi Graf",2}, - {"Frank Zappa",1},{"Dolly Buster",2},{"Mao Tse Tung",1},{"Ghandi",1}, - {"Dalai Lama",1},{"Teufel",1},{"Lenin",1},{"Edmund Stoiber",1}, - {"Ludwig van Beethoven",1},{"Wolfgang Amadeus Mozart",1}, - {"Richard Wagner",1},{"Erich Honecker",1},{"Adam Riese",1}, - {"Bill Clinton",1},{"Josef Stalin",1},{"Willy Brandt",1}, - {"John F. Kennedy",1},{"E.T.",1},{"Donald Duck",1},{"Lothar Matthäus",1}, - {"Hans Dietrich Genscher",1},{"Franz Josef Strauss",1},{"Sting",1}, - {"Hermann Hesse",1},{"Albert Einstein",1},{"Max Planck",1}, - {"Tom Jones",1},{"Heidi Kabel",2},{"Homer Simpson",1},{"Zeus",1}, - {"Helmut Schmidt",1},{"Antje Vollmer",2},{"Politiker",1},{"Papst",1}, - {"Bundeskanzler",1},{"Arzt",1},{"Friseuse",2},{"Teufel",1}, - {"Sandmännchen",3},{"Mutter",2},{"Vater",1},{"Säufer",1},{"Student",1}, - {"Bauer",1},{"Leiche",2},{"Polizist",1},{"Patientin",2},{"Bäcker",1}, - {"Wirt",1}, {"Schlachter",1},{"Baby",3},{"Reporter",1},{"Politiker",1}, - {"Beamtin",2},{"Oma",2},{"Putzfrau",2},{"Blinde",2},{"Wahnsinnige",2}, - {"Mörder",1},{"Psychiater",1},{"Prinz Charles",1},{"Onkel",1},{"Tante",2} -}; - -struct substantive sachen[]= -{ - {"Haus",3},{"Buch",3},{"Fahrrad",3},{"Schule",2},{"Auto",3},{"Nase",2}, - {"Mund",1},{"Kopf",1},{"Kaffee",1},{"Telephon",3},{"Tasse",2},{"Katze",2}, - {"Hund",1},{"Maus",2},{"Stuhl",1},{"Mann",1},{"Frau",2},{"Kind",3}, - {"Idiotin",2},{"Lampe",2},{"Panzer",1},{"Klavier",3},{"Gitarre",2}, - {"Straße",2},{"Wasser",3},{"Luft",2},{"Feuer",3},{"Erde",2},{"Mond",1}, - {"Sonne",2},{"Bild",3},{"Stadt",2},{"Land",3},{"Fluss",1}, - {"Bundeskanzler",1},{"Ball",1},{"Hut",1},{"Hose",2},{"Hemd",3},{"Tod",1}, - {"Geld",3},{"Tisch",1},{"Hand",2},{"Baum",1},{"Bier",3},{"Ratte",2}, - {"Esel",1},{"Musik",2},{"Blech",3},{"Dose",2},{"Zahn",1},{"Humor",1}, - {"Unterhose",2},{"Gift",3},{"Gesicht",3},{"Fuß",1},{"Auge",3},{"Warze",2}, - {"Ohr",3},{"Kanone",2},{"Milch",2},{"Messer",3},{"Papier",3},{"Haar",3}, - {"Welt",2},{"Motor",1},{"Langeweile",2},{"Grab",3},{"Schnaps",1}, - {"Vogel",1},{"Fisch",1},{"Meer",3},{"Banane",2},{"Brot",3}, - {"Sitzung",2},{"Labor",3},{"Kurzschluß",1},{"Lüge",2},{"Axt",2}, - {"Abstimmung",2},{"Toilette",2},{"Zigarette",2},{"Winter",1}, - {"Torte",2},{"Bahnhof",1},{"Sarg",1},{"Imbiss",1},{"Mund",1},{"Seife",2}, - {"Fernseher",1},{"Flasche",2},{"Eimer",1},{"Uhr",2},{"Irrenhaus",3}, - {"Wüste",2},{"Klumpen",1},{"Glück",3},{"Schiff",3},{"Käse",1},{"Quark",1}, - {"Sommer",1},{"Witz",1},{"Idee",2},{"Nacht",2},{"Dreck",1},{"Meer",3}, - {"Blut",3},{"Herz",3},{"Apfel",1},{"Banane",2},{"Mist",1},{"Atom",3}, - {"Note",2},{"Gehirn",3},{"Gefühl",3},{"Bombe",2},{"Vakuum",3}, - {"Zahl",2},{"Wort",3},{"Programm",3},{"Computer",1},{"Orient",1}, - {"Gabelstapler",1} -}; - -struct adjektive ad[]= -{ - {"schön"},{"doof"},{"gut"},{"schlecht"},{"gelb"},{"grün"},{"rot"}, - {"blau"},{"schnell"},{"lang"},{"kurz"},{"hell"},{"düster"},{"sanft"}, - {"hart"},{"langsam"},{"bitter"},{"süß"},{"kaputt"},{"nett"},{"groß"}, - {"klein"},{"leicht"},{"schwer"},{"dick"},{"dünn"},{"rund"},{"eckig"}, - {"heiß"},{"kalt"},{"schlau"},{"elektrisch"},{"nass"},{"trocken"},{"ratlos"}, - {"abartig"},{"genial"},{"bestechlich"},{"irr"},{"steif"},{"angespannt"}, - {"laut"},{"leis"},{"warm"},{"wütend"},{"sauber"},{"schmutzig"},{"arm"}, - {"ätzend"},{"langweilig"},{"interessant"},{"erfahren"},{"abgewählt"}, - {"durchgeknallt"},{"angenehm"},{"widerwärtig"},{"willig"},{"mutig"}, - {"schwach"},{"stark"},{"nervend"},{"spießig"},{"alt"},{"neu"},{"spitz"}, - {"stumpf"},{"teuflisch"},{"scharf"},{"lecker"},{"übelriechend"},{"halb"}, - {"ganz"},{"bleich"},{"peinlich"},{"taktlos"},{"gewieft"},{"windig"}, - {"größenwahnsinnig"},{"verrückt"},{"uralt"},{"aalglatt"},{"korrekt"}, - {"kompetent"},{"einfühlsam"},{"tot"},{"schleimig"},{"gestört"},{"hohl"}, - {"beknackt"},{"nackt"},{"barfüßig"},{"schwitzend"},{"laufend"},{"knackig"}, - {"unverschämt"},{"schläfrig"},{"wohlgeformt"},{"kugelförmig"},{"rauh"}, - {"degeneriert"},{"ekelhaft"},{"brutal"},{"gemein"},{"aggressiv"}, - {"aufdringlich"},{"betroffen"},{"geliebt"},{"gehasst"},{"beharrlich"}, - {"unmenschlich"},{"verblödet"},{"wichtig"},{"gigantisch"},{"winzig"}, - {"witzig"},{"komisch"},{"pervers"},{"fett"},{"stinkend"},{"lausig"}, - {"wendig"},{"breit"},{"locker"},{"einzigartig"},{"sterbend"},{"munter"}, - {"ungepflegt"},{"eisern"},{"echt"},{"besser"},{"wild"},{"ächzend"}, - {"frohlockend"},{"unscheinbar"},{"nebulös"},{"skandalös"},{"obzön"}, - {"beschränkt"},{"genervt"},{"hilflos"},{"unwürdig"},{"geleckt"}, - {"betrunken"},{"unwürdig"},{"bissig"},{"verkalkt"},{"senil"}, - {"jungfräulich"},{"ausgeleiert"},{"beleibt"},{"nachtragend"},{"errötend"}, - {"kahl"},{"würgend"},{"abwesend"},{"ruhig"},{"albern"},{"trostlos"}, - {"salzig"},{"lachend"},{"merkwürdig"},{"behaart"},{"leblos"},{"aufgeblasen"}, - {"frech"},{"kopflos"},{"schmierig"} -}; - -struct verben verb[]= -{ - {"geht","gehen",6},{"steht","stehen",2},{"sitzt","sitzen",2}, - {"spielt","spielen",7},{"singt","singen",2},{"trinkt","trinken",3}, - {"redet","reden",2}, {"liebt","lieben",7},{"schläft","schlafen",2}, - {"ißt","essen",3},{"lacht","lachen",2},{"tötet","töten",7}, - {"lügt","lügen",2},{"fliegt","fliegen",2},{"überfährt","überfahren",7}, - {"sieht","sehen",3},{"hört","hören",3},{"spricht","sprechen",2}, - {"berechnet","rechnen",3},{"schwimmt","schwimmen",2}, - {"zerschneidet","zerschnitten werden",3},{"raucht","rauchen",3}, - {"spaltet","spalten",3},{"verbrennt","verbrennen",2},{"ist","sein",2}, - {"hat","haben",1},{"zerbricht","zerbrechen",3},{"muss","müssen",4}, - {"kann","können",4},{"darf","dürfen",4},{"will","wollen",5}, - {"klaut","klauen",1},{"soll","sollen",4},{"studiert","studieren",3}, - {"reibt","reiben",3},{"liest","lesen",2},{"irrt","irren",2}, - {"spendiert","spendieren",1},{"schlägt","schlagen",3},{"fragt","fragen",7}, - {"zerstört","zerstören",1},{"erschießt","sich erschießen",1}, - {"überlegt","überlegen",2},{"trifft","treffen",7},{"leckt","lecken",1}, - {"wirft","werfen",1},{"vergiftet","vergiftet werden",1}, - {"öffnet","öffnen",1},{"schreit","schreien",2},{"sprengt","explodieren",3}, - {"erwürgt","würgen",7},{"arbeitet","arbeiten",2},{"erlegt","erlegen",1}, - {"putzt","putzen",1},{"stirbt","sterben",2}, {"kauft","kaufen",1}, - {"brüllt","brüllen",2},{"versteht","es verstehen",7}, - {"zertritt","zertreten werden",1},{"verendet","verenden",2}, - {"labert","labern",2},{"kratzt","kratzen",1},{"wird","nichts werden",2}, - {"entkleidet","sich entkleiden",7},{"verbiegt","sich verbiegen",1}, - {"verschenkt","es verschenken",7},{"vergisst","es vergessen",1}, - {"ergreift","greifen",1},{"baut","bauen",1},{"betet","beten",}, - {"rollt","rollen",3},{"bleibt","bleiben",2},{"wäscht","sich waschen",1}, - {"heiratet","heiraten",7},{"hebt","heben",1},{"denkt","nachdenken",2} -}; - -void end_sach_aus(void); -void nam_aus(void); -void end_nam_aus(void); -void adj_aus(void); -int verb_aus_k(void); -int verb_aus_gr(void); -int zufall(int); - -int main() -{ - int vindx; - int rem=0; - char end; - - setbuf(stdout, NULL); - randomize(); - printf("\n\t\t************************"); - printf("\n\t\t* DER ELEKTRISCHE POET *"); - printf("\n\t\t************************\n"); - printf("\n\tCopyright by J. Ahrensfeld & T. Burr"); - printf("\n\n\tFür die Texte ist Ihr Computer verantwortlich :-)\n"); - printf("\n\tZum beenden des Programmes 'x' eingeben!\n"); - printf("\n\tWeiter mit beliebiger Taste!\n"); - end = getch(); - - while(end != 'x') - { - if(rem >= 10) - { - printf("\n\n\tZum beenden des Programmes 'x' eingeben!\n"); - rem = 0; - if(getch() == 'x') - break; - } - printf("\n\n"); - nam_aus(); - - vindx=verb_aus_k(); - - switch (vindx) - { - case 1: end_sach_aus(); break; - - case 2: adj_aus(); break; - - case 3: end_sach_aus(); break; - - case 4: verb_aus_gr(); break; - - case 5: verb_aus_gr(); break; - - case 6: adj_aus(); break; - - case 7: end_nam_aus(); break; - } - - printf("."); - end = getch(); - rem++; - - } - printf("\n\n\tDas ist das Ende!"); - return 0; -} - -int zufall(int max) -{ - - return (rand()%max); -} - -void adj_aus(void) -{ - printf("%s", ad[zufall((sizeof(ad)/sizeof(*ad)))].adj); - return; -} - -void end_sach_aus(void) -{ - int index; - - index = zufall(sizeof(sachen)/sizeof(*sachen)); - if (sachen[index].sex==1) - printf("d%s", art[3]); - else - printf("d%s", art[(sachen[index].sex)-1]); - printf(" "); - adj_aus(); - if (sachen[index].sex==1) - printf("en %s", sachen[index].subst); - else - printf("e %s", sachen[index].subst); - return; -} - -void nam_aus(void) -{ - int index; - - index = zufall(sizeof(namen)/sizeof(*namen)); - printf("D%s", art[(namen[index].sex)-1]); - printf(" "); - adj_aus(); - printf("e %s " ,namen[index].subst); - return; -} - -void end_nam_aus(void) -{ - int index; - - index = zufall(sizeof(namen)/sizeof(*namen)); - if (namen[index].sex==1) - printf("d%s", art[3]); - else - printf("d%s", art[(namen[index].sex)-1]); - printf(" "); - adj_aus(); - if (namen[index].sex==1) - printf("en %s", namen[index].subst); - else - printf("e %s", namen[index].subst); - return; -} - -int verb_aus_k(void) -{ - int index; - - index = zufall(sizeof(verb)/sizeof(*verb)); - printf("%s ", verb[index].verb_k); - return (verb[index].art); -} - -int verb_aus_gr(void) -{ - int index; - - index = zufall(sizeof(verb)/sizeof(*verb)); - printf("%s", verb[index].verb_gr); - return index; -} diff --git a/lib/CPUs/MIPS/bsp/examples/queens.c b/lib/CPUs/MIPS/bsp/examples/queens.c deleted file mode 100644 index f9735e6..0000000 --- a/lib/CPUs/MIPS/bsp/examples/queens.c +++ /dev/null @@ -1,856 +0,0 @@ -/* -** Queens.c -- Find solutions to the Eight-Queens chess problem. -** Roberto Sierra 7/25/93 Version 1.1 -** 3/19/84 Version 1.0 -** -** Description: -** This program finds all the possible ways that N queens can -** be placed on an NxN chessboard so that the queens cannot -** capture one another -- that is, so that no rank, file or -** diagonal is occupied by more than one queen. By default, -** the program prints the first solution it finds. You can -** use the -a option to print all solutions, or the -c option -** just to count them. The program allows the chess board -** to be from 1x1 (trivial case) to 100x100. Warning: the -** larger the chess board, the longer it typically takes to -** find each solution, even though there may be more of them. -** -** This is a terrific example of the utility of recursion. The -** algorithm uses recursion to drastically limit the number -** of board positions that are tested. The program is able -** to find all 8x8 queen solutions in a fraction of a second -** (not counting print time). The code makes no attempt to -** eliminate symmetrical solutions, so the number of solutions -** reported will always be higher than the actual number of -** distinct solutions. -** -** -** Usage: -** Queens [-ac] n -** -** n number of queens (rows and columns). -** An integer from 1 to 100. -** -a Find (and print) all solutions. -** -c Count all solutions, but do not print them. -** -** The output is sent to stdout. All errors messages are -** sent to stderr. If a problem arises, the return code is -1. -** -** -** Examples: -** -** Queens 8 ## Show an 8x8 solution -** 8 queens on a 8x8 board... -** Q - - - - - - - -** - - - - Q - - - -** - - - - - - - Q -** - - - - - Q - - -** - - Q - - - - - -** - - - - - - Q - -** - Q - - - - - - -** - - - Q - - - - -** -** Queens -c 8 ## Count all 8x8 solutions -** 8 queens on a 8x8 board... -** ...there are 92 solutions. -** -** Queens -a 4 ## Show all 4x4 solutions -** 4 queens on a 4x4 board... -** -** Solution #1: -** - Q - - -** - - - Q -** Q - - - -** - - Q - -** -** Solution #2: -** - - Q - -** Q - - - -** - - - Q -** - Q - - -** -** ...there are 2 solutions. -** -** -** Build Instructions: -** You'll need an ANSI C compiler (or the willingness to edit -** the program a bit). If you've got Gnu C, then you can -** compile and load the program as follows: -** -** gcc Queens.c -ansi -o Queens -** -** [If you're using MPW on the Mac, define '-d MPW' on the -** compile line so that background processing will occur.] -** -** -** Algorithm: -** In a 1984 Byte article, I ran across an interesting letter -** from a high school student who was attempting to solve the -** Eight Queens problem using a BASIC interpreter. He had -** developed a program which placed eight queens successively -** on all sixty-four squares, testing for conflicts at each -** iteration. Of course, such a program would require 64^8 -** iterations (about 2.8x10^14 iterations). Even in C on a, -** fast CPU, this could take months or years. Byte's answer was -** to alter the loops so that the queens resided on separate -** ranks, thereby reducing the number of iterations required -** to find all solutions to 8^8 iterations (about 16 million). -** More reasonable, but still requiring a chunk of CPU time. -** -** I puzzled about this problem a bit, and came to realize that -** this was still wasting a lot of CPU cycles. Though I'm sure -** others have come up with good algorithms, I decided to come -** up with my own, with a particular eye on efficiency. The -** resulting algorithm finds all 8x8 solutions in a fraction -** of a second (there are 92 solutions, including rotations). -** On a Sun 4, it'll find all 365,596 solutions on a 14x14 board -** in a bit over 2 minutes (printing them out requires extra -** time, of course). Even Byte's solution would require 14^14 -** iterations (about 10^16) which would take aeons. -** -** My algorithm works as follows: -** (1) Place a queen in the top left corner. -** (2) Place another queen immediately below. -** (3) Test for conflicts. If the second queen conflicts (it -** does at first), then move it one square to the right. -** (4) Loop step 3 until there are no conflicts. Place -** the next queen on the board and recurse. -** (5) If any queen reaches the right edge of the board, -** remove it and 'pop' to the previous recursion level. -** (6) Now repeat these steps recursively until all eight -** queens (or however many) have been placed without -** conflict -- the result is a solution to the problem, -** which is counted and optionally printed. -** -** Because conflicts are tested as the recursion proceeds, -** this has the effect of 'pruning' the recursion so that -** a large number of board positions are not even attempted. -** The result is that the algorithm runs in reasonable time. -** -** I used a few tricks to make the test-for-conflict code -** extremely efficient -- there is no 'inner' loop to search -** along ranks, files, or diagonals. A series of arrays are -** maintained instead which indicate which queen currently -** 'owns' each rank, file or diagonal. This makes the -** algorithm really fly, though the code is a little hard to -** read. Lastly, pointer arithmetic is used to reduce the -** number of implicit multiplications used in array addressing. -** -** -** Contact: -** For queries regarding this program, contact Roberto Sierra -** at any of the following addresses: -** -** Roberto Sierra -** bert@netcom.com (preferred address) -** 73557.2101@compuserve.com -** -** Tempered MicroDesigns -** P.O. Box 170638 -** San Francisco, CA 94117 -** -** -** Fine Print: -** This program is in the public domain and can be used for -** any purpose whatsoever, including commercial application. -** [I'd like to hear what you do with it, though.] -** Absolutely no warranty or liability is implied or extended -** by the author. -** -** -** Modification History: -** PRS 3/19/84 v1.0 -- Original version. -** PRS 7/25/93 v1.1 -- ANSIfied the code. More efficient pointers. -** -*/ - -/***************************************************************/ -/* Timer options. You MUST uncomment one of the options below */ -/* or compile, for example, with the '-DUNIX' option. */ -/***************************************************************/ -/* #define Amiga */ -/* #define UNIX */ -/* #define UNIX_Old */ -/* #define VMS */ -/* #define BORLAND_C */ -/* #define MSC */ -/* #define MAC */ -/* #define IPSC */ -/* #define FORTRAN_SEC */ -/* #define GTODay */ -/* #define CTimer */ -/* #define UXPM */ -/* #define MAC_TMgr */ -/* #define PARIX */ -/* #define POSIX */ -/* #define WIN32 */ -/* #define POSIX1 */ -/***********************/ - -#include /* Need standard I/O functions */ -#include /* Need exit() routine interface */ -#include /* Need strcmp() interface */ -#ifdef MPW /* Macintosh MPW ONLY */ -#include /* Need cursor control interfaces */ -#endif - -#define MAXQUEENS 100 /* Maximum number of queens */ -#define MAXRANKS MAXQUEENS /* Maximum number of ranks (rows) */ -#define MAXFILES MAXQUEENS /* Maximum number of files (columns) */ -#define MAXDIAGS (MAXRANKS+MAXFILES-1) /* Maximum number of diagonals */ -#define EMPTY (MAXQUEENS+1) /* Marks unoccupied file or diagonal */ - -/* GLOBAL VARIABLES */ - -int queens; /* Number of queens to place */ -int ranks; /* Number of ranks (rows) */ -int files; /* Number of files (columns) */ -int printing = 1; /* TRUE if printing positions */ -int findall = 0; /* TRUE if finding all solutions */ - -unsigned long solutions = 0; /* Number of solutions found */ -int queen[MAXRANKS]; /* File on which each queen is located */ -int file[MAXFILES]; /* Which queen 'owns' each file */ -int fordiag[MAXDIAGS]; /* Which queen 'owns' forward diagonals */ -int bakdiag[MAXDIAGS]; /* Which queen 'owns' reverse diagonals */ -char *progname = 0; /* The name of this program */ - - - - - -/***********************/ -/**** ROUTINES ****/ -/***********************/ - -/* Internal prototypes */ -//void main(int argc,char **argv); /* Main program */ -void find(int level); /* Algorithm to find solutions */ -void pboard(void); /* Print a solution */ -void run_queens(int argc,char **argv); - - - - -/*---------------------- main() --------------------------- -** MAIN program. The main purpose of this routine is -** to deal with decoding the command line arguments, -** initializing the various arrays, and starting the -** recursive search routine. -*/ -int main(void) -{ - char *args[] = {"queens", "-c", "12"}; - run_queens(3, args); -} - -void run_queens(int argc,char **argv) -{ - register int i; /* Loop variable */ - register char *p; /* Pointer to argument */ - double starttime, benchtime, dtime(); - -#ifdef MPW /* Macintosh MPW ONLY */ - InitCursorCtl(0); /* Enable cursor control */ -#endif - - progname = argv[0]; /* The name of the program */ - - /**** DECODE COMMAND LINE ARGUMENTS ****/ - - for (i=1; i MAXQUEENS) { /* N can't be too large */ - fprintf(stderr,"%s: can't have more than %d queens\n", - progname, MAXQUEENS); - exit(-1); - } - } /* End of argument test */ - } /* End of argument scan loop */ - if (queens == 0) { - fprintf(stderr,"%s: missing queens argument\n",progname); - fprintf(stderr,"usage: %s [-ac] queens\n",progname); - exit(-1); - } - - - ranks = files = queens; /* NxN board for N queens */ - printf("%d queen%s on a %dx%d board...\n", - queens, queens>1? "s" : "", ranks, files); - fflush(stdout); - - starttime = dtime(); - - /* Initialization */ - solutions = 0; /* No solutions yet */ - for (i=0; i= level && /* No queen on the file? */ - *fdp >= level && *bdp >= level /* No queens on diagonals? */ - ) { - queen[level] = f; /* Note new position of queen */ - *fp = *fdp = *bdp = level; /* Place queen on file & diags */ - find(level+1); /* This level OK, recurse to next */ - *fp = *fdp = *bdp = EMPTY; /* Remove queen from file & diags */ - } /* End of conflict test */ - } /* End of file loop */ - } /* End if (level == queens) */ -} /* End of find() */ - - - - -/*------------------------- pboard() ----------------------- -** This routines prints the board for a particular solution. -** The output is sent to stdout. -*/ - -void pboard(void) -{ - register int i,j; /* Rank/File indices */ - - if (findall) { /* Only if searching for all */ - printf("\nSolution #%lu:\n",solutions); /* Print solution number */ - } - for (i=0; i -#define HZ 50 - -double dtime() -{ - double q; - - struct tt - { - long days; - long minutes; - long ticks; - } tt; - - DateStamp(&tt); - - q = ((double)(tt.ticks + (tt.minutes * 60L * 50L))) / (double)HZ; - - return q; -} -#endif - -/*****************************************************/ -/* UNIX dtime(). This is the preferred UNIX timer. */ -/* Provided by: Markku Kolkka, mk59200@cc.tut.fi */ -/* HP-UX Addition by: Bo Thide', bt@irfu.se */ -/*****************************************************/ -#ifdef UNIX -#include -#include - -#ifdef hpux -#include -#define getrusage(a,b) syscall(SYS_getrusage,a,b) -#endif - -struct rusage rusage; - -double dtime() -{ - double q; - - getrusage(RUSAGE_SELF,&rusage); - - q = (double)(rusage.ru_utime.tv_sec); - q = q + (double)(rusage.ru_utime.tv_usec) * 1.0e-06; - - return q; -} -#endif - -/***************************************************/ -/* UNIX_Old dtime(). This is the old UNIX timer. */ -/* Make sure HZ is properly defined in param.h !! */ -/***************************************************/ -#ifdef UNIX_Old -#include -#include -#include - -#ifndef HZ -#define HZ 60 -#endif - -struct tms tms; - -double dtime() -{ - double q; - - times(&tms); - - q = (double)(tms.tms_utime) / (double)HZ; - - return q; -} -#endif - -/*********************************************************/ -/* VMS dtime() for VMS systems. */ -/* Provided by: RAMO@uvphys.phys.UVic.CA */ -/* Some people have run into problems with this timer. */ -/*********************************************************/ -#ifdef VMS -#include time - -#ifndef HZ -#define HZ 100 -#endif - -struct tbuffer_t - { - int proc_user_time; - int proc_system_time; - int child_user_time; - int child_system_time; - }; - -struct tbuffer_t tms; - -double dtime() -{ - double q; - - times(&tms); - - q = (double)(tms.proc_user_time) / (double)HZ; - - return q; -} -#endif - -/******************************/ -/* BORLAND C dtime() for DOS */ -/******************************/ -#ifdef BORLAND_C -#include -#include -#include - -#define HZ 100 -struct time tnow; - -double dtime() -{ - double q; - - gettime(&tnow); - - q = 60.0 * (double)(tnow.ti_min); - q = q + (double)(tnow.ti_sec); - q = q + (double)(tnow.ti_hund)/(double)HZ; - - return q; -} -#endif - -/**************************************/ -/* Microsoft C (MSC) dtime() for DOS */ -/**************************************/ -#ifdef MSC -#include -#include - -#define HZ CLOCKS_PER_SEC -clock_t tnow; - -double dtime() -{ - double q; - - tnow = clock(); - - q = (double)tnow / (double)HZ; - - return q; -} -#endif - -/*************************************/ -/* Macintosh (MAC) Think C dtime() */ -/*************************************/ -#ifdef MAC -#include - -#define HZ 60 - -double dtime() -{ - double q; - - q = (double)clock() / (double)HZ; - - return q; -} -#endif - -/************************************************************/ -/* iPSC/860 (IPSC) dtime() for i860. */ -/* Provided by: Dan Yergeau, yergeau@gloworm.Stanford.EDU */ -/************************************************************/ -#ifdef IPSC -extern double dclock(); - -double dtime() -{ - double q; - - q = dclock(); - - return q; -} -#endif - -/**************************************************/ -/* FORTRAN dtime() for Cray type systems. */ -/* This is the preferred timer for Cray systems. */ -/**************************************************/ -#ifdef FORTRAN_SEC - -fortran double second(); - -double dtime() -{ - double q; - - second(&q); - - return q; -} -#endif - -/***********************************************************/ -/* UNICOS C dtime() for Cray UNICOS systems. Don't use */ -/* unless absolutely necessary as returned time includes */ -/* 'user+system' time. Provided by: R. Mike Dority, */ -/* dority@craysea.cray.com */ -/***********************************************************/ -#ifdef CTimer -#include - -double dtime() -{ - double q; - clock_t clock(void); - - q = (double)clock() / (double)CLOCKS_PER_SEC; - - return q; -} -#endif - -/********************************************/ -/* Another UNIX timer using gettimeofday(). */ -/* However, getrusage() is preferred. */ -/********************************************/ -#ifdef GTODay -#include - -struct timeval tnow; - -double dtime() -{ - double q; - - gettimeofday(&tnow,NULL); - q = (double)tnow.tv_sec + (double)tnow.tv_usec * 1.0e-6; - - return q; -} -#endif - -/*****************************************************/ -/* Fujitsu UXP/M timer. */ -/* Provided by: Mathew Lim, ANUSF, M.Lim@anu.edu.au */ -/*****************************************************/ -#ifdef UXPM -#include -#include -struct tmsu rusage; - -double dtime() -{ - double q; - - timesu(&rusage); - - q = (double)(rusage.tms_utime) * 1.0e-06; - - return q; -} -#endif - -/**********************************************/ -/* Macintosh (MAC_TMgr) Think C dtime() */ -/* requires Think C Language Extensions or */ -/* #include in the prefix */ -/* provided by Francis H Schiffer 3rd (fhs) */ -/* skipschiffer@genie.geis.com */ -/**********************************************/ -#ifdef MAC_TMgr -#include -#include - -static TMTask mgrTimer; -static Boolean mgrInited = false; -static double mgrClock; - -#define RMV_TIMER RmvTime( (QElemPtr)&mgrTimer ) -#define MAX_TIME 1800000000L -/* MAX_TIME limits time between calls to */ -/* dtime( ) to no more than 30 minutes */ -/* this limitation could be removed by */ -/* creating a completion routine to sum */ -/* 30 minute segments (fhs 1994 feb 9) */ - -static void Remove_timer( ) -{ - RMV_TIMER; - mgrInited = false; -} - -double dtime( ) -{ - if( mgrInited ) { - RMV_TIMER; - mgrClock += (MAX_TIME + mgrTimer.tmCount)*1.0e-6; - } else { - if( _atexit( &Remove_timer ) == 0 ) mgrInited = true; - mgrClock = 0.0; - } - - if ( mgrInited ) - { - mgrTimer.tmAddr = NULL; - mgrTimer.tmCount = 0; - mgrTimer.tmWakeUp = 0; - mgrTimer.tmReserved = 0; - InsTime( (QElemPtr)&mgrTimer ); - PrimeTime( (QElemPtr)&mgrTimer, -MAX_TIME ); - } - return( mgrClock ); -} -#endif - -/***********************************************************/ -/* Parsytec GCel timer. */ -/* Provided by: Georg Wambach, gw@informatik.uni-koeln.de */ -/***********************************************************/ -#ifdef PARIX -#include - -double dtime() -{ - double q; - - q = (double) (TimeNowHigh()) / (double) CLK_TCK_HIGH; - - return q; -} -#endif - -/************************************************/ -/* Sun Solaris POSIX dtime() routine */ -/* Provided by: Case Larsen, CTLarsen.lbl.gov */ -/************************************************/ -#ifdef POSIX -#include -#include -#include - -#ifdef __hpux -#include -#endif - -struct rusage rusage; - -double dtime() -{ - double q; - - getrusage(RUSAGE_SELF,&rusage); - - q = (double)(rusage.ru_utime.tv_sec); - q = q + (double)(rusage.ru_utime.tv_nsec) * 1.0e-09; - - return q; -} -#endif - - -/****************************************************/ -/* Windows NT (32 bit) dtime() routine */ -/* Provided by: Piers Haken, piersh@microsoft.com */ -/****************************************************/ -#ifdef WIN32 -#include - -double dtime(void) -{ - double q; - - q = (double)GetTickCount() * 1.0e-03; - - return q; -} -#endif - -/*****************************************************/ -/* Time according to POSIX.1 - */ -/* Ref: "POSIX Programmer's Guide" O'Reilly & Assoc.*/ -/*****************************************************/ -#ifdef POSIX1 -#define _POSIX_SOURCE 1 -#include -#include -#include - -struct tms tms; - -double dtime() -{ - double q; - times(&tms); - q = (double)tms.tms_utime / (double)CLK_TCK; - return q; -} -#endif - -/*-------- End of queens.c, Say goodnight Linda! --------*/ diff --git a/lib/CPUs/MIPS/bsp/examples/r3.c b/lib/CPUs/MIPS/bsp/examples/r3.c deleted file mode 100644 index 77eb757..0000000 --- a/lib/CPUs/MIPS/bsp/examples/r3.c +++ /dev/null @@ -1,466 +0,0 @@ -/* - * IOCCC Raytracer by Anders Gavare. - * - * The raytracer was one of the winners of the 17th IOCCC. - * - * NOTE: This is the UNOBFUSCATED version of the raytracer I used - * during development, not the actual entry sent to the contest. - * - * - * How to build: - * cc r3.c -o r3 (plus optimization flags) - * - * How to run: - * ./r3 > ray.ppm - * or - * ./r3 | xv - - */ -#include "libsys.h" -UINT32 *pP; - -xsize = 800; -ysize = 600; -An = 3; - -camera_X = 0; -camera_Y = -10; -camera_Z = -7; - -scale = 1296; -RootOfScale = 36; -maxcolor = 255; - -MaxDepth=9; -_=1<<15; - -/* -double sphere_x[44] = { - -15,-15,-15,-15, // I - -8,-8,-10,-6,-10,-6, // O - -1,-1, 1,1, // C - 6, 6, 8,8, // C - 13,13,15,15, // C - -11,-11,-11,-11,-9,-9,-7,-7, // r - 0,0,-2,-2,-2,2,2,2, // a - 7,7,9,9,11,11, // y - }; -double sphere_z[44] = { - 3,0,-3,-6, // I - -6, 3,0,0,-3,-3, // O - 0,-3,-6, 3, // C - 0,-3,-6, 3, // C - 0,-3,-6, 3, // C - -11,-13,-15,-17,-11,-15,-13,-17, // r - -11,-15,-13,-15,-17,-13,-15,-17, // a - -11,-13,-15,-17,-11,-13, // y - }; -*/ - -/* Common return variable: */ -return_var; -return_var2; -return_var3; -return_var4; - - -get_sphere_coordinates(b) -{ - return_var = "1111886:6:??AAFFHHMMOO55557799@@>>>BBBGGIIKK"[b]-64; - return_var3 = "C@=::C@@==@=:C@=:C@=:C531/513/5131/31/531/53"[b]-64; - -/* return_var = sphere_x[b]; */ - return_var2 = b<22? 9 : 0; -/* return_var3 = sphere_z[b]; */ - return_var4 = 2; -} - - -/* sqroot(x) returns the square root of x in return_var */ -sqroot_sub(x, mask, guess) -{ - mask? - ( - guess ^= mask, - guess*guess > x ? - ( guess ^= mask ) - : - 0, - sqroot_sub(x, mask/2, guess) - ) - : - ( return_var = guess ); -} - - -sqroot(x) -{ - sqroot_sub(x, _, 0); -} - - -/* - * hit_sphere(): - * - * returns where on a sphere we hit - * Returns distance in hit_sphere_q. (Negative return - * value if we didn't hit anything.) - */ -hit_sphere_q; -hit_sphere(objnr, x, y, z, - dx, dy, dz, - a, b) -{ - get_sphere_coordinates(objnr); - x -= return_var*scale; - y -= return_var2*scale; - z -= return_var3*scale; - - /* - * Solve the following equation: - * - * q^2 (dx^2+dy^2+dz^2) + q * 2(x*dx+y*dy+z*dz) - * + x^2+y^2+z^2 - r^2 = 0 - * - * We assume that |dx,dy,dz| is 1. - * - * q^2 + a q + b = 0 - * - * The solution is (of course) - * - * q = -a/2 +- sqrt(a^2/4 - b) - */ - - b = x*x/scale+y*y/scale+z*z/scale-return_var4*return_var4*scale; - - /* a = 2*(...), and then divide by -2 */ - a = -x*dx/scale-y*dy/scale-z*dz/scale; - - hit_sphere_q = - ( - (b = a*a/scale - b) >= 0 ? - ( -/* b = scale*sqrt((double)b/(double)scale), */ -/* sqroot(b*scale), */ - -/* sqroot_sub(b, _, 0), - b = return_var * RootOfScale, -*/ - sqroot_sub(b*scale, _, 0), - b = return_var, - - /* - * Return the lowest q (a+b or a-b) which is more - * than 0. Return negative if neither - * a+b or a-b is more than 0. - */ - - a + (a>b? -b : b) - ) - : - -1.0 - ); -} - - -/* - * find_closest(): - * - * find_closest() scans objects and returns an index - * to the object which was closest (has the lowest 'q'). - * x,y,z,dx,dy,dz are scaled. - * find_closest_i is the index number of the found object, - * -1 if none was found. find_closest_q is the distance - * (scaled). - */ -find_closest_i; /* index ("sphere number") */ -find_closest_q; /* distance (scaled) */ -find_closest(objnr, x, y, z, - dx, dy, dz, notindex) -{ - /* Initialize find_closest_i on first call: */ - find_closest_i = - !objnr ? -1 : find_closest_i; - - objnr < 44 ? - ( - hit_sphere(objnr, x,y,z, dx,dy,dz, 0,0), - (hit_sphere_q > 0 && objnr!=notindex && - (hit_sphere_q0 && find_closest_i >= 0? - ( - /* find_closest_i and _q are the object - number and distance of the object we - hit. */ - - orig_x += dir_x*find_closest_q/scale, - orig_y += dir_y*find_closest_q/scale, - orig_z += dir_z*find_closest_q/scale, - - /* - * Calculate color (diffuse light): - * (Note: use nZ as a temp variable while - * calculating nY) - */ - get_sphere_coordinates(find_closest_i), - nX = orig_x - return_var*scale, - nY = orig_y - return_var2*scale, - nZ = orig_z - return_var3*scale, - - tmpcol = (-2*nX -2*nY + nZ) / 3, /* sqrt(9), */ - /* Set return_var to the length of the normal - vector (in this case the sphere radius) */ -/* return_var = sqrt(nX*nX + nY*nY +nZ*nZ), */ - sqroot(nX*nX + nY*nY +nZ*nZ), -// return_var = return_var4*scale, - /* divide by return_var to get the color */ -// tmpcol = return_var!=0? tmpcol*scale/return_var : 0, - tmpcol /= return_var4, - - /* color is now -1..1 */ - tmpcol *= tmpcol, /* square the color 1..-1 => 1..1 */ - tmpcol *= 200, - tmpcol /= (scale*scale), -/* tmpcol += 5, */ - - closest_i_saved = find_closest_i, - - /* Mirror: out = in - 2*(-normal)*cos v - where v is the angle between in and - -normal */ - - /* -normal: (normalized to len=1.0) */ -/* return_var = sqrt(nX*nX + nY*nY + nZ*nZ), */ - return_var!=0? - ( - nX = -nX * scale / return_var, - nY = -nY * scale / return_var, - nZ = -nZ * scale / return_var - ) : 0, - - /* use return_var as a temp variable, - calculate cosinus between the vectors */ - return_var = (dir_x*nX + dir_y*nY + dir_z*nZ)/scale, -/* - dir_x -= 2 * nX * return_var / scale, - dir_y -= 2 * nY * return_var / scale, - dir_z -= 2 * nZ * return_var / scale, -*/ - dir_x -= nX * return_var / (scale/2), - dir_y -= nY * return_var / (scale/2), - dir_z -= nZ * return_var / (scale/2), - - trace_ray(orig_x, orig_y, orig_z, - dir_x, dir_y, dir_z, - depth-1, find_closest_i, 0,0), - - trace_ray_R /= 2, - trace_ray_G /= 2, - trace_ray_B /= 2, -/* - closest_i_saved &= 7, - !closest_i_saved? (closest_i_saved++) : 0, -*/ -/* - closest_i_saved = closest_i_saved<4? closest_i_saved+1 : 7, -*/ -/* - tvinga gråskalor: closest_i_saved = 7, -*/ -closest_i_saved = closest_i_saved<22? 7 : - ( - closest_i_saved<30 ? 1 : - ( - closest_i_saved<38 ? 2 : - ( - closest_i_saved<44 ? 4 : - ( - closest_i_saved == 44 ? 6 : - 3 - ) - ) - ) - ), - - trace_ray_R += closest_i_saved & 1 ? tmpcol : 0, - trace_ray_G += closest_i_saved & 2 ? tmpcol : 0, - trace_ray_B += closest_i_saved & 4 ? tmpcol : 0 - ) - : - ( - /* If we didn't hit anything, set the color anyway: */ - - depth==MaxDepth? /* True if this is a ray originating - from the camera */ - ( - orig_z += 2, - dir_z = orig_z > 0? orig_z / 8 : orig_z / 20 - ) - : 0, - - /* - * Colors according to Horizon_1 in gimp: - * At top of sky: 13,92,146 (light blue) - * At bottom sky: 255,255,255 (white) - * Top of ground: 213,168,111 (light brown) - * Bottom of ground: 103, 55, 26 (brown) - */ - - dir_z > 0? - ( - trace_ray_B = dir_z * dir_z / scale, - trace_ray_R = 255 - 250 * trace_ray_B / scale, - trace_ray_G = 255 - 150 * trace_ray_B / scale, - trace_ray_B = 255 - 100 * trace_ray_B / scale - ) - : - ( - trace_ray_B = dir_z * dir_z / scale, - trace_ray_B < scale/5? - ( - trace_ray_R = 255 - 210 * trace_ray_B / scale, - trace_ray_G = 255 - 435 * trace_ray_B / scale, - trace_ray_B = 255 - 720 * trace_ray_B / scale - ) - : - ( - trace_ray_B -= scale/5, - trace_ray_R = 213 - 110 * trace_ray_B / scale, - trace_ray_G = 168 - 113 * trace_ray_B / scale, - trace_ray_B = 111 - 85 * trace_ray_B / scale - ) - ), - - depth!=MaxDepth? - ( - trace_ray_R /= 2, - trace_ray_G /= 2, - trace_ray_B /= 2 - ) - : 0 - ); - - trace_ray_R = trace_ray_R<0? 0 : trace_ray_R>maxcolor? maxcolor: trace_ray_R; - trace_ray_G = trace_ray_G<0? 0 : trace_ray_G>maxcolor? maxcolor : trace_ray_G; - trace_ray_B = trace_ray_B<0? 0 : trace_ray_B>maxcolor? maxcolor : trace_ray_B; -} - - -/* - * do_pixels_in_line(): - * - * the horizontal "for loop" - */ -R; G; B; -dpil_helper(x,y, a,b) -{ - trace_ray( - scale*camera_X + scale*40*(An*x+a)/xsize/An - scale*20, - scale*camera_Y, - scale*camera_Z - scale*30*(An*y+b)/ysize/An + scale*15, - 0, scale, 0, MaxDepth, -1, 0,0); - - R += trace_ray_R; - G += trace_ray_G; - B += trace_ray_B; - - ++a - -#define IA 16807 -#define IM 2147483647 -#define AM (1.0/IM) -#define IQ 127773 -#define IR 2836 -#define NTAB 32 -#define NDIV (1+(IM-1)/NTAB) -#define EPS 1.2e-14 -#define RNMX (1.0-EPS) -/* From Numerical Recipes, p. 280, modified from float to double */ -/* returns a uniform deviate in (0,1) */ -double ran1(long *idum) -{ - int j; - long k; - static long iy=0; - static long iv[NTAB]; - double temp; - - if (*idum <=0 || !iy) { - if (-(*idum) < 1) *idum=1; - else *idum = -(*idum); - for (j=NTAB+7; j>=0; j--) { - k=(*idum)/IQ; - *idum=IA*(*idum-k*IQ)-IR*k; - if (*idum < 0) *idum += IM; - if (j < NTAB) iv[j] = *idum; - } - iy = iv[0]; - } - k=(*idum)/IQ; - *idum=IA*(*idum-k*IQ)-IR*k; - if (*idum < 0) *idum += IM; - j=iy/NDIV; - iy=iv[j]; - iv[j] = *idum; - if ((temp=AM*iy) > RNMX) return RNMX; - else return temp; -} -#undef IA -#undef IM -#undef AM -#undef IQ -#undef IR -#undef NTAB -#undef NDIV -#undef EPS -#undef RNMX - -/* Generate a N(0,1) r.v. */ -double gaussian(long *idum) -{ - static int iset=0; - static double gset; - double fac,r,v1,v2; - double ran1(); - if (iset == 0) { - do { - v1=2.0*ran1(idum)-1.0; - v2=2.0*ran1(idum)-1.0; - r=v1*v1+v2*v2; - } while (r >= 1.0 || r == 0.0); - fac=sqrt(-2.0*log(r)/r); - gset=v1*fac; - iset=1; - return v2*fac; - } else { - iset=0; - return gset; - } -} - -/* generate a random bit */ -int random_bit(long *idum) -{ - return((ran1(idum)<0.5) ? 0 : 1); -} diff --git a/lib/CPUs/MIPS/bsp/examples/random.h b/lib/CPUs/MIPS/bsp/examples/random.h deleted file mode 100644 index 673d6af..0000000 --- a/lib/CPUs/MIPS/bsp/examples/random.h +++ /dev/null @@ -1,6 +0,0 @@ -/* random.h */ - -/* functions provided by random.c */ -extern double ran1(long *idum); -extern double gaussian(long *idum); -extern int random_bit(long *idum); diff --git a/lib/CPUs/MIPS/bsp/examples/regdef.h b/lib/CPUs/MIPS/bsp/examples/regdef.h deleted file mode 100644 index 60c6c2a..0000000 --- a/lib/CPUs/MIPS/bsp/examples/regdef.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H - -/* - * Symbolic register names for 32 bit ABI - */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ - -/* CP0 registers */ -#define CP0_INDEX $0 /* R3000 available */ -#define CP0_RANDOM $1 /* R3000 available */ -#define CP0_ENTRYLO $2 /* R3000 available */ -#define CP0_CONTEXT $4 /* R3000 available */ -#define CP0_BADDR $8 /* R3000 available */ -#define CP0_ENTRYHI $10 /* R3000 available */ -#define CP0_SR $12 /* R3000 available */ -#define CP0_CR $13 /* R3000 available */ -#define CP0_EPC $14 /* R3000 available */ -#define CP0_PRID $15 /* R3000 available */ - -/* Status register masks */ -#define SR_MASK_IEC 0x00000001 -#define SR_MASK_KUC 0x00000002 -#define SR_MASK_IEP 0x00000004 -#define SR_MASK_KUP 0x00000008 -#define SR_MASK_IEO 0x00000010 -#define SR_MASK_KUO 0x00000020 -#define SR_MASK_IM 0x0000FF00 -#define SR_MASK_DS 0x00FF0000 -#define SR_MASK_RE 0x01000000 -#define SR_MASK_CU 0xF0000000 - -/* Cause register masks */ -#define CR_MASK_EXC 0x0000007C -#define CR_MASK_IP 0x0000FF00 -#define CR_MASK_CE 0x40000000 -#define CR_MASK_BD 0x80000000 - -#endif /* _ASM_REGDEF_H */ diff --git a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c b/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c deleted file mode 100644 index f1fdfd0..0000000 --- a/lib/CPUs/MIPS/bsp/examples/richards_benchmark.c +++ /dev/null @@ -1,408 +0,0 @@ - -/* C version of the systems programming language benchmark -** Author: M. J. Jordan Cambridge Computer Laboratory. -** -** Modified by: M. Richards, Nov 1996 -** to be ANSI C and runnable on 64 bit machines + other minor changes -** Modified by: M. Richards, 20 Oct 1998 -** made minor corrections to improve ANSI compliance (suggested -** by David Levine) -** -** Compile with, say -** -** gcc -o bench bench.c -** -** or -** -** gcc -o bench100 -Dbench100 bench.c (for a version that obeys -** the main loop 100x more often) -*/ - -#include -#include - -#ifdef SMALL_PROBLEM_SIZE -#define Count 1000*1000 -#define Qpktcountval 2326389 -#define Holdcountval 930555 -#else -#define Count 10000*1000 -#define Qpktcountval 23263894 -#define Holdcountval 9305557 -#endif - - -#define TRUE 1 -#define FALSE 0 -#define MAXINT 32767 - -#define BUFSIZE 3 -#define I_IDLE 1 -#define I_WORK 2 -#define I_HANDLERA 3 -#define I_HANDLERB 4 -#define I_DEVA 5 -#define I_DEVB 6 -#define PKTBIT 1 -#define WAITBIT 2 -#define HOLDBIT 4 -#define NOTPKTBIT !1 -#define NOTWAITBIT !2 -#define NOTHOLDBIT 0XFFFB - -#define S_RUN 0 -#define S_RUNPKT 1 -#define S_WAIT 2 -#define S_WAITPKT 3 -#define S_HOLD 4 -#define S_HOLDPKT 5 -#define S_HOLDWAIT 6 -#define S_HOLDWAITPKT 7 - -#define K_DEV 1000 -#define K_WORK 1001 - -struct packet -{ - struct packet *p_link; - int p_id; - int p_kind; - int p_a1; - char p_a2[4]; -}; - -struct task -{ - struct task *t_link; - int t_id; - int t_pri; - struct packet *t_wkq; - int t_state; - struct task *(*t_fn)(struct packet *); - long t_v1; - long t_v2; -}; - -char alphabet[28] = "0ABCDEFGHIJKLMNOPQRSTUVWXYZ"; -struct task *tasktab[11] = {0,0,0,0,0,0,0,0,0,0,0}; -struct task *tasklist = 0; -struct task *tcb; -long taskid; -long v1; -long v2; -int qpktcount = 0; -int holdcount = 0; -int tracing = 1; -int layout = 0; - -void append(struct packet *pkt, struct packet *ptr); - -void createtask(int id, - int pri, - struct packet *wkq, - int state, - struct task *(*fn)(struct packet *), - long v1, - long v2) -{ - struct task *t = (struct task *)malloc(sizeof(struct task)); - - tasktab[id] = t; - t->t_link = tasklist; - t->t_id = id; - t->t_pri = pri; - t->t_wkq = wkq; - t->t_state = state; - t->t_fn = fn; - t->t_v1 = v1; - t->t_v2 = v2; - tasklist = t; -} - -struct packet *pkt(struct packet *link, int id, int kind) -{ - int i; - struct packet *p = (struct packet *)malloc(sizeof(struct packet)); - - for (i=0; i<=BUFSIZE; i++) - p->p_a2[i] = 0; - - p->p_link = link; - p->p_id = id; - p->p_kind = kind; - p->p_a1 = 0; - - return (p); -} - -void trace(char a) -{ - if ( --layout <= 0 ) - { - printf("\n"); - layout = 50; - } - - printf("%c", a); -} - -void schedule() -{ - while ( tcb != 0 ) - { - struct packet *pkt; - struct task *newtcb; - - pkt=0; - - switch ( tcb->t_state ) - { - case S_WAITPKT: - pkt = tcb->t_wkq; - tcb->t_wkq = pkt->p_link; - tcb->t_state = tcb->t_wkq == 0 ? S_RUN : S_RUNPKT; - - case S_RUN: - case S_RUNPKT: - taskid = tcb->t_id; - v1 = tcb->t_v1; - v2 = tcb->t_v2; - if (tracing==TRUE) trace(taskid+'0'); - - newtcb = (*(tcb->t_fn))(pkt); - tcb->t_v1 = v1; - tcb->t_v2 = v2; - tcb = newtcb; - break; - - case S_WAIT: - case S_HOLD: - case S_HOLDPKT: - case S_HOLDWAIT: - case S_HOLDWAITPKT: - tcb = tcb->t_link; - break; - - default: - return; - } - } -} - -struct task *Wait(void) -{ - tcb->t_state |= WAITBIT; - return (tcb); -} - -struct task *holdself(void) -{ - ++holdcount; - tcb->t_state |= HOLDBIT; - return (tcb->t_link) ; -} - -struct task *findtcb(int id) -{ - struct task *t = 0; - - if (1<=id && id<=(long)10) - t = tasktab[id]; - if (t==0) printf("\nBad task id %d\n", id); - return(t); -} - -struct task *release(int id) -{ - struct task *t; - - t = findtcb(id); - if ( t==0 ) return (0); - - t->t_state &= NOTHOLDBIT; - if ( t->t_pri > tcb->t_pri ) return (t); - - return (tcb) ; -} - - -struct task *qpkt(struct packet *pkt) -{ - struct task *t; - - t = findtcb(pkt->p_id); - if (t==0) return (t); - - qpktcount++; - - pkt->p_link = 0; - pkt->p_id = taskid; - - if (t->t_wkq==0) - { - t->t_wkq = pkt; - t->t_state |= PKTBIT; - if (t->t_pri > tcb->t_pri) return (t); - } - else - { - append(pkt, (struct packet *)&(t->t_wkq)); - } - - return (tcb); -} - -struct task *idlefn(struct packet *pkt) -{ - --v2; - if ( v2==0 ) return ( holdself() ); - - if ( (v1&1) == 0 ) - { - v1 = ( v1>>1) & MAXINT; - return ( release(I_DEVA) ); - } - else - { - v1 = ( (v1>>1) & MAXINT) ^ 0XD008; - return ( release(I_DEVB) ); - } -} - -struct task *workfn(struct packet *pkt) -{ - if ( pkt==0 ) return ( Wait() ); - else - { - int i; - - v1 = I_HANDLERA + I_HANDLERB - v1; - pkt->p_id = v1; - - pkt->p_a1 = 0; - for (i=0; i<=BUFSIZE; i++) - { - v2++; - if ( v2 > 26 ) v2 = 1; - (pkt->p_a2)[i] = alphabet[v2]; - } - return ( qpkt(pkt) ); - } -} - -struct task *handlerfn(struct packet *pkt) -{ - if ( pkt!=0) append(pkt, - (struct packet *)(pkt->p_kind==K_WORK ? &v1 : &v2)); - - if ( v1!=0 ) - { - int count; - struct packet *workpkt = (struct packet *)v1; - count = workpkt->p_a1; - - if ( count > BUFSIZE ) - { - v1 = (long)(((struct packet *)v1)->p_link); - return ( qpkt(workpkt) ); - } - - if ( v2!=0 ) - { - struct packet *devpkt; - - devpkt = (struct packet *)v2; - v2 = (long)(((struct packet *)v2)->p_link); - devpkt->p_a1 = workpkt->p_a2[count]; - workpkt->p_a1 = count+1; - return( qpkt(devpkt) ); - } - } - return ( Wait() ); -} - -struct task *devfn(struct packet *pkt) -{ - if ( pkt==0 ) - { - if ( v1==0 ) return ( Wait() ); - pkt = (struct packet *)v1; - v1 = 0; - return ( qpkt(pkt) ); - } - else - { - v1 = (long)pkt; - if (tracing==TRUE) trace(pkt->p_a1); - return ( holdself() ); - } -} - -void append(struct packet *pkt, struct packet *ptr) -{ - pkt->p_link = 0; - - while ( ptr->p_link ) ptr = ptr->p_link; - - ptr->p_link = pkt; -} - -int main() -{ - struct packet *wkq = 0; - int retval; - - printf("Bench mark starting\n"); - - createtask(I_IDLE, 0, wkq, S_RUN, idlefn, 1, Count); - - wkq = pkt(0, 0, K_WORK); - wkq = pkt(wkq, 0, K_WORK); - - createtask(I_WORK, 1000, wkq, S_WAITPKT, workfn, I_HANDLERA, 0); - - wkq = pkt(0, I_DEVA, K_DEV); - wkq = pkt(wkq, I_DEVA, K_DEV); - wkq = pkt(wkq, I_DEVA, K_DEV); - - createtask(I_HANDLERA, 2000, wkq, S_WAITPKT, handlerfn, 0, 0); - - wkq = pkt(0, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); - wkq = pkt(wkq, I_DEVB, K_DEV); - - createtask(I_HANDLERB, 3000, wkq, S_WAITPKT, handlerfn, 0, 0); - - wkq = 0; - createtask(I_DEVA, 4000, wkq, S_WAIT, devfn, 0, 0); - createtask(I_DEVB, 5000, wkq, S_WAIT, devfn, 0, 0); - - tcb = tasklist; - - qpktcount = holdcount = 0; - - printf("Starting\n"); - - tracing = FALSE; - layout = 0; - - schedule(); - - printf("finished\n"); - - printf("qpkt count = %d holdcount = %d\n", - qpktcount, holdcount); - - printf("These results are "); - if (qpktcount == Qpktcountval && holdcount == Holdcountval) { - printf("correct"); - retval = 0; - } else { - printf("incorrect"); - retval = 1; - } - - printf("\nend of run\n"); - return retval; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.c b/lib/CPUs/MIPS/bsp/examples/rmd160.c deleted file mode 100644 index 8b0f2c7..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160.c +++ /dev/null @@ -1,294 +0,0 @@ -/********************************************************************\ - * - * FILE: rmd160.c - * - * CONTENTS: A sample C-implementation of the RIPEMD-160 - * hash-function. - * TARGET: any computer with an ANSI C compiler - * - * AUTHOR: Antoon Bosselaers, ESAT-COSIC - * DATE: 1 March 1996 - * VERSION: 1.0 - * - * Copyright (c) Katholieke Universiteit Leuven - * 1996, All Rights Reserved - * - * Conditions for use of the RIPEMD-160 Software - * - * The RIPEMD-160 software is freely available for use under the terms and - * conditions described hereunder, which shall be deemed to be accepted by - * any user of the software and applicable on any use of the software: - * - * 1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for - * all purposes be considered the owner of the RIPEMD-160 software and of - * all copyright, trade secret, patent or other intellectual property - * rights therein. - * 2. The RIPEMD-160 software is provided on an "as is" basis without - * warranty of any sort, express or implied. K.U.Leuven makes no - * representation that the use of the software will not infringe any - * patent or proprietary right of third parties. User will indemnify - * K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities - * which may arise as a result of its use of the software. In no - * circumstances K.U.Leuven R&D will be held liable for any deficiency, - * fault or other mishappening with regard to the use or performance of - * the software. - * 3. User agrees to give due credit to K.U.Leuven in scientific publications - * or communications in relation with the use of the RIPEMD-160 software - * as follows: RIPEMD-160 software written by Antoon Bosselaers, - * available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/. - * -\********************************************************************/ - -/* header files */ -#include -#include -#include -#include "rmd160.h" - -/********************************************************************/ - -void MDinit(dword *MDbuf) -{ - MDbuf[0] = 0x67452301UL; - MDbuf[1] = 0xefcdab89UL; - MDbuf[2] = 0x98badcfeUL; - MDbuf[3] = 0x10325476UL; - MDbuf[4] = 0xc3d2e1f0UL; - - return; -} - -/********************************************************************/ - -void compress(dword *MDbuf, dword *X) -{ - dword aa = MDbuf[0], bb = MDbuf[1], cc = MDbuf[2], - dd = MDbuf[3], ee = MDbuf[4]; - dword aaa = MDbuf[0], bbb = MDbuf[1], ccc = MDbuf[2], - ddd = MDbuf[3], eee = MDbuf[4]; - - /* round 1 */ - FF(aa, bb, cc, dd, ee, X[ 0], 11); - FF(ee, aa, bb, cc, dd, X[ 1], 14); - FF(dd, ee, aa, bb, cc, X[ 2], 15); - FF(cc, dd, ee, aa, bb, X[ 3], 12); - FF(bb, cc, dd, ee, aa, X[ 4], 5); - FF(aa, bb, cc, dd, ee, X[ 5], 8); - FF(ee, aa, bb, cc, dd, X[ 6], 7); - FF(dd, ee, aa, bb, cc, X[ 7], 9); - FF(cc, dd, ee, aa, bb, X[ 8], 11); - FF(bb, cc, dd, ee, aa, X[ 9], 13); - FF(aa, bb, cc, dd, ee, X[10], 14); - FF(ee, aa, bb, cc, dd, X[11], 15); - FF(dd, ee, aa, bb, cc, X[12], 6); - FF(cc, dd, ee, aa, bb, X[13], 7); - FF(bb, cc, dd, ee, aa, X[14], 9); - FF(aa, bb, cc, dd, ee, X[15], 8); - - /* round 2 */ - GG(ee, aa, bb, cc, dd, X[ 7], 7); - GG(dd, ee, aa, bb, cc, X[ 4], 6); - GG(cc, dd, ee, aa, bb, X[13], 8); - GG(bb, cc, dd, ee, aa, X[ 1], 13); - GG(aa, bb, cc, dd, ee, X[10], 11); - GG(ee, aa, bb, cc, dd, X[ 6], 9); - GG(dd, ee, aa, bb, cc, X[15], 7); - GG(cc, dd, ee, aa, bb, X[ 3], 15); - GG(bb, cc, dd, ee, aa, X[12], 7); - GG(aa, bb, cc, dd, ee, X[ 0], 12); - GG(ee, aa, bb, cc, dd, X[ 9], 15); - GG(dd, ee, aa, bb, cc, X[ 5], 9); - GG(cc, dd, ee, aa, bb, X[ 2], 11); - GG(bb, cc, dd, ee, aa, X[14], 7); - GG(aa, bb, cc, dd, ee, X[11], 13); - GG(ee, aa, bb, cc, dd, X[ 8], 12); - - /* round 3 */ - HH(dd, ee, aa, bb, cc, X[ 3], 11); - HH(cc, dd, ee, aa, bb, X[10], 13); - HH(bb, cc, dd, ee, aa, X[14], 6); - HH(aa, bb, cc, dd, ee, X[ 4], 7); - HH(ee, aa, bb, cc, dd, X[ 9], 14); - HH(dd, ee, aa, bb, cc, X[15], 9); - HH(cc, dd, ee, aa, bb, X[ 8], 13); - HH(bb, cc, dd, ee, aa, X[ 1], 15); - HH(aa, bb, cc, dd, ee, X[ 2], 14); - HH(ee, aa, bb, cc, dd, X[ 7], 8); - HH(dd, ee, aa, bb, cc, X[ 0], 13); - HH(cc, dd, ee, aa, bb, X[ 6], 6); - HH(bb, cc, dd, ee, aa, X[13], 5); - HH(aa, bb, cc, dd, ee, X[11], 12); - HH(ee, aa, bb, cc, dd, X[ 5], 7); - HH(dd, ee, aa, bb, cc, X[12], 5); - - /* round 4 */ - II(cc, dd, ee, aa, bb, X[ 1], 11); - II(bb, cc, dd, ee, aa, X[ 9], 12); - II(aa, bb, cc, dd, ee, X[11], 14); - II(ee, aa, bb, cc, dd, X[10], 15); - II(dd, ee, aa, bb, cc, X[ 0], 14); - II(cc, dd, ee, aa, bb, X[ 8], 15); - II(bb, cc, dd, ee, aa, X[12], 9); - II(aa, bb, cc, dd, ee, X[ 4], 8); - II(ee, aa, bb, cc, dd, X[13], 9); - II(dd, ee, aa, bb, cc, X[ 3], 14); - II(cc, dd, ee, aa, bb, X[ 7], 5); - II(bb, cc, dd, ee, aa, X[15], 6); - II(aa, bb, cc, dd, ee, X[14], 8); - II(ee, aa, bb, cc, dd, X[ 5], 6); - II(dd, ee, aa, bb, cc, X[ 6], 5); - II(cc, dd, ee, aa, bb, X[ 2], 12); - - /* round 5 */ - JJ(bb, cc, dd, ee, aa, X[ 4], 9); - JJ(aa, bb, cc, dd, ee, X[ 0], 15); - JJ(ee, aa, bb, cc, dd, X[ 5], 5); - JJ(dd, ee, aa, bb, cc, X[ 9], 11); - JJ(cc, dd, ee, aa, bb, X[ 7], 6); - JJ(bb, cc, dd, ee, aa, X[12], 8); - JJ(aa, bb, cc, dd, ee, X[ 2], 13); - JJ(ee, aa, bb, cc, dd, X[10], 12); - JJ(dd, ee, aa, bb, cc, X[14], 5); - JJ(cc, dd, ee, aa, bb, X[ 1], 12); - JJ(bb, cc, dd, ee, aa, X[ 3], 13); - JJ(aa, bb, cc, dd, ee, X[ 8], 14); - JJ(ee, aa, bb, cc, dd, X[11], 11); - JJ(dd, ee, aa, bb, cc, X[ 6], 8); - JJ(cc, dd, ee, aa, bb, X[15], 5); - JJ(bb, cc, dd, ee, aa, X[13], 6); - - /* parallel round 1 */ - JJJ(aaa, bbb, ccc, ddd, eee, X[ 5], 8); - JJJ(eee, aaa, bbb, ccc, ddd, X[14], 9); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 7], 9); - JJJ(ccc, ddd, eee, aaa, bbb, X[ 0], 11); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 9], 13); - JJJ(aaa, bbb, ccc, ddd, eee, X[ 2], 15); - JJJ(eee, aaa, bbb, ccc, ddd, X[11], 15); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 4], 5); - JJJ(ccc, ddd, eee, aaa, bbb, X[13], 7); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 6], 7); - JJJ(aaa, bbb, ccc, ddd, eee, X[15], 8); - JJJ(eee, aaa, bbb, ccc, ddd, X[ 8], 11); - JJJ(ddd, eee, aaa, bbb, ccc, X[ 1], 14); - JJJ(ccc, ddd, eee, aaa, bbb, X[10], 14); - JJJ(bbb, ccc, ddd, eee, aaa, X[ 3], 12); - JJJ(aaa, bbb, ccc, ddd, eee, X[12], 6); - - /* parallel round 2 */ - III(eee, aaa, bbb, ccc, ddd, X[ 6], 9); - III(ddd, eee, aaa, bbb, ccc, X[11], 13); - III(ccc, ddd, eee, aaa, bbb, X[ 3], 15); - III(bbb, ccc, ddd, eee, aaa, X[ 7], 7); - III(aaa, bbb, ccc, ddd, eee, X[ 0], 12); - III(eee, aaa, bbb, ccc, ddd, X[13], 8); - III(ddd, eee, aaa, bbb, ccc, X[ 5], 9); - III(ccc, ddd, eee, aaa, bbb, X[10], 11); - III(bbb, ccc, ddd, eee, aaa, X[14], 7); - III(aaa, bbb, ccc, ddd, eee, X[15], 7); - III(eee, aaa, bbb, ccc, ddd, X[ 8], 12); - III(ddd, eee, aaa, bbb, ccc, X[12], 7); - III(ccc, ddd, eee, aaa, bbb, X[ 4], 6); - III(bbb, ccc, ddd, eee, aaa, X[ 9], 15); - III(aaa, bbb, ccc, ddd, eee, X[ 1], 13); - III(eee, aaa, bbb, ccc, ddd, X[ 2], 11); - - /* parallel round 3 */ - HHH(ddd, eee, aaa, bbb, ccc, X[15], 9); - HHH(ccc, ddd, eee, aaa, bbb, X[ 5], 7); - HHH(bbb, ccc, ddd, eee, aaa, X[ 1], 15); - HHH(aaa, bbb, ccc, ddd, eee, X[ 3], 11); - HHH(eee, aaa, bbb, ccc, ddd, X[ 7], 8); - HHH(ddd, eee, aaa, bbb, ccc, X[14], 6); - HHH(ccc, ddd, eee, aaa, bbb, X[ 6], 6); - HHH(bbb, ccc, ddd, eee, aaa, X[ 9], 14); - HHH(aaa, bbb, ccc, ddd, eee, X[11], 12); - HHH(eee, aaa, bbb, ccc, ddd, X[ 8], 13); - HHH(ddd, eee, aaa, bbb, ccc, X[12], 5); - HHH(ccc, ddd, eee, aaa, bbb, X[ 2], 14); - HHH(bbb, ccc, ddd, eee, aaa, X[10], 13); - HHH(aaa, bbb, ccc, ddd, eee, X[ 0], 13); - HHH(eee, aaa, bbb, ccc, ddd, X[ 4], 7); - HHH(ddd, eee, aaa, bbb, ccc, X[13], 5); - - /* parallel round 4 */ - GGG(ccc, ddd, eee, aaa, bbb, X[ 8], 15); - GGG(bbb, ccc, ddd, eee, aaa, X[ 6], 5); - GGG(aaa, bbb, ccc, ddd, eee, X[ 4], 8); - GGG(eee, aaa, bbb, ccc, ddd, X[ 1], 11); - GGG(ddd, eee, aaa, bbb, ccc, X[ 3], 14); - GGG(ccc, ddd, eee, aaa, bbb, X[11], 14); - GGG(bbb, ccc, ddd, eee, aaa, X[15], 6); - GGG(aaa, bbb, ccc, ddd, eee, X[ 0], 14); - GGG(eee, aaa, bbb, ccc, ddd, X[ 5], 6); - GGG(ddd, eee, aaa, bbb, ccc, X[12], 9); - GGG(ccc, ddd, eee, aaa, bbb, X[ 2], 12); - GGG(bbb, ccc, ddd, eee, aaa, X[13], 9); - GGG(aaa, bbb, ccc, ddd, eee, X[ 9], 12); - GGG(eee, aaa, bbb, ccc, ddd, X[ 7], 5); - GGG(ddd, eee, aaa, bbb, ccc, X[10], 15); - GGG(ccc, ddd, eee, aaa, bbb, X[14], 8); - - /* parallel round 5 */ - FFF(bbb, ccc, ddd, eee, aaa, X[12] , 8); - FFF(aaa, bbb, ccc, ddd, eee, X[15] , 5); - FFF(eee, aaa, bbb, ccc, ddd, X[10] , 12); - FFF(ddd, eee, aaa, bbb, ccc, X[ 4] , 9); - FFF(ccc, ddd, eee, aaa, bbb, X[ 1] , 12); - FFF(bbb, ccc, ddd, eee, aaa, X[ 5] , 5); - FFF(aaa, bbb, ccc, ddd, eee, X[ 8] , 14); - FFF(eee, aaa, bbb, ccc, ddd, X[ 7] , 6); - FFF(ddd, eee, aaa, bbb, ccc, X[ 6] , 8); - FFF(ccc, ddd, eee, aaa, bbb, X[ 2] , 13); - FFF(bbb, ccc, ddd, eee, aaa, X[13] , 6); - FFF(aaa, bbb, ccc, ddd, eee, X[14] , 5); - FFF(eee, aaa, bbb, ccc, ddd, X[ 0] , 15); - FFF(ddd, eee, aaa, bbb, ccc, X[ 3] , 13); - FFF(ccc, ddd, eee, aaa, bbb, X[ 9] , 11); - FFF(bbb, ccc, ddd, eee, aaa, X[11] , 11); - - /* combine results */ - ddd += cc + MDbuf[1]; /* final result for MDbuf[0] */ - MDbuf[1] = MDbuf[2] + dd + eee; - MDbuf[2] = MDbuf[3] + ee + aaa; - MDbuf[3] = MDbuf[4] + aa + bbb; - MDbuf[4] = MDbuf[0] + bb + ccc; - MDbuf[0] = ddd; - - return; -} - -/********************************************************************/ - -void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen) -{ - unsigned int i; /* counter */ - dword X[16]; /* message words */ - - memset(X, 0, 16*sizeof(dword)); - - /* put bytes from strptr into X */ - for (i=0; i<(lswlen&63); i++) { - /* byte i goes into word X[i div 4] at pos. 8*(i mod 4) */ - X[i>>2] ^= (dword) *strptr++ << (8 * (i&3)); - } - - /* append the bit m_n == 1 */ - X[(lswlen>>2)&15] ^= (dword)1 << (8*(lswlen&3) + 7); - - if ((lswlen & 63) > 55) { - /* length goes to next block */ - compress(MDbuf, X); - memset(X, 0, 16*sizeof(dword)); - } - - /* append length in bits*/ - X[14] = lswlen << 3; - X[15] = (lswlen >> 29) | (mswlen << 3); - compress(MDbuf, X); - - return; -} - -/************************ end of file rmd160.c **********************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160.h b/lib/CPUs/MIPS/bsp/examples/rmd160.h deleted file mode 100644 index 70a33a6..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160.h +++ /dev/null @@ -1,154 +0,0 @@ -/********************************************************************\ - * - * FILE: rmd160.h - * - * CONTENTS: Header file for a sample C-implementation of the - * RIPEMD-160 hash-function. - * TARGET: any computer with an ANSI C compiler - * - * AUTHOR: Antoon Bosselaers, ESAT-COSIC - * DATE: 1 March 1996 - * VERSION: 1.0 - * - * Copyright (c) Katholieke Universiteit Leuven - * 1996, All Rights Reserved - * - * Conditions for use of the RIPEMD-160 Software - * - * The RIPEMD-160 software is freely available for use under the terms and - * conditions described hereunder, which shall be deemed to be accepted by - * any user of the software and applicable on any use of the software: - * - * 1. K.U.Leuven Department of Electrical Engineering-ESAT/COSIC shall for - * all purposes be considered the owner of the RIPEMD-160 software and of - * all copyright, trade secret, patent or other intellectual property - * rights therein. - * 2. The RIPEMD-160 software is provided on an "as is" basis without - * warranty of any sort, express or implied. K.U.Leuven makes no - * representation that the use of the software will not infringe any - * patent or proprietary right of third parties. User will indemnify - * K.U.Leuven and hold K.U.Leuven harmless from any claims or liabilities - * which may arise as a result of its use of the software. In no - * circumstances K.U.Leuven R&D will be held liable for any deficiency, - * fault or other mishappening with regard to the use or performance of - * the software. - * 3. User agrees to give due credit to K.U.Leuven in scientific publications - * or communications in relation with the use of the RIPEMD-160 software - * as follows: RIPEMD-160 software written by Antoon Bosselaers, - * available at http://www.esat.kuleuven.be/~cosicart/ps/AB-9601/. - * -\********************************************************************/ - -#ifndef RMD160H /* make sure this file is read only once */ -#define RMD160H - -/********************************************************************/ - -/* typedef 8 and 32 bit types, resp. */ -/* adapt these, if necessary, - for your operating system and compiler */ -typedef unsigned char byte; -typedef unsigned long dword; - - -/********************************************************************/ - -/* macro definitions */ - -/* collect four bytes into one word: */ -#define BYTES_TO_DWORD(strptr) \ - (((dword) *((strptr)+3) << 24) | \ - ((dword) *((strptr)+2) << 16) | \ - ((dword) *((strptr)+1) << 8) | \ - ((dword) *(strptr))) - -/* ROL(x, n) cyclically rotates x over n bits to the left */ -/* x must be of an unsigned 32 bits type and 0 <= n < 32. */ -#define ROL(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* the five basic functions F(), G() and H() */ -#define F(x, y, z) ((x) ^ (y) ^ (z)) -#define G(x, y, z) (((x) & (y)) | (~(x) & (z))) -#define H(x, y, z) (((x) | ~(y)) ^ (z)) -#define I(x, y, z) (((x) & (z)) | ((y) & ~(z))) -#define J(x, y, z) ((x) ^ ((y) | ~(z))) - -/* the ten basic operations FF() through III() */ -#define FF(a, b, c, d, e, x, s) {\ - (a) += F((b), (c), (d)) + (x);\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define GG(a, b, c, d, e, x, s) {\ - (a) += G((b), (c), (d)) + (x) + 0x5a827999UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define HH(a, b, c, d, e, x, s) {\ - (a) += H((b), (c), (d)) + (x) + 0x6ed9eba1UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define II(a, b, c, d, e, x, s) {\ - (a) += I((b), (c), (d)) + (x) + 0x8f1bbcdcUL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define JJ(a, b, c, d, e, x, s) {\ - (a) += J((b), (c), (d)) + (x) + 0xa953fd4eUL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define FFF(a, b, c, d, e, x, s) {\ - (a) += F((b), (c), (d)) + (x);\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define GGG(a, b, c, d, e, x, s) {\ - (a) += G((b), (c), (d)) + (x) + 0x7a6d76e9UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define HHH(a, b, c, d, e, x, s) {\ - (a) += H((b), (c), (d)) + (x) + 0x6d703ef3UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define III(a, b, c, d, e, x, s) {\ - (a) += I((b), (c), (d)) + (x) + 0x5c4dd124UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } -#define JJJ(a, b, c, d, e, x, s) {\ - (a) += J((b), (c), (d)) + (x) + 0x50a28be6UL;\ - (a) = ROL((a), (s)) + (e);\ - (c) = ROL((c), 10);\ - } - -/********************************************************************/ - -/* function prototypes */ - -void MDinit(dword *MDbuf); -/* - * initializes MDbuffer to "magic constants" - */ - -void compress(dword *MDbuf, dword *X); -/* - * the compression function. - * transforms MDbuf using message bytes X[0] through X[15] - */ - -void MDfinish(dword *MDbuf, byte *strptr, dword lswlen, dword mswlen); -/* - * puts bytes from strptr into X and pad out; appends length - * and finally, compresses the last block(s) - * note: length in bits == 8 * (lswlen + 2^32 mswlen). - * note: there are (lswlen mod 64) bytes left in strptr. - */ - -#endif /* RMD160H */ - -/*********************** end of file rmd160.h ***********************/ - diff --git a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c b/lib/CPUs/MIPS/bsp/examples/rmd160_test.c deleted file mode 100644 index 783a558..0000000 --- a/lib/CPUs/MIPS/bsp/examples/rmd160_test.c +++ /dev/null @@ -1,104 +0,0 @@ -#include -#include -#include -#include "libsys.h" - -#include "rmd160.h" - -#ifndef RMDsize -#define RMDsize 160 -#endif - -byte *RMD(byte *message) -/* - * returns RMD(message) - * message should be a string terminated by '\0' - */ -{ - dword MDbuf[RMDsize/32]; /* contains (A, B, C, D(, E)) */ - static byte hashcode[RMDsize/8]; /* for final hash-value */ - dword X[16]; /* current 16-word chunk */ - unsigned int i; /* counter */ - dword length; /* length in bytes of message */ - dword nbytes; /* # of bytes not yet processed */ - - /* initialize */ - MDinit(MDbuf); - length = (dword)strlen((char *)message); - - /* process message in 16-word chunks */ - for (nbytes=length; nbytes > 63; nbytes-=64) { - for (i=0; i<16; i++) { - X[i] = BYTES_TO_DWORD(message); - message += 4; - } - compress(MDbuf, X); - } /* length mod 64 bytes left */ - - /* finish: */ - MDfinish(MDbuf, message, length, 0); - - for (i=0; i>2]; /* implicit cast to byte */ - hashcode[i+1] = (MDbuf[i>>2] >> 8); /* extracts the 8 least */ - hashcode[i+2] = (MDbuf[i>>2] >> 16); /* significant bits. */ - hashcode[i+3] = (MDbuf[i>>2] >> 24); - } - - return (byte *)hashcode; -} - -#define MSG_SIZE 1024*1024 // Bit -int main (void) -{ - int result, i, j, cnt; - byte *hashcode; - byte hashref[] = {0xFC,0x20,0x7B,0x84,0x40,0x1C,0x49,0x0B,0x8D,0x69,0x88,0xD2,0x49,0x20,0x01,0x90,0x41,0x77,0x72,0x59}; - char msg[MSG_SIZE/8+1]; - char crlf[] = "\n"; - UINT32 start, stop; - - for (i=0; i < MSG_SIZE/8; i++) - msg[i] = 0x55; - - msg[i] = 0; - - setbuf(stdout, NULL); - - cnt = 0; - start = time(NULL); - stop = start + 1; - while(1) - { - hashcode = RMD((byte *)msg); - start = time(NULL); - if (memcmp(hashcode, hashref, sizeof(hashref))) - { - printf("Error RipeMD-160!\n"); - printf("Hash expected: "); - for (i=0; i= stop) - { - for (i=0; i %d Mbit/s\n\n", cnt, MSG_SIZE/(1024*1024), cnt*MSG_SIZE/(1024*1024)); - start = time(NULL); - stop = start + 1; - cnt = 0; - } - cnt++; - } - - return 0; -} - diff --git a/lib/CPUs/MIPS/bsp/examples/stanford.c b/lib/CPUs/MIPS/bsp/examples/stanford.c deleted file mode 100644 index 907477b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/stanford.c +++ /dev/null @@ -1,1117 +0,0 @@ -/* stanford baby benchmark suite from john hennessy -- - -There are copies all around; the MIPS performance brief has up-to-date -numbers for a bunch of machines. BUT, these wouldn't be my first -choice. SPEC, the industry benchmark collection group, will probably -specify a new set of benchmarks shortly and release then right after -that. I imagine they will include espresso, gcc, and other large, but -public domain programs, for real things. - -here's bench.c - John Hennessy -*/ - - -/* This is a suite of benchmarks that are relatively short, both in program - size and execution time. It requires no input, and prints the execution - time for each program, using the system- dependent routine Getclock, - below, to find out the current CPU time. It does a rudimentary check to - make sure each program gets the right output. These programs were - gathered by John Hennessy and modified by Peter Nye. - -4.2 VERSION */ - -#include -#include -#include -#include - -#ifndef HZ -#define HZ 60 -#endif -#define nil 0 -#define false 0 -#define true 1 -#define bubblebase 1.61 -#define dnfbase 3.5 -#define permbase 1.75 -#define queensbase 1.83 -#define towersbase 2.39 -#define quickbase 1.92 -#define intmmbase 1.46 -#define treebase 2.5 -#define mmbase 0.0 -#define fpmmbase 2.92 -#define puzzlebase 0.5 -#define fftbase 0.0 -#define fpfftbase 4.44 - /* Towers */ -#define maxcells 18 - - /* Intmm, Mm */ -#define rowsize 40 - - /* Puzzle */ -#define size 511 -#define classmax 3 -#define typemax 12 -#define d 8 - - /* Bubble, Quick */ -#define sortelements 5000 -#define srtelements 500 - - /* fft */ -#define fftsize 256 -#define fftsize2 129 -/* -type */ - /* Perm */ -#define permrange 10 - - /* tree */ -struct node -{ - struct node *left, *right; - int val; -}; - -/* Towers *//* - discsizrange = 1..maxcells; */ -#define stackrange 3 -/* cellcursor = 0..maxcells; */ -struct element -{ - int discsize; - int next; -}; -/* emsgtype = packed array[1..15] of char; -*/ -/* Intmm, Mm *//* - index = 1 .. rowsize; - intmatrix = array [index,index] of integer; - realmatrix = array [index,index] of real; - */ -/* Puzzle *//* - piececlass = 0..classmax; - piecetype = 0..typemax; - position = 0..size; - */ -/* Bubble, Quick *//* - listsize = 0..sortelements; - sortarray = array [listsize] of integer; - */ - /* FFT */ -struct complex -{ - float rp, ip; -}; -/* - carray = array [1..fftsize] of complex ; - c2array = array [1..fftsize2] of complex ; -*/ - -float value; -float fixed, floated; - - /* global */ -int timer; -int xtimes[11]; -int seed; - - /* Perm */ -int permarray[permrange + 1]; -int pctr; - - /* tree */ -struct node *tree; - - /* Towers */ -int stack[stackrange + 1]; -struct element cellspace[maxcells + 1]; -int freelist, movesdone; - - /* Intmm, Mm */ -int ima[rowsize + 1][rowsize + 1], imb[rowsize + 1][rowsize + 1], - imr[rowsize + 1][rowsize + 1]; -float rma[rowsize + 1][rowsize + 1], rmb[rowsize + 1][rowsize + 1], - rmr[rowsize + 1][rowsize + 1]; - - /* Puzzle */ -int piececount[classmax + 1], - class[typemax + 1], - piecemax[typemax + 1], - puzzl[size + 1], p[typemax + 1][size + 1], n, kount; - - /* Bubble, Quick */ -int sortlist[sortelements + 1], biggest, littlest, top; - - /* FFT */ -struct complex z[fftsize + 1], w[fftsize + 1], e[fftsize2 + 1]; -float zr, zi; - -/* global procedures */ - -int -Getclock () -{ - struct tms rusage; - times (&rusage); - return ((60*rusage.tms_utime/HZ) * 50 / 3); -}; - -Initrand () -{ - seed = 74755; -}; - -int -Rand () -{ - seed = (seed * 1309 + 13849) & 65535; - return (seed); -}; - - - - /* Permutation program, heavily recursive, written by Denny Brown. */ - -Swap (a, b) - int *a, *b; -{ - int t; - t = *a; - *a = *b; - *b = t; -}; - -Initialize () -{ - int i; - for (i = 1; i <= 7; i++) - { - permarray[i] = i - 1; - }; -}; - -Permute (n) - int n; -{ /* permute */ - int k; - pctr = pctr + 1; - if (n != 1) - { - Permute (n - 1); - for (k = n - 1; k >= 1; k--) - { - Swap (&permarray[n], &permarray[k]); - Permute (n - 1); - Swap (&permarray[n], &permarray[k]); - }; - }; -} /* permute */ ; - -Perm () -{ /* Perm */ - int i; - pctr = 0; - for (i = 1; i <= 5; i++) - { - Initialize (); - Permute (7); - }; - if (pctr != 43300) - printf (" Error in Perm.\n"); -} /* Perm */ ; - - - - /* Program to Solve the Towers of Hanoi */ - -Error (emsg) - char *emsg; -{ - printf (" Error in Towers: %s\n", emsg); -}; - -Makenull (s) -{ - stack[s] = 0; -}; - -int -Getelement () -{ - int temp; - if (freelist > 0) - { - temp = freelist; - freelist = cellspace[freelist].next; - } - else - Error ("out of space "); - return (temp); -}; - -Push (i, s) - int i, s; -{ - int errorfound, localel; - errorfound = false; - if (stack[s] > 0) - if (cellspace[stack[s]].discsize <= i) - { - errorfound = true; - Error ("disc size error"); - }; - if (!errorfound) - { - localel = Getelement (); - cellspace[localel].next = stack[s]; - stack[s] = localel; - cellspace[localel].discsize = i; - } -}; - -Init (s, n) - int s, n; -{ - int discctr; - Makenull (s); - for (discctr = n; discctr >= 1; discctr--) - Push (discctr, s); -}; - -int -Pop (s) - int s; -{ - int temp, temp1; - if (stack[s] > 0) - { - temp1 = cellspace[stack[s]].discsize; - temp = cellspace[stack[s]].next; - cellspace[stack[s]].next = freelist; - freelist = stack[s]; - stack[s] = temp; - return (temp1); - } - else - Error ("nothing to pop "); -}; - -Move (s1, s2) - int s1, s2; -{ - Push (Pop (s1), s2); - movesdone = movesdone + 1; -}; - -tower (i, j, k) - int i, j, k; -{ - int other; - if (k == 1) - Move (i, j); - else - { - other = 6 - i - j; - tower (i, other, k - 1); - Move (i, j); - tower (other, j, k - 1); - } -}; - - -Towers () -{ /* Towers */ - int i; - for (i = 1; i <= maxcells; i++) - cellspace[i].next = i - 1; - freelist = maxcells; - Init (1, 14); - Makenull (2); - Makenull (3); - movesdone = 0; - tower (1, 2, 14); - if (movesdone != 16383) - printf (" Error in Towers.\n"); -}; /* Towers */ - - - /* The eight queens problem, solved 50 times. */ -/* - type - doubleboard = 2..16; - doublenorm = -7..7; - boardrange = 1..8; - aarray = array [boardrange] of boolean; - barray = array [doubleboard] of boolean; - carray = array [doublenorm] of boolean; - xarray = array [boardrange] of boardrange; -*/ - -Try (i, q, a, b, c, x) - int i, *q, a[], b[], c[], x[]; -{ - int j; - j = 0; - *q = false; - while ((!*q) && (j != 8)) - { - j = j + 1; - *q = false; - if (b[j] && a[i + j] && c[i - j + 7]) - { - x[i] = j; - b[j] = false; - a[i + j] = false; - c[i - j + 7] = false; - if (i < 8) - { - Try (i + 1, q, a, b, c, x); - if (!*q) - { - b[j] = true; - a[i + j] = true; - c[i - j + 7] = true; - } - } - else - *q = true; - } - } -}; - -Doit () -{ - int i, q; - int a[9], b[17], c[15], x[9]; - i = 0 - 7; - while (i <= 16) - { - if ((i >= 1) && (i <= 8)) - a[i] = true; - if (i >= 2) - b[i] = true; - if (i <= 7) - c[i + 7] = true; - i = i + 1; - }; - - Try (1, &q, b, a, c, x); - if (!q) - printf (" Error in Queens.\n"); -}; - -Queens () -{ - int i; - for (i = 1; i <= 50; i++) - Doit (); -}; - - /* Multiplies two integer matrices. */ - -Initmatrix (m) - int m[rowsize + 1][rowsize + 1]; -{ - int temp, i, j; - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - { - temp = Rand (); - m[i][j] = temp - (temp / 120) * 120 - 60; - } -}; - -Innerproduct (result, a, b, row, column) - int *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1], - row, column; - /* computes the inner product of A[row,*] and B[*,column] */ -{ - int i; - *result = 0; - for (i = 1; i <= rowsize; i++) - *result = *result + a[row][i] * b[i][column]; -}; - -Intmm () -{ - int i, j; - Initrand (); - Initmatrix (ima); - Initmatrix (imb); - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - Innerproduct (&imr[i][j], ima, imb, i, j); -}; - - - /* Multiplies two real matrices. */ - -rInitmatrix (m) - float m[rowsize + 1][rowsize + 1]; -{ - int temp, i, j; - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - { - temp = Rand (); - m[i][j] = (temp - (temp / 120) * 120 - 60) / 3; - } -}; - -rInnerproduct (result, a, b, row, column) - float *result, a[rowsize + 1][rowsize + 1], b[rowsize + 1][rowsize + 1]; - int row, column; - /* computes the inner product of A[row,*] and B[*,column] */ -{ - int i; - *result = 0.0; - for (i = 1; i <= rowsize; i++) - *result = *result + a[row][i] * b[i][column]; -}; - -Mm () -{ - int i, j; - Initrand (); - rInitmatrix (rma); - rInitmatrix (rmb); - for (i = 1; i <= rowsize; i++) - for (j = 1; j <= rowsize; j++) - rInnerproduct (&rmr[i][j], rma, rmb, i, j); -}; - - - - - /* A compute-bound program from Forest Baskett. */ - -int -Fit (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - if (puzzl[j + k]) - return (false); - return (true); -}; - -int -Place (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - puzzl[j + k] = true; - piececount[class[i]] = piececount[class[i]] - 1; - for (k = j; k <= size; k++) - if (!puzzl[k]) - { - return (k); - }; - return (0); -}; - -Remove (i, j) - int i, j; -{ - int k; - for (k = 0; k <= piecemax[i]; k++) - if (p[i][k]) - puzzl[j + k] = false; - piececount[class[i]] = piececount[class[i]] + 1; -}; - -int -Trial (j) - int j; -{ - int i, k; - kount = kount + 1; - for (i = 0; i <= typemax; i++) - if (piececount[class[i]] != 0) - if (Fit (i, j)) - { - k = Place (i, j); - if (Trial (k) || (k == 0)) - { - return (true); - } - else - Remove (i, j); - }; - return (false); -}; - -Puzzle () -{ - int i, j, k, m; - for (m = 0; m <= size; m++) - puzzl[m] = true; - for (i = 1; i <= 5; i++) - for (j = 1; j <= 5; j++) - for (k = 1; k <= 5; k++) - puzzl[i + d * (j + d * k)] = false; - for (i = 0; i <= typemax; i++) - for (m = 0; m <= size; m++) - p[i][m] = false; - for (i = 0; i <= 3; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 0; k++) - p[0][i + d * (j + d * k)] = true; - class[0] = 0; - piecemax[0] = 3 + d * 1 + d * d * 0; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 3; k++) - p[1][i + d * (j + d * k)] = true; - class[1] = 0; - piecemax[1] = 1 + d * 0 + d * d * 3; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 3; j++) - for (k = 0; k <= 1; k++) - p[2][i + d * (j + d * k)] = true; - class[2] = 0; - piecemax[2] = 0 + d * 3 + d * d * 1; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 3; j++) - for (k = 0; k <= 0; k++) - p[3][i + d * (j + d * k)] = true; - class[3] = 0; - piecemax[3] = 1 + d * 3 + d * d * 0; - for (i = 0; i <= 3; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 1; k++) - p[4][i + d * (j + d * k)] = true; - class[4] = 0; - piecemax[4] = 3 + d * 0 + d * d * 1; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 3; k++) - p[5][i + d * (j + d * k)] = true; - class[5] = 0; - piecemax[5] = 0 + d * 1 + d * d * 3; - for (i = 0; i <= 2; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 0; k++) - p[6][i + d * (j + d * k)] = true; - class[6] = 1; - piecemax[6] = 2 + d * 0 + d * d * 0; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 2; j++) - for (k = 0; k <= 0; k++) - p[7][i + d * (j + d * k)] = true; - class[7] = 1; - piecemax[7] = 0 + d * 2 + d * d * 0; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 2; k++) - p[8][i + d * (j + d * k)] = true; - class[8] = 1; - piecemax[8] = 0 + d * 0 + d * d * 2; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 0; k++) - p[9][i + d * (j + d * k)] = true; - class[9] = 2; - piecemax[9] = 1 + d * 1 + d * d * 0; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 0; j++) - for (k = 0; k <= 1; k++) - p[10][i + d * (j + d * k)] = true; - class[10] = 2; - piecemax[10] = 1 + d * 0 + d * d * 1; - for (i = 0; i <= 0; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 1; k++) - p[11][i + d * (j + d * k)] = true; - class[11] = 2; - piecemax[11] = 0 + d * 1 + d * d * 1; - for (i = 0; i <= 1; i++) - for (j = 0; j <= 1; j++) - for (k = 0; k <= 1; k++) - p[12][i + d * (j + d * k)] = true; - class[12] = 3; - piecemax[12] = 1 + d * 1 + d * d * 1; - piececount[0] = 13; - piececount[1] = 3; - piececount[2] = 1; - piececount[3] = 1; - m = 1 + d * (1 + d * 1); - kount = 0; - if (Fit (0, m)) - n = Place (0, m); - else - printf ("Error1 in Puzzle\n"); - if (!Trial (n)) - printf ("Error2 in Puzzle.\n"); - else if (kount != 2005) - printf ("Error3 in Puzzle.\n"); -}; - - - - /* Sorts an array using quicksort */ - -Initarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= sortelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; -}; - -Quicksort (a, l, r) - int a[], l, r; - /* quicksort the array A from start to finish */ -{ - int i, j, x, w; - - i = l; - j = r; - x = a[(l + r) / 2]; - do - { - while (a[i] < x) - i = i + 1; - while (x < a[j]) - j = j - 1; - if (i <= j) - { - w = a[i]; - a[i] = a[j]; - a[j] = w; - i = i + 1; - j = j - 1; - } - } - while (i <= j); - if (l < j) - Quicksort (a, l, j); - if (i < r) - Quicksort (a, i, r); -}; - - -Quick () -{ - Initarr (); - Quicksort (sortlist, 1, sortelements); - if ((sortlist[1] != littlest) || (sortlist[sortelements] != biggest)) - { - printf (" Error in Quick.\n"); - } - -}; - - - /* Sorts an array using treesort */ - -tInitarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= sortelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; - -}; - -CreateNode (t, n) - struct node **t; - int n; -{ - *t = (struct node *) malloc (sizeof (struct node)); - (*t)->left = nil; - (*t)->right = nil; - (*t)->val = n; -}; - -Insert (n, t) - int n; - struct node *t; - /* insert n into tree */ -{ - if (n > t->val) - if (t->left == nil) - CreateNode (&t->left, n); - else - Insert (n, t->left); - else if (n < t->val) - if (t->right == nil) - CreateNode (&t->right, n); - else - Insert (n, t->right); -}; - -int -Checktree (p) - struct node *p; - /* check by inorder traversal */ -{ - int result; - result = true; - if (p->left != nil) - if (p->left->val <= p->val) - result = false; - else - result = Checktree (p->left) && result; - if (p->right != nil) - if (p->right->val >= p->val) - result = false; - else - result = Checktree (p->right) && result; - return (result); -}; /* checktree */ - -Trees () -{ - int i; - tInitarr (); - tree = (struct node *) malloc (sizeof (struct node)); - tree->left = nil; - tree->right = nil; - tree->val = sortlist[1]; - for (i = 2; i <= sortelements; i++) - Insert (sortlist[i], tree); - if (!Checktree (tree)) - printf (" Error in Tree.\n"); -}; - - - /* Sorts an array using bubblesort */ - -bInitarr () -{ - int i, temp; - Initrand (); - biggest = 0; - littlest = 0; - for (i = 1; i <= srtelements; i++) - { - temp = Rand (); - sortlist[i] = temp - (temp / 100000) * 100000 - 50000; - if (sortlist[i] > biggest) - biggest = sortlist[i]; - else if (sortlist[i] < littlest) - littlest = sortlist[i]; - }; -}; - -Bubble () -{ - int i, j; - bInitarr (); - top = srtelements; - - while (top > 1) - { - - i = 1; - while (i < top) - { - - if (sortlist[i] > sortlist[i + 1]) - { - j = sortlist[i]; - sortlist[i] = sortlist[i + 1]; - sortlist[i + 1] = j; - }; - i = i + 1; - }; - - top = top - 1; - }; - if ((sortlist[1] != littlest) || (sortlist[srtelements] != biggest)) - printf ("Error3 in Bubble.\n"); -}; - - -float -Cos (x) - float x; -/* computes cos of x (x in radians) by an expansion */ -{ - int i, factor; - float result, power; - - result = 1.0; - factor = 1; - power = x; - for (i = 2; i <= 10; i++) - { - factor = factor * i; - power = power * x; - if ((i & 1) == 0) - { - if ((i & 3) == 0) - result = result + power / factor; - else - result = result - power / factor; - }; - }; - return (result); -}; - -int -Min0 (arg1, arg2) - int arg1, arg2; -{ - if (arg1 < arg2) - return (arg1); - else - return (arg2); -}; - -Printcomplex (arg1, arg2, zarray, start, finish, increment) - int arg1, arg2, start, finish, increment; - struct complex zarray[]; -{ - int i; - printf ("\n"); - - i = start; - do - { - printf (" %15.3e%15.3e", zarray[i].rp, zarray[i].ip); - i = i + increment; - printf (" %15.3e%15.3e", zarray[i].rp, zarray[i].ip); - printf ("\n"); - i = i + increment; - } - while (i <= finish); - -}; - -Uniform11 (iy, yfl) - int iy; - float yfl; -{ - iy = (4855 * iy + 1731) & 8191; - yfl = iy / 8192.0; -} /* uniform */ ; - -Exptab (n, e) - int n; - struct complex e[]; - -{ /* exptab */ - float theta, divisor, h[26]; - int i, j, k, l, m; - - theta = 3.1415926536; - divisor = 4.0; - for (i = 1; i <= 25; i++) - { - h[i] = 1 / (2 * Cos (theta / divisor)); - divisor = divisor + divisor; - }; - - m = n / 2; - l = m / 2; - j = 1; - e[1].rp = 1.0; - e[1].ip = 0.0; - e[l + 1].rp = 0.0; - e[l + 1].ip = 1.0; - e[m + 1].rp = -1.0; - e[m + 1].ip = 0.0; - - do - { - i = l / 2; - k = i; - - do - { - e[k + 1].rp = h[j] * (e[k + i + 1].rp + e[k - i + 1].rp); - e[k + 1].ip = h[j] * (e[k + i + 1].ip + e[k - i + 1].ip); - k = k + l; - } - while (k <= m); - - j = Min0 (j + 1, 25); - l = i; - } - while (l > 1); - -} /* exptab */ ; - -Fft (n, z, w, e, sqrinv) - int n; - struct complex z[], w[]; - struct complex e[]; - float sqrinv; -{ - int i, j, k, l, m, index; - m = n / 2; - l = 1; - - do - { - k = 0; - j = l; - i = 1; - - do - { - - do - { - w[i + k].rp = z[i].rp + z[m + i].rp; - w[i + k].ip = z[i].ip + z[m + i].ip; - w[i + j].rp = e[k + 1].rp * (z[i].rp - z[i + m].rp) - - e[k + 1].ip * (z[i].ip - z[i + m].ip); - w[i + j].ip = e[k + 1].rp * (z[i].ip - z[i + m].ip) - + e[k + 1].ip * (z[i].rp - z[i + m].rp); - i = i + 1; - } - while (i <= j); - - k = j; - j = k + l; - } - while (j <= m); - - /*z = w ; */ index = 1; - do - { - z[index] = w[index]; - index = index + 1; - } - while (index <= n); - l = l + l; - } - while (l <= m); - - for (i = 1; i <= n; i++) - { - z[i].rp = sqrinv * z[i].rp; - z[i].ip = -sqrinv * z[i].ip; - }; - -}; - -Oscar () -{ /* oscar */ - int i; - Exptab (fftsize, e); - seed = 5767; - for (i = 1; i <= fftsize; i++) - { - Uniform11 (seed, zr); - Uniform11 (seed, zi); - z[i].rp = 20.0 * zr - 10.0; - z[i].ip = 20.0 * zi - 10.0; - }; - - - for (i = 1; i <= 20; i++) - { - Fft (fftsize, z, w, e, 0.0625); -// Printcomplex( 6, 99, z, 1, 256, 17 ); - }; -} /* oscar */ ; - -main () -{ - int i; - fixed = 0.0; - floated = 0.0; - printf ("Starting \n"); -/* rewrite (output); */ - setbuf(stdout, nil); - printf (" Perm"); - timer = Getclock (); - Perm (); - xtimes[1] = Getclock () - timer; - fixed = fixed + permbase * xtimes[1]; - floated = floated + permbase * xtimes[1]; - printf (" Towers"); - timer = Getclock (); - Towers (); - xtimes[2] = Getclock () - timer; - fixed = fixed + towersbase * xtimes[2]; - floated = floated + towersbase * xtimes[2]; - printf (" Queens"); - timer = Getclock (); - Queens (); - xtimes[3] = Getclock () - timer; - fixed = fixed + queensbase * xtimes[3]; - floated = floated + queensbase * xtimes[3]; - printf (" Intmm"); - timer = Getclock (); - Intmm (); - xtimes[4] = Getclock () - timer; - fixed = fixed + intmmbase * xtimes[4]; - floated = floated + intmmbase * xtimes[4]; - printf (" Mm"); - timer = Getclock (); - Mm (); - xtimes[5] = Getclock () - timer; - fixed = fixed + mmbase * xtimes[5]; - floated = floated + fpmmbase * xtimes[5]; - printf (" Puzzle"); - timer = Getclock (); - Puzzle (); - xtimes[6] = Getclock () - timer; - fixed = fixed + puzzlebase * xtimes[6]; - floated = floated + puzzlebase * xtimes[6]; - printf (" Quick"); - timer = Getclock (); - Quick (); - xtimes[7] = Getclock () - timer; - fixed = fixed + quickbase * xtimes[7]; - floated = floated + quickbase * xtimes[7]; - printf (" Bubble"); - timer = Getclock (); - Bubble (); - xtimes[8] = Getclock () - timer; - fixed = fixed + bubblebase * xtimes[8]; - floated = floated + bubblebase * xtimes[8]; - printf (" Tree"); - timer = Getclock (); - Trees (); - xtimes[9] = Getclock () - timer; - fixed = fixed + treebase * xtimes[9]; - floated = floated + treebase * xtimes[9]; - printf (" FFT"); - timer = Getclock (); - Oscar (); - xtimes[10] = Getclock () - timer; - fixed = fixed + fftbase * xtimes[10]; - floated = floated + fpfftbase * xtimes[10]; - printf ("\n"); - for (i = 1; i <= 10; i++) - printf ("%8d", xtimes[i]); - printf ("\n"); - /* compute composites */ - printf ("\n"); - printf ("Nonfloating point composite is %10.0f\n", fixed / 10.0); - printf ("\n"); - printf ("Floating point composite is %10.0f\n", floated / 10.0); -} diff --git a/lib/CPUs/MIPS/bsp/examples/startup.S b/lib/CPUs/MIPS/bsp/examples/startup.S deleted file mode 100644 index 3ac6c1b..0000000 --- a/lib/CPUs/MIPS/bsp/examples/startup.S +++ /dev/null @@ -1,87 +0,0 @@ - .file "startup.S" - - .section .rodata - .data -argv0: .asciz "\"This-MIPS-program\"" -argv: .word argv0 - - .text - .section .start, "ax" - .extern _init - .extern dbg_init - .extern _exc_vect_start - .extern _xcpt_handler - .align 2 - .globl _start -_start: - .set noreorder - j init - nop - .set reorder - - .text - .set noreorder -init: - # Set stack pointer - la $sp, stack_ptr - # Set global pointer - la $gp, _gp - - # zero bss - la $8, __bss_start - la $9, _end -$zeroise: - sw $0, 0($8) - bne $8, $9, $zeroise - addiu $8, 4 - - # Install exception vector jump code - la $t1, _exc_vect_copy_start - la $t2, _exc_vect_copy_end - la $t0, _exc_vect_start - -$install: lw $v0, 0($t1) - addiu $t1, 4 - sw $v0, 0($t0) - bne $t1, $t2, $install - addiu $t0, 4 - - # Call _init - la $k0, _init - jalr $k0 - nop - - # Call dbg_init - la $k0, dbg_init - jalr $k0 - nop - - # Set user-mode - mfc0 $a0, $12 - li $a1, 3 - or $a0, $a1 - mtc0 $a0, $12 - - # Set environment - li $a0, 1 - la $a1, argv - - # Call main - la $k0, main - jalr $k0 - nop - - # Terminate after main returns -_terminate: - nop - la $t0, exit - jalr $t0 - move $a0, $v0 - -_exc_vect_copy_start: - la $k0, _xcpt_handler - jr $k0 - nop -_exc_vect_copy_end: - - .set reorder diff --git a/lib/CPUs/MIPS/bsp/examples/test_exception.c b/lib/CPUs/MIPS/bsp/examples/test_exception.c deleted file mode 100644 index f9e9354..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_exception.c +++ /dev/null @@ -1,277 +0,0 @@ -#include -#include -#include "libsys.h" - -void _exc_break(void) -{ - __asm - ( - ".set noreorder\n" - "break 0x9\n" - ".set reorder\n" - - ); -} - -void _exc_syscall(void) -{ - __asm - ( - ".set noreorder\n" - "syscall\n" - ".set reorder\n" - - ); -} - -void _exc_arith(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x7FFFFFFF\n" - " addi $t1, $t0, 2\n" - ".set reorder\n" - - ); -} - -void _exc_store_err(void) -{ - volatile int *pSrc = (int*)sys_timer_sec; - volatile int *pDst = (int*)0x40000001; - - *pDst = *pSrc; - -} - -void _exc_load_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000000\n" - " li $t1, 0x40000000\n" - " lw $t1, 0($t1)\n" - " lw $t0, 2($t0)\n" - " lw $t1, 4($t0)\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_kaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x80000000\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_iaddr_daddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " li $t1, 0x40000002\n" - " jr $t0\n" - " lw $t1, 0($t1)\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_daddr_iaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " li $t1, 0x40000002\n" - " lw $t1, 0($t1)\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_iaddr_err(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40000003\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_ri(void) -{ - __asm - ( - ".set noreorder\n" - " li $t0, 0x40010000\n" - " li $t1, 0x9c563442\n" - " sw $t1, 0($t0)\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_ibe(void) -{ - __asm - ( - ".set noreorder\n" - " li $t1, 0x10000000\n" - " jr $t1\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void _exc_dbe(void) -{ - __asm - ( - ".set noreorder\n" - " li $t1, 0x10000000\n" - " lw $t0, 0($t1)\n" - "nop\n" - " jr $t0\n" - "nop\n" - ".set reorder\n" - - ); - -} - -void handler0(void) -{ - printf("Interrupt 0\n"); - interrupt_clr(0); -} - -void handler1(void) -{ - printf("Interrupt 1\n"); - interrupt_clr(1); -} - -int main(void) -{ - int buf[256]; - int i, sel; - - interrupt_register(0, handler0); - interrupt_enable(0); - interrupt_register(1, handler1); - interrupt_enable(1); - - while(1) - { - printf("Welche exception möchten Sie testen?\n"); - printf(" 1 : Reserved instruction\n"); - printf(" 2 : Privileged address (BadVAddr = 0x80000000)\n"); - printf(" 3 : Arithmetic overflow\n"); - printf(" 4 : Syscall\n"); - printf(" 5 : Breakpoint\n"); - printf(" 6 : Load error on instruction (BadVAddr = 0x40000003)\n"); - printf(" 7 : Load error on data (BadVAddr = 0x40000002)\n"); - printf(" 8 : Store error on data (BadVAddr = 0x40000001)\n"); - printf(" 9 : Bus error on instruction\n"); - printf("10 : Bus error on data\n"); - printf("11 : SW-interrupt 0\n"); - printf("12 : SW-interrupt 1\n"); - printf("13 : Load error on instruction and Load error on data (BadVAddr = 0x40000003)\n"); - printf("14 : Load error on data and Load error on instruction (BadVAddr = 0x40000002)\n"); - - scanf("%d", &sel); - printf("Jetzt kommt die exception (%d)!\n", sel); - - switch(sel) - { - case 1: - _exc_ri(); - break; - - case 2: - _exc_kaddr_err(); - break; - - case 3: - _exc_arith(); - break; - - case 4: - _exc_syscall(); - break; - - case 5: - _exc_break(); - break; - - case 6: - _exc_iaddr_err(); - break; - - case 7: - _exc_load_err(); - break; - - case 8: - _exc_store_err(); - break; - - case 9: - printf("IBE: Exception not implemented in current CPU!\nPush reset to restart!\n"); - _exc_ibe(); - break; - - case 10: - printf("DBE: Exception not implemented in current CPU!\nPush reset to restart!\n"); - _exc_dbe(); - break; - - case 11: - case 12: - interrupt_set(sel-11); - break; - - case 13: - _exc_iaddr_daddr_err(); - break; - - case 14: - _exc_daddr_iaddr_err(); - break; - - default: - break; - } - sel = 0; - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_flash.c b/lib/CPUs/MIPS/bsp/examples/test_flash.c deleted file mode 100644 index 7d40961..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_flash.c +++ /dev/null @@ -1,94 +0,0 @@ -/************************************************************************/ -/* */ -/* AMD CFI Enabled Flash Memory Drivers */ -/* File name: CFIDRIVE.C */ -/* Revision: 1.0 5/07/98 */ -/* */ -/* Copyright (c) 1998 ADVANCED MICRO DEVICES, INC. All Rights Reserved. */ -/* This software is unpublished and contains the trade secrets and */ -/* confidential proprietary information of AMD. Unless otherwise */ -/* provided in the Software Agreement associated herewith, it is */ -/* licensed in confidence "AS IS" and is not to be reproduced in whole */ -/* or part by any means except for backup. Use, duplication, or */ -/* disclosure by the Government is subject to the restrictions in */ -/* paragraph (b) (3) (B) of the Rights in Technical Data and Computer */ -/* Software clause in DFAR 52.227-7013 (a) (Oct 1988). */ -/* Software owned by */ -/* Advanced Micro Devices, Inc., */ -/* One AMD Place, */ -/* P.O. Box 3453 */ -/* Sunnyvale, CA 94088-3453. */ -/************************************************************************/ -/* This software constitutes a basic shell of source code for */ -/* programming all AMD Flash components. AMD */ -/* will not be responsible for misuse or illegal use of this */ -/* software for devices not supported herein. AMD is providing */ -/* this source code "AS IS" and will not be responsible for */ -/* issues arising from incorrect user implementation of the */ -/* source code herein. It is the user's responsibility to */ -/* properly design-in this source code. */ -/* */ -/************************************************************************/ - -#include -#include -#include "cfiflash.h" -#include "libsys.h" - -#define TEST_SIZE (1024*1024) -#define FLASH_OFFSET 0x700000 -int main(void) -{ - int i; - flash_t flash; - UINT8 *pFlash = (UINT8*)0xA4000000; - UINT32 result; - UINT8 *pBuf; - - setbuf(stdout, NULL); - result = flash_find(&flash, 0xA4000000); - - if (result < 0) - { - printf("flash_find() error!\n"); - return 1; - } - - printf("Found Flash at %8.8X\n", (UINT32)flash.pBase); - - pBuf = (UINT8*)malloc(TEST_SIZE); - - for (i=0; i < TEST_SIZE; i++) - pBuf[i] = i; - - printf("Flash erase from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_erase(&flash, FLASH_OFFSET, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - - printf("Flash program from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_program(&flash, FLASH_OFFSET, pBuf, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - - printf("Flash verify from %8.8X to %8.8X...", FLASH_OFFSET, FLASH_OFFSET+TEST_SIZE); - result = flash_verify(&flash, FLASH_OFFSET, pBuf, TEST_SIZE); - if (result < 0) - { - printf("error!\n"); - return 1; - } - printf("OK\n"); - -// PrintBuffer8((UINT8*)pFlash, 16, TEST_SIZE); - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/test_irq.c b/lib/CPUs/MIPS/bsp/examples/test_irq.c deleted file mode 100644 index e5f5b35..0000000 --- a/lib/CPUs/MIPS/bsp/examples/test_irq.c +++ /dev/null @@ -1,154 +0,0 @@ -#include -#include -#include -#include "irq.h" - -#define CPU_FREQ_HZ 100000000 - -#include "libsys.h" - -char buffer[16384]; -char * volatile pPtr_r; -char * volatile pPtr_w; - -void handler0(void) -{ - printf("Interrupt 0\n"); - interrupt_clr(0); -} - -void handler1(void) -{ - printf("Interrupt 1\n"); - interrupt_clr(1); -} - -void handler2(void) -{ - printf("Interrupt 2\n"); -} - -void handler3(void) -{ - volatile UINT32 *pUART0_stat = (UINT32*)sys_uart0_stat; - volatile UINT32 *pUART0_data = (UINT32*)sys_uart0_data; - volatile UINT32 *pUART1_stat = (UINT32*)sys_uart1_stat; - volatile UINT32 *pUART1_data = (UINT32*)sys_uart1_data; - - while(0x200 & *pUART0_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[16383]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART0_data; - } - - while(0x200 & *pUART1_stat) - { -// sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - if (pPtr_w == &buffer[16383]) - pPtr_w = buffer; - *(pPtr_w++) = *pUART1_data; - } - -} - -void handler4(void) -{ - printf("Interrupt 4\n"); -} - -void handler5(void) -{ - printf("Interrupt 5\n"); -} - -void handler6(void) -{ - printf("Interrupt 6\n"); -} - -void handler7(void) -{ - printf("Interrupt 7\n"); -} - -int main(void) -{ - - volatile UINT32 *pUART0_stat = (UINT32*)sys_uart0_stat; - volatile UINT32 *pUART1_stat = (UINT32*)sys_uart1_stat; - volatile UINT32 *pUART0_baud = (UINT32*)sys_uart0_baud; - volatile UINT32 *pUART1_baud = (UINT32*)sys_uart1_baud; - - UART1_setbaud(460800); - printf("Hello\n"); - memset(buffer, 0, sizeof(buffer)); - pPtr_r = buffer; - pPtr_w = buffer; - interrupt_register(0, handler0); - interrupt_enable(0); - - interrupt_register(1, handler1); - interrupt_enable(1); - - interrupt_register(2, handler2); - interrupt_enable(2); - - printf("UART0 Status = 0x%8.8X\n", *pUART0_stat); - printf("UART0 Baud = 0x%8.8X\n", *pUART0_baud); - printf("UART1 Status = 0x%8.8X\n", *pUART1_stat); - printf("UART1 Baud = 0x%8.8X\n", *pUART1_baud); - - // enable RX interrupt - *pUART0_stat |= (1 << 6); - *pUART1_stat |= (1 << 6); - printf("UART0 Status = 0x%8.8X\n", *pUART0_stat); - printf("UART1 Status = 0x%8.8X\n", *pUART1_stat); - - interrupt_register(3, handler3); - interrupt_enable(3); - - interrupt_register(4, handler4); -// interrupt_enable(4); - - interrupt_register(5, handler5); - interrupt_enable(5); - - interrupt_register(6, handler6); - interrupt_enable(6); - - interrupt_register(7, handler7); - interrupt_enable(7); - - printf("Start:\n"); - - interrupt_set(0); - interrupt_set(1); - interrupt_set(2); - interrupt_set(3); - interrupt_set(4); - interrupt_set(5); - interrupt_set(6); - interrupt_set(7); - - sputs("r: "); print_word((int)pPtr_r); sputs("\n"); - sputs("w: "); print_word((int)pPtr_w); sputs("\n"); - - // Print Status register - sputs("Status : "); - print_word(CP0_SR_read()); - sputs("\n"); - - while(1) - { - if(pPtr_w != pPtr_r) - { -// sputs("r: "); print_word((int)pPtr_r); sputs("\n"); - if (pPtr_r == &buffer[16383]) - pPtr_r = buffer; - writechar(*(pPtr_r++)); - } - } - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/testbench.c b/lib/CPUs/MIPS/bsp/examples/testbench.c deleted file mode 100644 index 5f9bf76..0000000 --- a/lib/CPUs/MIPS/bsp/examples/testbench.c +++ /dev/null @@ -1,853 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "libsys.h" - -#define TEST10_ERROR (ERROR | 0x10) -#define TEST11_ERROR (ERROR | 0x11) -#define TEST12_ERROR (ERROR | 0x12) -#define TEST13_ERROR (ERROR | 0x13) -#define TEST14_ERROR (ERROR | 0x14) -#define TEST15_ERROR (ERROR | 0x15) - -char buffer[16384]; -int g_i; - -extern int paranoia(int argc, char **argv); - -void handler3(void) -{ - volatile UINT32 *pUART_stat = (UINT32*)sys_uart_stat; - volatile UINT32 *pUART_data = (UINT32*)sys_uart_data; - volatile UINT32 *pLED = (UINT32*)sys_led_port; - - while((0x10 & *pUART_stat)) - { - buffer[g_i] = (char)*pUART_data; - _cg_putchar(buffer[g_i]); - g_i = (g_i+1)%sizeof(buffer); - } - -} - -int g_cnt; -void handler7(void) -{ - UINT32 volatile *pGPIO0 = (UINT32*)sys_gpio0; - UINT32 volatile *pTim_stat = (UINT32*)sys_itim_stat; - UINT32 volatile *pTim_ctrl = (UINT32*)sys_itim_ctrl; - UINT32 volatile *pTim0_cmp = (UINT32*)sys_itim0_cmp; - time_t curr_date; - struct tm *pDate; - - if (*pTim0_cmp < 0x200) - { - *pTim0_cmp = 0x200; - } - if (*pTim_stat & 1) - { - *pTim_stat = 1; - *pGPIO0 = g_cnt++; - } - - if (*pTim_stat & 4) - { - *pTim_stat = 4; - curr_date = time(NULL); - pDate = gmtime(&curr_date); - fprintf(stderr, "%s", asctime(pDate)); - } - -} - -int fibonacci(int f0, int f1, int *pDst, int len) -{ - int i; - - i = 0; - - pDst[i++] = f0; - pDst[i++] = f1; - - for (; i < len; i++) - { - pDst[i] = pDst[i-2] + pDst[i-1]; - } - - return i; -} - -void PrintCPUinfo(void) -{ - int result, rev_id; - int cache_size, cache_line; - - char *cpu_type_str[7] = {"invalid", "R2000", "R3000", "R6000", "R4000", "reserved", "R6000A"}; - - // Print Status register - result = CP0_SR_read(); - - printf("--------------------------------------------------\n"); - printf("Status : %8.8X\n", result); - - // Print Revision - result = CP0_PRID_read(); - rev_id = (result >> 8) & 0xFF; - printf("CPU type : MIPS "); - if ((rev_id > 0) && (rev_id < 0x07)) - { - printf(cpu_type_str[rev_id]); - printf(" Rev. "); - rev_id = result & 0xFF; - printf("%d", rev_id); - } - else - printf("Unknown"); - - printf("\n"); - cache_size = (result >> 16) & 7; - cache_line = (result >> 19) & 7; - printf("I-Cache : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line))); - cache_size = (result >> 24) & 7; - cache_line = (result >> 27) & 7; - printf("D-Cache : %d kBytes (%d Bytes per line)\n", 4*(int)pow(2.0, (double)(8+cache_size))/1024, 4*(int)pow(2.0, (double)(cache_line))); - printf("--------------------------------------------------\n"); - -} - -int Test10_LoadStore() -{ - int *buf, i, result, data, err; - volatile int *pPtr; - - buf = (int*)malloc(32*sizeof(int)); -// sputs("buf = "); -// print_word((int)buf); -// sputs("\n"); - - while(1) - { - err = TEST10_ERROR; - // Basic Load/Store - pPtr = buf; - *pPtr++ = 0x00000000; - *pPtr++ = 0x55555555; - *pPtr++ = 0xAAAAAAAA; - *pPtr++ = 0xFFFFFFFF; - pPtr = buf; - if (*pPtr++ != 0x00000000) - break; - if (*pPtr++ != 0x55555555) - break; - if (*pPtr++ != 0xAAAAAAAA) - break; - if (*pPtr++ != 0xFFFFFFFF) - break; - - // Filling from left - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data >> 1 | 0x80000000; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data >> 1 | 0x80000000; - } - if (i != 32) - break; - - // Filling from right - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0x00000000; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - } - if (i != 32) - break; - - // Walking ones - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1; - - } - pPtr = buf; - data = 0x00000001; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1; - } - if (i != 32) - break; - - // Walking zeros - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - *pPtr++ = data; - data = data << 1 | 1; - - } - pPtr = buf; - data = 0xFFFFFFFE; - for (i=0; i < 32; i++) - { - - if (*pPtr++ != data) - break; - - data = data << 1 | 1; - - } - if (i != 32) - break; - - err = NO_ERROR; - break; - } - free(buf); - return err; - -} - - -#define NUM_ELEMENTS 10000 -#define NUM_RUNS 3 -int Test11_AddSub() -{ - int buf[NUM_ELEMENTS], result, i, j, diff, fill, num_right_elements, num_right_runs; - - fill = 0xAAAAAAAA; - - num_right_runs = 0; - - for (i=0; i < NUM_RUNS; i++) - { - for (j=0; j < NUM_ELEMENTS; j++) - { - buf[j] = fill; - fill = ((fill ^ j) - 1) << 1; - } - num_right_elements = 2; - result = fibonacci(i, i+1, buf, NUM_ELEMENTS); - for (j=2; j < NUM_ELEMENTS; j++) - { - diff = buf[j] - buf[j-1]; - if (diff == buf[j-2]) - num_right_elements++; - } - if (num_right_elements == NUM_ELEMENTS) - num_right_runs++; - - } - - if (num_right_runs != NUM_RUNS) - return TEST11_ERROR; - - return NO_ERROR; -} - -int Test12_MulDiv() -{ - int mix, i, j; - int s1, s2, sp, st; - div_t div_res; - long cl; - - cl = (long)clock(); - srand(cl); - for (i=0; i < 100; i++) - { - for (j=1; j < 100; j++) - { - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s1 = (int)rand() ^ mix; - mix = (int)rand(); - mix = (mix << 8) ^ (mix << 16); - s2 = (int)rand() ^ mix; - if (!s2) - { - fprintf(stderr, "Test12_MulDiv(): Division by zero!\n"); - fprintf(stderr, "Clock() was 0x%8.8X\n", cl); - continue; - } - - div_res = div(s1, s2); - - sp = s2*div_res.quot; - st = div_res.rem + sp; - if (st != s1) - return TEST12_ERROR; - } - } - return NO_ERROR; -} - -int Test13_COP0_Load_Store(void) -{ - int i,size; - UINT32 *pSrc32, *pDst32; - - size = 0x2000; - pSrc32 = (UINT32*)0xBFC00000; - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - CP0_TR_read_ptr(&pSrc32[i]); - CP0_TR_write_ptr(&pDst32[i]); - } - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pSrc32[i]) - break; - - free(pDst32); - i++; - if (i) - return TEST13_ERROR; - - return NO_ERROR; -} - -int Test14_DCACHE_invalidate(void) -{ - int i,size; - UINT32 *pSrc32, *pDst32; - - size = 0x2000; - pSrc32 = (UINT32*)0xBFC00000; - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - pDst32[i] = pSrc32[i]; - DCACHE_invalidate_at(&pDst32[i]); - } - for (i=size/4-1; i >= 0; i--) - { - DCACHE_invalidate_at(&pDst32[i]); - if (pDst32[i] != pSrc32[i]) - break; - } - - free(pDst32); - i++; - if (i) - return TEST14_ERROR; - - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - for (i=0; i < size/4; i++) - { - pDst32[i] = pSrc32[i]; - } - DCACHE_invalidate_all(); - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pSrc32[i]) - break; - - free(pDst32); - i++; - if (i) - return TEST14_ERROR; - - return NO_ERROR; -} - -#define PI_SCALE 10000 -#define PI_MAXARR 2800 -#define PI_ARRINIT 2000 - -int Test15_pi_calc() -{ - int i, j, k; - int carry = 0; - int arr[PI_MAXARR+1]; - UINT32 int_part, result; - UINT16 pi_res[200] = {0}; - UINT16 pi_ref[200] = - { - 3141,5926,5358,9793,2384,6264,3383,2795, 288,4197,1693,9937,5105,8209,7494,4592,3078,1640,6286,2089,9862,8034,8253,4211, - 7067,9821,4808,6513,2823, 664,7093,8446, 955, 582,2317,2535,9408,1284,8111,7450,2841, 270,1938,5211, 555,9644,6229,4895, - 4930,3819,6442,8810,9756,6593,3446,1284,7564,8233,7867,8316,5271,2019, 914,5648,5669,2346, 348,6104,5432,6648,2133,9360, - 7260,2491,4127,3724,5870, 660,6315,5881,7488,1520,9209,6282,9254, 917,1536,4367,8925,9036, 11,3305,3054,8820,4665,2138, - 4146,9519,4151,1609,4330,5727, 365,7595,9195,3092,1861,1738,1932,6117,9310,5118,5480,7446,2379,9627,4956,7351,8857,5272, - 4891,2279,3818,3011,9491,2983,3673,3624,4065,6643, 860,2139,4946,3952,2473,7190,7021,7986, 943,7027,7053,9217,1762,9317, - 6752,3846,7481,8467,6694, 513,2000,5681,2714,5263,5608,2778,5771,3427,5778,9609,1736,3717,8721,4684,4090,1224,9534,3014, - 6549,5853,7105, 792,2796,8925,8923,5420,1995,6112,1290,2196, 864, 344,1815,9813,6297,7477,1309,9605,1870,7211,3499,9999, - 8372,9780,4995,1059,7317,3281,6096,3185 - }; - - // setbuf(stdout, NULL); - k = 0; - for (i = 0; i <= PI_MAXARR; ++i) - arr[i] = PI_ARRINIT; - - for (i = PI_MAXARR; i; i -= 14) - { - int sum = 0; - for (j = i; j > 0; --j) - { - sum = sum*j + PI_SCALE*arr[j]; - arr[j] = sum % (j*2-1); - sum /= (j*2-1); - } - result = carry + sum/PI_SCALE; - int_part = PI_SCALE * (result / PI_SCALE); - pi_res[k] = (UINT16)(result - int_part); - carry = sum % PI_SCALE; - k++; - } - - for (k=0; k < sizeof(pi_ref)/sizeof(UINT16); k++) - { - printf("%d", pi_res[k]); - } - printf("\n"); - - if(memcmp(pi_res, pi_ref, sizeof(pi_ref))) - return TEST15_ERROR; - - return NO_ERROR; -} - -#define TEST_SIZE (16*1024*1024) // Bytes -#define SMALL_TEST_SIZE (8192) // Bytes -int main (void) -{ - int result, i, j, cnt, size; - UINT32 volatile *pUART_baud = (UINT32*)sys_uart_baud; - UINT32 volatile *pReg = (UINT32*)sys_led_port; - UINT32 volatile *pReg_usec = (UINT32*)sys_timer_usec; - UINT32 volatile *pReg_sec = (UINT32*)sys_timer_sec; - UINT32 volatile *pSSRAM = (UINT32*)sys_ssram_io; - UINT32 volatile *pTim_ctrl = (UINT32*)sys_itim_ctrl; - UINT32 volatile *pTim_stat = (UINT32*)sys_itim_stat; - UINT32 volatile *pTim0_cnt = (UINT32*)sys_itim0_cnt; - UINT32 volatile *pTim0_cmp = (UINT32*)sys_itim0_cmp; - UINT32 volatile *pTim1_cnt = (UINT32*)sys_itim1_cnt; - UINT32 volatile *pTim1_cmp = (UINT32*)sys_itim1_cmp; - - g_cnt = 1; - - srand(clock()); - - *pTim0_cnt = 0; - *pTim1_cnt = 0; - *pTim0_cmp = (UINT32)(rand() & 0x3FF); - *pTim1_cmp = 100000000; - *pTim_stat = (1 << 2) | (1 << 0); - *pTim_ctrl = (3 << 2); - - time_t curr_date; - struct tm *pDate, date; - UINT32 start, end; - char sel[80]; - struct timeval time_sec; - - UINT8 *ram8 = NULL; - UINT16 *ram16 = NULL; - UINT32 *ram32 = NULL; - - UINT32 *pSrc32, *pDst32; - -// *pUART_baud = 1; - - setbuf(stdout, NULL); - PrintCPUinfo(); - - g_i = 0; - memset(buffer, 0, sizeof(buffer)); - interrupt_register(3, handler3); - fprintf(stderr, "UART interrupt registered.\n"); - - interrupt_register(7, handler7); - fprintf(stderr, "Timer interrupt registered.\n"); - - // ---------------------------------------------------------- - // Memtest BEGIN -/* printf("SSRAM Memory Test\r\n"); - printf("Small data test\r\n"); - printf("Write (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=0; i < SMALL_TEST_SIZE/4; i++) - pSSRAM[i] = (UINT32)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - PrintBuffer8((UINT8*)pSSRAM, 16, 256); - - printf("Verify (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--) - if (pSSRAM[i] != (UINT32)i) - break; - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); -*/ - // ---------------------------------------------------------- - // Memtest BEGIN - printf("SDRAM Memory Test\n"); - printf("Test size %d kByte\n\n", TEST_SIZE/1024); - - ram8 = (UINT8*)calloc(TEST_SIZE,sizeof(UINT8)); - printf("Zeroize Memory (memset)..."); - start = clock(); - memset(ram8, 0, TEST_SIZE); - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram8); - - ram8 = (UINT8*)calloc(TEST_SIZE,sizeof(UINT8)); - printf("Zeroize Memory (8-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE; i++) - ram8[i] = (UINT8)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram8); - - ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16)); - printf("Zeroize Memory (16-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram16); - - ram32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32)); - printf("Zeroize Memory (32-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/4; i++) - ram32[i] = (UINT32)0; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram32); - - ram8 = (UINT8*)calloc(TEST_SIZE,sizeof(UINT8)); - printf("Write (8-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE; i++) - ram8[i] = (UINT8)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - printf("Verify (8-Bit access)..."); - start = clock(); - for (i=TEST_SIZE-1; i >= 0; i--) - if (ram8[i] != (UINT8)i) - break; - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram8); - - ram16 = (UINT16*)calloc(TEST_SIZE/2,sizeof(UINT16)); - printf("Write (16-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/2; i++) - ram16[i] = (UINT16)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - printf("Verify (16-Bit access)..."); - start = clock(); - for (i=TEST_SIZE/2-1; i >= 0; i--) - if (ram16[i] != (UINT16)i) - break; - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - - free(ram16); - - ram32 = (UINT32*)calloc(TEST_SIZE/4,sizeof(UINT32)); - printf("Write (32-Bit access)..."); - start = clock(); - for (i=0; i < TEST_SIZE/4; i++) - { - ram32[i] = (UINT32)i; - } - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - printf("Verify (32-Bit access)..."); - start = clock(); - for (i=TEST_SIZE/4-1; i >= 0; i--) - { - if (ram32[i] != (UINT32)i) - break; - } - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - free(ram32); - - printf("Small data test\r\n"); - printf("Test size %d kByte\n\n", SMALL_TEST_SIZE/1024); - printf("Write (32-Bit access)..."); - ram32 = (UINT32*)calloc(SMALL_TEST_SIZE/4,sizeof(UINT32)); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=0; i < SMALL_TEST_SIZE/4; i++) - ram32[i] = (UINT32)i; - - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - // ------------------------------------------------------------------- - // Verify - printf("Verify (32-Bit access)..."); - start = clock(); - for (j=0; j < TEST_SIZE/SMALL_TEST_SIZE; j++) - for (i=SMALL_TEST_SIZE/4-1; i >= 0; i--) - if (ram32[i] != (UINT32)i) - break; - - end = clock(); - i++; - if (i) - printf("failed\r\n"); - else - printf("passed (%.2f MByte/s)\n", (double)TEST_SIZE/(1000*(end-start))); - - // ------------------------------------------------------------------- - - free(ram32); - - printf("Memcpy() Test \n"); - pSrc32 = (UINT32*)calloc(TEST_SIZE/8,sizeof(UINT32)); - pDst32 = (UINT32*)calloc(TEST_SIZE/8,sizeof(UINT32)); - printf("Copying %d kBytes...", TEST_SIZE/(2*1024)); - start = clock(); - memcpy(pDst32, pSrc32, TEST_SIZE/2); - end = clock(); - printf("done (%.2f MByte/s)\n", (double)TEST_SIZE/(2*1000*(end-start))); - - free(pSrc32); - free(pDst32); - - printf("Boot code read \n"); - size = 0x2000; - pSrc32 = (UINT32*)0xBFC00000; - pDst32 = (UINT32*)calloc(size,sizeof(UINT32)); - memcpy(pDst32, pSrc32, size); - printf("Verify Boot code..."); - for (i=size/4-1; i >= 0; i--) - if (pDst32[i] != pSrc32[i]) - break; - i++; - if (i) - printf("failed\r\n"); - else - printf("passed\r\n"); - - free(pDst32); - - memdump((UINT8*)pSrc32, 0, 16, size); - memdump((UINT8*)0x40000000, 0, 16, 1024); - - // Memtest END - // ---------------------------------------------------------- - sputs("\r\n"); - - printf("Aktuelles Datum\n"); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - printf("Datum und Uhrzeit setzen? [j/N]: "); - scanf("%s", sel); - if (toupper(sel[0]) == 'J') - { - do - { - printf("Datum\n"); - printf("Jahr : "); - scanf("%d", &date.tm_year); - printf("Monat : "); - scanf("%d", &date.tm_mon); - printf("Tag : "); - scanf("%d", &date.tm_mday); - - printf("Uhrzeit\n"); - printf("Stunde : "); - scanf("%d", &date.tm_hour); - printf("Minute : "); - scanf("%d", &date.tm_min); - printf("Sekunde : "); - scanf("%d", &date.tm_sec); - - date.tm_year -= 1900; - date.tm_mon -= 1; - time_sec.tv_sec = mktime(&date); - time_sec.tv_usec = 0; - settimeofday(&time_sec, NULL); - - printf("Datum\n"); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - printf("\nOK? [J/n]: "); - scanf("%s", sel); - printf("sel=%d\n", (int)sel[0]); - - - } while(toupper(sel[0]) == 'N'); - } - - interrupt_enable(7); - interrupt_enable(3); - *pTim_ctrl |= 3; - - cnt = 0; - while (1) - { - for (i=0; i < 100000; i++) - { - interrupt_disable(7); - } - for (i=0; i < 100000; i++) - { - interrupt_enable(7); - } - - *pReg = cnt & 0x3FFFFFFF; - - printf("-------------------------------------------\n"); - printf("-- LoadStore ------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test10_LoadStore(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- AddSub ---------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test11_AddSub(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- MulDiv ---------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test12_MulDiv(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- Cop0 LWZ0 and SWC0 ---------------------\n"); - printf("-------------------------------------------\n"); - result = Test13_COP0_Load_Store(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- D-Cache invalidate ---------------------\n"); - printf("-------------------------------------------\n"); - result = Test14_DCACHE_invalidate(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- PI calc --------------------------------\n"); - printf("-------------------------------------------\n"); - result = Test15_pi_calc(); - if (IS_ERROR(result)) - break; - printf("passed\n\n"); - - printf("-------------------------------------------\n"); - printf("-- Paranoia -------------------------------\n"); - printf("-------------------------------------------\n"); - paranoia(1, NULL); - printf("passed\n\n"); - - printf("Iteration %d: Passed\n", cnt); - curr_date = time(NULL); - pDate = gmtime(&curr_date); - puts(asctime(pDate)); - cnt++; - *pTim0_cmp = (UINT32)(rand() & 0x3FF); - *pTim_ctrl |= 1; - -// printf("V=%.17e\n", pow((double)cnt-1, (double)cnt)); - } - *pReg = 0x40000000 | cnt; - fprintf(stderr, "Failed with error %8.8X\n", result); - - return 1; - -} - diff --git a/lib/CPUs/MIPS/bsp/examples/whet.c b/lib/CPUs/MIPS/bsp/examples/whet.c deleted file mode 100644 index d939910..0000000 --- a/lib/CPUs/MIPS/bsp/examples/whet.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * @(#)whet.c 1.1 - */ - -/* - * Whetstone benchmark in C. This program is a translation of the - * original Algol version in "A Synthetic Benchmark" by H.J. Curnow - * and B.A. Wichman in Computer Journal, Vol 19 #1, February 1976. - * - * Used to test compiler optimization and floating point performance. - */ - -/* - * Compile with -DMEASURE_TIME for time measurement. - * - * Compile with -DPOUT to print intermediate results. - * Running this benchmark without printing the intermediate results is - * contrary to the authors' intentions! But using serial I/O can draw back - * the performance extremely when low baud rate communication is used. - */ -#define MEASURE_TIME 1 -//#define POUT 1 - -#define ITERATIONS 10 /* 10 Million Whetstone instructions */ - -#include -#include - -#ifdef MEASURE_TIME -#include -unsigned long Begin_Time,End_Time,Total_Time; -double whetstones; -#endif - -#define Pout(n, j, k, x1, x2, x3, x4) pout(n, j, k, x1, x2, x3, x4); - -double xx1, xx2, xx3, xx4, x, y, z, t, t1, t2; -double e1[4]; -unsigned int i, j, k, l, n1, n2, n3, n4, n6, n7, n8, n9, n10, n11; - -main() -{ - printf("\nWhetstone Benchmark\n\n"); - - printf( "%d iterations\n", ITERATIONS ); - -#ifdef MEASURE_TIME - Begin_Time = clock(); -#endif - - /* initialize constants */ - - t = 0.499975; - t1 = 0.50025; - t2 = 2.0; - - /* set values of module weights */ - - n1 = 0 * ITERATIONS; - n2 = 12 * ITERATIONS; - n3 = 14 * ITERATIONS; - n4 = 345 * ITERATIONS; - n6 = 210 * ITERATIONS; - n7 = 32 * ITERATIONS; - n8 = 899 * ITERATIONS; - n9 = 616 * ITERATIONS; - n10 = 0 * ITERATIONS; - n11 = 93 * ITERATIONS; - -/* MODULE 1: simple identifiers */ - - xx1 = 1.0; - xx2 = xx3 = xx4 = -1.0; - - for(i = 1; i <= n1; i += 1) { - xx1 = ( xx1 + xx2 + xx3 - xx4 ) * t; - xx2 = ( xx1 + xx2 - xx3 + xx4 ) * t; - xx3 = ( xx1 - xx2 + xx3 + xx4 ) * t; - xx4 = (-xx1 + xx2 + xx3 + xx4 ) * t; - } -#ifdef POUT - Pout(n1, n1, n1, xx1, xx2, xx3, xx4); -#endif - - -/* MODULE 2: array elements */ - - e1[0] = 1.0; - e1[1] = e1[2] = e1[3] = -1.0; - - for (i = 1; i <= n2; i +=1) { - e1[0] = ( e1[0] + e1[1] + e1[2] - e1[3] ) * t; - e1[1] = ( e1[0] + e1[1] - e1[2] + e1[3] ) * t; - e1[2] = ( e1[0] - e1[1] + e1[2] + e1[3] ) * t; - e1[3] = (-e1[0] + e1[1] + e1[2] + e1[3] ) * t; - } -#ifdef POUT - Pout(n2, n3, n2, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 3: array as parameter */ - - for (i = 1; i <= n3; i += 1) - pa(e1); -#ifdef POUT - Pout(n3, n2, n2, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 4: conditional jumps */ - - j = 1; - for (i = 1; i <= n4; i += 1) { - if (j == 1) - j = 2; - else - j = 3; - - if (j > 2) - j = 0; - else - j = 1; - - if (j < 1 ) - j = 1; - else - j = 0; - } -#ifdef POUT - Pout(n4, j, j, xx1, xx2, xx3, xx4); -#endif - -/* MODULE 5: omitted */ - -/* MODULE 6: integer arithmetic */ - - j = 1; - k = 2; - l = 3; - - for (i = 1; i <= n6; i += 1) { - j = j * (k - j) * (l -k); - k = l * k - (l - j) * k; - l = (l - k) * (k + j); - - e1[l - 2] = j + k + l; /* C arrays are zero based */ - e1[k - 2] = j * k * l; - } -#ifdef POUT - Pout(n6, j, k, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE 7: trig. functions */ - - x = y = 0.5; - - for(i = 1; i <= n7; i +=1) { - x = t * atan(t2*sin(x)*cos(x)/(cos(x+y)+cos(x-y)-1.0)); - y = t * atan(t2*sin(y)*cos(y)/(cos(x+y)+cos(x-y)-1.0)); - } -#ifdef POUT - Pout(n7, j, k, x, x, y, y); -#endif - -/* MODULE 8: procedure calls */ - - x = y = z = 1.0; - - for (i = 1; i <= n8; i +=1) - p3(x, y, &z); -#ifdef POUT - Pout(n8, j, k, x, y, z, z); -#endif - -/* MODULE9: array references */ - - j = 1; - k = 2; - l = 3; - - e1[0] = 1.0; - e1[1] = 2.0; - e1[2] = 3.0; - - for(i = 1; i <= n9; i += 1) - p0(); -#ifdef POUT - Pout(n9, j, k, e1[0], e1[1], e1[2], e1[3]); -#endif - -/* MODULE10: integer arithmetic */ - - j = 2; - k = 3; - - for(i = 1; i <= n10; i +=1) { - j = j + k; - k = j + k; - j = k - j; - k = k - j - j; - } -#ifdef POUT - Pout(n10, j, k, xx1, xx2, xx3, xx4); -#endif - -/* MODULE11: standard functions */ - - x = 0.75; - for(i = 1; i <= n11; i +=1) - x = sqrt( exp( log(x) / t1)); - -#ifdef POUT - Pout(n11, j, k, x, x, x, x); -#endif - -#ifdef MEASURE_TIME - End_Time = clock(); - - Total_Time = End_Time - Begin_Time; /* in 1/ seconds */ - - whetstones = (1e5 * ITERATIONS * CLOCKS_PER_SEC) / Total_Time; - printf("\nWhetstone runs in %ld clock ticks (%d). %ld Kwhets/second\n", - Total_Time, CLOCKS_PER_SEC, (long) whetstones / 1000 ); -#endif -} - -pa(e) -double e[4]; -{ - register int j; - - j = 0; - lab: - e[0] = ( e[0] + e[1] + e[2] - e[3] ) * t; - e[1] = ( e[0] + e[1] - e[2] + e[3] ) * t; - e[2] = ( e[0] - e[1] + e[2] + e[3] ) * t; - e[3] = ( -e[0] + e[1] + e[2] + e[3] ) / t2; - j += 1; - if (j < 6) - goto lab; -} - -p3(x, y, z) -double x, y, *z; -{ - x = t * (x + y); - y = t * (x + y); - *z = (x + y) /t2; -} - -p0() -{ - e1[j] = e1[k]; - e1[k] = e1[l]; - e1[l] = e1[j]; -} - -#ifdef POUT -pout(n, j, k, x1, x2, x3, x4) -unsigned int n, j, k; -double x1, x2, x3, x4; -{ - printf("%5u %5u %5u %11.3e %11.3e %11.3e %11.3e\n", - n, j, k, x1, x2, x3, x4); -} -#endif diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.c b/lib/CPUs/MIPS/bsp/examples/xcpt.c deleted file mode 100644 index a6eca43..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt.c +++ /dev/null @@ -1,139 +0,0 @@ -#include -#include -#include -#include -#include -#include "libsys.h" -#include "xcpt.h" -#include "irq.h" - -static fp_xcpt_t g_xcpt_handler[MAX_NUM_XCPT] = {NULL}; - -char *_xcpt_code_str[MAX_NUM_XCPT] = -{ - "Int", "Mod", "TLBL", "TLBS", "AdEL", "AdES", "IBE", "DBE", - "Sys", "Bp", "RI", "CpU", "Ov", "Tr", "NCD/VCEI", "MC/FPE", - "Res(16)", "Res(17)", "Res(18)", "Res(19)", "Res(20)", "Res(21)", "Res(22)", "WATCH", - "Res(24)", "Res(25)", "Res(26)", "Res(27)", "Res(28)", "Res(29)", "Res(30)", "VCED" - }; - -void xcpt_register(int xcpt_num, fp_xcpt_t fp) -{ - if ((xcpt_num >= Mod) && (xcpt_num <= VCED)) - g_xcpt_handler[xcpt_num] = fp; - -} - -int _xcpt_dispatch(struct xcptcontext * xcp) -{ - int xcpt_code, result, i; - - xcpt_code = ((0xFF & xcp->cr) >> 2); - - result = XCPT_ERR_NOTHANDLED; - switch(xcpt_code) - { - case Int: - result = _irq_dispatch(xcp); - break; - - default: - if (g_xcpt_handler[xcpt_code]) - { - result = (g_xcpt_handler[xcpt_code])(xcp); - } - break; - } - return result; -} - -int _xcpt_deliver(struct xcptcontext * _xcp) -{ - - int exc_code; - volatile int *pInstr; - - /* This function gets called by the low-level exception handler. */ - if (_xcpt_dispatch(_xcp) == XCPT_ERR_NOTHANDLED) - { - sputs("\n"); - PRINT_REG(" Status : ", _xcp->sr); - PRINT_REG(" Cause : ", _xcp->cr); - PRINT_REG(" EPC : ", _xcp->epc); - PRINT_REG("BadAddr : ", _xcp->baddr); - sputs("\n"); - PRINT_REG(" MDLO : ", _xcp->mdlo); - PRINT_REG(" MDHI : ", _xcp->mdhi); - - sputs("\n"); - - sputs("Registers:\n"); - PRINT_REG(" 0 (ze) : ", _xcp->regs[0]); - PRINT_REG(" 1 (at) : ", _xcp->regs[1]); - PRINT_REG(" 2 (v0) : ", _xcp->regs[2]); - PRINT_REG(" 3 (v1) : ", _xcp->regs[3]); - sputs("\n"); - PRINT_REG(" 4 (a0) : ", _xcp->regs[4]); - PRINT_REG(" 5 (a1) : ", _xcp->regs[5]); - PRINT_REG(" 6 (a2) : ", _xcp->regs[6]); - PRINT_REG(" 7 (a3) : ", _xcp->regs[7]); - sputs("\n"); - PRINT_REG(" 8 (t0) : ", _xcp->regs[8]); - PRINT_REG(" 9 (t1) : ", _xcp->regs[9]); - PRINT_REG("10 (t2) : ", _xcp->regs[10]); - PRINT_REG("11 (t3) : ", _xcp->regs[11]); - sputs("\n"); - PRINT_REG("12 (t4) : ", _xcp->regs[12]); - PRINT_REG("13 (t5) : ", _xcp->regs[13]); - PRINT_REG("14 (t6) : ", _xcp->regs[14]); - PRINT_REG("15 (t7) : ", _xcp->regs[15]); - sputs("\n"); - PRINT_REG("16 (s0) : ", _xcp->regs[16]); - PRINT_REG("17 (s1) : ", _xcp->regs[17]); - PRINT_REG("18 (s2) : ", _xcp->regs[18]); - PRINT_REG("19 (s3) : ", _xcp->regs[19]); - sputs("\n"); - PRINT_REG("20 (s4) : ", _xcp->regs[20]); - PRINT_REG("21 (s5) : ", _xcp->regs[21]); - PRINT_REG("22 (s6) : ", _xcp->regs[22]); - PRINT_REG("23 (s7) : ", _xcp->regs[23]); - sputs("\n"); - PRINT_REG("24 (t8) : ", _xcp->regs[24]); - PRINT_REG("25 (t9) : ", _xcp->regs[25]); - PRINT_REG("26 (k0) : ", _xcp->regs[26]); - PRINT_REG("27 (k1) : ", _xcp->regs[27]); - sputs("\n"); - PRINT_REG("28 (gp) : ", _xcp->regs[28]); - PRINT_REG("29 (sp) : ", _xcp->regs[29]); - PRINT_REG("30 (fp) : ", _xcp->regs[30]); - PRINT_REG("31 (ra) : ", _xcp->regs[31]); - sputs("\n"); - sputs("\n"); - - exc_code = (_xcp->cr >> 2) & 0x1F; - - sputs("Unhandled exception <"); - sputs(_xcpt_code_str[exc_code]); - sputs("> at PC : "); - - if (_xcp->cr & 0x80000000) - { - pInstr = (int*)(_xcp->epc + 4); - } - else - { - pInstr = (int*)(_xcp->epc); - } - print_word((int)pInstr); - sputs("\n"); - - sputs("Instruction at exception address : "); - print_word(*pInstr); - sputs("\n"); - - sputs("Terminate.\n"); - _exit(exc_code); - } - - return 0; -} diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt.h b/lib/CPUs/MIPS/bsp/examples/xcpt.h deleted file mode 100644 index 7ffde6e..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef XCPT_H -#define XCPT_H - -#define MAX_NUM_XCPT 32 -#define XCPT_ERR_NOTHANDLED 0x80000000 - -typedef enum -{ - Int = 0, Mod = 1, TLBL = 2, TLBS = 3, AdEL = 4, AdES = 5, - IBE = 6, DBE = 7, Syscall = 8, Bp = 9, RI = 10, CpU = 11, - Ov = 12, TRAP = 13, VCEI = 14, FPE = 15, C2E = 16, Watch = 23, VCED = 31 - -} EXCEPTION_CODE; - -typedef unsigned int reg_t; - -typedef struct xcptcontext -{ - /* This is the exception context frame that is passed to the exception - handlers. It gets filled in by the low-level exception handler in - "machine.S". An assembler version of this structure can be found at the - bottom of "machine.H".*/ - reg_t sr; /* Status Register */ - reg_t cr; /* Cause Register */ - reg_t epc; /* PC at time of exception. */ - reg_t baddr; - reg_t regs[32]; /* Copy of all general purpose registers */ - reg_t mdlo; /* HI/LO registers (used for memory management) */ - reg_t mdhi; - reg_t count; /* Timer registers */ - reg_t compare; - struct xcptcontext * prev; /* To link exceptions. (unused for now) */ - unsigned xclass; /* Priority class of this exception. (unused for now). */ - -} EXCEPTION_CONTEXT; - -typedef int (*fp_xcpt_t)(struct xcptcontext * xcp); - -#define PRINT_REG(tag_str, reg) \ - sputs(tag_str); \ - print_word(reg); \ - sputs(" "); - - - -// Public functions -void xcpt_register(int xcpt_num, fp_xcpt_t fp); - -#endif // XCPT_H diff --git a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h b/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h deleted file mode 100644 index 5735422..0000000 --- a/lib/CPUs/MIPS/bsp/examples/xcpt_asm.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef XCPT_ASM_H -#define XCPT_ASM_H - -/* LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol, @function; \ - .ent symbol, 0; \ -symbol: .frame sp, 0, ra - -/* END - mark end of function */ -#define END(function) \ - .end function; \ - .size function, .-function - -/* Exception stack size */ -#define XCP_SIZE 32768 - -/* save location for registers */ -#define XCP_SR 0 -#define XCP_CR 4 -#define XCP_EPC 8 -#define XCP_BADDR 12 -#define XCP_ZERO 16 -#define XCP_AT 20 -#define XCP_V0 24 -#define XCP_V1 28 -#define XCP_A0 32 -#define XCP_A1 36 -#define XCP_A2 40 -#define XCP_A3 44 -#define XCP_T0 48 -#define XCP_T1 52 -#define XCP_T2 56 -#define XCP_T3 60 -#define XCP_T4 64 -#define XCP_T5 68 -#define XCP_T6 72 -#define XCP_T7 76 -#define XCP_S0 80 -#define XCP_S1 84 -#define XCP_S2 88 -#define XCP_S3 92 -#define XCP_S4 96 -#define XCP_S5 100 -#define XCP_S6 104 -#define XCP_S7 108 -#define XCP_T8 112 -#define XCP_T9 116 -#define XCP_JP 116 -#define XCP_K0 120 -#define XCP_K1 124 -#define XCP_GP 128 -#define XCP_SP 132 -#define XCP_S8 136 -#define XCP_FP 136 -#define XCP_RA 140 -#define XCP_MDLO 144 -#define XCP_MDHI 148 -#define XCP_COUNT 152 -#define XCP_COMPARE 156 -#define XCP_PREV 160 -#define XCP_CLASS 164 - - -#endif /* XCPT_ASM_H */ diff --git a/lib/CPUs/MIPS/bsp/toolchain/howto_build.txt b/lib/CPUs/MIPS/bsp/toolchain/howto_build.txt deleted file mode 100644 index 270be3b..0000000 --- a/lib/CPUs/MIPS/bsp/toolchain/howto_build.txt +++ /dev/null @@ -1,46 +0,0 @@ -# --------------------------------------------------------------- -# 1. Binutils bauen und installieren -# --------------------------------------------------------------- -> tar -xzf binutils-2.19.tar.gz -> mkdir binutils-2.19_build -> cd binutils-2.19_build - -> ../binutils-2.19/configure --target=mipsel-elf --prefix=/usr/local -> make -> make install - -# --------------------------------------------------------------- -# 2. GCC bootstrapping -# --------------------------------------------------------------- -> tar -xzf gcc-4.3.2.tar.gz -> mkdir gcc-4.3.2_build -> cd gcc-4.3.2_build -> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --without-headers --with-newlib --with-float=soft --disable-multilib -> CFLAGS_FOR_TARGET="-mno-gpopt" make all-gcc -> make info-gcc -> make install-gcc - -# --------------------------------------------------------------- -# 3. Newlib bauen und installieren -# --------------------------------------------------------------- -> tar -xzf newlib-1.16.0.tar.gz -! Bug in newlib-1.16.0/newlib/libc/machine/mips/strlen.c. - Newlib von Hand patchen (32-bit MIPS targets): - "lbu $3,0($4)\n" - "nop\n" <= nop einfügen - "bnez $3,1b\n" - -> mkdir newlib-1.16.0_build -> cd newlib-1.16.0_build -> ../newlib-1.16.0/configure --target=mipsel-elf --prefix=/usr/local --with-float=soft --disable-multilib -> TARGET_CFLAGS="-mno-gpopt" make all -> make install - -# --------------------------------------------------------------- -# 4. GCC bauen und installieren -# --------------------------------------------------------------- -> cd gcc-4.3.2_build -> ../gcc-4.3.2/configure --target=mipsel-elf --prefix=/usr/local --enable-languages="c,c++" --disable-shared --with-newlib --with-float=soft --disable-multilib -> CFLAGS_FOR_TARGET="-mno-gpopt" make all -> make info -> make install diff --git a/lib/CPUs/MIPS/bsp/toolchain/make.sh b/lib/CPUs/MIPS/bsp/toolchain/make.sh deleted file mode 100644 index 1568da9..0000000 --- a/lib/CPUs/MIPS/bsp/toolchain/make.sh +++ /dev/null @@ -1,151 +0,0 @@ -#!/bin/sh -TARGET=mipsel-elf -PREFIX=/usr/local - -SRC_BINUTILS=binutils-2.19 -SRC_GCC=gcc-4.3.3 -SRC_NEWLIB=newlib-1.16.0 -SRC_GMP=gmp-4.2.4 -SRC_MPFR=mpfr-2.4.0 - -# --------------------------------------------------------------- -# 1. Binutils bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_BINUTILS.tar.bz2 ]; then - echo Downloading $SRC_BINUTILS - wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/binutils/$SRC_BINUTILS.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_BINUTILS -fi - -if [ ! -e ./$SRC_BINUTILS ]; then - echo Unpacking $SRC_BINUTILS - tar -xjf $SRC_BINUTILS.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_BINUTILS -fi - -if [ ! -e ./$SRC_BINUTILS-build ]; then - echo Building $SRC_BINUTILS - mkdir -p $SRC_BINUTILS-build - cd $SRC_BINUTILS-build - ../$SRC_BINUTILS/configure --target=$TARGET --prefix=$PREFIX || exit 1 - make || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_BINUTILS is already built. -fi - -# --------------------------------------------------------------- -# 2. GMP bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_GMP.tar.bz2 ]; then - echo Downloading $SRC_GMP - wget http://ftp.sunet.se/pub/gnu/gmp/$SRC_GMP.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_GMP -fi - -if [ ! -e ./$SRC_GMP ]; then - echo Unpacking $SRC_GMP - tar -xjf $SRC_GMP.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_GMP -fi - -if [ ! -e ./$SRC_GMP-build ]; then - echo Building $SRC_GMP - mkdir -p $SRC_GMP-build - cd $SRC_GMP-build - ../$SRC_GMP/configure --prefix=$PREFIX || exit 1 - make || exit 1 - make check || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_GMP is already built. -fi - -# --------------------------------------------------------------- -# 3. MPFR bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_MPFR.tar.bz2 ]; then - echo Downloading $SRC_MPFR - wget http://www.mpfr.org/mpfr-current/$SRC_MPFR.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_MPFR -fi - -if [ ! -e ./$SRC_MPFR ]; then - echo Unpacking $SRC_MPFR - tar -xjf $SRC_MPFR.tar.bz2 || exit 1 -else - echo Skipped unpacking $SRC_MPFR -fi - -if [ ! -e ./$SRC_MPFR-build ]; then - echo Building $SRC_MPFR - mkdir -p $SRC_MPFR-build - cd $SRC_MPFR-build - ../$SRC_MPFR/configure --prefix=$PREFIX || exit 1 - make || exit 1 - make check || exit 1 - make install || exit 1 - cd .. -else - echo $SRC_MPFR is already built. -fi - -# --------------------------------------------------------------- -# 4. GCC & newlib bauen und installieren -# --------------------------------------------------------------- -if [ ! -e $SRC_NEWLIB.tar.gz ]; then - echo Downloading $SRC_NEWLIB - wget ftp://sources.redhat.com/pub/newlib/$SRC_NEWLIB.tar.gz || exit 1 -else - echo Skipped downloading $SRC_NEWLIB -fi - -if [ ! -e ./$SRC_NEWLIB ]; then - echo Unpacking $SRC_NEWLIB - tar -xzf $SRC_NEWLIB.tar.gz || exit 1 - if [ -e $SRC_NEWLIB-jens.patch ]; then - echo Patching $SRC_NEWLIB - patch -p0 < $SRC_NEWLIB-jens.patch || exit 1 - fi -else - echo Skipped unpacking $SRC_NEWLIB -fi - -if [ ! -e $SRC_GCC.tar.bz2 ]; then - echo Downloading $SRC_GCC - wget ftp://ftp-stud.fht-esslingen.de/pub/Mirrors/ftp.gnu.org/gcc/$SRC_GCC/$SRC_GCC.tar.bz2 || exit 1 -else - echo Skipped downloading $SRC_GCC -fi - -if [ ! -e ./$SRC_GCC ]; then - echo Unpacking $SRC_GCC - tar -xjf $SRC_GCC.tar.bz2 || exit 1 - cd ./$SRC_GCC - ln -sf ../$SRC_NEWLIB/newlib/ . - cd .. -else - echo Skipped unpacking $SRC_GCC -fi - -if [ ! -e ./$SRC_GCC-build ]; then - echo Building $SRC_GCC - mkdir -p $SRC_GCC-build - cd $SRC_GCC-build - ../$SRC_GCC/configure --target=$TARGET --prefix=$PREFIX --with-float=soft --with-newlib --verbose --enable-languages="c,c++" || exit 1 - LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PREFIX/lib make all || exit 1 - make info || exit 1 - make install || exit 1 - cd .. - echo $PREFIX/lib >/etc/ld.so.conf.d/local.conf - ldconfig -else - echo $SRC_GCC is already built. -fi diff --git a/lib/CPUs/MIPS/bsp/toolchain/newlib-1.16.0-jens.patch b/lib/CPUs/MIPS/bsp/toolchain/newlib-1.16.0-jens.patch deleted file mode 100644 index bf61a14..0000000 --- a/lib/CPUs/MIPS/bsp/toolchain/newlib-1.16.0-jens.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur newlib-1.16.0/newlib/libc/machine/mips/strlen.c newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c ---- newlib-1.16.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100 -+++ newlib-1.16.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:52:58.000000000 +0100 -@@ -60,6 +60,7 @@ - " addiu $2,$4,1\n" - "\n" - "1: lbu $3,0($4)\n" -+ " nop\n" - " bnez $3,1b\n" - " addiu $4,$4,1\n" - "\n" diff --git a/lib/CPUs/MIPS/bsp/toolchain/newlib-1.17.0-jens.patch b/lib/CPUs/MIPS/bsp/toolchain/newlib-1.17.0-jens.patch deleted file mode 100644 index bc28abc..0000000 --- a/lib/CPUs/MIPS/bsp/toolchain/newlib-1.17.0-jens.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur newlib-1.17.0/newlib/libc/machine/mips/strlen.c newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c ---- newlib-1.17.0/newlib/libc/machine/mips/strlen.c 2002-03-14 03:41:43.000000000 +0100 -+++ newlib-1.17.0-fixed/newlib/libc/machine/mips/strlen.c 2009-02-14 15:45:19.000000000 +0100 -@@ -60,6 +60,7 @@ - " addiu $2,$4,1\n" - "\n" - "1: lbu $3,0($4)\n" -+ " nop\n" - " bnez $3,1b\n" - " addiu $4,$4,1\n" - "\n" diff --git a/lib/CPUs/MIPS/dist/files.dist b/lib/CPUs/MIPS/dist/files.dist deleted file mode 100644 index 724b078..0000000 --- a/lib/CPUs/MIPS/dist/files.dist +++ /dev/null @@ -1,35 +0,0 @@ -../../../misc/dpram_2w2r.vhd -../../../misc/dpram_1w1r.vhd -../../../FIFO/src/fifo_ctrl_pkg.vhd -../../../FIFO/src/fifo_sync_ctrl.vhd -../../../FIFO/src/fifo_sync.vhd - -../../../uart/bbfifo_16x8.vhd -../../../uart/kcuart_rx.vhd -../../../uart/kcuart_tx.vhd -../../../uart/uart_rx.vhd -../../../uart/uart_tx.vhd -../../../uart/uart_wb.vhd - -../../../misc/gpio_wb.vhd -../../../misc/async_types.vhd -../../../misc/async_port_wb.vhd -../src/async_defs.vhd - -../src/bootloader.ROM.vhd -../../../misc/rom_wb.vhd - -../src/core/mips_types.vhd -../src/core/mips_instr.vhd -../src/core/mips_reg.vhd -../src/core/mips_shifter.vhd -../src/core/mips_alu.vhd -../src/core/mips_muldiv.vhd -../src/core/mips_cop.vhd -../src/core/mips_icache.vhd -../src/core/mips_dcache.vhd -../src/core/mips_biu.vhd -../src/core/mips_bcu.vhd -../src/core/mips_pipeline.vhd -../src/core/mips_top.vhd -../src/tb_mips_top.vhd diff --git a/lib/CPUs/MIPS/dist/mdist b/lib/CPUs/MIPS/dist/mdist deleted file mode 100644 index 9ce37a4..0000000 --- a/lib/CPUs/MIPS/dist/mdist +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/sh - -PROJECT="mips_top" -DIST_FILE="./files.dist" -DIST_DIR="./release/mips.r12" - -# --------------------------------------------------------------- -mkdir -p $DIST_DIR/src -mkdir -p $DIST_DIR/sim -mkdir -p $DIST_DIR/doc -mkdir -p $DIST_DIR/bsp -mkdir -p $DIST_DIR/tools - -cp -a ../bsp/* $DIST_DIR/bsp/ -cp -a ../doc/*.pdf $DIST_DIR/doc/ -cp -a ../doc/*.txt $DIST_DIR/doc/ -cp -a ../tools/* $DIST_DIR/tools/ - -cp -a ./tmpl/notes.txt $DIST_DIR/ -cp -a ./tmpl/gpl-3.0.txt $DIST_DIR/ -cp -a ./tmpl/tb_mips_top.wdo $DIST_DIR/sim/ -cp -a ./tmpl/hello.flash.bin $DIST_DIR/sim/ -cp -a ./tmpl/mips_sys.vhd $DIST_DIR/src/ - -for i in $(cat -s $DIST_FILE); do - echo $i; - cp -a $i $DIST_DIR/src/ -done; - -# Delete CVS directories -rm -r $(find release/ -name CVS) - -# --------------------------------------------------------------- -# Generate testbench do-file -echo "vlib work" > $DIST_DIR/sim/tb_$PROJECT.fdo - -for i in $(cat -s $DIST_FILE); do - echo "vcom -explicit -93 \"../src/$(basename $i)\"" >> $DIST_DIR/sim/tb_$PROJECT.fdo -done; -echo "vsim -t 1ps -lib work tb_$PROJECT" >> $DIST_DIR/sim/tb_$PROJECT.fdo - -echo "do {tb_mips_top.wdo}" >> $DIST_DIR/sim/tb_$PROJECT.fdo -echo "view wave" >> $DIST_DIR/sim/tb_$PROJECT.fdo -echo "view structure" >> $DIST_DIR/sim/tb_$PROJECT.fdo -echo "view signals" >> $DIST_DIR/sim/tb_$PROJECT.fdo -echo "run 1600us" >> $DIST_DIR/sim/tb_$PROJECT.fdo - -# --------------------------------------------------------------- diff --git a/lib/CPUs/MIPS/dist/tmpl/gpl-3.0.txt b/lib/CPUs/MIPS/dist/tmpl/gpl-3.0.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/lib/CPUs/MIPS/dist/tmpl/gpl-3.0.txt +++ /dev/null @@ -1,674 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 3, 29 June 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU General Public License is a free, copyleft license for -software and other kinds of works. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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But first, please read -. diff --git a/lib/CPUs/MIPS/dist/tmpl/hello.flash.bin b/lib/CPUs/MIPS/dist/tmpl/hello.flash.bin deleted file mode 100644 index cd652ef12f82962bcc1fd2a1770fa71ef9360112..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7936 zcmeHLZEPIX6+OE;x}}q~Lv7>~3!FBHs9ig|#1SU3 zybE;^RacHnEjo=|DL;_fABz)88k|fhl)5S@76p__Mg0&`)2c!iKiafHCF++fO1nLG zcE_Fsdqi8L{s2qQGw+>y?>qOs`|f?Sx8K&&2Ec%i{~OspXn#g95e@{KgRocNgXaDJ z-`{tBxcS8kAH_Ud9R{or2CW9{w=|@!FfvvI_gbwuU`^mlmWeN07*Y(RDhwEF42-Nb z^oyy$7z)ayOyKtk~jhoC~+-&wCYWAbe+>4mG5A9|O zaWjpr<`A}-!`N<)pu@~zhnYvhoW!l>Fqsgq{F}(&UXb78OG@B7@GF!3PH1SCj zl(9E6HEuLeHpKn}K4Av&akCD(iIHy_L8Jm)lH^75Rq=xLd!X700QRRsIJfy{#f58R zEQp1GgZT=_pv z31U;krie{ZmhTJn@!V!jLG|Q@@Fo~aLf*{{6XdQOJ-~OF>q`7v#1#*GmUz$uf1Y@? z2mVvy(;oP5i62`5zmn&hlyiJqv;T zCy77ofzJ`od*J7ZPk7)Lh);Up7m1rI;7(3Z5I8DleLNJvB4uU#V;GIX@F#K`li_@* z7J6uq*)DAgCV9`v4QgoRd}iCE*m|TC5f4JO=Men{>R<&vj!lF3LzL4s!yknIXbtoF8YUgAPXZ9bJ`B@uSvRHK%4S7I; zy6Nx5+Io?d+^-W|DgOsC-dZ8LoHHMyD~-u;X)Q9dPHkHxFOd@-3Tq7I>-0Q#ly;q3 z5@ap;mA|}pJ|(PZioaN#h)RKRv_ zfdHS_q(Jlne7bdgCEYr~fUc$e7kQDb;(erwH<2snTupB^+v^bE`RJTg0tni3iT&02 z*m2FXxx`0g4VTa5`Bk|u(cdLGH}7l6Tl7}oq>5i9`{Q-*)%Hqu)|Kav(J!%s!W!NO zU*g`3o7H$Fu3%;sc+uV`*zZT|_i7yH_)DhjPY@?&LERwzt45N#x0!k*&z;?Gu18+Y zYin>Z;1BzG2Cu~+*71fnzi|zkLTTo(doj-(SB=7~!WLw! zEjhz=JkR$~MegUoah_+&=L7yL$8HFX;O%0{zJF3@N-f_Z80UT*;d%_(TpYWiSH-g+w&grH z_FiWEh%ZtPB&MA^z1;652kVms+{k#=r|01(zLxL8akV>sE7wQo_g#r+SG)>qxi)La zEy%cU9v9sjJjwIZwn<`D`VPm^`~L72b(F6!&;EtJ>#E^jZLXE{f%CI((jBvl8wJHj+@j;+qN)SS^g)pH;{{<%W+kWTSiwIki>JF2BPX z%el2Nz*ziLT#w4SS08>zUC+G8eC@+4 z#I8U6R`L8&+zGF{$!|OLBu<cDu&D;Oldr7xJG>L%(VA6bMf|g4 zEKgdzZDZ4d!)QZ7pSL!-}#q-5Pt)Z+M}N(2W>vkz~2Mv_}hTW z-w3MtTY+uAP(YaL=V1+jGp#+jEC_Ptt^UVMF3p2ny&qdUWF4u61>psOb z=I;{EO>v!>o1dNHI=}0CKf?HwSd)79YH`qxCFZ2d{3+$DnKLhz_tjaaXJnlxfnVC| zt=Tc)J`3IC_qhs&760T+RFrGHoC!HU#UiQFH@8mT6*||gpySl4^{7bbj7bF({GH|n ztA}$L$tU6{RIpZ_U~WCa^Bp)UwMpt-HHfiJNS$)>h}5dm9s8`cXOGlpmAX&!J;~Z! zvrYK%oSosF`i$gS@qHgTo;oFU?S-jRr=+HpaO&B1m2w@F-%|W2uqJ=SuE{F%t<>HM zXV^ym`4yQ}w(l0Zp+cUO0hyMJfqz`<-TGn&1n z3R+Z)Jd_zd+)}o!wP}%oT+5OzEv7{tjJo>m?6saO!6Mj2fee%1{#V$&z;hF1EYAm_>2~xU+|`KC%aQJV+g0M?T%zb@OLBcX1Th-FfqEeY+@=$wu0?wUnOQ z%g>JTb4TeJi;SlM2zY_Fa6$fHYmbPgZR zW+E+eO!4{5*uh)`ke zW9w(z$ChRrX3MdSu|3R|XPaP~WaE$7#x&b8wgTHpwzF(=Z1ZgA*?!J;fo*~9BHJal zMK)}N5oA-@LTnnFP!TTnlmFgqfYE&&j1z3mnAdZ}vEe23K4ZSJy{p?_eJWmi|L@*> Uy#iOg&vSfe?!y)Mpsm2a0f^t)^#A|> diff --git a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd b/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd deleted file mode 100644 index 3f34fcf..0000000 --- a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd +++ /dev/null @@ -1,338 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; -use work.async_types.all; -use work.async_defs.all; - -ENTITY mips_sys IS - GENERIC - ( - ICACHE_SIZE : natural := 512; -- words - DCACHE_SIZE : natural := 512; -- words - SRAM_ADDR_WIDTH : integer := 14; - FLASH_ADDR_WIDTH : integer := 14 - ); - PORT - ( - eb : in std_logic; - nmi : in std_logic; - rst : in std_logic; - clk : in std_logic; - flash_cs_n : out std_logic; - flash_oe_n : out std_logic; - flash_we_n : out std_logic; - flash_be_n : out unsigned(3 downto 0); - sram_cs_n : out std_logic; - sram_we_n : out std_logic; - sram_oe_n : out std_logic; - sram_be_n : out unsigned(3 downto 0); - sram_a : out unsigned(SRAM_ADDR_WIDTH-1 downto 0); - sram_d : inout unsigned(31 downto 0); - flash_a : out unsigned(FLASH_ADDR_WIDTH-1 downto 0); - flash_d : inout unsigned(31 downto 0); - - gpo0 : out unsigned(31 downto 0); - gpo1 : out unsigned(31 downto 0); - gpi0 : in unsigned(31 downto 0); - gpi1 : in unsigned(31 downto 0); - - rx : in std_logic; - tx : out std_logic; - - debug : out unsigned(1 downto 0) - ); -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - constant CLK_PERIOD : time := 10 ns; - - -- Master - signal ACK_I : STD_LOGIC := '0'; - signal SRDY_I : STD_LOGIC := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal DAT_I : unsigned(31 downto 0) := (others => '0'); - signal DAT_O : unsigned(31 downto 0); - signal WE_O : STD_LOGIC; - signal SEL_O : unsigned(3 downto 0); - signal CYC_O : STD_LOGIC; - signal STB_O : STD_LOGIC; - signal MRDY_O : STD_LOGIC; - signal INT : unsigned (5 downto 0) := (others => '0'); - - -- Slaves - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal DAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal DAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_sram : std_logic; - signal ACK_O_sram : std_logic; - signal SRDY_O_sram : std_logic; - signal DAT_O_sram : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal DAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart : std_logic; - signal ACK_O_uart : std_logic; - signal SRDY_O_uart : std_logic; - signal DAT_O_uart : unsigned(31 downto 0); - - signal int_uart : std_logic; - - type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); - signal mem_area : mem_area_t; - -BEGIN - ------------------------------------------------------------------- --- Memory mux ------------------------------------------------------------------- -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_rom <= '0'; - CYC_I_sram <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart => - CYC_I_uart <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sram => - CYC_I_sram <= CYC_O; - - when others => null; - - end case; - - end process; - - SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio; - ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio; - DAT_I <= DAT_O_sram when CYC_I_sram = '1' else - DAT_O_rom when CYC_I_rom = '1' else - DAT_O_flash when CYC_I_flash = '1' else - DAT_O_uart when CYC_I_uart = '1' else - DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - - ------------------------------------------------------------------- -inst_mips_top: entity work.mips_top - GENERIC MAP - ( - icache_size => ICACHE_SIZE, -- words - dcache_size => DCACHE_SIZE -- words - ) - PORT MAP - ( - debug => debug, - nmi => nmi, - eb => eb, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - INT => INT - ); - INT(1) <= int_uart; - -inst_rom : entity work.rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => DAT_O_rom - ); - -inst_gpio : entity work.gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_gpio, - - sys_gpo0 => gpo0, - sys_gpo1 => gpo1, - sys_gpi0 => gpi0, - sys_gpi1 => gpi1 - ); - -inst_flash_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => FLASH_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_flash, - async_a => flash_a, - async_d => flash_d, - async_cs => flash_cs_n, - async_wr => flash_we_n, - async_rd => flash_oe_n, - async_be => flash_be_n, - async_rst => open - ); - -inst_sram_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => SRAM_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_sram - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_sram, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_sram, - SRDY_O => SRDY_O_sram, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_sram, - async_a => sram_a, - async_d => sram_d, - async_cs => sram_cs_n, - async_wr => sram_we_n, - async_rd => sram_oe_n, - async_be => sram_be_n, - async_rst => open - ); - -inst_uart : entity work.uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart, - SRDY_O => SRDY_O_uart, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_uart, - INT_O => int_uart, - ser_rx => rx, - ser_tx => tx - ); - -END; diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt deleted file mode 100644 index 02dbb35..0000000 --- a/lib/CPUs/MIPS/dist/tmpl/notes.txt +++ /dev/null @@ -1,84 +0,0 @@ ------------------------------------------------------------------ -Changes in release 12 ------------------------------------------------------------------ -- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked - using a single mips*-elf-gcc command. - To use: Copy $THIS_RELEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/, - and see bsp/examples/Makefile gcc usage - GCC-provided crt*-functions are now called without problems. - In summary: The toolchain is now more compliant to the intentional use of GCC. -- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O, - which is now compliant to literature. -- gpio_wb.vhd: Timer hard-reset is now removed. This helps to keep current time in case of CPU hard-reset. -- new bsp-example source: gunzip -- updated drawing 'mips_jbus_timing.pdf' -- added drawing 'memory_map.pdf' -- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection. -- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register. - Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo() -- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis. - Removed idecode_rom.vhd from project as consequence. -- added cop0 instructions to invalidate I-cache and D-Cache -- added copz instructions lwcz and swcz -- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload -- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h -- exception handlers can now be registered to any exception type -- bugfix: cop0 registers were not written during exception commit. Cop registers now behave like general registers. -- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian) -- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode -- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU. -- uart_wb.vhd: added interrupt enable -- Interrupt pending flags (IP) are not anymore masked by Interrupt mask flags (IM) in H/W. - Masking has to be done in S/W. H/W masking was removed because it isn't MIPS-compliant. -- added NMI/RST pin (more MIPS compliant). Transition Asserting/Deasserting causes exception. - Exception vector is reset (0xBFC00000). It's a soft-reset, which can help debugging. NMI/RST is not maskable. - Using NMI/RST as reset is dangerous because periphery may not be reseted. Has to be done in S/W. - Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already. -- Bootloader: Startup.S now invalidates I/D-Caches at boot. -- uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge. -- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect. - Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug. - Symptom: Consecutive load instructions without nops using same target register (which is legal) like - lw $1, 0(mem) - lwl $1, 1(mem) - or - lwl $1, 0(mem) - lwr $1, 1(mem) - or similar, lead to incorrect result. Now it's fixed. - ------------------------------------------------------------------ -Changes in release 11 ------------------------------------------------------------------ -- bugfix in mips_pipeline: pc_is_branch is now initialized at reset - (fixes CPU unrecoverable state after reset) -- reverted "optimization" in mips_dcache, which behaved buggy during exceptions -- new example source: test_exception -- minor changes in libsys -- added async_port_timing in doc -- examples/testbench: date set now really works - ------------------------------------------------------------------ -Changes in release 10b ------------------------------------------------------------------ -- bugfix: fixed compiler bug (missing nop after lw) in bootloader, - which caused exception during boot - ------------------------------------------------------------------ -Changes in release 10a ------------------------------------------------------------------ -async_port_wb: -- added byte enable for async_port - -bootloader.c -- bugfix: fixed compiler bug (missing nop after lw) - -mips-core -- bugfix: SEL_O lines are also asserted correctly during reads - -tools/romgen -- TCL-Jtag now compatible with Chipscope 10.1 - -mips_sys.c -- use byte enable for sram and flash - - diff --git a/lib/CPUs/MIPS/dist/tmpl/tb_mips_top.wdo b/lib/CPUs/MIPS/dist/tmpl/tb_mips_top.wdo deleted file mode 100644 index 93f1ed5..0000000 --- a/lib/CPUs/MIPS/dist/tmpl/tb_mips_top.wdo +++ /dev/null @@ -1,60 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {MIPS top} -add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/mrdy_o -add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal /tb_mips_top/sel_o -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o -add wave -noupdate -format Literal /tb_mips_top/int -add wave -noupdate -divider Flash -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/flash_cs_n -add wave -noupdate -format Logic /tb_mips_top/flash_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d -add wave -noupdate -divider SRAM -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/sram_cs_n -add wave -noupdate -format Literal /tb_mips_top/sram_wr_n -add wave -noupdate -format Logic /tb_mips_top/sram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d -add wave -noupdate -divider GPIO -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 -add wave -noupdate -divider UART -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/int_uart_rx -add wave -noupdate -format Logic /tb_mips_top/rx -add wave -noupdate -format Logic /tb_mips_top/tx -add wave -noupdate -divider {Memory bus} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/mem_area -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {222066850 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {221809160 ps} {222394902 ps} diff --git a/lib/CPUs/MIPS/doc/J-MIPS.txt b/lib/CPUs/MIPS/doc/J-MIPS.txt deleted file mode 100644 index 6f6dcb2..0000000 --- a/lib/CPUs/MIPS/doc/J-MIPS.txt +++ /dev/null @@ -1,107 +0,0 @@ ------------------------------------------------------------------ -J-MIPS Features ------------------------------------------------------------------ - -- Synchrones Design -- Portable Beschreibung in VHDL -- Kompatible zur GNU Toolchain (Binutils, GCC, Newlib) -- Befehle kompatibel mit MIPS-1 ISA (z.B. MIPS R3000) -- 5-Stufige Pipeline und Hazardvermeidung durch Forwarding -- 64Bit Multiplier (32Bit Operanden), 12 Cycles Latenz -- 64Bit Divider (32Bit Operanden), 36 Cycles Latenz -- Coprocessor 0 (COP0) für Exceptionhandling -- Direct-mapped Instruction Cache mit variabler Größe, 8-words per Line -- Direct-mapped Data Cache mit variabler Größe, 8-words per Line -- J-Bus kompatible Bus Interface Unit (J-Bus ist im wesentlichen FIFO interface mit 'wichtigen' Signalnamen) -- 1,2 DMIPS/MHz mit 16Kbyte I/D-Cache (Dhrystone 2.1, GCC 4.3) - ------------------------------------------------------------------ -Known Limitations ------------------------------------------------------------------ -- keine MMU -- keine Unterstützung für Bus exceptions IBE und DBE -- kein externes Coprocessor interface (COP1..3) für z.B. FPU -- Befehle für Cop1..3 nicht implementiert: - CFCz, CTCz, COPz, MFCz, MTCz, LWCz, SWCz - Benutzung dieser Befehle führt zur Exception 'RI' (Reserved Instruction) -- nicht alle COP0 Register/Bits vorhanden. - ------------------------------------------------------------------ -Known Bugs ------------------------------------------------------------------ -- es gibt bestimmt noch nicht entdeckte Bugs - ------------------------------------------------------------------ -Known Optimizations ------------------------------------------------------------------ -- Area: Multiplier als technologieabhängiges Primitive instanzieren -- Area: Auf Divider verzichten -- Area: Auf Multiplier verzichten -- Area vs. Speed: Bei Hazards Pipeline-stall statt Forwarding. - Durch Stalling geringerer Befehlsdurchsatz dafür weniger Logik. - Weniger Logik bedeutet vielleicht wieder auch größere Taktfrequenz. - ------------------------------------------------------------------ -Known ToDos ------------------------------------------------------------------ -- Unterstützung für Bus exceptions IBE und DBE -- Externes COP1..3 interface, fehlende COP-Befehle implementieren -- Optimierungen evaluieren und ggf. durchführen - ------------------------------------------------------------------ -Synthesis results ------------------------------------------------------------------ -Virtex-4 XC4VSX35-10 - -Config: 16Kbyte I/D-Cache - -Number of Slices 2387 15360 15% -Number of Slice Flip Flops 1784 30720 5% -Number of 4 input LUTs 3962 30720 12% -Number of FIFO16/RAMB16s 18 192 9% - -Speed: 110MHz nach Synthesis - ------------------------------------------------------------------ -Virtex-1 XCV1000-4 - -Config: 4Kbyte I/D-Cache - -Number of Slices 2045 13824 16% -Number of Slice Flip Flops 1783 27648 7% -Number of 4 input LUTs 3923 27648 15% -Number of FIFO16/RAMB16s 20 32 62% - -Speed: 30MHz nach Synthesis - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC ohne Small-data section -- MIPS Rev. 9 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -1k 32 DMIPS 5 Mbit/s 345 kwhets/s 47/767 2,135s -2k 51 DMIPS 5 Mbit/s 534 kwhets/s 38/561 2,134s -4k 72 DMIPS 5 Mbit/s 623 kwhets/s 36/259 2,121s -8k 98 DMIPS 10 Mbit/s 1149 kwhets/s 31/228 1,938s -16k 115 DMIPS 17 Mbit/s 1234 kwhets/s 23/225 1,938s -32k 115 DMIPS 17 Mbit/s 1285 kwhets/s 24/218 1,938s -64k 115 DMIPS 17 Mbit/s 1285 kwhets/s 20/221 1,938s - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC mit Small-data section -- MIPS Rev. 9 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -16k 117 DMIPS 17 Mbit/s 1236 kwhets/s 24/230 1,811s - ------------------------------------------------------------------ -Performance bei 100MHz -- GCC mit Small-data section -- MIPS Rev. 10 ------------------------------------------------------------------ -I/D-Cache Dhrystone-2.1 RipeMD-160 Whetstone Stanford Queens(12x12) -16k 120 DMIPS 17 Mbit/s 1242 kwhets/s 25/219 1,803s - - diff --git a/lib/CPUs/MIPS/doc/async_port_timing.pdf b/lib/CPUs/MIPS/doc/async_port_timing.pdf deleted file mode 100644 index d9277a1..0000000 --- a/lib/CPUs/MIPS/doc/async_port_timing.pdf +++ /dev/null @@ -1,2 +0,0 @@ -%PDF-1.3 -%Çì \ No newline at end of file diff --git a/lib/CPUs/MIPS/doc/memory_map.pdf b/lib/CPUs/MIPS/doc/memory_map.pdf deleted file mode 100644 index e69de29..0000000 diff --git a/lib/CPUs/MIPS/doc/memory_map.vsd b/lib/CPUs/MIPS/doc/memory_map.vsd deleted file mode 100644 index a28ec1a022b70b932dc93a097ce38fb73d026709..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 17920 zcmeHu30xD`*7%vp!X{3DfQU%KCb(b%C@N2#5dm=xWf8U3fQpJm23g!~q6p$ftot5R zthL%kMQYX7ATE_w8|uCfhzo)>5mXk1`QIU>wcGFY{l53T_xk^s~kgV4qAfW-Ml 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zM??xu23Dd;aiyAz*y^CGPt8Pix2F^}*Y77A%cd1{PbIvax~rh`8^lP36fdtfg@(4c zo;hc9i&kDe{3Mfh8;w`7m4m)1`>9ymcq}g}vdPupJkVh4foT^hNkuESZko>y zdMx!L8brA$Od)E++Cl;R{IKOxeHvlH{E=4^=d8BZHTD!6OjT5x#+WcK^B&8!B*Wl< z;6r97MX|P0J2g`|8OQ{kC?C4i&xH9i&|-YB#6;UO#q$)v>jN{%M$2R=m=WtR7pw%I z-Z_?3Lwfk2FBFRqrt1oa+QKb?fZxlp2BQAf_U3YfsnsihyZ$F+JL!?}`xBz+|A6$Ej+3g% zj&JYAoH*R0T39$({(Sy^A)b>(d#PWrre9lEkll%YONG*F{w3&IJyw7Al~!5#;eucT zf8WnI>@0b96>>rHF~btTY4n@>?C;w?ja zdb*dq36oMK-e>kl;(~o23rdrj%ruF)FyERkyw)n?Cs$($@W7&0Ifk64n=3^9B_vB_ zH8!R(h_Wb&n24!gI0w#LpGAdqN%lU6&sNkcIKb0}UZHR%CB8QnvxdQHw9lpJA?i&I z_6jb. --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.async_types.all; - -package async_defs is - - constant ts_flash : async_timespec_t := - ( - ncyc_leadin => 1, - ncyc_pulse_rd => 12, - ncyc_pulse_wr => 7, - ncyc_leadout => 2, - ncyc_release => 3, - ncyc_pulse_rst => 8, - can_page_rd => true, - nbits_page_rd => 4, - ncyc_pulse_page_rd => 6, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - constant ts_sram : async_timespec_t := - ( - ncyc_leadin => 1, - ncyc_pulse_rd => 12, - ncyc_pulse_wr => 7, - ncyc_leadout => 1, - ncyc_release => 1, - ncyc_pulse_rst => 8, - can_page_rd => false, - nbits_page_rd => 0, - ncyc_pulse_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - -end async_defs; diff --git a/lib/CPUs/MIPS/src/bootloader.ROM.vhd b/lib/CPUs/MIPS/src/bootloader.ROM.vhd deleted file mode 100644 index d273a3b..0000000 --- a/lib/CPUs/MIPS/src/bootloader.ROM.vhd +++ /dev/null @@ -1,2082 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - constant word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A123C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - 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X"AFBE0260", -- 00001264 - X"AFB7025C", -- 00001268 - X"AFB60258", -- 0000126C - X"AFB50254", -- 00001270 - X"AFB40250", -- 00001274 - X"0FF0060A", -- 00001278 - X"AFB3024C", -- 0000127C - X"AE200000", -- 00001280 - X"36220004", -- 00001284 - X"02402021", -- 00001288 - X"3C05A400", -- 0000128C - X"8C500000", -- 00001290 - X"0FF002ED", -- 00001294 - X"00000000", -- 00001298 - X"04410003", -- 0000129C - X"3C04BFC0", -- 000012A0 - X"0BF004C9", -- 000012A4 - X"24841944", -- 000012A8 - X"02402021", -- 000012AC - X"0FF00350", -- 000012B0 - X"3205007F", -- 000012B4 - X"00409021", -- 000012B8 - X"8E220000", -- 000012BC - X"00000000", -- 000012C0 - X"30420008", -- 000012C4 - X"14400044", -- 000012C8 - X"3C11BFC0", -- 000012CC - X"0FF000B0", -- 000012D0 - X"262419F4", -- 000012D4 - X"3C02A400", -- 000012D8 - X"02428021", -- 000012DC - X"8E030000", -- 000012E0 - X"3C023149", -- 000012E4 - X"3442464A", -- 000012E8 - X"10620011", -- 000012EC - X"3C024A46", -- 000012F0 - X"34424931", -- 000012F4 - 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X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/core/.directory_history b/lib/CPUs/MIPS/src/core/.directory_history deleted file mode 100644 index 1dd52df..0000000 --- a/lib/CPUs/MIPS/src/core/.directory_history +++ /dev/null @@ -1,12 +0,0 @@ -VHDL/lib/CPUs/MIPS/src/core/dcache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd -VHDL/lib/CPUs/MIPS/src/core/icache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd - -VHDL/lib/CPUs/MIPS/src/core/mips_bui.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_biu.vhd -VHDL/lib/CPUs/MIPS/src/core/mips_dcache.vhd - -VHDL/lib/CPUs/MIPS/src/core/mips_icache.vhd - diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd deleted file mode 100644 index ef8c5db..0000000 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ /dev/null @@ -1,496 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library work; -use work.mips_types.all; - -ENTITY dcache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_we : in STD_LOGIC; - cpu_be : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); -END dcache; - -ARCHITECTURE behavior OF dcache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - -COMPONENT dpram_2w2r is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type dcache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_dcache_entry(x : tag_ram_data_t) return dcache_entry_t is - variable result : dcache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_dcache_entry; - - function to_tag_ram_data(x : dcache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache); - signal s, sn : cache_state_t; - - signal cache_req : std_logic; - signal cache_ack : std_logic; - signal cache_busy : std_logic; - signal cache_hit : std_logic; - signal tag_match : std_logic; - signal cache_hit_inv : std_logic; - signal tag_match_inv : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal addr_windex_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal cache_index_inv : unsigned(cache_index_width-1 downto 0); - signal tag_reg : unsigned(tag_width-1 downto 0); - signal tag_inv : unsigned(tag_width-1 downto 0); - signal tag_reg_inv : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : dcache_entry_t; - signal cache_entry_out : dcache_entry_t; - signal cache_entry_out_inv : dcache_entry_t; - signal cpu_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal cpu_data_ram_dout : word_t; - signal cpu_data_reg : word_t; - signal cpu_be_reg : unsigned(3 downto 0); - signal cpu_we_reg : std_logic; - signal ctrl_data_ram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal ctrl_data_ram_we : unsigned(3 downto 0); - signal cpu_data_ram_we : unsigned(3 downto 0); - signal cpu_we2 : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_dout : tag_ram_data_t; - signal tag_ram_dout_inv : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_din : tag_ram_data_t; - signal tag_ram_we : std_logic; - - signal fill_count : natural range 0 to 2**word_index_width-1; - signal fill_count_en : std_logic; - signal fill_count_rdy : std_logic; - signal flush_count : natural range 0 to 2**cache_index_width-1; - signal flush_count_rst : std_logic; - signal flush_count_en : std_logic; - signal flush_count_rdy : std_logic; - signal request_count : natural range 0 to 2**word_index_width-1; - signal request_count_en : std_logic; - signal request_count_rdy : std_logic; - signal was_miss : std_logic; - signal invalidate_all : std_logic; - signal invalidate_ack : std_logic; - signal invalidate_en : std_logic; - signal invalidate_req : std_logic; - signal cpu_hit_we : std_logic; - signal instant_raw : std_logic; - -begin - - cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - cpu_hit_we <= cpu_we2 and cache_hit; - -cpu_index_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '1' then - if ACK_I = '1' then - word_index_reg <= word_index_reg + 1; - end if; - elsif cache_busy = '0' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_reg <= cpu_tag; - end if; - end if; - end process; - -addr_windex_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '1'then - if SRDY_I = '1' then - addr_windex_reg <= addr_windex_reg + 1; - end if; - elsif cache_busy = '0' then - addr_windex_reg <= cpu_word_index; - end if; - end if; - end process; - -cpu_request_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cpu_we_reg <= '0'; - cache_req <= '0'; - elsif cpu_en = '1' and en = '1' then - if cache_busy = '0' then - cpu_we2 <= cpu_we; - cache_req <= '1'; - cpu_data_reg <= cpu_din; - cpu_be_reg <= cpu_be; - cpu_we_reg <= cpu_we; - end if; - elsif cache_ack = '1' then - cache_req <= '0'; - cpu_we2 <= '0'; - end if; - end if; - end process; - -instant_raw_logic: - process(CLK_I) - begin - if rising_edge(CLK_I) then - instant_raw <= '0'; - if cpu_word_index = word_index_reg then - instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we; - end if; - end if; - end process; - -inst_tag_ram : dpram_2w2r - GENERIC MAP - ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => '1', - we_a => tag_ram_we, - we_b => '0', - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_din, - din_b => tag_ram_din, - dout_a => tag_ram_dout_inv, - dout_b => tag_ram_dout - ); - -gen_data_ram: - for i in 0 to 3 generate - begin - - inst_data_ram : dpram_2w2r - GENERIC MAP - ( - addr_width => lg2(cache_size), - data_width => word_t'length/4 - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => '1', - we_a => cpu_data_ram_we(i), - we_b => ctrl_data_ram_we(i), - addr_a => ctrl_data_ram_addr, - addr_b => cpu_data_ram_addr, - din_a => cpu_data_reg(8*(i+1)-1 downto 8*i), - din_b => DAT_I(8*(i+1)-1 downto 8*i), - dout_a => open, - dout_b => cpu_data_ram_dout(8*(i+1)-1 downto 8*i) - ); - end generate; - - - -cache_invalidate_request: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then - invalidate_req <= '1'; - invalidate_all <= ctrl.inv_all or RST_I; - tag_reg_inv <= tag_inv; - elsif invalidate_ack = '1' then - invalidate_req <= '0'; - invalidate_all <= '0'; - end if; - end if; - end process; - -cache_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - cpu_busy <= cache_busy; - cpu_dout <= cpu_data_ram_dout; - - tag_match <= '1' when tag_reg = cache_entry_out.tag else '0'; - cache_hit <= tag_match and cache_entry_out.valid; - tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0'; - cache_hit_inv <= tag_match_inv and cache_entry_out_inv.valid; - tag_ram_din <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else cache_index_reg; - tag_ram_addr_rd <= cpu_cache_index when (was_miss = '0' and instant_raw = '0') else cache_index_reg; - - cache_entry_out <= to_dcache_entry(tag_ram_dout); - cache_entry_out_inv <= to_dcache_entry(tag_ram_dout_inv); - - cpu_data_ram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (cache_index_reg & word_index_reg); - ADDR_O <= tag_reg & cache_index_reg & addr_windex_reg & "00"; - ctrl_data_ram_addr <= cache_index_reg & word_index_reg; - ctrl_data_ram_we <= (others => fill_count_en and ACK_I); - cpu_data_ram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0'); - -cache_state: - process(s, cache_req, instant_raw, cache_hit, cache_hit_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_reg, SRDY_I, cpu_we_reg, invalidate_req, invalidate_all) - begin - cache_busy <= cache_req; - cache_ack <= '0'; - tag_ram_we <= '0'; - flush_count_en <= '0'; - flush_count_rst <= '0'; - invalidate_en <= '0'; - request_count_en <= '0'; - fill_count_en <= '0'; - CYC_O <= '0'; - STB_O <= '0'; - was_miss <= '0'; - invalidate_ack <= '0'; - - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_reg; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= ready; - when ready => - if invalidate_req = '1' then - sn <= invalidate; - invalidate_en <= '1'; - else - if cache_req = '1' then - if cache_hit = '0' and cpu_we_reg = '0' then - sn <= mem_request; - cache_busy <= '1'; - CYC_O <= '1'; - else - cache_busy <= instant_raw; - cache_ack <= not instant_raw; - end if; - end if; - end if; - when invalidate => - sn <= rd_cache; - invalidate_en <= '1'; - invalidate_ack <= '1'; - if invalidate_all = '1' then - sn <= flush; - flush_count_rst <= '1'; - elsif cache_hit_inv = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - sn <= rd_cache; - end if; - - when flush => - flush_count_en <= '1'; - invalidate_en <= '1'; - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if flush_count_rdy = '1' then - tag_ram_we <= '0'; - sn <= rd_cache; - end if; - when mem_request => - CYC_O <= '1'; - if SRDY_I = '1' then - sn <= mem_access; - end if; - when mem_access => - fill_count_en <= '1'; - request_count_en <= '1'; - CYC_O <= '1'; - STB_O <= '1'; - if request_count_rdy = '1' then - STB_O <= '0'; - sn <= mem_data; - end if; - when mem_data => - CYC_O <= '1'; - fill_count_en <= '1'; - if fill_count_rdy = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - end if; - when rd_cache => - was_miss <= '1'; - sn <= ready; - - when others => - sn <= ready; - end case; - - end process; - -flush_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if ctrl.inv_at = '1' then - flush_count <= to_integer(cache_index_inv); - elsif flush_count_rst = '1' then - flush_count_rdy <= '0'; - flush_count <= 2**cache_index_width-1; - elsif flush_count_en = '1' then - if flush_count /= 0 then - flush_count <= flush_count - 1; - else - flush_count_rdy <= '1'; - end if; - end if; - end if; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '0' then - request_count_rdy <= '0'; - request_count <= 2**word_index_width-1; - else - if SRDY_I = '1' then - if request_count /= 0 then - request_count <= request_count - 1; - else - request_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -fill_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '0' then - fill_count_rdy <= '0'; - fill_count <= 2**word_index_width-1; - else - if ACK_I = '1' then - if fill_count /= 0 then - fill_count <= fill_count - 1; - else - fill_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd deleted file mode 100644 index 9cb04ce..0000000 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ /dev/null @@ -1,460 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library work; -use work.mips_types.all; - -ENTITY icache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); -END icache; - -ARCHITECTURE behavior OF icache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - -COMPONENT dpram_2w2r is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type icache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is - variable result : icache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_icache_entry; - - function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, invalidate, flush, mem_request, mem_access, mem_data, rd_cache, upd_cache); - signal s, sn : cache_state_t; - - signal cache_req : std_logic; - signal cache_ack : std_logic; - signal cache_busy : std_logic; - signal cache_miss : std_logic; - signal tag_match : std_logic; - signal cache_miss_inv : std_logic; - signal tag_match_inv : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal addr_windex_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal cache_index_inv : unsigned(cache_index_width-1 downto 0); - signal tag_reg : unsigned(tag_width-1 downto 0); - signal tag_inv : unsigned(tag_width-1 downto 0); - signal tag_reg_inv : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : icache_entry_t; - signal cache_entry_out : icache_entry_t; - signal cache_entry_out_inv : icache_entry_t; - signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_rd : word_t; - signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_wr : word_t; - signal data_ram_we : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_rd : tag_ram_data_t; - signal tag_ram_data_rd_inv : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_wr : tag_ram_data_t; - signal tag_ram_we : std_logic; - - signal fill_count : natural range 0 to 2**word_index_width-1; - signal fill_count_en : std_logic; - signal fill_count_rdy : std_logic; - signal flush_count : natural range 0 to 2**cache_index_width-1; - signal flush_count_rst : std_logic; - signal flush_count_en : std_logic; - signal flush_count_rdy : std_logic; - signal request_count : natural range 0 to 2**word_index_width-1; - signal request_count_en : std_logic; - signal request_count_rdy : std_logic; - signal ram_read_en : std_logic; - signal was_miss : std_logic; - signal invalidate_all : std_logic; - signal invalidate_ack : std_logic; - signal invalidate_en : std_logic; - signal invalidate_req : std_logic; - -begin - - ram_read_en <= cpu_en or was_miss; - cache_index_inv <= ctrl.inv_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - tag_inv <= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - -cpu_index_reg: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cache_index_reg <= (others => '0'); - tag_reg <= (others => '0'); - elsif fill_count_en = '1' then - if ACK_I = '1' then - word_index_reg <= word_index_reg + 1; - end if; - elsif cache_busy = '0' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_reg <= cpu_tag; - end if; - end if; - end process; - -addr_windex_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '1'then - if SRDY_I = '1' then - addr_windex_reg <= addr_windex_reg + 1; - end if; - elsif cache_busy = '0' then - addr_windex_reg <= cpu_word_index; - end if; - end if; - end process; - -cpu_request_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cache_req <= '0'; - elsif cpu_en = '1' then - if cache_busy = '0' then - cache_req <= en; - end if; - elsif cache_ack = '1' then - cache_req <= '0'; - end if; - end if; - end process; - -cache_invalidate_request: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or ctrl.inv_all = '1' or ctrl.inv_at = '1' then - invalidate_req <= '1'; - invalidate_all <= ctrl.inv_all or RST_I; - tag_reg_inv <= tag_inv; - elsif invalidate_ack = '1' then - invalidate_req <= '0'; - invalidate_all <= '0'; - end if; - end if; - end process; - -inst_tag_ram : dpram_2w2r - GENERIC MAP - ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP - ( - clk_a => CLK_I, - clk_b => CLK_I, - en_a => '1', - en_b => ram_read_en, - we_a => tag_ram_we, - we_b => '0', - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_data_wr, - din_b => tag_ram_data_wr, - dout_a => tag_ram_data_rd_inv, - dout_b => tag_ram_data_rd - ); - -inst_data_ram : dpram_1w1r - GENERIC MAP - ( - addr_width => lg2(cache_size), - data_width => word_t'length - ) - PORT MAP - ( - clka => CLK_I, - clkb => CLK_I, - en_a => '1', - en_b => ram_read_en, - we_a => data_ram_we, - addr_a => data_ram_addr_wr, - addr_b => data_ram_addr_rd, - din_a => data_ram_data_wr, - dout_b => data_ram_data_rd - ); - -cache_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - ADDR_O <= tag_reg & cache_index_reg & addr_windex_reg & "00"; - cpu_busy <= cache_busy; - cpu_dout <= data_ram_data_rd; - - cache_entry_out <= to_icache_entry(tag_ram_data_rd); - tag_match <= '1' when tag_reg = cache_entry_out.tag else '0'; - cache_miss <= not (tag_match and cache_entry_out.valid); - - cache_entry_out_inv <= to_icache_entry(tag_ram_data_rd_inv); - tag_match_inv <= '1' when tag_reg_inv = cache_entry_out_inv.tag else '0'; - cache_miss_inv <= not (tag_match_inv and cache_entry_out_inv.valid); - - tag_ram_data_wr <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_wr <= to_unsigned(flush_count, cache_index_width) when invalidate_en = '1' else cache_index_reg; - tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; - data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg); - data_ram_addr_wr <= cache_index_reg & word_index_reg; - data_ram_data_wr <= DAT_I; - data_ram_we <= fill_count_en and ACK_I; - -cache_state: - process(s, cache_req, cache_miss, cache_miss_inv, flush_count_rdy, fill_count_rdy, request_count_rdy, tag_reg, SRDY_I, invalidate_req, invalidate_all) - begin - cache_busy <= cache_req; - cache_ack <= '0'; - tag_ram_we <= '0'; - flush_count_en <= '0'; - flush_count_rst <= '0'; - invalidate_en <= '0'; - request_count_en <= '0'; - fill_count_en <= '0'; - CYC_O <= '0'; - STB_O <= '0'; - was_miss <= '0'; - invalidate_ack <= '0'; - - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_reg; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= ready; - when ready => - if invalidate_req = '1' then - sn <= invalidate; - invalidate_en <= '1'; - elsif cache_req = '1' then - if cache_miss = '1' then - sn <= mem_request; - CYC_O <= '1'; - else - cache_busy <= '0'; - cache_ack <= '1'; - end if; - end if; - when invalidate => - sn <= rd_cache; - invalidate_en <= '1'; - invalidate_ack <= '1'; - if invalidate_all = '1' then - sn <= flush; - flush_count_rst <= '1'; - elsif cache_miss_inv = '0' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - sn <= rd_cache; - end if; - - when flush => - flush_count_en <= '1'; - invalidate_en <= '1'; - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if flush_count_rdy = '1' then - tag_ram_we <= '0'; - sn <= rd_cache; - end if; - when mem_request => - CYC_O <= '1'; - if SRDY_I = '1' then - sn <= mem_access; - end if; - when mem_access => - request_count_en <= '1'; - fill_count_en <= '1'; - CYC_O <= '1'; - STB_O <= '1'; - if request_count_rdy = '1' then - STB_O <= '0'; - sn <= mem_data; - end if; - when mem_data => - CYC_O <= '1'; - fill_count_en <= '1'; - if fill_count_rdy = '1' then - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - end if; - when rd_cache => - was_miss <= '1'; - sn <= ready; - when others => - sn <= ready; - end case; - - end process; - -flush_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if ctrl.inv_at = '1' then - flush_count <= to_integer(cache_index_inv); - elsif flush_count_rst = '1' then - flush_count_rdy <= '0'; - flush_count <= 2**cache_index_width-1; - elsif flush_count_en = '1' then - if flush_count /= 0 then - flush_count <= flush_count - 1; - else - flush_count_rdy <= '1'; - end if; - end if; - end if; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_count_en = '0' then - request_count_rdy <= '0'; - request_count <= 2**word_index_width-1; - else - if SRDY_I = '1' then - if request_count /= 0 then - request_count <= request_count - 1; - else - request_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -fill_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if fill_count_en = '0' then - fill_count_rdy <= '0'; - fill_count <= 2**word_index_width-1; - else - if ACK_I = '1' then - if fill_count /= 0 then - fill_count <= fill_count - 1; - else - fill_count_rdy <= '1'; - end if; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd deleted file mode 100644 index a64b5a4..0000000 --- a/lib/CPUs/MIPS/src/core/mips_alu.vhd +++ /dev/null @@ -1,184 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity alu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_res : unsigned (data_width-1 downto 0); - signal and_res : unsigned (data_width-1 downto 0); - signal xor_res : unsigned (data_width-1 downto 0); - signal nor_res : unsigned (data_width-1 downto 0); - signal or_res : unsigned (data_width-1 downto 0); - signal eq, sa, sb, sr, c, z : STD_LOGIC; - signal lts, ltu : STD_LOGIC; - --------------------------------------------------------------------------- -begin - - eq <= '1' when op1_in = op2_in else '0' after 3 ns; - sa <= op1_in(op1_in'left); - sb <= op2_in(op2_in'left); - sr <= sum_res(sum_res'left); - z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - - flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr)); - flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr)); --- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb)))); - lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr)); - - ltu <= (not eq) and (not c); - flags.lts <= lts; - flags.ltu <= ltu; - flags.c <= c; - --------------------------------------------------------------------------- -proc_op_and: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - and_res <= (x1 and x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_xor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - xor_res <= (x1 xor x2) after 2 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_nor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - nor_res <= (x1 nor x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_or: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - or_res <= (x1 or x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu) - begin - - result <= sum_res; - - case ctrl.outsel is - - when alu_adder => - result <= sum_res; - - when alu_and => - result <= and_res; - - when alu_xor => - result <= xor_res; - - when alu_nor => - result <= nor_res; - - when alu_or => - result <= or_res; - - when alu_shift2 => - result <= op2_shifted; - - when alu_ltu => - result <= (data_width-1 downto 1 => '0') & ltu; - - when alu_lts => - result <= (data_width-1 downto 1 => '0') & lts; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, ctrl) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - - op1 := '0' & op1_in & not ctrl.add; - if (ctrl.add = '1') then - op2 := '0' & op2_in & '0'; - else - op2 := '0' & not op2_in & '1'; - end if; - sum := op1 + op2; - - -- Form sum + carry - sum_res <= unsigned(sum(data_width downto 1)) after 4 ns; - c <= sum(sum'left) after 4 ns; - - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd deleted file mode 100644 index 51b5ed7..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bcu.vhd +++ /dev/null @@ -1,52 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity bcu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); -end bcu; - -architecture Behavioral of bcu is - --------------------------------------------------------------------------- -begin - - flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns; - flags.ltz <= op1_in(op1_in'left) after 1 ns; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd deleted file mode 100644 index dab7de0..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ /dev/null @@ -1,507 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity biu is - Generic - ( - icache_size : natural := 2048; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 2048; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - cop0_ctrl_in : in cop0_ctrl_out_t; - cpu_imem_err : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_err : out STD_LOGIC; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_we : in STD_LOGIC; - cpu_dmem_be : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t - ); -end biu; - -architecture behavior of biu is - - COMPONENT icache - GENERIC - ( - cache_size : natural; -- words - line_size : natural -- words - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); - END COMPONENT; - - COMPONENT dcache - GENERIC - ( - cache_size : natural; -- words - line_size : natural -- words - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - STB_O : out STD_LOGIC; - CYC_O : out STD_LOGIC; - ctrl : in cache_ctrl_t; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_we : in STD_LOGIC; - cpu_be : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC - ); - END COMPONENT; - - type bus_state_t is (init, ready, icache_bus_access, dcache_bus_access, write_bus, read_bus, read_finish); - - signal s, sn : bus_state_t; - signal bus_idle : std_logic; - signal busy : std_logic; - signal dmem_be : unsigned(3 downto 0); - signal dcache_dout : word_t; - signal dcache_mem_gnt : std_logic; - signal icache_mem_gnt : std_logic; - signal dmem_mem_wr_gnt : std_logic; - signal dmem_mem_rd_gnt : std_logic; - signal dcache_busy : std_logic; - signal icache_busy : std_logic; - signal CYC_O_icache : std_logic; - signal CYC_O_dcache : std_logic; - signal CYC_O_dmem_rd : std_logic; - signal CYC_O_dmem_wr : std_logic; - signal SRDY_I_icache : std_logic; - signal SRDY_I_dcache : std_logic; - signal ADDR_O_icache : word_t; - signal ADDR_O_dcache : word_t; - signal ADDR_O_dmem_rd : word_t; - signal ADDR_O_dmem_wr : word_t; - signal STB_O_icache : std_logic; - signal STB_O_dcache : std_logic; - signal STB_O_dmem_rd : std_logic; - signal STB_O_dmem_wr : std_logic; - signal DAT_I_dmem_rd : word_t; - signal DAT_O_dmem_wr : word_t; - signal SEL_O_dmem_wr : unsigned(3 downto 0); - signal SEL_O_dmem_rd : unsigned(3 downto 0); - signal dcached : std_logic; - signal dcache_en : std_logic; - signal uncached_access : std_logic; - - type timeout_cnt_t is range 0 to 1E5-1; - signal bus_timeout_cnt : timeout_cnt_t; - signal bus_timeout : std_logic; - - signal bout_fifo_din : unsigned(68 downto 0); - signal bout_fifo_dout : unsigned(68 downto 0); - signal bout_fifo_re : std_logic; - signal bout_fifo_we : std_logic; - signal bout_fifo_full : std_logic; - signal bout_fifo_empty : std_logic; - signal bout_rdy : std_logic; - - alias bout_fifo_addr_in is bout_fifo_din(31 downto 0); - alias bout_fifo_data_in is bout_fifo_din(63 downto 32); - alias bout_fifo_sel_in is bout_fifo_din(67 downto 64); - alias bout_fifo_we_in is bout_fifo_din(68); - alias bout_fifo_addr_out is bout_fifo_dout(31 downto 0); - alias bout_fifo_data_out is bout_fifo_dout(63 downto 32); - alias bout_fifo_sel_out is bout_fifo_dout(67 downto 64); - alias bout_fifo_we_out is bout_fifo_dout(68); - - signal write_fifo_din : unsigned(67 downto 0); - signal write_fifo_dout : unsigned(67 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; - signal write_busy : std_logic; - - alias write_fifo_addr_in is write_fifo_din(31 downto 0); - alias write_fifo_data_in is write_fifo_din(63 downto 32); - alias write_fifo_sel_in is write_fifo_din(67 downto 64); - alias write_fifo_addr_out is write_fifo_dout(31 downto 0); - alias write_fifo_data_out is write_fifo_dout(63 downto 32); - alias write_fifo_sel_out is write_fifo_dout(67 downto 64); - - signal read_cycle : std_logic; - -begin - - - MRDY_O <= '1'; - -read_cyc_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - read_cycle <= '0'; - else - read_cycle <= (dmem_mem_rd_gnt and CYC_O_dmem_rd) - or (dcache_mem_gnt and CYC_O_dcache) - or (icache_mem_gnt and CYC_O_icache); - end if; - end if; - end process; - - CYC_O <= not bout_fifo_empty or read_cycle; - STB_O <= not bout_fifo_empty; - ADDR_O <= bout_fifo_addr_out; - DAT_O <= bout_fifo_data_out; - SEL_O <= bout_fifo_sel_out; - WE_O <= bout_fifo_we_out; - - cpu_imem_rdy <= not icache_busy after 4.5 ns; - busy <= CYC_O_dmem_rd or dcache_busy or (write_busy); - cpu_dmem_rdy <= not busy after 4.5 ns; - -inst_icache : icache - GENERIC MAP - ( - cache_size => icache_size, -- words - line_size => icache_line -- words - ) - PORT MAP - ( - CLK_I => CLK_I, - RST_I => RST_I, - STB_O => STB_O_icache, - CYC_O => CYC_O_icache, - ADDR_O => ADDR_O_icache, - DAT_I => DAT_I, - ACK_I => ACK_I, - SRDY_I => SRDY_I_icache, - ctrl => cop0_ctrl_in.icache, - en => '1', - cpu_en => cpu_imem_en, - cpu_addr => cpu_imem_addr, - cpu_dout => cpu_imem_din, - cpu_busy => icache_busy - ); - - SRDY_I_icache <= bout_rdy and icache_mem_gnt; - -inst_dcache : dcache - GENERIC MAP - ( - cache_size => dcache_size, -- words - line_size => dcache_line -- words - ) - PORT MAP - ( - CLK_I => CLK_I, - RST_I => RST_I, - CYC_O => CYC_O_dcache, - STB_O => STB_O_dcache, - ADDR_O => ADDR_O_dcache, - DAT_I => DAT_I, - ACK_I => ACK_I, - SRDY_I => SRDY_I_dcache, - ctrl => cop0_ctrl_in.dcache, - en => dcached, - cpu_en => dcache_en, - cpu_we => cpu_dmem_we, - cpu_be => cpu_dmem_be, - cpu_addr => cpu_dmem_addr, - cpu_din => cpu_dmem_dout, - cpu_dout => dcache_dout, - cpu_busy => dcache_busy - ); - - SRDY_I_dcache <= bout_rdy and dcache_mem_gnt; - - dcached <= '1' when cpu_dmem_addr(31 downto 29) /= "101" else '0'; - cpu_dmem_din <= dcache_dout when uncached_access = '0' else DAT_I_dmem_rd; - dcache_en <= cpu_dmem_en; -- and not (CYC_O_dmem_rd or write_busy);-- and not busy; - --- Instantiate synchronous FIFO -inst_bout_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 4, - data_width => 69 - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => bout_fifo_we, - re => bout_fifo_re, - fifo_full => bout_fifo_full, - fifo_empty => bout_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => bout_fifo_din, - data_r => bout_fifo_dout - ); - bout_rdy <= not bout_fifo_full; - bout_fifo_re <= not bout_fifo_empty and SRDY_I; - - bout_fifo_we <= STB_O_dmem_wr or STB_O_dmem_rd or STB_O_dcache or STB_O_icache; - - bout_fifo_data_in <= DAT_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '-'); - - bout_fifo_addr_in <= ADDR_O_dmem_wr when dmem_mem_wr_gnt = '1' else - ADDR_O_dmem_rd when dmem_mem_rd_gnt = '1' else - ADDR_O_dcache when dcache_mem_gnt = '1' else - ADDR_O_icache when icache_mem_gnt = '1' else (others => '-'); - - bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else - SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1'); - - bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0'; - --- Instantiate synchronous FIFO -inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 4, - data_width => 68 - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_busy, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - CYC_O_dmem_wr <= not write_fifo_empty; - DAT_O_dmem_wr <= write_fifo_data_out; - ADDR_O_dmem_wr <= write_fifo_addr_out; - SEL_O_dmem_wr <= write_fifo_sel_out; - - write_fifo_data_in <= cpu_dmem_dout; - write_fifo_addr_in <= cpu_dmem_addr; - write_fifo_sel_in <= cpu_dmem_be; - write_fifo_re <= STB_O_dmem_wr; - write_fifo_we <= cpu_dmem_en and not busy and cpu_dmem_we; - -dmem_rd_flags: - process(CLK_I) - begin - if rising_edge(CLK_I) then - uncached_access <= '0'; - if RST_I = '1' then - CYC_O_dmem_rd <= '0'; - else - if ACK_I = '1' and dmem_mem_rd_gnt = '1' then - uncached_access <= '1'; - CYC_O_dmem_rd <= '0'; - end if; - if cpu_dmem_en = '1' and busy = '0' and cpu_dmem_we = '0' then - if dcached = '0' then - CYC_O_dmem_rd <= '1'; - end if; - end if; - end if; - end if; - end process; - -dmem_rd_data: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - DAT_I_dmem_rd <= (others => '0'); - elsif ACK_I = '1' and CYC_O_dmem_rd = '1' then - DAT_I_dmem_rd <= DAT_I; - end if; - end if; - end process; - -dmem_rd_regs: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if cpu_dmem_en = '1' and busy = '0' then - ADDR_O_dmem_rd <= cpu_dmem_addr; - SEL_O_dmem_rd <= cpu_dmem_be; - end if; - end if; - end process; - -bus_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -bus_state: - process(s, CYC_O_icache, CYC_O_dcache, CYC_O_dmem_wr, CYC_O_dmem_rd, bout_rdy, ACK_I) - begin - - icache_mem_gnt <= '0'; - dcache_mem_gnt <= '0'; - dmem_mem_rd_gnt <= '0'; - dmem_mem_wr_gnt <= '0'; - STB_O_dmem_rd <= '0'; - STB_O_dmem_wr <= '0'; - bus_idle <= '0'; - sn <= s; - case s is - when init => - sn <= ready; - when ready => - bus_idle <= '1'; - if CYC_O_dmem_wr = '1' then - sn <= write_bus; - elsif CYC_O_dmem_rd = '1' then - sn <= read_bus; - elsif CYC_O_icache = '1' then - sn <= icache_bus_access; - elsif CYC_O_dcache = '1' then - sn <= dcache_bus_access; - end if; - when icache_bus_access => - icache_mem_gnt <= '1'; - if CYC_O_icache = '0' then - sn <= ready; - end if; - when dcache_bus_access => - dcache_mem_gnt <= '1'; - if CYC_O_dcache = '0' then - sn <= ready; - end if; - when write_bus => - dmem_mem_wr_gnt <= '1'; - if CYC_O_dmem_wr = '1' then - if bout_rdy = '1' then - STB_O_dmem_wr <= '1'; - end if; - else - sn <= ready; - end if; - when read_bus => - dmem_mem_rd_gnt <= '1'; - if bout_rdy = '1' then - STB_O_dmem_rd <= '1'; - sn <= read_finish; - end if; - when read_finish => - dmem_mem_rd_gnt <= '1'; - if ACK_I = '1' then - sn <= ready; - end if; - when others => - sn <= ready; - end case; - - end process; - -bus_timeout_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if bus_idle = '0' then - if bus_timeout_cnt /= 0 then - bus_timeout_cnt <= bus_timeout_cnt - 1; - else - bus_timeout <= '1'; - end if; - else - bus_timeout_cnt <= timeout_cnt_t'high; - bus_timeout <= '0'; - end if; - end if; - end process; - -bus_err: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - cpu_imem_err <= '0'; - cpu_dmem_err <= '0'; - elsif bus_timeout = '1' then - cpu_imem_err <= icache_mem_gnt; - cpu_dmem_err <= dcache_mem_gnt or dmem_mem_wr_gnt or dmem_mem_rd_gnt; - end if; - end if; - end process; - -------------------------------------------------------------------- - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd deleted file mode 100644 index af898eb..0000000 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ /dev/null @@ -1,546 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; -use work.mips_instr.all; - -entity cop is - Generic - ( - icache_size : natural := 2048; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 2048; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - eb : in STD_LOGIC; - int : in unsigned(5 downto 0); - nmi : in STD_LOGIC; - ir_en : in STD_LOGIC; - ir : in word_t; - ctrl_in : in cop0_ctrl_in_t; - ctrl_out : out cop0_ctrl_out_t; - din : in word_t; - dout : out word_t - ); -end cop; - -architecture Behavioral of cop is - - signal epc : word_t; - signal cause : word_t; - signal status : word_t; - signal imem_addr : word_t; - signal imem_addr_we : STD_LOGIC; - signal BadVAddr : word_t; - signal exc_code : unsigned(4 downto 0); - signal test_reg : word_t; - signal test_reg_we : STD_LOGIC; - signal stat_reg_we : STD_LOGIC; - signal eflags_reg_we : STD_LOGIC; - signal epc_reg_we : STD_LOGIC; - signal code_reg_we : STD_LOGIC; - signal ip_reg_we : STD_LOGIC; - signal bd : STD_LOGIC; - signal sw_int : unsigned(1 downto 0); - signal ip : unsigned(7 downto 0); - signal im : unsigned(7 downto 0); - signal status_save : STD_LOGIC; - signal status_rest : STD_LOGIC; - signal eflags : exc_flags_t; - signal EB_reg : STD_LOGIC; - signal icache_info : unsigned(7 downto 0); - signal dcache_info : unsigned(7 downto 0); - signal reg_rptr : reg_ptr_t; - signal reg_wptr : reg_ptr_t; - signal inject_exc : STD_LOGIC; - signal latch_vect_en : STD_LOGIC; - signal int_nmi : STD_LOGIC; - signal nmi_asserted : std_logic; - - type cop_pipe_t is record - opc : opcode_t; - RFE : std_logic; - CO : std_logic; - reg_ptr : reg_ptr_t; - rs : reg_ptr_t; - rd : reg_ptr_t; - rt : reg_ptr_t; - func : func_t; - we : std_logic; - re : std_logic; - cs : std_logic; - end record; - - signal cop_pipe_ID : cop_pipe_t; - signal cop_pipe_EX : cop_pipe_t; - - function eval_int(ip : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in ip'range loop - result := result or ip(i); - end loop; - - return result; - end eval_int; - - type exc_state_t is (exc_idle, exc_pipe_flush, exc_commit, exc_inject, exc_enter, exc_leave, exc_left); - signal exc_state, exc_staten : exc_state_t; - --------------------------------------------------------------------------- -begin - - icache_info <= "00" & to_unsigned(lg2(icache_line), 3) & to_unsigned(lg2(icache_size)-8, 3); - dcache_info <= "00" & to_unsigned(lg2(dcache_line), 3) & to_unsigned(lg2(dcache_size)-8, 3); - cop_pipe_ID.cs <= ir_en; - cop_pipe_ID.opc <= extract_opc(ir); - cop_pipe_ID.rs <= extract_rs(ir); - cop_pipe_ID.rd <= extract_rd(ir); - cop_pipe_ID.rt <= extract_rt(ir); - cop_pipe_ID.func <= extract_func(ir); - cop_pipe_ID.CO <= ir(25); - cop_pipe_ID.re <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "111000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00000")) else '0'; - cop_pipe_ID.we <= cop_pipe_ID.cs when (cop_pipe_ID.opc = "110000" or (cop_pipe_ID.opc = "010000" and cop_pipe_ID.rs = "00100")) else '0'; - cop_pipe_ID.RFE <= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0'; - ctrl_out.EB <= EB_reg xor (status(25) and status(1)); - ctrl_out.user_mode <= status(1); - ctrl_out.exc_inject <= inject_exc or rst; - cop_pipe_ID.reg_ptr <= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt; - - im <= status(15 downto 8); - cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00"; - - eflags.Ov <= ctrl_in.events.alu_ovf or ctrl_in.events.alu_uvf; - eflags.DAdEL <= ctrl_in.events.data_load_err; - eflags.DAdES <= ctrl_in.events.data_store_err; - eflags.IAdEL <= ctrl_in.events.inst_load_err; - eflags.IAdEK <= ctrl_in.events.inst_priv_addr and status(1); - eflags.Sys <= ctrl_in.events.syscall; - eflags.Bp <= ctrl_in.events.break; - eflags.RI <= ctrl_in.events.illegal; - eflags.Int <= ctrl_in.events.int; - --- NMI/RST transition detector -proc_nmi_transition: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - int_nmi <= '0'; - nmi_asserted <= '0'; - elsif latch_vect_en = '1' then - int_nmi <= '0'; - elsif nmi_asserted = '1' then - if nmi = '0' then - nmi_asserted <= '0'; - int_nmi <= '1'; - end if; - elsif nmi = '1' then - nmi_asserted <= '1'; - end if; - end if; - end process; - - --- Main exception FSM -proc_exc_state: - process(exc_state, ctrl_in, cop_pipe_ID) - begin - - ctrl_out.exc_commit <= '0'; - ctrl_out.exc_pending <= '0'; - ctrl_out.exc_exit <= '0'; - epc_reg_we <= '0'; - code_reg_we <= '0'; - status_save <= '0'; - status_rest <= '0'; - inject_exc <= '0'; - imem_addr_we <= '0'; - latch_vect_en <= '0'; - - exc_staten <= exc_state; - - case exc_state is - - when exc_idle => - if cop_pipe_ID.RFE = '1' then - exc_staten <= exc_leave; - ctrl_out.exc_exit <= '1'; - ctrl_out.exc_commit <= '1'; - elsif ctrl_in.exc_req = '1' then - exc_staten <= exc_pipe_flush; - imem_addr_we <= '1'; - end if; - - when exc_pipe_flush => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if ctrl_in.exc_ack = '1' then - exc_staten <= exc_commit; - end if; - - when exc_commit => - latch_vect_en <= '1'; - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if ctrl_in.sdu.ID_stall = '0' then - exc_staten <= exc_inject; - end if; - - when exc_inject => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - code_reg_we <= '1'; - status_save <= '1'; - epc_reg_we <= '1'; - inject_exc <= '1'; - exc_staten <= exc_enter; - - when exc_enter => - ctrl_out.exc_pending <= '1'; - exc_staten <= exc_idle; - - when exc_leave => - exc_staten <= exc_left; - status_rest <= '1'; - ctrl_out.exc_exit <= '1'; - ctrl_out.exc_commit <= '1'; - - when exc_left => - exc_staten <= exc_idle; - - when others => - exc_staten <= exc_idle; - - end case; - end process; - -proc_exc_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_state <= exc_idle; - else - exc_state <= exc_staten; - end if; - end if; - end process; - --- Endian switch sampled at hard reset -sample_endian: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - EB_reg <= eb; - end if; - end if; - end process; - --- Sample imem_addr for later use -exception_last_imem_addr: - process(clk) - begin - if rising_edge(clk) then - if imem_addr_we = '1' then - imem_addr <= ctrl_in.imem_addr; - end if; - end if; - end process; - --- EPC reg and BD-bit write -cop_exception_epc_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bd <= '0'; - epc <= (others => '0'); - elsif epc_reg_we = '1' then - bd <= '0'; - epc <= ctrl_in.epc_mem; - if ctrl_in.bd_wb = '1' then - bd <= '1'; - epc <= ctrl_in.epc_wb; - end if; - end if; - end if; - end process; - --- BadVaddr and exception code write -cop_exception_map: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_code <= (others => '0'); - BadVAddr <= (others => '0'); - elsif code_reg_we = '1' then - if eflags.Ov = '1' then - exc_code <= "01100"; - elsif eflags.Sys = '1' then - exc_code <= "01000"; - elsif eflags.Bp = '1' then - exc_code <= "01001"; - elsif eflags.RI = '1' then - exc_code <= "01010"; - elsif eflags.IAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= imem_addr; - elsif eflags.IAdEK = '1' then - exc_code <= "00100"; - BadVAddr <= imem_addr; - elsif eflags.DAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.DAdES = '1' then - exc_code <= "00101"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.Int = '1' then - exc_code <= "00000"; - end if; - end if; - end if; - end process; - - ctrl_out.icache.inv_addr <= test_reg; - ctrl_out.dcache.inv_addr <= test_reg; - --- Custom I/D-Cache operations: invalidate all/line -cop_cache_op: - process(clk) - begin - if rising_edge(clk) then - ctrl_out.icache.inv_at <= '0'; - ctrl_out.icache.inv_all <= '0'; - ctrl_out.dcache.inv_at <= '0'; - ctrl_out.dcache.inv_all <= '0'; - if cop_pipe_ID.cs = '1' and cop_pipe_ID.CO = '1' then - case cop_pipe_ID.func is - when "100000" => - ctrl_out.icache.inv_all <= '1'; - when "100001" => - ctrl_out.icache.inv_at <= '1'; - when "100010" => - ctrl_out.dcache.inv_all <= '1'; - when "100011" => - ctrl_out.dcache.inv_at <= '1'; - - when others => null; - end case; - end if; - end if; - end process; - --- IP register write and signalling Int to pipeline -cop_ip_reg_write: - process(clk) - variable ip_v : unsigned(7 downto 0); - variable ipm_v : unsigned(7 downto 0); - begin - if rising_edge(clk) then - if rst = '1' then - sw_int <= (others => '0'); - elsif ctrl_in.sdu.WB_nop = '0' then - if ip_reg_we = '1' then - sw_int <= din(9 downto 8); - end if; - end if; - ip_v := (int & sw_int); - ipm_v := ip_v and im; - ip <= ip_v; - ctrl_out.int <= (eval_int(ipm_v) and status(0)); - ctrl_out.NMI <= int_nmi; - end if; - end process; - --- Exception vector dispatch -cop_exc_vector: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - ctrl_out.exc_vec <= X"BFC00000"; - elsif latch_vect_en = '1' then - if ctrl_in.events.nmi = '1' then - ctrl_out.exc_vec <= X"BFC00000"; - else - ctrl_out.exc_vec <= X"80000080"; - if status(22) = '1' then - ctrl_out.exc_vec <= X"BFC00180"; - end if; - end if; - end if; - end if; - end process; - --- Cop pipeline -cop_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cop_pipe_EX.cs <= '0'; - cop_pipe_EX.we <= '0'; - cop_pipe_EX.re <= '0'; - elsif ctrl_in.sdu.stall_all = '0' then - cop_pipe_EX <= cop_pipe_ID; - if cop_pipe_ID.we = '1' then - reg_wptr <= cop_pipe_ID.reg_ptr; - end if; - if cop_pipe_ID.re = '1' then - reg_rptr <= cop_pipe_ID.reg_ptr; - end if; - end if; - end if; - end process; - --- COP Register read -cop_register_read: - process(reg_rptr, BadVAddr, status, cause, epc, dcache_info, icache_info, test_reg) - variable reg : word_t; - begin - - case reg_rptr is - when "01000" => -- BadVAddr - reg := BadVAddr; - - when "01100" => -- Status - reg := status; - - when "01101" => -- Cause - reg := cause; - - when "01110" => -- EPC (Exception Program Counter) - reg := epc; - - when "01111" => -- PRId (Processor Revision Register) - reg := dcache_info & icache_info & X"02" & to_unsigned(REVISION ,8); - - when "11111" => -- test_reg - reg := test_reg; - - when others => - reg := (others => '-'); - - end case; - - dout <= reg after 2 ns; - - end process; - --- COP Register write strobe generation -cop_we_gen: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - elsif ctrl_in.sdu.stall_all = '0' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - if cop_pipe_EX.we = '1' then - - case reg_wptr is - - when "01100" => - stat_reg_we <= '1'; -- not status(1) or status(28); - when "01101" => - ip_reg_we <= '1'; -- not status(1) or status(28); - when "11111" => - test_reg_we <= '1'; -- not status(1) or status(28); - when others => null; - - end case; - - end if; - end if; - end if; - end process; - --- COP Test Register -cop_test_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg <= (others => '0'); - elsif ctrl_in.sdu.WB_nop = '0' then - if test_reg_we = '1' then - test_reg <= din; - end if; - end if; - end if; - end process; - --- COP Status Register -cop_status_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - status <= X"00600000"; - elsif status_save = '1' then - if ctrl_in.events.nmi = '0' then - status(5 downto 4) <= status(3 downto 2); - status(3 downto 2) <= status(1 downto 0); - else - status(22) <= '1'; - end if; - status(1 downto 0) <= "00"; - elsif status_rest = '1' then - status(1 downto 0) <= status(3 downto 2); - status(3 downto 2) <= status(5 downto 4); - elsif ctrl_in.sdu.WB_nop = '0' then - if stat_reg_we = '1' then - if status(1) = '0' then - status(0) <= din(0); -- IEc - status(1) <= din(1); -- KUc - status(2) <= din(2); -- IEp - status(3) <= din(3); -- KUp - status(4) <= din(4); -- IEo - status(5) <= din(5); -- KUo - end if; - status(15 downto 8) <= din(15 downto 8); -- IM - status(22) <= din(22); -- BEV - status(25) <= din(25); -- RE - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd deleted file mode 100644 index b187444..0000000 --- a/lib/CPUs/MIPS/src/core/mips_instr.vhd +++ /dev/null @@ -1,1062 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - --------------------------------------------------------------------------- -package mips_instr is - - function extract_opc(instr : word_t) return opcode_t; - function extract_rs(instr : word_t) return reg_ptr_t; - function extract_rt(instr : word_t) return reg_ptr_t; - function extract_rd(instr : word_t) return reg_ptr_t; - function extract_shamt(instr : word_t) return shamt_t; - function extract_func(instr : word_t) return func_t; - function extract_simm32(instr : word_t) return word_t; - function extract_uimm16(instr : word_t) return word_t; - function extract_jimm32(instr, pc : word_t) return word_t; - function extract_bimm18(instr, pc : word_t) return word_t; - function decode_op(instr : word_t) return op_t; - function ctrl_lines_default return ctrl_lines_t; - function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t; - -end mips_instr; - --------------------------------------------------------------------------- -library work; -use work.mips_types.all; - -package body mips_instr is - - function extract_opc(instr : word_t) return opcode_t is - variable result : opcode_t; - begin - result := instr(31 downto 26); - - return result; - - end extract_opc; - - function extract_rs(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(25 downto 21); - - return result; - - end extract_rs; - - function extract_rt(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(20 downto 16); - - return result; - - end extract_rt; - - function extract_rd(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(15 downto 11); - - return result; - - end extract_rd; - - function extract_shamt(instr : word_t) return shamt_t is - variable result : shamt_t; - begin - result := instr(10 downto 6); - - return result; - - end extract_shamt; - - function extract_func(instr : word_t) return func_t is - variable result : func_t; - begin - result := instr(5 downto 0); - - return result; - - end extract_func; - - function extract_simm32(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => instr(15)) & instr(15 downto 0); - - return result; - - end extract_simm32; - - function extract_uimm16(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => '0') & instr(15 downto 0); - - return result; - - end extract_uimm16; - - function extract_jimm32(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := pc(31 downto 28) & instr(25 downto 0) & "00"; - - return result; - - end extract_jimm32; - - function extract_bimm18(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00"; - - return result; - - end extract_bimm18; - - function decode_op(instr : word_t) return op_t is - variable result : op_t; - variable opc : natural range 0 to 63; - variable func : natural range 0 to 63; - variable rt : natural range 0 to 31; - variable rs : natural range 0 to 31; - - begin - - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - rs := to_integer(extract_rs(instr)); - - result := reserved; - - case opc is - - when 0 => - case func is - - when 0 => - result := op_sll; - - when 2 => - result := op_srl; - - when 3 => - result := op_sra; - - when 4 => - result := op_sllv; - - when 6 => - result := op_srlv; - - when 7 => - result := op_srav; - - when 8 => - result := op_jr; - - when 9 => - result := op_jalr; - - when 12 => - result := op_syscall; - - when 13 => - result := op_break; - - when 16 => - result := op_mfhi; - - when 17 => - result := op_mthi; - - when 18 => - result := op_mflo; - - when 19 => - result := op_mtlo; - - when 24 => - result := op_mult; - - when 25 => - result := op_multu; - - when 26 => - result := op_div; - - when 27 => - result := op_divu; - - when 32 => - result := op_add; - - when 33 => - result := op_addu; - - when 34 => - result := op_sub; - - when 35 => - result := op_subu; - - when 36 => - result := op_and; - - when 37 => - result := op_or; - - when 38 => - result := op_xor; - - when 39 => - result := op_nor; - - when 42 => - result := op_slt; - - when 43 => - result := op_sltu; - - when others => null; -- undef - - end case; - - when 1 => - case rt is - - when 0 => - result := op_bltz; - - when 1 => - result := op_bgez; - - when 16 => - result := op_bltzal; - - when 17 => - result := op_bgezal; - - when others => null; -- undef - - end case; - - when 2 => - result := op_j; - - when 3 => - result := op_jal; - - when 4 => - result := op_beq; - - when 5 => - result := op_bne; - - when 6 => - result := op_blez; - - when 7 => - result := op_bgtz; - - when 8 => - result := op_addi; - - when 9 => - result := op_addiu; - - when 10 => - result := op_slti; - - when 11 => - result := op_sltiu; - - when 12 => - result := op_andi; - - when 13 => - result := op_ori; - - when 14 => - result := op_xori; - - when 15 => - result := op_lui; - - when 16 => - result := op_cop0; - case rs is - when 0 => - result := op_mfc0; - when 2 => - result := op_cfc0; -- illegal - when 4 => - result := op_mtc0; - when 6 => - result := op_ctc0; -- illegal - when 8 => - case rt is - when 0 => - result := op_bcf0; -- illegal - when 1 => - result := op_bct0; -- illegal - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 17 => - result := op_cop1; - case rs is - when 0 => - result := op_mfc1; - when 2 => - result := op_cfc1; - when 4 => - result := op_mtc1; - when 6 => - result := op_ctc1; - when 8 => - case rt is - when 0 => - result := op_bcf1; - when 1 => - result := op_bct1; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 18 => - result := op_cop2; - case rs is - when 0 => - result := op_mfc2; - when 2 => - result := op_cfc2; - when 4 => - result := op_mtc2; - when 6 => - result := op_ctc2; - when 8 => - case rt is - when 0 => - result := op_bcf2; - when 1 => - result := op_bct2; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 19 => - result := op_cop3; - case rs is - when 0 => - result := op_mfc3; - when 2 => - result := op_cfc3; - when 4 => - result := op_mtc3; - when 6 => - result := op_ctc3; - when 8 => - case rt is - when 0 => - result := op_bcf3; - when 1 => - result := op_bct3; - - when others => null; -- undef - end case; - - when others => null; -- undef - - end case; - - when 32 => - result := op_lb; - - when 33 => - result := op_lh; - - when 34 => - result := op_lwl; - - when 35 => - result := op_lw; - - when 36 => - result := op_lbu; - - when 37 => - result := op_lhu; - - when 38 => - result := op_lwr; - - when 40 => - result := op_sb; - - when 41 => - result := op_sh; - - when 42 => - result := op_swl; - - when 43 => - result := op_sw; - - when 46 => - result := op_swr; - - when 48 => - result := op_lwc0; -- illegal - - when 49 => - result := op_lwc1; - - when 50 => - result := op_lwc2; - - when 51 => - result := op_lwc3; - - when 56 => - result := op_swc0; -- illegal - - when 57 => - result := op_swc1; - - when 58 => - result := op_swc2; - - when 59 => - result := op_swc3; - - when others => null; -- undef - - end case; - - return result; - - end decode_op; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.cop_instr_en := '0'; - result.cop_read := '0'; - result.jump := '0'; - result.jump_long := '0'; - result.branch := '0'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.shift_right := '0'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.imm_src := src_imm16; - result.reg_write := '0'; - result.dmem_we := '0'; - result.dmem_en := '0'; - result.wptr_srcsel := wptr_src_imm; - result.reg_link := '0'; - result.shift_offset := "00"; - result.shift_byp := '1'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '1'; - result.word4_en := '0'; - result.word2_en := '0'; - result.align_left := '0'; - result.load_signed := '0'; - result.mul_access := '0'; - result.mul_hilo_we := '0'; - result.mul_start := '0'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - result.mul_hilo_sel := '1'; - result.exc_break := '0'; - result.exc_syscall := '0'; - result.exc_illegal := '0'; - result.except_en := '0'; - result.alu_exc_en := '0'; - - return result; - - end ctrl_lines_default; - - function opcode_ctrl_lines(instr : word_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable opc : integer range 0 to 2**opcode_t'length-1; - variable func : integer range 0 to 2**func_t'length-1; - variable rt : integer range 0 to 2**reg_ptr_t'length-1; - variable rs : integer range 0 to 2**reg_ptr_t'length-1; - begin - - result := ctrl_lines_default; - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - rs := to_integer(extract_rs(instr)); - - case opc is --- SPECIAL - when 0 => - case func is - - -- when op_add => - when 32 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - - -- when op_addu => - when 33 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_and => - when 36 => - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_break => - when 13 => - result.exc_break := '1'; - result.except_en := '1'; - - -- when op_div => - when 26 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '0'; - - -- when op_divu => - when 27 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - - -- when op_jalr => - when 9 => - result.jump_long := '1'; - result.wptr_srcsel := wptr_src_imm; - result.reg_write := '1'; - result.reg_link := '1'; - - -- when op_jr => - when 8 => - result.jump_long := '1'; - - -- when op_mfhi => - when 16 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '1'; - - -- when op_mflo => - when 18 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '0'; - - -- when op_mthi => - when 17 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '1'; - - -- when op_mtlo => - when 19 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '0'; - - -- when op_mult => - when 24 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '1'; - - -- when op_multu => - when 25 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '1'; - - -- when op_or => - when 37 => - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_nor => - when 39 => - result.alu.outsel := alu_nor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sll => - when 0 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_sllv => - when 4 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_slt => - when 42 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sltu => - when 43 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_sra => - when 3 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_srav => - when 7 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_srl => - when 2 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - - -- when op_srlv => - when 6 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - - -- when op_sub => - when 34 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - - -- when op_subu => - when 35 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - -- when op_syscall => - when 12 => - result.exc_syscall := '1'; - result.except_en := '1'; - - -- when op_xor => - when 38 => - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - --- REGIMM - when 1 => - case rt is - - -- when op_bgez => - when 1 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - - -- when op_bgezal => - when 17 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - -- when op_bltz => - when 0 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - - -- when op_bltzal => - when 16 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - --- when COPz => - when 16 | 17 | 18 | 19 => - result.cop_instr_en := '1'; - case rs is - when 0 => -- MFCz - result.cop_read := '1'; - result.reg_write := '1'; - when 2 => -- CFCz - result.cop_read := '1'; - result.reg_write := '1'; - - when others => null; -- undef - - end case; - - --- when op_addi => - when 8 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addiu => - when 9 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_andi => - when 12 => - result.imm_src := src_imm16; - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_beq => - when 4 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - --- when op_bgtz => - when 7 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '1'; - --- when op_blez => - when 6 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '0'; - --- when op_bne => - when 5 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '1'; - --- when op_j => - when 2 => - result.jump := '1'; - --- when op_jal => - when 3 => - result.jump := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_lb => - when 32 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '1'; - result.word4_en := '1'; - --- when op_lbu => - when 36 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '0'; - result.word4_en := '1'; - --- when op_lh => - when 33 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '1'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lhu => - when 37 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lui => - when 15 => - result.imm_src := src_imm16_high; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.alu.outsel := alu_adder; - result.reg_write := '1'; - result.alu.add := '1'; - --- when op_lw => - when 35 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.except_en := '1'; - --- when op_lwcz => - when 48 | 49 | 50 | 51 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.except_en := '1'; - result.cop_instr_en := '1'; - --- when op_lwl => - when 34 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - result.align_left := '1'; - --- when op_lwr => - when 38 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "00"; - result.align_left := '0'; - --- when op_ori => - when 13 => - result.imm_src := src_imm16; - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_sb => - when 40 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word4_en := '1'; - --- when op_sh => - when 41 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_slti => - when 10 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sltiu => - when 11 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sw => - when 43 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - --- when op_swcz => - when 56 | 57 | 58 | 59 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - result.cop_instr_en := '1'; - result.cop_read := '1'; - --- when op_swl => - when 42 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - --- when op_swr => - when 46 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.align_left := '1'; - --- when op_xori => - when 14 => - result.imm_src := src_imm16; - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end opcode_ctrl_lines; - -end mips_instr; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- - diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd deleted file mode 100644 index efce36b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd +++ /dev/null @@ -1,454 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - subtype pprod_t is unsigned (39 downto 0); - subtype prod_t is unsigned (63 downto 0); - subtype byte_t is unsigned (7 downto 0); - - type pprod_array_t is array (natural range <>) of pprod_t; - type word_array_t is array (natural range <>) of word_t; - type byte_array_t is array (natural range <>) of byte_t; - - signal pprod : pprod_array_t(0 to 3); - signal sign1 : std_logic; - signal sign2 : std_logic; - signal s1_r : std_logic; - signal s2_r : std_logic; - signal sr_r : std_logic; - signal cy : unsigned (3 downto 0); - signal mul_start : std_logic; - signal mul_en : std_logic; - signal sum_en : std_logic; - signal pre_sum_vld : std_logic; - signal pp_reg : unsigned (63 downto 8); - signal pre_const : word_array_t(0 to 1); - signal result : prod_t; - signal add_op1 : unsigned (39 downto 0); - signal add_op2 : unsigned (39 downto 0); - signal add_res : unsigned (39 downto 0); - signal ppadd_op1 : word_array_t(0 to 3); - signal ppadd_op2 : word_array_t(0 to 3); - signal ppadd_res : word_array_t(0 to 3); - signal ppadd_cyi : unsigned (3 downto 0); - signal ppadd_cyo : unsigned (3 downto 0); - - signal pp_op1_r : word_t; - signal pp_op1 : word_t; - signal pp_op2 : word_t; - signal pp_op2_r : byte_array_t(0 to 3); - signal bsy : std_logic; - - signal div_add_res : unsigned (32 downto 0); - signal div_add_op1 : unsigned (32 downto 0); - signal div_add_op2 : unsigned (32 downto 0); - signal div_add_cyi : std_logic; - signal div_qbit : std_logic; - signal div_start : std_logic; - signal div_en : std_logic; - - signal div_A : unsigned (32 downto 0); - signal div_M : unsigned (32 downto 0); - signal div_M_n : unsigned (32 downto 0); - signal div_Q : word_t; - - type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3); - signal s, sn : md_state_t; - signal cycle_cnt : natural range 0 to 31; - signal cycle_cnt_preset : natural range 0 to 31; - signal cycle_cnt_load : std_logic; - signal div_fin_en : unsigned (2 downto 0); - --------------------------------------------------------------------------- -begin --- 9A0CD0570B88D78 - - busy <= bsy; - - sign1 <= din_hi(din_hi'left) and s_un; - sign2 <= din_lo(din_lo'left) and s_un; - pp_op1 <= not din_hi when sign1 = '1' else din_hi; - pp_op2 <= not din_lo when sign2 = '1' else din_lo; - --------------------------------------------------------------------------- -md_state: - process(s, start, mul_divn, cycle_cnt) - begin - - bsy <= '1'; - cycle_cnt_load <= '0'; - cycle_cnt_preset <= 7; - - mul_en <= '0'; - div_en <= '0'; - sum_en <= '0'; - pre_sum_vld <= '0'; - mul_start <= '0'; - div_start <= '0'; - div_fin_en <= "000"; - sn <= s; - case s is - when md_rdy => - bsy <= '0'; - if start = '1' then - if mul_divn = '1' then - sn <= mul_pre1; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 7; - mul_start <= '1'; - else - sn <= div_process; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 31; - div_start <= '1'; - end if; - end if; - when mul_pre1 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pre2; - when mul_pre2 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pp; - when mul_pp => - mul_en <= '1'; - if cycle_cnt = 0 then - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 3; - sn <= mul_sum; - end if; - when mul_sum => - sum_en <= '1'; - if cycle_cnt = 0 then - bsy <= '0'; - sn <= md_rdy; - end if; - when div_process => - div_en <= '1'; - if cycle_cnt = 0 then - sn <= div_post1; - end if; - when div_post1 => - div_fin_en <= "001"; - sn <= div_post2; - when div_post2 => - div_fin_en <= "010"; - sn <= div_post3; - when div_post3 => - div_fin_en <= "100"; - sn <= md_rdy; - bsy <= '0'; - when others => - sn <= md_rdy; - end case; - - end process; - -md_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= md_rdy; - else - s <= sn; - end if; - end if; - end process; - -md_cycle_cnt: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cycle_cnt <= 0; - elsif cycle_cnt_load = '1' then - cycle_cnt <= cycle_cnt_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - end if; - end if; - end process; - -proc_out_reg: - process(hilo_sel, result) - begin - if hilo_sel = '1' then - dout <= result(63 downto 32); - else - dout <= result(31 downto 0); - end if; - end process; - -proc_in_reg: - process(clk) - variable pre_cond : unsigned(1 downto 0); - begin - if rising_edge(clk) then - if mul_start = '1' or div_start = '1' then - pp_op1_r <= pp_op1; - pre_const(0) <= (others => '0'); - pre_const(1) <= (others => '0'); - pre_cond := (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un); - s1_r <= pre_cond(1); - s2_r <= pre_cond(0); - sr_r <= pre_cond(0) xor pre_cond(1); - case pre_cond is - when "01" => - pre_const(0) <= din_hi; - pre_const(1) <= X"FFFF_FFFF"; - when "10" => - pre_const(0) <= X"0000_0000"; - pre_const(1) <= X"FFFF_FFFF"; - when "11" => - pre_const(0) <= not din_hi; - pre_const(1) <= X"0000_0001"; - when others => null; - end case; - elsif pre_sum_vld = '1' then - pre_const(0) <= pre_const(1); - end if; - end if; - end process; - -proc_mul_sr: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - for i in 0 to 3 loop - cy(i) <= '0'; - pprod(i) <= ppadd_res(i) & X"00"; - end loop; - elsif mul_en = '1' then - for i in 0 to 3 loop - cy(i) <= ppadd_cyo(i); - pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1); - end loop; - elsif sum_en = '1' then - for i in 1 to 3 loop - pprod(i-1) <= pprod(i); - end loop; - end if; - end if; - end process; - -gen_mul32x8pp: - for i in 0 to 3 generate - begin - - pp_adder_mux: - process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i)) - variable v2 : unsigned(7 downto 0); - begin - ppadd_cyi(i) <= '0'; - ppadd_op1(i) <= (others => '0'); - if mul_start = '1' then - ppadd_op2(i) <= (others => '0'); - v2 := pp_op2(8*(i+1)-1 downto 8*i); - if v2(0) = '1' then - ppadd_cyi(i) <= sign1; - ppadd_op1(i) <= pp_op1; - end if; - else - ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9); - v2 := pp_op2_r(i); - if v2(0) = '1' then - ppadd_cyi(i) <= s1_r; - ppadd_op1(i) <= pp_op1_r; - end if; - end if; - end process; - - pp_adder: - process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i)) - variable sum_pp : unsigned(33 downto 0); - begin - sum_pp := ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i)); - ppadd_res(i) <= sum_pp(sum_pp'left-1 downto 1); - ppadd_cyo(i) <= sum_pp(sum_pp'left); - end process; - - proc_mul_ctrl: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1); - elsif mul_en = '1' then - pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1); - end if; - end if; - end process; - - end generate; - -comb_mul_adder: - process(add_op1, add_op2) - variable sum_mul : unsigned(39 downto 0); - begin - sum_mul := (add_op1) + (add_op2); - add_res <= sum_mul(sum_mul'left downto 0); - end process; - -comb_mul_adder_mux: - process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r) - variable s_ext : std_logic; - begin - if pre_sum_vld = '1' then - add_op1 <= pp_reg(63 downto 24); - add_op2 <= pre_const(0) & X"00"; - else - s_ext := pp_reg(63) and sr_r; - add_op1 <= (7 downto 0 => s_ext) & pp_reg(63 downto 32); - add_op2 <= pprod(0); - end if; - end process; - -comb_mul: - process(clk) - variable tmp : prod_t; - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_reg <= (others => '0'); - elsif pre_sum_vld = '1' then - pp_reg <= add_res & X"0000"; - elsif sum_en = '1' then - tmp := add_res & pp_reg(31 downto 8); - pp_reg <= tmp(63 downto 8); - result <= tmp; - if sr_r = '1' then - result <= not tmp; - end if; - elsif div_fin_en(1) = '1' then - result(63 downto 32) <= div_A(31 downto 0); - if s1_r = '1' then - result(63 downto 32) <= div_add_res(31 downto 0); - end if; - elsif div_fin_en(2) = '1' then - result(31 downto 0) <= div_Q; - if sr_r = '1' then - result(31 downto 0) <= div_add_res(31 downto 0); - end if; - elsif hilo_we = '1' then - if hilo_sel = '1' then - result(63 downto 32) <= din_hi; - else - result(31 downto 0) <= din_hi; - end if; - end if; - end if; - end process; - -div_adder: - process(div_add_op1, div_add_op2, div_add_cyi) - variable sum_div : unsigned(33 downto 0); - begin - sum_div := (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi); - div_add_res <= sum_div(sum_div'left downto 1); - end process; - -div_adder_mux: - process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n) - begin - - div_add_cyi <= s2_r xor div_qbit; - div_add_op1 <= div_A(31 downto 0) & div_Q(31); - div_add_op2 <= (others => '0'); - if div_start = '1' then - div_add_op1 <= '0' & pp_op1; - div_add_cyi <= sign1; - elsif div_en = '1' then - div_add_op2 <= div_M; - if div_qbit = '1' then - div_add_op2 <= div_M_n; - end if; - elsif div_fin_en(0) = '1' then - div_add_op2 <= div_M; - div_add_cyi <= s2_r; - div_add_op1 <= '0' & div_A(31 downto 0); - elsif div_fin_en(1) = '1' then - div_add_cyi <= s1_r; - div_add_op1 <= '0' & not div_A(31 downto 0); - elsif div_fin_en(2) = '1' then - div_add_cyi <= sr_r; - div_add_op1 <= '0' & not div_Q; - end if; - end process; - -divide: - process(clk) - variable quo : std_logic; - begin - if rising_edge(clk) then - if div_start = '1' then - div_qbit <= '1'; - div_Q <= div_add_res(31 downto 0); - div_A <= (others => '0'); - if sign2 = '1' then - div_M_n <= '1' & din_lo; - div_M <= '0' & not din_lo; - else - div_M_n <= '1' & not din_lo; - div_M <= '0' & din_lo; - end if; - elsif div_en = '1' then - div_qbit <= not div_add_res(32); - div_A <= div_add_res(32 downto 0); - div_Q <= div_Q(30 downto 0) & not div_add_res(32); - elsif div_fin_en(0) = '1' then - if div_A(32) = '1' then - div_A <= '0' & div_add_res(31 downto 0); - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd deleted file mode 100644 index 2cc39e8..0000000 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ /dev/null @@ -1,851 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The pipeline --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - imem_err : in STD_LOGIC; - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_err : in STD_LOGIC; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_we : out STD_LOGIC; - dmem_be : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t; - cop_ir : out word_t; - cop_ir_en : out STD_LOGIC; - cop_din : in word_t; - cop_dout : out word_t; - c0_ctrl_out : out cop0_ctrl_in_t; - c0_ctrl_in : in cop0_ctrl_out_t - - ); -end pipeline; - -architecture Behavioral of pipeline is - --------------------------------------------------------------------------- - COMPONENT reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT shifter is - Generic - ( - data_width : integer - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT alu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT bcu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - signal ID_stage : ID_t; - signal EX_stage : EX_t; - signal MEM_stage : MEM_t; - signal WB_stage : WB_t; - signal clk_2, clk_1 : STD_LOGIC; - signal hdu : hdu_t; - signal sdu : sdu_t; - signal reg_a : word_t; - signal reg_b : word_t; - signal branch_ce : STD_LOGIC; - signal cpu_run : STD_LOGIC; - signal alu_result : word_t; - signal mul_result : word_t; - signal mul_busy : STD_LOGIC; - signal EX_events_instr : event_t; - signal EX_events_alu : event_t; - signal EX_events_mem : event_t; - signal EX_events : event_t; - signal MEM_events : event_t; - signal bcu_op_a : word_t; - signal bcu_op_b : word_t; - signal bcu_flags : bcu_flags_t; - signal vaddr : word_t; - signal dmem_src : word_t; - signal stage_rst : unsigned(3 downto 0); - signal pipe_rst : STD_LOGIC; - - signal pc : pc_t; - --------------------------------------------------------------------------- -begin - - clk_1 <= clk; - clk_2 <= not clk; - cpu_run <= ce; - - -- Stall Detection Unit --------------------------------------------------- - sdu.ID_nop <= sdu.imem_dep or c0_ctrl_in.exc_pending or ID_stage.exc or EX_stage.exc or MEM_stage.exc; - sdu.EX_nop <= sdu.mul_dep or ID_stage.nop or ID_stage.exc; - sdu.MEM_nop <= EX_stage.nop or EX_stage.exc; - sdu.WB_nop <= sdu.dmem_dep or MEM_stage.nop; - - sdu.stall_all <= sdu.dmem_dep; - sdu.ID_stall <= sdu.stall_all or sdu.imem_dep or sdu.mul_dep or c0_ctrl_in.exc_exit; - sdu.EX_stall <= sdu.stall_all; - sdu.MEM_stall <= sdu.stall_all; - sdu.WB_stall <= '0'; - - sdu.mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); - sdu.imem_dep <= not imem_rdy; - sdu.dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; - --------------------------------------------------------------------------- - imem_en <= cpu_run and not (sdu.mul_dep or sdu.dmem_dep or c0_ctrl_in.exc_commit); - --------------------------------------------------------------------------- --- Coprocessor assignments --------------------------------------------------------------------------- - c0_ctrl_out.bd_wb <= WB_stage.bd; - c0_ctrl_out.epc_mem <= MEM_stage.pcn; - c0_ctrl_out.epc_wb <= MEM_stage.epc; - c0_ctrl_out.imem_addr <= EX_stage.epc; - c0_ctrl_out.dmem_addr <= MEM_stage.va; - c0_ctrl_out.sdu <= sdu; - c0_ctrl_out.events <= WB_stage.events; - c0_ctrl_out.exc_req <= MEM_stage.exc; - c0_ctrl_out.exc_ack <= WB_stage.exc; - cop_ir <= ID_stage.IR; - cop_ir_en <= ID_stage.ctrl.cop_instr_en; - cop_dout <= dmem_din when MEM_stage.ctrl.dmem_en = '1' else MEM_stage.ex_result; - --------------------------------------------------------------------------- --- Muldiv --------------------------------------------------------------------------- -inst_muldiv: muldiv - PORT MAP - ( - rst => rst, - clk => clk, - hilo_we => EX_stage.ctrl.mul_hilo_we, - din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b, - mul_divn => EX_stage.ctrl.mul_mul_divn, - start => EX_stage.ctrl.mul_start, - s_un => EX_stage.ctrl.mul_s_un, - hilo_sel => EX_stage.ctrl.mul_hilo_sel, - busy => mul_busy, - dout => mul_result - ); - --------------------------------------------------------------------------- --- IF stage --------------------------------------------------------------------------- - imem_addr <= pc.curr; - - pipe_rst <= stage_rst(0); - -proc_stage_reset: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - stage_rst <= (others => '1'); - else - stage_rst <= stage_rst(stage_rst'left-1 downto 0) & '0'; - end if; - end if; - end process; - -proc_stage_pc: - process(pc) - begin - if pc.branch_take = '1' then - pc.curr <= pc.pc_branch after 2 ns; - else - pc.curr <= pc.nxt after 2 ns; - end if; - end process; - -proc_stage_pc_branch: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.ID_stall = '0' then - pc.pc_branch <= pc.curr + ID_stage.bimm18; - end if; - end if; - end process; - -proc_stage_branch_ce: - process(clk_1) - begin - if rising_edge(clk_1) then - if pipe_rst = '1' then - branch_ce <= '1'; - else - branch_ce <= c0_ctrl_in.exc_pending; - if sdu.ID_stall = '0' and c0_ctrl_in.exc_inject = '0' then - branch_ce <= '1'; - end if; - end if; - end if; - end process; - -proc_stage_pc_next: - process(clk_1) - begin - if rising_edge(clk_1) then - if c0_ctrl_in.exc_inject = '1' then - pc.nxt <= c0_ctrl_in.exc_vec; - elsif sdu.ID_stall = '0' then - pc.last <= pc.curr; - if ID_stage.ctrl.jump = '1' then - pc.nxt <= ID_stage.jimm32; - elsif ID_stage.ctrl.jump_long = '1' then - pc.nxt <= ID_stage.reg_a; - else - pc.nxt <= pc.curr + 4; - end if; - end if; - end if; - end process; - -proc_stage_branch: - process(clk_2) - begin - if rising_edge(clk_2) and branch_ce = '1' then - pc.branch_take <= '0'; - if EX_stage.ctrl.branch = '1' then - - case EX_stage.ctrl.bc_src is - - when bc_eq_ne => - pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.eq; - - when bc_lez_gtz => - pc.branch_take <= EX_stage.ctrl.bc_not xor (bcu_flags.eq or bcu_flags.ltz); - - when bc_ltz_gez => - pc.branch_take <= EX_stage.ctrl.bc_not xor bcu_flags.ltz; - - when others => null; - end case; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ID stage --------------------------------------------------------------------------- - ID_stage.IR <= to_01(imem_data); - ID_stage.pcn <= pc.curr; - ID_stage.op <= decode_op(ID_stage.IR); - ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); - ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); - ID_stage.shamt <= extract_shamt(ID_stage.IR); - ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); - ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); - ID_stage.ctrl <= opcode_ctrl_lines(ID_stage.IR) when sdu.ID_nop = '0' else ctrl_lines_default; - ID_stage.reg_write <= ID_stage.ctrl.reg_write; - ID_stage.epc <= pc.last; - ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works - ID_stage.nop <= sdu.ID_nop; - -proc_ID_except: - process(ID_stage, c0_ctrl_in, pc) - begin - ID_stage.events <= events_clr; - ID_stage.events.inst_load_err <= not c0_ctrl_in.exc_pending and (pc.nxt(1) or pc.nxt(0)); - ID_stage.events.inst_priv_addr <= not c0_ctrl_in.exc_pending and (pc.nxt(word_t'left) and c0_ctrl_in.user_mode); - end process; - -proc_stage_hdu: - process(ID_stage, EX_stage, MEM_stage, WB_stage) - variable read_a, read_b : boolean; - variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; - variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; - variable reg_ptr_a : reg_ptr_t; - variable reg_ptr_b : reg_ptr_t; - begin - - reg_ptr_a := ID_stage.reg_a_rptr; - reg_ptr_b := ID_stage.reg_b_rptr; - raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - - hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; - hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; - hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; - hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; - hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; - hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; - - end process; - -proc_stage_fwd_a: - process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_a; - if hdu.alu_fwd_a_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_a_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_a_wb then - data := WB_stage.data; - end if; - ID_stage.reg_a <= to_01(data) after 2 ns; - end process; - -proc_stage_fwd_b: - process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_b; - if hdu.alu_fwd_b_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_b_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_b_wb then - data := WB_stage.data; - end if; - ID_stage.reg_b <= to_01(data) after 2 ns; - end process; - -proc_imm_mux: - process(ID_stage) - variable data : word_t; - begin - data := extract_uimm16(ID_stage.IR); - - case ID_stage.ctrl.imm_src is - - when src_imm32 => - data := extract_simm32(ID_stage.IR); - - when src_imm16 => - data := extract_uimm16(ID_stage.IR); - - when src_imm16_high => - data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); - - when others => null; - - end case; - - ID_stage.imm <= data after 2 ns; - - end process; - --------------------------------------------------------------------------- -inst_reg_dual: reg_dual - GENERIC MAP - ( - addr_width => reg_ptr_t'length, - data_width => word_t'length - ) - PORT MAP - ( - clk_w => clk_1, - we => WB_stage.wreg_we, - en => '1', - wptr => WB_stage.reg_wptr, - din => WB_stage.data, - rptr_a => ID_stage.reg_a_rptr, - rptr_b => ID_stage.reg_b_rptr, - dout_a => reg_a, - dout_b => reg_b - ); - --------------------------------------------------------------------------- --- EX stage --------------------------------------------------------------------------- - EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); - EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; - -proc_stage_ID_EX_1: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(1) = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - EX_stage.epc <= (others => '0'); - EX_stage.pcn <= (others => '0'); - EX_stage.events_in <= events_clr; - elsif sdu.EX_stall = '0' then - EX_stage.reg_a <= ID_stage.reg_a; - EX_stage.reg_b <= ID_stage.reg_b; - EX_stage.events_in <= ID_stage.events; - EX_stage.op <= ID_stage.op; - EX_stage.ctrl <= ID_stage.ctrl; - EX_stage.reg_write <= ID_stage.reg_write; - EX_stage.nop <= sdu.EX_nop; - EX_stage.IR <= ID_stage.IR; - EX_stage.pcn <= ID_stage.pcn; - EX_stage.epc <= ID_stage.epc; - if sdu.EX_nop = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - end if; - end if; - end if; - end process; - -proc_stage_EX_instr_except: - process(EX_stage) - begin - EX_events_instr <= events_clr; - EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal; - EX_events_instr.break <= EX_stage.ctrl.exc_break; - EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall; - end process; - -proc_stage_EX_alu_except: - process(EX_stage) - begin - EX_events_alu <= events_clr; - if EX_stage.ctrl.alu_exc_en = '1' then - if EX_stage.alu_flags.ovf = '1' then - EX_events_alu.alu_ovf <= '1'; - end if; - if EX_stage.alu_flags.uvf = '1' then - EX_events_alu.alu_uvf <= '1'; - end if; - end if; - end process; - - vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR); - -proc_stage_EX_mem_except: - process(clk_1) - begin - if rising_edge(clk_1) then - if pipe_rst = '1' then - dmem_en <= '0'; - elsif sdu.EX_stall = '0' then - EX_events_mem <= events_clr; - dmem_en <= '0'; - if ID_stage.ctrl.dmem_en = '1' then - dmem_en <= '1'; - if ID_stage.ctrl.except_en = '1' then - if ID_stage.ctrl.word2_en = '1' then - if vaddr(0) = '1' then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - elsif vaddr(1 downto 0) /= "00" then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - end if; - end if; - end if; - end if; - end process; - -proc_stage_DMEM_ADDR: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.EX_stall = '0' then - EX_stage.va <= vaddr; - if c0_ctrl_in.EB = '1' then - if ID_stage.ctrl.word2_en = '0' then - EX_stage.pa_off <= not vaddr(1 downto 0); - else - EX_stage.pa_off <= not vaddr(1) & vaddr(0); - end if; - else - EX_stage.pa_off <= vaddr(1 downto 0); - end if; - end if; - end if; - end process; - dmem_src <= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b; - dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns; - dmem_we <= EX_stage.ctrl.dmem_we; - dmem_dout <= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; - dmem_addr <= EX_stage.va; - EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in; - EX_stage.exc <= event_is_active(EX_stage.events); - --------------------------------------------------------------------------- -proc_wptr_mux: - process(EX_stage) - variable opclass : opcode_t; - variable reg_wptr : reg_ptr_t; - begin - - opclass := extract_opc(EX_stage.IR); - case opclass is - when "000000" => - reg_wptr := extract_rd(EX_stage.IR); - when others => - reg_wptr := extract_rt(EX_stage.IR); - end case; - - EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; - if reg_wptr = "00000" then - EX_stage.wreg_we <= '0' after 1 ns; - end if; - - EX_stage.reg_wptr <= reg_wptr after 1 ns; - case EX_stage.ctrl.wptr_srcsel is - when wptr_src_imm => - EX_stage.reg_wptr <= reg_wptr after 1 ns; - - when wptr_src_const => - EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; - EX_stage.wreg_we <= '1' after 1 ns; - - when others => null; - end case; - - end process; - --------------------------------------------------------------------------- -proc_stage_bcu_op: - process(clk_1) - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - bcu_op_a <= ID_stage.reg_a; - bcu_op_b <= ID_stage.reg_b; - end if; - end process; - -EX_stage.alu_op1 <= EX_stage.reg_a; - -alu_op2_mux: - process(clk_1) - variable data : word_t; - begin - - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_b; - - case ID_stage.ctrl.alu.op2_src is - - when alu_src_reg => - data := ID_stage.reg_b; - - when alu_src_imm => - data := ID_stage.imm; - - when others => null; - - end case; - - EX_stage.alu_op2 <= data; - end if; - - end process; - -shifter_sa_mux: - process(clk_1) - variable data : shamt_t; - variable data_inv : shamt_t; - - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_a(4 downto 0); - case ID_stage.ctrl.shamt2_srcsel is - - when sa_src_reg => - data := ID_stage.reg_a(4 downto 0); - - when sa_src_imm => - data := ID_stage.shamt; - - when others => null; - - end case; - data_inv := not data + 1; - if ID_stage.ctrl.alu.shift_right = '0' then - EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; - else - EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; - end if; - EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; - EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; - EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; - end if; - - end process; - --------------------------------------------------------------------------- -inst_shifter: shifter - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b, - dout => EX_stage.alu_op2_s - ); - -inst_alu: alu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => EX_stage.alu_op1, - op2_in => EX_stage.alu_op2, - op2_shifted => EX_stage.alu_op2_s, - ctrl => EX_stage.ctrl.alu, - result => alu_result, - flags => EX_stage.alu_flags - ); - -inst_bcu: bcu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => bcu_op_a, - op2_in => bcu_op_b, - flags => bcu_flags - ); - --------------------------------------------------------------------------- --- MEM stage --------------------------------------------------------------------------- -proc_stage_MEM_n: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(2) = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - MEM_stage.pa_off <= (others => '0'); - MEM_stage.events_in <= events_clr; - elsif sdu.MEM_stall = '0' then - MEM_stage.events_in <= EX_stage.events; - MEM_stage.op <= EX_stage.op; - MEM_stage.wreg_we <= EX_stage.wreg_we; - MEM_stage.ctrl <= EX_stage.ctrl; - if EX_stage.ctrl.dmem_en = '1' then - MEM_stage.va <= EX_stage.va; - end if; - MEM_stage.pa_off <= EX_stage.pa_off; - MEM_stage.reg_wptr <= EX_stage.reg_wptr; - MEM_stage.nop <= sdu.MEM_nop; - if MEM_stage.reg_wptr = EX_stage.reg_wptr then - if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then - MEM_stage.ex_result <= MEM_stage.data; - end if; - else - MEM_stage.ex_result <= EX_stage.reg_b; - end if; - if EX_stage.ctrl.cop_instr_en = '1' then - if EX_stage.ctrl.cop_read = '1' then - MEM_stage.ex_result <= cop_din; - end if; - elsif EX_stage.ctrl.dmem_en = '0' then - MEM_stage.ex_result <= EX_stage.result; - end if; - if sdu.MEM_nop = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - else - MEM_stage.pcn <= EX_stage.pcn; - MEM_stage.epc <= EX_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_MEM_mux: - process(MEM_stage, dmem_din) - variable temp1 : word_t; - variable temp2 : word_t; - variable data : word_t; - variable be : unsigned(3 downto 0); - begin - data := MEM_stage.ex_result; - if MEM_stage.ctrl.reg_link = '1' then - data := MEM_stage.epc + 8; - elsif MEM_stage.ctrl.dmem_en = '1' then - temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); - temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); - be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); - if be(0) = '1' then - data(7 downto 0) := temp2(7 downto 0); - end if; - if be(1) = '1' then - data(15 downto 8) := temp2(15 downto 8); - end if; - if be(2) = '1' then - data(23 downto 16) := temp2(23 downto 16); - end if; - if be(3) = '1' then - data(31 downto 24) := temp2(31 downto 24); - end if; - end if; - MEM_stage.data <= data after 1 ns; - - end process; - -proc_stage_MEM_except: - process(MEM_stage, c0_ctrl_in) - begin - MEM_stage.events <= MEM_stage.events_in; - MEM_stage.events.Int <= c0_ctrl_in.int; - MEM_stage.events.NMI <= c0_ctrl_in.NMI; - end process; - - MEM_stage.exc <= event_is_active(MEM_stage.events); - --------------------------------------------------------------------------- --- WB stage --------------------------------------------------------------------------- -proc_stage_WB_p: - process(clk_1) - begin - if rising_edge(clk_1) then - if stage_rst(3) = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '1'; - WB_stage.reg_wptr <= (others => '0'); - WB_stage.data <= (others => '0'); - WB_stage.events <= events_clr; - elsif sdu.WB_stall = '0' then - WB_stage.op <= MEM_stage.op; - WB_stage.wreg_we <= MEM_stage.wreg_we; - WB_stage.reg_wptr <= MEM_stage.reg_wptr; - WB_stage.data <= MEM_stage.data; - WB_stage.exc <= '0'; - if sdu.stall_all = '0' then - WB_stage.exc <= MEM_stage.exc; - if MEM_stage.exc = '1' then - WB_stage.events <= MEM_stage.events; - end if; - end if; - WB_stage.nop <= sdu.WB_nop; - if sdu.WB_nop = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '0'; - else - WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd deleted file mode 100644 index e7b72da..0000000 --- a/lib/CPUs/MIPS/src/core/mips_reg.vhd +++ /dev/null @@ -1,72 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk_w : in STD_LOGIC; - we : in STD_LOGIC; - en : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - - signal reg_mem : mem_t; - -begin - -reg_in: - process(clk_w) - begin - if rising_edge(clk_w) then - if we = '1' and en = '1' then - reg_mem(to_integer(wptr)) <= din; - end if; - end if; - end process; - - dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns; - dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns; - -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd deleted file mode 100644 index 7f047ec..0000000 --- a/lib/CPUs/MIPS/src/core/mips_shifter.vhd +++ /dev/null @@ -1,117 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The shifter unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity shifter is - Generic - ( - data_width : integer := 8 - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); -end shifter; - -architecture Behavioral of shifter is - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 5) of word_t; - - signal rot_data : word_array_t; - signal sa_rnd : unsigned (4 downto 0); - signal fill : std_logic; - - type fill_mask_rom_t is array (0 to 2*data_width-1) of unsigned(data_width-1 downto 0); --------------------------------------------------------------------------- -function gen_fill_mask_rom(data_width : natural) return fill_mask_rom_t is - variable result : fill_mask_rom_t; - begin - result(0) := (data_width-1 downto 0 => '0'); - for i in 1 to data_width-1 loop - result(i) := (data_width-1-i downto 0 => '0') & (i-1 downto 0 => '1'); - end loop; - result(data_width) := (data_width-1 downto 0 => '0'); - for i in 1 to data_width-1 loop - result(data_width+i) := (i-1 downto 0 => '1') & (data_width-1-i downto 0 => '0'); - end loop; - return result; - -end gen_fill_mask_rom; - -function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is - variable result : unsigned(x'range); - constant sa : natural := 2**stage_num; - begin - if en = '1' then - result := x(sa-1 downto 0) & x(x'left downto sa); - else - result := x; - end if; - return result; - -end rot_stage; - - constant fill_mask_rom : fill_mask_rom_t := gen_fill_mask_rom(data_width); - signal fill_mask : unsigned(data_width-1 downto 0); - signal fill_mask_addr : unsigned(5 downto 0); - signal dout_filled : unsigned (data_width-1 downto 0); - --------------------------------------------------------------------------- -begin - - rot_data(0) <= din; - -gen_rotate_right: - for stage in 0 to 4 generate - begin - rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage); - end generate; - - sa_rnd <= shift_ctrl.shamt_rnd; - fill <= shift_ctrl.shift_arith and din(data_width-1); - fill_mask_addr <= shift_ctrl.shift_right & shift_ctrl.shamt_nrm; - fill_mask <= fill_mask_rom(to_integer(fill_mask_addr)); - -proc_fill_neu: - process(fill_mask, fill, rot_data(5)) - begin - if fill = '1' then - dout_filled <= rot_data(5) or fill_mask; - else - dout_filled <= rot_data(5) and not fill_mask; - end if; - end process; - - dout <= dout_filled after 5 ns; - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd deleted file mode 100644 index 1ebee86..0000000 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ /dev/null @@ -1,305 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_top is - Generic - ( - icache_size : natural := 8192; -- words - icache_line : natural := 8; -- words - dcache_size : natural := 4096; -- words - dcache_line : natural := 8 -- words - ); - Port - ( - debug : out unsigned(1 downto 0); - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - ); - -end mips_top; - -architecture rtl of mips_top is - --------------------------------------------------------------------------- --- Pipeline --------------------------------------------------------------------------- - COMPONENT pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - imem_err : in STD_LOGIC; - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_err : in STD_LOGIC; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_we : out STD_LOGIC; - dmem_be : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t; - cop_ir : out word_t; - cop_ir_en : out STD_LOGIC; - cop_din : in word_t; - cop_dout : out word_t; - c0_ctrl_out : out cop0_ctrl_in_t; - c0_ctrl_in : in cop0_ctrl_out_t - ); - END COMPONENT; - signal imem_err : std_logic; - signal imem_rdy : std_logic; - signal imem_en : std_logic; - signal imem_addr : word_t; - signal imem_din : word_t; - signal dmem_err : std_logic; - signal dmem_rdy : std_logic; - signal dmem_en : std_logic; - signal dmem_we : std_logic; - signal dmem_addr : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_be : unsigned(3 downto 0); - - signal biu_rst : STD_LOGIC; - signal cpu_rst : STD_LOGIC; - signal cpu_run : STD_LOGIC; - - signal pipe_cop_ir : word_t; - signal pipe_cop_ir_en : STD_LOGIC; - signal pipe_cop_din : word_t; - signal pipe_cop_dout : word_t; - signal pipe_c0_ctrl_out : cop0_ctrl_in_t; - signal pipe_c0_ctrl_in : cop0_ctrl_out_t; - --------------------------------------------------------------------------- --- Coprocessor --------------------------------------------------------------------------- - COMPONENT cop is - GENERIC - ( - icache_size : natural; - icache_line : natural; - dcache_size : natural; - dcache_line : natural - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - nmi : in STD_LOGIC; - eb : in STD_LOGIC; - int : in unsigned (5 downto 0); - ir_en : in STD_LOGIC; - ir : in word_t; - ctrl_in : in cop0_ctrl_in_t; - ctrl_out : out cop0_ctrl_out_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- --- Bus Interface Unit --------------------------------------------------------------------------- - COMPONENT biu - GENERIC - ( - icache_size : natural; - icache_line : natural; - dcache_size : natural; - dcache_line : natural - ); - PORT - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - cop0_ctrl_in : in cop0_ctrl_out_t; - cpu_imem_err : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_err : out STD_LOGIC; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_we : in STD_LOGIC; - cpu_dmem_be : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t - ); - END COMPONENT; - -begin - -------------------------------------------------------------------- - debug(0) <= imem_err; - debug(1) <= dmem_err; - - process(CLK_I) - variable reset_delay : unsigned (31 downto 0); - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - reset_delay := (others => '0'); - biu_rst <= '1'; - cpu_rst <= '1'; - cpu_run <= '0'; - else - reset_delay := reset_delay(reset_delay'left-1 downto 0) & '1'; - if reset_delay(20) = '1' then - biu_rst <= '0'; - end if; - if reset_delay(31) = '1' then - cpu_rst <= '0'; - end if; - if reset_delay(16) = '1' then - cpu_run <= '1'; - end if; - end if; - end if; - end process; - -inst_pipeline: pipeline - PORT MAP - ( - rst => cpu_rst, - clk => CLK_I, - ce => cpu_run, - imem_err => imem_err, - imem_rdy => imem_rdy, - imem_en => imem_en, - imem_addr => imem_addr, - imem_data => imem_din, - dmem_err => dmem_err, - dmem_rdy => dmem_rdy, - dmem_en => dmem_en, - dmem_we => dmem_we, - dmem_be => dmem_be, - dmem_addr => dmem_addr, - dmem_din => dmem_din, - dmem_dout => dmem_dout, - cop_ir => pipe_cop_ir, - cop_ir_en => pipe_cop_ir_en, - cop_din => pipe_cop_din, - cop_dout => pipe_cop_dout, - c0_ctrl_out => pipe_c0_ctrl_out, - c0_ctrl_in => pipe_c0_ctrl_in - ); - -inst_cop: cop - GENERIC MAP - ( - icache_size => icache_size, -- words - icache_line => icache_line, -- words - dcache_size => dcache_size, -- words - dcache_line => dcache_line -- words - ) - PORT MAP - ( - rst => cpu_rst, - clk => CLK_I, - nmi => nmi, - eb => eb, - int => INT, - ir_en => pipe_cop_ir_en, - ir => pipe_cop_ir, - ctrl_in => pipe_c0_ctrl_out, - ctrl_out => pipe_c0_ctrl_in, - dout => pipe_cop_din, - din => pipe_cop_dout - ); - -inst_biu: biu - GENERIC MAP - ( - icache_size => icache_size, -- words - icache_line => icache_line, -- words - dcache_size => dcache_size, -- words - dcache_line => dcache_line -- words - ) - PORT MAP - ( - RST_I => biu_rst, - CLK_I => CLK_I, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - cop0_ctrl_in => pipe_c0_ctrl_in, - cpu_imem_err => imem_err, - cpu_imem_rdy => imem_rdy, - cpu_imem_en => imem_en, - cpu_imem_addr => imem_addr, - cpu_imem_din => imem_din, - cpu_dmem_err => dmem_err, - cpu_dmem_rdy => dmem_rdy, - cpu_dmem_en => dmem_en, - cpu_dmem_we => dmem_we, - cpu_dmem_be => dmem_be, - cpu_dmem_addr => dmem_addr, - cpu_dmem_din => dmem_din, - cpu_dmem_dout => dmem_dout - ); - -end rtl; diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd deleted file mode 100644 index d820a21..0000000 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ /dev/null @@ -1,670 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JIPS --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - --------------------------------------------------------------------------- -package mips_types is - - -- Revision of the CPU - constant REVISION : integer := 12; - constant WORD_WIDTH : integer := 32; - - --Types - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (5 downto 0); - subtype word_t is unsigned (WORD_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (4 downto 0); - subtype shamt_t is unsigned(4 downto 0); - subtype sa_t is natural range 0 to 63; - subtype func_t is unsigned(5 downto 0); - - type op_t is - ( - reserved, - nop, - op_sll, - op_srl, - op_sra, - op_sllv, - op_srlv, - op_srav, - op_jr, - op_jalr, - op_syscall, - op_break, - op_mfhi, - op_mthi, - op_mflo, - op_mtlo, - op_mult, - op_multu, - op_div, - op_divu, - op_add, - op_addu, - op_sub, - op_subu, - op_and, - op_or, - op_xor, - op_nor, - op_slt, - op_sltu, - op_bltz, - op_bgez, - op_bltzal, - op_bgezal, - op_j, - op_jal, - op_beq, - op_bne, - op_blez, - op_bgtz, - op_addi, - op_addiu, - op_slti, - op_sltiu, - op_andi, - op_ori, - op_xori, - op_lui, - op_lb, - op_lh, - op_lwl, - op_lw, - op_lbu, - op_lhu, - op_lwr, - op_sb, - op_sh, - op_swl, - op_sw, - op_swr, - op_cop0, - op_cop1, - op_cop2, - op_cop3, - op_mfc0, - op_cfc0, - op_mtc0, - op_ctc0, - op_bcf0, - op_bct0, - op_mfc1, - op_cfc1, - op_mtc1, - op_ctc1, - op_bcf1, - op_bct1, - op_mfc2, - op_cfc2, - op_mtc2, - op_ctc2, - op_bcf2, - op_bct2, - op_mfc3, - op_cfc3, - op_mtc3, - op_ctc3, - op_bcf3, - op_bct3, - op_lwc0, - op_lwc1, - op_lwc2, - op_lwc3, - op_swc0, - op_swc1, - op_swc2, - op_swc3 - ); - - attribute ENUM_ENCODING : string; - - type imm_src_t is (src_imm32, src_imm16, src_imm16_high); - type sa_src_t is (sa_src_reg, sa_src_imm); - type alu_src1_t is (alu_src_reg); - type alu_src2_t is (alu_src_reg, alu_src_imm); - type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez); - type shift_opsel_t is (shift_sll, shift_srl, shift_sra); - type wptr_src_t is (wptr_src_imm, wptr_src_const); - --- attribute ENUM_ENCODING of itype_t: type is "ONE-HOT"; - - type pc_t is record - curr : word_t; - last : word_t; - nxt : word_t; - pc_branch : word_t; - branch_take : std_logic; - end record; - - type alu_outsel_t is - ( - alu_adder, - alu_shift2, - alu_and, - alu_or, - alu_xor, - alu_nor, - alu_ltu, - alu_lts - ); - - type sdu_t is record - imem_dep : STD_LOGIC; - dmem_dep : STD_LOGIC; - mul_dep : STD_LOGIC; - ID_nop : STD_LOGIC; - EX_nop : STD_LOGIC; - MEM_nop : STD_LOGIC; - WB_nop : STD_LOGIC; - ID_stall : STD_LOGIC; - EX_stall : STD_LOGIC; - MEM_stall : STD_LOGIC; - WB_stall : STD_LOGIC; - stall_all : STD_LOGIC; - end record; - - type hdu_t is record - alu_fwd_a_ex : boolean; - alu_fwd_a_mem : boolean; - alu_fwd_a_wb : boolean; - alu_fwd_b_ex : boolean; - alu_fwd_b_mem : boolean; - alu_fwd_b_wb : boolean; - end record; - - type alu_flags_t is record - c : STD_LOGIC; - uvf : STD_LOGIC; - ovf : STD_LOGIC; - ltu : STD_LOGIC; - lts : STD_LOGIC; - end record; - - type bcu_flags_t is record - eq : STD_LOGIC; - ltz : STD_LOGIC; - end record; - - type event_t is record - NMI : STD_LOGIC; - Int : STD_LOGIC; - data_load_err : STD_LOGIC; - data_store_err : STD_LOGIC; - inst_load_err : STD_LOGIC; - inst_priv_addr : STD_LOGIC; - alu_ovf : STD_LOGIC; - alu_uvf : STD_LOGIC; - syscall : STD_LOGIC; - break : STD_LOGIC; - illegal : STD_LOGIC; - end record; - - type exc_flags_t is record - Int : STD_LOGIC; - DAdEL : STD_LOGIC; - DAdES : STD_LOGIC; - IAdEL : STD_LOGIC; - IAdEK : STD_LOGIC; - Ov : STD_LOGIC; - Sys : STD_LOGIC; - Bp : STD_LOGIC; - RI : STD_LOGIC; - IBE : STD_LOGIC; - DBE : STD_LOGIC; - end record; - - type except_t is record - act : STD_LOGIC; - epc : word_t; - cause : word_t; - end record; - - type cache_ctrl_t is record - inv_addr : word_t; - inv_at : STD_LOGIC; - inv_all : STD_LOGIC; - end record; - - type cop0_ctrl_in_t is record - sdu : sdu_t; - events : event_t; - bd_wb : STD_LOGIC; - epc_mem : word_t; - epc_wb : word_t; - imem_addr : word_t; - dmem_addr : word_t; - exc_req : STD_LOGIC; - exc_ack : STD_LOGIC; - end record; - - type cop0_ctrl_out_t is record - EB : STD_LOGIC; - exc_inject : STD_LOGIC; - exc_commit : STD_LOGIC; - exc_pending : STD_LOGIC; - exc_exit : STD_LOGIC; - user_mode : STD_LOGIC; - NMI : STD_LOGIC; - int : STD_LOGIC; - exc_vec : word_t; - icache : cache_ctrl_t; - dcache : cache_ctrl_t; - end record; - - type alu_ctrl_t is record - outsel : alu_outsel_t; - add : STD_LOGIC; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - op1_src : alu_src1_t; - op2_src : alu_src2_t; - end record; - - type shift_ctrl_t is record - shamt_nrm : shamt_t; - shamt_rnd : shamt_t; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - end record; - - type ctrl_lines_t is record - branch : STD_LOGIC; - jump_long : STD_LOGIC; - jump : STD_LOGIC; - bc_not : STD_LOGIC; - bc_src : bc_src_t; - imm_src : imm_src_t; - alu : alu_ctrl_t; - reg_write : STD_LOGIC; - reg_link : STD_LOGIC; - dmem_we : STD_LOGIC; - dmem_en : STD_LOGIC; - shamt2_srcsel : sa_src_t; - wptr_srcsel : wptr_src_t; - cop_instr_en : STD_LOGIC; - cop_read : STD_LOGIC; - shift_offset : unsigned(1 downto 0); - shift_byp : STD_LOGIC; - byte_en_byp : STD_LOGIC; - sign_ext_byp : STD_LOGIC; - word4_en : STD_LOGIC; - word2_en : STD_LOGIC; - align_left : STD_LOGIC; - load_signed : STD_LOGIC; - mul_access : STD_LOGIC; - mul_hilo_we : STD_LOGIC; - mul_mul_divn : STD_LOGIC; - mul_start : STD_LOGIC; - mul_s_un : STD_LOGIC; - mul_hilo_sel : STD_LOGIC; - exc_break : STD_LOGIC; - exc_syscall : STD_LOGIC; - exc_illegal : STD_LOGIC; - except_en : STD_LOGIC; - alu_exc_en : STD_LOGIC; - end record; - - type ID_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - jimm32 : word_t; - bimm18 : word_t; - imm : word_t; - shamt : shamt_t; - ctrl : ctrl_lines_t; - reg_write : STD_LOGIC; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - reg_a : word_t; - reg_b : word_t; - events : event_t; - end record; - - type EX_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - reg_a : word_t; - reg_b : word_t; - ctrl : ctrl_lines_t; - shift_ctrl : shift_ctrl_t; - alu_op1 : word_t; - alu_op2 : word_t; - alu_op2_s : word_t; - alu_flags : alu_flags_t; - result : word_t; - reg_write : STD_LOGIC; - wreg_we : STD_LOGIC; - reg_wptr : reg_ptr_t; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type MEM_t is record - nop : STD_LOGIC; - exc : std_logic; - op : op_t; - pcn : word_t; - epc : word_t; - ctrl : ctrl_lines_t; - ex_result : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type WB_t is record - nop : STD_LOGIC; - exc : std_logic; - events : event_t; - op : op_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - bd : STD_LOGIC; - end record; - - - type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t; - type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t; - type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t; - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned; - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned; - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t; - function events_clr return event_t; - function event_is_active(e : event_t) return std_logic; - function "or" (a, b : event_t) return event_t; - - function lg2(x : natural) return natural; - function po2(x : natural) return natural; - -end mips_types; - --------------------------------------------------------------------------- -package body mips_types is - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - begin - - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(23 downto 0) & x(31 downto 24); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end store_shift; - --------------------------------------------------------------------------- - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - result := (3 downto 0 => be_src); - if bypass = '0' then - if word2_en = '1' then - case va is - when "00" => - result := "00" & be_src & be_src; - when "10" => - result := be_src & be_src & "00"; - when others => null; - end case; - elsif word4_en = '1' then - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & '0'; - when "10" => - result := '0' & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => null; - end case; - elsif align_left = '1' then - case va is - when "00" => - result := be_src & be_src & be_src & be_src; - when "01" => - result := be_src & be_src & be_src & '0'; - when "10" => - result := be_src & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => null; - end case; - else - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & be_src; - when "10" => - result := '0' & be_src & be_src & be_src; - when "11" => - result := be_src & be_src & be_src & be_src; - when others => null; - end case; - end if; - end if; - - return result; - - end store_be; - --------------------------------------------------------------------------- - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - - begin - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(7 downto 0) & x(31 downto 8); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end load_shift; - --------------------------------------------------------------------------- - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - result := (3 downto 0 => '1'); - if bypass = '0' then - if align_left = '1' then - case va is - when "00" => - result := "1000"; - when "01" => - result := "1100"; - when "10" => - result := "1110"; - when "11" => - result := "1111"; - when others => null; - end case; - else - case va is - when "00" => - result := "1111"; - when "01" => - result := "0111"; - when "10" => - result := "0011"; - when "11" => - result := "0001"; - when others => null; - end case; - end if; - end if; - - return result; - - end load_be; - --------------------------------------------------------------------------- - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is - variable result : word_t; - variable sign : std_logic; - - begin - if bypass = '1' then - result := x; - elsif word2_en = '1' then - sign := signed and x(15); - result := (31 downto 16 => sign) & x(15 downto 0); - else - sign := signed and x(7); - result := (31 downto 8 => sign) & x(7 downto 0); - end if; - - return result; - end load_sign_ext; - --------------------------------------------------------------------------- - function events_clr return event_t is - variable result : event_t; - begin - result.NMI := '0'; - result.Int := '0'; - result.data_load_err := '0'; - result.data_store_err := '0'; - result.inst_load_err := '0'; - result.inst_priv_addr := '0'; - result.alu_ovf := '0'; - result.alu_uvf := '0'; - result.syscall := '0'; - result.break := '0'; - result.illegal := '0'; - - return result; - - end events_clr; - --------------------------------------------------------------------------- - function event_is_active(e : event_t) return std_logic is - variable result : std_logic; - begin - result := '0'; - - result := result or e.NMI; - result := result or e.Int; - result := result or e.data_load_err; - result := result or e.data_store_err; - result := result or e.inst_load_err; - result := result or e.inst_priv_addr; - result := result or e.alu_ovf; - result := result or e.alu_uvf; - result := result or e.syscall; - result := result or e.break; - result := result or e.illegal; - - return result; - - end event_is_active; - --------------------------------------------------------------------------- - function "or" (a, b : event_t) return event_t is - variable result : event_t; - begin - result.NMI := a.NMI or b.NMI; - result.Int := a.Int or b.Int; - result.data_load_err := a.data_load_err or b.data_load_err; - result.data_store_err := a.data_store_err or b.data_store_err; - result.inst_load_err := a.inst_load_err or b.inst_load_err; - result.inst_priv_addr := a.inst_priv_addr or b.inst_priv_addr; - result.alu_ovf := a.alu_ovf or b.alu_ovf; - result.alu_uvf := a.alu_uvf or b.alu_uvf; - result.syscall := a.syscall or b.syscall; - result.break := a.break or b.break; - result.illegal := a.illegal or b.illegal; - - return result; - - end "or"; - --------------------------------------------------------------------------- - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - --------------------------------------------------------------------------- - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - --------------------------------------------------------------------------- -end mips_types; - diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd deleted file mode 100644 index ba364eb..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_muldiv IS -END tb_mips_muldiv; - -ARCHITECTURE behavior OF tb_mips_muldiv IS - - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - s_un : in std_logic; - start : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - signal ENABLE_FAIL_REPORT : boolean := true; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal busy : std_logic; - signal mul_divn : std_logic := '0'; - signal s_un : std_logic := '1'; - signal hilo_we : std_logic := '0'; - signal start : std_logic := '0'; - signal din_hi : word_t := (others => '-'); - signal din_lo : word_t := (others => '-'); - signal dout : word_t; - signal hilo_sel : std_logic := '0'; - signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0'); - signal ref_result : unsigned (2*word_t'length-1 downto 0); - signal ref_hi : unsigned (word_t'length-1 downto 0); - signal rtmp : unsigned (2*word_t'length-1 downto 0); - signal tmp2 : unsigned (word_t'length-1 downto 0); - signal check : std_logic; - - type word_array_t is array (natural range <>) of word_t; - - constant operands : word_array_t(0 to 63) := - ( - X"00000000", - X"00000001", - X"00000010", - X"00000100", - X"00001000", - X"00010000", - X"00100000", - X"01000000", - X"10000000", - X"0000000F", - X"000000FF", - X"00000FFF", - X"0000FFFF", - X"000FFFFF", - X"00FFFFFF", - X"0FFFFFFF", - X"12345678", - X"23456789", - X"7FFFFFFF", - X"80000000", - X"A541B3B9", - X"80000001", - X"80000010", - X"80000100", - X"80001000", - X"80010000", - X"80100000", - X"81000000", - X"87654321", - X"98765432", - X"FFFFFFFF", - X"FFFFFFFE", - X"FFFFFFFD", - X"FFFFFFFB", - X"FFFFFFF7", - X"FFFFFFEF", - X"FFFFFFDF", - X"FFFFFFBF", - X"FFFFFF7F", - X"FFFFFEFF", - X"FFFFFDFF", - X"FFFFFBFF", - X"FFFFF7FF", - X"FFFFEFFF", - X"FFFFDFFF", - X"FFFFBFFF", - X"FFFF7FFF", - X"FFFEFFFF", - X"FFFDFFFF", - X"FFFBFFFF", - X"FFF7FFFF", - X"FFEFFFFF", - X"FFDFFFFF", - X"FFBFFFFF", - X"FF7FFFFF", - X"FEFFFFFF", - X"FDFFFFFF", - X"FBFFFFFF", - X"F7FFFFFF", - X"EFFFFFFF", - X"DFFFFFFF", - X"BFFFFFFF", - X"CFFFFFFF", - X"7FFFFFFF" - ); - -BEGIN - -uut: muldiv - PORT MAP( - rst => rst, - clk => clk, - hilo_we => hilo_we, - din_hi => din_hi, - din_lo => din_lo, - mul_divn => mul_divn, - s_un => s_un, - start => start, - hilo_sel => hilo_sel, - busy => busy, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -REF_GEN: process - begin - if mul_divn = '0' then - wait until rising_edge(clk) and check = '1'; - if s_un = '1' then - rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo)); - wait until rising_edge(clk); - tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32))); - wait until rising_edge(clk); - ref_hi <= tmp2(31 downto 0); - else - rtmp <= md_result(31 downto 0) * din_lo; - wait until rising_edge(clk); - tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32); - wait until rising_edge(clk); - ref_hi <= tmp2(31 downto 0); - end if; - wait until rising_edge(clk); - - if din_lo /= X"00000000" then - if ENABLE_FAIL_REPORT then - assert din_hi = ref_hi report "Error on divison" severity failure; - end if; - end if; - else - wait until rising_edge(clk) and check = '1'; - if s_un = '1' then - ref_result <= unsigned(signed(din_hi) * signed(din_lo)); - else - ref_result <= unsigned(din_hi) * unsigned(din_lo); - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - if ENABLE_FAIL_REPORT then - assert ref_result = md_result report "Error on multiplication" severity failure; - end if; - end if; - - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - - mul_divn <= '0'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - mul_divn <= '1'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - check <= '0'; - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - md_result(31 downto 0) <= dout; - wait until rising_edge(clk); - hilo_sel <= '1'; - wait until rising_edge(clk); - md_result(63 downto 32) <= dout; - check <= '1'; - wait until rising_edge(clk); - check <= '0'; - wait for 8*CLK_PERIOD; - end loop; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd deleted file mode 100644 index 854a2c8..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ /dev/null @@ -1,452 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; -use work.async_types.all; -use work.async_defs.all; - -ENTITY tb_mips_top IS -END tb_mips_top; - -ARCHITECTURE behavior OF tb_mips_top IS - - constant CLK_PERIOD : time := 10 ns; - constant SRAM_ADDR_WIDTH : integer := 17; -- bits - constant FLASH_ADDR_WIDTH : integer := 17; -- bits - - signal debug : unsigned(1 downto 0); - - -- Master - signal nmi : STD_LOGIC := '0'; - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal eb : STD_LOGIC := '1'; - signal ACK_I : STD_LOGIC := '0'; - signal SRDY_I : STD_LOGIC := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal DAT_I : unsigned(31 downto 0) := (others => '0'); - signal DAT_O : unsigned(31 downto 0); - signal WE_O : STD_LOGIC; - signal SEL_O : unsigned(3 downto 0); - signal CYC_O : STD_LOGIC; - signal STB_O : STD_LOGIC; - signal MRDY_O : STD_LOGIC; - signal INT : unsigned (5 downto 0) := (others => '0'); - - -- Slaves - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal DAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal DAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_sram : std_logic; - signal ACK_O_sram : std_logic; - signal SRDY_O_sram : std_logic; - signal DAT_O_sram : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal DAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart : std_logic; - signal ACK_O_uart : std_logic; - signal SRDY_O_uart : std_logic; - signal DAT_O_uart : unsigned(31 downto 0); - - signal flash_cs_n : std_logic; - signal flash_we_n : std_logic; - signal flash_oe_n : std_logic; - signal flash_be_n : unsigned(3 downto 0); - signal sram_cs_n : std_logic; - signal sram_be_n : unsigned(3 downto 0); - signal sram_wr_n : std_logic; - signal sram_oe_n : std_logic; - signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0); - signal sram_d : unsigned(31 downto 0); - signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0); - signal flash_d : unsigned(31 downto 0); - signal flash_page_mode_en : std_logic; - - signal gpo0 : unsigned(31 downto 0); - signal gpo1 : unsigned(31 downto 0); - signal gpi0 : unsigned(31 downto 0) := (others => '0'); - signal gpi1 : unsigned(31 downto 0) := (others => '0'); - - signal int_timer : std_logic; - signal int_uart : std_logic; - signal rx : std_logic := '1'; - signal tx : std_logic; - - type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); - signal mem_area : mem_area_t; - - type word_array_t is array (natural range <>) of unsigned(31 downto 0); - signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1); - signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1); - -BEGIN - ------------------------------------------------------------------- -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------- --- Memory mux ------------------------------------------------------------------- -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - flash_page_mode_en <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - flash_page_mode_en <= '1'; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - mem_area <= mem_uart; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_rom <= '0'; - CYC_I_sram <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart => - CYC_I_uart <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sram => - CYC_I_sram <= CYC_O; - - when others => null; - - end case; - - end process; - - SRDY_I <= SRDY_O_flash or SRDY_O_sram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio; - ACK_I <= ACK_O_flash or ACK_O_sram or ACK_O_rom or ACK_O_uart or ACK_O_gpio; - DAT_I <= DAT_O_sram when CYC_I_sram = '1' else - DAT_O_rom when CYC_I_rom = '1' else - DAT_O_flash when CYC_I_flash = '1' else - DAT_O_uart when CYC_I_uart = '1' else - DAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - - ------------------------------------------------------------------- -uut: entity work.mips_top - GENERIC MAP - ( - icache_size => 1024, -- words - dcache_size => 1024 -- words - ) - PORT MAP - ( - debug => debug, - eb => eb, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I, - SRDY_I => SRDY_I, - ADDR_O => ADDR_O, - DAT_I => DAT_I, - DAT_O => DAT_O, - WE_O => WE_O, - SEL_O => SEL_O, - CYC_O => CYC_O, - STB_O => STB_O, - MRDY_O => MRDY_O, - INT => INT, - nmi => nmi - ); - INT(1) <= int_uart; - INT(5) <= int_timer; - -inst_rom : entity work.rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => DAT_O_rom - ); - -inst_gpio : entity work.gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpo0 => gpo0, - sys_gpo1 => gpo1, - sys_gpi0 => gpi0, - sys_gpi1 => gpi1 - ); - -inst_flash_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => FLASH_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_flash, - page_mode_en => flash_page_mode_en, - async_a => flash_a, - async_d => flash_d, - async_cs => flash_cs_n, - async_wr => flash_we_n, - async_rd => flash_oe_n, - async_be => flash_be_n, - async_rst => open - ); - -inst_sram_port : entity work.async_port_wb - GENERIC MAP - ( - addr_width => SRAM_ADDR_WIDTH, - data_width => 32, - byte_sel_width => 4, - async_timespec => ts_sram - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_sram, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_sram, - SRDY_O => SRDY_O_sram, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_sram, - page_mode_en => '0', - async_a => sram_a, - async_d => sram_d, - async_cs => sram_cs_n, - async_wr => sram_wr_n, - async_rd => sram_oe_n, - async_be => sram_be_n, - async_rst => open - ); - -inst_uart : entity work.uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart, - SRDY_O => SRDY_O_uart, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_O_uart, - INT_O => int_uart, - ser_rx => rx, - ser_tx => tx - ); - ------------------------------------------------------------------- -SRAM_READ: - process(sram_a, sram_cs_n, sram_oe_n, sram_be_n) - begin - sram_d <= (others => 'Z') after 10 ns; - if sram_oe_n = '0' then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns; - end if; - if sram_be_n(1) = '0' then - sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns; - end if; - if sram_be_n(2) = '0' then - sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns; - end if; - if sram_be_n(3) = '0' then - sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns; - end if; - end if; - end if; - end process; - -SRAM_WRITE: - process(sram_wr_n) - begin - if rising_edge(sram_wr_n) then - if sram_cs_n = '0' then - if sram_be_n(0) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0); - end if; - if sram_be_n(1) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8); - end if; - if sram_be_n(2) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16); - end if; - if sram_be_n(3) = '0' then - sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24); - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -FLASH_READ: - process(rst, flash_cs_n, flash_oe_n, flash_a) - type file_t is file of integer; - file load_flash : file_t open read_mode is "lwl.flash.bin"; - variable instr : integer; - variable index : natural; - variable temp : signed(31 downto 0); - begin - if rst = '1' then - index := 0; - while not endfile(load_flash) loop - read(load_flash, instr); - temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); - index := index + 1; - end loop; - else - flash_d <= (others => 'Z') after 25 ns; - index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2)); - if flash_oe_n = '0' then - if flash_cs_n = '0' then - if flash_be_n(0) = '0' then - flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after 25 ns; - end if; - if flash_be_n(1) = '0' then - flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after 25 ns; - end if; - if flash_be_n(2) = '0' then - flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after 25 ns; - end if; - if flash_be_n(3) = '0' then - flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after 25 ns; - end if; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------- -STIMULUS: process - - begin - - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 778254*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '1'; - wait for 3000*CLK_PERIOD; - wait until rising_edge(clk); - nmi <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top.prj b/lib/CPUs/MIPS/syn/ise101/mips_top.prj deleted file mode 100644 index d7e78b5..0000000 --- a/lib/CPUs/MIPS/syn/ise101/mips_top.prj +++ /dev/null @@ -1,18 +0,0 @@ -vhdl work "../../../../misc/dpram_2w2r.vhd" -vhdl work "../../../../misc/dpram_1w1r.vhd" -vhdl work "../../../../FIFO/src/fifo_sync_ctrl.vhd" -vhdl work "../../../../FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../src/core/mips_types.vhd" -vhdl work "../../../../FIFO/src/fifo_sync.vhd" -vhdl work "../../src/core/mips_shifter.vhd" -vhdl work "../../src/core/mips_reg.vhd" -vhdl work "../../src/core/mips_muldiv.vhd" -vhdl work "../../src/core/mips_instr.vhd" -vhdl work "../../src/core/mips_icache.vhd" -vhdl work "../../src/core/mips_dcache.vhd" -vhdl work "../../src/core/mips_bcu.vhd" -vhdl work "../../src/core/mips_alu.vhd" -vhdl work "../../src/core/mips_pipeline.vhd" -vhdl work "../../src/core/mips_cop.vhd" -vhdl work "../../src/core/mips_biu.vhd" -vhdl work "../../src/core/mips_top.vhd" diff --git a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj b/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj deleted file mode 100644 index ebe6b75..0000000 --- a/lib/CPUs/MIPS/syn/ise101/mips_top_vhdl.prj +++ /dev/null @@ -1,18 +0,0 @@ -vhdl work "W:\vhdl\lib\misc\dpram_2w2r.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_icache.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_dcache.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_biu.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd" diff --git a/lib/CPUs/MIPS/todo.txt b/lib/CPUs/MIPS/todo.txt deleted file mode 100644 index d2bccbf..0000000 --- a/lib/CPUs/MIPS/todo.txt +++ /dev/null @@ -1,32 +0,0 @@ -2008-10-26 -- Area-Optimierung: DIV und MUL verwenden gleiche Ressourcen -- Area-Optimierung: MUL32x32 primitive für Virtex-4 -- shifter: log shifter besser als built-in sll, srl, sra? Nein (2008-10-27) -- External COP 1..3 interface -- FPU (COP1) -- MMU - -2008-10-27 -- Area vs. speed : Pipeline-stall statt forwarding -- Caches: - Lock-up free cache (refill critical word first then un-lock CPU) (geringer Effekt, zu kompliziert => geringere Zuverlässigkeit) - - 1,2,4-way assoziative - - 2nd-Level cache in System - - Write-back policy - -2008-11-15 -- Bus exceptions IBE DBE (BUI/Cache restart notwendig) - -2009-03-18 -- cache line sizes von 1 word (4 bytes) gibt NULL-vector. Fehler in Berechnung der inedx_widths - -2009-8-8 -- Soft-Reset. Ähnlich wie Exception (Reset/NMI). Speicherung von EPC (done) -- CP_COND - -2009-10-17 -- Soft-reset implemetiert. Register werden wie bei normaler Exception verändert. - TodO: Bei Soft-reset (laut Buch) KUc=0, IEc=0 und BEV=1 initialisieren - -- Uncached write: Geht wie bei cached-write in den Write-Buffer. Folge: Mögliche lange Latenz bis uncached memory-mapped I/O tatsächlich geschieben wird. - Könnte bei IRQ acknowledging Probleme bereiten (z.b. mehrfaches (unötiges) anspringen der ISR, obwohl IRQ schon acknowleded wurde). - Work-around: Nach schreiben von memory-mapped I/O, gleiche Adresse zurücklesen (lesen wartet bis write-buffer leer). diff --git a/lib/CPUs/MIPS/tools/Makefile b/lib/CPUs/MIPS/tools/Makefile deleted file mode 100644 index 1c8ef53..0000000 --- a/lib/CPUs/MIPS/tools/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -CFLAGS=-O2 -CC=gcc -PREFIX=/usr/local -all: romgen ramgen flashgen - -romgen: ./src/romgen.c - $(CC) $(CFLAGS) ./src/romgen.c -lm -o ./romgen - -ramgen: ./src/ramgen.c - $(CC) $(CFLAGS) ./src/ramgen.c -lm -o ./ramgen - -flashgen: ./src/flashgen.c - $(CC) $(CFLAGS) ./src/flashgen.c -lm -o ./flashgen_el - $(CC) $(CFLAGS) -DTARGET_IS_BIG_ENDIAN ./src/flashgen.c -lm -o ./flashgen_eb - -install: - cp romgen $(PREFIX)/bin - cp ramgen $(PREFIX)/bin - cp flashgen_el $(PREFIX)/bin - cp flashgen_eb $(PREFIX)/bin -clean: - rm -rf romgen* ramgen* flashgen* diff --git a/lib/CPUs/MIPS/tools/src/flashgen.c b/lib/CPUs/MIPS/tools/src/flashgen.c deleted file mode 100644 index cc775a7..0000000 --- a/lib/CPUs/MIPS/tools/src/flashgen.c +++ /dev/null @@ -1,153 +0,0 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define SDRAM_BASE 0x40000000 -#define FLASH_OFFSET 0x00000000 - -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -UINT32 to_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -UINT32 from_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -// -------------------------------------------------------------- -typedef struct _sflash_img_hdr_t -{ - UINT8 magic[4]; - UINT32 target_addr; - UINT32 img_offset; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -// -------------------------------------------------------------- -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_flash[1024]; - char name_prj[1024]; - char *pBuf; - flash_img_hdr_t img_hdr = {0}; - - FILE *pFile; - int filesize; - long start, end; - int i; - - if (argc < 2) - { - fprintf(stderr, "Usage: flashgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - pFile = fopen(pFilenameIn, "rb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_flash, "%s.flash.bin", name_prj); - - // determine filesize - fseek(pFile, 0, SEEK_SET); - start = ftell(pFile); - fseek(pFile, 0, SEEK_END); - end = ftell(pFile); - fseek(pFile, 0, SEEK_SET); - filesize = (end-start); - - pBuf = (char*)malloc(filesize); - fread(pBuf, 1, filesize, pFile); - - fclose(pFile); - - pFile = fopen(name_flash, "wb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", name_flash); - return 1; - } - - img_hdr.magic[0] = 'J'; - img_hdr.magic[1] = 'F'; - img_hdr.magic[2] = 'I'; - img_hdr.magic[3] = '1'; -#ifdef TARGET_IS_BIG_ENDIAN - img_hdr.target_addr = to_big_endian32(SDRAM_BASE); - img_hdr.img_size = to_big_endian32(filesize); - img_hdr.img_offset = to_big_endian32(FLASH_OFFSET + sizeof(flash_img_hdr_t)); - img_hdr.hdr_next = to_big_endian32(FLASH_OFFSET); -#else - img_hdr.target_addr = SDRAM_BASE; - img_hdr.img_size = filesize; - img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = FLASH_OFFSET; -#endif - fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); - fwrite(pBuf, 1, filesize, pFile); - - fclose(pFile); - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c deleted file mode 100644 index 8f61118..0000000 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ /dev/null @@ -1,385 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); - fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: ramgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); -// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c deleted file mode 100644 index 60c00c3..0000000 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ /dev/null @@ -1,429 +0,0 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define ARCH_NAME "data" -#define ENT_NAME "rom" -#define JTAG_ADDR_WIDTH 16 - -UINT32 g_endianess_EB; - -// -------------------------------------------------------------- -UINT32 conv_endian32(UINT32 src) -{ - UINT32 dst; - - dst = (0xFF000000 & (src << 24)) - | (0x00FF0000 & (src << 8)) - | (0x0000FF00 & (src >> 8)) - | (0x000000FF & (src >> 24)); - - return dst; -}; - -UINT32 to_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -UINT32 from_big_endian32(UINT32 src) -{ -#ifndef NATIVE_IS_BIG_ENDIAN - return conv_endian32(src); -#else - return src; -#endif -} - -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "\t\tX\"%8.8X\"", to_big_endian32(word)); - else - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = - {"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - if (g_endianess_EB) - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, to_big_endian32(word)); - else - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen [{EL|EB}]\n"); - return 1; - } - - pFilenameIn = argv[1]; - nbits_addr = atoi(argv[2]); - - g_endianess_EB = 0; - if (argc == 4) - { - if ((toupper(argv[3][0]) == 'E') && (toupper(argv[3][1]) == 'B')) - g_endianess_EB = 1; - } - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/FIFO/sim/tb_gray_counter.fdo b/lib/FIFO/sim/tb_gray_counter.fdo deleted file mode 100644 index b619f71..0000000 --- a/lib/FIFO/sim/tb_gray_counter.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/tb_gray_counter.vhd" -vsim -t 1ps -lib work tb_gray_counter -view wave -do {tb_gray_counter.wdo} -view structure -view signals - -run 1us diff --git a/lib/FIFO/sim/tb_gray_counter.wdo b/lib/FIFO/sim/tb_gray_counter.wdo deleted file mode 100644 index b33112f..0000000 --- a/lib/FIFO/sim/tb_gray_counter.wdo +++ /dev/null @@ -1,25 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_gray_counter/rst -add wave -noupdate -format Logic /tb_gray_counter/ce -add wave -noupdate -format Logic /tb_gray_counter/clk -add wave -noupdate -format Literal /tb_gray_counter/bcnt -add wave -noupdate -format Literal /tb_gray_counter/bnxt -add wave -noupdate -format Literal /tb_gray_counter/gcnt -add wave -noupdate -format Literal /tb_gray_counter/gnxt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {20898 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {134759 ps} diff --git a/lib/FIFO/src/.directory_history b/lib/FIFO/src/.directory_history deleted file mode 100644 index d1192e2..0000000 --- a/lib/FIFO/src/.directory_history +++ /dev/null @@ -1,8 +0,0 @@ -VHDL/lib/FIFO/src/async_fifo_ctrl.vhd -VHDL/lib/FIFO/src/fifo_async_ctrl.vhd -VHDL/lib/FIFO/src/fifo_async_ctrl.vhd - -VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd - -VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd -VHDL/lib/FIFO/src/fifo_sync_ctrl.vhd diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd deleted file mode 100644 index c0fd7b6..0000000 --- a/lib/FIFO/src/async_fifo_ctrl.vhd +++ /dev/null @@ -1,247 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity fifo_async_ctrl is - Generic - ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end fifo_async_ctrl; - -architecture Behavioral of fifo_async_ctrl is - - signal gcnt_w : unsigned (addr_width downto 0); - signal gcnt2_w : unsigned (addr_width downto 0); - signal bcnt2_aw : unsigned (addr_width downto 0); - signal bcnt_w : unsigned (addr_width downto 0); - signal gnxt_w : unsigned (addr_width downto 0); - signal bnxt_w : unsigned (addr_width downto 0); - signal gcnt_r : unsigned (addr_width downto 0); - signal gcnt2_r : unsigned (addr_width downto 0); - signal bcnt2_ar : unsigned (addr_width downto 0); - signal bcnt_r : unsigned (addr_width downto 0); - signal gnxt_r : unsigned (addr_width downto 0); - signal bnxt_r : unsigned (addr_width downto 0); - - signal empty, full : std_logic; - signal write_inhibit, read_inhibit : std_logic; - signal winc, rinc : std_logic; - - -- synthesis translate_off - signal diffw : signed (addr_width downto 0); - signal diffr : signed (addr_width downto 0); - -- synthesis translate_on - -begin - - ptr_w <= bcnt_w(addr_width-1 downto 0); - ptr_r <= bnxt_r(addr_width-1 downto 0); - winc <= we and (not write_inhibit); - rinc <= re and (not read_inhibit); - fifo_full <= write_inhibit; - fifo_empty <= read_inhibit; - -proc_write_inhibit: - process(rst, clk_w) - begin - if rst = '1' then - write_inhibit <= '0'; - elsif rising_edge(clk_w) then - write_inhibit <= full; - end if; - end process; - -proc_read_inhibit: - process(rst, clk_r) - begin - if rst = '1' then - read_inhibit <= '1'; - elsif rising_edge(clk_r) then - read_inhibit <= empty; - end if; - end process; - -proc_sync_grptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - gcnt2_r <= p2; - p2 := p1; - p1 := gcnt_r; - end if; - end process; - -proc_ptr_gwptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - gcnt2_w <= p2; - p2 := p1; - p1 := gcnt_w; - end if; - end process; - -proc_status_full: - process(gnxt_w, gcnt2_r) - begin - if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then - full <= '1'; - else - full <= '0'; - end if; - end process; - -proc_status_empty: - process(gnxt_r, gcnt2_w) - begin - if (gnxt_r = gcnt2_w) then - empty <= '1'; - else - empty <= '0'; - end if; - end process; - -proc_sync_arptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - bcnt2_ar <= p2; - p2 := p1; - p1 := bcnt_r; - end if; - end process; - -proc_ptr_awptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - bcnt2_aw <= p2; - p2 := p1; - p1 := bcnt_w; - end if; - end process; - -proc_status_almost_full: - process(rst, clk_w) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffw <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_afull <= '0'; - diff := (others => '0'); - elsif rising_edge(clk_w) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar))); - end if; - end process; - -proc_status_almost_empty: - process(rst, clk_r) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffr <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_aempty <= '1'; - diff := (others => '0'); - elsif rising_edge(clk_r) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r))); - end if; - end process; - -inst_gray_counter_w : entity work.gray_counter - generic map - ( - width => addr_width+1, - init_value => 0 - ) - port map - ( - rst => rst, - clk => clk_w, - ce => winc, - bcnt => bcnt_w, - bnxt => bnxt_w, - gcnt => gcnt_w, - gnxt => gnxt_w - ); - -inst_gray_counter_r : entity work.gray_counter - generic map - ( - width => addr_width+1, - init_value => 0 - ) - port map - ( - rst => rst, - clk => clk_r, - ce => rinc, - bcnt => bcnt_r, - bnxt => bnxt_r, - gcnt => gcnt_r, - gnxt => gnxt_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/dpram_1w1r.vhd b/lib/FIFO/src/dpram_1w1r.vhd deleted file mode 100644 index c63153e..0000000 --- a/lib/FIFO/src/dpram_1w1r.vhd +++ /dev/null @@ -1,77 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r; - -architecture Behavioral of dpram_1w1r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_async.vhd b/lib/FIFO/src/fifo_async.vhd deleted file mode 100644 index e892bc5..0000000 --- a/lib/FIFO/src/fifo_async.vhd +++ /dev/null @@ -1,110 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_async is - Generic - ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_async; - -architecture Behavioral of fifo_async is - - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : std_logic; - signal mem_we : std_logic; - -begin - - mem_we <= we and not full; - fifo_full <= full; - - -- Instantiate the Unit Under Test (UUT) - inst_fifo_async_ctrl: entity work.fifo_async_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => fifo_empty, - fifo_afull => fifo_afull, - fifo_aempty => fifo_aempty - - ); - -inst_dpram_1w1r: entity work.dpram_1w1r - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd deleted file mode 100644 index 7404fc2..0000000 --- a/lib/FIFO/src/fifo_ctrl_pkg.vhd +++ /dev/null @@ -1,67 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package fifo_ctrl_pkg is - - -- Constants - -- Types - - -- Functions - function bin2gray(xb : unsigned) return unsigned; - function gray2bin(xg : unsigned) return unsigned; - -end fifo_ctrl_pkg; - -package body fifo_ctrl_pkg is - - function bin2gray(xb : unsigned) return unsigned is - variable xg : unsigned(xb'left downto xb'right); - begin - - xg(xg'left) := xb(xb'left); - for i in 1 to xb'left loop - xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i); - end loop; - - return xg; - end bin2gray; - - function gray2bin(xg : unsigned) return unsigned is - variable xb : unsigned(xg'left downto xg'right); - begin - - xb(xb'left) := xg(xg'left); - for i in 1 to xg'left loop - xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i); - end loop; - - return xb; - end gray2bin; - -end fifo_ctrl_pkg; - diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd deleted file mode 100644 index 810ba7c..0000000 --- a/lib/FIFO/src/fifo_sync.vhd +++ /dev/null @@ -1,119 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic - ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_wr_en : STD_LOGIC; - signal mem_rd_en : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - signal pre_full : STD_LOGIC; - signal pre_empty : STD_LOGIC; - -begin - - mem_wr_en <= not full; - mem_rd_en <= not pre_empty; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - -inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_pre_full => pre_full, - fifo_pre_empty => pre_empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - -inst_dpram_1w1r: entity work.dpram_1w1r - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => mem_wr_en, - en_b => mem_rd_en, - we_a => we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_sync_dist.vhd b/lib/FIFO/src/fifo_sync_dist.vhd deleted file mode 100644 index beb89f5..0000000 --- a/lib/FIFO/src/fifo_sync_dist.vhd +++ /dev/null @@ -1,117 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync_dist is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync_dist; - -architecture Behavioral of fifo_sync_dist is - - signal mem_wr_en : STD_LOGIC; - signal mem_rd_en : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - signal pre_full : STD_LOGIC; - signal pre_empty : STD_LOGIC; - -begin - - mem_wr_en <= not full; - mem_rd_en <= not pre_empty; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_pre_full => pre_full, - fifo_pre_empty => pre_empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => mem_wr_en, - en_b => mem_rd_en, - we_a => we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd deleted file mode 100644 index 66fc155..0000000 --- a/lib/FIFO/src/gray_counter.vhd +++ /dev/null @@ -1,86 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity gray_counter is - Generic ( - width : natural := 3; - init_value : natural := 0 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - bcnt : out unsigned (width-1 downto 0); - bnxt : out unsigned (width-1 downto 0); - gcnt : out unsigned (width-1 downto 0); - gnxt : out unsigned (width-1 downto 0) - ); -end gray_counter; - -architecture Behavioral of gray_counter is - - signal cntb : unsigned (width-1 downto 0); - signal nxtb : unsigned (width-1 downto 0); - signal cntg : unsigned (width-1 downto 0); - signal nxtg : unsigned (width-1 downto 0); - -begin - - bnxt <= nxtb; - gnxt <= nxtg; - - process(rst, clk, ce, cntb, nxtb) - begin - if rst = '1' then - cntb <= to_unsigned(init_value, width); - nxtb <= to_unsigned(init_value, width); - cntg <= to_unsigned(init_value, width); - nxtg <= to_unsigned(init_value, width); - bcnt <= to_unsigned(init_value, width); - gcnt <= to_unsigned(init_value, width); - else - if rising_edge(clk) then - bcnt <= nxtb; - gcnt <= nxtg; - cntb <= nxtb; - cntg <= nxtg; - end if; - nxtg <= bin2gray(nxtb); - nxtb <= cntb; - if ce = '1' then - nxtb <= cntb + 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd deleted file mode 100644 index c0f293e..0000000 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ /dev/null @@ -1,202 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity fifo_sync_ctrl is - Generic - ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_pre_full : out STD_LOGIC; - fifo_pre_empty : out STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end fifo_sync_ctrl; - -architecture Behavioral of fifo_sync_ctrl is - - signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0); - signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0); - signal empty, full : std_logic; - signal pre_empty, pre_full : std_logic; - signal was_write : std_logic; - signal write, read : std_logic; - signal diff : unsigned (addr_width downto 0); - -begin - - read <= re and not empty; - write <= we and not full; - - fifo_full <= full; - fifo_empty <= empty; - fifo_pre_full <= pre_full; - fifo_pre_empty <= pre_empty; - - -proc_diff_gen: - process(rst, clk) - begin - if rst = '1' then - diff <= (others => '0'); - elsif rising_edge(clk) then - if write = '1' and read = '0' then - diff <= diff + 1; - elsif write = '0' and read = '1' then - diff <= diff - 1; - end if; - end if; - end process; - -proc_status_almost_full: - process(rst, clk) - begin - if rst = '1' then - fifo_afull <= '0'; - elsif rising_edge(clk) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - end if; - end process; - -proc_status_almost_empty: - process(rst, clk) - begin - if rst = '1' then - fifo_aempty <= '1'; - elsif rising_edge(clk) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - end if; - end process; - -proc_full_reg: - process(rst, clk) - begin - if rst = '1' then - full <= '0'; - elsif rising_edge(clk) then - full <= pre_full; - end if; - end process; - -proc_empty_reg: - process(rst, clk) - begin - if rst = '1' then - empty <= '1'; - elsif rising_edge(clk) then - empty <= pre_empty; - end if; - end process; - -proc_status_w: - process(was_write, pW_next, pR_next, pW, pR, write, read) - begin - if (pW_next = pR) and (write = '1' or was_write = '1') then - pre_full <= '1'; - else - pre_full <= '0'; - end if; - if (pR_next = pW) and (read = '1' or was_write = '0') then - pre_empty <= '1'; - else - pre_empty <= '0'; - end if; - end process; - -proc_flag_write: - process(rst, clk) - begin - if rst = '1' then - was_write <= '0'; - elsif rising_edge(clk) then - if write = '1' then - was_write <= '1'; - elsif read = '1' then - was_write <= '0'; - end if; - end if; - end process; - -proc_ptr_w: - process(rst, clk, pW, write, full) - begin - if rst = '1' then - pW <= to_unsigned(0, addr_width); - pW_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if write = '1' then - pW <= pW_next; - end if; - end if; - pW_next <= pW; - if write = '1' then - pW_next <= pW + 1; - end if; - ptr_w <= pW; - end process; - -proc_ptr_r: - process(rst, clk, pR_next, pR, read, empty) - begin - if rst = '1' then - pR <= to_unsigned(0, addr_width); - pR_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if read = '1' then - pR <= pR_next; - end if; - end if; - pR_next <= pR; - if read = '1' then - pR_next <= pR + 1; - end if; - ptr_r <= pR_next; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/tb_fifo_async.vhd b/lib/FIFO/src/tb_fifo_async.vhd deleted file mode 100644 index e0c2b62..0000000 --- a/lib/FIFO/src/tb_fifo_async.vhd +++ /dev/null @@ -1,222 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_fifo_async IS -END tb_fifo_async; - -ARCHITECTURE behavior OF tb_fifo_async IS - - --Constants - constant PERIOD_W : time := 10 ns; - constant PERIOD_R : time := 22.1 ns; - constant ADDR_WIDTH : integer := 3; - constant DATA_WIDTH : integer := 8; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk_w : STD_LOGIC := '0'; - signal clk_r : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal ref_r : unsigned (7 downto 0); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.fifo_async - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - data_width => DATA_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we, - re => re, - data_w => din, - data_r => dout, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - tb_clk_w : PROCESS - BEGIN - clk_w <= not clk_w; - wait for PERIOD_W/2; - END PROCESS; - - tb_clk_r : PROCESS - BEGIN - clk_r <= not clk_r; - wait for PERIOD_R/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD_W; - rst <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 25*PERIOD_W; - write_en <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 25*PERIOD_W; - write_en <= '0'; - wait for 7*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 1*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 3*PERIOD_W; - write_en <= '1'; - wait for 4*PERIOD_W; - write_en <= '0'; - wait for 17*PERIOD_W; - write_en <= '1'; - wait for 55*PERIOD_W; - write_en <= '0'; - wait for 1*PERIOD_W; - write_en <= '1'; - wait for 1*PERIOD_W; - write_en <= '0'; - wait for 3*PERIOD_W; - write_en <= '1'; - wait for 44*PERIOD_W; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD_R; - read_en <= '1'; - wait for 25*PERIOD_R; - read_en <= '0'; - wait for 25*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 5*PERIOD_R; - read_en <= '1'; - wait for 1*PERIOD_R; - read_en <= '0'; - wait for 7*PERIOD_R; - read_en <= '1'; - wait for 15*PERIOD_R; - read_en <= '0'; - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - - tb_w : PROCESS(rst, clk_w) - BEGIN - - if rst = '1' then - din <= (others => '0'); - elsif rising_edge(clk_w) then - if we = '1' then - din <= din + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk_r) - BEGIN - - if rst = '1' then - ref_r <= (others => '0'); - elsif rising_edge(clk_r) then - if re = '1' then - assert ref_r = dout report "FIFO read error!" severity failure; - ref_r <= ref_r + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_fifo_sync.vhd b/lib/FIFO/src/tb_fifo_sync.vhd deleted file mode 100644 index c25b260..0000000 --- a/lib/FIFO/src/tb_fifo_sync.vhd +++ /dev/null @@ -1,206 +0,0 @@ -------------------------------------------------------------------------- --- Project: FIFO, generic FIFOs written in VHDL --- Release 1 --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA --- --- For questions and ideas, please contact the author at jens@jayfield.org --- ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_fifo_sync IS -END tb_fifo_sync; - -ARCHITECTURE behavior OF tb_fifo_sync IS - - --Constants - constant PERIOD : time := 10 ns; - constant ADDR_WIDTH : integer := 3; - constant DATA_WIDTH : integer := 8; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal ref_r : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.fifo_sync - GENERIC MAP - ( - data_width => DATA_WIDTH, - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - data_w => din, - data_r => dout, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD; - rst <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 1*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 3*PERIOD; - write_en <= '1'; - wait for 4*PERIOD; - write_en <= '0'; - wait for 17*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD; - read_en <= '1'; - wait for 25*PERIOD; - read_en <= '0'; - wait for 25*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 7*PERIOD; - read_en <= '1'; - wait for 20*PERIOD; - read_en <= '0'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - - tb_w : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - din <= (others => '0'); - elsif rising_edge(clk) then - if we = '1' then - din <= din + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - ref_r <= (others => '0'); - elsif rising_edge(clk) then - if re = '1' then - assert ref_r = dout report "FIFO read error!" severity failure; - ref_r <= ref_r + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_gray_counter.vhd b/lib/FIFO/src/tb_gray_counter.vhd deleted file mode 100644 index 00380d7..0000000 --- a/lib/FIFO/src/tb_gray_counter.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_gray_counter --- Module Name: tb_gray_counter.vhd --- Project Name: gray_counter package --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -ENTITY tb_gray_counter IS -END tb_gray_counter; - -ARCHITECTURE behavior OF tb_gray_counter IS - - constant PERIOD : time := 10 ns; - constant WIDTH : integer := 3; - - --Signals - signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal ce : STD_LOGIC := '0'; - -BEGIN - -inst_gray_counter : entity work.gray_counter - generic map (width => WIDTH) - port map ( - rst => rst, - clk => clk, - ce => ce, - bcnt => bcnt, - bnxt => bnxt, - gcnt => gcnt, - gnxt => gnxt - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_counter : PROCESS - - BEGIN - - wait for 4*PERIOD; - rst <= '0'; - wait for 1*PERIOD; - ce <= '1'; - wait for 3*PERIOD; - ce <= '0'; - wait for 4*PERIOD; - ce <= '1'; - wait for 1*PERIOD; - ce <= '0'; - wait for 1*PERIOD; - ce <= '1'; - - wait; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/PCK_FIO-1.16/PCK_FIO.html b/lib/PCK_FIO-1.16/PCK_FIO.html deleted file mode 100644 index 8b8c8c5..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.html +++ /dev/null @@ -1,297 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
- -PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -

The fo function is currently overloaded as follows: -

  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -
-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double-quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO has been developed with this latter package, and still -refers to this package by default. However, PCK_FIO  works with -IEEE.numeric_std -as well. To use IEEE.numeric_std, replace the reference to IEEE.std_logic_arith -in the source code.  This needs to be done consistently in a design -database (e.g. in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution is a file TB_PCK_FIO.vhd with a test -bench for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company-wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some -simulators/versions have problems with the package. The following is an -overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SimulatorPCK_FIO handling
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
PCK_FIO and various simulators/versions
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

- - diff --git a/lib/PCK_FIO-1.16/PCK_FIO.out.gold b/lib/PCK_FIO-1.16/PCK_FIO.out.gold deleted file mode 100644 index dcd183e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.out.gold +++ /dev/null @@ -1,206 +0,0 @@ -PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO ------------------------------------------ - -This is the result of running the PCK_FIO testbench. -This file should be compared with PCK_FIO.out.gold, which is -the reference output. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - --------------------- --- Basic features -- --------------------- - --- First some auxiliary declarations -> file RESULT: text is out "PCK_FIO.out"; -> variable L: line; -> variable BoolTrue: boolean := TRUE; -> variable BoolFalse: boolean := FALSE; -> variable IntPos: integer := 5678; -> variable BigIntPos: integer := 12345678; -> variable IntNeg: integer := -8765; -> variable BigIntNeg: integer := -87654321; -> variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); -> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); -> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); -> variable SigPos: signed(6 downto 0) := signed'("0010010"); -> variable SigNeg: signed(6 downto 0) := signed'("1010010"); -> variable BitX: std_logic := 'X'; -> variable Bit1: std_logic := '1'; -> variable Bit0: std_logic := '0'; - - --- fprint call with no arguments -> fprint(RESULT, L, "No arguments.\n);" -No arguments. - --- Special characters need to be escaped -> fprint(RESULT, L, "Special characters: \% \\ " \n"); -Special characters: % \ " - --- Various format specifiers interprete the same object differently -> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);" -> fo(Uns), fo(Uns), fo(Uns), fo(Uns) -> ); -Format specifiers: 0x52 82 1010010 U:1010010 - --- Format string can be shortened by using the iteration specifier -> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);" -> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) -> ); -Iteration specifier: 0x52 0x12 0x52 0x12 - ------------------------------------- --- Support for bit-oriented types -- ------------------------------------- - --- Reasonable format -> fprint(RESULT, L, "Reasonable format: %9{%r }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F - --- Decimal format -> fprint(RESULT, L, "Decimal format: %7{%d }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Decimal format: 18 82 18 -46 -1 1 -1 1 0 - --- Bit format -> fprint(RESULT, L, "Bit format: %7{%b }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0 - - --- Alignment --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Bitvectors with : %4{|}\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg) -> ); - --- Results of the call with various format specifiers - -Bitvectors with %1r: 0x52|0x12|0x12|0x52| -Bitvectors with %2r: 0x52|0x12|0x12|0x52| -Bitvectors with %3r: 0x52|0x12|0x12|0x52| -Bitvectors with %4r: 0x52|0x12|0x12|0x52| -Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52| - -Bitvectors with %-1r: 0x52|0x12|0x12|0x52| -Bitvectors with %-2r: 0x52|0x12|0x12|0x52| -Bitvectors with %-3r: 0x52|0x12|0x12|0x52| -Bitvectors with %-4r: 0x52|0x12|0x12|0x52| -Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 | - -Bitvectors with %1d: 82|18|18|-46| -Bitvectors with %2d: 82|18|18|-46| -Bitvectors with %3d: 82| 18| 18|-46| -Bitvectors with %4d: 82| 18| 18| -46| -Bitvectors with %5d: 82| 18| 18| -46| -Bitvectors with %6d: 82| 18| 18| -46| -Bitvectors with %7d: 82| 18| 18| -46| -Bitvectors with %8d: 82| 18| 18| -46| -Bitvectors with %9d: 82| 18| 18| -46| - -Bitvectors with %-1d: 82|18|18|-46| -Bitvectors with %-2d: 82|18|18|-46| -Bitvectors with %-3d: 82 |18 |18 |-46| -Bitvectors with %-4d: 82 |18 |18 |-46 | -Bitvectors with %-5d: 82 |18 |18 |-46 | -Bitvectors with %-6d: 82 |18 |18 |-46 | -Bitvectors with %-7d: 82 |18 |18 |-46 | -Bitvectors with %-8d: 82 |18 |18 |-46 | -Bitvectors with %-9d: 82 |18 |18 |-46 | - - -------------------------------- --- Support for integer types -- -------------------------------- - - --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Integers with : %4{|}\n", -> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) -> ); - --- Results of the call with various format specifiers - -Integers with %5d: 5678|-8765|12345678|-87654321| -Integers with %6d: 5678| -8765|12345678|-87654321| -Integers with %7d: 5678| -8765|12345678|-87654321| -Integers with %8d: 5678| -8765|12345678|-87654321| -Integers with %9d: 5678| -8765| 12345678|-87654321| -Integers with %10d: 5678| -8765| 12345678| -87654321| - -Integers with %-5d: 5678 |-8765|12345678|-87654321| -Integers with %-6d: 5678 |-8765 |12345678|-87654321| -Integers with %-7d: 5678 |-8765 |12345678|-87654321| -Integers with %-8d: 5678 |-8765 |12345678|-87654321| -Integers with %-9d: 5678 |-8765 |12345678 |-87654321| -Integers with %-10d: 5678 |-8765 |12345678 |-87654321 | - -Integers with %5r: 5678|-8765| 5678|-4321| -Integers with %6r: 5678|- 8765| 45678|-54321| -Integers with %7r: 5678|- 8765| 345678|-654321| -Integers with %8r: 5678|- 8765| 2345678|-7654321| -Integers with %9r: 5678|- 8765| 12345678|-87654321| -Integers with %10r: 5678|- 8765| 12345678|- 87654321| - -Integers with %-5r: 5678|-8765| 1234|-8765| -Integers with %-6r: 5678 |-8765 | 12345|-87654| -Integers with %-7r: 5678 |-8765 | 123456|-876543| -Integers with %-8r: 5678 |-8765 | 1234567|-8765432| -Integers with %-9r: 5678 |-8765 | 12345678|-87654321| -Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 | - - ----------------------- --- Support for time -- ----------------------- --- For portability reasons, time is converted --- into an integer value (of nanoseconds) -> wait for 648 ns -> fprint (RESULT, L, "The time is now %d ns\n", fo(now)); -The time is now 648 ns - ----------------------------------------- --- Erroneous calls and error messages -- ----------------------------------------- - --- Less arguments than formats specifiers -> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); -82 18 -** Warning: FIO_PrintLastValue: Format specifier beyond last argument -** in format string: "%d %d %d %d \n" -** ------^ - --- Unsupported format specifier -> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); -0x52 -** Warning: FIO_PrintArg: Unexpected format specifier 'v' -** in format string: "%r %v %r %r\n" -** ----^ -** Assuming 'q' to proceed: V:0010010 0x52 0x12 - - ----------------------------------------- --- Things you wouldn't expect to work -- ----------------------------------------- - --- Nested iteration -> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); -<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>> diff --git a/lib/PCK_FIO-1.16/PCK_FIO.vhd b/lib/PCK_FIO-1.16/PCK_FIO.vhd deleted file mode 100644 index e5e6a8e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.vhd +++ /dev/null @@ -1,916 +0,0 @@ ----- File: PCK_FIO.vhd ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- Revision history: ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.16 1999/04/21 08:28:46 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.14 1997/07/14 10:16:04 jand ----- prefix/postfix for bits/bitvectors set to empty strings by default ----- ----- Revision 1.13 1997/07/11 17:42:57 jand ----- Corrected Easics address ----- ----- Revision 1.12 1997/07/11 17:38:49 jand ----- Improved prefix/postfix support ----- ----- Revision 1.11 1995/11/15 13:46:02 jand ----- Catched integer'low value in fo for integers ----- ----- Revision 1.10 1995/08/11 16:42:26 jand ----- Reimplemented FIO_FormatExpand as a procedure in an attempt to ----- avoid memory leakage problems in VSS ----- ----- Revision 1.9 1995/08/09 13:47:51 jand ----- Removed array of line trick in fprint for less memory, less ----- CPU time, and more conservatism in general ----- Rearranged FIO_PrintValue call so that fprint remains concise ----- ----- Revision 1.8 1995/08/09 10:32:27 jand ----- Removed fprint_flat to have a single call level ----- Added explicit deallocators of line variables (has strong influence ----- on memory usage in VSS - and possibly CPU time) ----- Redefined 'fo' for type time to make it more portable ----- ----- Revision 1.7 1995/08/07 08:56:04 jand ----- Improved conciseness of fprint argument handling through array of line type ----- ----- Revision 1.6 1995/08/04 18:19:13 jand ----- Increase # arguments from 16 to 32 ----- Corrected bug within fprint 's call to Arg16 ----- Added support for bit format specifier 'b' ----- ----- Revision 1.5 1995/08/02 10:22:37 jand ----- Release 1.1 under GNU ----- ----- Revision 1.4 1995/08/01 11:15:52 jand ----- Added escaping during iteration string read ----- ----- Revision 1.3 1995/08/01 08:23:47 jand ----- Many improvements in robustness, conciseness and coding style ----- ----- Revision 1.2 1995/07/30 16:15:43 jand ----- Improved robustness for release to the world ----- ----- Revision 1.1 1995/07/30 14:21:30 jand ----- Initial revision ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - -package body PCK_FIO is - - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - function fo (Arg: string) return string is - begin - return Arg; - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; diff --git a/lib/PCK_FIO-1.16/README b/lib/PCK_FIO-1.16/README deleted file mode 100644 index 4af4c99..0000000 --- a/lib/PCK_FIO-1.16/README +++ /dev/null @@ -1,72 +0,0 @@ -# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ -# $Log: not supported by cvs2svn $ -# Revision 1.3 1999/04/21 08:08:35 jand -# Tested with IEEE.numeric_std -# Small patch for Leapfrog -# -# - - PCK_FIO, Version 1.16 - Copyright (C) 1995, 1999 Easics NV - ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Contents --------- - -This distribution contains the following files: - - PCK_FIO.vhd: VHDL source of the PCK_FIO package - TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation ------------- - -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO.vhd into the same library. - -If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need -to edit the source code of the package and the test bench and replace the -package use clause. PCK_FIO works with either of these packages. - -To install the documentation, point your web browser to the file PCK_FIO.html -and bookmark it. - - -Installation check ------------------- - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. diff --git a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd b/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd deleted file mode 100644 index c64d045..0000000 --- a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd +++ /dev/null @@ -1,504 +0,0 @@ ----- File: TB_PCK_FIO.vhd ----- ----- TBC_PCK_FIO: a test bench for the PCK_FIO package. ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 396 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.7 1999/04/21 08:23:53 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.3 1998/09/29 10:09:44 vhdl ----- to EASICS_PACKAGES ----- ----- Revision 1.2 1998/09/29 09:17:51 vhdl ----- library EASICS_PACKAGES; ----- ----- Revision 1.1 1998/09/29 09:15:44 vhdl ----- Initial revision ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n);""\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); - - -fprint(RESULT, L, - "\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES deleted file mode 100644 index b755a56..0000000 --- a/lib/PCK_FIO-2002.7/CHANGES +++ /dev/null @@ -1,86 +0,0 @@ ----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -Changes from version 1.16 to version 2002.07 -============================================ - -PCK_FIO is now distributed under the GNU Lesser General Public Licencse -instead of the ordinary GPL, to better reflect intended usage. - -Cosmetic changes in source code to correct some typos in the testbench output. -A new testbench is also supplied. - -The package now uses IEEE.numeric_std as default. - -URL http://www.easics.com has been made part of address. - -Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993. -Because of backwards-incompatibility, it has been necessary to supply -different sets of files for 1987 and 1993. - -Split the packages into a separate file for the header and a -separate file for the body (in compliance with Easics' guidelines). - -These changes resulted in the files: - -Files for VHDL-1993: --------------------- - PCK_FIO_1993.vhd : the source code of the header file for the package - PCK_FIO_1993_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1993.vhd: the testbench for the package - -Files for VHDL-1987: --------------------- - PCK_FIO_1987.vhd: the source code of the header file for the package - PCK_FIO_1987_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1987.vhd: the testbench for the package - -Updated README and PCK_FIO.html to support these changes. - -Adapted package files to support NUL termination of strings. -fo(Arg: string) now prints the string until the first NUL. -Several examples of its use are demonstrated in the supplied testbenches. - -Made cosmetic changes to code to improve readability. - -Acknowledgment --------------- -These changes have been implemented by Peter Geens. - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html deleted file mode 100644 index 6b5fc72..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO.html +++ /dev/null @@ -1,339 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-

-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-

-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-

-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -
  -
The fo function is currently overloaded as follows:
- -
  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -


To support null-terminated strings, the function fo(Arg: -string) processes Arg up to the first NUL character, -if any. If you want the whole string to be outputted you can just enter -the string as a direct argument in fprint.  See also the -examples in the testbench. -

-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-

-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO works with both packages,  but refers to the standard -package IEEE.numeric_std by default. To use IEEE.std_logic_arith -instead, replace the reference to IEEE.numeric_std in the source -code.  This needs to be done consistently in a design database (e.g. -in the PCK_FIO test bench as well). -

-

-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-

-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-

-

-Test bench

-Included in the distribution are the files TB_PCK_FIO_1987.vhd and -TB_PCK_FIO_1993 with a test bench,depending on the standard you're -running, for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-

-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is available in either standard VHDL Std1076-1987 or standard -VHDL Std1076-1993. Nevertheless, some simulators/versions have problems -with the package. The following is an overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1987 and various simulators/versions
SimulatorPCK_FIO_1987
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Synopsys VSS/Scirocco 2000.02Incorrect output in compiled mode, interpreted mode works
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
- -
  -
- - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1993 and various simulators/versions
SimulatorPCK_FIO_1993
Synopsys VSS/Scirocco 2000.02Compile errors due to improper handling of files by Synopsys
Synopsys VSS/Scirocco 2000.06works fine
Modeltech modelsim 5.4c and higherOK
- -

Although the package name suggests file IO, it only does file output. -

-

-

-Author

-Jan Decaluwe -

-

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See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd deleted file mode 100644 index 44e42cf..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd +++ /dev/null @@ -1,821 +0,0 @@ ----- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg: string) - -- gives index until first NUL - -- reads string from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd deleted file mode 100644 index 9df893e..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd +++ /dev/null @@ -1,108 +0,0 @@ ----- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd deleted file mode 100644 index 3d123f0..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd +++ /dev/null @@ -1,814 +0,0 @@ ----- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - - package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (file F: text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (file F: text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg :string) - -- returns index of first NUL in Arg or if no NUL is present just Arg'length - -- goes through Arg from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - -- returns the Arg string until the first NUL was encountered - -- if fo is used on a string with NUL in it it will stop reading the rest - -- of the string, even if a larger field width has been supplied. fo will - -- then just pad the remaining characters with blanco's - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README deleted file mode 100644 index b16c6c5..0000000 --- a/lib/PCK_FIO-2002.7/README +++ /dev/null @@ -1,88 +0,0 @@ ----- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Version 2002.07 -=============== - -Contents -======== - -This distribution contains the following files: - - PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package - PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package - PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package - PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package - TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO - TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation -============ - -VHDL-1987 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library. - -VHDL-1993 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library. - -Numeric packages ----------------- -If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need -to edit the source code of the package, both header and body, and the test bench -and replace the package use clause. PCK_FIO works with either of these packages. - -Documentation -------------- -To install the documentation, put the file point PCK_FIO.html in a path of -your choosing, point your web browser to it, and bookmark it. - - -Installation check -================== - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd deleted file mode 100644 index 2e18ff4..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd +++ /dev/null @@ -1,531 +0,0 @@ ----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one - use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- temp_string: string:="ABC"&NUL&"DEF" --- test for detecting NUL in string -fprint(RESULT, L, "\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then" - & " in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number" & - " of characters in the string fprint\n" & - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd deleted file mode 100644 index 0386a11..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd +++ /dev/null @@ -1,536 +0,0 @@ ----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text open write_mode is "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- TempString: string:="ABC" & NUL & "DEF" --- test for detecting NUL in string -fprint(RESULT, L ,"\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"& - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 deleted file mode 100644 index c5a4a92..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001 - -ANALYZER = vcom -quiet -nologo -ANALYZER_C = vcom -quiet -nologo -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1987.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1987_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1987.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 deleted file mode 100644 index 0f9a351..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001 - -ANALYZER = vcom -quiet -nologo -93 -ANALYZER_C = vcom -quiet -nologo -93 -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1993.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1993_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1993.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj deleted file mode 100644 index ba54b14..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj +++ /dev/null @@ -1,13 +0,0 @@ -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo deleted file mode 100644 index 1f30d78..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl.wdo} -view wave -view structure -view signals -run 800us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo deleted file mode 100644 index 4a9d3f1..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo +++ /dev/null @@ -1,93 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {14963876 ps} 0} -configure wave -namecolwidth 184 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {14733925 ps} {15711632 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo deleted file mode 100644 index 4de7283..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl_fifo -do {tb_sdr_ctrl_fifo.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo deleted file mode 100644 index bd233a2..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo +++ /dev/null @@ -1,68 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd -add wave -noupdate -divider {Read FIFO} -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/was_write -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/pw_next -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_fifo_sync_ctrl/fifo_empty -add wave -noupdate -divider {Write FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_fifo_sync_ctrl/pw_next -add wave -noupdate -divider {Command FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_fifo_sync_ctrl/fifo_full -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {13893123 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {13879998 ps} {13928553 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo deleted file mode 100644 index 7d046f8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_r_rand_w.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo deleted file mode 100644 index d3d9e2b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_w_rand_r.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo deleted file mode 100644 index 832ec1b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo deleted file mode 100644 index eb20b08..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo +++ /dev/null @@ -1,82 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {60573747 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {60552548 ps} {60600861 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo deleted file mode 100644 index 0e41aef..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 10000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo deleted file mode 100644 index e3087e6..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo +++ /dev/null @@ -1,84 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {16004147 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {15914249 ps} {16324366 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo deleted file mode 100644 index b3be3ab..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend -do {tb_sdram_ctrl_frontend.wdo} -view wave -view structure -view signals -run 40us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo deleted file mode 100644 index 5d5538e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo +++ /dev/null @@ -1,48 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_in -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_dm_rd_out -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/u_data_vld -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {27802417 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {27712165 ps} {27944343 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd deleted file mode 100644 index c924c8c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd +++ /dev/null @@ -1,240 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Clock generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - read_phaseshift : integer := 0; - frequency_hz : integer := 100E6 - ); - port - ( - -- Clocks and Reset - rst : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_fb_in : in std_logic; -- feedback clock - read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0° - read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270° - sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0° - sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270° - locked_out : out std_logic; -- DCM locked status - error_out : out std_logic -- indicates DCM Errors - ); - -end; - -architecture tech of clockgen is - - constant CLKIN_PER : real := real(1000E6/frequency_hz); - - signal locked : unsigned(1 downto 0); - signal dcm_rst : unsigned(1 downto 0); - signal read_clk0 : std_logic; - signal read_clk270 : std_logic; - signal read_clk0_bufg : std_logic; - signal read_clk270_bufg : std_logic; - signal sys_clk0 : std_logic; - signal sys_clk270 : std_logic; - signal sys_clk0_bufg : std_logic; - signal sys_clk270_bufg : std_logic; - signal dcm1_locked, dcm2_locked : unsigned(2 downto 0); - signal cnt_q : unsigned(4 downto 0); - - type STATE_TYPE is (s0, s1, s2, s3, s4); - signal state_q : STATE_TYPE; - -begin - - read_clk0_out <= read_clk0_bufg; - read_clk270_out <= read_clk270_bufg; - sys_clk0_out <= sys_clk0_bufg; - sys_clk270_out <= sys_clk270_bufg; - -bufg11: bufg - port map - ( - o => sys_clk0_bufg, - i => sys_clk0 - ); - -bufg12: bufg - port map ( - o => sys_clk270_bufg, - i => sys_clk270 - ); - -bufg13: bufg - port map - ( - o => read_clk0_bufg, - i => read_clk0 - ); - -bufg14: bufg - port map ( - o => read_clk270_bufg, - i => read_clk270 - ); - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(0), -- DCM LOCK status output - CLKFB => clk_fb_in, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - - inst_DCM_BASE_1 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => read_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => read_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(1), -- DCM LOCK status output - CLKFB => read_clk0_bufg, -- DCM clock feedback - CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - - dcm_rst(1) <= not locked(0); - -dcm_fsm: - process(rst, clk_in) - begin - if rst = '1' then - state_q <= s0; - dcm_rst(0) <= '0'; - cnt_q <= "11111"; - error_out <= '0'; - locked_out <= '0'; - dcm1_locked <= (others => '0'); - dcm2_locked <= (others => '0'); - elsif rising_edge(clk_in) then - case state_q is - when s0 => - state_q <= s1; - - when s1 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '1'; - state_q <= s2; - end if; - - when s2 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '0'; - state_q <= s3; - end if; - - when s3 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - state_q <= s4; - error_out <= '0'; - end if; - - when s4 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - locked_out <= '1'; - else - error_out <= '1'; - end if; - end case; - - -- synchronize 'dcm1_locked' - dcm1_locked <= dcm1_locked(1 downto 0) & locked(0); - dcm2_locked <= dcm2_locked(1 downto 0) & locked(1); - - end if; - end process; - -end architecture tech; - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd deleted file mode 100644 index f5ab332..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,389 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - sdr_data_req_r : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - - type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0); - signal dm_out_pipe : dm_out_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -dmout_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in dm_out_pipe'length-1 downto 1 loop - dm_out_pipe(i) <= dm_out_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - dm_out_pipe(0) <= sdr_dm_rd_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - sdr_data_req_r <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - sdr_dm_rd_out <= dm_out_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_req_r <= phy_ctrl.re; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd deleted file mode 100644 index 02ad3a7..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_we : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - mem_we <= we; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd deleted file mode 100644 index 4f799c5..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Reset generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity reset is - port - ( - clk : in std_logic; - rst_in : in std_logic; - rst_out : out std_logic - ); -end; - -architecture tech of reset is - - signal rst : std_logic; - signal shift_pipe : std_logic_vector(3 downto 0); - attribute KEEP : string; - attribute KEEP of shift_pipe : signal is "TRUE"; - -begin - - rst <= shift_pipe(0); - -bufg_reset: bufg - port map - ( - o => rst_out, - i => rst - ); - -fdp0: fdp - generic map - ( - init => '1' - ) - port map - ( - d => rst_in, - c => clk, - pre => '0', - q => shift_pipe(3) - ); - -fdp1: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(3), - c => clk, - pre => '0', - q => shift_pipe(2) - ); - -fdp2: fdp - generic map - ( - init => '1' - ) - port map - ( - d => shift_pipe(2), - c => clk, - pre => '0', - q => shift_pipe(1) - ); - -fdp3: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(1), - c => clk, - pre => '0', - q => shift_pipe(0) - ); - -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd deleted file mode 100644 index a50b6e8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd +++ /dev/null @@ -1,269 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic (BL : natural := 2); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 10; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL); - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 10; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd deleted file mode 100644 index b62e085..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 1; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd deleted file mode 100644 index dbb5b80..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd +++ /dev/null @@ -1,487 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : natural := 100E6; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal act_request : std_logic; - signal act_request_set : std_logic; - signal act_request_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - act_request_set <= '0'; - act_request_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - act_request_set <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if sdr_cmd_busy = '0' then - if refresh_request = '1' then - sdr_mode(BIT_PRE_ALL) <= '1'; - sdr_cmd_we <= '1'; - sdr_cmd <= SD_PRE; - st_ctrl_next <= REFRESH; - else - u_busy <= '0'; - if u_cmd_we = '1' then - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_WRITE_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_WRITE_ACT; - else - st_ctrl_next <= USER_WRITE_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_WRITE; - end if; - when UCMD_READ => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_READ_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_READ_ACT; - else - st_ctrl_next <= USER_READ_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_READ; - end if; - when others => null; - end case; - end if; - end if; - end if; - - when USER_WRITE_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - act_request_set <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -act_request_register: - process (rst, clk) - begin - if rst = '1' then - act_request <= '1'; - elsif rising_edge(clk) then - if act_request_set = '1' then - act_request <= '1'; - elsif act_request_clr = '1' then - act_request <= '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd deleted file mode 100644 index 268636e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,293 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0; - fifo_depth : integer := 4 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - busy : out STD_LOGIC; - en : in STD_LOGIC; - r_wn : in STD_LOGIC; - be : in unsigned(SDR_DM_WIDTH-1 downto 0); - addr : in user_addr_t; - din : in unsigned(SDR_DATA_WIDTH-1 downto 0); - dout : out unsigned(SDR_DATA_WIDTH-1 downto 0); - dout_re : in STD_LOGIC; - dout_vld : out STD_LOGIC; - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend; - -architecture struct of sdram_ctrl_frontend is - - -- Number of user data words for simulation - signal rst_out : std_logic; - signal clk_out : std_logic; - - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0); - - alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - - alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH); - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - read_phaseshift => read_phaseshift, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => sys_rst_in, - sys_clk_in => sys_clk_in, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => sys_clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm_wr_in, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - sys_rst_out <= rst_out; - sys_clk_out <= clk_out; - busy <= not rdy; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full); - write_fifo_we <= en and not r_wn and rdy; - write_fifo_data_in <= din; - write_fifo_dm_in <= not be; - cat_fifo_we <= en and rdy; - cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ; - addr_fifo_in <= addr; - dm_rd_fifo_in <= not be; - tag_fifo_in <= (others=>'0'); - dout <= read_fifo_data_out; - dout_vld <= not read_fifo_empty; - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_rd_in <= dm_rd_fifo_out; - u_dm_wr_in <= write_fifo_dm_out; - u_tag_in <= tag_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out; - read_fifo_re <= (not read_fifo_empty) and dout_re; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r; - read_fifo_dm_in <= u_dm_rd_out; - - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd deleted file mode 100644 index 19768a4..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,289 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_data_req_r : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - signal clk0 : std_logic; - signal clk270 : std_logic; - signal read_clk270 : std_logic; - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal cg_rst : std_logic; - signal cg_read_clk0 : std_logic; - signal cg_read_clk270 : std_logic; - signal cg_sys_clk0 : std_logic; - signal cg_sys_clk270 : std_logic; - signal cg_locked : std_logic; - signal cg_error : std_logic; - signal ctrl_rst : std_logic; - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_ADDR_WIDTH : positive := 2; - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - clk0 <= cg_sys_clk0; - clk270 <= cg_sys_clk270; - read_clk270 <= cg_read_clk270; - cg_rst <= not cg_locked; - - --------------------------------- - sys_clk_out <= cg_sys_clk0; - sys_rst_out <= ctrl_rst; - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out)); - - --------------------------------- - inst_reset: entity work.reset - port map - ( - clk => clk0, - rst_in => cg_rst, - rst_out => ctrl_rst - ); - - inst_clockgen : entity work.clockgen - generic map - ( - read_phaseshift => read_phaseshift, - frequency_hz => f_sysclk - ) - port map - ( - rst => sys_rst_in, - clk_in => sys_clk_in, - clk_fb_in => sys_clk_fb, - read_clk0_out => cg_read_clk0, - read_clk270_out => cg_read_clk270, - sys_clk0_out => cg_sys_clk0, - sys_clk270_out => cg_sys_clk270, - locked_out => cg_locked, - error_out => cg_error - ); - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => 100E6, - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => CMD_FIFO_ADDR_WIDTH, - data_width => CMD_FIFO_DATA_WIDTH, - almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1), - almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1) - ) - PORT MAP - ( - rst => ctrl_rst, - clk => clk0, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_tag_in => tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => col_fifo_out, - mode_word => mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => ctrl_rst, - sys_clk0 => clk0, - sys_clk270 => clk270, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => read_clk270, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_req_r => u_data_req_r, - sdr_data_w => u_data_wr, - sdr_dm_wr_in => u_dm_wr_in, - sdr_dm_rd_in => u_dm_rd_in, - sdr_dm_rd_out => u_dm_rd_out, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd deleted file mode 100644 index d235d75..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd +++ /dev/null @@ -1,133 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - subtype cycle_cnt_t is natural range 0 to 10; - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd deleted file mode 100644 index 034215c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd +++ /dev/null @@ -1,336 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd deleted file mode 100644 index 51910b0..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd +++ /dev/null @@ -1,420 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdr_ctrl_fifo is -end; - -architecture struct of tb_sdr_ctrl_fifo is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - - signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_re : std_logic := '0'; - signal cmd_fifo_we : std_logic := '0'; - signal cmd_fifo_full : std_logic := '0'; - signal cmd_fifo_empty : std_logic := '0'; - signal cmd_fifo_almost_full : std_logic := '0'; - signal cmd_fifo_almost_empty : std_logic := '0'; - - signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_re : std_logic := '0'; - signal write_fifo_we : std_logic := '0'; - signal write_fifo_full : std_logic := '0'; - signal write_fifo_empty : std_logic := '0'; - signal write_fifo_almost_full : std_logic := '0'; - signal write_fifo_almost_empty : std_logic := '0'; - - signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_re : std_logic := '0'; - signal read_fifo_we : std_logic := '0'; - signal read_fifo_full : std_logic := '0'; - signal read_fifo_empty : std_logic := '0'; - signal read_fifo_almost_full : std_logic := '0'; - signal read_fifo_almost_empty : std_logic := '0'; - - signal write_start : std_logic := '1'; - signal read_start : std_logic := '1'; - - alias cmd_fifo_in is cmd_fifo_din(25 downto 24); - alias addr_fifo_in is cmd_fifo_din(23 downto 0); - alias cmd_fifo_out is cmd_fifo_dout(25 downto 24); - alias addr_fifo_out is cmd_fifo_dout(23 downto 0); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- Instantiate synchronous FIFO - inst_command_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2+24 - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => cmd_fifo_almost_full, - fifo_aempty => cmd_fifo_almost_empty, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => write_fifo_almost_full, - fifo_aempty => write_fifo_almost_empty, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => read_fifo_almost_full, - fifo_aempty => read_fifo_almost_empty, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cmd_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_dout; - read_fifo_re <= (not read_fifo_empty) and read_start; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01020304"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"05060708"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000002"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"00001111"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000004"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"22223333"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000006"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"44445555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000008"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"66667777"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"88889999"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAABBBB"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000e"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"CCCCDDDD"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"EEEEFFFF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000012"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - --- wait until rising_edge(clk_out) and u_busy='0'; --- write_start <= '1'; --- wait until rising_edge(clk_out) and write_fifo_empty='1'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01234567"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"89ABCDEF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000016"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"11223344"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"55667788"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"99990000"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAA5555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001A"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001C"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - - wait for 40*CLK_PERIOD; - read_start <= '1'; - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd deleted file mode 100644 index 961b58e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd +++ /dev/null @@ -1,322 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_write_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_read_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd deleted file mode 100644 index 286fb33..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd +++ /dev/null @@ -1,320 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd deleted file mode 100644 index 5f96aa3..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd +++ /dev/null @@ -1,319 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd deleted file mode 100644 index c60d600..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd +++ /dev/null @@ -1,333 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_in : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_dm_rd_out : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm_wr_in => u_dm, - u_dm_rd_in => u_dm_rd_in, - u_dm_rd_out => u_dm_rd_out, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_READ; - u_write_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - u_read_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_WRITE; - u_read_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd deleted file mode 100644 index 95ffa58..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,385 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend is -end; - -architecture struct of tb_sdram_ctrl_frontend is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal addr : user_addr_t := (others => '0'); - signal r_wn : std_logic := '0'; - signal en : std_logic := '0'; - signal busy : std_logic; - signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111"; - signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal dout_vld : std_logic; - signal dout_re : std_logic; - signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6, - fifo_depth => 4 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - busy => busy, - en => en, - r_wn => r_wn, - be => be, - addr => addr, - din => din, - dout => dout, - dout_re => dout_re, - dout_vld => dout_vld, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(clk_out) - begin - if rising_edge(clk_out) then - if dout_vld = '1' then - dout_reg <= dout; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - dout_re <= dout_vld; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '0'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '1'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - en <= '1'; - r_wn <= '0'; - din <= X"01020304"; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"05060708"; - addr <= X"000002"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"00001111"; - addr <= X"000004"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"22223333"; - addr <= X"000006"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"44445555"; - addr <= X"000008"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"66667777"; - addr <= X"00000a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"88889999"; - addr <= X"00000c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAABBBB"; - addr <= X"00000e"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCDDDD"; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"EEEEFFFF"; - addr <= X"000012"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"FFFFFFFF"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"87CCCCCC"; - be <= "1000"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CC65CCCC"; - be <= "0100"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCC43CC"; - be <= "0010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"89ABCDEF"; - addr <= X"000016"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCCC21"; - be <= "0001"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55555555"; - be <= "1010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAAAAAA"; - be <= "0101"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - be <= "1111"; - en <= '1'; - r_wn <= '0'; - din <= X"11223344"; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55667788"; - addr <= X"00001a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"99990000"; - addr <= X"00001c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAA5555"; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001A"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001C"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj b/lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj deleted file mode 100644 index 334db73..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/ise9/sdram_ctrl_top.prj +++ /dev/null @@ -1,13 +0,0 @@ -vhdl work "../../../misc/utils_pkg.vhd" -vhdl work "../src/sdram_config.vhd" -vhdl work "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../src/sdram_types.vhd" -vhdl work "../../../FIFO/src/sync_fifo_ctrl.vhd" -vhdl work "../../../FIFO/src/dpram.vhd" -vhdl work "../src/sdram_ctrl.vhd" -vhdl work "../src/sdram_cmd.vhd" -vhdl work "../src/reset_virtex4.vhd" -vhdl work "../src/fifo_sync.vhd" -vhdl work "../src/ddr_phy_virtex4.vhd" -vhdl work "../src/clockgen_virtex4.vhd" -vhdl work "../src/sdram_ctrl_top.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk b/lib/SDRAM/ddr_sdr_v1_5/sim/ModelSim SE .lnk deleted file mode 100644 index 7529afdc6c1615f1c9bfc9531f8280b8d69bbc68..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1473 zcmdT^TS!x39RF{#P$-zVz{F}vt07^VAJ!rRHa3Oc_=v{Xp;GPWu-w8{0{Ii;Pq z@aq2QY}#osTwPDa)fP@R`o`>~5^>`(zpBh7SA%nZgS8W)9i*ZxTDmo6I@{+l*AHl5 z<)RP;sRg)+0{Hxp6058=uZu*R9F}|bJNJVm-B{@!vc%ja2txshVUXC|hmEkMR+INZJ4&b$2hfZP{$^pH*re zpBT6jZF+JiulQ;1nFq9P$k+Y;Z+Z=miY_E|;mPqz! zgsNa~PVVZArntncN+nJZ`*pb>-;*%}HQ`%EUzje#3kxY_{Nze30qC7iDTm?nY-6R! zzXoOQEXP{Lh%1K%VG}m?2AM8ihhnN21J%Q3w; fLJyH|q7OE({es1O4i#3#*wnAWOl$=WrXzm^$C@OA diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo deleted file mode 100644 index d420b71..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend64_wb -do {tb_sdram_ctrl_frontend64_wb.wdo} -view wave -view structure -view signals -run 200us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo deleted file mode 100644 index 419220a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo +++ /dev/null @@ -1,50 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt -add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {34438503 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {210 us} diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo deleted file mode 100644 index be11690..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../misc/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend_wb.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend_wb.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend_wb -do {tb_sdram_ctrl_frontend_wb.wdo} -view wave -view structure -view signals -run 200us diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo deleted file mode 100644 index 354a054..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo +++ /dev/null @@ -1,50 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt -add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {34438503 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {210 us} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd deleted file mode 100644 index 2920643..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,370 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - sdr_data_req_r : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - sdr_data_req_r <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_req_r <= phy_ctrl.re; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd deleted file mode 100644 index 4f799c5..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Reset generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity reset is - port - ( - clk : in std_logic; - rst_in : in std_logic; - rst_out : out std_logic - ); -end; - -architecture tech of reset is - - signal rst : std_logic; - signal shift_pipe : std_logic_vector(3 downto 0); - attribute KEEP : string; - attribute KEEP of shift_pipe : signal is "TRUE"; - -begin - - rst <= shift_pipe(0); - -bufg_reset: bufg - port map - ( - o => rst_out, - i => rst - ); - -fdp0: fdp - generic map - ( - init => '1' - ) - port map - ( - d => rst_in, - c => clk, - pre => '0', - q => shift_pipe(3) - ); - -fdp1: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(3), - c => clk, - pre => '0', - q => shift_pipe(2) - ); - -fdp2: fdp - generic map - ( - init => '1' - ) - port map - ( - d => shift_pipe(2), - c => clk, - pre => '0', - q => shift_pipe(1) - ); - -fdp3: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(1), - c => clk, - pre => '0', - q => shift_pipe(0) - ); - -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd deleted file mode 100644 index d3d11ce..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ /dev/null @@ -1,268 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic (BL : natural := 2); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 10; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 10; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd deleted file mode 100644 index b0a6253..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 1; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd deleted file mode 100644 index 42ad1c9..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd +++ /dev/null @@ -1,491 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : natural := 100E6; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH_PRE, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - signal bank_addr_last : bank_addr_t; - signal row_addr_last : row_addr_t; - signal col_addr_last : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal bank_active_reg : unsigned(0 to 3); - signal bank_is_active : std_logic; - signal bank_activate : std_logic; - signal bank_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - bank_is_active <= bank_active_reg(to_integer(u_bank_addr)); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, bank_addr_last, row_addr_last, refresh_request, bank_is_active) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - bank_activate <= '0'; - bank_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - bank_clr <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if refresh_request = '1' then - st_ctrl_next <= REFRESH_PRE; - else - u_busy <= '0'; - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode <= u_bank_addr & u_row_addr; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if u_cmd_we = '1' then - addr_reg_load_en <= '1'; - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) then - st_ctrl_next <= USER_WRITE_PRE; - elsif bank_is_active = '0' then - st_ctrl_next <= USER_WRITE_ACT; - elsif sdr_cmd_busy = '1' then - st_ctrl_next <= USER_WRITE; - else - sdr_cmd_we <= '1'; - end if; - when UCMD_READ => - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) then - st_ctrl_next <= USER_READ_PRE; - elsif bank_is_active = '0' then - st_ctrl_next <= USER_READ_ACT; - elsif sdr_cmd_busy = '1' then - st_ctrl_next <= USER_READ; - else - sdr_cmd_we <= '1'; - end if; - when others => null; - end case; - end if; - end if; - - when USER_WRITE_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; - sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - bank_activate <= '1'; - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; - sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - bank_activate <= '1'; - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH_PRE => - bank_clr <= '1'; - sdr_cmd <= SD_PRE; --- sdr_mode <= bank_addr_last & row_addr_last; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= REFRESH; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -bank_active_register: - process (clk) - begin - if rising_edge(clk) then - if bank_clr = '1' then - bank_active_reg <= (others => '0'); -- assumes PRE_ALL !!!!!!!!!!!!! - elsif bank_activate = '1' then - bank_active_reg(to_integer(bank_addr_reg)) <= '1'; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_last <= bank_addr_reg; - row_addr_last <= row_addr_reg; - col_addr_last <= col_addr_reg; - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd deleted file mode 100644 index 6f8a5fd..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ /dev/null @@ -1,272 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend64_wb is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - fifo_depth : integer := 4 - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - CLK270_I : in STD_LOGIC; - CLK270VAR_I : in STD_LOGIC; - - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(SDR_DM_WIDTH-1 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0); - DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend64_wb; - -architecture struct of sdram_ctrl_frontend64_wb is - - -- Number of user data words for simulation - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - - alias write_fifo_dm_in is write_fifo_din(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - alias write_fifo_data_in is write_fifo_din(SDR_DATA_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - alias write_fifo_data_out is write_fifo_dout(SDR_DATA_WIDTH-1 downto 0); - - alias read_fifo_data_in is read_fifo_din(SDR_DATA_WIDTH-1 downto 0); - alias read_fifo_data_out is read_fifo_dout(SDR_DATA_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => write_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => read_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => RST_I, - sys_clk0_in => CLK_I, - - sys_clk270_in => CLK270_I, - capture_clk270_in => CLK270VAR_I, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm_wr_in, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - SRDY_O <= rdy; - ACK_O <= not (read_fifo_empty); - DAT_O <= read_fifo_data_out; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I; - write_fifo_we <= STB_I and WE_I and rdy; - write_fifo_data_in <= DAT_I; - write_fifo_dm_in <= not SEL_I; - cat_fifo_we <= STB_I and rdy; - cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; - addr_fifo_in <= ADDR_I(25 downto 3) & "0"; - tag_fifo_in <= "000" & ADDR_I(2); - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_wr_in <= (write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-5 downto SDR_DATA_WIDTH) & write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH+4)) when u_tag_wr(0) = '1' else write_fifo_dm_out(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto SDR_DATA_WIDTH); - u_tag_in <= tag_fifo_out; - u_data_w <= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when u_tag_wr(0) = '1' else write_fifo_data_out(63 downto 0); - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= (u_data_r(31 downto 0) & u_data_r(63 downto 32)) when u_tag_rd(0) = '1' else u_data_r(63 downto 0); - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd deleted file mode 100644 index 8c617d8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ /dev/null @@ -1,272 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend_wb is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - fifo_depth : integer := 4 - ); - Port - ( - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - CLK270_I : in STD_LOGIC; - CLK270VAR_I : in STD_LOGIC; - - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend_wb; - -architecture struct of sdram_ctrl_frontend_wb is - - -- Number of user data words for simulation - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal rdy : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(35 downto 0); - signal write_fifo_dout : unsigned(35 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(31 downto 0); - signal read_fifo_dout : unsigned(31 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-1 downto 4); - alias write_fifo_dm_in is write_fifo_din(3 downto 0); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-1 downto 4); - alias write_fifo_dm_out is write_fifo_dout(3 downto 0); - - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-1 downto 0); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => write_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => read_fifo_din'length - ) - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => RST_I, - sys_clk0_in => CLK_I, - - sys_clk270_in => CLK270_I, - capture_clk270_in => CLK270VAR_I, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm_wr_in, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - SRDY_O <= rdy; - ACK_O <= not (read_fifo_empty); - DAT_O <= read_fifo_data_out; - rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full) and CYC_I; - write_fifo_we <= STB_I and WE_I and rdy; - write_fifo_data_in <= DAT_I; - write_fifo_dm_in <= not SEL_I; - cat_fifo_we <= STB_I and rdy; - cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; - addr_fifo_in <= ADDR_I(24 downto 2) & "0"; - tag_fifo_in <= "000" & ADDR_I(25); - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm_wr_in <= ("1111" & write_fifo_dm_out) when u_tag_wr(0) = '0' else (write_fifo_dm_out & "1111"); - u_tag_in <= tag_fifo_out; - u_data_w <= write_fifo_data_out & write_fifo_data_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - read_fifo_re <= (not read_fifo_empty) and MRDY_I; - read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r(31 downto 0) when u_tag_rd(0) = '0' else u_data_r(63 downto 32); - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd deleted file mode 100644 index 114af81..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,244 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk0_in : in STD_LOGIC; - sys_clk270_in : in STD_LOGIC; - capture_clk270_in : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_data_req_r : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal ctrl_rst : std_logic; - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_ADDR_WIDTH : positive := 2; - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out)); - - --------------------------------- - inst_reset: entity work.reset - port map - ( - clk => sys_clk0_in, - rst_in => sys_rst_in, - rst_out => ctrl_rst - ); - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => 100E6, - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => sys_clk0_in, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => CMD_FIFO_ADDR_WIDTH, - data_width => CMD_FIFO_DATA_WIDTH, - almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1), - almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1) - ) - PORT MAP - ( - rst => ctrl_rst, - clk => sys_clk0_in, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => sys_clk0_in, - u_tag_in => tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => col_fifo_out, - mode_word => mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => ctrl_rst, - sys_clk0 => sys_clk0_in, - sys_clk270 => sys_clk270_in, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => capture_clk270_in, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_req_r => u_data_req_r, - sdr_data_w => u_data_wr, - sdr_dm => u_dm, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd deleted file mode 100644 index d235d75..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd +++ /dev/null @@ -1,133 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - subtype cycle_cnt_t is natural range 0 to 10; - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd deleted file mode 100644 index 1805da3..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd +++ /dev/null @@ -1,860 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend64_wb is -end; - -architecture struct of tb_sdram_ctrl_frontend64_wb is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal CLK_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(SDR_DM_WIDTH-1 downto 0); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal DAT_O : unsigned(SDR_DATA_WIDTH-1 downto 0); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - signal sddat : unsigned(31 downto 0) := (others => '-'); - signal sdsel : unsigned(3 downto 0) := (others => '1'); - - type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst); - signal sd_cmd : sd_cmd_t; - -begin - - process(part_cs_n, part_ras_n, part_cas_n, part_we_n) - variable cmd : unsigned (2 downto 0); - - begin - cmd := part_ras_n & part_cas_n & part_we_n; - sd_cmd <= nop; - if part_cs_n = '0' then - case cmd is - when "000" => - sd_cmd <= lmr; - when "001" => - sd_cmd <= ar; - when "010" => - sd_cmd <= pre; - when "011" => - sd_cmd <= act; - when "100" => - sd_cmd <= write; - when "101" => - sd_cmd <= read; - when "110" => - sd_cmd <= bst; - when "111" => - sd_cmd <= nop; - - when others => - sd_cmd <= nop; - - end case; - end if; - end process; - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - sys1_phaseshift => 0, - frequency_hz => 100E6 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => clk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0° - sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); - - - clk_fb <= part_clk_p after 1 ns; - RST_O <= not locked; - DAT_O <= X"DEADBEEF" & sddat; - SEL_O <= "0000" & sdsel; - - -- DDR SDRAM Controller Core - sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => 100E6, - fifo_depth => 3 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - CLK270_I => CLK270_O, - CLK270VAR_I => CLK270VAR_O, - - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(15 downto 0)), - dqs => std_logic_vector(part_dqs(1 downto 0)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(1 downto 0)) - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(31 downto 16)), - dqs => std_logic_vector(part_dqs(3 downto 2)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(3 downto 2)) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I(31 downto 0); - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - - wait until RST_O = '0'; - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sddat <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 8192 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "0011"; - ADDR_O <= X"0000_0080"; - sddat <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"1111_0000"; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"2222_0000"; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"3333_0000"; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - sdsel <= "1111"; - sddat <= X"4444_0000"; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - sddat <= sddat + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd deleted file mode 100644 index 385985e..0000000 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd +++ /dev/null @@ -1,855 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend_wb is -end; - -architecture struct of tb_sdram_ctrl_frontend_wb is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal CLK_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - type sd_cmd_t is (nop, lmr, ar, pre, act, write, read, bst); - signal sd_cmd : sd_cmd_t; - -begin - - process(part_cs_n, part_ras_n, part_cas_n, part_we_n) - variable cmd : unsigned (2 downto 0); - - begin - cmd := part_ras_n & part_cas_n & part_we_n; - sd_cmd <= nop; - if part_cs_n = '0' then - case cmd is - when "000" => - sd_cmd <= lmr; - when "001" => - sd_cmd <= ar; - when "010" => - sd_cmd <= pre; - when "011" => - sd_cmd <= act; - when "100" => - sd_cmd <= write; - when "101" => - sd_cmd <= read; - when "110" => - sd_cmd <= bst; - when "111" => - sd_cmd <= nop; - - when others => - sd_cmd <= nop; - - end case; - end if; - end process; - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - sys1_phaseshift => 0, - frequency_hz => 100E6 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => clk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0° - sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); - - - clk_fb <= part_clk_p after 1 ns; - RST_O <= not locked; - - -- DDR SDRAM Controller Core - sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => 100E6, - fifo_depth => 3 - ) - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - CLK270_I => CLK270_O, - CLK270VAR_I => CLK270VAR_O, - - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(15 downto 0)), - dqs => std_logic_vector(part_dqs(1 downto 0)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(1 downto 0)) - ); - - -- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map - ( - dq => std_logic_vector(part_data(31 downto 16)), - dqs => std_logic_vector(part_dqs(3 downto 2)), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm(3 downto 2)) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - - wait until RST_O = '0'; - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 8192 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "0011"; - ADDR_O <= X"0000_0080"; - DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - end loop; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - for k in 0 to 3 loop - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ --- wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_1C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - end loop; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SSRAM/sim/ModelSim SE .lnk b/lib/SSRAM/sim/ModelSim SE .lnk deleted file mode 100644 index 935209c2310801e57ad76e532c79f82bfed1afce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1447 zcmdT^T}YEr7=ETR6bck4m`JV2iUm`r+58DyYAHE4Tre+2W^U;x&V^fU!IurZ$Zq;E z2{H<^3#FTGguF=wDXc4rs4lD|qVfl|5`!q}Ip4RfANslJrgM0I&U@aU=e*xJUo`-Y zE{+@+S2*@w;8IUL`Q%hUKQXDfdOa{NB<^eFx081@IJZ{u)TsV3Zqewl(LQ6F($5u1 z$pcRku_Gtv%6ep%6}e(g-;_PbRTj>|SH&r?*V^{gS~_VmARbyQjovn&>2ns=4C?4* zM>~9IB5#0~(?eT2Y9blN%pav>SZ(DM)dxCrjixf>M{WL!j`+Q23e0%laOKl=EbA*G&>qv{uM`k{AMEIw_uXYTNKoGNn^$ zbNhmRu)FqlUsHR7*Xwav1%QC3vAMp$XlisRr*QpZHIyh@# zVW(VB(H&B2_SaF0(Q@pl6!5gG3-Tk5?&X#(o2mw0#OWR#AH3Yr@c2$@_S2Np50G}# z-TnS=`#K(oXYJ2YKAxk>T3>0iR%HEzxB^*3^!v`m;QZH07W-~PIVyOk9H`=|9+k9M zY5DW{d*o1R5_Y3UE{eS3<<-%D-iz((U*eZ}qxD4n={E*#$?AF8Li!%h2<;+xdWCXU z-4pkDfp%SQSQfe%b+ZQT&5>{{Hs_rhr{zV_FRHrg2~16-qJ;j1{ku9l7F^+H@d?U1 z5kDw9?WIviN;7Bahf#>Vs4mYNw4oC#!7!XFZq64xZ59~YyWc*#9Wc9&d5x@YW?XD;1R-m&nB<`6Z)#$h~Uz45*-*-qat93tjm RW=T-I?F7Dwt(3k<=C3#96%+sf diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo deleted file mode 100644 index 9aafbb0..0000000 --- a/lib/SSRAM/sim/tb_ssram_frontend_wb.fdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -# Top and TB -vcom -explicit -93 "../src/package_utility.vhd" -vcom -explicit -93 "../src/CY7C1354B.vhd" -vcom -explicit -93 "../src/ssram_frontend_wb.vhd" -vcom -explicit -93 "../src/tb_ssram_frontend_wb.vhd" - -vsim -t 1ps -lib work tb_ssram_frontend_wb -do {tb_ssram_frontend_wb.wdo} -view wave -view structure -view signals -run 6us - \ No newline at end of file diff --git a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo b/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo deleted file mode 100644 index 71718ed..0000000 --- a/lib/SSRAM/sim/tb_ssram_frontend_wb.wdo +++ /dev/null @@ -1,47 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ssram_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/rst_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/cyc_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/stb_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/we_o -add wave -noupdate -format Literal /tb_ssram_frontend_wb/sel_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ack_i -add wave -noupdate -format Logic /tb_ssram_frontend_wb/mrdy_o -add wave -noupdate -format Logic /tb_ssram_frontend_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_d -add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_dp -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/ssram_a -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_cke_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_adv -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_mode -add wave -noupdate -format Literal /tb_ssram_frontend_wb/ssram_bw_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_we_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_oe_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_ce_n -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_zz -add wave -noupdate -format Literal -radix hexadecimal /tb_ssram_frontend_wb/dout_reg -add wave -noupdate -format Literal -radix unsigned /tb_ssram_frontend_wb/dout_cnt -add wave -noupdate -format Literal /tb_ssram_frontend_wb/inst_ssram_frontend_wb/vld_pipe -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk_fb -add wave -noupdate -format Logic /tb_ssram_frontend_wb/ssram_clk -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1343191 ps} 0} {{Cursor 2} {178651436 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {6300 ns} diff --git a/lib/SSRAM/src/CY7C1354B.vhd b/lib/SSRAM/src/CY7C1354B.vhd deleted file mode 100644 index d652656..0000000 --- a/lib/SSRAM/src/CY7C1354B.vhd +++ /dev/null @@ -1,388 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: CY7C1354B.VHD --- Version: 2.0 --- Date: Nov 22nd, 2004 --- Model: BUS Functional --- --- --- Author: RKF --- Company: Cypress Semiconductor --- Model: CY7C1354B (256k x 36) --- Mode: Pipelined --- --- Description: NoBL SRAM VHDL Model --- --- Limitation: None --- --- Note: - BSDL Model available separately --- - Set simulator resolution to "ps" timescale --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 2004 Cypress Semiconductor --- All rights reserved --- --- Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor --- --- Rev Author Date Changes --- --- -------- ------- ---------- --- 2.0 RKF 11/22/2004 - Second Release --- - Fully Tested with New Test Bench and Test Vectors ------------------------------------------------------------------------------------------ - -LIBRARY ieee,work; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_unsigned.all; - Use IEEE.Std_Logic_Arith.all; --- Use work.all; - USE work.package_utility.all; - -ENTITY cy7c1354 IS - - GENERIC ( - - -- Constant parameters - addr_bits : INTEGER := 18; - data_bits : INTEGER := 32; - par_bits : INTEGER := 4; - - -- Timing parameters for -5 (225 Mhz) --- tCYC : TIME := 4.4 ns; --- tCH : TIME := 1.8 ns; --- tCL : TIME := 1.8 ns; --- tCO : TIME := 2.8 ns; --- tAS : TIME := 1.4 ns; --- tCENS : TIME := 1.4 ns; --- tWES : TIME := 1.4 ns; --- tDS : TIME := 1.4 ns; --- tAH : TIME := 0.4 ns; --- tCENH : TIME := 0.4 ns; --- tWEH : TIME := 0.4 ns; --- tDH : TIME := 0.4 ns - - - - -- Timing parameters for -6 (200 Mhz) - --tCYC : TIME := 5.0 ns; - --tCH : TIME := 2.0 ns; - --tCL : TIME := 2.0 ns; - --tCO : TIME := 3.2 ns; - --tAS : TIME := 1.5 ns; - --tCENS : TIME := 1.5 ns; - --tWES : TIME := 1.5 ns; - --tDS : TIME := 1.5 ns; - --tAH : TIME := 0.5 ns; - --tCENH : TIME := 0.5 ns; - --tWEH : TIME := 0.5 ns; - --tDH : TIME := 0.5 ns - - - -- Timing parameters for -7 (166 Mhz) - tCYC : TIME := 6.0 ns; - tCH : TIME := 2.4 ns; - tCL : TIME := 2.4 ns; - tCO : TIME := 3.5 ns; - tAS : TIME := 1.5 ns; - tCENS : TIME := 1.5 ns; - tWES : TIME := 1.5 ns; - tDS : TIME := 1.5 ns; - tAH : TIME := 0.5 ns; - tCENH : TIME := 0.5 ns; - tWEH : TIME := 0.5 ns; - tDH : TIME := 0.5 ns - - - - ); - - -- Port Declarations - PORT ( - Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O - Dpq : INOUT STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0); -- Data parity I/O - Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address - Mode : IN STD_LOGIC := '1'; -- Burst Mode - Clk : IN STD_LOGIC; -- Clk - CEN_n : IN STD_LOGIC; -- CEN# - AdvLd_n : IN STD_LOGIC; -- Adv/Ld# - Bwa_n : IN STD_LOGIC; -- Bwa# - Bwb_n : IN STD_LOGIC; -- BWb# - Bwc_n : IN STD_LOGIC; -- Bwc# - Bwd_n : IN STD_LOGIC; -- BWd# - Rw_n : IN STD_LOGIC; -- RW# - Oe_n : IN STD_LOGIC; -- OE# - Ce1_n : IN STD_LOGIC; -- CE1# - Ce2 : IN STD_LOGIC; -- CE2 - Ce3_n : IN STD_LOGIC; -- CE3# - Zz : IN STD_LOGIC -- Snooze Mode - ); -END cy7c1354; - -ARCHITECTURE behave OF cy7c1354 IS - SIGNAL ce : STD_LOGIC := '0'; - SIGNAL doe : STD_LOGIC := '0'; - SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL dout_p : STD_LOGIC_VECTOR ((par_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z'); - -BEGIN - - - ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2; - - doe <= NOT(Oe_n) AND NOT(Zz); - - -- Output Buffers - WITH doe SELECT - Dq <= TRANSPORT dout AFTER (tCO) WHEN '1', - (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; - - WITH doe SELECT - Dpq <= TRANSPORT dout_p AFTER (tCO) WHEN '1', - (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS; - - - -- Check for Clock Timing Violation - clk_check : PROCESS - VARIABLE clk_high, clk_low : TIME := 0 ns; - BEGIN - WAIT ON Clk; - IF Clk = '1' AND NOW >= tCYC THEN - ASSERT (NOW - clk_low >= tCH) - REPORT "Clk width low - tCH violation" - SEVERITY ERROR; - ASSERT (NOW - clk_high >= tCYC) - REPORT "Clk period high - tCYC violation" - SEVERITY ERROR; - clk_high := NOW; - ELSIF Clk = '0' AND NOW /= 0 ns THEN - ASSERT (NOW - clk_high >= tCL) - REPORT "Clk width high - tCL violation" - SEVERITY ERROR; - ASSERT (NOW - clk_low >= tCYC) - REPORT "Clk period low - tCYC violation" - SEVERITY ERROR; - clk_low := NOW; - END IF; - END PROCESS; - - -- Check for Setup Timing Violation - setup_check : PROCESS - BEGIN - WAIT ON Clk; - IF Clk = '1' and (Ce1_n = '0' and Ce2 = '1' and Ce3_n = '0') THEN - ASSERT (Addr'LAST_EVENT >= tAS) - REPORT "Addr - tAS violation" - SEVERITY ERROR; - ASSERT (CEN_n'LAST_EVENT >= tCENS) - REPORT "CKE# - tCENS violation" - SEVERITY ERROR; - ASSERT (Ce1_n'LAST_EVENT >= tWES) - REPORT "CE1# - tWES violation" - SEVERITY ERROR; - ASSERT (Ce2'LAST_EVENT >= tWES) - REPORT "CE2 - tWES violation" - SEVERITY ERROR; - ASSERT (Ce3_n'LAST_EVENT >= tWES) - REPORT "CE3# - tWES violation" - SEVERITY ERROR; - ASSERT (AdvLd_n'LAST_EVENT >= tWES) - REPORT "ADV/LD# - tWES violation" - SEVERITY ERROR; - ASSERT (Rw_n'LAST_EVENT >= tWES) - REPORT "RW# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwa_n'LAST_EVENT >= tWES) - REPORT "BWa# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwb_n'LAST_EVENT >= tWES) - REPORT "BWb# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwc_n'LAST_EVENT >= tWES) - REPORT "BWc# - tWES violation" - SEVERITY ERROR; - ASSERT (Bwd_n'LAST_EVENT >= tWES) - REPORT "BWd# - tWES violation" - SEVERITY ERROR; - ASSERT (Dq'LAST_EVENT >= tDS) - REPORT "Dq - tDS violation" - SEVERITY ERROR; - END IF; - END PROCESS; - - -- Check for Hold Timing Violation - hold_check : PROCESS - BEGIN - WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH); - IF Clk'DELAYED(tAH) = '1' THEN - ASSERT (Addr'LAST_EVENT > tAH) - REPORT "Addr - tAH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tCENH) = '1' THEN - ASSERT (CEN_n'LAST_EVENT > tCENH) - REPORT "CKE# - tCENH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tDH) = '1' THEN - ASSERT (Dq'LAST_EVENT > tDH) - REPORT "Dq - tDH violation" - SEVERITY ERROR; - END IF; - IF Clk'DELAYED(tWEH) = '1' THEN - ASSERT (Ce1_n'LAST_EVENT > tWEH) - REPORT "CE1# - tWEH violation" - SEVERITY ERROR; - ASSERT (Ce2'LAST_EVENT > tWEH) - REPORT "CE2 - tWEH violation" - SEVERITY ERROR; - ASSERT (Ce3_n'LAST_EVENT > tWEH) - REPORT "CE3 - tWEH violation" - SEVERITY ERROR; - ASSERT (AdvLd_n'LAST_EVENT > tWEH) - REPORT "ADV/LD# - tWEH violation" - SEVERITY ERROR; - ASSERT (Rw_n'LAST_EVENT > tWEH) - REPORT "RW# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwa_n'LAST_EVENT > tWEH) - REPORT "BWa# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwb_n'LAST_EVENT > tWEH) - REPORT "BWb# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwc_n'LAST_EVENT > tWEH) - REPORT "BWc# - tWEH violation" - SEVERITY ERROR; - ASSERT (Bwd_n'LAST_EVENT > tWEH) - REPORT "BWd# - tWEH violation" - SEVERITY ERROR; - END IF; - - END PROCESS; - - -- Main Program - main : PROCESS - - TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (((data_bits+par_bits) / 4) - 1 DOWNTO 0); - - VARIABLE Addr_in : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE first_Addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0'); - VARIABLE Addr_read : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE Addr_write : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0'); - VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0'; - VARIABLE bank0 : memory_array; - VARIABLE bank1 : memory_array; - VARIABLE bank2 : memory_array; - VARIABLE bank3 : memory_array; - - VARIABLE ce_in : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE rw_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111"; - VARIABLE bwa_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwb_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwc_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bwd_in : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000"; - VARIABLE bcnt : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - - BEGIN - WAIT ON Clk; - IF Clk'EVENT AND Clk = '1' THEN - IF CEN_n = '0' AND Zz = '0' THEN - -- Write Address Register - Addr_write := Addr_read; - - -- Read Address Register - Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0; - - -- Address Register - IF AdvLd_n = '0' and ce = '1' THEN - Addr_in := Addr; - first_Addr := Addr(1 DOWNTO 0); - bcnt := Addr(1 DOWNTO 0); - END IF; - - - -- Burst Logic - IF Mode = '0' AND AdvLd_n = '1' THEN - bcnt := bcnt + 1; - ELSIF Mode = '1' AND AdvLd_n = '1' THEN - IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN - bcnt := bcnt + 1; - ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN - bcnt := bcnt - 1; - END IF; - END IF; - - - bAddr1 := bcnt (1); - bAddr0 := bcnt (0); - - -- Read Logic - ce_in (0) := ce_in (1); - - IF AdvLd_n = '0' THEN - ce_in (1) := ce; - END IF; - - rw_in (0) := rw_in (1); - rw_in (1) := rw_in (2); - - IF AdvLd_n = '0' THEN - rw_in (2) := NOT(ce AND NOT(Rw_n)); - END IF; - - -- Write Registry and Data Coherency Control Logic - bwa_in (0) := bwa_in (1); - bwb_in (0) := bwb_in (1); - bwc_in (0) := bwc_in (1); - bwd_in (0) := bwd_in (1); - bwa_in (1) := bwa_in (2); - bwb_in (1) := bwb_in (2); - bwc_in (1) := bwc_in (2); - bwd_in (1) := bwd_in (2); - bwa_in (2) := Bwa_n; - bwb_in (2) := Bwb_n; - bwc_in (2) := Bwc_n; - bwd_in (2) := Bwd_n; - - -- Write Data to Memory - IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN - bank0 (CONV_INTEGER1 (Addr_write)) := Dpq(0) & Dq ( (data_bits / 4) - 1 DOWNTO 0); - END IF; - IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN - bank1 (CONV_INTEGER1 (Addr_write)) := Dpq(1) & Dq ((data_bits / 2 - 1) DOWNTO (data_bits / 4)); - END IF; - IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN - bank2 (CONV_INTEGER1 (Addr_write)) := Dpq(2) & Dq ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)); - END IF; - IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN - bank3 (CONV_INTEGER1 (Addr_write)) := Dpq(3) & Dq (data_bits - 1 DOWNTO (3 * (data_bits / 4))); - END IF; - END IF; - - Addr_read_sig <= Addr_read; - - -- Read Data from Memory Array - IF ce_in (0) = '1' AND rw_in (1) = '1' THEN - dout ((data_bits / 4) - 1 DOWNTO 0) <= bank0 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout ((data_bits / 2 - 1) DOWNTO (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout ((3 * (data_bits / 4)) - 1 DOWNTO (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout (data_bits - 1 DOWNTO (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))( (data_bits / 4) - 1 DOWNTO 0); - dout_p(0) <= bank0 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(1) <= bank1 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(2) <= bank2 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - dout_p(3) <= bank3 (CONV_INTEGER1 (Addr_read))(data_bits / 4); - ELSE - dout <= (OTHERS => 'Z'); - dout_p <= (OTHERS => 'Z'); - END IF; - END IF; - END PROCESS; - -END behave; - - - diff --git a/lib/SSRAM/src/package_utility.vhd b/lib/SSRAM/src/package_utility.vhd deleted file mode 100644 index 9fb543f..0000000 --- a/lib/SSRAM/src/package_utility.vhd +++ /dev/null @@ -1,73 +0,0 @@ ---**************************************************************** ---** MODEL : package_utility ** ---** COMPANY : Cypress Semiconductor ** ---** REVISION: 1.0 Created new package utility model ** ---** ** ---**************************************************************** -Library ieee,work; - Use ieee.std_logic_1164.all; - Use IEEE.Std_Logic_Arith.all; - Use IEEE.std_logic_TextIO.all; - --- Use work.package_timing.all; - -Library Std; - Use STD.TextIO.all; - -Package package_utility is - -FUNCTION convert_string( S: in STRING) RETURN STD_LOGIC_VECTOR; -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER; - -End; -- package package_utility - -Package body package_utility is - - ------------------------------------------------------------------------------------------------- ---Converts string into std_logic_vector ------------------------------------------------------------------------------------------------- - -FUNCTION convert_string(S: in STRING) RETURN STD_LOGIC_VECTOR IS - VARIABLE result : STD_LOGIC_VECTOR(S'RANGE); - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '0' THEN - result(i) := '0'; - ELSIF S(i) = '1' THEN - result(i) := '1'; - ELSIF S(i) = 'X' THEN - result(i) := 'X'; - ELSE - result(i) := 'Z'; - END IF; - END LOOP; - RETURN result; -END convert_string; - ------------------------------------------------------------------------------------------------- ---Converts std_logic_vector into integer ------------------------------------------------------------------------------------------------- - -FUNCTION CONV_INTEGER1(S : STD_LOGIC_VECTOR) RETURN INTEGER IS - VARIABLE result : INTEGER := 0; - BEGIN - FOR i IN S'RANGE LOOP - IF S(i) = '1' THEN - result := result + (2**i); - ELSIF S(i) = '0' THEN - result := result; - ELSE - result := 0; - END IF; - END LOOP; - RETURN result; - END CONV_INTEGER1; - - - - -end package_utility; - - - - diff --git a/lib/SSRAM/src/ssram_frontend_wb.vhd b/lib/SSRAM/src/ssram_frontend_wb.vhd deleted file mode 100644 index 056b328..0000000 --- a/lib/SSRAM/src/ssram_frontend_wb.vhd +++ /dev/null @@ -1,181 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -Library UNISIM; -use UNISIM.vcomponents.all; - -ENTITY ssram_frontend_wb IS - Generic - ( - latency : natural := 2; -- clock cycles - addr_width : natural := 20; - data_width : natural := 32; - parity_width : natural := 4 - ); - Port - ( - -- J-Bus domain - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - - -- Sync SRAM domain - ssram_clk_o : out std_logic; - ssram_clk_fb : in std_logic; - ssram_cke_n : out std_logic; - ssram_ce_n : out std_logic; - ssram_oe_n : out std_logic; - ssram_we_n : out std_logic; - ssram_adv : out std_logic; - ssram_mode : out std_logic; - ssram_zz : out std_logic; - ssram_a : out unsigned(addr_width-1 downto 0); - ssram_d : inout unsigned(data_width-1 downto 0); - ssram_dp : inout unsigned(parity_width-1 downto 0); - ssram_bw_n : out unsigned(3 downto 0) - ); -END ssram_frontend_wb; - -ARCHITECTURE behavior OF ssram_frontend_wb IS - - constant topad : time := 3 ns; - subtype ssram_d_t is unsigned(data_width+parity_width-1 downto 0); - type data_pipe_t is array (latency downto 0) of ssram_d_t; - - signal ssram_clk : std_logic; - signal dcm_locked : std_logic; - signal dcm_clk0 : std_logic; - signal dcm_clk1 : std_logic; - signal data_en : std_logic; - signal drive : std_logic; - signal vld_pipe : unsigned(latency downto 0); - signal drive_pipe : unsigned(latency downto 0); - signal data_pipe : data_pipe_t; - signal ssram_dout : ssram_d_t; - -begin - - SRDY_O <= CYC_I and dcm_locked; - ACK_O <= vld_pipe(vld_pipe'left); - DAT_O(data_width-1 downto 0) <= ssram_d; - - data_en <= CYC_I and STB_I; - ssram_dout <= "0000" & DAT_I(data_width-1 downto 0); - drive <= drive_pipe(drive_pipe'left); - - ssram_clk_o <= ssram_clk after topad; - ssram_cke_n <= not dcm_locked after topad; - ssram_oe_n <= not vld_pipe(vld_pipe'left-1) after topad; - -inst_clock_out : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ssram_clk, -- 1-bit DDR output - C => dcm_clk1, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ssram_bufg: bufg - port map - ( - o => dcm_clk1, - i => dcm_clk0 - ); - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => 10.0 , -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => ssram_clk_fb, -- DCM clock feedback - CLKIN => CLK_I, -- Clock input (from IBUFG, BUFG or DCM) - RST => RST_I -- DCM asynchronous reset input - ); - - -data_valid_pipeline: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - vld_pipe <= (others => '0'); - else - vld_pipe <= vld_pipe(vld_pipe'left-1 downto 0) & (data_en and MRDY_I and not WE_I); - end if; - end if; - end process; - -data_out_pipeline: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ssram_ce_n <= '1' after topad; - ssram_we_n <= '1' after topad; - ssram_adv <= '0' after topad; - ssram_mode <= '0' after topad; - ssram_zz <= '1' after topad; - drive_pipe <= (others => '0'); - elsif dcm_locked = '1' then - ssram_ce_n <= not data_en after topad; - ssram_we_n <= not (WE_I and data_en) after topad; - ssram_adv <= '0' after topad; - ssram_mode <= '0' after topad; - ssram_zz <= '0' after topad; - ssram_a <= ADDR_I(addr_width-1 downto 0) after topad; - ssram_bw_n <= not SEL_I after topad; - drive_pipe <= drive_pipe(drive_pipe'left-1 downto 0) & (data_en and WE_I); - data_pipe <= data_pipe(data_pipe'left-1 downto 0) & ssram_dout; - end if; - end if; - end process; - - ssram_d <= data_pipe(data_pipe'left)(data_width-1 downto 0) after topad when drive = '1' else (others => 'Z') after topad; - ssram_dp <= data_pipe(data_pipe'left)(data_width+parity_width-1 downto data_width) after topad when drive = '1' else (others => 'Z') after topad; - -end behavior; diff --git a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd b/lib/SSRAM/src/tb_ssram_frontend_wb.vhd deleted file mode 100644 index 86f1411..0000000 --- a/lib/SSRAM/src/tb_ssram_frontend_wb.vhd +++ /dev/null @@ -1,457 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -USE work.package_utility.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -ENTITY tb_ssram_frontend_wb IS -END tb_ssram_frontend_wb; - -ARCHITECTURE behavior OF tb_ssram_frontend_wb IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - SIGNAL ssram_d : unsigned (32 - 1 DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL ssram_dp : unsigned (4 - 1 DOWNTO 0) := (OTHERS => 'Z'); - SIGNAL ssram_a : unsigned (20 - 1 DOWNTO 0) := (OTHERS => '0'); - SIGNAL ssram_clk : STD_LOGIC := '0'; - SIGNAL ssram_cke_n : STD_LOGIC; - SIGNAL ssram_adv : STD_LOGIC; - SIGNAL ssram_mode : STD_LOGIC; - SIGNAL ssram_bw_n : unsigned(3 downto 0); - SIGNAL ssram_we_n : STD_LOGIC; - SIGNAL ssram_oe_n : STD_LOGIC; - SIGNAL ssram_ce_n : STD_LOGIC; - SIGNAL ssram_zz : STD_LOGIC; - - SIGNAL ssram_clk_fb : STD_LOGIC; - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - -BEGIN - - ssram_clk_fb <= ssram_clk after 0.5 ns; - -inst_ssram_frontend_wb : entity work.ssram_frontend_wb - GENERIC MAP - ( - addr_width => 20, - data_width => 32, - parity_width => 4 - ) - PORT MAP - ( - -- J-Bus domain - RST_I => RST_O, - CLK_I => CLK_O, - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - - -- Sync SRAM domain - ssram_clk_o => ssram_clk, - ssram_clk_fb => ssram_clk_fb, - ssram_cke_n => ssram_cke_n, - ssram_ce_n => ssram_ce_n, - ssram_oe_n => ssram_oe_n, - ssram_we_n => ssram_we_n, - ssram_adv => ssram_adv, - ssram_mode => ssram_mode, - ssram_zz => ssram_zz, - ssram_a => ssram_a, - ssram_d => ssram_d, - ssram_dp => ssram_dp, - ssram_bw_n => ssram_bw_n - ); - -inst_ssram : entity work.cy7c1354 - -- PORT MAP Declarations - PORT MAP - ( - Dq => STD_LOGIC_VECTOR(ssram_d), -- Data I/O - Dpq => STD_LOGIC_VECTOR(ssram_dp), -- Data I/O - Addr => STD_LOGIC_VECTOR(ssram_a(19 downto 2)), -- Address - Mode => ssram_mode, -- Burst Mode - Clk => ssram_clk, -- Clk - CEN_n => ssram_cke_n, -- CEN# - AdvLd_n => ssram_adv, -- Adv/Ld# - Bwa_n => ssram_bw_n(0), -- Bwa# - Bwb_n => ssram_bw_n(1), -- BWb# - Bwc_n => ssram_bw_n(2), -- Bwc# - Bwd_n => ssram_bw_n(3), -- BWd# - Rw_n => ssram_we_n, -- RW# - Oe_n => ssram_oe_n, -- OE# - Ce1_n => ssram_ce_n, -- CE1# - Ce2 => '1', -- CE2 - Ce3_n => '0', -- CE3# - Zz => ssram_zz - ); - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -STIMULUS: process - - begin - - wait for 5*CLK_PERIOD; - RST_O <= '0'; - - wait until rising_edge(CLK_O); - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "0011"; - ADDR_O <= X"0000_0010"; - DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0010"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 3*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 31 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"1111_0000"; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"2222_0000"; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"3333_0000"; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "1111"; - DAT_O <= X"4444_0000"; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - end loop; - - WE_O <= '0'; - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - ------------------------------------------------------------ - wait for 10*CLK_PERIOD; - ------------------------------------------------------------ - - -- 8-word burst cycle - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - ADDR_O <= X"0000_0400"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - - ADDR_O <= X"0000_0800"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - - ADDR_O <= X"0000_0C00"; - - for i in 0 to 7 loop - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - end loop; - - STB_O <= '0'; - wait until rising_edge(CLK_O) and dout_cnt = 31; - CYC_O <= '0'; - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/sim/ModelSim SE .lnk b/lib/VGA_ctrl/sim/ModelSim SE .lnk deleted file mode 100644 index 0a329502962c27f43d6954378270457c758fb048..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1453 zcmdT^T}V@57=EWGQ7D+WV2RXpz!%PlzBz>Dn0 z%p}Ap%r2B}yfN~|6r!-MB%-=7iipY|v>)jrih90tw$l&&+;r1-c)$1k-rwhY&-Z<` zM5NMWU?!TDX4-ciOC4nOso9wB){N@%)z~8AbdM9?&fHN^?^?-ICHpJ0U8SK-o@ee^ z-GWU}4?oVPohH+z4OCcZ^C?c>guPTGExgv3<+M@x)MN#B9cYMcv!AH)CkT->+xekjE~3*%tsr#-?VPs>>Pfcp?P>>7PTf>R4xFq8 za$@DD8faY5{CWR{Ks7ujx;UOlG5T-oTAbB$ZgxJ2{TSLD4PCvh0b6s#HrA@V5@_>g-tZ zC6_a^q}#%tDG&5}(vIL3e2wS}v!!Km(ZD56uEvv~{sjX!j+mz#%O&|0I16Vr)-gdE zIW!8NsJTx(3(C&Qp#i#(Hqr~&?1f#T6LicN#|fSdb#WL0QIH^yF?Fs XzhJPKLj@IacEi`;PHY1Yr!s#9ePRv0 diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo deleted file mode 100644 index a990d6e..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo +++ /dev/null @@ -1,25 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/clkgen_virtex4.vhd" -vcom -explicit -93 "../src/char_gen.vhd" -vcom -explicit -93 "../src/vga_sync.vhd" -vcom -explicit -93 "../src/vga_timing.vhd" -vcom -explicit -93 "../src/vga_backend.vhd" -vcom -explicit -93 "../src/vga_frontend.vhd" -vcom -explicit -93 "../src/tb_vga_frontend.vhd" -vsim -t 1ps -lib work tb_vga_frontend -view wave -do {tb_vga_frontend.wdo} -view structure -view signals - -run 20ms diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend.wdo deleted file mode 100644 index 744cafd..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend.wdo +++ /dev/null @@ -1,65 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_vga_frontend/clk_o -add wave -noupdate -format Logic /tb_vga_frontend/rst_o -add wave -noupdate -divider Master -add wave -noupdate -format Logic /tb_vga_frontend/cyc_o -add wave -noupdate -format Logic /tb_vga_frontend/stb_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_o -add wave -noupdate -format Literal /tb_vga_frontend/sel_o -add wave -noupdate -format Logic /tb_vga_frontend/we_o -add wave -noupdate -format Logic /tb_vga_frontend/ack_i -add wave -noupdate -format Logic /tb_vga_frontend/mrdy_o -add wave -noupdate -format Logic /tb_vga_frontend/srdy_i -add wave -noupdate -divider Slave -add wave -noupdate -format Logic /tb_vga_frontend/cyc_i -add wave -noupdate -format Logic /tb_vga_frontend/stb_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend/addr_i -add wave -noupdate -format Literal /tb_vga_frontend/sel_i -add wave -noupdate -format Logic /tb_vga_frontend/we_i -add wave -noupdate -format Logic /tb_vga_frontend/ack_o -add wave -noupdate -format Logic /tb_vga_frontend/mrdy_i -add wave -noupdate -format Logic /tb_vga_frontend/srdy_o -add wave -noupdate -divider VGA -add wave -noupdate -format Logic /tb_vga_frontend/vga_clk_out -add wave -noupdate -format Logic /tb_vga_frontend/vga_blank_n -add wave -noupdate -format Logic /tb_vga_frontend/vga_sync_n -add wave -noupdate -format Logic /tb_vga_frontend/vga_hsync -add wave -noupdate -format Logic /tb_vga_frontend/vga_vsync -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_red -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_green -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend/vga_blue -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/s -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/request_cnt -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/read_cnt -add wave -noupdate -divider Backend -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/ctrl_scan_en -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/sys_rst -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_vga_rdy -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/stat_scan -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/scan_enable -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/is_scan -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_hpos -add wave -noupdate -format Literal /tb_vga_frontend/inst_vga_frontend/stat_vpos -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/rst -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/dcm_locked -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_draw -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/cg_en -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/hready -add wave -noupdate -format Logic /tb_vga_frontend/inst_vga_frontend/inst_vga_backend/vready -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {1382189057 ps} {1476673938 ps} diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo deleted file mode 100644 index 664a74c..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo +++ /dev/null @@ -1,25 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jul 06 20:49:07 Westeuropäische Sommerzeit 2006 -## -vlib work -vcom -explicit -93 "../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" -vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/clkgen_virtex4.vhd" -vcom -explicit -93 "../src/char_gen.vhd" -vcom -explicit -93 "../src/vga_sync.vhd" -vcom -explicit -93 "../src/vga_timing.vhd" -vcom -explicit -93 "../src/vga_backend.vhd" -vcom -explicit -93 "../src/vga_frontend64.vhd" -vcom -explicit -93 "../src/tb_vga_frontend64.vhd" -vsim -t 1ps -lib work tb_vga_frontend64 -view wave -do {tb_vga_frontend64.wdo} -view structure -view signals - -run 20ms diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo deleted file mode 100644 index a73a3f1..0000000 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.wdo +++ /dev/null @@ -1,65 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_vga_frontend64/clk_o -add wave -noupdate -format Logic /tb_vga_frontend64/rst_o -add wave -noupdate -divider Master -add wave -noupdate -format Logic /tb_vga_frontend64/cyc_o -add wave -noupdate -format Logic /tb_vga_frontend64/stb_o -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_o -add wave -noupdate -format Literal /tb_vga_frontend64/sel_o -add wave -noupdate -format Logic /tb_vga_frontend64/we_o -add wave -noupdate -format Logic /tb_vga_frontend64/ack_i -add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_o -add wave -noupdate -format Logic /tb_vga_frontend64/srdy_i -add wave -noupdate -divider Slave -add wave -noupdate -format Logic /tb_vga_frontend64/cyc_i -add wave -noupdate -format Logic /tb_vga_frontend64/stb_i -add wave -noupdate -format Literal -radix hexadecimal /tb_vga_frontend64/addr_i -add wave -noupdate -format Literal /tb_vga_frontend64/sel_i -add wave -noupdate -format Logic /tb_vga_frontend64/we_i -add wave -noupdate -format Logic /tb_vga_frontend64/ack_o -add wave -noupdate -format Logic /tb_vga_frontend64/mrdy_i -add wave -noupdate -format Logic /tb_vga_frontend64/srdy_o -add wave -noupdate -divider VGA -add wave -noupdate -format Logic /tb_vga_frontend64/vga_clk_out -add wave -noupdate -format Logic /tb_vga_frontend64/vga_blank_n -add wave -noupdate -format Logic /tb_vga_frontend64/vga_sync_n -add wave -noupdate -format Logic /tb_vga_frontend64/vga_hsync -add wave -noupdate -format Logic /tb_vga_frontend64/vga_vsync -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_red -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_green -add wave -noupdate -format Literal -radix decimal /tb_vga_frontend64/vga_blue -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/s -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/request_cnt -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/read_cnt -add wave -noupdate -divider Backend -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/ctrl_scan_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/sys_rst -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_vga_rdy -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/stat_scan -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/scan_enable -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/is_scan -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_hpos -add wave -noupdate -format Literal /tb_vga_frontend64/inst_vga_frontend64/stat_vpos -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/rst -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/dcm_locked -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_draw -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/cg_en -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/hready -add wave -noupdate -format Logic /tb_vga_frontend64/inst_vga_frontend64/inst_vga_backend/vready -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1420398899 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {1382189057 ps} {1476673938 ps} diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd deleted file mode 100644 index b0f8579..0000000 --- a/lib/VGA_ctrl/src/char_gen.vhd +++ /dev/null @@ -1,546 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: char_gen - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity char_gen is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72; - - -- User supplied parameters - CHARACTER_SCALE : natural := 1; - CHAR_ROM_SIZE_X : natural := 8; -- Pixels - CHAR_ROM_SIZE_Y : natural := 16; -- Pixels - CHAR_ROM_DEPTH : natural := 256; -- Chars - MAX_CHAR_PER_LINE : natural := 32; -- Chars - MAX_LINE_PER_FRAME : natural := 16; -- Chars - CHAR_SPACING_X : natural := 0; -- Pixels - CHAR_SPACING_Y : natural := 0; -- Pixels - SCREEN_OFFSET_X : natural := 16; -- Pixels - SCREEN_OFFSET_Y : natural := 16 -- Pixels - ); - Port - ( - -- System signals - rst : in std_logic; - vga_clk : in std_logic; - sys_clk : in std_logic; - ce : in std_logic; - frame_pulse : in std_logic; - - - -- Host Signals - clr_screen : in std_logic; - clr_line : in std_logic; - ascii_data : in unsigned(7 downto 0); - ascii_data_we : in std_logic; - ascii_posy_we : in std_logic; - ascii_posx_we : in std_logic; - ready : out std_logic; - - -- Control signals - pos_x : in natural range 0 to tsvga.ts_h.ncyc_scan-1; - pos_y : in natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- Output - char_draw_en : out std_logic - - ); -end char_gen; - -architecture Behavioral of char_gen is - - constant A_RAM_ADDR_WIDTH : integer := 12; - constant A_RAM_DATA_WIDTH : integer := 8; - - type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - - - function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is - variable result : offset_rom_t; - - variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - begin - for i in 0 to num_lines-1 loop - result(i) := offset; - offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1); - end loop; - return result; - end gen_offset_rom; - - constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME); - - -- Calculated parameters - type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen); - signal s, sn : cg_state_t; - - constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE; - constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE; - constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE; - constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE; - - signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1; - signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1; - signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1; - signal char_x_cnt : natural range 0 to CELL_SIZE_X-1; - signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1; - signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0); - signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0); - signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0); - - signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_ram_we : std_logic; - signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1; - signal a_cnt_rst : std_logic; - signal a_cnt_en : std_logic; - signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1; - signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_we : std_logic; - signal csr_posx_overflow : std_logic; - signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posx_cnt_set : std_logic; - signal csr_posx_cnt_en : std_logic; - signal csr_posy_overflow : std_logic; - signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1; - signal csr_posy_cnt_set : std_logic; - signal csr_posy_cnt_en : std_logic; - - signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - -- Visible Cursor - constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2; - - type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0); - constant cursor_rom : cursor_rom_t := - ( - -- Cursor off - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - - -- Cursor on - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "00000000", - "00000000", - "00000000" - - ); - signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0); - signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal cursor_visible : std_logic; - signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1; - signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1; - - -- Scrolling - signal scroll_offset : natural range 0 to MAX_CHAR_PER_LINE-1; - signal scroll_active : std_logic; - - -begin - - a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset); - line_addr <= offset_rom(csr_posy_reg); - char_addr <= to_unsigned(csr_posx_reg, char_addr'length); - char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - - inst_char_rom : entity work.char_rom - PORT MAP - ( - CLK => vga_clk, - ADDR => char_rom_addr, - DATA => char_rom_data - ); - - inst_ascii_ram: entity work.dpram_1w1r - GENERIC MAP ( - addr_width => A_RAM_ADDR_WIDTH, - data_width => A_RAM_DATA_WIDTH - ) - PORT MAP( - clka => sys_clk, - clkb => vga_clk, - en_a => '1', - en_b => '1', - we_a => a_ram_we, - addr_a => a_addr_wr, - addr_b => a_addr_rd, - din_a => a_data_wr, - dout_b => a_data_rd - ); - - --------------------------------------------------------------------------------------------- - --- ASCII RAM control - --------------------------------------------------------------------------------------------- - asci_ram_fsm: - process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr) - begin - sn <= s; - a_cnt_rst <= '0'; - a_cnt_en <= '0'; - a_ram_we <= '0'; - a_data_wr <= a_data_reg; - a_addr_wr <= char_addr + line_addr; - ready <= '0'; - - case s is - - when cg_init => - sn <= cg_clr_screen; - a_cnt_rst <= '1'; - when cg_ready => - ready <= '1'; - a_ram_we <= a_data_we; - if clr_screen = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_screen; - elsif clr_line = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_line; - end if; - when cg_clr_line => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH); - if a_cnt = MAX_CHAR_PER_LINE-1 then - sn <= cg_ready; - end if; - when cg_clr_screen => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH); - if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then - sn <= cg_ready; - end if; - - when others => - sn <= cg_ready; - - end case; - end process; - - asci_ram_fsm_next: process (rst, sys_clk) - begin - if rst = '1' then - s <= cg_init; - elsif rising_edge(sys_clk) then - s <= sn; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_ram_cnt: process (rst, sys_clk) - begin - if rst = '1' then - a_cnt <= 0; - elsif rising_edge(sys_clk) then - if a_cnt_rst = '1' then - a_cnt <= 0; - elsif a_cnt_en = '1' then - if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then - a_cnt <= a_cnt + 1; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_addr_reg: process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - a_data_reg <= (others => '0'); - a_data_we <= '0'; - elsif rising_edge(sys_clk) then - a_data_we <= '0'; - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - if ascii_posy_we = '1' then - csr_posy_cnt_din <= to_integer(ascii_data); - csr_posy_cnt_set <= '1'; - elsif ascii_posx_we = '1' then - csr_posx_cnt_din <= to_integer(ascii_data); - csr_posx_cnt_set <= '1'; - elsif ascii_data_we = '1' then - if ascii_data < X"20" then - if ascii_data = X"0D" then - csr_posx_cnt_din <= 0; - csr_posx_cnt_set <= '1'; - elsif ascii_data = X"0A" then - csr_posy_cnt_en <= '1'; - end if; - else - a_data_reg <= ascii_data - X"20"; - a_data_we <= '1'; - csr_posx_cnt_en <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posx_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_reg <= 0; - csr_posx_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posx_overflow <= '0'; - if csr_posx_cnt_set = '1' then - csr_posx_reg <= csr_posx_cnt_din; - elsif csr_posx_cnt_en = '1' then - if csr_posx_reg < MAX_CHAR_PER_LINE-1 then - csr_posx_reg <= csr_posx_reg + 1; - else - csr_posx_reg <= 0; - csr_posx_overflow <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posy_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posy_reg <= 0; - csr_posy_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posy_overflow <= '0'; - if csr_posy_cnt_set = '1' then - csr_posy_reg <= csr_posy_cnt_din; - elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then - if csr_posy_reg < MAX_LINE_PER_FRAME-1 then - csr_posy_reg <= csr_posy_reg + 1; - else - csr_posy_reg <= 0; - csr_posy_overflow <= '1'; - end if; - end if; - end if; - end process; - - scroll_gen: process (rst, sys_clk) - begin - if rst = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif rising_edge(sys_clk) then - if clr_screen = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif csr_posy_overflow = '1' then - scroll_active <= '1'; - scroll_offset <= 1; - end if; - if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then - scroll_offset <= scroll_offset + 1; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Cursor generator - --------------------------------------------------------------------------------------------- - proc_sync_csr_posx: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1; - begin - if rising_edge(vga_clk) then - csr_posx_synced <= p2; - p2 := p1; - p1 := csr_posx_reg; - end if; - end process; - - proc_sync_csr_posy: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1; - begin - if rising_edge(vga_clk) then - csr_posy_synced <= p2; - p2 := p1; - p1 := csr_posy_reg; - end if; - end process; - - csr_blink_cnt: process (rst, vga_clk) - begin - if rst = '1' then - cursor_cnt <= 0; - cursor_visible <= '0'; - elsif rising_edge(vga_clk) then - if frame_pulse = '1' then - if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then - cursor_cnt <= cursor_cnt + 1; - else - cursor_cnt <= 0; - cursor_visible <= not cursor_visible; - end if; - end if; - end if; - end process; - - cursor_rom_read: process (vga_clk) - begin - if rising_edge(vga_clk) then - cursor_rom_data <= (others => '0'); - if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then - cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr)); - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Character generator - --------------------------------------------------------------------------------------------- - char_rom_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) then - char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length); - end if; - end process; - - --------------------------------------------------------------------------------------------- - char_reg_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) and ce = '1' then - if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access - for i in 0 to CHAR_ROM_SIZE_X-1 loop - for j in 0 to CHARACTER_SCALE-1 loop - char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i); - end loop; - end loop; - else - char_reg <= char_reg(char_reg'left-1 downto 0) & '0'; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - cg_ctrl: process (rst, vga_clk) - variable enable_x : std_logic; - variable enable_y : std_logic; - variable char_en : std_logic; - variable char_en2 : std_logic; - begin - - if (rst = '1') then - enable_x := '0'; - enable_y := '0'; - line_offset <= 0; - cell_x_cnt <= 0; - cell_y_cnt <= 0; - char_x_cnt <= 0; - char_y_cnt <= 0; - char_en := '0'; - elsif rising_edge(vga_clk) and ce = '1' then - char_draw_en <= char_en2 and char_reg(char_reg'left); - char_en2 := char_en; - char_en := '0'; - if pos_y = SCREEN_OFFSET_Y then - enable_y := '1'; - cell_y_cnt <= 0; - char_x_cnt <= 0; - line_offset <= scroll_offset; - end if; - if pos_x = SCREEN_OFFSET_X and enable_y = '1' then - enable_x := '1'; - cell_x_cnt <= 0; - char_x_cnt <= 0; - elsif enable_x = '1' and enable_y = '1' then - if char_x_cnt < CELL_SIZE_X-1 then - char_x_cnt <= char_x_cnt + 1; - else - char_x_cnt <= 0; - if cell_x_cnt < MAX_CHAR_PER_LINE-1 then - cell_x_cnt <= cell_x_cnt + 1; - else - enable_x := '0'; - if char_y_cnt < CELL_SIZE_Y-1 then - char_y_cnt <= char_y_cnt + 1; - else - char_y_cnt <= 0; - if cell_y_cnt < MAX_LINE_PER_FRAME-1 then - cell_y_cnt <= cell_y_cnt + 1; - else - enable_y := '0'; - end if; - if line_offset < MAX_LINE_PER_FRAME-1 then - line_offset <= line_offset + 1; - else - line_offset <= 0; - end if; - end if; - end if; - end if; - if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then - char_en := '1'; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd deleted file mode 100644 index 0b58baf..0000000 --- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clkgen is - Generic - ( - sys_freq : integer := 100E6; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - vga_clk : out std_logic; - dcm_locked : out std_logic - ); -end clkgen; - -architecture tech of clkgen is - - signal vga_clk0 : std_logic; - signal dcm_clk0 : std_logic; - signal dcm_clk_fb : std_logic; - - begin - - -- Compnent instantiation - DCM_VGA_CLK_inst : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => 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z2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2G$1F2L2D3 CZx);Y diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd deleted file mode 100644 index 5a544d0..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd +++ /dev/null @@ -1,540 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230 - x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238 - x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240 - x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248 - x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250 - x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260 - x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268 - x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270 - x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278 - x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280 - x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290 - x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298 - x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0 - x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8 - x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0 - x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0 - x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8 - x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8 - x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630 - x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640 - x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648 - x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650 - x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660 - x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668 - x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670 - x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678 - x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680 - x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690 - x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0 - x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8 - x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0 - x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8 - x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8 - x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808 - x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810 - x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818 - x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828 - x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838 - x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840 - x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848 - x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850 - x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858 - x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860 - x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888 - x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898 - x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0 - x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0 - x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40 - x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8 - x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00 - x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10 - x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18 - x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20 - x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28 - x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40 - x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48 - x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50 - x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58 - x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60 - x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68 - x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70 - x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78 - x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88 - x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90 - x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98 - x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0 - x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8 - x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0 - x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8 - x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0 - x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8 - x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0 - x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40 - x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8 - x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd deleted file mode 100644 index c52e7f7..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000 - x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008 - x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010 - x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018 - x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020 - x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038 - x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040 - x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048 - x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050 - x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058 - x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068 - x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070 - x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078 - x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080 - x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088 - x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090 - x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098 - x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8 - x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0 - x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8 - x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0 - x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0 - x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0 - x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108 - x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110 - x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118 - x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120 - x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128 - x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130 - x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140 - x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148 - x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150 - x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160 - x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178 - x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180 - x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188 - x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190 - x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198 - x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8 - x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0 - x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0 - x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8 - x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200 - x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208 - x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210 - x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230 - x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238 - x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240 - x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248 - x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250 - x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260 - x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268 - x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270 - x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278 - x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280 - x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290 - x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298 - x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0 - x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8 - x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0 - x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0 - x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8 - x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0 - x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8 - x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0 - x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8 - x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328 - x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380 - x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390 - x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400 - x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408 - x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410 - x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418 - x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438 - x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440 - x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448 - x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450 - x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458 - x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468 - x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470 - x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478 - x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488 - x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490 - x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498 - x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8 - x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0 - x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8 - x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0 - x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0 - x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0 - x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508 - x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518 - x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520 - x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528 - x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530 - x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540 - x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548 - x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550 - x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578 - x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580 - x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588 - x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590 - x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598 - x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0 - x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8 - x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0 - x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0 - x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608 - x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630 - x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638 - x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640 - x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648 - x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650 - x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660 - x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668 - x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670 - x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678 - x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680 - x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690 - x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698 - x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0 - x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8 - x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0 - x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0 - x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8 - x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0 - x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8 - x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0 - x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8 - x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728 - x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780 - x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790 - x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd deleted file mode 100644 index 95a9bd1..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 - x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008 - x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010 - x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018 - x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020 - x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028 - x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030 - x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038 - x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040 - x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048 - x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050 - x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058 - x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060 - x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068 - x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070 - x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078 - x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080 - x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088 - x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090 - x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098 - x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0 - x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8 - x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0 - x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8 - x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0 - x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8 - x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108 - x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110 - x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118 - x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120 - x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140 - x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148 - x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150 - x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180 - x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188 - x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190 - x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198 - x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0 - x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8 - x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0 - x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8 - x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0 - x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200 - x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208 - x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210 - x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230 - x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238 - x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248 - x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250 - x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260 - x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268 - x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278 - x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280 - x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288 - x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290 - x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298 - x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0 - x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8 - x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0 - x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8 - x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370 - x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408 - x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410 - x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508 - x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518 - x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520 - x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538 - x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540 - x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548 - x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550 - x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560 - x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568 - x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570 - x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578 - x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590 - x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598 - x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0 - x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608 - x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618 - x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620 - x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630 - x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638 - x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640 - x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648 - x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650 - x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658 - x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660 - x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678 - x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0 - x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0 - x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740 - x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748 - x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750 - x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758 - x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd deleted file mode 100644 index ce977b6..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008 - x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010 - x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018 - x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028 - x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038 - x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040 - x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050 - x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058 - x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060 - x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088 - x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098 - x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0 - x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8 - x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0 - x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108 - x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118 - x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120 - x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128 - x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130 - x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180 - x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0 - x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240 - x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248 - x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260 - x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268 - x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280 - x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288 - x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0 - x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd deleted file mode 100644 index 3b60051..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd +++ /dev/null @@ -1,4383 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - 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10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 108 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 109 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "01101011", -- | ## # ##| 06 - "01101011", -- | ## # ##| 07 - "01101011", -- | ## # ##| 08 - "01101011", -- | ## # ##| 09 - "01101011", -- | ## # ##| 10 - "01100011", -- | ## ##| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 110 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 111 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 112 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 113 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 114 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01101110", -- | ## ### | 06 - "01110000", -- | ### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 115 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "00111100", -- | #### | 08 - "00000110", -- | ## | 09 - "00000110", -- | ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 116 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "01111110", -- | ###### | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 117 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 118 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 119 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - 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## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 122 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01111110", -- | ###### | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 123 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00110000", -- | ## | 07 - "01100000", -- | ## | 08 - "00110000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 124 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00011000", -- | ## | 14 - -- ASCII 125 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00001100", -- | ## | 07 - "00000110", -- | ## | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "00111100", -- | #### | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 163 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "11111100", -- |###### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "11000000", -- |## | 10 - "11111110", -- |####### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 164 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "01100110", -- | ## ## | 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "10011001", -- |# ## #| 05 - "10100101", -- |# # # #| 06 - "10100001", -- |# # #| 07 - "10100101", -- |# # # #| 08 - "10011001", -- |# ## #| 09 - "11000011", -- |## ##| 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 170 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00000110", -- | ## | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "00111110", -- | ##### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 171 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - 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--------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111011", -- | #### ##| 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "11000000", -- |## | 14 - -- ASCII 182 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011111", -- | #####| 03 - "00111110", -- | ##### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "00111110", -- | ##### | 08 - "00011110", -- | #### | 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000110", -- | ## | 12 - "00000110", -- | ## | 13 - "00000110", -- | ## | 14 - -- ASCII 183 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011100", -- | ### | 06 - "00011100", -- | ### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 184 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00111000", -- | ### | 14 - -- ASCII 185 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111000", -- | ### | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 186 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "00111100", -- | #### | 07 - "00000000", -- | | 08 - "01111110", -- | ###### | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 187 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "11001100", -- |## ## | 07 - "01100110", -- | ## ## | 08 - "00110011", -- | ## ##| 09 - "01100110", -- | ## ## | 10 - "11001100", -- |## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 188 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00110111", -- | ## ###| 08 - "01101111", -- | ## ####| 09 - "11011011", -- |## ## ##| 10 - "00011111", -- | #####| 11 - "00000011", -- | ##| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 189 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100000", -- | ## | 02 - "11100000", -- |### | 03 - "01100011", -- | ## ##| 04 - "01100110", -- | ## ## | 05 - "01101100", -- | ## ## | 06 - "00011000", -- | ## | 07 - "00111110", -- | ##### | 08 - "01100011", -- | ## ##| 09 - "11000110", -- |## ## | 10 - "00001100", -- | ## | 11 - "00001111", -- | ####| 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 190 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "11100000", -- |### | 02 - "00110000", -- | ## | 03 - "01100011", -- | ## ##| 04 - "00110110", -- | ## ## | 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| | 13 - "00000000", -- | | 14 - -- ASCII 195 --------------- - "00111011", -- | ### ##| 00 - "01101110", -- | ## ### | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 196 --------------- - "01100110", -- | ## ## | 00 - "01100110", -- | ## ## | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 197 --------------- - "00111100", -- | #### | 00 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"00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "01111100", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 242 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - 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09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- Padding --------------- - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd deleted file mode 100644 index e46151c..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 072 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111110", -- | ###### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 073 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 074 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00000110", -- | ## | 05 - "00000110", -- | ## | 06 - "00000110", -- | ## | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 075 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- 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| 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 126 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01110001", -- | ### #| 03 - "11011011", -- |## ## ##| 04 - "10001110", -- |# ### | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 127 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 128 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 129 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 130 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 131 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 132 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - 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-- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 140 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 141 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 142 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - 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-- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 145 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 146 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011100", -- | ### | 04 - "00001100", -- | ## | 05 - "00011000", -- | ## | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 147 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 148 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 149 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 150 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 151 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 152 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 153 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 154 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 155 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 156 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 157 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 158 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 159 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 160 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 161 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00111100", -- | #### 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-- | | 15 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "11111111", -- |########| 12 - "11111111", -- |########| 13 - "11111111", -- |########| 14 - "00000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd deleted file mode 100644 index 9b32d16..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd +++ /dev/null @@ -1,4351 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(8 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 033 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "001111000", -- | #### | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 034 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 035 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "001101100", -- | ## ## | 04 - "011111110", -- | ####### | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "001101100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 036 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "000110000", -- | ## | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 037 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011100000", -- | ### | 02 - "110110000", -- |## ## | 03 - "110110100", -- |## ## # | 04 - "011101100", -- | ### ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011011100", -- | ## ### | 09 - "010110110", -- | # ## ## | 10 - "000110110", -- | ## ## | 11 - "000011100", -- | ### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 038 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "111111110", -- |######## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 039 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 040 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "001100000", -- | ## | 06 - "001100000", -- | ## | 07 - "001100000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 041 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001100000", -- | ## | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000011000", -- | ## | 06 - "000011000", -- | ## | 07 - "000011000", -- | ## | 08 - "000011000", -- | ## | 09 - "000011000", -- | ## | 10 - "000110000", -- | ## | 11 - "000110000", -- | ## | 12 - "001100000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 042 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001101100", -- | ## ## | 05 - "000111000", -- | ### | 06 - "011111110", -- | ####### | 07 - "000111000", -- | ### | 08 - "001101100", -- | ## ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 043 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000110000", -- | ## | 05 - "000110000", -- | ## | 06 - "011111100", -- | ###### | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 044 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 045 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 046 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000111000", -- | ### | 10 - "000111000", -- | ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 047 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000001100", -- | ## | 03 - "000001100", -- | ## | 04 - "000011000", -- | ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "001100000", -- | ## | 09 - "001100000", -- | ## | 10 - "011000000", -- | ## | 11 - "011000000", -- | ## | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 048 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111100", -- | #### | 03 - "001100110", -- | ## ## | 04 - "001101110", -- | ## ### | 05 - "001101110", -- | ## ### | 06 - "001100110", -- | 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--------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 136 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 137 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--------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 144 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 145 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000011000", -- | ## | 03 - "000110000", -- | ## | 04 - "000111000", -- | ### | 05 - "000111000", -- | ### | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 146 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000111000", -- | ### | 03 - "000111000", -- | ### | 04 - "000011000", -- | ## | 05 - "000110000", -- | ## | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 147 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 148 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 - "011111100", -- | ###### | 04 - "011111100", -- | ###### | 05 - "011111100", -- | ###### | 06 - "011111100", -- | ###### | 07 - "011111100", -- | ###### | 08 - "011111100", -- | ###### | 09 - "011111100", -- | ###### | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 149 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011111100", -- | ###### | 03 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-- | ## ## | 08 - "011111000", -- | ##### | 09 - "011000000", -- | ## | 10 - "011000000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 223 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001110000", -- | ### | 03 - "011011000", -- | ## ## | 04 - "011011000", -- | ## ## | 05 - "011011000", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011011000", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 224 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 225 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 226 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 227 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 228 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 229 --------------- - "000000000", -- | | 00 - "001111000", -- | #### | 01 - "011001100", -- | ## ## | 02 - "001111000", -- | #### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "000001100", -- | ## | 06 - "000001100", -- | ## | 07 - "001111100", -- | ##### | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 230 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "011011100", -- | ## ### | 05 - "000110110", -- | ## ## | 06 - "000110110", -- | ## ## | 07 - "011111110", -- | ####### | 08 - "110110000", -- |## ## | 09 - "110110000", -- |## ## | 10 - "011101110", -- | ### ### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 231 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011000000", -- | ## | 07 - "011000000", -- | ## | 08 - "011000000", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000011000", -- | ## | 13 - "001110000", -- | ### | 14 - "000000000", -- | | 15 - -- ASCII 232 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 233 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 234 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 235 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011111100", -- | ###### | 08 - "011000000", -- | ## | 09 - "011000000", -- | ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 236 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 237 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - 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"000000000", -- | | 04 - "011110000", -- | #### | 05 - "000110000", -- | ## | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "011111100", -- | ###### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 240 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "000110000", -- | ## | 04 - "011011000", -- | ## ## | 05 - "000111100", -- | #### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 241 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "011111000", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011001100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 242 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 243 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 244 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 245 --------------- - "000000000", -- | | 00 - "011100010", -- | ### # | 01 - "110110110", -- |## ## ## | 02 - "100011100", -- |# ### | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 246 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "001111000", -- | #### | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 247 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000110000", -- | ## | 04 - "000110000", -- | ## | 05 - "000000000", -- | | 06 - "011111100", -- | ###### | 07 - "000000000", -- | | 08 - "000110000", -- | ## | 09 - "000110000", -- | ## | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 248 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "001111100", -- | ##### | 05 - "011001100", -- | ## ## | 06 - "011011100", -- | ## ### | 07 - "011111100", -- | ###### | 08 - "011101100", -- | ### ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 249 --------------- - "000000000", -- | | 00 - "011100000", -- | ### | 01 - "001100000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 250 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 251 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "001111000", -- | #### | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111100", -- | ##### | 11 - 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"000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 254 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 255 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- Padding --------------- - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - 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"000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - 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"000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd deleted file mode 100644 index d50d36f..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(15 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 033 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 034 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100110000000000", -- |## ## | 03 - "1100110000000000", -- |## ## | 04 - "1100110000000000", -- |## ## | 05 - "1100110000000000", -- |## ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 035 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011011000000000", -- | ## ## | 03 - "0011011000000000", -- | ## ## | 04 - "0111111100000000", -- | ####### | 05 - "0011011000000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0110110000000000", -- | ## ## | 09 - "1111111000000000", -- |####### | 10 - "0110110000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 036 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011110000000000", -- | #### | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110000000000000", -- | ## | 07 - "0011110000000000", -- | #### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 037 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000001100000", -- | ### ## | 03 - "1101100011000000", -- |## ## ## | 04 - "1101100110000000", -- |## ## ## | 05 - "1101101100000000", -- |## ## ## | 06 - "0111011000000000", -- | ### ## | 07 - "0000110111000000", -- | ## ### | 08 - "0001101101100000", -- | ## ## ## | 09 - "0011001101100000", -- | ## ## ## | 10 - "0110001101100000", -- | ## ## ## | 11 - "1100000111000000", -- |## ### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 038 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "1111000000000000", -- |#### | 14 - "0000000000000000", -- | | 15 - -- ASCII 039 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 040 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0011000000000000", -- | ## | 15 - -- ASCII 041 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 042 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "1111110000000000", -- |###### | 04 - "0011000000000000", -- | ## | 05 - "0111100000000000", -- | #### | 06 - "0100100000000000", -- | # # | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 043 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 044 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "1100000000000000", -- |## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 045 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "1111000000000000", -- |#### | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 046 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 047 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0011000000000000", -- | ## | 04 - "0011000000000000", -- | ## | 05 - "0011000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "1100000000000000", -- |## | 11 - "1100000000000000", -- |## | 12 - "1100000000000000", -- |## | 13 - "1100000000000000", -- |## | 14 - "0000000000000000", -- | | 15 - -- ASCII 048 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110011000000000", -- | ## ## | 07 - "0110011000000000", -- | ## ## | 08 - "0110011000000000", -- | ## ## | 09 - "0110011000000000", -- | ## ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 049 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0111100000000000", -- | #### | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0001100000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 050 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0110011000000000", -- | ## ## | 05 - "0000011000000000", -- | ## | 06 - "0000110000000000", -- | ## | 07 - "0001100000000000", -- | ## | 08 - "0011000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0111111000000000", -- | ###### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 051 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011110000000000", -- | #### | 03 - "0110011000000000", -- | ## ## | 04 - "0000011000000000", -- | ## | 05 - "0000011000000000", -- | ## | 06 - "0001110000000000", -- | ### | 07 - "0000011000000000", -- | ## | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 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"0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 273 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 274 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 275 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 276 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 277 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 278 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 279 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 280 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 281 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 282 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 283 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 284 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 285 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 286 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 287 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd deleted file mode 100644 index f5bbcc5..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008 - x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010 - x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038 - x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040 - x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048 - x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050 - x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058 - x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060 - x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088 - x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090 - x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098 - x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0 - x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8 - x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100 - x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108 - x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118 - x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128 - x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148 - x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150 - x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158 - x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168 - x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170 - x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178 - x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180 - x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188 - x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190 - x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 - x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 - x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 - x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200 - x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208 - x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240 - x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248 - x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268 - x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270 - x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278 - x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280 - x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288 - x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300 - x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308 - x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310 - x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318 - x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330 - x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338 - x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348 - x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368 - x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378 - x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380 - x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388 - x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390 - x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat deleted file mode 100644 index 9cfa61b..0000000 --- a/lib/VGA_ctrl/src/fonts/make_rom.bat +++ /dev/null @@ -1,6 +0,0 @@ -@echo off - -bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd -bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd -bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd -bff2rom System_16x16.bff y >char_rom_system_16x16.vhd diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd deleted file mode 100644 index a07ec69..0000000 --- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd +++ /dev/null @@ -1,201 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.vga_types.all; - -ENTITY tb_vga_frontend IS -END tb_vga_frontend; - -ARCHITECTURE behavior OF tb_vga_frontend IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal MDAT_I : unsigned(31 downto 0); - signal MDAT_O : unsigned(31 downto 0); - - -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(3 downto 0); - signal ACK_O : std_logic; - signal MRDY_I : std_logic; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_O : unsigned(31 downto 0); - - -- VGA signals - signal vga_clk_out : std_logic; - signal vga_red : unsigned(7 downto 0); - signal vga_green : unsigned(7 downto 0); - signal vga_blue : unsigned(7 downto 0); - signal vga_blank_n : std_logic; - signal vga_sync_n : std_logic; - signal vga_hsync : std_logic; - signal vga_vsync : std_logic; - -BEGIN - -inst_vga_frontend : entity work.vga_frontend - GENERIC MAP - ( - sys_freq => 100E6, - fifo_depth => 2048, - fifo_almost_full_thresh => 2000, - fifo_almost_empty_thresh => 48, - tsvga => ts_vga_800_600_72 - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_I, - STB_O => STB_I, - WE_O => WE_I, - SEL_O => SEL_I, - ACK_I => ACK_O, - SRDY_I => SRDY_O, - MRDY_O => MRDY_I, - ADDR_O => ADDR_I, - MDAT_I => MDAT_O, - MDAT_O => MDAT_I, - - -- JBUS Slave signals - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => SDAT_O, - SDAT_O => SDAT_I, - - -- VGA signals - vga_clk_out => vga_clk_out, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - --- Slave - SRDY_O <= CYC_I; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - MDAT_O <= X"00000000"; - elsif (CYC_I and STB_I) = '1' then - MDAT_O <= MDAT_O + 1; - ACK_O <= '1'; - else - ACK_O <= '0'; - end if; - end if; - end process; - --- Master -STIMULUS: process - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - - -- 8 single cycles - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0000"; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0000"; - ADDR_O <= X"0000_0010"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0035"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0035"; - ADDR_O <= X"0000_0020"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd deleted file mode 100644 index 279f854..0000000 --- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd +++ /dev/null @@ -1,201 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -use work.vga_types.all; - -ENTITY tb_vga_frontend64 IS -END tb_vga_frontend64; - -ARCHITECTURE behavior OF tb_vga_frontend64 IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - - -- Master - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal WE_O : std_logic; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic := '0'; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic := '0'; - signal ADDR_O : unsigned(31 downto 0); - signal MDAT_I : unsigned(63 downto 0); - signal MDAT_O : unsigned(63 downto 0); - - -- Slave - signal CYC_I : std_logic := '0'; - signal STB_I : std_logic := '0'; - signal WE_I : std_logic := '0'; - signal SEL_I : unsigned(7 downto 0); - signal ACK_O : std_logic; - signal MRDY_I : std_logic; - signal SRDY_O : std_logic; - signal ADDR_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_I : unsigned(31 downto 0) := (others => '-'); - signal SDAT_O : unsigned(31 downto 0); - - -- VGA signals - signal vga_clk_out : std_logic; - signal vga_red : unsigned(7 downto 0); - signal vga_green : unsigned(7 downto 0); - signal vga_blue : unsigned(7 downto 0); - signal vga_blank_n : std_logic; - signal vga_sync_n : std_logic; - signal vga_hsync : std_logic; - signal vga_vsync : std_logic; - -BEGIN - -inst_vga_frontend64 : entity work.vga_frontend64 - GENERIC MAP - ( - sys_freq => 100E6, - fifo_depth => 2048, - fifo_almost_full_thresh => 2000, - fifo_almost_empty_thresh => 48, - tsvga => ts_vga_800_600_72 - ) - PORT MAP - ( - -- System signals - RST_I => RST_O, - CLK_I => CLK_O, - - -- JBUS Master signals - CYC_O => CYC_I, - STB_O => STB_I, - WE_O => WE_I, - SEL_O => SEL_I, - ACK_I => ACK_O, - SRDY_I => SRDY_O, - MRDY_O => MRDY_I, - ADDR_O => ADDR_I, - MDAT_I => MDAT_O, - MDAT_O => MDAT_I, - - -- JBUS Slave signals - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => SDAT_O, - SDAT_O => SDAT_I, - - -- VGA signals - vga_clk_out => vga_clk_out, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - --- Slave - SRDY_O <= CYC_I; - - process(CLK_O) - begin - if rising_edge(CLK_O) then - if RST_O = '1' then - MDAT_O <= X"00000000_00000000"; - elsif (CYC_I and STB_I) = '1' then - MDAT_O <= MDAT_O + 1; - ACK_O <= '1'; - else - ACK_O <= '0'; - end if; - end if; - end process; - --- Master -STIMULUS: process - - begin - - wait for 6*CLK_PERIOD; - RST_O <= '0'; - - -- 8 single cycles - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0000"; - ADDR_O <= X"0000_0008"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0000"; - ADDR_O <= X"0000_0010"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0035"; - ADDR_O <= X"0000_0004"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '1'; - SDAT_I <= X"0000_0035"; - ADDR_O <= X"0000_0020"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O); - CYC_O <= '0'; - - - - wait; - - end process; - -END; diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd deleted file mode 100644 index e9ebc99..0000000 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ /dev/null @@ -1,195 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_backend is - Generic - ( - sys_freq : integer := 100E6; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - sys_rst : in std_logic; - sys_clk : in std_logic; - - -- Color channels - color_in : in color_array_t; - color_op : in color_op_t; - color_en : unsigned (VGA_NUM_CH-1 downto 0); - - -- Control signals - ctrl_scan_en : in std_logic; - - -- Status signals - stat_vga_rdy : out std_logic; - stat_scan : out std_logic; - stat_hsync : out std_logic; - stat_vsync : out std_logic; - stat_hready : out std_logic; - stat_vready : out std_logic; - stat_hscan : out std_logic; - stat_vscan : out std_logic; - stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- VGA domain signals - vga_clk_out : out std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_backend; - -architecture Behavioral of vga_backend is - - signal scan_enable : std_logic; - signal is_scan : std_logic; - signal is_hscan : std_logic; - signal is_vscan : std_logic; - signal hsync : std_logic; - signal vsync : std_logic; - signal hready : std_logic; - signal vready : std_logic; - signal vga_clk : std_logic; - signal dcm_locked : std_logic; - signal rst : std_logic; - -begin - - vga_clk_out <= vga_clk; - -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - rst => sys_rst, - clk => sys_clk, - vga_clk => vga_clk, - dcm_locked => dcm_locked - ); - -inst_vga_timing: entity work.vga_timing - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - sys_rst => sys_rst, - vga_clk => vga_clk, - vga_ce => dcm_locked, - sync_h => hsync, - sync_v => vsync, - scan_pos_h => stat_hpos, - scan_pos_v => stat_vpos, - is_scan_h => is_hscan, - is_scan_v => is_vscan, - scan_rdy_h => hready, - scan_rdy_v => vready - ); - - --------------------------------------------------------------------------------------------- - rst <= not dcm_locked; - stat_vga_rdy <= dcm_locked; - stat_hsync <= hsync; - stat_vsync <= vsync; - stat_hscan <= is_hscan; - stat_vscan <= is_vscan; - stat_hready <= hready; - stat_vready <= vready; - stat_scan <= is_scan; - - vga_blank_n <= '1'; - vga_sync_n <= '0'; - is_scan <= is_hscan and is_vscan and scan_enable; - - --------------------------------------------------------------------------------------------- - proc_vga_start: - process (rst, vga_clk) - begin - if rst = '1' then - scan_enable <= '0'; - elsif rising_edge(vga_clk) then - if vsync = '1' then - if ctrl_scan_en = '1' then - scan_enable <= '1'; - else - scan_enable <= '0'; - end if; - end if; - end if; - end process; - - proc_vga_color_out: - process (vga_clk) - variable do_scan : std_logic; - variable color : color_t; - begin - if rising_edge(vga_clk) then - vga_red <= X"00"; - vga_green <= X"00"; - vga_blue <= X"00"; - if is_scan = '1' then - for i in 0 to VGA_NUM_CH-1 loop - color := color_in(i); - if color_en(i) = '1' then - vga_red <= color(r); -- ToDo: color_op over channels - vga_green <= color(g); -- ToDo: color_op over channels - vga_blue <= color(b); -- ToDo: color_op over channels - end if; - end loop; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - proc_vga_sync_out: - process (rst, vga_clk) - variable hsync_r : std_logic; - variable vsync_r : std_logic; - begin - if rst = '1' then - vga_hsync <= tsvga.ts_h.sync_polarity; - vga_vsync <= tsvga.ts_v.sync_polarity; - hsync_r := tsvga.ts_h.sync_polarity; - vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk) then - vga_hsync <= hsync_r; - vga_vsync <= vsync_r; - hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); - vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); - end if; - end process; - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_frontend.vhd b/lib/VGA_ctrl/src/vga_frontend.vhd deleted file mode 100644 index 78eae44..0000000 --- a/lib/VGA_ctrl/src/vga_frontend.vhd +++ /dev/null @@ -1,415 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_frontend is - Generic - ( - sys_freq : integer := 100E6; - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(31 downto 0); - MDAT_O : out unsigned(31 downto 0); - - -- JBUS Slave signals - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_out : out std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_frontend; - -architecture Behavioral of vga_frontend is - - signal vga_clk : std_logic; - - -- Color FIFO signals - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_color_re : std_logic; - signal fifo_color_we : std_logic; - signal fifo_color_out : unsigned(31 downto 0); - signal fifo_color_in : unsigned(31 downto 0); - - -- Backend signals - signal scan_rdy : std_logic; - signal ctrl_scan_en : std_logic; - signal color_in : color_array_t; - signal color_op : color_op_t; - signal color_en : unsigned (VGA_NUM_CH-1 downto 0); - - signal stat_vga_rdy : std_logic; - signal stat_hready : std_logic; - signal stat_vready : std_logic; - signal stat_scan : std_logic; - signal stat_hscan : std_logic; - signal stat_vscan : std_logic; - signal stat_hsync : std_logic; - signal stat_vsync : std_logic; - signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1; - signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- CG signals - signal cg_en : std_logic; - signal cg_rdy : std_logic; - signal cg_draw : std_logic; - signal cg_clr_screen : std_logic; - signal cg_clr_line : std_logic; - signal cg_ascii_data : unsigned(7 downto 0); - signal cg_ascii_data_we : std_logic; - signal cg_ascii_posy_we : std_logic; - signal cg_ascii_posx_we : std_logic; - - -- Bus master signals - constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; - - signal vga_mem_offset : unsigned(31 downto 0); - signal vga_scan_rdy : std_logic; - signal vga_master_en : std_logic; - signal request_cnt_rst : std_logic; - signal request_cnt_en : std_logic; - signal pixel_cnt_rst : std_logic; - signal read_bus_en : std_logic; - signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1; - signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1; - - type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data); - signal s, sn : vm_state_t; - -begin - - vga_clk_out <= vga_clk; - -inst_vga_backend : entity work.vga_backend - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - sys_rst => RST_I, - sys_clk => CLK_I, - - -- Color channels - color_in => color_in, - color_op => color_op, - color_en => color_en, - - -- Control signals - ctrl_scan_en => ctrl_scan_en, - - -- Status signals - stat_vga_rdy => stat_vga_rdy, - stat_scan => stat_scan, - stat_hsync => stat_hsync, - stat_vsync => stat_vsync, - stat_hready => stat_hready, - stat_vready => stat_vready, - stat_hscan => stat_hscan, - stat_vscan => stat_vscan, - stat_hpos => stat_hpos, - stat_vpos => stat_vpos, - - -- VGA domain signals - vga_clk_out => vga_clk, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - ctrl_scan_en <= '1'; - color_en(0) <= not fifo_empty; - color_en(1) <= cg_draw; - color_in(0) <= to_color_t(fifo_color_out); - color_in(1) <= (X"FF", X"FF", X"FF", X"FF"); -- white opaque - color_op <= op_over; - vga_scan_rdy <= stat_hready and stat_vready; - -inst_linefifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(fifo_depth), - data_width => 32, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => vga_clk, - we => fifo_color_we, - re => fifo_color_re, - data_w => fifo_color_in, - data_r => fifo_color_out, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - fifo_color_in <= MDAT_I; - fifo_color_re <= stat_scan; - fifo_color_we <= ACK_I and read_bus_en; -- TODO: - MRDY_O <= not fifo_full; - SEL_O <= (others => '0'); - WE_O <= '0'; - -vga_master_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -vga_master: - process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt) - begin - - CYC_O <= '0'; - STB_O <= '0'; - pixel_cnt_rst <= '0'; - request_cnt_rst <= '0'; - request_cnt_en <= '0'; - read_bus_en <= '0'; - sn <= s; - - case s is - when init => - if stat_vga_rdy = '1' then - sn <= idle; - end if; - - when idle => - pixel_cnt_rst <= '1'; - if vga_master_en = '1' and vga_scan_rdy = '1' then - sn <= rdy; - end if; - - when rdy => --- pixel_cnt_rst <= '1'; - if fifo_almost_empty = '1' then - sn <= bus_request; - end if; - - when bus_request => - CYC_O <= '1'; - request_cnt_rst <= '1'; - if SRDY_I = '1' then - sn <= bus_access; - end if; - - when bus_access => - CYC_O <= '1'; - STB_O <= '1'; - request_cnt_en <= '1'; - read_bus_en <= '1'; - if fifo_almost_full = '1' then - sn <= bus_data; - end if; - when bus_data => - CYC_O <= '1'; - read_bus_en <= '1'; - if read_cnt = request_cnt then - sn <= rdy; - if vga_master_en = '0' then - sn <= idle; - end if; - end if; - when others => - sn <= idle; - - end case; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - request_cnt <= 0; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if request_cnt /= MAX_REQUEST_CNT-1 then - request_cnt <= request_cnt + 1; - end if; - end if; - end if; - end process; - -read_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - read_cnt <= 0; - elsif read_bus_en = '1' and ACK_I = '1' then - if read_cnt /= MAX_REQUEST_CNT-1 then - read_cnt <= read_cnt + 1; - end if; - end if; - end if; - end process; - -pixel_counter: - process(CLK_I) - variable pixel_cnt : natural range 0 to MAX_REQUEST_CNT-1; - begin - if rising_edge(CLK_I) then - if pixel_cnt_rst = '1' then - pixel_cnt := 0; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if pixel_cnt /= MAX_REQUEST_CNT-1 then - pixel_cnt := pixel_cnt + 1; - else - pixel_cnt := 0; - end if; - end if; - ADDR_O <= vga_mem_offset + (to_unsigned(pixel_cnt, 30) & "00"); - end if; - end process; - -inst_char_gen : entity work.char_gen - GENERIC MAP - ( - tsvga => tsvga, - CHARACTER_SCALE => 1, - CHAR_ROM_SIZE_X => 8, -- Pixels - CHAR_ROM_SIZE_Y => 16, -- Pixels - CHAR_ROM_DEPTH => 256, -- Chars - MAX_CHAR_PER_LINE => 80, -- Chars - MAX_LINE_PER_FRAME => 32, -- Chars - CHAR_SPACING_X => 0, -- Pixels - CHAR_SPACING_Y => 0, -- Pixels - SCREEN_OFFSET_X => 16, -- Pixels - SCREEN_OFFSET_Y => 16 -- Pixels - ) - PORT MAP - ( - rst => RST_I, - sys_clk => CLK_I, - vga_clk => vga_clk, - ce => cg_en, - frame_pulse => scan_rdy, - clr_screen => cg_clr_screen, - clr_line => cg_clr_line, - ascii_data => cg_ascii_data, - ascii_data_we => cg_ascii_data_we, - ascii_posy_we => cg_ascii_posy_we, - ascii_posx_we => cg_ascii_posx_we, - ready => cg_rdy, - pos_x => stat_hpos, - pos_y => stat_vpos, - char_draw_en => cg_draw - ); - SRDY_O <= CYC_I; -- and cg_rdy; - cg_ascii_data <= SDAT_I(7 downto 0); - cg_ascii_data_we <= ADDR_I(2) and CYC_I and STB_I and WE_I; - cg_ascii_posy_we <= ADDR_I(3) and CYC_I and STB_I and WE_I; - cg_ascii_posx_we <= ADDR_I(4) and CYC_I and STB_I and WE_I; - cg_clr_screen <= ADDR_I(5) and CYC_I and STB_I and WE_I; - cg_clr_line <= ADDR_I(6) and CYC_I and STB_I and WE_I; - SDAT_O <= X"0000000" & "000" & cg_rdy; - scan_rdy <= stat_hready and stat_vready; - cg_en <= stat_scan; - -data_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ACK_O <= '0'; - else - ACK_O <= CYC_I and STB_I and not WE_I; - end if; - end if; - end process; - -data_valid_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - vga_master_en <= '0'; - vga_mem_offset <= X"40000000"; - elsif (CYC_I and STB_I and WE_I) = '1' then - if ADDR_I(8) = '1' then - vga_master_en <= SDAT_I(0); - elsif ADDR_I(9) = '1' then - vga_mem_offset <= SDAT_I(31 downto 2) & "00"; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_frontend64.vhd b/lib/VGA_ctrl/src/vga_frontend64.vhd deleted file mode 100644 index 5276869..0000000 --- a/lib/VGA_ctrl/src/vga_frontend64.vhd +++ /dev/null @@ -1,436 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_frontend64 is - Generic - ( - sys_freq : integer := 100E6; - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(7 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(63 downto 0); - MDAT_O : out unsigned(63 downto 0); - - -- JBUS Slave signals - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_out : out std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_frontend64; - -architecture Behavioral of vga_frontend64 is - - - signal vga_clk : std_logic; - - -- Color FIFO signals - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal fifo_color_re : std_logic; - signal fifo_color_we : std_logic; - signal fifo_color_out : unsigned(63 downto 0); - signal fifo_color_in : unsigned(63 downto 0); - - -- Backend signals - signal scan_rdy : std_logic; - signal ctrl_scan_en : std_logic; - signal color_in : color_array_t; - signal color_op : color_op_t; - signal color_en : unsigned (VGA_NUM_CH-1 downto 0); - - signal stat_vga_rdy : std_logic; - signal stat_hready : std_logic; - signal stat_vready : std_logic; - signal stat_scan : std_logic; - signal stat_hscan : std_logic; - signal stat_vscan : std_logic; - signal stat_hsync : std_logic; - signal stat_vsync : std_logic; - signal stat_hpos : natural range 0 to tsvga.ts_h.ncyc_scan-1; - signal stat_vpos : natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- CG signals - signal cg_en : std_logic; - signal cg_rdy : std_logic; - signal cg_draw : std_logic; - signal cg_clr_screen : std_logic; - signal cg_clr_line : std_logic; - signal cg_ascii_data : unsigned(7 downto 0); - signal cg_ascii_data_we : std_logic; - signal cg_ascii_posy_we : std_logic; - signal cg_ascii_posx_we : std_logic; - signal cg_color : color_t; - - -- Bus master signals - constant MAX_REQUEST_CNT : natural := tsvga.ts_h.ncyc_scan*tsvga.ts_v.ncyc_scan; - - signal mem_offset : unsigned(31 downto 0); - signal vga_mem_offset : unsigned(31 downto 0); - signal vga_scan_rdy : std_logic; - signal vga_master_en : std_logic; - signal request_cnt_rst : std_logic; - signal request_cnt_en : std_logic; - signal pixel_cnt_rst : std_logic; - signal read_bus_en : std_logic; - signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1; - signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1; - - signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0); - - type vm_state_t is (init, idle, rdy, bus_request, bus_access, bus_data); - signal s, sn : vm_state_t; - -begin - - vga_clk_out <= vga_clk; - -inst_vga_backend : entity work.vga_backend - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - -- System signals - sys_rst => RST_I, - sys_clk => CLK_I, - - -- Color channels - color_in => color_in, - color_op => color_op, - color_en => color_en, - - -- Control signals - ctrl_scan_en => ctrl_scan_en, - - -- Status signals - stat_vga_rdy => stat_vga_rdy, - stat_scan => stat_scan, - stat_hsync => stat_hsync, - stat_vsync => stat_vsync, - stat_hready => stat_hready, - stat_vready => stat_vready, - stat_hscan => stat_hscan, - stat_vscan => stat_vscan, - stat_hpos => stat_hpos, - stat_vpos => stat_vpos, - - -- VGA domain signals - vga_clk_out => vga_clk, - vga_red => vga_red, - vga_green => vga_green, - vga_blue => vga_blue, - vga_blank_n => vga_blank_n, - vga_sync_n => vga_sync_n, - vga_hsync => vga_hsync, - vga_vsync => vga_vsync - ); - - odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length); - ctrl_scan_en <= '1'; - color_en(0) <= not fifo_empty; - color_en(1) <= cg_draw; - color_in(0) <= to_color_t(fifo_color_out(31 downto 0)) when odd_pixel(0) = '0' else to_color_t(fifo_color_out(63 downto 32)); - color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque - color_op <= op_over; - vga_scan_rdy <= stat_hready and stat_vready; - -inst_linefifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => NextExpBaseTwo(fifo_depth), - data_width => 64, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP - ( - rst => RST_I, - clk_w => CLK_I, - clk_r => vga_clk, - we => fifo_color_we, - re => fifo_color_re, - data_w => fifo_color_in, - data_r => fifo_color_out, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - fifo_color_in <= MDAT_I; - fifo_color_re <= stat_scan and odd_pixel(0); - fifo_color_we <= ACK_I and read_bus_en; -- TODO: - MRDY_O <= not fifo_full; - SEL_O <= (others => '0'); - WE_O <= '0'; - -vga_master_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - -vga_master: - process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt) - begin - - CYC_O <= '0'; - STB_O <= '0'; - pixel_cnt_rst <= '0'; - request_cnt_rst <= '0'; - request_cnt_en <= '0'; - read_bus_en <= '0'; - sn <= s; - - case s is - when init => - if stat_vga_rdy = '1' then - sn <= idle; - end if; - - when idle => - pixel_cnt_rst <= '1'; - if vga_master_en = '1' and vga_scan_rdy = '1' then - sn <= rdy; - end if; - - when rdy => --- pixel_cnt_rst <= '1'; - if fifo_almost_empty = '1' then - sn <= bus_request; - end if; - - when bus_request => - CYC_O <= '1'; - request_cnt_rst <= '1'; - if SRDY_I = '1' then - sn <= bus_access; - end if; - - when bus_access => - CYC_O <= '1'; - STB_O <= '1'; - request_cnt_en <= '1'; - read_bus_en <= '1'; - if fifo_almost_full = '1' then - sn <= bus_data; - end if; - when bus_data => - CYC_O <= '1'; - read_bus_en <= '1'; - if read_cnt = request_cnt then - sn <= rdy; - if vga_master_en = '0' then - sn <= idle; - end if; - end if; - when others => - sn <= idle; - - end case; - end process; - -request_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - request_cnt <= 0; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if request_cnt /= MAX_REQUEST_CNT-1 then - request_cnt <= request_cnt + 1; - end if; - end if; - end if; - end process; - -read_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if request_cnt_rst = '1' then - read_cnt <= 0; - elsif read_bus_en = '1' and ACK_I = '1' then - if read_cnt /= MAX_REQUEST_CNT-1 then - read_cnt <= read_cnt + 1; - end if; - end if; - end if; - end process; - -pixel_counter: - process(CLK_I) - variable pixel_cnt : natural range 0 to MAX_REQUEST_CNT/2-1; - begin - if rising_edge(CLK_I) then - if pixel_cnt_rst = '1' then - pixel_cnt := 0; - mem_offset <= vga_mem_offset; - elsif request_cnt_en = '1' and SRDY_I = '1' then - if pixel_cnt /= MAX_REQUEST_CNT/2-1 then - pixel_cnt := pixel_cnt + 1; - else - pixel_cnt := 0; - mem_offset <= vga_mem_offset; - end if; - end if; - ADDR_O <= mem_offset + (to_unsigned(pixel_cnt, 29) & "000"); - end if; - end process; - -inst_char_gen : entity work.char_gen - GENERIC MAP - ( - tsvga => tsvga, - CHARACTER_SCALE => 1, - CHAR_ROM_SIZE_X => 8, -- Pixels - CHAR_ROM_SIZE_Y => 16, -- Pixels - CHAR_ROM_DEPTH => 256, -- Chars - MAX_CHAR_PER_LINE => 80, -- Chars - MAX_LINE_PER_FRAME => 32, -- Chars - CHAR_SPACING_X => 0, -- Pixels - CHAR_SPACING_Y => 0, -- Pixels - SCREEN_OFFSET_X => 16, -- Pixels - SCREEN_OFFSET_Y => 16 -- Pixels - ) - PORT MAP - ( - rst => RST_I, - sys_clk => CLK_I, - vga_clk => vga_clk, - ce => cg_en, - frame_pulse => scan_rdy, - clr_screen => cg_clr_screen, - clr_line => cg_clr_line, - ascii_data => cg_ascii_data, - ascii_data_we => cg_ascii_data_we, - ascii_posy_we => cg_ascii_posy_we, - ascii_posx_we => cg_ascii_posx_we, - ready => cg_rdy, - pos_x => stat_hpos, - pos_y => stat_vpos, - char_draw_en => cg_draw - ); - SRDY_O <= CYC_I; -- and cg_rdy; - SDAT_O <= X"0000000" & "000" & cg_rdy; - scan_rdy <= stat_hready and stat_vready; - cg_en <= stat_scan; - -data_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ACK_O <= '0'; - else - ACK_O <= CYC_I and STB_I and not WE_I; - end if; - end if; - end process; - -data_valid_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cg_ascii_data_we <= '0'; - cg_ascii_posy_we <= '0'; - cg_ascii_posx_we <= '0'; - cg_clr_screen <= '0'; - cg_clr_line <= '0'; - if RST_I = '1' then - vga_master_en <= '0'; - vga_mem_offset <= X"40000000"; - cg_color <= (X"FF", X"FF", X"FF", X"FF"); - elsif (CYC_I and STB_I and WE_I) = '1' then - if ADDR_I(2) = '1' then - cg_ascii_data_we <= '1'; - cg_ascii_data <= SDAT_I(7 downto 0); - elsif ADDR_I(3) = '1' then - cg_ascii_posy_we <= '1'; - elsif ADDR_I(4) = '1' then - cg_ascii_posx_we <= '1'; - elsif ADDR_I(5) = '1' then - cg_clr_screen <= '1'; - elsif ADDR_I(6) = '1' then - cg_clr_line <= '1'; - elsif ADDR_I(7) = '1' then - cg_color <= to_color_t(SDAT_I(31 downto 0)); - elsif ADDR_I(8) = '1' then - vga_master_en <= SDAT_I(0); - elsif ADDR_I(9) = '1' then - vga_mem_offset <= SDAT_I(31 downto 2) & "00"; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd deleted file mode 100644 index 56e4384..0000000 --- a/lib/VGA_ctrl/src/vga_sync.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:15:39 10/21/05 --- Design Name: --- Module Name: fsm_scan - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_sync is - Generic - ( - ts : scan_timespec_t := (4,2,1,3,'0') - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - pos : out natural range 0 to ts.ncyc_scan-1; - sync : out std_logic; - is_scan : out std_logic; - rdy_scan : out std_logic - ); - end vga_sync; - -architecture Behavioral of vga_sync is - - type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back); - - -- Counter - signal state, next_state : timing_state_t; - signal count_srst : std_logic; - signal count : natural range 0 to ts.ncyc_scan-1; - -begin - - pos <= count; - ---------------------------------------------------------------------------------------------- -counter: - process (clk) - begin - if rising_edge(clk) then - if ce = '1' then - if count_srst = '1' then - count <= 0; - else - count <= count + 1; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------------------------- -SYNC_TIMING: -process (state, count) - begin - count_srst <= '0'; - rdy_scan <= '0'; - is_scan <= '0'; - sync <= '0'; - - next_state <= state; --default is to stay in current state - - case (state) is - - when st_init => - count_srst <= '1'; - next_state <= st_front; - when st_front => - if count = ts.ncyc_porch_front - 1 then - count_srst <= '1'; - next_state <= st_sync; - end if; - when st_sync => - sync <= '1'; - if count = ts.ncyc_sync_pulse - 1 then - count_srst <= '1'; - next_state <= st_back; - end if; - when st_back => - if count = ts.ncyc_porch_back - 1 then - count_srst <= '1'; - next_state <= st_scan; - end if; - when st_scan => - is_scan <= '1'; - if count = ts.ncyc_scan - 1 then - count_srst <= '1'; - rdy_scan <= '1'; - next_state <= st_front; - end if; - when others => - next_state <= st_init; - - end case; - end process; - -SYNC_TIMING_NEXT: - process (rst, clk) - begin - if rst = '1' then - state <= st_init; - elsif rising_edge(clk) and ce = '1' then - state <= next_state; - end if; - end process; - ---------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd deleted file mode 100644 index c110652..0000000 --- a/lib/VGA_ctrl/src/vga_timing.vhd +++ /dev/null @@ -1,102 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_timing is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - sys_rst : in std_logic; - vga_clk : in std_logic; - vga_ce : in std_logic; - sync_h : out std_logic; - sync_v : out std_logic; - scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - is_scan_h : out std_logic; - is_scan_v : out std_logic; - scan_rdy_h : out std_logic; - scan_rdy_v : out std_logic - ); -end vga_timing; - -architecture Behavioral of vga_timing is - - --------------------------------------------------------------------------------------------- - signal is_scan_h_i : std_logic; - signal is_scan_v_i : std_logic; - signal scan_rdy_h_i : std_logic; - signal scan_rdy_v_i : std_logic; - signal sync_h_i : std_logic; - signal sync_v_i : std_logic; - - --------------------------------------------------------------------------------------------- -begin - - is_scan_h <= is_scan_h_i; - is_scan_v <= is_scan_v_i; - scan_rdy_h <= scan_rdy_h_i; - scan_rdy_v <= scan_rdy_v_i; - sync_h <= sync_h_i; - sync_v <= sync_v_i; - - --------------------------------------------------------------------------------------------- - inst_vga_sync_h: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_h - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => vga_ce, - pos => scan_pos_h, - sync => sync_h_i, - is_scan => is_scan_h_i, - rdy_scan => scan_rdy_h_i - ); - - inst_vga_sync_v: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_v - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => scan_rdy_h_i, - pos => scan_pos_v, - sync => sync_v_i, - is_scan => is_scan_v_i, - rdy_scan => scan_rdy_v_i - ); - ---------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd deleted file mode 100644 index 80667c2..0000000 --- a/lib/VGA_ctrl/src/vga_types.vhd +++ /dev/null @@ -1,241 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package vga_types is - - -- Constants - constant VGA_NUM_CH : natural := 2; - - -- Types - type color_range_t is (r, g, b, a); - type color_t is array (color_range_t) of unsigned(7 downto 0); - type color_array_t is array (0 to VGA_NUM_CH-1) of color_t; - - type color_op_t is (op_over, op_xor, op_alpha); - - type scan_timespec_t is - record - ncyc_scan : integer; - ncyc_porch_front : integer; - ncyc_sync_pulse : integer; - ncyc_porch_back : integer; - sync_polarity : std_logic; - end record; - - type vga_timespec_t is - record - f_pxl_clk : integer; - nfps : integer; - ts_h : scan_timespec_t; - ts_v : scan_timespec_t; - end record; - - ----------------------------------------------------------------------- - -- Common timimg specifications - ----------------------------------------------------------------------- - -- For test bench (not for H/W use) - constant ts_vga_testbench : vga_timespec_t := - ( - f_pxl_clk => 100E6, - nfps => 6, - ts_h => (80,5,2,3,'0'), - ts_v => (60,4,2,3,'0') - ); - - -- 640 x 480 @ 60 Hz (not recommended) - constant ts_vga_640_480_60 : vga_timespec_t := - ( - f_pxl_clk => 25175000, - nfps => 60, - ts_h => (640,16,96,48,'0'), - ts_v => (480,11,2,31,'0') - ); - - -- 640 x 480 @ 72 Hz (not recommended) - constant ts_vga_640_480_72 : vga_timespec_t := - ( - f_pxl_clk => 31500000, - nfps => 72, - ts_h => (640,24,40,128,'0'), - ts_v => (480,9,3,28,'0') - ); - - -- 800 x 600 @ 60 Hz (OK) - constant ts_vga_800_600_60 : vga_timespec_t := - ( - f_pxl_clk => 40000000, - nfps => 60, - ts_h => (800,40,128,88,'0'), - ts_v => (600,1,4,23,'0') - ); - - -- 800 x 600 @ 72 Hz (OK) - constant ts_vga_800_600_72 : vga_timespec_t := - ( - f_pxl_clk => 50000000, - nfps => 72, - ts_h => (800,56,120,64,'0'), - ts_v => (600,37,6,23,'0') - ); - - -- 1024 x 768 @ 60 Hz (Noisy) - constant ts_vga_1024_768_60 : vga_timespec_t := - ( - f_pxl_clk => 65000000, - nfps => 60, - ts_h => (1024,24,136,160,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1024 x 768 @ 70 Hz (OK) - constant ts_vga_1024_768_70 : vga_timespec_t := - ( - f_pxl_clk => 75000000, - nfps => 70, - ts_h => (1024,24,136,144,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1280 x 1024 @ 70 Hz (Noisy) - constant ts_vga_1280_1024_70 : vga_timespec_t := - ( - f_pxl_clk => 125000000, - nfps => 70, - ts_h => (1280,16,176,192,'0'), - ts_v => (1024,3,3,42,'0') - ); - - -- 1280 x 1024 @ 72 Hz (OK) - constant ts_vga_1280_1024_72 : vga_timespec_t := - ( - f_pxl_clk => 130000000, - nfps => 72, - ts_h => (1280,32,160,224,'0'), - ts_v => (1024,2,2,33,'0') - ); - - -- Functions - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - function DCM_PERIOD(f_sys_hz : natural) return real; - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural; - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural; - - function to_color_t(x : unsigned) return color_t; - function to_unsigned(x : color_t) return unsigned; - -end vga_types; - - -package body vga_types is - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - begin - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - m := f_vga_mhz/GCD(f_sys_mhz, f_vga_mhz); - - if m = 1 then - m := 2; - end if; - - return m; - - end DCM_FREQ_M; - - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - variable d : natural; - begin - m := DCM_FREQ_M(f_sys_hz, f_vga_hz); - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - d := m*f_sys_mhz/f_vga_mhz; - - return d; - - end DCM_FREQ_D; - - function DCM_PERIOD(f_sys_hz : natural) return real is - begin - - return 1.0E9/real(f_sys_hz); - - end DCM_PERIOD; - - function to_color_t(x : unsigned) return color_t is - variable result : color_t; - begin - result(r) := x(x'right+7 downto x'right+0); - result(g) := x(x'right+15 downto x'right+8); - result(b) := x(x'right+23 downto x'right+16); - result(a) := x(x'right+31 downto x'right+24); - - return result; - end to_color_t; - - function to_unsigned(x : color_t) return unsigned is - variable result : unsigned(31 downto 0); - begin - result(7 downto 0) := x(r); - result(15 downto 8) := x(g); - result(23 downto 16) := x(b); - result(31 downto 24) := x(a); - - return result; - end to_unsigned; - -end vga_types; - - diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo b/lib/ac97_ctrl/sim/tb_ac97_wb.fdo deleted file mode 100644 index bbdc249..0000000 --- a/lib/ac97_ctrl/sim/tb_ac97_wb.fdo +++ /dev/null @@ -1,20 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../misc/dpram_1w1r_dist.vhd" -vcom -explicit -93 "../../FIFO/src/fifo_sync_dist.vhd" -vcom -explicit -93 "../../misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/core/ac_io.vhd" -vcom -explicit -93 "../src/core/ac97_wb.vhd" -vcom -explicit -93 "../src/tb_ac97_wb.vhd" -vsim -t 1ps -lib work tb_ac97_wb -do {tb_ac97_wb.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo b/lib/ac97_ctrl/sim/tb_ac97_wb.wdo deleted file mode 100644 index f7e1885..0000000 --- a/lib/ac97_ctrl/sim/tb_ac97_wb.wdo +++ /dev/null @@ -1,77 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Logic /tb_ac97_wb/rst_o -add wave -noupdate -format Logic /tb_ac97_wb/int_i -add wave -noupdate -format Logic /tb_ac97_wb/cyc_o -add wave -noupdate -format Logic /tb_ac97_wb/stb_o -add wave -noupdate -format Logic /tb_ac97_wb/we_o -add wave -noupdate -format Logic /tb_ac97_wb/ack_i -add wave -noupdate -format Logic /tb_ac97_wb/mrdy_o -add wave -noupdate -format Logic /tb_ac97_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dat_o -add wave -noupdate -format Logic /tb_ac97_wb/dout_rst -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/dout_reg -add wave -noupdate -format Literal /tb_ac97_wb/dout_cnt -add wave -noupdate -format Logic /tb_ac97_wb/ac97_bit_clk -add wave -noupdate -format Logic /tb_ac97_wb/ac97_reset_n -add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_out -add wave -noupdate -format Logic /tb_ac97_wb/ac97_ssync -add wave -noupdate -format Logic /tb_ac97_wb/ac97_sdata_in -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_reg_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/cmd_pending -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_cmd_addr -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_cmd_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_tx_pcm_we -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/stat_reg -add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_reg_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/stat_pending -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac_stat_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_tx_pcm_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_rx_pcm_addr -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_sync_strobe -add wave -noupdate -format Literal /tb_ac97_wb/uut/ac_slot_valid -add wave -noupdate -format Logic /tb_ac97_wb/uut/ac_ready -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_data_start -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_status -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_frame -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_frame_valid -add wave -noupdate -format Logic /tb_ac97_wb/uut/sync_tx -add wave -noupdate -format Literal /tb_ac97_wb/uut/request -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/tx_fifo_dout -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_full -add wave -noupdate -format Logic /tb_ac97_wb/uut/tx_fifo_empty -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_data_start -add wave -noupdate -format Logic /tb_ac97_wb/clk_o -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/rx_fifo_dout -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_re -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_we -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_full -add wave -noupdate -format Logic /tb_ac97_wb/uut/rx_fifo_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_ac97_wb/uut/ac97_stat -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {200000401 ps} 0} {{Cursor 2} {699514236 ps} 0} {{Cursor 4} {4999959266 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {699260742 ps} {700038909 ps} diff --git a/lib/ac97_ctrl/sim/tb_ac_in.fdo b/lib/ac97_ctrl/sim/tb_ac_in.fdo deleted file mode 100644 index fd7fb1f..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_in.fdo +++ /dev/null @@ -1,14 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/tb_ac_in.vhd" -vsim -t 1ps -lib work tb_ac_in -do {tb_ac_in.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac_in.wdo b/lib/ac97_ctrl/sim/tb_ac_in.wdo deleted file mode 100644 index a7d0e35..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_in.wdo +++ /dev/null @@ -1,43 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_in/uut/rst -add wave -noupdate -format Logic /tb_ac_in/uut/clk -add wave -noupdate -format Logic /tb_ac_in/uut/sync_frame -add wave -noupdate -format Logic /tb_ac_in/uut/sync_status -add wave -noupdate -divider {AC97 lines} -add wave -noupdate -format Logic /tb_ac_in/uut/ac_reset -add wave -noupdate -format Logic /tb_ac_in/uut/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_in/uut/ac_sdata_in -add wave -noupdate -format Logic /tb_ac_in/uut/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/stat_data -add wave -noupdate -format Literal /tb_ac_in/uut/pcm_out_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/pcm_out_data -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_ac_in/uut/data_array -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/tag -add wave -noupdate -format Literal /tb_ac_in/uut/sac -add wave -noupdate -format Literal /tb_ac_in/uut/bitcnt -add wave -noupdate -format Literal /tb_ac_in/uut/slotcnt -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_in/uut/rx_reg -add wave -noupdate -format Logic /tb_ac_in/uut/stat_read -add wave -noupdate -format Logic /tb_ac_in/uut/host_update -add wave -noupdate -format Logic /tb_ac_in/uut/slot_end -add wave -noupdate -format Logic /tb_ac_in/uut/sync_end -add wave -noupdate -format Logic /tb_ac_in/uut/last_slot -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {53431686 ps} 0} {{Cursor 2} {44308511 ps} 0} {{Cursor 4} {677821715 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {52190046 ps} {56168939 ps} diff --git a/lib/ac97_ctrl/sim/tb_ac_io.fdo b/lib/ac97_ctrl/sim/tb_ac_io.fdo deleted file mode 100644 index 4b0180f..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_io.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/core/ac_in.vhd" -vcom -explicit -93 "../src/core/ac_io.vhd" -vcom -explicit -93 "../src/tb_ac_io.vhd" -vsim -t 1ps -lib work tb_ac_io -do {tb_ac_io.wdo} -view wave -view structure -view signals -run 700us diff --git a/lib/ac97_ctrl/sim/tb_ac_io.wdo b/lib/ac97_ctrl/sim/tb_ac_io.wdo deleted file mode 100644 index b445bdb..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_io.wdo +++ /dev/null @@ -1,51 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_io/uut/rst -add wave -noupdate -format Logic /tb_ac_io/uut/clk -add wave -noupdate -format Logic /tb_ac_io/uut/ready -add wave -noupdate -format Literal /tb_ac_io/uut/slot_valid -add wave -noupdate -format Logic /tb_ac_io/uut/sync_strobe -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/stat_data -add wave -noupdate -format Literal /tb_ac_io/uut/rx_pcm_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/rx_pcm_data -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/cmd_data -add wave -noupdate -format Logic /tb_ac_io/uut/cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/tx_pcm_data -add wave -noupdate -format Logic /tb_ac_io/uut/tx_pcm_we -add wave -noupdate -divider {AC97 lines} -add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_in -add wave -noupdate -format Logic /tb_ac_io/uut/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_io/uut/ac_reset_n -add wave -noupdate -format Logic /tb_ac_io/uut/ac_sdata_out -add wave -noupdate -format Logic /tb_ac_io/uut/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_in/stat_read -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/rx_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_out/tx_reg -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/bitcnt -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/sac -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_io/uut/inst_ac_in/tag -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_in/data_array -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/bitcnt -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slotcnt -add wave -noupdate -format Logic /tb_ac_io/uut/inst_ac_out/ssync -add wave -noupdate -format Literal /tb_ac_io/uut/inst_ac_out/slot_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {0 ps} 0} {{Cursor 2} {292930000 ps} 0} {{Cursor 4} {4999959266 ps} 0} -configure wave -namecolwidth 173 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {735 us} diff --git a/lib/ac97_ctrl/sim/tb_ac_out.fdo b/lib/ac97_ctrl/sim/tb_ac_out.fdo deleted file mode 100644 index ac9d3c4..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_out.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## Autogenerated by ProjNav (creatfdo.tcl) on Tue Jun 05 17:37:16 Westeuropäische Normalzeit 2007 -## -vlib work -vcom -explicit -93 "../../../lib/src/misc/singleshot.vhd" -vcom -explicit -93 "../src/core/ac_out.vhd" -vcom -explicit -93 "../src/tb_ac_out.vhd" -vsim -t 1ps -lib work tb_ac_out -do {tb_ac_out.wdo} -view wave -view structure -view signals -run 600us diff --git a/lib/ac97_ctrl/sim/tb_ac_out.wdo b/lib/ac97_ctrl/sim/tb_ac_out.wdo deleted file mode 100644 index b9d9a25..0000000 --- a/lib/ac97_ctrl/sim/tb_ac_out.wdo +++ /dev/null @@ -1,41 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ac_out/rst -add wave -noupdate -format Logic /tb_ac_out/clk -add wave -noupdate -format Logic /tb_ac_out/ce -add wave -noupdate -divider {Host hand shake} -add wave -noupdate -format Logic /tb_ac_out/sync_tx -add wave -noupdate -divider {Command I/F} -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/cmd_data -add wave -noupdate -format Logic /tb_ac_out/uut/cmd_we -add wave -noupdate -divider {PCM I/F} -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/pcm_in_data -add wave -noupdate -format Logic /tb_ac_out/pcm_in_we -add wave -noupdate -divider {AC97 I/F} -add wave -noupdate -format Logic /tb_ac_out/ac_bit_clk -add wave -noupdate -format Logic /tb_ac_out/ac_reset -add wave -noupdate -format Logic /tb_ac_out/ac_sdata_out -add wave -noupdate -format Logic /tb_ac_out/ac_ssync -add wave -noupdate -divider Debug -add wave -noupdate -format Literal -radix hexadecimal /tb_ac_out/uut/tx_reg -add wave -noupdate -format Literal /tb_ac_out/uut/sac -add wave -noupdate -format Literal /tb_ac_out/uut/bitcnt -add wave -noupdate -format Literal /tb_ac_out/uut/slotcnt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {544839100 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {532851785 ps} {556826415 ps} diff --git a/lib/ac97_ctrl/src/core/ac97_wb.vhd b/lib/ac97_ctrl/src/core/ac97_wb.vhd deleted file mode 100644 index 1b4fb57..0000000 --- a/lib/ac97_ctrl/src/core/ac97_wb.vhd +++ /dev/null @@ -1,330 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY ac97_wb IS - Generic - ( - fifo_depth : natural := 8 - ); - Port - ( - -- J-Bus domain - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - - -- AC97 domain - ac97_sdata_in : in std_logic; - ac97_bit_clk : in std_logic; - ac97_reset_n : out std_logic; - ac97_sdata_out : out std_logic; - ac97_ssync : out std_logic - ); -END ac97_wb; - -ARCHITECTURE behavior OF ac97_wb IS - - constant ac_data_width : natural := 20; - constant pcm_data_width : natural := 18; - constant stat_data_width : natural := 16; - signal cmd_reg_we : std_logic; - signal cmd_pending : std_logic; - signal ac_cmd_data : unsigned(ac_data_width-1 downto 0); - signal ac_cmd_addr : unsigned(ac_data_width-1 downto 0); - signal ac_cmd_we : std_logic; - signal ac_tx_pcm_we : std_logic; - - signal stat_reg : unsigned(stat_data_width-1 downto 0); - signal stat_reg_re : std_logic; - signal stat_valid : std_logic; - signal stat_pending : std_logic; - signal ac_stat_data : unsigned(ac_data_width-1 downto 0); - signal ac_stat_addr : unsigned(ac_data_width-1 downto 0); - signal ac_stat_read : std_logic; - signal ac_stat_valid : std_logic; - - signal ac_tx_pcm_data : unsigned(ac_data_width-1 downto 0); - signal ac_tx_pcm_addr : unsigned (3 downto 0); - signal ac_rx_pcm_data : unsigned(ac_data_width-1 downto 0); - signal ac_rx_pcm_addr : unsigned (3 downto 0); - signal ac_sync_strobe : unsigned(0 to 2); - signal ac_slot_valid : unsigned(0 to 12); - signal ac_ready : std_logic; - signal rx_frame_valid : std_logic; - signal sync_frame : std_logic; - signal sync_tx : std_logic; - signal sync_status : std_logic; - signal request : unsigned(3 to 12); - - signal tx_data_start : std_logic; - signal tx_fifo_din : unsigned(pcm_data_width-1 downto 0); - signal tx_fifo_dout : unsigned(pcm_data_width-1 downto 0); - signal tx_fifo_re : std_logic; - signal tx_fifo_we : std_logic; - signal tx_fifo_full : std_logic; - signal tx_fifo_empty : std_logic; - signal tx_fifo_almost_full : std_logic; - signal tx_fifo_almost_empty : std_logic; - - signal rx_data_irq : std_logic; - signal rx_data_ack : std_logic; - - signal ac97_stat : unsigned(31 downto 0); - signal addr_reg : unsigned(31 downto 0); - signal data_reg : unsigned(31 downto 0); - signal int_en_frame_sync : std_logic; - signal int_en_rx : std_logic; - signal int_en_tx : std_logic; - signal rx_en : std_logic; - signal tx_en : std_logic; - signal rx_fifo_rst : std_logic; - signal tx_fifo_rst : std_logic; - - function GetRequest(slot1 : unsigned) return unsigned is - variable res : unsigned(3 to 12); - begin - res := (others => '0'); - for i in res'range loop - res(i) := not slot1(14-i); - end loop; - return res; - - end GetRequest; - - type ac_state_t is (reset, idle, pcm_3, pcm_4); - signal rx_state, rx_state_n : ac_state_t; - -begin - - SRDY_O <= CYC_I; - INT_O <= (rx_data_irq and int_en_rx) or (not tx_fifo_full and int_en_tx) or (sync_frame and int_en_frame_sync) ; - - rx_frame_valid <= ac_slot_valid(0); - sync_frame <= ac_sync_strobe(0); - sync_status <= ac_sync_strobe(1); - sync_tx <= ac_sync_strobe(2); - request <= GetRequest(ac_stat_addr); - - ac_stat_read <= not addr_reg(9); - ac_stat_valid <= '1' when (sync_status = '1' and ac_slot_valid(0 to 2) = "111") else '0'; - ac97_stat <= ac_ready & '0' & X"00000" & '0' & int_en_rx & int_en_tx & int_en_frame_sync & '0' & tx_fifo_full & rx_data_irq & tx_fifo_almost_full & stat_valid & cmd_pending; - -command_logic: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - ac_cmd_we <= '0'; - if RST_I = '1' then - cmd_pending <= '0'; - elsif cmd_reg_we = '1' and cmd_pending = '0' then - cmd_pending <= '1'; - elsif (rx_frame_valid and sync_tx) = '1' and cmd_pending = '1' then - ac_cmd_we <= '1'; - cmd_pending <= '0'; - end if; - end if; - end process; - -status_logic: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - if RST_I = '1' then - stat_pending <= '0'; - elsif cmd_reg_we = '1' and cmd_pending = '0' then - stat_pending <= ac_stat_read; - elsif ac_stat_valid = '1' then - stat_pending <= '0'; - end if; - end if; - end process; - -command_register: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if cmd_reg_we = '1' and cmd_pending = '0' then - ac_cmd_addr <= ac_stat_read & addr_reg(8 downto 2) & X"000"; - ac_cmd_data <= data_reg(stat_data_width-1 downto 0) & X"0"; - end if; - end if; - end process; - -status_register: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - if RST_I = '1' then - stat_valid <= '0'; - elsif stat_pending = '1' and ac_stat_valid = '1' then - stat_reg <= ac_stat_data(ac_data_width-1 downto ac_data_width-stat_data_width); - stat_valid <= '1'; - elsif stat_reg_re = '1' then - stat_valid <= '0'; - end if; - end if; - end process; - - -- Instantiate synchronous FIFO -inst_tx_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => pcm_data_width, - almost_full_thresh => 90*(2**fifo_depth)/100, - almost_empty_thresh => 10*(2**fifo_depth)/100 - ) - PORT MAP - ( - rst => tx_fifo_rst, - clk => CLK_I, - we => tx_fifo_we, - re => tx_fifo_re, - fifo_full => tx_fifo_full, - fifo_empty => tx_fifo_empty, - fifo_afull => tx_fifo_almost_full, - fifo_aempty => tx_fifo_almost_empty, - data_w => tx_fifo_din, - data_r => tx_fifo_dout - ); - tx_fifo_rst <= not tx_en or RST_I; - -tx_logic: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' or tx_en = '0' then - ac_tx_pcm_addr <= "0011"; - tx_data_start <= '0'; - elsif sync_tx = '1' and (request(3) and request(4)) = '1' then - ac_tx_pcm_addr <= "0011"; - tx_data_start <= '1'; - elsif ac_tx_pcm_addr /= "0100" then - ac_tx_pcm_addr <= ac_tx_pcm_addr + 1; - else - tx_data_start <= '0'; - end if; - end if; - end process; - - ac_tx_pcm_we <= not tx_fifo_empty and tx_data_start; - tx_fifo_re <= ac_tx_pcm_we; - - tx_fifo_din <= data_reg(pcm_data_width-1 downto 0); - - ac_rx_pcm_addr <= addr_reg(5 downto 2); - -rx_logic: - process (CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - rx_data_irq <= '0'; - elsif rx_frame_valid = '1' and sync_frame = '1' then - if ac_slot_valid(3) = '1' and ac_slot_valid(4) = '1' then - rx_data_irq <= rx_en; - end if; - elsif rx_data_ack = '1' then - rx_data_irq <= '0'; - end if; - end if; - end process; - -inst_ac_io : entity work.ac_io - PORT MAP - ( - rst => RST_I, - clk => CLK_I, - ready => ac_ready, - sync_strobe => ac_sync_strobe, - slot_valid => ac_slot_valid, - stat_addr => ac_stat_addr, - stat_data => ac_stat_data, - rx_pcm_addr => ac_rx_pcm_addr, - rx_pcm_data => ac_rx_pcm_data, - cmd_addr => ac_cmd_addr, - cmd_data => ac_cmd_data, - cmd_we => ac_cmd_we, - tx_pcm_addr => ac_tx_pcm_addr, - tx_pcm_data => ac_tx_pcm_data, - tx_pcm_we => ac_tx_pcm_we, - ac_sdata_in => ac97_sdata_in, - ac_bit_clk => ac97_bit_clk, - ac_reset_n => ac97_reset_n, - ac_sdata_out => ac97_sdata_out, - ac_ssync => ac97_ssync - ); - - ac_tx_pcm_data <= tx_fifo_dout & (ac_data_width-pcm_data_width-1 downto 0 => '0'); - -slave_data_out: - process (CLK_I) - begin - - if rising_edge(CLK_I) then - tx_fifo_we <= '0'; - stat_reg_re <= '0'; - cmd_reg_we <= '0'; - rx_data_ack <= '0'; - ACK_O <= '0'; - if RST_I = '1' then - addr_reg <= (others => '0'); - int_en_frame_sync <= '0'; - int_en_rx <= '0'; - int_en_tx <= '0'; - tx_en <= '0'; - rx_en <= '0'; - else --- DAT_O <= (others => '-'); - - if (STB_I and CYC_I) = '1' then - ACK_O <= not WE_I; - - case ADDR_I(11 downto 10) is - - when "00" => - DAT_O <= ac97_stat; - if WE_I = '1' then - int_en_frame_sync <= DAT_I(0); - int_en_tx <= DAT_I(1); - int_en_rx <= DAT_I(2); - tx_en <= DAT_I(4); - rx_en <= DAT_I(5); - end if; - when "01" => - addr_reg <= ADDR_I; - data_reg <= DAT_I; - stat_reg_re <= not WE_I; - cmd_reg_we <= WE_I; - DAT_O <= (31 downto stat_data_width => '0') & stat_reg; - - when "10" => - rx_data_ack <= not WE_I; - addr_reg <= ADDR_I; - data_reg <= DAT_I; - tx_fifo_we <= WE_I; - DAT_O <= (31 downto pcm_data_width => ac_rx_pcm_data(ac_data_width-1)) & ac_rx_pcm_data(ac_data_width-1 downto ac_data_width-pcm_data_width); - - when others => null; - - end case; - end if; - end if; - end if; - - end process; - -end behavior; diff --git a/lib/ac97_ctrl/src/core/ac_in.vhd b/lib/ac97_ctrl/src/core/ac_in.vhd deleted file mode 100644 index a072a9b..0000000 --- a/lib/ac97_ctrl/src/core/ac_in.vhd +++ /dev/null @@ -1,309 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 08:27:43 08/26/2006 --- Design Name: --- Module Name: ac_out - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_in is - Port ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); -end ac_in; - -architecture Behavioral of ac_in is - ------------------------------------------------------------------- -COMPONENT singleshot -GENERIC (mode : integer); -PORT( - rst : IN std_logic; - clk : IN std_logic; - input : IN std_logic; - output : OUT std_logic - ); -END COMPONENT; - ------------------------------------------------------------------- -type sac_t is (ac_idle, ac_tag, ac_data); -subtype bitcnt_t is integer range 0 to 19; -subtype slotcnt_t is integer range 0 to 12; -subtype slot_valid_t is UNSIGNED(0 to 12); -subtype tag_t is UNSIGNED(15 downto 0); -subtype slot_t is UNSIGNED(19 downto 0); -type slot_array_t is array (natural range <>) of slot_t; - -signal data_array : slot_array_t (1 to 12); -signal tag : tag_t; - -signal sac, snac : sac_t; -signal bitcnt : bitcnt_t; -signal bitcnt_rst, bitcnt_en : STD_LOGIC; -signal slotcnt : slotcnt_t; -signal slotcnt_rst, slotcnt_en : STD_LOGIC; - -signal rx_reg : slot_t; -signal stat_read, host_update : STD_LOGIC; -signal sync_end, slot_end, last_slot, start_of_frame : STD_LOGIC; - ------------------------------------------------------------------- -function GetSlotValid(data : tag_t) return slot_valid_t is -variable res : slot_valid_t := (others => '0'); -begin - res := (others => '0'); - for i in slot_valid_t'range loop - res(i) := data(data'left-i); - end loop; - return res; - -end GetSlotValid; - ------------------------------------------------------------------- -begin - -------------------------------------------------------------- --- proc_status_flags -------------------------------------------------------------- -proc_status_flags: -process (rst, clk, host_update, tag, data_array) -begin - if rising_edge(clk) then - sync_status <= '0'; - if rst = '1' then - slot_valid <= (others => '0'); - stat_addr <= (others => '0'); - stat_data <= (others => '0'); - elsif host_update = '1' then - sync_status <= '1'; - slot_valid <= GetSlotValid(tag); - stat_addr <= data_array(1); - stat_data <= data_array(2); - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_pcm_data -------------------------------------------------------------- -proc_pcm_data: -process (clk, pcm_out_addr, data_array) -variable slot_id : integer range 0 to 12; -begin - pcm_out_data <= (others => '-'); - slot_id := to_integer(pcm_out_addr); - if (slot_id > 2) then - pcm_out_data <= data_array(slot_id); - end if; -end process; - -------------------------------------------------------------- --- proc_read_data -------------------------------------------------------------- -proc_read_data : -process (ac_reset, ac_bit_clk, slot_end, slotcnt) -begin - - if ac_reset = '1' then - stat_read <= '0'; - elsif rising_edge(ac_bit_clk) then - stat_read <= '0'; - if slot_end = '1' and slotcnt /= 0 then - data_array(slotcnt) <= rx_reg; - if slotcnt = 2 then - stat_read <= '1'; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_read_stat -------------------------------------------------------------- -proc_read_tag : -process (ac_reset, ac_bit_clk, sync_end) -begin - - if ac_reset = '1' then - tag <= (others => '0'); - elsif rising_edge(ac_bit_clk) then - if sync_end = '1' then - tag <= rx_reg(15 downto 0); - end if; - end if; - -end process; - -------------------------------------------------------------- --- proc_slot_count -------------------------------------------------------------- -proc_slot_count: -process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt) -begin - if rising_edge(ac_bit_clk) then - if slotcnt_rst = '1' then - slotcnt <= slotcnt_t'low; - elsif slotcnt_en = '1' then - if slotcnt /= slotcnt_t'high then - slotcnt <= slotcnt + 1; - else - slotcnt <= slotcnt_t'low; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_bit_count -------------------------------------------------------------- -proc_bit_count: -process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt) -begin - if rising_edge(ac_bit_clk) then - if bitcnt_rst = '1' then - bitcnt <= bitcnt_t'low; - elsif bitcnt_en = '1' then - if bitcnt /= bitcnt_t'high then - bitcnt <= bitcnt + 1; - else - bitcnt <= bitcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_fsm: -process (bitcnt, slotcnt, sac, ac_ssync) -begin - snac <= sac; - bitcnt_rst <= '0'; - bitcnt_en <= '1'; - slotcnt_rst <= '0'; - slotcnt_en <= '0'; - slot_end <= '0'; - sync_end <= '0'; - last_slot <= '0'; - start_of_frame <= '0'; - - if bitcnt = 19 then - slot_end <= '1'; - end if; - if slotcnt = 12 and bitcnt = 19 then - last_slot <= '1'; - end if; - - case sac is - - when ac_idle => - bitcnt_rst <= '1'; - slotcnt_rst <= '1'; - if (ac_ssync = '1') then - snac <= ac_tag; - end if; - - when ac_tag => - if (bitcnt = 0) then - start_of_frame <= '1'; - elsif (bitcnt = 15) then - slotcnt_en <= '1'; - bitcnt_rst <= '1'; - sync_end <= '1'; - if (ac_ssync = '0') then - snac <= ac_data; - else - snac <= ac_idle; - end if; - end if; - - when ac_data => - if bitcnt = 19 then - slotcnt_en <= '1'; - if slotcnt = 12 then - slotcnt_rst <= '1'; - snac <= ac_tag; - end if; - end if; - when others => null; - end case; -end process; - -proc_ac_fsm_next: -process (ac_reset, ac_bit_clk, snac) -begin - if ac_reset = '1' then - sac <= ac_idle; - elsif rising_edge(ac_bit_clk) then - sac <= snac; - end if; -end process; - -------------------------------------------------------------- --- Receive Shift Register -------------------------------------------------------------- -process (ac_reset, ac_bit_clk, ac_sdata_in) -begin - if ac_reset = '1' then - rx_reg <= (others => '0'); - elsif falling_edge(ac_bit_clk) then - rx_reg <= rx_reg(rx_reg'left-1 downto 0) & ac_sdata_in; - end if; -end process; - ------------------------------------------------------------------- -singleshot_inst1: singleshot -GENERIC MAP ( - mode => 0) -PORT MAP( - rst => rst, - clk => clk, - input => stat_read, - output => host_update -); - -singleshot_inst2: singleshot -GENERIC MAP ( - mode => 1) -PORT MAP( - rst => rst, - clk => clk, - input => start_of_frame, - output => sync_frame -); - -------------------------------------------------------------- - -end Behavioral; - diff --git a/lib/ac97_ctrl/src/core/ac_io.vhd b/lib/ac97_ctrl/src/core/ac_io.vhd deleted file mode 100644 index 211a5ef..0000000 --- a/lib/ac97_ctrl/src/core/ac_io.vhd +++ /dev/null @@ -1,189 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 18:29:55 08/26/2006 --- Design Name: --- Module Name: ac_io - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_io is - Port - ( - rst : in std_logic; - clk : in std_logic; - ready : out std_logic; - sync_strobe : out unsigned(0 to 2); - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - rx_pcm_addr : in unsigned (3 downto 0); - rx_pcm_data : out unsigned (19 downto 0); - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - tx_pcm_addr : in unsigned(3 downto 0); - tx_pcm_data : in unsigned(19 downto 0); - tx_pcm_we : in std_logic; - ac_sdata_in : in std_logic; - ac_bit_clk : in std_logic; - ac_reset_n : out std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); -end ac_io; - -architecture Behavioral of ac_io is - - COMPONENT ac_in - Port - ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); - END COMPONENT; - - COMPONENT ac_out - PORT - ( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned(3 downto 0); - pcm_in_data : in unsigned(19 downto 0); - pcm_in_we : in std_logic; - ac_bit_clk : in std_logic; - ac_reset : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - SIGNAL ac_reset : std_logic; - SIGNAL ssync_rx : std_logic; - SIGNAL ssync_tx : std_logic; - SIGNAL sync_frame : std_logic; - SIGNAL sync_status : std_logic; - SIGNAL sync_tx : std_logic; - -begin - -inst_ac_in: ac_in - PORT MAP - ( - rst => rst, - clk => clk, - sync_frame => sync_frame, - sync_status => sync_status, - slot_valid => slot_valid, - stat_addr => stat_addr, - stat_data => stat_data, - pcm_out_addr => rx_pcm_addr, - pcm_out_data => rx_pcm_data, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_in => ac_sdata_in, - ac_ssync => ssync_rx - ); - -inst_ac_out: ac_out - PORT MAP - ( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => tx_pcm_addr, - pcm_in_data => tx_pcm_data, - pcm_in_we => tx_pcm_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ssync_tx - ); - - ------------------------------------------------------------------ - ready <= not ac_reset; - ac_ssync <= ssync_tx; - ssync_rx <= ssync_tx; - sync_strobe <= sync_frame & sync_status & sync_tx; - - ------------------------------------------------------------------ - proc_reset_gen: - process (rst, clk, ac_bit_clk) - type rstate_t is (s0, s1); - variable rstate, rstaten : rstate_t; - subtype cnt_t is integer range 0 to 999; - variable cnt : cnt_t; - begin - if rising_edge(clk) then - if rst = '1' then - rstate := s0; - cnt := cnt_t'high; - ac_reset <= '1'; - ac_reset_n <= '0'; - else - rstaten := rstate; - case rstate is - when s0 => - if cnt /= 0 then - cnt := cnt - 1; - else - ac_reset_n <= '1'; - if ac_bit_clk = '1' then - rstaten := s1; - cnt := cnt_t'high; - end if; - end if; - - when s1 => - if cnt /= 0 then - cnt := cnt - 1; - else - ac_reset <= '0'; - end if; - end case; - rstate := rstaten; - end if; - end if; - end process; - - ------------------------------------------------------------------ - -end Behavioral; - diff --git a/lib/ac97_ctrl/src/core/ac_out.vhd b/lib/ac97_ctrl/src/core/ac_out.vhd deleted file mode 100644 index a770495..0000000 --- a/lib/ac97_ctrl/src/core/ac_out.vhd +++ /dev/null @@ -1,276 +0,0 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 15:41:12 06/05/2007 --- Design Name: --- Module Name: ac_out - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity ac_out is - Port ( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned (19 downto 0); - cmd_data : in unsigned (19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned (3 downto 0); - pcm_in_data : in unsigned (19 downto 0); - pcm_in_we : in std_logic; - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); -end ac_out; - -architecture Behavioral of ac_out is - ------------------------------------------------------------------- -COMPONENT singleshot -GENERIC (mode : integer); -PORT( - rst : IN std_logic; - clk : IN std_logic; - input : IN std_logic; - output : OUT std_logic - ); -END COMPONENT; - ------------------------------------------------------------------- -subtype tag_t is UNSIGNED(15 downto 0); -subtype slot_valid_t is UNSIGNED(1 to 12); -signal slot_valid : slot_valid_t; -subtype slot_t is UNSIGNED(19 downto 0); -type slot_array_t is array (natural range <>) of slot_t; -signal data_array : slot_array_t (1 to 12); - signal tx_reg : UNSIGNED(19 downto 0); -signal last_slot, ssync : STD_LOGIC; - -type sac_t is (ac_idle, ac_tag, ac_data); -signal sac, snac : sac_t; - -subtype bitcnt_t is integer range 0 to 19; -subtype slotcnt_t is integer range 0 to 12; - -signal bitcnt : bitcnt_t; -signal bitcnt_rst, bitcnt_en : STD_LOGIC; -signal slotcnt : slotcnt_t; -signal slotcnt_rst, slotcnt_en : STD_LOGIC; - -signal slot_start : STD_LOGIC; - ------------------------------------------------------------------- -function CreateTag(slot_valid : slot_valid_t) return tag_t is -variable tag : tag_t := (others => '0'); -begin - tag := (others => '0'); - for i in slot_valid_t'range loop - tag(15-i) := slot_valid(i); - if slot_valid(i) = '1' then - tag(15) := '1'; - end if; - end loop; - tag(0) := '0'; -- ID0 - tag(1) := '0'; -- ID1 - tag(2) := '0'; -- Reserved --- tag(15) := '1'; -- Frame is valid - return tag; - -end CreateTag; - -begin - ------------------------------------------------------------------- -proc_slot_reg: -process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot) -variable slot_id : integer range 0 to 12; -begin - slot_id := to_integer(pcm_in_addr); - if rising_edge(clk) then - if rst = '1' then - for i in data_array'range(1) loop - data_array(i) <= (others => '0'); - end loop; - slot_valid <= (others => '0'); - elsif last_slot = '1' then - slot_valid <= (others => '0'); - else - if cmd_we = '1' then - slot_valid(1) <= '1'; - slot_valid(2) <= '1'; - data_array(1) <= cmd_addr; - data_array(2) <= cmd_data; - end if; - if pcm_in_we = '1' then - if (slot_id > 2) then - data_array(slot_id) <= pcm_in_data; - slot_valid(slot_id) <= '1'; - end if; - end if; - end if; - end if; -end process; - -------------------------------------------------------------- --- proc_slot_count -------------------------------------------------------------- -proc_slot_count: -process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt) -begin - if rising_edge(ac_bit_clk) then - if slotcnt_rst = '1' then - slotcnt <= slotcnt_t'low; - elsif slotcnt_en = '1' then - if slotcnt /= slotcnt_t'high then - slotcnt <= slotcnt + 1; - else - slotcnt <= slotcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- --- proc_bit_count ------------------------------------------------------------------- -proc_bit_count: -process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt) -begin - if rising_edge(ac_bit_clk) then - if bitcnt_rst = '1' then - bitcnt <= bitcnt_t'low; - elsif bitcnt_en = '1' then - if bitcnt /= bitcnt_t'high then - bitcnt <= bitcnt + 1; - else - bitcnt <= bitcnt_t'low; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_fsm: -process (bitcnt, slotcnt, sac) -begin - snac <= sac; - bitcnt_rst <= '0'; - bitcnt_en <= '1'; - slotcnt_rst <= '0'; - slotcnt_en <= '0'; - slot_start <= '0'; - ssync <= '0'; - - if bitcnt = 0 then - slot_start <= '1'; - end if; - - case sac is - - when ac_idle => - bitcnt_rst <= '1'; - slotcnt_rst <= '1'; - snac <= ac_tag; - - when ac_tag => - ssync <= '1'; - if (bitcnt = 15) then - slotcnt_en <= '1'; - bitcnt_rst <= '1'; - snac <= ac_data; - end if; - - when ac_data => - if bitcnt = 19 then - slotcnt_en <= '1'; - if slotcnt = 12 then - slotcnt_rst <= '1'; - snac <= ac_tag; - end if; - end if; - when others => null; - end case; -end process; - -proc_ac_fsm_next: -process (ac_reset, ac_bit_clk, snac) -begin - if ac_reset = '1' then - sac <= ac_idle; - elsif rising_edge(ac_bit_clk) then - sac <= snac; - end if; -end process; - ------------------------------------------------------------------- -proc_tx_shift_reg: -process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array) -begin - - if ac_reset = '1' then - tx_reg <= (others => '0'); - elsif rising_edge(ac_bit_clk) then - last_slot <= '0'; - if slot_start = '1' then - if ssync = '1' then - tx_reg <= CreateTag(slot_valid) & "0000"; - else - if slotcnt /= 0 then - tx_reg <= data_array(slotcnt); - if slotcnt = 12 then - last_slot <= '1'; - end if; - end if; - end if; - else - tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0'; - end if; - end if; -end process; - ------------------------------------------------------------------- -proc_ac_sync_out: -process (ac_reset, ac_bit_clk, ssync, tx_reg) -begin - if ac_reset = '1' then - ac_ssync <= '0'; - ac_sdata_out <= '0'; - elsif rising_edge(ac_bit_clk) then - ac_ssync <= ssync; - ac_sdata_out <= tx_reg(tx_reg'left); - end if; -end process; - ------------------------------------------------------------------- -singleshot_inst1: singleshot -GENERIC MAP ( - mode => 0) -PORT MAP( - rst => rst, - clk => clk, - input => last_slot, - output => sync_tx -); - -end Behavioral; diff --git a/lib/ac97_ctrl/src/tb_ac97_wb.vhd b/lib/ac97_ctrl/src/tb_ac97_wb.vhd deleted file mode 100644 index 7ab47a4..0000000 --- a/lib/ac97_ctrl/src/tb_ac97_wb.vhd +++ /dev/null @@ -1,152 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac97_wb IS -END tb_ac97_wb; - -ARCHITECTURE behavior OF tb_ac97_wb IS - - constant SYS_CLK_PERIOD : time := 10 ns; - CONSTANT BIT_CLK_PERIOD : time := 100 ns; --- constant BIT_CLK_PERIOD : time := 81.38 ns; - - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal INT_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - - SIGNAL ac97_bit_clk : std_logic := '0'; - SIGNAL ac97_reset_n : std_logic; - SIGNAL ac97_sdata_out : std_logic; - SIGNAL ac97_ssync : std_logic; - SIGNAL ac97_sdata_in : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) -uut : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 4 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => CLK_O, - RST_I => RST_O, - CYC_I => CYC_O, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I, - INT_O => INT_I, - - -- AC97 domain - ac97_sdata_in => ac97_sdata_in, - ac97_bit_clk => ac97_bit_clk, - ac97_reset_n => ac97_reset_n, - ac97_sdata_out => ac97_sdata_out, - ac97_ssync => ac97_ssync - ); - - - ac97_sdata_in <= ac97_sdata_out; - -CLK_GEN: process - begin - wait for SYS_CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - - bit_clk_gen : PROCESS - begin - if (ac97_reset_n = '0') then - ac97_bit_clk <= '0'; - wait until ac97_reset_n = '1'; - wait for 150 us; - end if; - wait for BIT_CLK_PERIOD/2; - ac97_bit_clk <= not ac97_bit_clk; - END PROCESS; - -STIMULUS: process - - begin - - wait for 3*SYS_CLK_PERIOD; - RST_O <= '0'; - - wait for 200 us; - wait until rising_edge(CLK_O); - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - DAT_O <= X"0000_0000"; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O); - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - wait until rising_edge(CLK_O); - - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"5555_1000"; - ADDR_O <= X"0000_0800"; - wait until rising_edge(CLK_O); - DAT_O <= X"5555_1001"; - wait until rising_edge(CLK_O); - STB_O <= '0'; - CYC_O <= '0'; - - WAIT; - END PROCESS; -END; diff --git a/lib/ac97_ctrl/src/tb_ac_in.vhd b/lib/ac97_ctrl/src/tb_ac_in.vhd deleted file mode 100644 index 359e79b..0000000 --- a/lib/ac97_ctrl/src/tb_ac_in.vhd +++ /dev/null @@ -1,203 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_in IS -END tb_ac_in; - -ARCHITECTURE behavior OF tb_ac_in IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_in - Port ( - rst : in std_logic; - clk : in std_logic; - sync_frame : out std_logic; - sync_status : out std_logic; - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - pcm_out_addr : in unsigned (3 downto 0); - pcm_out_data : out unsigned (19 downto 0); - ac_reset : in std_logic; - ac_bit_clk : in std_logic; - ac_sdata_in : in std_logic; - ac_ssync : in std_logic - ); - END COMPONENT; - - COMPONENT ac_out - PORT( - rst : in std_logic; - clk : in std_logic; - sync_tx : out std_logic; - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - pcm_in_addr : in unsigned(3 downto 0); - pcm_in_data : in unsigned(19 downto 0); - pcm_in_we : in std_logic; - ac_bit_clk : in std_logic; - ac_reset : in std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL pcm_in_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL pcm_in_addr : unsigned(3 downto 0) := "0011"; - SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL ac_sdata_in : std_logic; - SIGNAL pcm_out_addr : unsigned(3 downto 0) := "0101"; - SIGNAL ac_reset : std_logic := '1'; - - --Outputs - SIGNAL sync_frame : std_logic; - SIGNAL sync_status : std_logic; - SIGNAL sync_tx : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - SIGNAL stat_addr : unsigned(19 downto 0); - SIGNAL stat_data : unsigned(19 downto 0); - SIGNAL stat_valid : std_logic; - SIGNAL pcm_out_data : unsigned(19 downto 0); - SIGNAL pcm_out_valid : std_logic; - SIGNAL pcm_out_avail : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_in PORT MAP( - rst => rst, - clk => clk, - sync_frame => sync_frame, - sync_status => sync_status, - stat_addr => stat_addr, - stat_data => stat_data, - pcm_out_addr => pcm_out_addr, - pcm_out_data => pcm_out_data, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_in => ac_sdata_in, - ac_ssync => ac_ssync - ); - - inst_ac_out: ac_out PORT MAP( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => pcm_in_addr, - pcm_in_data => pcm_in_data, - pcm_in_we => pcm_in_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - ac_sdata_in <= ac_sdata_out; - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : - PROCESS - BEGIN - wait for BIT_CLK_PERIOD; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb_out : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait for 100*SYS_CLK_PERIOD; - ac_reset <= '0'; - - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"12340"; - cmd_addr <= X"8B930"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - pcm_in_we <= '0'; - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - for i in 3 to 12 loop - pcm_in_addr <= to_unsigned(i, 4); - pcm_in_data <= to_unsigned(2048*k + integer(i), 20); - pcm_in_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - pcm_in_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - - tb_in : PROCESS(clk, pcm_out_addr, sync_status) - BEGIN - if rising_edge(clk) then - if sync_status = '1' then - pcm_out_addr <= "0011"; - elsif pcm_out_addr /= "1100" then - pcm_out_addr <= pcm_out_addr + 1; - end if; - end if; - END PROCESS; -END; diff --git a/lib/ac97_ctrl/src/tb_ac_io.vhd b/lib/ac97_ctrl/src/tb_ac_io.vhd deleted file mode 100644 index 6f25c1d..0000000 --- a/lib/ac97_ctrl/src/tb_ac_io.vhd +++ /dev/null @@ -1,186 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_io IS -END tb_ac_io; - -ARCHITECTURE behavior OF tb_ac_io IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_io - Port ( - rst : in std_logic; - clk : in std_logic; - ready : out std_logic; - sync_strobe : out unsigned(0 to 2); - slot_valid : out unsigned(0 to 12); - stat_addr : out unsigned (19 downto 0); - stat_data : out unsigned (19 downto 0); - rx_pcm_addr : in unsigned (3 downto 0); - rx_pcm_data : out unsigned (19 downto 0); - cmd_addr : in unsigned(19 downto 0); - cmd_data : in unsigned(19 downto 0); - cmd_we : in std_logic; - tx_pcm_addr : in unsigned(3 downto 0); - tx_pcm_data : in unsigned(19 downto 0); - tx_pcm_we : in std_logic; - ac_sdata_in : in std_logic; - ac_bit_clk : in std_logic; - ac_reset_n : out std_logic; - ac_sdata_out : out std_logic; - ac_ssync : out std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - CONSTANT BIT_CLK_PERIOD : time := 100 ns; --- constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL acio_ready : std_logic; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL tx_pcm_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL tx_pcm_addr : unsigned(3 downto 0) := "0011"; - SIGNAL tx_pcm_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL ac_sdata_in : std_logic; - SIGNAL rx_pcm_addr : unsigned(3 downto 0) := "0101"; - - --Outputs - SIGNAL slot_valid : unsigned(0 to 12); - SIGNAL sync_strobe : unsigned(0 to 2); - SIGNAL ac_reset_n : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - SIGNAL stat_addr : unsigned(19 downto 0); - SIGNAL stat_data : unsigned(19 downto 0); - SIGNAL rx_pcm_data : unsigned(19 downto 0); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_io PORT MAP( - rst => rst, - clk => clk, - ready => acio_ready, - sync_strobe => sync_strobe, - slot_valid => slot_valid, - stat_addr => stat_addr, - stat_data => stat_data, - rx_pcm_addr => rx_pcm_addr, - rx_pcm_data => rx_pcm_data, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - tx_pcm_addr => tx_pcm_addr, - tx_pcm_data => tx_pcm_data, - tx_pcm_we => tx_pcm_we, - ac_sdata_in => ac_sdata_in, - ac_bit_clk => ac_bit_clk, - ac_reset_n => ac_reset_n, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - ac_sdata_in <= ac_sdata_out; - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : PROCESS - begin - if (ac_reset_n = '0') then - ac_bit_clk <= '0'; - wait until ac_reset_n = '1'; - wait for 150 us; - end if; - wait for BIT_CLK_PERIOD/2; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb_out : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait until (ac_reset_n = '1'); - - wait until rising_edge(clk) and sync_strobe(2) = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"12340"; - cmd_addr <= X"8B930"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - tx_pcm_we <= '0'; - wait until rising_edge(clk) and sync_strobe(2) = '1'; - wait for 10*BIT_CLK_PERIOD; - for i in 3 to 12 loop - tx_pcm_addr <= to_unsigned(i, 4); - tx_pcm_data <= to_unsigned(2048*k + integer(i), 20); - tx_pcm_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - tx_pcm_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - - tb_in : PROCESS(clk, rx_pcm_addr, sync_strobe) - BEGIN - if rising_edge(clk) then - if sync_strobe(1) = '1' then - rx_pcm_addr <= "0011"; - elsif rx_pcm_addr /= "1100" then - rx_pcm_addr <= rx_pcm_addr + 1; - end if; - end if; - END PROCESS; - -END; diff --git a/lib/ac97_ctrl/src/tb_ac_out.vhd b/lib/ac97_ctrl/src/tb_ac_out.vhd deleted file mode 100644 index 6f6cb42..0000000 --- a/lib/ac97_ctrl/src/tb_ac_out.vhd +++ /dev/null @@ -1,149 +0,0 @@ - --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:33:47 06/05/2007 --- Design Name: eval_ac --- Module Name: E:/work/VHDL/eval_ac/tb_eval_ac.vhd --- Project Name: ac_out --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: ac_out --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY tb_ac_out IS -END tb_ac_out; - -ARCHITECTURE behavior OF tb_ac_out IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ac_out - PORT( - rst : IN std_logic; - clk : IN std_logic; - sync_tx : OUT std_logic; - cmd_addr : IN unsigned(19 downto 0); - cmd_data : IN unsigned(19 downto 0); - cmd_we : IN std_logic; - pcm_in_addr : IN unsigned(3 downto 0); - pcm_in_data : IN unsigned(19 downto 0); - pcm_in_we : IN std_logic; - ac_bit_clk : IN std_logic; - ac_reset : in std_logic; - ac_sdata_out : OUT std_logic; - ac_ssync : OUT std_logic - ); - END COMPONENT; - - constant SYS_CLK_PERIOD : time := 10 ns; - constant BIT_CLK_PERIOD : time := 81.38 ns; - - --Inputs - SIGNAL rst : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL ce : std_logic := '0'; - SIGNAL cmd_we : std_logic := '0'; - SIGNAL pcm_in_we : std_logic := '0'; - SIGNAL ac_bit_clk : std_logic := '0'; - SIGNAL cmd_addr : unsigned(19 downto 0) := (others=>'0'); - SIGNAL cmd_data : unsigned(19 downto 0) := (others=>'0'); - SIGNAL pcm_in_addr : unsigned(3 downto 0) := (others=>'0'); - SIGNAL pcm_in_data : unsigned(19 downto 0) := (others=>'0'); - - --Outputs - SIGNAL sync_tx : std_logic; - SIGNAL ac_reset : std_logic; - SIGNAL ac_sdata_out : std_logic; - SIGNAL ac_ssync : std_logic; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: ac_out PORT MAP( - rst => rst, - clk => clk, - sync_tx => sync_tx, - cmd_addr => cmd_addr, - cmd_data => cmd_data, - cmd_we => cmd_we, - pcm_in_addr => pcm_in_addr, - pcm_in_data => pcm_in_data, - pcm_in_we => pcm_in_we, - ac_reset => ac_reset, - ac_bit_clk => ac_bit_clk, - ac_sdata_out => ac_sdata_out, - ac_ssync => ac_ssync - ); - - sys_clk_gen : - PROCESS - BEGIN - wait for SYS_CLK_PERIOD; - clk <= not clk; - END PROCESS; - - bit_clk_gen : - PROCESS - BEGIN - wait for BIT_CLK_PERIOD; - ac_bit_clk <= not ac_bit_clk; - END PROCESS; - - tb : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 100*SYS_CLK_PERIOD; - rst <= '0'; - - wait for 100*SYS_CLK_PERIOD; - ac_reset <= '0'; - - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - cmd_data <= X"aaaa0"; - cmd_addr <= X"1DFC0"; - - wait until rising_edge(clk); - cmd_we <= '1'; - wait until rising_edge(clk); - cmd_we <= '0'; - - for k in 1 to 10 loop - pcm_in_we <= '0'; - wait until rising_edge(clk) and sync_tx = '1'; - wait for 100*SYS_CLK_PERIOD; - for i in 3 to 12 loop - pcm_in_addr <= to_unsigned(i, 4); - pcm_in_data <= to_unsigned(2048*k + integer(i), 20); - pcm_in_we <= '1'; - wait until rising_edge(clk); - end loop; - end loop; - pcm_in_we <= '0'; - - -- Place stimulus here - - wait; -- will wait forever - END PROCESS; - -END; diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m deleted file mode 100644 index ccac021..0000000 --- a/lib/filter/sim/eval_lowpass.m +++ /dev/null @@ -1,37 +0,0 @@ -function eval_filter(N) -omega_lp = 0.15 -omega_hp = 0.05 - -omega_bp_m = 0.02; -bw2_bp = 0.02; - -lp = lowpass(N, omega_lp, 1.0); -coef_lp = hann(N)'.*lp./sum(lp.^2); - -hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1)); -coef_hp = hp./sum(hp.^2).*hann(N)'; - -bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1)); -coef_bp = bp./sum(bp.^2).*hann(N)'; - -abs_lp = 20*log10(abs(fft(coef_lp))); -abs_hp = 20*log10(abs(fft(coef_hp))); -abs_bp = 20*log10(abs(fft(coef_bp))); - -close all; -plot((0:N/2)/N, abs_lp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_hp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_bp(1:N/2+1));grid; - -figure -plot((0:N-1), coef_lp);grid; -figure -plot((0:N-1), coef_hp);grid; -figure -plot((0:N-1), coef_bp);grid; - -mean_lp = mean(coef_lp-mean(coef_lp)) -mean_hp = mean(coef_hp) -mean_bp = mean(coef_bp) diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m deleted file mode 100644 index 292964d..0000000 --- a/lib/filter/sim/lowpass.m +++ /dev/null @@ -1,20 +0,0 @@ -function coef = lowpass(N, omega, scale) - -phi = 0; -dphi = 2*omega; -if (mod(N, 2) == 0) - M = N/2; - for i=0:M-1, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i-1+1) = coef(M+i+1); - end; -else - M = (N-1)/2; - for i=1:M, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i+1) = coef(M+i+1); - end; - coef(M+1) = scale*Sinc(0.0); -end; diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo deleted file mode 100644 index 5260669..0000000 --- a/lib/filter/sim/tb_fir_iterative.fdo +++ /dev/null @@ -1,18 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_iterative.vhd" -vcom -explicit -93 "../src/tb_fir_iterative.vhd" -vsim -t 1ps -lib work tb_fir_iterative -do {tb_fir_iterative.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo deleted file mode 100644 index cb193af..0000000 --- a/lib/filter/sim/tb_fir_iterative.wdo +++ /dev/null @@ -1,144 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {5100000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {42 us} diff --git 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z>$86m_c#mRqr4Y=ZmzcK#Bg;WCJKrU&;{5u2sH~54XhYZyUrI7zc`D-yrGZ+MoJWe zw{SyIZb=SA=AcSdO3)G#ke7)Fy$H$Fm!Cx``hHkbW$Gh{i5q1eNFVTsIak*-__>FI zT#+)VR+4_vt%qO?z@qgvkGvU!;Hn)ne4CvhH8P@m7+Rz17NwM{rzX3+aKxxcs!mhM z@qxGuzM@ZYEy>-o0?Kw`wagB}tMn!+6kKBp=44#$`NsFfhB+UKHN!;*I<@nm1~;CC z&S2jaJ^e%qZ?(f-m{br+k6LC>yN;|_3uwA%+}Wj7KfSCjtui*Rl>r+`n6Z%vq8UoK zfSx%i6yqcGlwyx3kLHWzbyiYjUkju2@TJfu5>T5!xy-(?gbY)qu#_tsL;kZ5l$1-4 F{vU39VMYJ| diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo deleted file mode 100644 index 6bee97f..0000000 --- a/lib/filter/sim/tb_fir_parallel.fdo +++ /dev/null @@ -1,18 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_parallel.vhd" -vcom -explicit -93 "../src/tb_fir_parallel.vhd" -vsim -t 1ps -lib work tb_fir_parallel -do {tb_fir_parallel.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo deleted file mode 100644 index f0e20ce..0000000 --- a/lib/filter/sim/tb_fir_parallel.wdo +++ /dev/null @@ -1,29 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_parallel/clk -add wave -noupdate -format Logic /tb_fir_parallel/srst -add wave -noupdate -format Logic /tb_fir_parallel/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out -add wave -noupdate -format Logic /tb_fir_parallel/out_valid -add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19450000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {25152750 ps} diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m deleted file mode 100644 index 75a542c..0000000 --- a/lib/filter/sim/tb_fir_results.m +++ /dev/null @@ -1,10 +0,0 @@ -% Read data -function tb_fir_results() -fir = TEXTREAD('fir.txt')'; - -N= length(fir); - -% Output -close all; -plot(0:N-1, fir); grid; - diff --git a/lib/filter/sim/tb_fir_semi_parallel.fdo b/lib/filter/sim/tb_fir_semi_parallel.fdo deleted file mode 100644 index 63079c8..0000000 --- a/lib/filter/sim/tb_fir_semi_parallel.fdo +++ /dev/null @@ -1,20 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_sys.vhd" -vcom -explicit -93 "../src/delay_line.vhd" -vcom -explicit -93 "../src/fir_semi_parallel.vhd" -vcom -explicit -93 "../src/tb_fir_semi_parallel.vhd" -vsim -t 1ps -lib work tb_fir_semi_parallel -do {tb_fir_semi_parallel.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/filter/sim/tb_fir_semi_parallel.wdo b/lib/filter/sim/tb_fir_semi_parallel.wdo deleted file mode 100644 index aba8fb1..0000000 --- a/lib/filter/sim/tb_fir_semi_parallel.wdo +++ /dev/null @@ -1,57 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/rst -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/clk -add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/h_in -add wave -noupdate -format Logic /tb_fir_semi_parallel/dout_vld -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_in -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/d_out -add wave -noupdate -format Logic /tb_fir_semi_parallel/rdy -add wave -noupdate -divider {Real out} -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/xi -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_semi_parallel/yo -add wave -noupdate -divider -height 50 -add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/count0 -add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/start -add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/count_array -add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/en_array -add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/ce_array -add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we -add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/x -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/accu_load -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu -add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y -add wave -noupdate -divider {stage 1} -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram -add wave -noupdate -divider {stage 2} -add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {52500 ns} diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo deleted file mode 100644 index e9fefb8..0000000 --- a/lib/filter/sim/tb_fir_stage.fdo +++ /dev/null @@ -1,17 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/tb_fir_stage.vhd" -vsim -t 1ps -lib work tb_fir_stage -do {tb_fir_stage.wdo} -view wave -view structure -view signals -run 2us diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo deleted file mode 100644 index 916de83..0000000 --- a/lib/filter/sim/tb_fir_stage.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_stage/clk -add wave -noupdate -format Logic /tb_fir_stage/srst -add wave -noupdate -divider Input -add wave -noupdate -format Logic /tb_fir_stage/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in -add wave -noupdate -format Literal /tb_fir_stage/xi -add wave -noupdate -divider Output -add wave -noupdate -format Logic /tb_fir_stage/out_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo -add wave -noupdate -divider {Stage signals} -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1655000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {2100 ns} diff --git a/lib/filter/sim/tb_fir_stage_sys.fdo b/lib/filter/sim/tb_fir_stage_sys.fdo deleted file mode 100644 index b2417c3..0000000 --- a/lib/filter/sim/tb_fir_stage_sys.fdo +++ /dev/null @@ -1,17 +0,0 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_sys.vhd" -vcom -explicit -93 "../src/tb_fir_stage_sys.vhd" -vsim -t 1ps -lib work tb_fir_stage_sys -do {tb_fir_stage_sys.wdo} -view wave -view structure -view signals -run 2us diff --git a/lib/filter/sim/tb_fir_stage_sys.wdo b/lib/filter/sim/tb_fir_stage_sys.wdo deleted file mode 100644 index 21e822e..0000000 --- a/lib/filter/sim/tb_fir_stage_sys.wdo +++ /dev/null @@ -1,28 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_stage_sys/clk -add wave -noupdate -divider Input -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in -add wave -noupdate -format Literal /tb_fir_stage_sys/xi -add wave -noupdate -divider Output -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo -add wave -noupdate -divider {Stage signals} -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x -add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1060000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {706931 ps} {1268317 ps} diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd deleted file mode 100644 index a05e317..0000000 --- a/lib/filter/src/delay_line.vhd +++ /dev/null @@ -1,129 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; - -entity delay_line is -Generic -( - nbits : integer := 12; - nbits_frac : integer := 11; - ntaps : integer := 4; - delay_fix : integer := 1 -); -Port -( - rst : in std_logic; - clk : in std_logic; - shift_en : in std_logic; - delay : in natural range 0 to ntaps-1; - din : in sfixed; - dout : out sfixed -); -end delay_line; - -architecture ram_based of delay_line is - - ------------------------------------------------------------------------------- - signal count : natural range 0 to ntaps-1; - signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0); - signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0); - signal ram_w : unsigned(nbits-1 downto 0); - signal ram_r : unsigned(nbits-1 downto 0); - - ------------------------------------------------------------------------------- -begin - - addr_w <= to_unsigned(count, addr_w'length); - addr_r <= addr_w + not to_unsigned(delay, addr_w'length); - - ram_w <= unsigned(din); - dout <= sfixed(ram_r); - -counter: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - count <= 0; - elsif shift_en = '1' then - if count /= ntaps-1 then - count <= count + 1; - else - count <= 0; - end if; - end if; - end if; - end process; - - inst_dpram_1w1r: entity work.dpram_1w1r - GENERIC MAP - ( - addr_width => NextExpBaseTwo(ntaps), - data_width => nbits - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => shift_en, - addr_a => addr_w, - addr_b => addr_r, - din_a => ram_w, - dout_b => ram_r - ); - -end ram_based; - -architecture reg_based of delay_line is - - ------------------------------------------------------------------------------- - subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac)); - type delay_pipe_t is array (ntaps-1 downto 0) of word_t; - type delay_fix_pipe_t is array (delay_fix downto 0) of word_t; - - ------------------------------------------------------------------------------- -begin - -shift_register: - process(clk) - variable delay_pipe : delay_pipe_t; - begin - if rising_edge(clk) then - dout <= delay_pipe(delay); - if shift_en = '1' then - delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din; - end if; - end if; - end process; - -end reg_based; - diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd deleted file mode 100644 index 1359d25..0000000 --- a/lib/filter/src/filter_pkg.vhd +++ /dev/null @@ -1,219 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; - -library work; -use work.fixed_util_pkg.all; - -------------------------------------------------------------------------------- -package filter_pkg is - - function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t; - function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t; - function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t; - function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t; - function Window_Hamming (x : real_array_t) return real_array_t; - function Window_VonHann (x : real_array_t) return real_array_t; - function Window_Blackman (x : real_array_t) return real_array_t; - function Sinc (x : real) return real; - function FilterEnergy (x : real_array_t) return real; - function FilterMean (x : real_array_t) return real; - function FilterScale (x : real_array_t; scale : real) return real_array_t; - function FilterTestCoef (N : positive) return real_array_t; - -end; -- package filter_pkg; - -------------------------------------------------------------------------------- -package body filter_pkg is - - function Prototype_Lowpass (N : positive; omega : real) return real_array_t is - variable res : real_array_t(0 to N-1); - variable M : positive; - variable phi : real := 0.0; - variable dphi : real := pi*omega; - begin - if (N mod 2) = 0 then - M := N/2; - for i in 0 to M-1 loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i-1) := res(M+i); - end loop; - else - M := (N-1)/2; - for i in 1 to M loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i) := res(M+i); - end loop; - res(M) := Sinc(0.0); - end if; - return res; - - end Prototype_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t is - variable lp : real_array_t(0 to N-1); - begin - lp := Prototype_Lowpass(N, omega); - - return Window_VonHann(FilterScale(lp, gain/FilterEnergy(lp))); - - end FilterCoef_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t is - variable lp, res : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := pi; - begin - lp := Prototype_Lowpass(N, 0.5-omega); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp))); - - end FilterCoef_Highpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t is - variable lp, res, mean, sum : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi*omega_m; - begin - lp := Prototype_Lowpass(N, bw2/2.0); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp))); - - end FilterCoef_Bandpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t is - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := 0.0; - end loop; - res(delay) := gain; - - return res; - - end FilterCoef_Delta; - - ------------------------------------------------------------------------------- - function FilterTestCoef (N : positive) return real_array_t is - variable phi : real := 0.0; - variable dphi : real := 1.0/real(N); - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := phi; - phi := phi + dphi; - end loop; - return res; - - end FilterTestCoef; - - ------------------------------------------------------------------------------- - function Window_Hamming (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.54 - 0.46*(cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_Hamming; - - ------------------------------------------------------------------------------- - function Window_VonHann (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := 0.5 * x(i) * (1.0 - (cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_VonHann; - - ------------------------------------------------------------------------------- - function Window_Blackman (x : real_array_t) return real_array_t is - variable res : real_array_t(0 to x'length-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi)); - phi := phi + dphi; - end loop; - return res; - - end Window_Blackman; - - ------------------------------------------------------------------------------- - function Sinc (x : real) return real is - variable res : real := 1.0; - begin - if x /= 0.0 then - res := sin(x)/x; - end if; - - return res; - - end Sinc; - - ------------------------------------------------------------------------------- - function FilterScale (x : real_array_t; scale : real) return real_array_t is - variable res : real_array_t(x'range); - begin - for i in x'range loop - res(i) := scale * x(i); - end loop; - - return res; - - end FilterScale; - - ------------------------------------------------------------------------------- - function FilterEnergy (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i)*x(i); - end loop; - - return res; - - end FilterEnergy; - - ------------------------------------------------------------------------------- - function FilterMean (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i); - end loop; - - return res/real(x'length); - - end FilterMean; - -------------------------------------------------------------------------------- -end; -- package filter_pkg; diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd deleted file mode 100644 index bc1dba5..0000000 --- a/lib/filter/src/fir_iterative.vhd +++ /dev/null @@ -1,323 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_iterative is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - fir_mode : fir_iterative_mode_t := normal; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out natural; - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed -); -end fir_iterative; - -architecture Behavioral of fir_iterative is - -------------------------------------------------------------------------------- - constant fir_stage_mode : fir_stage_mode_t := transposed; - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode); - - subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - type state_t is (init, idle, start, proc, p1, p2, output); - signal s, sn : state_t; - signal x_stage, xo, y_stage : stage_t; - signal stage_en, cnt_en, new_round : std_logic; - - subtype tap_cnt_t is natural range 0 to ntaps-1; - signal htap_cnt : tap_cnt_t; - signal xtap_cnt_w : tap_cnt_t; - signal xtap_cnt_r : tap_cnt_t; - signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic; - subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1; - signal h_addr : tap_range_t; - signal xmem_din, xmem_dout : in_t; - signal xmem_we, y_valid : std_logic; - - type xmem_t is array (0 to ntaps-1) of in_t; - signal xmem : xmem_t; - signal y_out_reg : out_t; - signal y_reg_valid : std_logic; - - ------------------------------------------------------------------------------- -begin - - h_addr_out <= h_addr; - x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate); - - ---------------------------------------- - process (clk) - begin - if rising_edge(clk) then - y_reg_valid <= '0'; - if srst = '1' then - y_out_reg <= to_sfixed(0, y_out_reg); - elsif y_valid = '1' then - y_out_reg <= resize(y_stage, y_out_reg); - y_reg_valid <= '1'; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - y_dout_valid <= '0'; - if srst = '1' then - y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac)); - elsif y_reg_valid = '1' then - y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - y_dout_valid <= '1'; - end if; - end if; - end process; - - ---------------------------------------- - proc_xmem_rw: process (clk) - begin - if rising_edge(clk) then - if xmem_we = '1' then - xmem(xtap_cnt_w) <= xmem_din; - end if; - xmem_dout <= xmem(xtap_cnt_r); - end if; - end process; - - ---------------------------------------- - proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout) - begin - xmem_din <= to_sfixed(0, xmem_din); - if new_round = '1' and clr_xmem = '0' then - xmem_din <= sfixed(x_din); - end if; - end process; - - ---------------------------------------- - proc_xmem_pointer: process(clk, new_round ,clr_xmem) - begin - xmem_we <= clr_xmem or new_round; - if rising_edge(clk) then - if srst = '1' then - xtap_cnt_w <= tap_cnt_t'high; - elsif xmem_we = '1' then - if xtap_cnt_w /= tap_cnt_t'low then - xtap_cnt_w <= xtap_cnt_w - 1; - else - xtap_cnt_w <= tap_cnt_t'high; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_h_addr: process(htap_cnt) - begin - if fir_mode = symmetric then - if ntaps_is_even then - if htap_cnt > ntaps/2-1 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - else - if htap_cnt > (ntaps-1)/2 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - end if; - else - h_addr <= htap_cnt; - end if; - end process; - - ---------------------------------------- - proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en) - begin - if rising_edge(clk) then - if cnt_reset = '1' then - htap_cnt <= tap_cnt_t'low; - xtap_cnt_r <= xtap_cnt_w; - elsif cnt_en = '1' then - if htap_cnt /= tap_cnt_t'high then - htap_cnt <= htap_cnt + 1; - else - htap_cnt <= tap_cnt_t'low; - end if; - if xtap_cnt_r /= tap_cnt_t'high then - xtap_cnt_r <= xtap_cnt_r + 1; - else - xtap_cnt_r <= tap_cnt_t'low; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_valid_out: process(srst, clk, valid, new_round) - variable val_pipe : unsigned(4 downto 0); - variable ctrl_pipe : unsigned(2 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - ctrl_pipe := (others => '0'); - fir_stage_en <= '0'; - fir_stage_clr <= '0'; - else - ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round; - fir_stage_en <= stage_en; - fir_stage_clr <= ctrl_pipe(2); - end if; - end if; - cnt_reset <= new_round; - end process; - - ---------------------------------------- - proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w) - begin - clr_xmem <= '0'; - new_round <= '0'; - cnt_en <= '0'; - ready <= '0'; - valid <= '0'; - sn <= s; - stage_en <= '0'; - y_valid <= '0'; - - case s is - when init => - clr_xmem <= '1'; - if xtap_cnt_w = tap_cnt_t'low then - sn <= idle; - end if; - - when idle => - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when start => - new_round <= '1'; - sn <= proc; - - when proc => - stage_en <= '1'; - cnt_en <= '1'; - if htap_cnt = tap_cnt_t'high then - sn <= p1; - end if; - - when p1 => - sn <= p2; - - when p2 => - sn <= output; - ready <= '1'; - - when output => - sn <= idle; - y_valid <= '1'; - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when others => null; - end case; - end process; - - proc_fsm_next: process(srst, clk, sn) - begin - if rising_edge(clk) then - if srst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - ---------------------------------------- - inst_fir_stage: entity work.fir_stage_sys - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - input_latency => 1, - coef_latency => 1, - pipe_latency => 3 - ) - PORT MAP - ( - rst => fir_stage_clr, - clk => clk, - x_in => x_stage, - y_in => y_stage, - h_in => h_din, - x_out => xo, - y_out => y_stage - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd deleted file mode 100644 index af8bb68..0000000 --- a/lib/filter/src/fir_iterative_pkg.vhd +++ /dev/null @@ -1,52 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use ieee.numeric_std.all; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_iterative_pkg is - - type fir_iterative_mode_t is (normal, symmetric); - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer; - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- -package body fir_iterative_pkg is - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is - variable res : integer; - begin - res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode)))); - return res; - end taps_nbits; - - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - variable res : integer := ntaps; - begin - if mode = symmetric then - if ntaps_is_even then - res := ntaps/2; - else - res := (ntaps-1)/2 + 1; - end if; - end if; - return res; - end ntaps_addr; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd deleted file mode 100644 index 2561848..0000000 --- a/lib/filter/src/fir_parallel.vhd +++ /dev/null @@ -1,218 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_parallel is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed -); -end fir_parallel; - -architecture Behavioral of fir_parallel is - -------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - type coeff_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - type stages_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - constant fir_stage_mode : fir_stage_mode_t := transposed; - - SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - - SIGNAL x : stages_array_t(0 to ntaps-2); - SIGNAL y : stages_array_t(0 to ntaps-2); - SIGNAL h : coeff_array_t(0 to ntaps-1); - - ------------------------------------------------------------------------------- -begin - - -- Assign coefficients - assign_coeffs: - for i in 0 to ntaps-1 generate - h(i) <= to_sfixed(h_in, i); - end generate; - - ---------------------------------------- - -- Instantiate the FIR stages - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => d_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0), - y_out_clr => '0' - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i), - y_out_clr => '0' - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => d_out, - y_out_clr => '0' - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd deleted file mode 100644 index 9243d8c..0000000 --- a/lib/filter/src/fir_parallel_pkg.vhd +++ /dev/null @@ -1,29 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; -use work.fir_stage_pkg.all; - -------------------------------------------------------------------------------- -package fir_parallel_pkg is - - type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym); - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- -package body fir_parallel_pkg is - - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_pkg.vhd b/lib/filter/src/fir_pkg.vhd deleted file mode 100644 index 9e904b5..0000000 --- a/lib/filter/src/fir_pkg.vhd +++ /dev/null @@ -1,54 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use ieee.numeric_std.all; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_pkg is - - type fir_stage_mode_t is (transposed, systolic); - type fir_iterative_mode_t is (normal, symmetric); - type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym); - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer; - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer; - -end; -- package fir_pkg; - -------------------------------------------------------------------------------- -package body fir_pkg is - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is - variable res : integer; - begin - res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode)))); - return res; - end taps_nbits; - - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - variable res : integer := ntaps; - begin - if mode = symmetric then - if ntaps_is_even then - res := ntaps/2; - else - res := (ntaps-1)/2 + 1; - end if; - end if; - return res; - end ntaps_addr; - -end; -- package fir_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd deleted file mode 100644 index 68493c1..0000000 --- a/lib/filter/src/fir_semi_parallel.vhd +++ /dev/null @@ -1,300 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_semi_parallel is -Generic -( - ntaps_per_stage : integer := 32; - nstages : integer := 2; - pipe_latency : integer := 4; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11 -); -Port -( - rst : in std_logic; - clk : in std_logic; - h_addr : in natural range 0 to nstages*ntaps_per_stage-1; - h_we : in std_logic; - h_in : in sfixed; - din_vld : in std_logic; - din : in sfixed; - dout_vld : out std_logic; - start : in std_logic; - rdy : out std_logic; - dout : out sfixed -); -end fir_semi_parallel; - -architecture Behavioral of fir_semi_parallel is - - ------------------------------------------------------------------------------- - constant coef_addr_nbits : natural := NextExpBaseTwo(ntaps_per_stage) + NextExpBaseTwo(nstages); - - subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - subtype count_t is natural range 0 to ntaps_per_stage-1; - type count_array_t is array (nstages-1 downto 0) of count_t; - - subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - type stage_array_t is array (0 to nstages) of stage_t; - - signal count_array : count_array_t; - signal count0 : count_t; - signal ce_array : unsigned(nstages downto 0); - signal en_array : unsigned(nstages downto 0); - signal coef_addr : unsigned(coef_addr_nbits-1 downto 0); - - SIGNAL x : stage_array_t; - SIGNAL xo : stage_array_t; - SIGNAL y : stage_array_t; - SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - SIGNAL act : std_logic := '0'; - SIGNAL start_r : std_logic := '0'; - signal accu_load : std_logic; - signal accu_ld_pipe : unsigned(nstages+pipe_latency-1 downto 0); - - signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - signal coef_we : unsigned(nstages-1 downto 0); - - type coef_array_t is array (0 to nstages-1) of unsigned(nbits_stages-1 downto 0); - signal coef_din : unsigned(nbits_stages-1 downto 0); - signal coef_dout : coef_array_t; - - ------------------------------------------------------------------------------- -begin - - assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure; - assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure; - - x(0) <= resize(din_r, x(0)); - y(0) <= to_sfixed(0.0, y(0)); - - accu_load <= accu_ld_pipe(accu_ld_pipe'left); - start_r <= act and ce_array(ce_array'left) and not ce_array(ce_array'left-1); - -din_register: - process(clk) - begin - if rising_edge(clk) then - if din_vld = '1' then - din_r <= din; - end if; - end if; - end process; - -accu_load_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - accu_ld_pipe <= (others => '0'); - else - accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & start_r; - end if; - end if; - end process; - -coef_we_gen: - process(clk) - variable i : natural range 0 to nstages-1; - variable caddr : unsigned(coef_addr_nbits-1 downto 0); - variable saddr : unsigned(NextExpBaseTwo(nstages)-1 downto 0); - begin - if rising_edge(clk) then - caddr := to_unsigned(h_addr, coef_addr_nbits); - saddr := caddr(caddr'left downto NextExpBaseTwo(ntaps_per_stage)); - i := to_integer(saddr); - coef_we <= (others => '0'); - coef_we(i) <= '1'; - coef_din <= unsigned(h_in); - coef_addr <= caddr; - end if; - end process; - -rdy_logic: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - rdy <= '1'; - act <= '0'; - elsif start = '1' then - rdy <= '0'; - act <= '1'; - elsif count0 = count_t'high-2 then - rdy <= '1'; - act <= '0'; - end if; - end if; - end process; - -counter: - process(clk) - variable cnt : count_t; - variable enable : std_logic; - begin - if rising_edge(clk) then - if rst = '1' then - cnt := count_t'high; - elsif cnt /= count_t'high then - cnt := cnt + 1; - else - enable := '0'; - if start_r = '1' then - enable := '1'; - cnt := 0; - end if; - end if; - count0 <= cnt; - count_array <= count_array(count_array'left-1 downto 0) & cnt; - en_array <= en_array(en_array'left-1 downto 0) & enable; - end if; - end process; - -ce_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - ce_array <= (others => '0'); - else - ce_array <= ce_array(ce_array'left-1 downto 0) & din_vld; - end if; - end if; - end process; - -gen_coef_ram: - for i in 0 to nstages-1 generate - signal addr_a : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0); - signal addr_b : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0); - begin - addr_a <= coef_addr(addr_a'length-1 downto 0); - addr_b <= to_unsigned(count_array(i), addr_b'length); - inst_coef_ram: entity work.dpram_1w1r - GENERIC MAP - ( - addr_width => NextExpBaseTwo(ntaps_per_stage), - data_width => nbits_stages - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => coef_we(i), - addr_a => addr_a, - addr_b => addr_b, - din_a => coef_din, - dout_b => coef_dout(i) - ); - end generate; - - -gen_stages: - for i in 0 to nstages-1 generate - signal h_in : coef_t; - begin - h_in <= sfixed(coef_dout(i)); - inst_fir_stage: entity work.fir_stage_sys - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - pipe_latency => pipe_latency - ) - PORT MAP - ( - clk => clk, - ce => en_array(i), - x_in => x(i+1), - y_in => y(i), - h_in => h_in, - x_out => xo(i+1), - y_out => y(i+1) - ); - end generate; - - -gen_delays: - for i in 0 to nstages-1 generate - begin - inst_delay_line : entity work.delay_line(ram_based) - GENERIC MAP - ( - nbits => nbits_stages, - nbits_frac => nbits_stages_frac, - ntaps => ntaps_per_stage, - delay_fix => 0 - ) - PORT MAP - ( - rst => rst, - clk => clk, - shift_en => ce_array(i), - delay => count_array(i), - din => x(i), - dout => x(i+1) - ); - end generate; - -acumulator: - process(clk) - begin - if rising_edge(clk) then - dout_vld <= accu_load; - if rst = '1' then - dout_vld <= '0'; - elsif en_array(en_array'left) = '1' then - if accu_load = '1' then - dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); - accu <= y(nstages); - else - accu <= resize(accu + y(nstages), accu); - end if; - end if; - end if; - end process; - - -end Behavioral; diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd deleted file mode 100644 index a519cf4..0000000 --- a/lib/filter/src/fir_stage.vhd +++ /dev/null @@ -1,157 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_stage is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic -); -end fir_stage; - -architecture Behavioral of fir_stage is - -signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); -signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); -signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); -signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg_y: process(clk) - begin - if rising_edge(clk) then - if srst = '1' or y_out_clr = '1' then - yin <= to_sfixed(0, yin); - else - yin <= resize(y_in, yin); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in) - variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - xin <= to_sfixed(0, xin); - hin <= to_sfixed(0, hin); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - end if; - end if; - end if; - else - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - valid <= in_valid; - end if; - x_out <= resize(x_in, p); - - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, xin, hin) - variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - begin - p := resize(xin * hin, p); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - prod <= to_sfixed(0, prod); - p_valid <= '0'; - else - prod <= p; - p_valid <= valid; - end if; - end if; - else - prod <= p; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, prod, yin) - variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - begin - yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); --- if rising_edge(clk) then --- if srst = '1' or y_out_clr = '1' then --- y_out <= to_sfixed(0, yout); --- out_valid <= '0'; --- else --- y_out <= yout; --- out_valid <= p_valid; --- end if; --- end if; - out_valid <= p_valid; - y_out <= yout; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd deleted file mode 100644 index c6408b8..0000000 --- a/lib/filter/src/fir_stage_pkg.vhd +++ /dev/null @@ -1,18 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -package fir_stage_pkg is - -type fir_stage_mode_t is (transposed, systolic); - -end; -- package fir_stage_pkg; - -package body fir_stage_pkg is - -end; -- package fir_stage_pkg; diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd deleted file mode 100644 index af0f74a..0000000 --- a/lib/filter/src/fir_stage_sys.vhd +++ /dev/null @@ -1,109 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_stage_sys is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - pipe_latency : integer := 4 -); -Port -( - clk : in std_logic; - ce : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - x_out : out sfixed; - y_out : out sfixed -); -end fir_stage_sys; - -architecture Behavioral of fir_stage_sys is - -constant min_pipe_lat : integer := 4; - -subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); -subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - -type input_pipe_t is array (pipe_latency-2 downto 0) of in_t; -type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t; - -signal yin : in_t; -signal prod : out_t; - ------------------------------------------------------------- -begin - - assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure; - - yin <= resize(y_in, yin); - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable h_pipe : coef_pipe_t; - variable x_pipe : input_pipe_t; - begin - if rising_edge(clk) then - if ce = '1' then - x_pipe := x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0)); - h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0)); - prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(clk) - variable yout : out_t; - variable xout : in_t; - begin - if rising_edge(clk) then - if ce = '1' then - yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate); - y_out <= yout; - xout := resize(x_in, xout, fixed_wrap, fixed_truncate); - x_out <= xout; - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd deleted file mode 100644 index 76b6024..0000000 --- a/lib/filter/src/tb_fir_iterative.vhd +++ /dev/null @@ -1,234 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; -use work.fir_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_iterative IS - Generic ( - ntaps : integer := 11; - nbits_in : integer := 15; - nbits_in_frac : integer := 15; - nbits_stages : integer := 15; - nbits_stages_frac : integer := 15; - nbits_out : integer := 15; - nbits_out_frac : integer := 15; - fir_mode : fir_iterative_mode_t := symmetric; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_iterative; - -ARCHITECTURE behavior OF tb_fir_iterative IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_iterative - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - fir_mode : fir_iterative_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out natural; - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant nsamples : integer := 32; - - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL x_valid : std_logic := '0'; - SIGNAL h_din : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - SIGNAL x_din : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL y_dout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL y_valid : std_logic; - SIGNAL ready : std_logic; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients --- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1); - SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); --- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps); - signal x_input : real_array_t(0 to nsamples-1) := - ( - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.9999, - -0.0000, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0 - - ); - type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - signal ymem : ymem_t; - - signal y_cnt : integer ; - SIGNAL xi, yo : real := 0.0; - SIGNAL h_addr : natural; - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_din); - yo <= to_real(y_dout); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_iterative: fir_iterative - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_din => h_din, - h_addr_out => h_addr, - ready => ready, - x_valid => x_valid, - x_din => x_din, - y_dout_valid => y_valid, - y_dout => y_dout - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - for i in 0 to nsamples-1 loop - if i = nsamples/2 then - wait for 43*PERIOD; - end if; - ------------------------------------------ - wait until rising_edge(clk) and ready = '1'; - x_din <= to_sfixed(x_input(i), x_din); - x_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_valid <= '0'; - end loop; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - process(srst, clk, y_valid) - begin - if rising_edge(clk) then - h_din <= to_sfixed(coeffs(h_addr), h_din); - if srst = '1' then - y_cnt <= 0; - - elsif y_valid = '1' then - ymem(y_cnt) <= y_dout; - y_cnt <= y_cnt + 1; - end if; - end if; - end process; - -END; diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd deleted file mode 100644 index e1ff939..0000000 --- a/lib/filter/src/tb_fir_parallel.vhd +++ /dev/null @@ -1,193 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; -use work.fir_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_parallel IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 16; - nbits_in_frac : integer := 16; - nbits_stages : integer := 16; - nbits_stages_frac : integer := 15; - nbits_out : integer := 16; - nbits_out_frac : integer := 16; - has_in_reg : boolean := false; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_parallel; - -ARCHITECTURE behavior OF tb_fir_parallel IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_parallel - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_parallel_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac); - - SIGNAL xi, yo : real := 0.0; - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_parallel: fir_parallel - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_in => coeff_in, - in_valid => in_valid, - d_in => x_in, - out_valid => out_valid, - d_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file fi : file_t open read_mode is "wav_in.dat"; - variable si : sample_t; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - while not endfile(fi) loop - read(fi, si); - x_in <= to_sfixed(to_signed(si, x_in'length)); - in_valid <= '1'; - wait for PERIOD; - wait until rising_edge(clk); - end loop; - ------------------------------------------ - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file fo : file_t open write_mode is "wav_out.dat"; - variable so : sample_t; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - so := to_integer(y_out); - write(fo, so); - end if; - - END PROCESS; - -END; diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd deleted file mode 100644 index 33da80f..0000000 --- a/lib/filter/src/tb_fir_semi_parallel.vhd +++ /dev/null @@ -1,289 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; -use work.fir_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_semi_parallel IS - Generic - ( - ntaps_per_stage : integer := 32; - nstages : integer := 2; - nbits_in : integer := 32; - nbits_in_frac : integer := 30; - nbits_stages : integer := 32; - nbits_stages_frac : integer := 30; - nbits_out : integer := 32; - nbits_out_frac : integer := 30 - ); -END tb_fir_semi_parallel; - -ARCHITECTURE behavior OF tb_fir_semi_parallel IS - - ------------------------------------------------------------------------------- - --Constants - constant PERIOD : time := 10 ns; - constant nsamples : integer := 32; - constant M : integer := 1; - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL rst : std_logic := '1'; - SIGNAL din_vld : std_logic := '0'; - SIGNAL d_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - signal h_addr : natural := 0; - SIGNAL h_we : std_logic := '0'; - SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - SIGNAL start : std_logic := '0'; - - --Outputs - SIGNAL d_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL dout_vld : std_logic; - SIGNAL rdy : std_logic; - - SIGNAL fileout_enable : std_logic := '1'; - - - SIGNAL xi, yo : real := 0.0; - - CONSTANT ntaps : natural := nstages*ntaps_per_stage; - type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is - variable res : h_mem_t; - begin - for i in 0 to ntaps-1 loop - res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round); - end loop; - - return res; - end to_h_mem; - - CONSTANT coeffs : real_array_t(0 to ntaps-1) := FilterCoef_Lowpass(ntaps, 0.1, 4.0); - CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps, h_in); - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - signal x_input : real_array_t(0 to nsamples-1) := - ( - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 1.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0 - - ); - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(d_in); - yo <= to_real(d_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut : entity work.fir_semi_parallel - GENERIC MAP - ( - ntaps_per_stage => ntaps_per_stage, - nstages => nstages, - pipe_latency => 5, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac - ) - PORT MAP - ( - rst => rst, - clk => clk, - h_addr => h_addr, - h_we => h_we, - h_in => h_in, - din_vld => din_vld, - din => d_in, - dout_vld => dout_vld, - rdy => rdy, - start => start, - dout => d_out - ); - - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file fi : file_t open read_mode is "wav_in.dat"; - variable si : sample_t; - variable remain : integer; - variable j : integer; - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - rst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - -- write coeffs - for i in 0 to ntaps-1 loop - wait until rising_edge(clk); - h_addr <= i; - h_in <= h_mem(i); - h_we <= '1'; - end loop; - wait until rising_edge(clk); --- h_addr <= 0; --- h_in <= to_sfixed(0.25, h_in); --- h_we <= '1'; --- wait until rising_edge(clk); - h_we <= '0'; - - -- Write zeros - remain := ntaps_per_stage*nstages; - j := 0; - while remain /= 0 loop - wait until rising_edge(clk) and rdy = '1'; - for i in 0 to M-1 loop - d_in <= to_sfixed(0.0, d_in); - din_vld <= '1'; - j := j + 1; - remain := remain - 1; - wait until rising_edge(clk); - end loop; - din_vld <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - end loop; - - ------------------------------------------ - -- Write data - remain := nsamples; - j := 0; - while remain /= 0 loop - wait until rising_edge(clk) and rdy = '1'; - for i in 0 to M-1 loop - d_in <= to_sfixed(x_input(j), d_in); - din_vld <= '1'; - j := j + 1; - remain := remain - 1; - wait until rising_edge(clk); - end loop; - din_vld <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - end loop; - - -- Write zeros - remain := 100; - j := 0; - while remain /= 0 loop - wait until rising_edge(clk) and rdy = '1'; - for i in 0 to M-1 loop - d_in <= to_sfixed(0.0, d_in); - din_vld <= '1'; - j := j + 1; - remain := remain - 1; - wait until rising_edge(clk); - end loop; - din_vld <= '0'; --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); --- wait until rising_edge(clk); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - end loop; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable) - file fo : file_t open write_mode is "wav_out.dat"; - variable so : sample_t; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' then - if dout_vld = '1' then - so := to_integer(d_out); - write(fo, so); - end if; - end if; - - END PROCESS; - -END; diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd deleted file mode 100644 index 04bb03f..0000000 --- a/lib/filter/src/tb_fir_stage.vhd +++ /dev/null @@ -1,276 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_stage IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 24; - nbits_in_frac : integer := 23; - nbits_stages : integer := 25; - nbits_stages_frac : integer := 23; - nbits_out : integer := 24; - nbits_out_frac : integer := 22; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_stage; - -ARCHITECTURE behavior OF tb_fir_stage IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic - ); - END COMPONENT; - - type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL x : stages_t(0 to ntaps-2); - SIGNAL y : stages_t(0 to ntaps-2); - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - function to_sfixed(x_real : real_array_t) return stages_t is - variable res : stages_t(x_real'range); - begin - for i in x_real'range loop - res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round); - end loop; - - return res; - end to_sfixed; - - constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); - - SIGNAL xi, yo : real := 0.0; - -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - y_out_clr => '0', - clk => clk, - in_valid => in_valid, - x_in => x_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - y_out_clr => '0', - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - y_out_clr => '0', - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - x_in <= to_sfixed(0.0, x_in); - - wait until rising_edge(clk); - in_valid <= '1'; - - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 20*PERIOD; - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(1.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 150*PERIOD; - - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_FIR: text open write_mode is "fir.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_FIR, L,"%s\n", REAL'image(yo)); - end if; - - END PROCESS; - -END; diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd deleted file mode 100644 index b0afe32..0000000 --- a/lib/filter/src/tb_fir_stage_sys.vhd +++ /dev/null @@ -1,230 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.fir_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_stage_sys IS - Generic - ( - ntaps : integer := 33; - nbits_in : integer := 24; - nbits_in_frac : integer := 23; - nbits_stages : integer := 25; - nbits_stages_frac : integer := 23; - nbits_out : integer := 24; - nbits_out_frac : integer := 22 - ); -END tb_fir_stage_sys; - -ARCHITECTURE behavior OF tb_fir_stage_sys IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_stage_sys - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - input_latency : integer; - coef_latency : integer; - pipe_latency : integer - ); - PORT - ( - clk : in std_logic; - ce : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - x_out : out sfixed; - y_out : out sfixed - ); - END COMPONENT; - - type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); - - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL ce : std_logic := '1'; - SIGNAL clk : std_logic := '0'; - SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - - SIGNAL x : stages_t(0 to ntaps-2); - SIGNAL y : stages_t(0 to ntaps-2); - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - function to_sfixed(x_real : real_array_t) return stages_t is - variable res : stages_t(x_real'range); - begin - for i in x_real'range loop - res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round); - end loop; - - return res; - end to_sfixed; - - constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); - - SIGNAL xi, yo : real := 0.0; - -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_first_stage_sys: fir_stage_sys - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - input_latency => 1, - coef_latency => 1, - pipe_latency => 2 - ) - PORT MAP - ( - clk => clk, - ce => ce, - x_in => x_in, - y_in => zero_in, - h_in => h(ntaps-1), - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage_sys - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - input_latency => 2, - coef_latency => 1, - pipe_latency => 2 - ) - PORT MAP - ( - clk => clk, - ce => ce, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage_sys - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - input_latency => 2, - coef_latency => 1, - pipe_latency => 2 - ) - PORT MAP - ( - clk => clk, - ce => ce, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - x_out => x_out, - y_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - x_in <= to_sfixed(0.0, x_in); - - wait for 40*PERIOD; - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(1.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 150*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable) - file RESULT_FIR: text open write_mode is "fir.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' then - fprint(RESULT_FIR, L,"%s\n", REAL'image(yo)); - end if; - - END PROCESS; - -END; diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd deleted file mode 100644 index 6397ebc..0000000 --- a/lib/fix_std/fix_std.vhd +++ /dev/null @@ -1,1007 +0,0 @@ ---------------------------------------------------------------------- --- --- Package fix_std --- Fixed point arithmetic based on numeric_std --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package fix_std is - - -------------------------------------------------------------------- - - -- Integer subtype specifying legal values for a bit index. - -- At present it's restricted to 'natural' to conform with - -- the behaviour of mainstream synthesis tools. For simulation, - -- or in the future when synthesis tools are able to cope, it - -- would be possible to change this subtype to be the full - -- integer range, thus allowing negative subscripts for - -- fraction bits. - -- - subtype Fix_Subscr is natural; - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - constant FixP: Fix_Subscr := 100; - - -- Type declarations for the basic unsigned and signed fixed point - -- data types: - -- - type UFix is array (Fix_Subscr range <>) of std_logic; - type SFix is array (Fix_Subscr range <>) of std_logic; - - -- Type declarations for control of rounding and overflow modes: - -- - type Fix_Rounding_Mode is ( - clip_LS, -- Throw away unwanted least significant bits - towards_zero, -- Round towards zero - same as clip_LS for UFix - to_nearest -- Round to nearest. Exact halves round up. - ); - type Fix_Overflow_Mode is ( - clip_MS, -- Throw away unwanted most significant bits - saturate -- Saturate overflow to nearest representable value - ); - - -- Defaults for these modes: - -- - constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - - --------------------------- - -- E. Extraction functions - --------------------------- - - -- E.1. Return the integral part of a UFix value - function Int(U: UFix) return UFix; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - -- - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - - -- T.9 to T.16: Signed conversions - -- - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix; - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - -- - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - -- - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.6 to V.10: Copy an expression into a SFix variable - -- - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix; - - -- A.4.4. UFix := UFix - natural - function "-" (L: UFix; R: natural) return UFix; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix; - - -- No need to define "&"[UFix, SFix] explicitly, because - -- the types are incompatible and so there's no default - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix; - - -end; -- package fix_std; diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd deleted file mode 100644 index 695cd11..0000000 --- a/lib/fix_std/fix_stdb.vhd +++ /dev/null @@ -1,1910 +0,0 @@ ---------------------------------------------------------------------- --- --- Package body fix_std --- Fixed point arithmetic based on numeric_std --- Compile using VHDL-93 (required to support 'ASCENDING --- array attribute). --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code --- * Fixed definition of extract functions to return just one bit --- if their results would otherwise be null ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package body fix_std is - - -------------------------------------------------------------------- - -- DEFERRED CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - -- constant FixP : Fix_Subscr := 100; - - -- Default values for overflow and rounding modes: - -- - -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - -- END OF DEFERRED CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Severity levels for various errors - - -- Concatenation errors - bad sign extension, discontiguous range etc - -- These are only warnings - they just give the wrong answer. - -- - constant concat_severity : severity_level := WARNING; - - -- Subtype direction errors - the present implementation can't - -- handle fixed-point objects with ascending ranges. These messages - -- are intended to give early warning of problems that would - -- definitely cause other fatal errors at elaboration or run time. - -- - constant direction_severity : severity_level := FAILURE; - - -- Assertion error message constants - - constant bad_direction_msg : string := - " has ascending range"; - - constant concat_range_msg : string := - "Concatenation bounds should have contiguous ranges"; - - constant concat_sxt_msg : string := - "Concatenation corrupts sign of result"; - - constant concat_signLS_msg : string := - "RHS of concatenation should be unsigned"; - - constant compare_meta_msg : string := - "Metavalue detected in FIX_STD comparison, returning FALSE"; - - -------------------------------------------------------------------- - -- END OF IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- DO NOT MODIFY ANY CODE BELOW THIS POINT. - -------------------------------------------------------------------- - - -- Assumed bit width of INTEGER type in VHDL - -- - constant INT_WIDTH : positive := 32; - - -- Single-bit zero values - subtype Izero_UFixT is UFix(FixP downto FixP); - subtype Izero_SFixT is SFix(FixP downto FixP); - subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1); - constant Izero_UFix: Izero_UFixT := "0"; - constant Izero_SFix: Izero_SFixT := "0"; - constant Fzero_UFix: Fzero_UFixT := "0"; - - -------------------------------------------------------------------- - -- LOCAL PRIVATE SUBPROGRAMS - -------------------------------------------------------------------- - - -- Min, Max: Find minimum and maximum of two integers. - -- Useful for determining appropriate range for operation results. - -- - function Max(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L>R then - return L; - else - return R; - end if; - end; - -- - function Min(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L FixP then - return Span(U); - else - return U(U'LEFT downto FixP); - end if; - end; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix is - begin - if U'LEFT < FixP-1 then - return Span(U); - elsif U'RIGHT >= FixP then - return Fzero_UFix; - else - return U(FixP-1 downto U'RIGHT); - end if; - end; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix is - begin - if S'LENGTH = 0 then - return Izero_SFix; - elsif S'LEFT <= FixP then - return SFix'(FixP => S(S'LEFT)); - elsif S'RIGHT > FixP then - return Span(S); - else - return S(S'LEFT downto FixP); - end if; - end; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix is - variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - if S'LEFT < FixP then - for I in FixP-1 downto S'LEFT+1 loop - P(I) := S(S'LEFT); - end loop; - P(S'RANGE) := S; - return UFix(S(FixP-1 downto S'RIGHT)); - elsif S'RIGHT >= FixP then - return Fzero_UFix; - else - return UFix(S(FixP-1 downto S'RIGHT)); - end if; - end; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix is - variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - F(S'RANGE) := S; - for I in F'LEFT downto S'LEFT+1 loop - F(I) := S(S'LEFT); - end loop; - for I in S'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix is - variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP)); - begin - F(U'RANGE) := U; - for I in F'LEFT downto U'LEFT+1 loop - F(I) := '0'; - end loop; - for I in U'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix is - variable F: UFix(FixP+N'LENGTH-1 downto FixP); - begin - F := UFix(N); - return F; - end; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(N'LEFT downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, rounding=>rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(FixP+bits-1 downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, overflow, rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP); - begin - Copy_V(F_UFix, N, overflow, rounding); - return to_integer(unsigned(F_UFix)); - end; - - -- T.9 to T.16: Signed conversions - - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix is - variable F: SFix(FixP+N'LENGTH-1 downto FixP); - begin - F := SFix(N); - return F; - end; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: SFix(N'LEFT downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, rounding=>rounding); - F := signed(F_SFix); - return F; - end; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: UFix(FixP+bits-1 downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, overflow, rounding); - F := signed(F_SFix); - return F; - end; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP); - begin - Copy_V(F_SFix, N, overflow, rounding); - return to_integer(signed(F_SFix)); - end; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix is - variable F: SFix(U'LEFT+1 downto U'RIGHT); - begin - F := SFix('0' & U); - return F; - end; - - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is UFix(target'RANGE); - variable W: UFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - W(source'RANGE) := source; - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS | towards_zero => - null; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := UFix( - unsigned(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - target := W(target'RANGE); - if HighZero'LENGTH > 0 then - if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then - case overflow is - when clip_MS => - null; - when saturate => - target := target_T'(others => '1'); - end case; - end if; - end if; - end; - - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT); - constant target_zero: UFix(target'RANGE) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - -- Rounding & sign-extend - Copy_V(W, source, clip_MS, rounding); - -- Saturation? - if W < 0 and overflow = saturate then - target := target_zero; - else - Copy_V(target, UFix(W), overflow, clip_LS); - end if; - end; - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source); - begin - Copy_V(target, U, overflow, rounding); - end; - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - -- V.6 to V.10: Copy an expression into a SFix variable - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is SFix(target'RANGE); - variable W: SFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - variable HighSX: SFix(W'LEFT downto target'LEFT+1); - begin - for i in HighSX'RANGE loop - HighSX(i) := source(source'LEFT); - end loop; - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - -- Make W a copy of source, duly extended at both ends - W := (others => '0'); - W(source'RANGE) := source; - W(HighSX'RANGE) := HighSX; - -- Do any rounding required - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS => - null; - when towards_zero => - if - (to_UX01(W(W'LEFT)) = '1') -- it's negative? - and - (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up? - then - W(W'LEFT downto target'RIGHT) := SFix( - signed(W(W'LEFT downto target'RIGHT)) + 1 - ); - end if; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := SFix( - signed(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - -- Do any overflow required - target := W(target'RANGE); - if HighSX'LENGTH > 0 then - if signed(W(HighSX'RANGE)) /= signed(HighSX) then - case overflow is - when clip_MS => - null; - when saturate => - target := Target_T'(others => not W(W'LEFT)); - target(target'LEFT) := W(W'LEFT); - end case; - end if; - end if; - end; - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. Addition - -- of an integer to a UFix or SFix is accomplished by first - -- converting the integer to the same subtype as the other - -- operand, thereby giving rise to one-bit growth; default - -- truncation and rounding modes are used for the conversion. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed('0' & R))); - return F; - end; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed(R(R'LEFT) & R))); - return F; - end; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix is - variable F: SFix(R'RANGE); - begin - F := R; - if to_X01(R(R'LEFT)) = '1' then - F := SFix(-(signed(R))); - end if; - return F; - end; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix is - variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LU, RU: unsigned(F'RANGE); - begin - LU := (others => '0'); - RU := (others => '0'); - LU(L'RANGE) := unsigned(L); - RU(R'RANGE) := unsigned(R); - F := UFix(LU + RU); - return F; - end; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix is - begin - return L + to_UFix(R); - end; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix is - variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LS, RS: signed(F'RANGE); - begin - LS := (others => '0'); - RS := (others => '0'); - LS(L'RANGE) := signed(L); - RS(R'RANGE) := signed(R); - for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop; - for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop; - F := SFix(LS + RS); - return F; - end; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix is - begin - return L + SFix('0' & R); - end; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix is - begin - return SFix('0' & L) + R; - end; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix is - begin - return L + to_SFix(R); - end; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) + R; - end; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix is - begin - return R + L; - end; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix is - variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - F := UFix(unsigned(LW) - unsigned(RW)); - return F; - end; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix is - begin - return L - to_UFix(R); - end; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) - R; - end; - - -- A.4.4. UFix := UFix - integer - function "-" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix is - variable L_fp: UFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix is - begin - return To_SFix(L) - R; - end; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix is - begin - return L - to_SFix(R); - end; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) - R; - end; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix is - variable L_fp: SFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix is - variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := UFix(unsigned(L) * unsigned(R)); - return F; - end; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix is - begin - return L * to_UFix(R); - end; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) * R; - end; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix is - begin - return R * L; - end; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix is - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := SFix(signed(L) * signed(R)); - return F; - end; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix is - constant RS: SFix := SFix('0' & R); - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - variable FW: SFix(F'LEFT+1 downto F'RIGHT); - begin - FW := SFix(signed(L) * signed(RS)); - Copy_V(F, FW); -- never overflows - return F; - end; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix is - begin - return R * L; - end; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix is - begin - return L * to_SFix(R); - end; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) * R; - end; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix is - begin - return R * L; - end; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - -- - -- Our implementation is based on only two operators, "=" and "<". - -- All other operators are derived from these two, either by - -- logical inversion of the result or by swapping operands. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean is - variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - return unsigned(LW) = unsigned(RW); - end; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean is - begin - return L = to_UFix(R); - end; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean is - begin - return to_UFix(L) = R; - end; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return To_SFix(L) = RS; - end; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean is - begin - return R = L; - end; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - -- clip modes are OK because we aren't losing any bits - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) = signed(RW); - end; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean is - begin - return L = To_SFix(R); - end; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean is - begin - return R = L; - end; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean is - begin - return L = to_SFix(R); - end; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean is - begin - return to_SFix(L) = R; - end; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return L = RS; - end; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean is - begin - return R = L; - end; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean is - variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := unsigned(L); - RW(R'RANGE) := unsigned(R); - return unsigned(LW) < unsigned(RW); - end; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean is - begin - return L < To_UFix(R); - end; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean is - begin - return To_UFix(L) < R; - end; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) < signed(RW); - end; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean is - begin - return not (L = R); - end; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean is - begin - return not (L = R); - end; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean is - begin - return not (L = R); - end; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean is - begin - return R < L; - end; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean is - begin - return R < L; - end; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean is - begin - return R < L; - end; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean is - begin - return not (L < R); - end; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean is - begin - return not (L < R); - end; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean is - begin - return not (L < R); - end; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean is - begin - return not (R < L); - end; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean is - begin - return not (R < L); - end; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean is - begin - return not (R < L); - end; - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix is - begin - return UFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix is - begin - return UFix(concat(std_logic_vector(L), R)); - end; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix is - begin - return UFix(concat(L, std_logic_vector(R))); - end; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix is - begin - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix is - begin - report concat_signLS_msg - severity concat_severity; - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix is - begin - return SFix(concat(std_logic_vector(L), R)); - end; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix is - begin - assert std_match(L, R(R'LEFT)) - report concat_sxt_msg - severity concat_severity; - return SFix(concat(L, std_logic_vector(R))); - end; - - -end; -- package body fix_std; diff --git a/lib/fixed/fixed_util_pkg.vhd b/lib/fixed/fixed_util_pkg.vhd deleted file mode 100644 index 584f186..0000000 --- a/lib/fixed/fixed_util_pkg.vhd +++ /dev/null @@ -1,159 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -package fixed_util_pkg is - - ------------------------------------------------------------- - -- Frequently used constants - constant pi : real := 3.141592653589793e+000; - constant sqrt2 : real := 1.414213562373095e+000; - constant sqrt2_inv : real := 7.071067811865475e-001; - - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - - -- Safe variant of uproto - function uhi (nbits : integer; nbits_frac : integer) return integer; - function ulo (nbits : integer; nbits_frac : integer) return integer; - - -- Safe variant of sproto - function shi (nbits : integer; nbits_frac : integer) return integer; - function slo (nbits : integer; nbits_frac : integer) return integer; - - function to_unsigned (src : ufixed) return UNSIGNED; - function to_signed (src : sfixed) return SIGNED; - - type real_array_t is array (natural range <>) of real; - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t; - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed; - -------------------------------------------------------------------------------- -end; -- package fixed_util_pkg; - -package body fixed_util_pkg is - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac)) := (others => '0'); - begin - return result(uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac)); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (shi(nbits,nbits_frac) downto slo(nbits,nbits_frac)) := (others => '0'); - begin - return result(shi(nbits,nbits_frac) downto slo(nbits,nbits_frac)); - end sproto; - - ------------------------------------------------------------- - function uhi (nbits : integer; nbits_frac : integer) return integer is - begin - return nbits-nbits_frac-1; - end uhi; - - ------------------------------------------------------------- - function ulo (nbits : integer; nbits_frac : integer) return integer is - begin - return -nbits_frac; - end ulo; - - ------------------------------------------------------------- - function shi (nbits : integer; nbits_frac : integer) return integer is - begin - return nbits-nbits_frac; - end shi; - - ------------------------------------------------------------- - function slo (nbits : integer; nbits_frac : integer) return integer is - begin - return -nbits_frac+1; - end slo; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is - variable res : sfixed_array_t(0 to x'length-1, proto'range); - variable tt : sfixed(proto'range); - begin - for i in x'range loop - tt := to_sfixed(x(i), proto); - for j in proto'range loop - res(i,j) := tt(j); - end loop; - end loop; - return res; - end to_sfixed_array; - - --------------------------------------------------------------------------- - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is - variable p : sfixed(shi(nbits, nbits_int) downto slo(nbits, nbits_int)); - begin - return to_sfixed_array(x, p); - end to_sfixed_array; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is - variable dst : ufixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is - variable dst : sfixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - -------------------------------------------------------------------------------- -end; -- package fixed_util_pkg; diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd deleted file mode 100644 index bcd2700..0000000 --- a/lib/fixed_ja/fixed_ja.vhd +++ /dev/null @@ -1,322 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -package fixed_ja is - - - type ufixed_t is array (integer range <>) of STD_LOGIC; - type sfixed_t is array (integer range <>) of STD_LOGIC; - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent); - type saturate_mode_t is (none, saturate); - - -- Declare functions and procedure - - constant ASSERT_NO_WARN : boolean := false; - constant default_round_mode : round_mode_t := none; - constant default_saturate_mode : saturate_mode_t := none; - - -- null array constants - constant NAUF : ufixed_t (0 downto 1) := (others => '0'); - constant NASF : sfixed_t (0 downto 1) := (others => '0'); - constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0'); - - -- Constructor helpers - -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range); - function uproto (nbits : integer; nbits_int : integer) return ufixed_t; - - -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range); - function sproto (nbits : integer; nbits_int : integer) return sfixed_t; - - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t; - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t; - - -- Conversion Functions - function to_ufixed(src : ufixed_t) return ufixed_t; - function to_sfixed(src : sfixed_t) return sfixed_t; - function to_ufixed(src : sfixed_t) return ufixed_t; - function to_sfixed(src : ufixed_t) return sfixed_t; - - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- fixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t; - - -- fixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t; - - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t; - - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t; - - -- fixed <= slv - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t; - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t; - - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t; - - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t; - - -- real <= ufixed - function to_real(src : ufixed_t) return real; - - -- real <= sfixed - function to_real(src : sfixed_t) return real; - - -- slv <= ufixed - function to_slv(src : ufixed_t) return std_logic_vector; - - -- slv <= sfixed - function to_slv(src : sfixed_t) return std_logic_vector; - - -- UNSIGNED <= ufixed - function to_unsigned (src : ufixed_t) return UNSIGNED; - - -- SIGNED <= sfixed - function to_signed (src : sfixed_t) return SIGNED; - - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer; - - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer; - - function to_string(src : ufixed_t) return string; - function to_string(src : sfixed_t) return string; - function to_string(src : std_logic_vector) return string; - - ------------------------------------------------------------- - -- Arithmetic shift left - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t; - function "sla" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Arithmetic shift right - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t; - function "sra" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Multiplication - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Sum - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t; - function "+" (a : sfixed_t; b : integer) return sfixed_t; - function "+" (a : ufixed_t; b : unsigned) return ufixed_t; - function "+" (a : sfixed_t; b : signed) return sfixed_t; - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : std_logic) return ufixed_t; - function "+" (a : sfixed_t; b : std_logic) return sfixed_t; - - - ------------------------------------------------------------- - -- Difference - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t; - function "-" (a : sfixed_t; b : integer) return sfixed_t; - function "-" (a : ufixed_t; b : unsigned) return ufixed_t; - function "-" (a : sfixed_t; b : signed) return sfixed_t; - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : std_logic) return ufixed_t; - function "-" (a : sfixed_t; b : std_logic) return sfixed_t; - - ------------------------------------------------------------- - -- Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean; - function "=" (a : sfixed_t; b : sfixed_t) return boolean; - function "=" (a : ufixed_t; b : sfixed_t) return boolean; - function "=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean; - function "/=" (a : sfixed_t; b : sfixed_t) return boolean; - function "/=" (a : ufixed_t; b : sfixed_t) return boolean; - function "/=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean; - function "<" (a : sfixed_t; b : sfixed_t) return boolean; - function "<" (a : ufixed_t; b : sfixed_t) return boolean; - function "<" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean; - function ">" (a : sfixed_t; b : sfixed_t) return boolean; - function ">" (a : ufixed_t; b : sfixed_t) return boolean; - function ">" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less or equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean; - function "<=" (a : sfixed_t; b : sfixed_t) return boolean; - function "<=" (a : ufixed_t; b : sfixed_t) return boolean; - function "<=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean; - function ">=" (a : sfixed_t; b : sfixed_t) return boolean; - function ">=" (a : ufixed_t; b : sfixed_t) return boolean; - function ">=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Unary Arithmetic Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t; - function "-" (src : ufixed_t) return sfixed_t; - function "-" (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t; - function fpart (src : ufixed_t) return ufixed_t; - function ipart (src : sfixed_t) return sfixed_t; - function fpart (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Print function - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string); - procedure print_info(src : in sfixed_t; prefix : in string); - procedure print_info(src : in string; prefix : in string); - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - function cmsb(src : ufixed_t) return integer; - function clsb(src : ufixed_t) return integer; - - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - - function "MOD" (X, Y: in REAL ) return REAL; - function ipart(src : real) return real; - function fpart(src : real) return real; - - function and_red(arg : ufixed_t) return STD_ULOGIC; - function nand_red(arg : ufixed_t) return STD_ULOGIC; - function or_red(arg : ufixed_t) return STD_ULOGIC; - function nor_red(arg : ufixed_t) return STD_ULOGIC; - function xor_red(arg : ufixed_t) return STD_ULOGIC; - function xnor_red(arg : ufixed_t) return STD_ULOGIC; - function and_red(arg : sfixed_t) return STD_ULOGIC; - function nand_red(arg : sfixed_t) return STD_ULOGIC; - function or_red(arg : sfixed_t) return STD_ULOGIC; - function nor_red(arg : sfixed_t) return STD_ULOGIC; - function xor_red(arg : sfixed_t) return STD_ULOGIC; - function xnor_red(arg : sfixed_t) return STD_ULOGIC; - - -------------------------------------------------------------- - -end; -- package fixed_ja; - diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd deleted file mode 100644 index a85b626..0000000 --- a/lib/fixed_ja/fixed_ja_body.vhd +++ /dev/null @@ -1,1921 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.math_real.all; -use std.textio.all; - -package body fixed_ja is - - ------------------------------------------------------------- - -- Local Procedures - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in ufixed_t; - result : out ufixed_t; - overflowx : out BOOLEAN ) is - - variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0'); - begin -- round_up - srcuns (srcuns'high-1 downto 0) := to_unsigned (src); - resuns := srcuns + 1; - - result := to_ufixed(resuns(src'high-src'low downto 0), src); - overflowx := (resuns(resuns'high) = '1'); - - end procedure round_up; - - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in sfixed_t; - result : out sfixed_t; - overflowx : out BOOLEAN ) is - - variable srcs, ress : SIGNED (src'high-src'low+1 downto 0); - begin -- round_up - srcs (srcs'high-1 downto 0) := to_signed (src); - srcs(srcs'high) := src(src'high); -- sign extend - ress := srcs + 1; - - result := to_sfixed(ress (ress'high-1 downto 0), src); - overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0')); - - end procedure round_up; - - ------------------------------------------------------------- - -- Local functions - ------------------------------------------------------------- - -- round_fixed() --- function round_fixed --- ( --- src : ufixed_t; --- remainder : ufixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return ufixed_t is --- variable res : ufixed_t(src'range); --- begin --- return res; --- --- end round_fixed; - - ------------------------------------------------------------- --- function round_fixed --- ( --- src : sfixed_t; --- remainder : sfixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return sfixed_t is --- variable res : signed(src'length-1 downto 0); --- begin --- return src; --- --- end round_fixed; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0'); - variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - begin - - if proto'high < -1 then - assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - dst := (others => '0'); - dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - if or_red(RemainLow) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round Half-up - -- Round nearest - when round_half_up | round_nearest => - if (RemainLow(RemainLow'high) = '1') then - round_up(tmp, dst, ovf); - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero | none => null; - - when others => - assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or or_red(RemainHigh) = '1'; - end if; - - -- Saturate - if ovf then - dst := (others => '1'); - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - begin - return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0'); - variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - variable sign : std_logic; - begin - - if proto'high < 0 then - assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - sign := src(src'high); - dst := (others => '0'); - dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - round_up(tmp, dst, ovf); - if ovf then - dst(dst'high) := '0'; - end if; - - -- Round Half-up - when round_half_up => - if RemainLow(RemainLow'high) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round nearest - when round_nearest => - if RemainLow(RemainLow'high) = '1' then - if RemainLow'length = 1 then - if sign = '0' then - round_up(tmp, dst, ovf); - end if; - elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero => - if (or_red(RemainLow) = '1' and sign = '1') then - round_up(tmp, dst, ovf); - end if; - - -- No Round - when none => - -- Same as RoundToZero but overflow detection is omitted - dst := tmp + (or_red(RemainLow) and sign); - - when others => - assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - - -- Check negative zero - if dst(dst'high) = '1' then - if or_red(dst(dst'high-1 downto dst'low)) = '0' then - dst(dst'high) := '0'; - -- assert false report "Reshape(S): -0 detected" severity note; - end if; - end if; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or - (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or - (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or - (sign = '0' and or_red(RemainHigh) = '1'); - end if; - - -- Saturate - if ovf then - if (sign = '1') then - dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1'; - else - dst := '0' & (dst'high-1 downto dst'low => '1'); - end if; - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - begin - return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - -- Constuctor helpers - ------------------------------------------------------------- - function uproto (nbits : integer; nbits_int : integer) return ufixed_t is - constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0'); - begin - return result(nbits_int-1 downto nbits_int-nbits); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_int : integer) return sfixed_t is - constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0'); - begin - return result(nbits_int downto nbits_int-nbits+1); - end sproto; - - ------------------------------------------------------------- - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is - constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high + 1; - if (a'high < 0 or b'high < 0) then - if (hi > -1) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end uproto; - - ------------------------------------------------------------- - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is - constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high; - if (a'high = 0 or b'high = 0) then - if (hi > 0) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end sproto; - - ------------------------------------------------------------- - -- Type conversions - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed(src : ufixed_t) return ufixed_t is - begin - return to_ufixed(src, src); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= sfixed - function to_ufixed(src : sfixed_t) return ufixed_t is - variable dst : ufixed_t(src'range) := (others => '0'); - begin - dst := ufixed_t(abs(src)); - return dst(src'high-1 downto src'low); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed(src : sfixed_t) return sfixed_t is - begin - return src; - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= ufixed - function to_sfixed(src : ufixed_t) return sfixed_t is - variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0'); - begin - dst(src'range) := sfixed_t(src); - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is - begin - return to_ufixed(to_unsigned(src, proto'length), proto); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is - variable dst : ufixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0)); - - return dst; - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is - begin - - return to_sfixed(to_signed(src, proto'length), proto); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0)); - dst(dst'high) := src(src'high); - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is - variable result : ufixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (unsigned(src), proto); - return result; - end if; - - end function to_ufixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end function to_ufixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is - variable result : sfixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (signed(src), proto); - return result; - end if; - - end function to_sfixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - ------------------------------------------------------------- - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - constant nbits_ext : integer := nbits + 1; - constant fix_hi : integer := nbits_int - 1; - constant fix_lo : integer := nbits_int - nbits_ext; - - variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0'); - variable i : integer := 0; - variable remain : real := 0.0; - - begin - - if (nbits_int < 0) then - assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error; - end if; - - if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then --- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning; --- print_info(dst, "dst: "); - end if; - - remain := abs(src); - for i in dst'range loop - if remain >= 2.0**i then - dst(i) := '1'; - remain := remain - 2.0**i; - else - dst(i) := '0'; - end if; - end loop; - - return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0'); - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - - begin - utmp := to_ufixed(src, utmp, rnd_mode, sat_mode); - if (src < 0.0) then - dst := -to_sfixed(utmp); - else - dst := to_sfixed(utmp); - end if; - - return dst; - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= real - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode); - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - end to_sfixed; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is - variable dst : ufixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is - variable dst : sfixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : unsigned(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - begin - - for i in src'reverse_range loop - case src(i) is - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - - end case; - - end loop ; - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac; - - return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : signed(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - variable is_neg : boolean := false; - begin - - is_neg := src(src'left) = '-'; - - for i in src'reverse_range loop - case src(i) is - when '-' => null; - when '+' => null; - - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - end case; - end loop ; - nbits := nbits + 1; - - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac-1; - - if is_neg then - dst(nbits-1 downto 0) := -dst(nbits-1 downto 0); - end if; - - return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_sfixed; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed_t) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed_t) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - ------------------------------------------------------------- - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer is - begin - return to_integer(to_unsigned(src)); - end to_integer; - - ------------------------------------------------------------- - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer is - begin - return to_integer(to_signed(src)); - end to_integer; - - ------------------------------------------------------------- - -- to_real - function to_real(src : ufixed_t) return real is - variable dst : real := 0.0; - begin - for i in src'range loop - if (src(i) = '1') then - dst := dst + real(2.0**i); - end if; - end loop; - return dst; - - end to_real; - - ------------------------------------------------------------- - function to_real(src : sfixed_t) return real is - variable dst : real := 0.0; - begin - dst := to_real(to_ufixed(src)); - - if (src(src'high) = '1') then - dst := -dst; - end if; - - return dst; - - end to_real; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - function to_string(src : ufixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j : integer := 0; - - begin - j := src'length+1; - for i in src'high downto 0 loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - function to_string(src : sfixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j, start : integer := 0; - variable strlen : integer := 0; - variable src_abs : sfixed_t(src'range) := (others => '0'); - - begin - if (src'high < 0) then - assert false report "Illegal signed fix point number" severity error; - end if; - - start := src'high; - strlen := src'length; - - j := src'length+1; - if (src(start) = '1') then - str(j) := '-'; - j := j - 1; - start := start - 1; - strlen := strlen + 1; - end if; - - src_abs := abs(src); - - for i in start downto 0 loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str(strlen downto 1); - - end to_string; - - ------------------------------------------------------------- - function to_string(src : std_logic_vector) return string is - variable str : string(src'length downto 1) := (others => '0'); - variable i : integer := 0; - - begin - for i in src'range loop - if (src(i) = '1') then - str(i+1) := '1'; - end if; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - -- Binary Operators - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length) then - result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sla" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable sign : std_logic := '0'; - - begin - sign := src(src'high); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length-1) then - result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length) then - result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count); - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "sra" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0'); - variable sign, do_sub : std_logic := '0'; - - begin - src_slv := to_signed(src); - sign := src(src'high); - do_sub := src(src'high) and src(src'low); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length-1) then - res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count); - if (do_sub = '1') then - result(src'high downto src'low) := to_sfixed(res_slv+1, result); - else - result(src'high downto src'low) := to_sfixed(res_slv, result); - end if; - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low); - - begin - if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1; - else - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result); - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low); - - begin - if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then - result := to_sfixed(signed(a) * signed(b), result) sla 2; - else - result := to_sfixed(signed(a) * signed(b), result) sla 1; - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) * b; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b * a; - - end "*"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low); - - begin - result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result))); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result); --- result := to_sfixed(signed(a) + signed(b), result); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) + b; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b + a; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : signed) return sfixed_t is - - begin - - return sfixed_t(signed(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + to_unsigned(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) + to_signed(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(to_unsigned(a) + buns); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(to_signed(a) + bs); - return result; - - end "+"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low); - begin - result := to_ufixed(to_sfixed(a) - to_sfixed(b)); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is - begin - return to_sfixed(a) - b; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return a - to_sfixed(b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - return ufixed_t(unsigned(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : signed) return sfixed_t is - - begin - return sfixed_t(signed(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) - to_unsigned(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) - to_signed(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(unsigned(a) - buns); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(signed(a) - bs); - return result; - - end "-"; - - ------------------------------------------------------------- - -- Unary Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(abs(signed(src)), src); - - end "abs"; - - ------------------------------------------------------------- - function "-" (src : ufixed_t) return sfixed_t is - begin - return -to_sfixed(src); - - end "-"; - - ------------------------------------------------------------- - function "-" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(-signed(src), src); - - end "-"; - - ------------------------------------------------------------- - -- Binary Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) = to_unsigned(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) = to_signed(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) = b; - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return b = a; - end "="; - - ------------------------------------------------------------- - -- Binary Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - -- Binary less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) < to_unsigned(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) < to_signed(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) < b; - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a < to_sfixed(b); - - end "<"; - - ------------------------------------------------------------- - -- Binary greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) > to_unsigned(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) > to_signed(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) > b; - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a > to_sfixed(b); - end ">"; - - ------------------------------------------------------------- - -- Binary less equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - ------------------------------------------------------------- - -- Binary greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t is - begin - return src(src'high downto 0); - end ipart; - - function fpart (src : ufixed_t) return ufixed_t is - begin - return src(-1 downto src'low); - end fpart; - - function ipart (src : sfixed_t) return sfixed_t is - begin - return src(src'high-1 downto 0); - end ipart; - - function fpart (src : sfixed_t) return sfixed_t is - begin - return src(-1 downto src'low); - end fpart; - - ------------------------------------------------------------- - -- Print functions - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in sfixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in string; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - -- Count significant bits for integer part - function cmsb(src : ufixed_t) return integer is - variable j, i : integer := src'high; - begin - for i in src'range loop - if src(i) = '1' then - exit; - end if; - j := j - 1; - end loop; - - -- LRM nachlesen: hier is i=src'high re-initialisert - - return j; - - end cmsb; - - ------------------------------------------------------------- - -- Count significant bits for fractional part - function clsb(src : ufixed_t) return integer is - variable j, i : integer := src'low; - begin - for i in src'reverse_range loop - if src(i) = '1' then - exit; - end if; - j := j + 1; - end loop; - - -- LRM nachlesen: hier is i=src'low re-initialisert - - return j; - - end clsb; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - ------------------------------------------------------------- - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - - end "MOD"; - - ------------------------------------------------------------- - -- misc. conversion - function ipart(src : real) return real is - begin - return floor(src); - - end ipart; - - ------------------------------------------------------------- - function fpart(src : real) return real is - begin - return src - floor(src); - - end fpart; - - ------------------------------------------------------------- - function or_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '0'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := or_red (BUS_int (BUS_int'left downto Half)); - Lower := or_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper or Lower; - end if; - end if; - return Result; - - end function or_red; - - ------------------------------------------------------------- - function and_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '1'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := and_red (BUS_int (BUS_int'left downto Half)); - Lower := and_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper and Lower; - end if; - end if; - return Result; - - end function and_red; - - ------------------------------------------------------------- - function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is - variable Upper, Lower : STD_ULOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range - begin - if (arg'length >= 1) then - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := xor_red (BUS_int (BUS_int'left downto Half)); - Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper xor Lower; - end if; - end if; - return Result; - - end function xor_red; - - ------------------------------------------------------------- - -- Reduction operators, same as numeric_std functions - function and_red(arg : ufixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : ufixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - function and_red(arg : sfixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : sfixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - ------------------------------------------------------------- - -end; -- package body fixed_ja; diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/jasm/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/jasm/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/jasm/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/jasm/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/jasm/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm deleted file mode 100644 index df557b1..0000000 --- a/lib/jasm/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/jasm/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd deleted file mode 100644 index 04d2861..0000000 --- a/lib/misc/async_port_wb.vhd +++ /dev/null @@ -1,321 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.7 2009-10-28 22:44:07 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use work.async_types.all; - - ------------------------------------------------------------------ -entity async_port_wb is - Generic - ( - addr_width : natural := 32; - data_width : natural := 32; - byte_sel_width : natural := 4; - async_timespec : async_timespec_t - ); - Port - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - page_mode_en : in STD_LOGIC; - async_a : out unsigned(addr_width-1 downto 0); - async_d : inout unsigned(data_width-1 downto 0); - async_cs : out std_logic; - async_wr : out std_logic; - async_rd : out std_logic; - async_be : out unsigned(byte_sel_width-1 downto 0); - async_rst : out std_logic - ); -end async_port_wb; - -architecture Behavioral of async_port_wb is - - type async_t is record - cs : std_logic; - wr : std_logic; - rd : std_logic; - rst : std_logic; - drive_d : std_logic; - end record; - - type async_state_t is (start, reset, idle, leadin, pulse, leadout, release); - - signal s, sn : async_state_t; - signal as : async_t; - signal ack : std_logic; - signal cc_rst : std_logic; - signal cycle_cnt : natural range 0 to 15; - signal cycle_reload : natural range 0 to 15; - signal rdy : std_logic; - signal rdyo : std_logic; - signal en : std_logic; - signal is_idle : std_logic; - signal DAT_I_r : unsigned(data_width-1 downto 0); - signal SEL_I_r : unsigned(byte_sel_width-1 downto 0); - signal WE_I_r : std_logic; - signal ADDR_I_r : unsigned(addr_width-1 downto 0); - signal page_mode_en_r : std_logic; - signal do_page_read : std_logic; - - ------------------------------------------------------------------ - begin - - ASSERT async_timespec.ncyc_pulse_rd > 0 report "Read pulse length must be greater than zero!" severity failure; - ASSERT async_timespec.ncyc_pulse_wr > 0 report "Write pulse length must be greater than zero!" severity failure; - ASSERT (not async_timespec.can_page_rd OR (async_timespec.ncyc_pulse_page_rd > 0)) report "Read page pulse length must be greater than zero!" severity failure; - - SRDY_O <= CYC_I and rdyo; - en <= CYC_I and STB_I; - - do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = WE_I_r) and (WE_I = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0'; - - proc_cycle_counter: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if cc_rst = '1' then - cycle_cnt <= cycle_reload; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - end if; - end if; - end process; - - ------------------------------------------------------------------ - proc_state_next: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - s <= start; - else - s <= sn; - end if; - end if; - end process; - - proc_state: - process(s, cycle_cnt, en, WE_I, WE_I_r, do_page_read) - begin - - cycle_reload <= async_timespec.ncyc_pulse_rst; - cc_rst <= '0'; - as.rst <= '0'; - as.cs <= '0'; - as.wr <= '0'; - as.rd <= '0'; - as.drive_d <= '0'; - ack <= '0'; - rdy <= '0'; - is_idle <= '0'; - - sn <= s; - case s is - - when start => - cc_rst <= '1'; - sn <= reset; - when reset => - as.rst <= '1'; - if cycle_cnt = 0 then - sn <= idle; - end if; - when idle => - rdy <= '1'; - is_idle <= '1'; - if en = '1' then - as.cs <= '1'; - cc_rst <= '1'; - if async_timespec.ncyc_leadin = 0 then - sn <= pulse; - if WE_I = '1' then - cycle_reload <= async_timespec.ncyc_pulse_wr-1; - as.wr <= '1'; - as.drive_d <= '1'; - else - cycle_reload <= async_timespec.ncyc_pulse_rd-1; - as.rd <= '1'; - end if; - else - cycle_reload <= async_timespec.ncyc_leadin-1; - sn <= leadin; - end if; - end if; - - when leadin => - as.cs <= '1'; - if cycle_cnt = 0 then - cc_rst <= '1'; - sn <= pulse; - if WE_I_r = '1' then - cycle_reload <= async_timespec.ncyc_pulse_wr-1; - as.wr <= '1'; - as.drive_d <= '1'; - else - cycle_reload <= async_timespec.ncyc_pulse_rd-1; - as.rd <= '1'; - end if; - end if; - - when pulse => - as.cs <= '1'; - as.rd <= not WE_I_r; - as.drive_d <= WE_I_r; - as.wr <= WE_I_r; - if cycle_cnt = 0 then - as.wr <= '0'; - cc_rst <= '1'; - ack <= not WE_I_r; - rdy <= do_page_read; - if en = '1' and do_page_read = '1' then - as.cs <= '1'; - cycle_reload <= async_timespec.ncyc_pulse_page_rd; - sn <= pulse; - elsif async_timespec.ncyc_leadout = 0 then - if async_timespec.ncyc_release = 0 then - sn <= idle; - else - cycle_reload <= async_timespec.ncyc_release-1; - sn <= release; - end if; - else - cycle_reload <= async_timespec.ncyc_leadout-1; - sn <= leadout; - end if; - end if; - - when leadout => - as.cs <= '1'; - as.drive_d <= WE_I_r; - if cycle_cnt = 0 then - cc_rst <= '1'; - rdy <= '1'; - if en = '1' then - sn <= idle; - elsif async_timespec.ncyc_release = 0 then - sn <= idle; - else - cycle_reload <= async_timespec.ncyc_release-1; - sn <= release; - end if; - end if; - - when release => - if cycle_cnt = 0 then - sn <= idle; - end if; - - when others => - sn <= idle; - - end case; - end process; - - ------------------------------------------------------------------ - output_ctrl: - process(CLK_I) - begin - if rising_edge(CLK_I) then - async_cs <= (not async_timespec.pol_cs) xor as.cs; - async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I_r); - async_wr <= (not async_timespec.pol_we) xor as.wr; - async_rd <= (not async_timespec.pol_oe) xor as.rd; - async_rst <= (not async_timespec.pol_rst) xor as.rst; - end if; - end process; - - ------------------------------------------------------------------ - din_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if as.rd = '1' then - DAT_O(data_width-1 downto 0) <= async_d; - end if; - end if; - end process; - - ------------------------------------------------------------------ - output_addr: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - async_a <= (others => '0'); - SEL_I_r <= (others => '0'); - elsif en = '1' and rdy = '1' then - async_a <= ADDR_I(addr_width-1 downto 0); - SEL_I_r <= SEL_I(byte_sel_width-1 downto 0); - if is_idle = '1' then - ADDR_I_r <= ADDR_I(addr_width-1 downto 0); - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------ - data_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - page_mode_en_r <= page_mode_en; - if en = '1' and rdy = '1' then - DAT_I_r <= DAT_I(data_width-1 downto 0); - WE_I_r <= WE_I; - end if; - end if; - end process; - - ------------------------------------------------------------------ - output_SRDY: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - rdyo <= '1'; - elsif en = '1' then - rdyo <= rdy and not rdyo; - end if; - end if; - end process; - - ------------------------------------------------------------------ - output_ACK: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ACK_O <= '0'; - else - ACK_O <= ack; - end if; - end if; - end process; - - ------------------------------------------------------------------ - output_data: - process(CLK_I) - begin - if rising_edge(CLK_I) then - async_d <= (others => 'Z'); - if as.drive_d = '1' then - async_d <= DAT_I_r; - end if; - end if; - end process; - - ------------------------------------------------------------------ - -end Behavioral; diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd deleted file mode 100644 index 295217f..0000000 --- a/lib/misc/async_types.vhd +++ /dev/null @@ -1,47 +0,0 @@ -------------------------------------------------------------------------- --- Project: MIPS System controller --- This file: --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package async_types is - - type async_timespec_t is record - ncyc_leadin : natural; - ncyc_pulse_rd : natural; - ncyc_pulse_wr : natural; - ncyc_leadout : natural; - ncyc_release : natural; - ncyc_pulse_rst : natural; - can_page_rd : boolean; - nbits_page_rd : natural; - ncyc_pulse_page_rd : natural; - pol_cs : std_logic; - pol_oe : std_logic; - pol_we : std_logic; - pol_be : std_logic; - pol_rst : std_logic; - end record; - -end async_types; diff --git a/lib/misc/bbfifo.vhd b/lib/misc/bbfifo.vhd deleted file mode 100644 index aa8799f..0000000 --- a/lib/misc/bbfifo.vhd +++ /dev/null @@ -1,123 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/bbfifo.vhd,v 1.1 2008-10-20 19:26:01 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity bbfifo is - Generic - ( - depth : integer := 2; - data_width : integer := 8 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - re : in STD_LOGIC; - we : in STD_LOGIC; - ready : out STD_LOGIC; - avail : out STD_LOGIC; - din : in unsigned(data_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -end bbfifo; - -architecture Behavioral of bbfifo is - - type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0); - signal req : unsigned(0 to depth); - signal rdy : unsigned(1 to depth+1); - signal bucket_array : bucket_array_t; - signal ce_in : unsigned(1 to depth); - signal ce_out : unsigned(1 to depth); - -begin - - req(0) <= we; - rdy(depth+1) <= re; - ready <= '1' when req(0 to depth-1) /= (0 to depth-1 => '1') else '0'; - avail <= req(depth); - bucket_array(0) <= din; - dout <= bucket_array(depth); - -gen_ce: - for i in 1 to depth generate - begin - process (rdy, req) - begin - ce_in(i) <= not req(i) and req(i-1); - end process; - end generate; - -gen_rdy: - for i in 1 to depth generate - begin - process (clk) - begin - if rising_edge(clk) then - if rst = '1' then - rdy(i) <= '1'; - elsif req(i-1) = '1' then - rdy(i) <= rdy(i+1); - end if; - end if; - end process; - end generate; - -gen_req: - for i in 1 to depth generate - begin - process (clk) - begin - if rising_edge(clk) then - if rst = '1' then - req(i) <= '0'; - elsif rdy(i+1) = '1' then - req(i) <= req(i-1); - end if; - end if; - end process; - end generate; - -gen_data: - for i in 1 to depth generate - begin - process (clk) - begin - if rising_edge(clk) then - if rst = '1' then - bucket_array(i) <= (others => '0'); - elsif req(i-1) = '1' then - bucket_array(i) <= bucket_array(i-1); - end if; - end if; - end process; - end generate; - -end Behavioral; - diff --git a/lib/misc/clockgen_virtex4.vhd b/lib/misc/clockgen_virtex4.vhd deleted file mode 100644 index a5cac9c..0000000 --- a/lib/misc/clockgen_virtex4.vhd +++ /dev/null @@ -1,236 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Clock generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - sys1_phaseshift : integer := 0; - frequency_hz : integer := 100E6 - ); - port - ( - -- Clocks and Reset - rst : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_fb_in : in std_logic; -- feedback clock - sys1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0° - sys0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270° - locked_out : out std_logic; -- DCM locked status - error_out : out std_logic -- indicates DCM Errors - ); -end; - -architecture tech of clockgen is - - constant CLKIN_PER : real := real(1000E6/frequency_hz); - - signal locked : unsigned(1 downto 0); - signal dcm_rst : unsigned(1 downto 0); - signal sys1_clk0 : std_logic; - signal sys1_clk270 : std_logic; - signal sys1_clk0_bufg : std_logic; - signal sys1_clk270_bufg : std_logic; - signal sys0_clk0 : std_logic; - signal sys0_clk270 : std_logic; - signal sys0_clk0_bufg : std_logic; - signal sys0_clk270_bufg : std_logic; - signal dcm1_locked, dcm2_locked : unsigned(2 downto 0); - signal cnt_q : unsigned(4 downto 0); - - type STATE_TYPE is (s0, s1, s2, s3, s4); - signal state_q : STATE_TYPE; - -begin - - sys1_clk0_out <= sys1_clk0_bufg; - sys1_clk270_out <= sys1_clk270_bufg; - sys0_clk0_out <= sys0_clk0_bufg; - sys0_clk270_out <= sys0_clk270_bufg; - -bufg11: bufg - port map - ( - o => sys0_clk0_bufg, - i => sys0_clk0 - ); - -bufg12: bufg - port map ( - o => sys0_clk270_bufg, - i => sys0_clk270 - ); - -bufg13: bufg - port map - ( - o => sys1_clk0_bufg, - i => sys1_clk0 - ); - -bufg14: bufg - port map ( - o => sys1_clk270_bufg, - i => sys1_clk270 - ); - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys0_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys0_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(0), -- DCM LOCK status output - CLKFB => clk_fb_in, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - - inst_DCM_BASE_1 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => sys1_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys1_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys1_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(1), -- DCM LOCK status output - CLKFB => sys1_clk0_bufg, -- DCM clock feedback - CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - - dcm_rst(1) <= not locked(0); - -dcm_fsm: - process(rst, clk_in) - begin - if rst = '1' then - state_q <= s0; - dcm_rst(0) <= '0'; - cnt_q <= "11111"; - error_out <= '0'; - locked_out <= '0'; - dcm1_locked <= (others => '0'); - dcm2_locked <= (others => '0'); - elsif rising_edge(clk_in) then - case state_q is - when s0 => - state_q <= s1; - - when s1 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '1'; - state_q <= s2; - end if; - - when s2 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '0'; - state_q <= s3; - end if; - - when s3 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - state_q <= s4; - error_out <= '0'; - end if; - - when s4 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - locked_out <= '1'; - else - error_out <= '1'; - end if; - end case; - - -- synchronize 'dcm1_locked' - dcm1_locked <= dcm1_locked(1 downto 0) & locked(0); - dcm2_locked <= dcm2_locked(1 downto 0) & locked(1); - - end if; - end process; - -end architecture tech; - - diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd deleted file mode 100644 index 79317a5..0000000 --- a/lib/misc/debounce.vhd +++ /dev/null @@ -1,91 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:34:24 10/23/05 --- Design Name: --- Module Name: debounce - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity debounce is - Generic ( ncyc_latency : integer := 100); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end debounce; - -architecture Behavioral of debounce is - -type debounce_state_t is (init_st, wait_st, rel_st); -signal debounce_cs : debounce_state_t; -signal debounce_ns : debounce_state_t; -signal count : integer range 0 to ncyc_latency; -signal input_last : std_logic; - -begin - - debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input) - begin - if (rst = '1') then - count <= 0; - output <= input; - input_last <= input; - else - if rising_edge(clk) then - debounce_cs <= debounce_ns; - if (debounce_cs = wait_st) then - if (count /= 0) then - count <= count - 1; - end if; - else - count <= ncyc_latency; - if (debounce_cs = rel_st) then - output <= input; - input_last <= input; - end if; - end if; - end if; - end if; - end process; - - debounce_in: process(rst, clk, input, input_last, debounce_cs, count) - begin - debounce_ns <= debounce_cs; - case debounce_cs is - when init_st => - if (input /= input_last) then - debounce_ns <= wait_st; - end if; - when wait_st => - if (count = 0) then - debounce_ns <= rel_st; - end if; - when others => - debounce_ns <= init_st; - end case; - end process; - -end Behavioral; diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd deleted file mode 100644 index 206a61c..0000000 --- a/lib/misc/debounce2.vhd +++ /dev/null @@ -1,142 +0,0 @@ -------------------------------------------------- --- Signal Debouncer --- Jeff Bazinet --- February 14, 2002 ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - - -library ieee; -use ieee.std_logic_1164.all; -library lpm; -use lpm.lpm_components.lpm_counter; - - -entity debounce is - generic(BUFFER_WIDTH: positive:= 30; - CLOCK_DIV: positive:= 15 - ); - port( clock: in std_logic; - reset: in std_logic; - signal_in: in std_logic; - signal_out: out std_logic - ); -end entity debounce; - - -architecture rtl of debounce is - - --------------------------------------------------------------- - -- SIGNAL DECLARATION - --------------------------------------------------------------- - - -- General - signal reset_n: std_logic; - - -- SLOW CLOCK GENERATION - signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0); - signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1); - signal clock_slow: std_logic; - signal clock_slow_wire: std_logic; - - -- DATA BUFFER FILL - signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- CHECK FOR DEBOUNCE STABILITY - signal stable: std_logic; - signal stable_old: std_logic; - signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- PUSH BUTTON ENABLE - signal button_pushed: std_logic; - - begin - - --------------------------------------------------------------- - -- SLOW CLOCK GENERATION - --------------------------------------------------------------- - - COUNTER_1: lpm_counter - generic map (lpm_width => CLOCK_DIV) - port map ( - clock => clock, - sclr => reset_n, - cout => clock_slow_wire - ); - - process (clock) is - begin - - clock_slow <= clock_slow_wire; - - end process; - - --------------------------------------------------------------- - -- DATA BUFFER FILL - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - data_buffer_reg <= (others => '1'); - elsif rising_edge(clock_slow) then - data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in; - end if; - - end process; - - --------------------------------------------------------------- - -- CHECK FOR DEBOUNCE STABILITY - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - stable <= '0'; - stable_old <= '0'; - stable_state_reg <= (others => '0'); - elsif rising_edge(clock) then - if (data_buffer_reg = stable_state_reg) then - stable <= '1'; - stable_state_reg <= (others => '0'); - else - stable <= '0'; - end if; - stable_old <= stable; - end if; - - end process; - - --------------------------------------------------------------- - -- PUSH BUTTON ENABLE - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - button_pushed <= '0'; - elsif rising_edge(clock) then - if (stable_old = '0' and stable = '1') then - button_pushed <= '1'; - else - button_pushed <= '0'; - end if; - end if; - - end process; - - --------------------------------------------------------------- - --------------------------------------------------------------- - - signal_out <= button_pushed; - reset_n <= not reset; - -end rtl; diff --git a/lib/misc/dpram_1w1r.vhd b/lib/misc/dpram_1w1r.vhd deleted file mode 100644 index dee0972..0000000 --- a/lib/misc/dpram_1w1r.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r; - -architecture Behavioral of dpram_1w1r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd deleted file mode 100644 index e07555c..0000000 --- a/lib/misc/dpram_1w1r_dist.vhd +++ /dev/null @@ -1,84 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r_dist is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r_dist; - -architecture Behavioral of dpram_1w1r_dist is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - - attribute ram_style : string; - attribute ram_style of RAM: signal is "distributed"; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_2w2r.vhd b/lib/misc/dpram_2w2r.vhd deleted file mode 100644 index e5a9e6a..0000000 --- a/lib/misc/dpram_2w2r.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.2 2009-01-14 20:26:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity dpram_2w2r is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_2w2r; - -architecture Behavioral of dpram_2w2r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clk_a) -begin -if clk_a'event and clk_a = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - dout_a <= RAM(to_integer(addr_a)); - end if; -end if; -end process; - -process (clk_b) -begin -if clk_b'event and clk_b = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/gpio_wb.vhd b/lib/misc/gpio_wb.vhd deleted file mode 100644 index 6df62c0..0000000 --- a/lib/misc/gpio_wb.vhd +++ /dev/null @@ -1,320 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY gpio_wb IS - Port - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_TIM_O : out STD_LOGIC; - - sys_gpo0 : out unsigned(31 downto 0); - sys_gpo1 : out unsigned(31 downto 0); - sys_gpi0 : in unsigned(31 downto 0); - sys_gpi1 : in unsigned(31 downto 0) - - ); -END gpio_wb; - -ARCHITECTURE behavior OF gpio_wb IS - - constant num_timers : natural := 2; - - signal gpo0_reg : unsigned(31 downto 0); - signal gpo1_reg : unsigned(31 downto 0); - signal gpi0_reg : unsigned(31 downto 0); - signal gpi1_reg : unsigned(31 downto 0); - -- Signals to form an timer generating an interrupt every microsecond - subtype tick_usec_t is natural range 0 to 99; - signal tick_usec : tick_usec_t; - signal cnt_usec : unsigned(31 downto 0); - signal cnt_sec : unsigned(31 downto 0); - signal cnt_usec_preset : unsigned(31 downto 0); - signal cnt_sec_preset : unsigned(31 downto 0); - signal cnt_usec_en : std_logic; - signal cnt_usec_we : std_logic; - signal cnt_sec_en : std_logic; - signal cnt_sec_we : std_logic; - - type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0); - signal timer_cnt : timer_array_t; - signal timer_cmp : timer_array_t; - signal timer_en : unsigned(0 to num_timers-1); - signal timer_inten : unsigned(0 to num_timers-1); - signal timer_irq : unsigned(0 to num_timers-1); - signal timer_ovl : unsigned(0 to num_timers-1); - signal timer_irq_ack : unsigned(0 to num_timers-1); - signal timer_cnt_we : unsigned(0 to num_timers-1); - signal timer_cmp_we : unsigned(0 to num_timers-1); - - signal reg_data_wr : unsigned(31 downto 0); - -begin - - SRDY_O <= CYC_I; - -tim_irq: - process(timer_irq) - variable irq : std_logic; - begin - irq := '0'; - for i in 0 to num_timers-1 loop - irq := irq or timer_irq(i); - end loop; - INT_TIM_O <= irq; - end process; - ------------------------------------------------------------------- -led_out: - process(CLK_I) - begin - if rising_edge(CLK_I) then - sys_gpo0 <= gpo0_reg; - sys_gpo1 <= gpo1_reg; - end if; - end process; - ------------------------------------------------------------------- -btn_ps2_in: - process(CLK_I) - begin - if rising_edge(CLK_I) then - gpi0_reg <= sys_gpi0; - gpi1_reg <= sys_gpi1; - end if; - end process; - ------------------------------------------------------------------- -registers_write: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cnt_usec_we <= '0'; - cnt_sec_we <= '0'; - timer_cnt_we <= (others => '0'); - timer_cmp_we <= (others => '0'); - timer_irq_ack <= (others => '0'); - if RST_I = '1' then - gpo0_reg <= (others => '0'); - gpo1_reg <= (others => '0'); - timer_en <= (others => '0'); - timer_inten <= (others => '0'); - elsif (STB_I and CYC_I and WE_I) = '1' then - reg_data_wr <= DAT_I; - case ADDR_I(6 downto 2) is - - when "00000" => - if SEL_I(0) = '1' then - gpo0_reg(7 downto 0) <= DAT_I(7 downto 0); - end if; - if SEL_I(1) = '1' then - gpo0_reg(15 downto 8) <= DAT_I(15 downto 8); - end if; - if SEL_I(2) = '1' then - gpo0_reg(23 downto 16) <= DAT_I(23 downto 16); - end if; - if SEL_I(3) = '1' then - gpo0_reg(31 downto 24) <= DAT_I(31 downto 24); - end if; - - when "00001" => - if SEL_I(0) = '1' then - gpo1_reg(7 downto 0) <= DAT_I(7 downto 0); - end if; - if SEL_I(1) = '1' then - gpo1_reg(15 downto 8) <= DAT_I(15 downto 8); - end if; - if SEL_I(2) = '1' then - gpo1_reg(23 downto 16) <= DAT_I(23 downto 16); - end if; - if SEL_I(3) = '1' then - gpo1_reg(31 downto 24) <= DAT_I(31 downto 24); - end if; - - when "00010" => - cnt_usec_we <= '1'; - - when "00011" => - cnt_sec_we <= '1'; - - when "00110" => -- timer control - for i in 0 to num_timers-1 loop - timer_en(i) <= DAT_I(2*i+0); - timer_inten(i) <= DAT_I(2*i+1); - end loop; - when "00111" => -- timer status - for i in 0 to num_timers-1 loop - timer_irq_ack(i) <= DAT_I(2*i); -- IRQ acknowledge - end loop; - - when "01000" => -- timer count 0 - timer_cnt_we(0) <= '1'; - - when "01001" => -- timer count 1 - timer_cnt_we(1) <= '1'; - - when "01100" => -- timer compare 0 - timer_cmp_we(0) <= '1'; - - when "01101" => -- timer compare 1 - timer_cmp_we(1) <= '1'; - - when others => null; - end case; - end if; - end if; - end process; - -registers_read: - process(CLK_I) - begin - if rising_edge(CLK_I) then - ACK_O <= '0'; - if (STB_I and CYC_I) = '1' then - ACK_O <= not WE_I; - DAT_O <= (others => '0'); - case ADDR_I(6 downto 2) is - - when "00000" => - DAT_O <= gpi0_reg; - - when "00001" => - DAT_O <= gpi1_reg; - - when "00010" => - DAT_O <= cnt_usec; - - when "00011" => - DAT_O <= cnt_sec; - - when "00110" => -- timer control - for i in 0 to num_timers-1 loop - DAT_O(2*i+0) <= timer_en(i); - DAT_O(2*i+1) <= timer_inten(i); - end loop; - - when "00111" => -- timer status - for i in 0 to num_timers-1 loop - DAT_O(2*i+0) <= timer_irq(i); - DAT_O(2*i+1) <= timer_ovl(i); - end loop; - - when "01000" => -- timer count 0 - DAT_O <= timer_cnt(0); - - when "01001" => -- timer count 1 - DAT_O <= timer_cnt(1); - - when "01100" => -- timer compare 0 - DAT_O <= timer_cmp(0); - - when "01101" => -- timer compare 1 - DAT_O <= timer_cmp(1); - - when others => null; - end case; - end if; - end if; - end process; - -cnt_usec_tick: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cnt_usec_en <= '0'; - if tick_usec >= tick_usec_t'high then - tick_usec <= 0; - cnt_usec_en <= '1'; - else - tick_usec <= tick_usec + 1; - end if; - end if; - end process; - --- H/W Clock -cnt_usec_clock: - process(CLK_I) - begin - if rising_edge(CLK_I) then - cnt_sec_en <= '0'; - if cnt_usec_we = '1' then - cnt_usec <= reg_data_wr; - elsif cnt_usec_en = '1' then - if cnt_usec >= to_unsigned(1E6 - 1, 32) then - cnt_usec <= (others => '0'); - cnt_sec_en <= '1'; - else - cnt_usec <= cnt_usec + 1; - end if; - end if; - end if; - end process; - -cnt_sec_clock: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if cnt_sec_we = '1' then - cnt_sec <= reg_data_wr; - elsif cnt_sec_en = '1' then - cnt_sec <= cnt_sec + 1; - end if; - end if; - end process; - --- Interrupt timer -proc_int_timer: - process(CLK_I) - begin - if rising_edge(CLK_I) then - for i in 0 to num_timers-1 loop - if RST_I = '1' then - timer_ovl(i) <= '0'; - timer_irq(i) <= '0'; - elsif timer_irq_ack(i) = '1' then - timer_ovl(i) <= '0'; - timer_irq(i) <= '0'; - elsif timer_cnt_we(i) = '1' then - timer_cnt(i) <= reg_data_wr; - elsif timer_en(i) = '1' then - if timer_cnt(i) >= timer_cmp(i) then - timer_cnt(i) <= (others => '0'); - if timer_inten(i) = '1' then - if timer_irq(i) = '1' then - timer_ovl(i) <= '1'; - end if; - timer_irq(i) <= '1'; - end if; - else - timer_cnt(i) <= timer_cnt(i) + 1; - end if; - end if; - end loop; - end if; - end process; - -proc_int_timer_reload: - process(CLK_I) - begin - if rising_edge(CLK_I) then - for i in 0 to num_timers-1 loop - if timer_cmp_we(i) = '1' then - timer_cmp(i) <= reg_data_wr; - end if; - end loop; - end if; - end process; - ------------------------------------------------------------------- -end behavior; diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd deleted file mode 100644 index 11f97eb..0000000 --- a/lib/misc/lcd_port.vhd +++ /dev/null @@ -1,69 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - - ------------------------------------------------------------------ -entity lcd_port is - Port ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - end lcd_port; - -architecture Behavioral of lcd_port is - - constant clcd_e : integer := 7; - constant clcd_rs : integer := 6; - constant clcd_rw : integer := 5; - - type lcd_t is record - d : unsigned(3 downto 0); - e : std_logic; - rs : std_logic; - rw : std_logic; - end record; - - ------------------------------------------------------------------ - begin - - proc_lcd_port: - process(rst, clk) - variable vlcd : lcd_t; - begin - if (rst = '1') then - dout <= (others => '0'); - vlcd.d := (others => '0'); - vlcd.e := '0'; - vlcd.rw := '1'; - vlcd.rs := '0'; - elsif rising_edge(clk) then - dout <= unsigned("0000" & lcd_d); - if we = '1' then - vlcd.d := din(3 downto 0); - vlcd.e := din(clcd_e); - vlcd.rs := din(clcd_rs); - vlcd.rw := din(clcd_rw); - end if; - end if; - if vlcd.rw = '0' then - lcd_d <= unsigned(vlcd.d); - else - lcd_d <= (others => 'Z'); - end if; - lcd_e <= vlcd.e; - lcd_rs <= vlcd.rs; - lcd_rw <= vlcd.rw; - end process; - ------------------------------------------------------------------ - -end Behavioral; diff --git a/lib/misc/mult_signed.vhd b/lib/misc/mult_signed.vhd deleted file mode 100644 index 7740b37..0000000 --- a/lib/misc/mult_signed.vhd +++ /dev/null @@ -1,62 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.numeric_std.all; - -entity signed_mult is -generic -( - latency : natural := 2; - data_width : natural := 16 -); -port -( - clk : in std_logic; - ce : in std_logic; - a : in signed (data_width-1 downto 0); - b : in signed (data_width-1 downto 0); - result : out signed (2*data_width-1 downto 0) -); -end signed_mult; - -architecture rtl of signed_mult is - - constant in_latency : natural := latency - 1; - constant out_latency : natural := latency - in_latency; - - subtype in_t is signed (data_width-1 downto 0); - subtype out_t is signed (2*data_width-1 downto 0); - type in_pipe_t is array (in_latency downto 1) of in_t; - type out_pipe_t is array (out_latency downto 1) of out_t; - - signal a_pipe : in_pipe_t; - signal b_pipe : in_pipe_t; - signal out_pipe : out_pipe_t; - -begin - - result <= out_pipe(out_latency); - -input_pipe_reg: - process(clk) - begin - if rising_edge(clk) then - if ce = '1' then - a_pipe <= a_pipe(in_latency-1 downto 1) & a; - b_pipe <= b_pipe(in_latency-1 downto 1) & b; - end if; - end if; - end process; - -mult_pipe_reg: - process (clk) - variable res : out_t; - begin - if rising_edge(clk) then - res := a_pipe(in_latency) * b_pipe(in_latency); - if ce = '1' then - out_pipe <= out_pipe(out_latency-1 downto 1) & res; - end if; - end if; - end process; - -end rtl; diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd deleted file mode 100644 index 2f5d8bd..0000000 --- a/lib/misc/oneshot.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:52:19 10/22/05 --- Design Name: --- Module Name: oneshot - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ --- Component Template --- --- COMPONENT oneshot --- GENERIC (mode : integer); --- PORT( --- rst : IN std_logic; --- clk : IN std_logic; --- input : IN std_logic; --- output : OUT std_logic --- ); --- END COMPONENT; --- --- Instantation Template --- --- oneshot_int: oneshot --- GENERIC MAP ( --- mode => 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity oneshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end oneshot; - -architecture Behavioral of oneshot is - -type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st); - -signal shot_cs : shot_state_t; -signal shot_ns : shot_state_t; - -begin - -mode_0: -if mode = 0 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= release_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_1: -if mode = 1 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= release_neg_st; - end if; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - - - -end Behavioral; diff --git a/lib/misc/pkg_template.vhd b/lib/misc/pkg_template.vhd deleted file mode 100644 index fe866e8..0000000 --- a/lib/misc/pkg_template.vhd +++ /dev/null @@ -1,18 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/pkg_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package template_pkg is - -- Constants - -- Types - -- Functions - -end template_pkg; - -package body template_pkg is - -end template_pkg; - diff --git a/lib/misc/ram_sim.vhd b/lib/misc/ram_sim.vhd deleted file mode 100644 index 6d26672..0000000 --- a/lib/misc/ram_sim.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(31 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram(index)(7 downto 0) <= din(7 downto 0); - end if; - if we(1) = '1' then - sram(index)(15 downto 8) <= din(15 downto 8); - end if; - if we(2) = '1' then - sram(index)(23 downto 16) <= din(23 downto 16); - end if; - if we(3) = '1' then - sram(index)(31 downto 24) <= din(31 downto 24); - end if; - dout <= sram(index); - end if; - end process; - -end behavior; diff --git a/lib/misc/ram_wb.vhd b/lib/misc/ram_wb.vhd deleted file mode 100644 index 2ebf242..0000000 --- a/lib/misc/ram_wb.vhd +++ /dev/null @@ -1,80 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY ram_wb IS - Port - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0) - ); -END ram_wb; - -ARCHITECTURE behavior OF ram_wb IS - - COMPONENT ram - GENERIC - ( - word_addr_width : integer - ); - PORT - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); - END COMPONENT; - - signal data_en : std_logic; - signal we : unsigned(3 downto 0); - -begin - - we <= SEL_I and (3 downto 0 => WE_I); - - data_en <= CYC_I and STB_I and MRDY_I; - SRDY_O <= CYC_I; - -data_valid_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ACK_O <= '0'; - else - ACK_O <= data_en and not WE_I; - end if; - end if; - end process; - -inst_ram : ram - GENERIC MAP - ( - word_addr_width => 6 - ) - PORT MAP - ( - clk => CLK_I, - ce => data_en, - we => we, - addr => ADDR_I, - din => DAT_I, - dout => DAT_O - ); - - - -end behavior; diff --git a/lib/misc/rom_sim.vhd b/lib/misc/rom_sim.vhd deleted file mode 100644 index 98c0484..0000000 --- a/lib/misc/rom_sim.vhd +++ /dev/null @@ -1,2082 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - constant word_array : word_array_t := - ( - - X"3C1A1040", -- 00000000 - X"375A000C", -- 00000004 - X"409A6000", -- 00000008 - X"241A0000", -- 0000000C - X"409A6800", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1ABFC0", -- 00000020 - X"275A01C4", -- 00000024 - X"03400008", -- 00000028 - X"00000000", -- 0000002C - X"00000000", -- 00000030 - X"00000000", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1BA000", -- 00000184 - X"277B0000", -- 00000188 - X"001AD082", -- 0000018C - X"335A000F", -- 00000190 - X"035BD025", -- 00000194 - X"AF7A0000", -- 00000198 - X"401A6800", -- 0000019C - X"00000000", -- 000001A0 - X"001AD202", -- 000001A4 - X"335A00FF", -- 000001A8 - X"1740FFFB", -- 000001AC - X"00000000", -- 000001B0 - X"401A7000", -- 000001B4 - X"00000000", -- 000001B8 - X"03400008", -- 000001BC - X"42000010", -- 000001C0 - X"3C1AA001", -- 000001C4 - X"275A0008", -- 000001C8 - X"241B000D", -- 000001CC - X"A35B0000", -- 000001D0 - X"3C1DBFD0", -- 000001D4 - X"27BDFFF0", -- 000001D8 - X"241A0005", -- 000001DC - X"1340009F", -- 000001E0 - X"241AFFFB", -- 000001E4 - X"1340009D", -- 000001E8 - X"241A0000", -- 000001EC - X"13400003", -- 000001F0 - X"00000000", -- 000001F4 - X"0BF00118", -- 000001F8 - X"00000000", -- 000001FC - X"241A0005", -- 00000200 - X"241B0006", -- 00000204 - X"135B0095", -- 00000208 - X"241AFFFB", -- 0000020C - X"135B0093", -- 00000210 - X"241A0000", -- 00000214 - X"135B0091", -- 00000218 - X"241A0006", -- 0000021C - X"135B0003", -- 00000220 - X"00000000", -- 00000224 - X"0BF00118", -- 00000228 - X"00000000", -- 0000022C - X"241AFFFB", -- 00000230 - X"0741008A", -- 00000234 - X"241A0005", -- 00000238 - X"07410002", -- 0000023C - X"00000000", -- 00000240 - X"0BF00118", -- 00000244 - X"241A0000", -- 00000248 - X"07410002", -- 0000024C - X"00000000", -- 00000250 - X"0BF00118", -- 00000254 - X"241AFFFB", -- 00000258 - X"1F400080", -- 0000025C - X"241A0000", -- 00000260 - X"1F40007E", -- 00000264 - X"241A0005", -- 00000268 - X"1F400002", -- 0000026C - X"00000000", -- 00000270 - X"0BF00118", -- 00000274 - X"241A0005", -- 00000278 - X"1B400078", -- 0000027C - X"241A0000", -- 00000280 - X"1B400002", -- 00000284 - X"00000000", -- 00000288 - X"0BF00118", -- 0000028C - X"241AFFFB", -- 00000290 - X"1B400002", -- 00000294 - X"00000000", -- 00000298 - X"0BF00118", -- 0000029C - X"241A0005", -- 000002A0 - X"0740006E", -- 000002A4 - X"241A0000", -- 000002A8 - X"0740006C", -- 000002AC - X"241AFFFB", -- 000002B0 - X"07400002", -- 000002B4 - X"00000000", -- 000002B8 - X"0BF00118", -- 000002BC - X"241A0005", -- 000002C0 - X"241B0006", -- 000002C4 - X"175B0002", -- 000002C8 - X"00000000", -- 000002CC - X"0BF00118", -- 000002D0 - X"241AFFFB", -- 000002D4 - X"175B0002", -- 000002D8 - X"00000000", -- 000002DC - X"0BF00118", -- 000002E0 - X"241AFFFA", -- 000002E4 - X"175B0002", -- 000002E8 - X"00000000", -- 000002EC - X"0BF00118", -- 000002F0 - X"241A0000", -- 000002F4 - X"175B0002", -- 000002F8 - X"00000000", -- 000002FC - X"0BF00118", -- 00000300 - X"241A0006", -- 00000304 - X"175B0055", -- 00000308 - X"241A0005", -- 0000030C - X"17400002", -- 00000310 - X"00000000", -- 00000314 - X"0BF00118", -- 00000318 - X"241AFFFB", -- 0000031C - X"17400002", -- 00000320 - X"00000000", -- 00000324 - X"0BF00118", -- 00000328 - X"241A0000", -- 0000032C - X"1740004B", -- 00000330 - X"241B0005", -- 00000334 - X"2F7A0006", -- 00000338 - X"2F7AFFFA", -- 0000033C - X"241BFFFB", -- 00000340 - X"2F7A0006", -- 00000344 - X"2F7AFFFA", -- 00000348 - X"241B0006", -- 0000034C - X"2F7A0005", -- 00000350 - X"2F7AFFFB", -- 00000354 - X"241BFFFA", -- 00000358 - X"2F7A0005", -- 0000035C - X"2F7AFFFB", -- 00000360 - X"241B0005", -- 00000364 - X"2B7A0006", -- 00000368 - X"2B7AFFFA", -- 0000036C - X"241BFFFB", -- 00000370 - X"2B7A0006", -- 00000374 - X"2B7AFFFA", -- 00000378 - X"241B0006", -- 0000037C - X"2B7A0005", -- 00000380 - X"2B7AFFFB", -- 00000384 - X"241BFFFA", -- 00000388 - X"2B7A0005", -- 0000038C - X"2B7AFFFB", -- 00000390 - X"241A0005", -- 00000394 - X"241B0006", -- 00000398 - X"035BD02B", -- 0000039C - X"241A0005", -- 000003A0 - X"241BFFFA", -- 000003A4 - X"035BD02B", -- 000003A8 - X"241AFFFB", -- 000003AC - X"241B0006", -- 000003B0 - X"035BD02B", -- 000003B4 - X"241AFFFB", -- 000003B8 - X"241BFFFA", -- 000003BC - X"035BD02B", -- 000003C0 - X"241A0006", -- 000003C4 - X"241B0005", -- 000003C8 - X"035BD02B", -- 000003CC - X"241A0006", -- 000003D0 - X"241BFFFB", -- 000003D4 - X"035BD02B", -- 000003D8 - X"241AFFFA", -- 000003DC - X"241B0005", -- 000003E0 - X"035BD02B", -- 000003E4 - X"241AFFFA", -- 000003E8 - X"241BFFFB", -- 000003EC - X"035BD02B", -- 000003F0 - X"241A0005", -- 000003F4 - X"241B0006", -- 000003F8 - X"035BD02A", -- 000003FC - X"241A0005", -- 00000400 - X"241BFFFA", -- 00000404 - X"035BD02A", -- 00000408 - X"241AFFFB", -- 0000040C - X"241B0006", -- 00000410 - X"035BD02A", -- 00000414 - X"241AFFFB", -- 00000418 - X"241BFFFA", -- 0000041C - X"035BD02A", -- 00000420 - X"241A0006", -- 00000424 - X"241B0005", -- 00000428 - X"035BD02A", -- 0000042C - X"241A0006", -- 00000430 - X"241BFFFB", -- 00000434 - X"035BD02A", -- 00000438 - X"241AFFFA", -- 0000043C - X"241B0005", -- 00000440 - X"035BD02A", -- 00000444 - X"241AFFFA", -- 00000448 - X"241BFFFB", -- 0000044C - X"035BD02A", -- 00000450 - X"3C1ABFC0", -- 00000454 - X"275A0F2C", -- 00000458 - X"0340F809", -- 0000045C - X"00000000", -- 00000460 - X"0BF00118", -- 00000464 - X"00000000", -- 00000468 - X"27BDFFF0", -- 0000046C - X"AFBE000C", -- 00000470 - X"03A0F021", -- 00000474 - X"40026000", -- 00000478 - X"03C0E821", -- 0000047C - X"8FBE000C", -- 00000480 - X"03E00008", -- 00000484 - X"27BD0010", -- 00000488 - X"27BDFFF0", -- 0000048C - X"AFBE000C", -- 00000490 - X"03A0F021", -- 00000494 - X"40027800", -- 00000498 - X"03C0E821", -- 0000049C - X"8FBE000C", -- 000004A0 - X"03E00008", -- 000004A4 - X"27BD0010", -- 000004A8 - X"27BDFFF0", -- 000004AC - X"AFBE000C", -- 000004B0 - X"03A0F021", -- 000004B4 - X"3C02A001", -- 000004B8 - X"34420004", -- 000004BC - X"AFC20004", -- 000004C0 - X"3C02A001", -- 000004C4 - X"AFC20000", -- 000004C8 - X"8FC20004", -- 000004CC - X"00000000", -- 000004D0 - X"8C420000", -- 000004D4 - X"00000000", -- 000004D8 - X"30420010", -- 000004DC - X"1040FFFA", -- 000004E0 - X"00000000", -- 000004E4 - X"8FC20000", -- 000004E8 - X"00000000", -- 000004EC - X"8C420000", -- 000004F0 - X"00000000", -- 000004F4 - X"00021600", -- 000004F8 - X"00021603", -- 000004FC - X"03C0E821", -- 00000500 - X"8FBE000C", -- 00000504 - X"27BD0010", -- 00000508 - X"03E00008", -- 0000050C - X"00000000", -- 00000510 - X"27BDFFE8", -- 00000514 - X"AFBE0014", -- 00000518 - X"03A0F021", -- 0000051C - X"00801021", -- 00000520 - X"A3C20008", -- 00000524 - X"3C02A001", -- 00000528 - X"34420004", -- 0000052C - X"AFC20004", -- 00000530 - X"3C02A001", -- 00000534 - X"AFC20000", -- 00000538 - X"8FC20004", -- 0000053C - X"00000000", -- 00000540 - X"8C420000", -- 00000544 - X"00000000", -- 00000548 - X"30420002", -- 0000054C - X"1440FFFA", -- 00000550 - X"00000000", -- 00000554 - X"83C30008", -- 00000558 - X"8FC20000", -- 0000055C - X"00000000", -- 00000560 - X"AC430000", -- 00000564 - X"03C0E821", -- 00000568 - X"8FBE0014", -- 0000056C - X"27BD0018", -- 00000570 - X"03E00008", -- 00000574 - X"00000000", -- 00000578 - X"27BDFFF0", -- 0000057C - X"AFBF000C", -- 00000580 - X"AFBE0008", -- 00000584 - X"03A0F021", -- 00000588 - X"00801021", -- 0000058C - X"A3C20000", -- 00000590 - X"83C30000", -- 00000594 - X"2402000A", -- 00000598 - X"1462000B", -- 0000059C - X"00000000", -- 000005A0 - X"2404000D", -- 000005A4 - X"0FF00145", -- 000005A8 - X"00000000", -- 000005AC - X"83C20000", -- 000005B0 - X"00000000", -- 000005B4 - X"00402021", -- 000005B8 - X"0FF00145", -- 000005BC - X"00000000", -- 000005C0 - X"0BF00178", -- 000005C4 - X"00000000", -- 000005C8 - X"83C20000", -- 000005CC - X"00000000", -- 000005D0 - X"00402021", -- 000005D4 - X"0FF00145", -- 000005D8 - X"00000000", -- 000005DC - X"03C0E821", -- 000005E0 - X"8FBF000C", -- 000005E4 - X"8FBE0008", -- 000005E8 - X"27BD0010", -- 000005EC - X"03E00008", -- 000005F0 - X"00000000", -- 000005F4 - X"27BDFFE8", -- 000005F8 - X"AFBF0014", -- 000005FC - X"AFBE0010", -- 00000600 - X"03A0F021", -- 00000604 - X"AFC40008", -- 00000608 - X"8FC20008", -- 0000060C - X"00000000", -- 00000610 - X"AFC20000", -- 00000614 - X"0BF00194", -- 00000618 - X"00000000", -- 0000061C - X"8FC20008", -- 00000620 - X"00000000", -- 00000624 - X"80420000", -- 00000628 - X"00000000", -- 0000062C - X"00401821", -- 00000630 - X"8FC20008", -- 00000634 - X"00000000", -- 00000638 - X"24420001", -- 0000063C - X"AFC20008", -- 00000640 - X"00602021", -- 00000644 - X"0FF0015F", -- 00000648 - X"00000000", -- 0000064C - X"8FC20008", -- 00000650 - X"00000000", -- 00000654 - X"80420000", -- 00000658 - X"00000000", -- 0000065C - X"1440FFEF", -- 00000660 - X"00000000", -- 00000664 - X"8FC30008", -- 00000668 - X"8FC20000", -- 0000066C - X"00000000", -- 00000670 - X"00621023", -- 00000674 - X"03C0E821", -- 00000678 - X"8FBF0014", -- 0000067C - X"8FBE0010", -- 00000680 - X"27BD0018", -- 00000684 - X"03E00008", -- 00000688 - X"00000000", -- 0000068C - X"27BDFFE8", -- 00000690 - X"AFBF0014", -- 00000694 - X"AFBE0010", -- 00000698 - X"03A0F021", -- 0000069C - X"00801021", -- 000006A0 - X"A3C20008", -- 000006A4 - X"AFC00004", -- 000006A8 - X"0BF001CD", -- 000006AC - X"00000000", -- 000006B0 - X"93C20008", -- 000006B4 - X"00000000", -- 000006B8 - X"00021102", -- 000006BC - X"A3C20000", -- 000006C0 - X"83C20008", -- 000006C4 - X"00000000", -- 000006C8 - X"00021100", -- 000006CC - X"A3C20008", -- 000006D0 - X"93C20000", -- 000006D4 - X"00000000", -- 000006D8 - X"2C42000A", -- 000006DC - X"10400007", -- 000006E0 - X"00000000", -- 000006E4 - X"93C20000", -- 000006E8 - X"00000000", -- 000006EC - X"24420030", -- 000006F0 - X"A3C20001", -- 000006F4 - X"0BF001C4", -- 000006F8 - X"00000000", -- 000006FC - X"93C20000", -- 00000700 - X"00000000", -- 00000704 - X"24420037", -- 00000708 - X"A3C20001", -- 0000070C - X"83C20001", -- 00000710 - X"00000000", -- 00000714 - X"00402021", -- 00000718 - X"0FF00145", -- 0000071C - X"00000000", -- 00000720 - X"8FC20004", -- 00000724 - X"00000000", -- 00000728 - X"24420001", -- 0000072C - X"AFC20004", -- 00000730 - X"8FC20004", -- 00000734 - X"00000000", -- 00000738 - X"28420002", -- 0000073C - X"1440FFDC", -- 00000740 - X"00000000", -- 00000744 - X"03C0E821", -- 00000748 - X"8FBF0014", -- 0000074C - X"8FBE0010", -- 00000750 - X"27BD0018", -- 00000754 - X"03E00008", -- 00000758 - X"00000000", -- 0000075C - X"27BDFFE8", -- 00000760 - X"AFBF0014", -- 00000764 - X"AFBE0010", -- 00000768 - X"03A0F021", -- 0000076C - X"AFC40008", -- 00000770 - X"AFC00004", -- 00000774 - X"0BF001F1", -- 00000778 - X"00000000", -- 0000077C - X"8FC20008", -- 00000780 - X"00000000", -- 00000784 - X"00021603", -- 00000788 - X"A3C20001", -- 0000078C - X"83C20001", -- 00000790 - X"00000000", -- 00000794 - X"00402021", -- 00000798 - X"0FF001A4", -- 0000079C - X"00000000", -- 000007A0 - X"8FC20008", -- 000007A4 - X"00000000", -- 000007A8 - X"00021200", -- 000007AC - X"AFC20008", -- 000007B0 - X"8FC20004", -- 000007B4 - X"00000000", -- 000007B8 - X"24420001", -- 000007BC - X"AFC20004", -- 000007C0 - X"8FC20004", -- 000007C4 - X"00000000", -- 000007C8 - X"28420004", -- 000007CC - X"1440FFEB", -- 000007D0 - X"00000000", -- 000007D4 - X"03C0E821", -- 000007D8 - X"8FBF0014", -- 000007DC - X"8FBE0010", -- 000007E0 - X"27BD0018", -- 000007E4 - X"03E00008", -- 000007E8 - X"00000000", -- 000007EC - X"27BDFFE8", -- 000007F0 - X"AFBE0014", -- 000007F4 - X"03A0F021", -- 000007F8 - X"AFC40008", -- 000007FC - X"A3C00000", -- 00000800 - X"AFC00004", -- 00000804 - X"0BF00229", -- 00000808 - X"00000000", -- 0000080C - X"8FC30004", -- 00000810 - X"8FC20008", -- 00000814 - X"00000000", -- 00000818 - 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X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - -end data; diff --git a/lib/misc/rom_wb.vhd b/lib/misc/rom_wb.vhd deleted file mode 100644 index 9fa3715..0000000 --- a/lib/misc/rom_wb.vhd +++ /dev/null @@ -1,61 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom_wb IS - Port - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0) - ); -END rom_wb; - -ARCHITECTURE behavior OF rom_wb IS - - COMPONENT rom - PORT - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); - END COMPONENT; - - signal data_en : std_logic; - -begin - - data_en <= CYC_I and STB_I and MRDY_I; - SRDY_O <= CYC_I; - -data_valid_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - ACK_O <= '0'; - else - ACK_O <= data_en; -- and not WE_I; - end if; - end if; - end process; - -inst_rom : rom - PORT MAP - ( - clk => CLK_I, - ce => data_en, - addr => ADDR_I, - dout => DAT_O - ); - - -end behavior; diff --git a/lib/misc/sim/ModelSim SE .lnk b/lib/misc/sim/ModelSim SE .lnk deleted file mode 100644 index 75fb6b5be9e5e3558345481913609bf399457989..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1445 zcmdT^T}V@57=GtW6bdGuz(i_At0VrE5Yz zV-t0KPt$3K$#i)g<(1h4HRy-3hw_z;$NHu?liby=ebx4Mn6{IaQfXo2mgP*Z$6D3T zA<9ib3Qz-h9Z7inuw_$K0%6qhS=5o!RnAu)XwNsA%cwAcF>09?J=UuO48sWoA2ORM z3|>!-kVnK(C6gFP&d!|udXfS@ ze{)EbjQ%#XXi~GkAiME8>q1hy2mwbzeLuA+=gEcF2V#(GD> z(j&I`0+A45y6#}0Ay_9#e!a_By+uZIy`Y>z__ZsJJY*w*S}_41rXhetIt(d6 zhEPiYXT2SYSB%v{vek6#s2KJK;~VfJHJyu1n>RZ8UZrr4kN00{t$T7eEAM&c>4&s- z(AW9#Z+;HP!AWBV<<-?VoZbqTlQ*pBmnVbLTk`F#oSWLtf2|nseY&WeczjVcPv)?@Xj-tpR!<@2%~^m9MMu(RZ; zCCKTxj~V7*=enb^;>5mon%52vN7Y=@hj?BpJ{0|YTxU3J^*p;tC5X4icD1+83DG;+ zH074C-;*2mQWlh07P3(3rx9Ylq%P0$+O`u*ktnEphSv@u=f(PBMSly)Qdx~P2@IkP z8bD0Q+$Em{rKe@!4qa5eui>-jb;u6TePf5*GkHU~#VjU?!D_@Nhv*UNjrDfOZp41W VVmSwMOCs!Mufm 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity singleshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end singleshot; - -architecture Behavioral of singleshot is - -type s_t is (idle, shot_in, active, shot_out); -signal s, sn : s_t; - -begin - -process (rst, clk, sn) -begin - if rising_edge(clk) then - if rst = '1' then - s <= idle; - else - s <= sn; - end if; - end if; -end process; - -mode_1: -if mode = 1 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_0: -if mode = 0 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -end Behavioral; diff --git a/lib/misc/tb_bbfifo.vhd b/lib/misc/tb_bbfifo.vhd deleted file mode 100644 index 95fa7b9..0000000 --- a/lib/misc/tb_bbfifo.vhd +++ /dev/null @@ -1,136 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity tb_bbfifo is -end; - -architecture behave of tb_bbfifo is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal re : std_logic := '0'; - signal we : std_logic := '0'; - signal ready : std_logic; - signal avail : std_logic; - signal din : unsigned(7 downto 0) := (others => '0'); - signal dout : unsigned(7 downto 0); - signal dout_reg : unsigned(7 downto 0); - - -begin - -inst_bbfifo : entity work.bbfifo - GENERIC MAP - ( - depth => 4, - data_width => 8 - ) - PORT MAP - ( - rst => rst, - clk => clk, - re => re, - we => we, - ready => ready, - avail => avail, - din => din, - dout => dout - ); - - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -RE_GEN: process - begin - wait for 2*CLK_PERIOD; - wait until rising_edge(clk) and avail = '1'; - re <= '0'; - dout_reg <= dout; - wait until rising_edge(clk); - re <= '0'; - end process; - ------------------------------------------------------------------------------------------- - -STIMULUS: process - - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - din <= X"10"; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - wait until rising_edge(clk) and ready = '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '0'; - wait until rising_edge(clk) and ready = '1'; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '0'; - wait until rising_edge(clk) and ready = '1'; - wait until rising_edge(clk) and ready = '1'; - wait until rising_edge(clk) and ready = '1'; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - we <= '1'; - din <= din + 1; - wait until rising_edge(clk) and ready = '1'; - - - wait; - - end process; - -end architecture behave; diff --git a/lib/misc/tb_ram_wb.vhd b/lib/misc/tb_ram_wb.vhd deleted file mode 100644 index b165069..0000000 --- a/lib/misc/tb_ram_wb.vhd +++ /dev/null @@ -1,408 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -ENTITY tb_ram_wb IS -END tb_ram_wb; - -ARCHITECTURE behavior OF tb_ram_wb IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal WE_O : std_logic := '0'; - signal SEL_O : unsigned(3 downto 0) := (others => '1'); - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - signal DAT_O : unsigned(31 downto 0) := (others => '-'); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - -BEGIN - -inst_ram_wb : entity work.ram_wb - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - CYC_I => CYC_O, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => DAT_O, - DAT_O => DAT_I - ); - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' and WE_O = '0' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - RST_O <= '0'; - - -- 8 single cycles - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - DAT_O <= X"1234_0000"; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - DAT_O <= DAT_O + 1; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - - -- 8-word burst cycle - wait for 3*CLK_PERIOD; - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and dout_cnt = 7; - CYC_O <= '0'; - - wait for 3*CLK_PERIOD; - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '1'; - SEL_O <= "0011"; - ADDR_O <= X"0000_0080"; - DAT_O <= X"DEADBEEF"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - wait for 3*CLK_PERIOD; - wait until rising_edge(CLK_O); - -- 1-word burst cycle - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0080"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - wait until rising_edge(CLK_O) and ACK_I = '1'; - CYC_O <= '0'; - - -- 8-word burst cycle - wait for 3*CLK_PERIOD; - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_0000"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - MRDY_O <= '0'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - MRDY_O <= '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and dout_cnt = 54; - CYC_O <= '0'; - - wait; - - end process; - -END; diff --git a/lib/misc/tb_rom_wb.vhd b/lib/misc/tb_rom_wb.vhd deleted file mode 100644 index 0e414f9..0000000 --- a/lib/misc/tb_rom_wb.vhd +++ /dev/null @@ -1,223 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -ENTITY tb_rom_wb IS -END tb_rom_wb; - -ARCHITECTURE behavior OF tb_rom_wb IS - - constant CLK_PERIOD : time := 10 ns; - signal CLK_O : std_logic := '1'; - signal RST_O : std_logic := '1'; - signal CYC_O : std_logic := '0'; - signal STB_O : std_logic := '0'; - signal ACK_I : std_logic; - signal MRDY_O : std_logic := '1'; - signal SRDY_I : std_logic; - signal ADDR_O : unsigned(31 downto 0) := (others => '-'); - signal DAT_I : unsigned(31 downto 0); - - signal dout_rst : std_logic := '0'; - signal dout_reg : unsigned(31 downto 0); - signal dout_cnt : natural range 0 to 255; - -BEGIN - -inst_rom_wb : entity work.rom_wb - PORT MAP - ( - RST_I => RST_O, - CLK_I => CLK_O, - CYC_I => CYC_O, - STB_I => STB_O, - ACK_O => ACK_I, - SRDY_O => SRDY_I, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_O => DAT_I - ); - -read_register: - process(CLK_O) - begin - if rising_edge(CLK_O) then - if dout_rst = '1' then - dout_cnt <= 0; - elsif ACK_I = '1' then - dout_reg <= DAT_I; - dout_cnt <= dout_cnt + 1; - end if; - end if; - end process; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - CLK_O <= not CLK_O; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - RST_O <= '0'; - - -- 8-word burst cycle - wait for 3*CLK_PERIOD; - dout_rst <= '1'; - wait until rising_edge(CLK_O); - dout_rst <= '0'; - CYC_O <= '1'; - STB_O <= '1'; - ADDR_O <= X"0000_0180"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - MRDY_O <= '0'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - MRDY_O <= '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - ADDR_O <= ADDR_O + 4; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - wait until rising_edge(CLK_O) and dout_cnt = 54; - CYC_O <= '0'; - - wait; - - end process; - -END; diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd deleted file mode 100644 index f96f294..0000000 --- a/lib/misc/tb_template.vhd +++ /dev/null @@ -1,63 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_template IS -END tb_template; - -ARCHITECTURE behavior OF tb_template IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT your_comp - GENERIC - ( - ); - PORT - ( - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - --Inputs - signal clk : STD_LOGIC := '0'; - - --Outputs - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: your_comp - GENERIC MAP - ( - ) - PORT MAP - ( - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - - assert false report "Test finished" severity error; - wait; - - END PROCESS; - -END tb_template; diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd deleted file mode 100644 index 789a1b0..0000000 --- a/lib/misc/utils_pkg.vhd +++ /dev/null @@ -1,76 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.2 2009-01-02 15:28:01 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package utils_pkg is - - -- Constants - - -- Functions - function NextPowerOfTwo(x : real) return real; - function NextExpBaseTwo(x : real) return real; - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - -end utils_pkg; - - -package body utils_pkg is - - function NextExpBaseTwo(x : real) return real is - begin - return ceil(log2(x)); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : real) return real is - begin - - return 2.0**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(NextExpBaseTwo(real(x))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - -end utils_pkg; - - diff --git a/lib/radio/cordic/eval_cordic.m b/lib/radio/cordic/eval_cordic.m deleted file mode 100644 index 8754ccd..0000000 --- a/lib/radio/cordic/eval_cordic.m +++ /dev/null @@ -1,171 +0,0 @@ -function eval_cordic(Nmax, doplot) -N = 100; - -arctan_tbl = (atan(2.^-(0:N-1))/pi)' -%gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))' - -% Rotation mode -disp('Rotation:') -for i=1:N, - phi(i) = 2*pi*(i-N/2)/N; - [x(i),y(i)] = cordic_rot(0, 1, phi(i), Nmax, 0); -end; -close all; -figure -plot(1:N, x, 1:N, y); -legend('x','y') -grid; - -% Vector mode -disp('Magnitude and phase:') -for i=1:N, - [mag(i), phi(i)] = cordic_vec(x(i), y(i), Nmax, 0); -end; -figure -plot(1:N, mag, 1:N, phi); -legend('Magnitude','Phase') -grid; - - -% ------------------------------------------------------------ -function [mag, phi] = cordic_cart2polar(x, y, Nmax, doplot) - [mag, phi] = cordic_vec(x, y, Nmax, doplot); - -% ------------------------------------------------------------ -function [x, y] = cordic_polar2cart(mag, phi, Nmax, doplot) - [mag, phi] = cordic_vec(x, y, Nmax, doplot); - -% ------------------------------------------------------------ -function [xout, yout] = cordic_rot(xin, yin, phi, N, doplot) - - % Initialize - arctan_tbl = atan(2.^-(0:N-1)); - gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1)))); - - coeffs = arctan_tbl'; - gains = gain_tbl'; - - % Calculate initial rotation - if (phi < (-pi/2)) - z = phi + pi; - x = -xin; - y = -yin; - else - if (phi > pi/2) - z = phi - pi; - x = -xin; - y = -yin; - else - x = xin; - y = yin; - z = phi; - end; - end; - - % Loop - for i=1:N, - xi(i) = x; - yi(i) = y; - zi(i) = z; - - S = 2^(-(i-1)); - if (z < 0) - t = x + y*S; - y = y - x*S; - z = z + arctan_tbl(i); - x = t; - else - t = x - y*S; - y = y + x*S; - z = z - arctan_tbl(i); - x = t; - end; - - end; - - % Result - k = gain_tbl(i); - xout = k*x; - yout = k*y; - - % Output - if(doplot) - close all; - figure(1); - plot(1:N, xi, 1:N, yi, 1:N, zi) - legend('x','y','z'); - title('Convergence'); - grid; - - figure(2); - plot(xi.*gain_tbl, yi.*gain_tbl, '-x') - title('Polar plot'); - grid; - end; - -% ------------------------------------------------------------ -function [mag, phi] = cordic_vec(xin, yin, N, doplot) - - % Initialize - arctan_tbl = atan(2.^-(0:N-1)); - gain_tbl = 1./cumprod(sqrt(1+2.^-(2*(0:N-1)))); - - coeffs = arctan_tbl'; - gains = gain_tbl'; - - % Calculate initial rotation - if (xin < 0) - x = -xin; - y = -yin; - if (yin < 0) - z = -pi; - else - z = pi; - end; - else - x = xin; - y = yin; - z = 0; - end; - - % Loop - for i=1:N, - xi(i) = x; - yi(i) = y; - zi(i) = z; - - S = 2^(-(i-1)); - if (y < 0) - t = x - y*S; - y = y + x*S; - z = z - arctan_tbl(i); - x = t; - else - t = x + y*S; - y = y - x*S; - z = z + arctan_tbl(i); - x = t; - end; - - end; - - % Result - k = gain_tbl(i); - mag = k*x; - phi = z; - - % Output - if(doplot) - close all; - figure(1); - plot(1:N, xi, 1:N, yi, 1:N, zi) - legend('x','y','z'); - title('Convergence'); - grid; - - figure(2); - plot(xi.*gain_tbl, yi.*gain_tbl, '-x') - title('Polar plot'); - grid; - end; - \ No newline at end of file diff --git a/lib/radio/cordic/sim/eval_cordic.m b/lib/radio/cordic/sim/eval_cordic.m deleted file mode 100644 index dc42068..0000000 --- a/lib/radio/cordic/sim/eval_cordic.m +++ /dev/null @@ -1,10 +0,0 @@ -% function eval_cordic(x0,y0,z0, mode) -function eval_cordic(x0,y0,z0, mode) - -if (mode == 'rot') - Xn = x0*cos(z0) - y0*sin(z0) - Yn = y0*cos(z0) + x0*sin(z0) -else - Xn = sqrt(x0^2 + y0^2) - Yn = z0 + atan(y0/x0) -end; \ No newline at end of file diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo deleted file mode 100644 index 562789d..0000000 --- a/lib/radio/cordic/sim/tb_cordic_pipe_top.fdo +++ /dev/null @@ -1,18 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/cordic_pkg.vhd" -vcom -explicit -93 "../src/cordic_pipe_stage.vhd" -vcom -explicit -93 "../src/cordic_pipe_pre.vhd" -vcom -explicit -93 "../src/cordic_pipe_post.vhd" -vcom -explicit -93 "../src/cordic_pipe_top.vhd" -vcom -explicit -93 "../src/tb_cordic_pipe_top.vhd" -vsim -t 1ps -lib work tb_cordic_pipe_top -do {tb_cordic_pipe_top.wdo} -view wave -view structure -view signals -run 2000us diff --git a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo b/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo deleted file mode 100644 index 3e65178..0000000 --- a/lib/radio/cordic/sim/tb_cordic_pipe_top.wdo +++ /dev/null @@ -1,37 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cordic_pipe_top/clk -add wave -noupdate -format Logic /tb_cordic_pipe_top/rst -add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/xout -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/yout -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/zout -add wave -noupdate -format Logic /tb_cordic_pipe_top/vld_out -add wave -noupdate -divider {Pre stage} -add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_in -add wave -noupdate -format Logic /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/vld_out -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zin -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/xout -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/yout -add wave -noupdate -format Literal -radix decimal /tb_cordic_pipe_top/uut/inst_cordic_pipe_pre/zout -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {10770000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {48466483 ps} diff --git a/lib/radio/cordic/sim/tb_cordic_top.fdo b/lib/radio/cordic/sim/tb_cordic_top.fdo deleted file mode 100644 index 1cb5c84..0000000 --- a/lib/radio/cordic/sim/tb_cordic_top.fdo +++ /dev/null @@ -1,19 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/cordic_pkg.vhd" -vcom -explicit -93 "../src/cordic_rom.vhd" -vcom -explicit -93 "../src/cordic_stage.vhd" -vcom -explicit -93 "../src/cordic_stage_pre.vhd" -vcom -explicit -93 "../src/cordic_stage_post.vhd" -vcom -explicit -93 "../src/cordic_top.vhd" -vcom -explicit -93 "../src/tb_cordic_top.vhd" -vsim -t 1ps -lib work tb_cordic_top -do {tb_cordic_top.wdo} -view wave -view structure -view signals -run 2000us diff --git a/lib/radio/cordic/sim/tb_cordic_top.wdo b/lib/radio/cordic/sim/tb_cordic_top.wdo deleted file mode 100644 index 6cec344..0000000 --- a/lib/radio/cordic/sim/tb_cordic_top.wdo +++ /dev/null @@ -1,64 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider Top -add wave -noupdate -format Literal /tb_cordic_top/uut/cordic_mode -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/xout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/yout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/zout -add wave -noupdate -format Logic /tb_cordic_top/ce -add wave -noupdate -format Logic /tb_cordic_top/valid -add wave -noupdate -divider {Pre stage} -add wave -noupdate -format Literal /tb_cordic_top/uut/inst_cordic_stage_pre/cordic_mode -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/xout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/yout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_pre/zout -add wave -noupdate -divider {Process stage} -add wave -noupdate -format Literal /tb_cordic_top/uut/count -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/coeff -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/xout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/yout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage/zout -add wave -noupdate -divider {Post stage} -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zin -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/xout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/yout -add wave -noupdate -format Literal -radix hexadecimal /tb_cordic_top/uut/inst_cordic_stage_post/zout -add wave -noupdate -divider Signals -add wave -noupdate -format Logic /tb_cordic_top/uut/ce -add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_ready -add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_en -add wave -noupdate -format Logic /tb_cordic_top/uut/pre_stage_valid -add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_ready -add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_en -add wave -noupdate -format Logic /tb_cordic_top/uut/proc_stage_valid -add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_ready -add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_en -add wave -noupdate -format Logic /tb_cordic_top/uut/post_stage_valid -add wave -noupdate -format Literal /tb_cordic_top/uut/state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1463518 ps} 0} -configure wave -namecolwidth 184 -configure wave -valuecolwidth 124 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {655140 ps} {1967644 ps} diff --git a/lib/radio/cordic/sim/tb_results.m b/lib/radio/cordic/sim/tb_results.m deleted file mode 100644 index 9f68f7c..0000000 --- a/lib/radio/cordic/sim/tb_results.m +++ /dev/null @@ -1,34 +0,0 @@ -% Read data -X = TEXTREAD('x.txt'); -Y = TEXTREAD('y.txt'); -Z = TEXTREAD('z.txt'); - -% Output -close all; -plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, Z); -title ('Output'); -legend('X','Y','Z'); -grid; - -W= 2*pi/100; -phi = 0; - -xd = -cos(phi+W*(0:length(X)-1))'; -yd = -sin(phi+W*(0:length(Y)-1))'; - -VarErrorX = var(X-xd) -VarErrorY = var(Y-yd) -MeanErrorX = mean(X-xd) -MeanErrorY = mean(Y-yd) - -figure; -plot(0:length(X)-1, X-xd, 0:length(Y)-1, Y-yd, 0:length(Z)-1, Z); -title ('Error'); -legend('X - X_D','Y - Y_D', 'Z'); -grid; - -figure; -plot(0:length(X)-1, X, 0:length(Y)-1, Y, 0:length(Z)-1, xd, 0:length(yd)-1, yd); -title ('Output'); -legend('X','Y','X_D','Y_D'); -grid; diff --git a/lib/radio/cordic/src/cordic_pipe_post.vhd b/lib/radio/cordic/src/cordic_pipe_post.vhd deleted file mode 100644 index c1203cc..0000000 --- a/lib/radio/cordic/src/cordic_pipe_post.vhd +++ /dev/null @@ -1,107 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_pre - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_pipe_post is -Generic -( - cordic_mode : cordic_mode_t := cordic_mode_rotate; - nstages : integer := 0; - nbits_x : integer := 8; - nbits_x_frac : integer := 6; - nbits_y : integer := 8; - nbits_y_frac : integer := 6; - nbits_z : integer := 8; - nbits_z_frac : integer := 8 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic -); -end cordic_pipe_post; - -architecture Behavioral of cordic_pipe_post is - -constant gain_x : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_x, nbits_x_frac), fixed_wrap, fixed_round); -constant gain_y : sfixed := to_sfixed(gain_tbl(nstages), sproto(nbits_y, nbits_y_frac), fixed_wrap, fixed_round); - ------------------------------------------------------------- -begin - ------------------------------------------------------------- -cordic_proc_pre_stage: - process(clk) - variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); - variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); - variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); - - begin - - if rising_edge(clk) then - vld_out <= '0'; - if rst = '1' then - xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); - yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); - zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); - elsif vld_in = '1' then - - vld_out <= '1'; - - xi := resize(xin, xi); - yi := resize(yin, yi); - zi := resize(zin, zi); - - xo := resize(xi * gain_x, xo, cordic_saturate_mode, cordic_round_mode); - yo := resize(yi * gain_y, yo, cordic_saturate_mode, cordic_round_mode); - zo := zi; - - xout <= xo after tpd; - yout <= yo after tpd; - zout <= zo after tpd; - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_pipe_pre.vhd b/lib/radio/cordic/src/cordic_pipe_pre.vhd deleted file mode 100644 index ae03c5e..0000000 --- a/lib/radio/cordic/src/cordic_pipe_pre.vhd +++ /dev/null @@ -1,137 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_pre - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_pipe_pre is -Generic -( - cordic_mode : cordic_mode_t := cordic_mode_rotate; - z_range : real := pi; - nbits_x : integer := 8; - nbits_x_frac : integer := 6; - nbits_y : integer := 8; - nbits_y_frac : integer := 6; - nbits_z : integer := 8; - nbits_z_frac : integer := 8 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic -); -end cordic_pipe_pre; - -architecture Behavioral of cordic_pipe_pre is - -constant pi_sfix : sfixed := to_sfixed(z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); -constant pi2_sfix : sfixed := to_sfixed(z_range/2.0, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); - ------------------------------------------------------------- -begin - ------------------------------------------------------------- -cordic_proc_pre_stage: - process(clk) - variable xi, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); - variable yi, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); - variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); - - begin - - if rising_edge(clk) then - vld_out <= '0'; - if rst = '1' then - xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); - yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); - zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); - elsif vld_in = '1' then - - vld_out <= '1'; - - xi := xin; - yi := yin; - zi := zin; - - xo := xi; - yo := yi; - zo := zi; - - if (zi < -pi2_sfix) then - xo := resize(-xi, xo); - yo := resize(-yi, yo); - zo := resize(zi + pi_sfix, zo); - elsif (zi > pi2_sfix) then - xo := resize(-xi, xo); - yo := resize(-yi, yo); - zo := resize(zi - pi_sfix, zo); - end if; - - xout <= xo after tpd; - yout <= yo after tpd; - zout <= zo after tpd; - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; - --- if (y < 0) then --- x' = -y --- y' = x --- z' = z + pi/2; --- else --- x' = y --- y' = -x --- z' = z - pi/2; --- end if; --- --- if (x < 0) then --- x' = -x; --- y' = -y; --- z' = z - pi --- else --- x' = x; --- y' = y; --- z' = z --- end if; diff --git a/lib/radio/cordic/src/cordic_pipe_stage.vhd b/lib/radio/cordic/src/cordic_pipe_stage.vhd deleted file mode 100644 index 0428f8a..0000000 --- a/lib/radio/cordic/src/cordic_pipe_stage.vhd +++ /dev/null @@ -1,115 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_pipe_stage is -Generic -( - cordic_mode : cordic_mode_t := cordic_mode_rotate; - z_range : real := pi; - stage_num : integer := 0; - nbits_x : integer := 8; - nbits_x_frac : integer := 6; - nbits_y : integer := 8; - nbits_y_frac : integer := 6; - nbits_z : integer := 8; - nbits_z_frac : integer := 8 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic -); -end cordic_pipe_stage; - -architecture Behavioral of cordic_pipe_stage is - -constant coeff : sfixed := to_sfixed(arctan_tbl(stage_num)*z_range, sproto(nbits_z, nbits_z_frac), fixed_wrap, fixed_round); - -begin - ------------------------------------------------------------- -cordic_proc_stage: - process(clk) - variable xi, xt, xo : sfixed(shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac)); - variable yi, yt, yo : sfixed(shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac)); - variable zi, zo : sfixed(shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac)); - - begin - - if rising_edge(clk) then - vld_out <= '0'; - if rst = '1' then - xout <= (shi(nbits_x, nbits_x_frac) downto slo(nbits_x, nbits_x_frac) => '0'); - yout <= (shi(nbits_y, nbits_y_frac) downto slo(nbits_y, nbits_y_frac) => '0'); - zout <= (shi(nbits_z, nbits_z_frac) downto slo(nbits_z, nbits_z_frac) => '0'); - elsif vld_in = '1' then - - vld_out <= '1'; - - xi := xin; - yi := yin; - zi := zin; - - xt := xi sra stage_num; - yt := yi sra stage_num; - - if zi(zi'high) = '1' then - xo := resize(xi + yt, xo); - yo := resize(yi - xt, yo); - zo := resize(zi + coeff, zo); - else - xo := resize(xi - yt, xo); - yo := resize(yi + xt, yo); - zo := resize(zi - coeff, zo); - end if; - - xout <= xo after tpd; - yout <= yo after tpd; - zout <= zo after tpd; - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_pipe_top.vhd b/lib/radio/cordic/src/cordic_pipe_top.vhd deleted file mode 100644 index e4b73f8..0000000 --- a/lib/radio/cordic/src/cordic_pipe_top.vhd +++ /dev/null @@ -1,319 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:52:30 10/02/05 --- Design Name: --- Module Name: cordic_top - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity cordic_pipe_top is -Generic -( - cordic_mode : cordic_mode_t := cordic_mode_rotate; - z_range : real := 1.0; - gain_corr_mode : gain_corr_mode_t := gain_mode_disabled; - nstages : integer := 18; - nbits_x_in : integer := 18; - nbits_y_in : integer := 18; - nbits_z_in : integer := 18; - nbits_frac_x_in : integer := 16; - nbits_frac_y_in : integer := 16; - nbits_frac_z_in : integer := 16; - nbits_x_out : integer := 18; - nbits_y_out : integer := 18; - nbits_z_out : integer := 18; - nbits_frac_x_out : integer := 17; - nbits_frac_y_out : integer := 17; - nbits_frac_z_out : integer := 17 -); -Port -( - rst : in std_logic; - clk : in std_logic; - vld_in : in std_logic; - xin : in sfixed(shi(nbits_x_in, nbits_frac_x_in) downto slo(nbits_x_in, nbits_frac_x_in)); - yin : in sfixed(shi(nbits_y_in, nbits_frac_y_in) downto slo(nbits_y_in, nbits_frac_y_in)); - zin : in sfixed(shi(nbits_z_in, nbits_frac_z_in) downto slo(nbits_z_in, nbits_frac_z_in)); - xout : out sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); - yout : out sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); - zout : out sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); - vld_out : out std_logic -); -end cordic_pipe_top; - -architecture Behavioral of cordic_pipe_top is - ------------------------------------------------------------------------ -COMPONENT cordic_pipe_pre is -GENERIC -( - cordic_mode : cordic_mode_t; - z_range : real; - nbits_x : integer; - nbits_x_frac : integer; - nbits_y : integer; - nbits_y_frac : integer; - nbits_z : integer; - nbits_z_frac : integer -); -PORT( - rst : IN std_logic; - clk : IN std_logic; - vld_in : IN std_logic; - xin : IN sfixed; - yin : IN sfixed; - zin : IN sfixed; - xout : OUT sfixed; - yout : OUT sfixed; - zout : OUT sfixed; - vld_out : out std_logic -); -END COMPONENT; - -COMPONENT cordic_pipe_stage -GENERIC -( - cordic_mode : cordic_mode_t; - z_range : real; - stage_num : integer; - nbits_x : integer; - nbits_x_frac : integer; - nbits_y : integer; - nbits_y_frac : integer; - nbits_z : integer; - nbits_z_frac : integer -); -PORT( - rst : IN std_logic; - clk : IN std_logic; - vld_in : IN std_logic; - xin : IN sfixed; - yin : IN sfixed; - zin : IN sfixed; - xout : OUT sfixed; - yout : OUT sfixed; - zout : OUT sfixed; - vld_out : out std_logic -); -END COMPONENT; - -COMPONENT cordic_pipe_post is -GENERIC -( - cordic_mode : cordic_mode_t; - nstages : integer; - nbits_x : integer; - nbits_x_frac : integer; - nbits_y : integer; - nbits_y_frac : integer; - nbits_z : integer; - nbits_z_frac : integer -); -PORT( - rst : IN std_logic; - clk : IN std_logic; - vld_in : IN std_logic; - xin : IN sfixed; - yin : IN sfixed; - zin : IN sfixed; - xout : OUT sfixed; - yout : OUT sfixed; - zout : OUT sfixed; - vld_out : out std_logic -); -END COMPONENT; - ------------------------------------------------------------------------ - --- Define number of internal stage bits -constant stage_x_nbits : integer := nbits_x_in + integer(log2(real(nbits_x_in))+0.5); -constant stage_x_nbits_frac : integer := nbits_frac_x_in + integer(log2(real(nbits_x_in))+0.5); -constant stage_y_nbits : integer := nbits_y_in + integer(log2(real(nbits_y_in))+0.5); -constant stage_y_nbits_frac : integer := nbits_frac_y_in + integer(log2(real(nbits_y_in))+0.5); -constant stage_z_nbits : integer := nbits_z_in + integer(log2(real(nbits_z_in))+0.5); -constant stage_z_nbits_frac : integer := nbits_frac_z_in + integer(log2(real(nbits_z_in))+0.5); - --- INPUT --- Input pre stage -signal pre_xin : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); -signal pre_yin : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); -signal pre_zin : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); -signal pre_xout : sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); -signal pre_yout : sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); -signal pre_zout : sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); - --- Input processing stage -subtype stage_x_t is sfixed(shi(stage_x_nbits, stage_x_nbits_frac) downto slo(stage_x_nbits, stage_x_nbits_frac)); -subtype stage_y_t is sfixed(shi(stage_y_nbits, stage_y_nbits_frac) downto slo(stage_y_nbits, stage_y_nbits_frac)); -subtype stage_z_t is sfixed(shi(stage_z_nbits, stage_z_nbits_frac) downto slo(stage_z_nbits, stage_z_nbits_frac)); -type stage_x_array_t is array(0 to nstages) of stage_x_t; -type stage_y_array_t is array(0 to nstages) of stage_y_t; -type stage_z_array_t is array(0 to nstages) of stage_z_t; - -signal stage_vld: unsigned(0 to nstages); -signal stage_x : stage_x_array_t; -signal stage_y : stage_y_array_t; -signal stage_z : stage_z_array_t; - --- Output post stage -signal post_xin : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); -signal post_yin : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); -signal post_zin : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); -signal post_xout : sfixed(shi(nbits_x_out, nbits_frac_x_out) downto slo(nbits_x_out, nbits_frac_x_out)); -signal post_yout : sfixed(shi(nbits_y_out, nbits_frac_y_out) downto slo(nbits_y_out, nbits_frac_y_out)); -signal post_zout : sfixed(shi(nbits_z_out, nbits_frac_z_out) downto slo(nbits_z_out, nbits_frac_z_out)); -signal post_vld : std_logic; - -begin - - pre_xin <= resize(xin, pre_xin); - pre_yin <= resize(yin, pre_yin); - pre_zin <= resize(zin, pre_zin); - - stage_x(0) <= resize(pre_xout, stage_x(0)); - stage_y(0) <= resize(pre_yout, stage_y(0)); - stage_z(0) <= resize(pre_zout, stage_z(0)); - - post_xin <= resize(stage_x(nstages), post_xin, cordic_saturate_mode, cordic_round_mode); - post_yin <= resize(stage_y(nstages), post_yin, cordic_saturate_mode, cordic_round_mode); - post_zin <= resize(stage_z(nstages), post_zin, cordic_saturate_mode, cordic_round_mode); - -gen_output_unity: - if gain_corr_mode = gain_mode_unity generate - begin - xout <= post_xout; - yout <= post_yout; - zout <= post_zout; - vld_out <= post_vld; - end generate; - -gen_output_disabled: - if gain_corr_mode = gain_mode_disabled generate - begin - xout <= post_xin; - yout <= post_yin; - zout <= post_zin; - vld_out <= stage_vld(nstages); - end generate; - ------------------------------------------------------------------------ -Inst_cordic_pipe_pre: cordic_pipe_pre -GENERIC MAP -( - cordic_mode => cordic_mode_rotate, - z_range => z_range, - nbits_x => stage_x_nbits, - nbits_x_frac => stage_x_nbits_frac, - nbits_y => stage_y_nbits, - nbits_y_frac => stage_y_nbits_frac, - nbits_z => stage_z_nbits, - nbits_z_frac => stage_z_nbits_frac -) -PORT MAP -( - rst => rst, - clk => clk, - vld_in => vld_in, - xin => pre_xin, - yin => pre_yin, - zin => pre_zin, - xout => pre_xout, - yout => pre_yout, - zout => pre_zout, - vld_out => stage_vld(0) -); - -gen_pipe: - for i in 1 to nstages generate - - Inst_cordic_pipe: cordic_pipe_stage - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - z_range => z_range, - stage_num => i-1, - nbits_x => stage_x_nbits, - nbits_x_frac => stage_x_nbits_frac, - nbits_y => stage_y_nbits, - nbits_y_frac => stage_y_nbits_frac, - nbits_z => stage_z_nbits, - nbits_z_frac => stage_z_nbits_frac - ) - PORT MAP - ( - rst => rst, - clk => clk, - vld_in => stage_vld(i-1), - xin => stage_x(i-1), - yin => stage_y(i-1), - zin => stage_z(i-1), - xout => stage_x(i), - yout => stage_y(i), - zout => stage_z(i), - vld_out => stage_vld(i) - ); - - end generate; - -gen_post_process: - if gain_corr_mode = gain_mode_unity generate - begin - - Inst_cordic_pipe_post: cordic_pipe_post - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - nstages => nstages, - nbits_x => nbits_x_out, - nbits_x_frac => nbits_frac_x_out, - nbits_y => nbits_y_out, - nbits_y_frac => nbits_frac_y_out, - nbits_z => nbits_z_out, - nbits_z_frac => nbits_frac_z_out - ) - PORT MAP - ( - rst => rst, - clk => clk, - vld_in => stage_vld(nstages), - xin => post_xin, - yin => post_yin, - zin => post_zin, - xout => post_xout, - yout => post_yout, - zout => post_zout, - vld_out => post_vld - ); - - end generate; - --------------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_pkg.vhd b/lib/radio/cordic/src/cordic_pkg.vhd deleted file mode 100644 index d26d2b6..0000000 --- a/lib/radio/cordic/src/cordic_pkg.vhd +++ /dev/null @@ -1,208 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - -package cordic_pkg is - - constant tpd : time := 0 ns; - - type cordic_mode_t is (none, cordic_mode_rotate, cordic_mode_vector); - type reg_mode_t is (none, reg_mode_in, reg_mode_out, reg_mode_inout); - type gain_corr_mode_t is (gain_mode_disabled, gain_mode_unity); - - -- Global set arithmetic rounding mode - constant cordic_round_mode : fixed_round_style_type := fixed_round; - - -- Global set arithmetic saturating mode - constant cordic_saturate_mode : fixed_overflow_style_type := fixed_wrap; - - constant max_iteration : integer := 80; - - -- Normalized Arctan table (for phases z = -1..+1) - -- MatLab command: arctan_tbl = (atan(2.^-(0:N-1))/pi)' - -- (Print format: long e, compact) - constant arctan_tbl : real_array_t (0 to max_iteration-1) := - ( - 2.500000000000000e-001, - 1.475836176504333e-001, - 7.797913037736932e-002, - 3.958342416056555e-002, - 1.986852430554084e-002, - 9.943947823589275e-003, - 4.973187278950414e-003, - 2.486745393669739e-003, - 1.243391668714101e-003, - 6.216982059233716e-004, - 3.108493994100204e-004, - 1.554247367611316e-004, - 7.771237301258342e-005, - 3.885618708529400e-005, - 1.942809361502228e-005, - 9.714046816558053e-006, - 4.857023409409890e-006, - 2.428511704846303e-006, - 1.214255852440821e-006, - 6.071279262226194e-007, - 3.035639631115858e-007, - 1.517819815558274e-007, - 7.589099077791802e-008, - 3.794549538895954e-008, - 1.897274769447984e-008, - 9.486373847239929e-009, - 4.743186923619965e-009, - 2.371593461809983e-009, - 1.185796730904992e-009, - 5.928983654524958e-010, - 2.964491827262479e-010, - 1.482245913631239e-010, - 7.411229568156197e-011, - 3.705614784078099e-011, - 1.852807392039049e-011, - 9.264036960195246e-012, - 4.632018480097623e-012, - 2.316009240048812e-012, - 1.158004620024406e-012, - 5.790023100122029e-013, - 2.895011550061015e-013, - 1.447505775030507e-013, - 7.237528875152536e-014, - 3.618764437576268e-014, - 1.809382218788134e-014, - 9.046911093940670e-015, - 4.523455546970335e-015, - 2.261727773485168e-015, - 1.130863886742584e-015, - 5.654319433712919e-016, - 2.827159716856459e-016, - 1.413579858428230e-016, - 7.067899292141149e-017, - 3.533949646070574e-017, - 1.766974823035287e-017, - 8.834874115176436e-018, - 4.417437057588218e-018, - 2.208718528794109e-018, - 1.104359264397055e-018, - 5.521796321985272e-019, - 2.760898160992636e-019, - 1.380449080496318e-019, - 6.902245402481590e-020, - 3.451122701240795e-020, - 1.725561350620398e-020, - 8.627806753101988e-021, - 4.313903376550994e-021, - 2.156951688275497e-021, - 1.078475844137749e-021, - 5.392379220688743e-022, - 2.696189610344371e-022, - 1.348094805172186e-022, - 6.740474025860928e-023, - 3.370237012930464e-023, - 1.685118506465232e-023, - 8.425592532326160e-024, - 4.212796266163080e-024, - 2.106398133081540e-024, - 1.053199066540770e-024, - 5.265995332703850e-025 - ); - - -- Gain correction table - -- MatLab command: gain_tbl = (1./cumprod(sqrt(1+2.^-(2*(0:N-1)))))' - -- (Print format: long e, compact) - constant gain_tbl : real_array_t (0 to max_iteration-1) := - ( - 7.071067811865475e-001, - 6.324555320336759e-001, - 6.135719910778963e-001, - 6.088339125177524e-001, - 6.076482562561681e-001, - 6.073517701412959e-001, - 6.072776440935260e-001, - 6.072591122988928e-001, - 6.072544793325624e-001, - 6.072533210898752e-001, - 6.072530315291344e-001, - 6.072529591389448e-001, - 6.072529410413973e-001, - 6.072529365170103e-001, - 6.072529353859135e-001, - 6.072529351031394e-001, - 6.072529350324457e-001, - 6.072529350147724e-001, - 6.072529350103540e-001, - 6.072529350092495e-001, - 6.072529350089733e-001, - 6.072529350089043e-001, - 6.072529350088870e-001, - 6.072529350088827e-001, - 6.072529350088816e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001, - 6.072529350088813e-001 - ); - -end; -- package cordic_pkg; - -------------------------------------------------------------------------------- -package body cordic_pkg is - -end; -- package body cordic_pkg; diff --git a/lib/radio/cordic/src/cordic_rom.vhd b/lib/radio/cordic/src/cordic_rom.vhd deleted file mode 100644 index 9af2ac8..0000000 --- a/lib/radio/cordic/src/cordic_rom.vhd +++ /dev/null @@ -1,84 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:37:26 10/02/05 --- Design Name: --- Module Name: coeff_rom - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity rom_arctan is - Generic - ( - nbits : integer := 8; - nbits_frac : integer := 8 - ); - Port - ( - addr : in unsigned(6 downto 0); - dout : out sfixed - ); -end rom_arctan; - -architecture Behavioral of rom_arctan is - -subtype word_t is sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); -type rom_t is array (natural range <>) of word_t; - -------------------------------------------------------------------------------- -function rom_gen(nstages : integer; round_mode : fixed_round_style_type) return rom_t is -variable rom : rom_t (0 to nstages-1); -variable word : word_t; -begin - - for i in 0 to nstages-1 loop - word := to_sfixed(arctan_tbl(i)*pi, word, fixed_wrap, round_mode); - rom(i) := word; - end loop; - - return rom; -end rom_gen; - -------------------------------------------------------------------------------- --- Create ROM -constant arctan_rom : rom_t (0 to max_iteration-1) := rom_gen(max_iteration, cordic_round_mode); - -------------------------------------------------------------------------------- - -begin - --- ROM implementation -rom_arctan: process(addr) -begin - dout <= arctan_rom(to_integer(addr)); -end process; - -------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_stage.vhd b/lib/radio/cordic/src/cordic_stage.vhd deleted file mode 100644 index 26953ce..0000000 --- a/lib/radio/cordic/src/cordic_stage.vhd +++ /dev/null @@ -1,291 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_stage is -Generic -( - nbits : integer := 8; - nbits_frac : integer := 6; - nbits_out : integer := 8; - nbits_frac_out : integer := 6; - reg_mode : reg_mode_t := reg_mode_in -); -Port -( - clk : in std_logic; - rst : in std_logic; - ce : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - coeff : in sfixed; - dir_cw : in std_logic; - stage_count : in integer; - cordic_mode : in cordic_mode_t; - ready : out std_logic; - valid : out std_logic -); -end cordic_stage; - -architecture Behavioral of cordic_stage is - -type xyz_in_t is record - x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); -end record; - -type xyz_out_t is record - x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); -end record; - -constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); -constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); - -signal xyz_in : xyz_in_t; -signal xyz_out : xyz_out_t; -signal valid_r, ready_r : std_logic; - -begin ------------------------------------------------------------- -gen_direct: if reg_mode = none generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; ------------------------------------------------------------- - -gen_reg_in: if (reg_mode = reg_mode_in) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_out: if (reg_mode = reg_mode_out) generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_inout: if (reg_mode = reg_mode_inout) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - -end generate; - ------------------------------------------------------------- -cordic_proc_stage: process(rst, clk, ce, stage_count, coeff, dir_cw, xyz_in) -variable dir_cw_r : std_logic; -variable stage_count_r : integer range 0 to nbits-1; -variable x2, y2 : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - -begin - - if (rst = '1') then - dir_cw_r := dir_cw; - stage_count_r := 0; - x2 := zero_in_sfix; - y2 := zero_in_sfix; - xyz_out.x <= zero_out_sfix; - xyz_out.y <= zero_out_sfix; - xyz_out.z <= zero_out_sfix; - else - if (clk'event and clk = '1') then - dir_cw_r := dir_cw; - stage_count_r := stage_count; - end if; - - x2 := xyz_in.x sra stage_count_r; - y2 := xyz_in.y sra stage_count_r; - - if (dir_cw_r = '1') then - xyz_out.x <= resize(xyz_in.x + y2, xyz_out.x'left, xyz_out.x'right) after tpd; - xyz_out.y <= resize(xyz_in.y - x2, xyz_out.y'left, xyz_out.y'right) after tpd; - xyz_out.z <= resize(xyz_in.z + coeff, xyz_out.z'left, xyz_out.z'right) after tpd; - else - xyz_out.x <= resize(xyz_in.x - y2, xyz_out.x'left, xyz_out.x'right) after tpd; - xyz_out.y <= resize(xyz_in.y + x2, xyz_out.y'left, xyz_out.y'right) after tpd; - xyz_out.z <= resize(xyz_in.z - coeff, xyz_out.z'left, xyz_out.z'right) after tpd; - end if; - end if; -end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_stage_post.vhd b/lib/radio/cordic/src/cordic_stage_post.vhd deleted file mode 100644 index a17c665..0000000 --- a/lib/radio/cordic/src/cordic_stage_post.vhd +++ /dev/null @@ -1,279 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_post - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_stage_post is -Generic -( - nbits : integer := 8; - nbits_frac : integer := 6; - nbits_out : integer := 8; - nbits_frac_out : integer := 6; - reg_mode : reg_mode_t := reg_mode_in -); -Port -( - clk : in std_logic; - rst : in std_logic; - ce : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - cordic_mode : in cordic_mode_t; - ready : out std_logic; - valid : out std_logic -); -end cordic_stage_post; - -architecture Behavioral of cordic_stage_post is - -type xyz_in_t is record - x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); -end record; - -type xyz_out_t is record - x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); -end record; - -constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); -constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); - -signal xyz_in : xyz_in_t; -signal xyz_out : xyz_out_t; -signal valid_r, ready_r : std_logic; - ------------------------------------------------------------- -begin - -gen_direct: if reg_mode = none generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; ------------------------------------------------------------- - -gen_reg_in: if (reg_mode = reg_mode_in) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_out: if (reg_mode = reg_mode_out) generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_inout: if (reg_mode = reg_mode_inout) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - - end generate; - ------------------------------------------------------------- -cordic_post_stage: process(xyz_in, cordic_mode) -begin - - xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right); - - case cordic_mode is - - when cordic_mode_rotate => - - xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode); - xyz_out.y <= resize(xyz_in.y * to_sfixed(gain_tbl(nbits_out-1), xyz_in.y), xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode); - xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode); - - when cordic_mode_vector => - - xyz_out.x <= resize(xyz_in.x * to_sfixed(gain_tbl(nbits_out-1), xyz_in.x), xyz_out.x'left, xyz_out.x'right, cordic_saturate_mode, cordic_round_mode); - xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right, cordic_saturate_mode, cordic_round_mode); - xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right, cordic_saturate_mode, cordic_round_mode); - - when others => null; - - end case; -end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/cordic_stage_pre.vhd b/lib/radio/cordic/src/cordic_stage_pre.vhd deleted file mode 100644 index 0e9f82a..0000000 --- a/lib/radio/cordic/src/cordic_stage_pre.vhd +++ /dev/null @@ -1,320 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_pre - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cordic_stage_pre is -Generic -( - nbits : integer := 8; - nbits_frac : integer := 6; - nbits_out : integer := 8; - nbits_frac_out : integer := 6; - reg_mode : reg_mode_t := reg_mode_in -); -Port -( - clk : in std_logic; - rst : in std_logic; - ce : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - cordic_mode : in cordic_mode_t; - ready : out std_logic; - valid : out std_logic -); -end cordic_stage_pre; - -architecture Behavioral of cordic_stage_pre is - -type xyz_in_t is record - x : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - y : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - z : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); -end record; - -type xyz_out_t is record - x : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - y : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - z : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); -end record; - -constant zero_in_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); -constant zero_out_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); -constant pi_out_sfix : sfixed := to_sfixed(pi, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); -constant pi2_out_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); -constant pi2_in_sfix : sfixed := to_sfixed(pi/2.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); - -signal xyz_in : xyz_in_t; -signal xyz_out : xyz_out_t; -signal valid_r, ready_r : std_logic; - ------------------------------------------------------------- -begin - -gen_direct: if reg_mode = none generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; ------------------------------------------------------------- - -gen_reg_in: if (reg_mode = reg_mode_in) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - else - ready <= ready_r; - valid <= valid_r; - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_out: if (reg_mode = reg_mode_out) generate - - reg_in : process (rst, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - else - ready_r <= '1'; - valid_r <= ce; - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - -end generate; - ------------------------------------------------------------- -gen_reg_inout: if (reg_mode = reg_mode_inout) generate - - reg_in : process (rst, clk, ce, xin, yin, zin) - begin - if (rst = '1') then - ready_r <= '0'; - valid_r <= '0'; - xyz_in.x <= zero_in_sfix; - xyz_in.y <= zero_in_sfix; - xyz_in.z <= zero_in_sfix; - elsif rising_edge(clk) then - ready_r <= '1'; - valid_r <= ce; - if (ce = '1') then - xyz_in.x <= resize(xin, xyz_in.x'left, xyz_in.x'right); - xyz_in.y <= resize(yin, xyz_in.y'left, xyz_in.y'right); - xyz_in.z <= resize(zin, xyz_in.z'left, xyz_in.z'right); - end if; - end if; - end process; - - reg_out : process (rst, clk, ce, ready_r, valid_r, xyz_out) - begin - if (rst = '1') then - ready <= '0'; - valid <= '0'; - xout <= zero_out_sfix; - yout <= zero_out_sfix; - zout <= zero_out_sfix; - elsif rising_edge(clk) then - ready <= ready_r; - valid <= valid_r; - if (ce = '1') then - xout <= xyz_out.x; - yout <= xyz_out.y; - zout <= xyz_out.z; - end if; - end if; - end process; - - end generate; - ------------------------------------------------------------- -cordic_proc_pre_stage: process(xyz_in, cordic_mode) -begin - - xyz_out.x <= resize(xyz_in.x, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(xyz_in.y, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z, xyz_out.z'left, xyz_out.z'right); - - case cordic_mode is - - when cordic_mode_rotate => - - if (xyz_in.z < -pi2_in_sfix) then - xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z + pi_out_sfix, xyz_out.z'left, xyz_out.z'right); - elsif (xyz_in.z > pi2_in_sfix) then - xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right); - end if; - - - when cordic_mode_vector => - --- if (xyz_in.x < zero_in_sfix) then --- xyz_out.x <= resize(-xyz_in.x, xyz_out.x'left, xyz_out.x'right); --- xyz_out.y <= resize(-xyz_in.y, xyz_out.y'left, xyz_out.y'right); --- xyz_out.z <= resize(xyz_in.z - pi_out_sfix, xyz_out.z'left, xyz_out.z'right); --- end if; - if (xyz_in.y < zero_in_sfix) then - xyz_out.x <= resize(-xyz_in.y, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(xyz_in.x, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z + pi2_out_sfix, xyz_out.z'left, xyz_out.z'right); - else - xyz_out.x <= resize(xyz_in.y, xyz_out.x'left, xyz_out.x'right); - xyz_out.y <= resize(-xyz_in.x, xyz_out.y'left, xyz_out.y'right); - xyz_out.z <= resize(xyz_in.z - pi2_out_sfix, xyz_out.z'left, xyz_out.z'right); - end if; - - when others => null; - - end case; -end process; - ------------------------------------------------------------- -end Behavioral; - --- if (y < 0) then --- x' = -y --- y' = x --- z' = z + pi/2; --- else --- x' = y --- y' = -x --- z' = z - pi/2; --- end if; --- --- if (x < 0) then --- x' = -x; --- y' = -y; --- z' = z - pi --- else --- x' = x; --- y' = y; --- z' = z --- end if; diff --git a/lib/radio/cordic/src/cordic_top.vhd b/lib/radio/cordic/src/cordic_top.vhd deleted file mode 100644 index 8f41847..0000000 --- a/lib/radio/cordic/src/cordic_top.vhd +++ /dev/null @@ -1,466 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:52:30 10/02/05 --- Design Name: --- Module Name: cordic_top - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity cordic_top is -Generic -( - nbits : integer := 8; - nbits_frac : integer := 6; - nbits_out : integer := 8; - nbits_frac_out : integer := 6 -); -Port ( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - xin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - yin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - zin : in sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - xout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - yout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - zout : out sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - ready : out std_logic; - valid : out std_logic; - cordic_mode : in cordic_mode_t -); -end cordic_top; - -architecture Behavioral of cordic_top is - ------------------------------------------------------------------------ -COMPONENT cordic_stage_pre is -GENERIC -( - nbits : integer; - nbits_frac : integer; - nbits_out : integer; - nbits_frac_out : integer; - reg_mode : reg_mode_t -); -PORT -( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - cordic_mode : in cordic_mode_t; - ready : OUT std_logic; - valid : out std_logic -); -END COMPONENT; - -COMPONENT cordic_stage -GENERIC -( - nbits : integer; - nbits_frac : integer; - nbits_out : integer; - nbits_frac_out : integer; - reg_mode : reg_mode_t -); -PORT( - rst : IN std_logic; - clk : IN std_logic; - ce : IN std_logic; - xin : IN sfixed; - yin : IN sfixed; - zin : IN sfixed; - xout : OUT sfixed; - yout : OUT sfixed; - zout : OUT sfixed; - coeff : in sfixed; - dir_cw : in std_logic; - stage_count : IN integer; - cordic_mode : in cordic_mode_t; - ready : OUT std_logic; - valid : out std_logic -); -END COMPONENT; - -COMPONENT cordic_stage_post is -GENERIC -( - nbits : integer; - nbits_frac : integer; - nbits_out : integer; - nbits_frac_out : integer; - reg_mode : reg_mode_t -); -PORT -( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - cordic_mode : in cordic_mode_t; - ready : OUT std_logic; - valid : out std_logic -); -END COMPONENT; - -COMPONENT rom_arctan is -GENERIC -( - nbits : integer := 8; - nbits_frac : integer := 8 -); -PORT -( - addr : in unsigned(6 downto 0); - dout : out sfixed -); -END COMPONENT; - ------------------------------------------------------------------------ -type state_type is (st_input, st_ready, st_pre_stage_in, st_pre_stage_out, st_proc_stage_in, st_proc_stage_out, st_post_stage_in, st_post_stage_out); - -constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits_out, nbits_frac_out)'high, sproto(nbits_out, nbits_frac_out)'low); - --- Define number of LSB guard bits -constant guard_nbits : integer := integer(log2(real(nbits))+0.5); - --- Define number of internal stage bits -constant stage_nbits : integer := nbits + guard_nbits; -- add more internal precision -constant stage_nbits_frac : integer := nbits_frac; - --- Set number of coefficient bits -constant coeff_nbits : integer := nbits; -constant coeff_nbits_frac : integer := nbits; -- coeffs have no integer part - --- Set number of iteration with respect to bit size -constant max_stage_count : integer := stage_nbits; - --- INPUT --- Input pre stage -signal pre_stage_en : std_logic; -signal xin_pre, yin_pre, zin_pre : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - --- Output pre stage -signal pre_stage_ready, pre_stage_valid : std_logic; -signal xout_pre, yout_pre, zout_pre : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); - --- Input processing stage -signal proc_stage_en: std_logic; -signal xin_stage, yin_stage, zin_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); - --- Output processing stage -signal proc_stage_ready, proc_stage_valid : std_logic; -signal xout_stage, yout_stage, zout_stage : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); - --- Input post stage -signal post_stage_en : std_logic; -signal xin_post, yin_post, zin_post : sfixed(sproto(stage_nbits, stage_nbits_frac)'high downto sproto(stage_nbits, stage_nbits_frac)'low); - --- Output post stage -signal post_stage_ready, post_stage_valid : std_logic; -signal xout_post, yout_post, zout_post : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low); - --- ROM -signal rom_addr : unsigned (6 downto 0); -signal rom_data : sfixed(sproto(coeff_nbits, coeff_nbits_frac)'high downto sproto(coeff_nbits, coeff_nbits_frac)'low); - --- Misc. -signal state, next_state : state_type; -signal count : integer range 0 to max_stage_count-1 := 0; -signal count_en, dir_cw, valid_s : std_logic; - - -begin - ------------------------------------------------------------------------ -cordic_proc_mode : process(rst, zin_stage, yin_stage, cordic_mode) - -begin - - if (rst = '1') then - dir_cw <= '0'; - else - dir_cw <= '0'; - case cordic_mode is - - when cordic_mode_rotate => - if (zin_stage(zin_stage'high) = '1') then - dir_cw <= '1'; - end if; - - when cordic_mode_vector => - if (yin_stage(yin_stage'high) = '1') then - dir_cw <= '0'; - else - dir_cw <= '1'; - end if; - - when others => null; - - end case; - end if; -end process; - ------------------------------------------------------------------------ -counter: process (clk, rst, count, count_en) -begin - if (rst = '1') then - count <= 0; - rom_addr <= (others => '0'); - else - if (clk'event and clk = '1') then - rom_addr <= to_unsigned(count, rom_addr'length); - if (count_en = '1' and count < max_stage_count-1) then - count <= count + 1 after tpd; - else - count <= 0; - end if; - end if; - end if; -end process; - ------------------------------------------------------------------------ -OUTPUT_PROC: process (clk, rst, state, xout_stage, yout_stage, zout_stage) -begin - if (rst='1') then - valid <= '0'; - xout <= zero_sfix after tpd; - yout <= zero_sfix after tpd; - zout <= zero_sfix after tpd; - - -- assign other outputs to reset value - elsif (clk'event and clk = '1') then - valid <= '0'; - if(post_stage_valid = '1') then - xout <= xout_post; - yout <= yout_post; - zout <= zout_post; - valid <= '1'; - end if; - end if; -end process; - ------------------------------------------------------------------------ ---Insert the following in the architecture after the begin keyword - FSM_PROC: process (clk, rst, xout_stage, yout_stage, zout_stage) - begin - if (rst='1') then - state <= st_ready; - -- assign other outputs to reset value - elsif (clk'event and clk = '1') then - state <= next_state after tpd; - -- assign other outputs to internal signals - end if; - end process; - - --MOORE State Machine - Outputs based on state only -Control_proc: process (state, xin, yin, zin, xout_pre, yout_pre, zout_pre, xout_stage, yout_stage, zout_stage) -begin - --insert statements to decode internal output signals - --below is simple example - ready <= '0'; - valid_s <= '0'; - count_en <= '0'; - pre_stage_en <= '0'; - proc_stage_en <= '0'; - post_stage_en <= '0'; - - xin_pre <= xin; - yin_pre <= yin; - zin_pre <= zin; - xin_stage <= xout_stage; - yin_stage <= yout_stage; - zin_stage <= zout_stage; - xin_post <= xout_stage; - yin_post <= yout_stage; - zin_post <= zout_stage; - - case (state) is - when st_ready => - ready <= '1'; - when st_pre_stage_in => - pre_stage_en <= '1'; - when st_pre_stage_out => - count_en <= '1'; - proc_stage_en <= '1'; - xin_stage <= xout_pre; - yin_stage <= yout_pre; - zin_stage <= zout_pre; - when st_proc_stage_in => - count_en <= '1'; - proc_stage_en <= '1'; - when st_post_stage_in => - post_stage_en <= '1'; - - when others => - end case; -end process; - -NEXT_STATE_DECODE: process (state, ce, count) -begin - --declare default state for next_state to avoid latches - next_state <= state; --default is to stay in current state - --insert statements to decode next_state - --below is a simple example - case (state) is - when st_ready => - if ce = '1' then - next_state <= st_input; - end if; - - when st_input => - if ce = '0' then - next_state <= st_pre_stage_in; - end if; - - when st_pre_stage_in => - next_state <= st_pre_stage_out; - - when st_pre_stage_out => - next_state <= st_proc_stage_in; - - when st_proc_stage_in => - if (count = max_stage_count-2) then - next_state <= st_post_stage_in; - end if; - - when st_post_stage_in => - next_state <= st_ready; - - when others => - next_state <= st_ready; - - end case; -end process; - ------------------------------------------------------------------------ -Inst_cordic_stage_pre: cordic_stage_pre -GENERIC MAP -( - nbits => nbits, - nbits_frac => nbits_frac, - nbits_out => stage_nbits, - nbits_frac_out => stage_nbits_frac, - reg_mode => reg_mode_in -) -PORT MAP -( - rst => rst, - clk => clk, - ce => pre_stage_en, - xin => xin_pre, - yin => yin_pre, - zin => zin_pre, - xout => xout_pre, - yout => yout_pre, - zout => zout_pre, - ready => pre_stage_ready, - valid => pre_stage_valid, - cordic_mode => cordic_mode -); - -Inst_cordic_stage: cordic_stage -GENERIC MAP -( - nbits => stage_nbits, - nbits_frac => stage_nbits_frac, - nbits_out => stage_nbits, - nbits_frac_out => stage_nbits_frac, - reg_mode => reg_mode_in -) -PORT MAP -( - rst => rst, - clk => clk, - ce => proc_stage_en, - xin => xin_stage, - yin => yin_stage, - zin => zin_stage, - xout => xout_stage, - yout => yout_stage, - zout => zout_stage, - coeff => rom_data, - dir_cw => dir_cw, - stage_count => count, - ready => proc_stage_ready, - valid => proc_stage_valid, - cordic_mode => cordic_mode -); - -Inst_cordic_stage_post: cordic_stage_post -GENERIC MAP -( - nbits => stage_nbits, - nbits_frac => stage_nbits_frac, - nbits_out => nbits_out, - nbits_frac_out => nbits_frac_out, - reg_mode => reg_mode_in -) -PORT MAP -( - rst => rst, - clk => clk, - ce => post_stage_en, - xin => xin_post, - yin => yin_post, - zin => zin_post, - xout => xout_post, - yout => yout_post, - zout => zout_post, - ready => post_stage_ready, - valid => post_stage_valid, - cordic_mode => cordic_mode -); - -Inst_rom_arctan: rom_arctan -GENERIC MAP -( - nbits => coeff_nbits, - nbits_frac => coeff_nbits_frac -) -PORT MAP -( - addr => rom_addr, - dout => rom_data -); - --------------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd b/lib/radio/cordic/src/tb_cordic_pipe_top.vhd deleted file mode 100644 index c88dd33..0000000 --- a/lib/radio/cordic/src/tb_cordic_pipe_top.vhd +++ /dev/null @@ -1,653 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 10/02/2005 --- Design Name: cordic_top --- Module Name: tb_cordic_top.vhd --- Project Name: cordic --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: cordic_top --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- --- Results:In 16i2 and Out 16i0 ------------------------------- --- xmean = -3.051757808671257e-7 --- ymean = 1.525878906192144e-6 --- zmean = 0.0 --- xvar = 7.723598281502283e-10 --- yvar = 8.539443970667266e-10 --- zvar = 0.0 --- xstd = 2.779136247380161e-5 --- ystd = 2.922232703031582e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 16i2 and Out 16i1 ------------------------------- --- xmean = 6.103515628828741e-7 --- ymean = -1.220703125057855e-6 --- zmean = 0.0 --- xvar = 9.76293486677989e-10 --- yvar = 7.934037490259732e-10 --- zvar = 0.0 --- xstd = 3.124569549038697e-5 --- ystd = 2.816742354256017e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 16i2 and Out 16i2 ------------------------------- --- xmean = 2.441406250382875e-6 --- ymean = -1.220703125057855e-6 --- zmean = 0.0 --- xvar = 2.126680036682826e-9 --- yvar = 2.117107754473399e-9 --- zvar = 0.0 --- xstd = 4.611594124251206e-5 --- ystd = 4.601203923402438e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i0 ------------------------------- --- xmean = -9.312842871812748e-12 --- ymean = -5.78558739545293e-17 --- zmean = 0.0 --- xvar = 1.671709854744817e-19 --- yvar = 1.790442305004033e-19 --- zvar = 0.0 --- xstd = 4.088654857951228e-10 --- ystd = 4.231361843430591e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i1 ------------------------------- --- xmean = 9.313608620496825e-12 --- ymean = 9.31316789028083e-12 --- zmean = 0.0 --- xvar = 1.876480788588237e-19 --- yvar = 2.238344116260579e-19 --- zvar = 0.0 --- xstd = 4.331836548841885e-10 --- ystd = 4.731114156581492e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i2 ------------------------------- --- xmean = -3.72525201102771e-11 --- ymean = -5.78558739545293e-17 --- zmean = 0.0 --- xvar = 5.458335981037092e-19 --- yvar = 5.704280631341228e-19 --- zvar = 0.0 --- xstd = 7.388055211648797e-10 --- ystd = 7.552668820583376e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 64i2 and Out 64i0 ------------------------------- --- xmean = 3.45418680637588e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205267218835516e-16 --- xvar = 5.54111959258452e-28 --- yvar = 5.549496221074054e-28 --- zvar = 7.916891206490056e-29 --- xstd = 2.353958281827551e-14 --- ystd = 2.355736874329146e-14 --- zstd = 8.897691389619023e-15 --- ------------------------------- --- Results:In 64i2 and Out 64i1 ------------------------------- --- xmean = 3.45418680637588e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205267218835516e-16 --- xvar = 5.541120861185077e-28 --- yvar = 5.549497432144743e-28 --- zvar = 7.916856202525234e-29 --- xstd = 2.353958551288674e-14 --- ystd = 2.355737131376237e-14 --- zstd = 8.897671719346156e-15 --- ------------------------------- --- Results:In 64i2 and Out 64i2 ------------------------------- --- xmean = 3.343164503913365e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205223850748616e-16 --- xvar = 5.540559656182732e-28 --- yvar = 5.549495010008071e-28 --- zvar = 7.916821581863743e-29 --- xstd = 2.353839343749427e-14 --- ystd = 2.355736617283025e-14 --- zstd = 8.897652264425568e-15 --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cordic_pipe_top IS - Generic ( - nbits_x_in : integer := 18; - nbits_y_in : integer := 18; - nbits_z_in : integer := 24; - nbits_frac_x_in : integer := 17; - nbits_frac_y_in : integer := 17; - nbits_frac_z_in : integer := 22; - nbits_x_out : integer := 18; - nbits_y_out : integer := 18; - nbits_z_out : integer := 18; - nbits_frac_x_out : integer := 17; - nbits_frac_y_out : integer := 17; - nbits_frac_z_out : integer := 17 - ); -END tb_cordic_pipe_top; - -ARCHITECTURE behavior OF tb_cordic_pipe_top IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cordic_pipe_top - GENERIC - ( - cordic_mode : cordic_mode_t; - z_range : real; - gain_corr_mode : gain_corr_mode_t; - nstages : integer; - nbits_x_in : integer; - nbits_y_in : integer; - nbits_z_in : integer; - nbits_frac_x_in : integer; - nbits_frac_y_in : integer; - nbits_frac_z_in : integer; - nbits_x_out : integer; - nbits_y_out : integer; - nbits_z_out : integer; - nbits_frac_x_out : integer; - nbits_frac_y_out : integer; - nbits_frac_z_out : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Constants - constant num_cycles : integer := 5; - constant num_steps_per_cycle : integer := 100; - constant PERIOD : time := 10 ns; - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL rst : std_logic := '1'; - SIGNAL vld_in : std_logic := '0'; - SIGNAL xin : sfixed(sproto(nbits_x_in, nbits_frac_x_in)'high downto sproto(nbits_x_in, nbits_frac_x_in)'low) := to_sfixed(0.0, sproto(nbits_x_in, nbits_frac_x_in)'high, sproto(nbits_x_in, nbits_frac_x_in)'low); - SIGNAL yin : sfixed(sproto(nbits_y_in, nbits_frac_y_in)'high downto sproto(nbits_y_in, nbits_frac_y_in)'low) := to_sfixed(0.0, sproto(nbits_y_in, nbits_frac_y_in)'high, sproto(nbits_y_in, nbits_frac_y_in)'low); - SIGNAL zin : sfixed(sproto(nbits_z_in, nbits_frac_z_in)'high downto sproto(nbits_z_in, nbits_frac_z_in)'low) := to_sfixed(0.0, sproto(nbits_z_in, nbits_frac_z_in)'high, sproto(nbits_z_in, nbits_frac_z_in)'low); - - --Outputs - SIGNAL xout : sfixed(sproto(nbits_x_out, nbits_frac_x_out)'high downto sproto(nbits_x_out, nbits_frac_x_out)'low); - SIGNAL yout : sfixed(sproto(nbits_y_out, nbits_frac_y_out)'high downto sproto(nbits_y_out, nbits_frac_y_out)'low); - SIGNAL zout : sfixed(sproto(nbits_z_out, nbits_frac_z_out)'high downto sproto(nbits_z_out, nbits_frac_z_out)'low); - SIGNAL vld_out : std_logic; - - -------------------------------------------------------------------- - --Functions - -------------------------------------------------------------------- - type real_vector_t is array (natural range <>) of real; - function mean(x : real_vector_t; len : integer) return real is - variable xm : real := 0.0; - begin - for i in 0 to len-1 loop - xm := xm + x(i); - end loop; - - return xm / real(len); - end mean; - - -------------------------------------------------------------------- - function var(x : real_vector_t; len : integer) return real is - variable xv, xm, xp : real := 0.0; - begin - xm := mean(x, len); - - for i in 0 to len-1 loop - xp := x(i) - xm; - xv := xv + xp*xp; - end loop; - - return xv / real(len); - end var; - - -------------------------------------------------------------------- - function stddev(x : real_vector_t; len : integer) return real is - variable xv, xs : real := 0.0; - begin - xv := var(x, len); - if xv > 0.0 then - xs := sqrt(xv); - end if; - - return xs; - end stddev; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cordic_pipe_top - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - z_range => pi, - gain_corr_mode => gain_mode_disabled, - nstages => 18, - nbits_x_in => nbits_x_in, - nbits_frac_x_in => nbits_frac_x_in, - nbits_y_in => nbits_y_in, - nbits_frac_y_in => nbits_frac_y_in, - nbits_z_in => nbits_z_in, - nbits_frac_z_in => nbits_frac_z_in, - nbits_x_out => nbits_x_out, - nbits_frac_x_out => nbits_frac_x_out, - nbits_y_out => nbits_y_out, - nbits_frac_y_out => nbits_frac_y_out, - nbits_z_out => nbits_z_out, - nbits_frac_z_out => nbits_frac_z_out - ) - PORT MAP - ( - rst => rst, - clk => clk, - vld_in => vld_in, - xin => xin, - yin => yin, - zin => zin, - xout => xout, - yout => yout, - zout => zout, - vld_out => vld_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1); - variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real; - variable argx, argy, argz : real := 0.0; - variable phi, dphi : real := 0.0; - file RESULT: text open write_mode is "STD_OUTPUT"; - file RESULT_X: text open write_mode is "x.txt"; - file RESULT_Y: text open write_mode is "y.txt"; - file RESULT_Z: text open write_mode is "z.txt"; - variable L: line; - variable j : integer := 0; - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - rst <= '0'; - - wait for 2*PERIOD; - - for i in 0 to arctan_tbl'length-1 loop - fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i))); - end loop; - for i in 0 to gain_tbl'length-1 loop - fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i))); - end loop; - fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI)); - fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0))); - fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0))); - - ------------------------------------------- - -- 1 - argx := 1.0; - argy := 0.0; - argz := -pi/4.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 2 - argx := 1.0; - argy := 0.0; - argz := pi/2.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 3 - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := pi/2.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 4 - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := -pi/4.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 5 - argx := 1.0; - argy := 1.0; - argz := 0.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 6 - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := 0.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 7 - argx := -sqrt2_inv; - argy := sqrt2_inv; - argz := 0.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 8 - argx := -sqrt2_inv; - argy := -sqrt2_inv; - argz := 0.0; - - wait until rising_edge(clk); - xin <= to_sfixed(argx, xin, fixed_wrap, fixed_round); - yin <= to_sfixed(argy, yin, fixed_wrap, fixed_round); - zin <= to_sfixed(argz, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT, L,"--------------------------------\n"); --- fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- Place stimulus here - wait for 10*PERIOD; - wait until rising_edge(clk) and vld_out = '0'; - j := 0; - dphi := 2.0*pi/real(num_steps_per_cycle); - for k in 0 to num_cycles-1 loop - phi := -pi; - for i in 0 to num_steps_per_cycle-1 loop - xin <= to_sfixed(1.0, xin); - yin <= to_sfixed(0.0, yin); - zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round); - - vld_in <= '1'; - wait until rising_edge(clk); - vld_in <= '0'; - - wait until rising_edge(clk) and vld_out = '1'; - - fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout))); - fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout))); - fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout))); - --- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi))); --- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi))); --- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0)); - - xerr(j) := to_real(xout) - cos(phi); - yerr(j) := to_real(yout) - sin(phi); - zerr(j) := to_real(zout); - j := j + 1; - phi := (phi + dphi); - end loop; - end loop; - xmean := mean(xerr, j); - ymean := mean(yerr, j); - zmean := mean(zerr, j); - xvar := var(xerr, j); - yvar := var(yerr, j); - zvar := var(zerr, j); - xstd := stddev(xerr, j); - ystd := stddev(yerr, j); - zstd := stddev(zerr, j); - fprint(RESULT, L,"------------------------------------------\n"); - fprint(RESULT, L,"Results: \n"); - fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean)); - fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean)); - fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean)); - fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar)); - fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar)); - fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar)); - fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd)); - fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd)); - fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd)); - fprint(RESULT, L,"------------------------------------------\n"); - - assert false report "Test finished" severity error; - wait; - END PROCESS; - -END; diff --git a/lib/radio/cordic/src/tb_cordic_top.vhd b/lib/radio/cordic/src/tb_cordic_top.vhd deleted file mode 100644 index ff75043..0000000 --- a/lib/radio/cordic/src/tb_cordic_top.vhd +++ /dev/null @@ -1,649 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 10/02/2005 --- Design Name: cordic_top --- Module Name: tb_cordic_top.vhd --- Project Name: cordic --- Target Device: --- Tool versions: --- Description: --- --- VHDL Test Bench Created by ISE for module: cordic_top --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --- Notes: --- This testbench has been automatically generated using types std_logic and --- std_logic_vector for the ports of the unit under test. Xilinx recommends --- that these types always be used for the top-level I/O of a design in order --- to guarantee that the testbench will bind correctly to the post-implementation --- simulation model. --------------------------------------------------------------------------------- --- Results:In 16i2 and Out 16i0 ------------------------------- --- xmean = -3.051757808671257e-7 --- ymean = 1.525878906192144e-6 --- zmean = 0.0 --- xvar = 7.723598281502283e-10 --- yvar = 8.539443970667266e-10 --- zvar = 0.0 --- xstd = 2.779136247380161e-5 --- ystd = 2.922232703031582e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 16i2 and Out 16i1 ------------------------------- --- xmean = 6.103515628828741e-7 --- ymean = -1.220703125057855e-6 --- zmean = 0.0 --- xvar = 9.76293486677989e-10 --- yvar = 7.934037490259732e-10 --- zvar = 0.0 --- xstd = 3.124569549038697e-5 --- ystd = 2.816742354256017e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 16i2 and Out 16i2 ------------------------------- --- xmean = 2.441406250382875e-6 --- ymean = -1.220703125057855e-6 --- zmean = 0.0 --- xvar = 2.126680036682826e-9 --- yvar = 2.117107754473399e-9 --- zvar = 0.0 --- xstd = 4.611594124251206e-5 --- ystd = 4.601203923402438e-5 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i0 ------------------------------- --- xmean = -9.312842871812748e-12 --- ymean = -5.78558739545293e-17 --- zmean = 0.0 --- xvar = 1.671709854744817e-19 --- yvar = 1.790442305004033e-19 --- zvar = 0.0 --- xstd = 4.088654857951228e-10 --- ystd = 4.231361843430591e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i1 ------------------------------- --- xmean = 9.313608620496825e-12 --- ymean = 9.31316789028083e-12 --- zmean = 0.0 --- xvar = 1.876480788588237e-19 --- yvar = 2.238344116260579e-19 --- zvar = 0.0 --- xstd = 4.331836548841885e-10 --- ystd = 4.731114156581492e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 32i2 and Out 32i2 ------------------------------- --- xmean = -3.72525201102771e-11 --- ymean = -5.78558739545293e-17 --- zmean = 0.0 --- xvar = 5.458335981037092e-19 --- yvar = 5.704280631341228e-19 --- zvar = 0.0 --- xstd = 7.388055211648797e-10 --- ystd = 7.552668820583376e-10 --- zstd = 0.0 --- ------------------------------- --- Results:In 64i2 and Out 64i0 ------------------------------- --- xmean = 3.45418680637588e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205267218835516e-16 --- xvar = 5.54111959258452e-28 --- yvar = 5.549496221074054e-28 --- zvar = 7.916891206490056e-29 --- xstd = 2.353958281827551e-14 --- ystd = 2.355736874329146e-14 --- zstd = 8.897691389619023e-15 --- ------------------------------- --- Results:In 64i2 and Out 64i1 ------------------------------- --- xmean = 3.45418680637588e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205267218835516e-16 --- xvar = 5.541120861185077e-28 --- yvar = 5.549497432144743e-28 --- zvar = 7.916856202525234e-29 --- xstd = 2.353958551288674e-14 --- ystd = 2.355737131376237e-14 --- zstd = 8.897671719346156e-15 --- ------------------------------- --- Results:In 64i2 and Out 64i2 ------------------------------- --- xmean = 3.343164503913365e-17 --- ymean = 3.859475130978118e-17 --- zmean = 2.205223850748616e-16 --- xvar = 5.540559656182732e-28 --- yvar = 5.549495010008071e-28 --- zvar = 7.916821581863743e-29 --- xstd = 2.353839343749427e-14 --- ystd = 2.355736617283025e-14 --- zstd = 8.897652264425568e-15 --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cordic_top IS - Generic ( - nbits : integer := 32; - nbits_frac : integer := 30; - nbits_out : integer := 32; - nbits_frac_out : integer := 31 - ); -END tb_cordic_top; - -ARCHITECTURE behavior OF tb_cordic_top IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cordic_top - GENERIC ( - nbits : integer; - nbits_frac : integer; - nbits_out : integer; - nbits_frac_out : integer - ); - PORT( - rst : IN std_logic; - clk : IN std_logic; - ce : in std_logic; - xin : IN sfixed; - yin : IN sfixed; - zin : IN sfixed; - xout : OUT sfixed; - yout : OUT sfixed; - zout : OUT sfixed; - ready : OUT std_logic; - valid : out std_logic; - cordic_mode : in cordic_mode_t - ); - END COMPONENT; - - --Constants - constant num_cycles : integer := 5; - constant num_steps_per_cycle : integer := 100; - constant PERIOD : time := 10 ns; - - constant one_sfix : sfixed := to_sfixed(1.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); - constant zero_sfix : sfixed := to_sfixed(0.0, sproto(nbits, nbits_frac)'high, sproto(nbits, nbits_frac)'low); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL rst : std_logic := '1'; - SIGNAL ce : std_logic := '0'; - SIGNAL xin, yin, zin : sfixed(sproto(nbits, nbits_frac)'high downto sproto(nbits, nbits_frac)'low) := zero_sfix; - - --Outputs - SIGNAL xout, yout, zout : sfixed(sproto(nbits_out, nbits_frac_out)'high downto sproto(nbits_out, nbits_frac_out)'low); - SIGNAL valid, ready : std_logic; - SIGNAL cordic_mode : cordic_mode_t := cordic_mode_vector; - - - -------------------------------------------------------------------- - --Functions - -------------------------------------------------------------------- - type real_vector_t is array (natural range <>) of real; - function mean(x : real_vector_t; len : integer) return real is - variable xm : real := 0.0; - begin - for i in 0 to len-1 loop - xm := xm + x(i); - end loop; - - return xm / real(len); - end mean; - - -------------------------------------------------------------------- - function var(x : real_vector_t; len : integer) return real is - variable xv, xm, xp : real := 0.0; - begin - xm := mean(x, len); - - for i in 0 to len-1 loop - xp := x(i) - xm; - xv := xv + xp*xp; - end loop; - - return xv / real(len); - end var; - - -------------------------------------------------------------------- - function stddev(x : real_vector_t; len : integer) return real is - variable xv, xs : real := 0.0; - begin - xv := var(x, len); - if xv > 0.0 then - xs := sqrt(xv); - end if; - - return xs; - end stddev; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cordic_top - GENERIC MAP ( - nbits => nbits, - nbits_frac => nbits_frac, - nbits_out => nbits_out, - nbits_frac_out => nbits_frac_out - ) - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - xin => xin, - yin => yin, - zin => zin, - xout => xout, - yout => yout, - zout => zout, - ready => ready, - valid => valid, - cordic_mode => cordic_mode - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - variable xerr, yerr, zerr : real_vector_t (0 to num_steps_per_cycle*num_cycles-1); - variable xvar, xstd, xmean, yvar, ystd, ymean, zvar, zstd, zmean : real; - variable argx, argy, argz : real := 0.0; - variable phi, dphi : real := 0.0; - file RESULT: text open write_mode is "STD_OUTPUT"; - file RESULT_X: text open write_mode is "x.txt"; - file RESULT_Y: text open write_mode is "y.txt"; - file RESULT_Z: text open write_mode is "z.txt"; - variable L: line; - variable j : integer := 0; - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - rst <= '0'; - - wait for 2*PERIOD; - - for i in 0 to arctan_tbl'length-1 loop - fprint(RESULT, L,"coeff arctan (%d) = %s\n", fo(i), REAL'image(arctan_tbl(i))); - end loop; - for i in 0 to gain_tbl'length-1 loop - fprint(RESULT, L,"coeff gain (%d) = %s\n", fo(i), REAL'image(gain_tbl(i))); - end loop; - fprint(RESULT, L,"Pi = %s\n", REAL'image(MATH_PI)); - fprint(RESULT, L,"sqrt(2) = %s\n", REAL'image(SQRT(2.0))); - fprint(RESULT, L,"1/sqrt(2) = %s\n", REAL'image(1.0/SQRT(2.0))); - - ------------------------------------------- - -- 1 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_rotate; - argx := 1.0; - argy := 0.0; - argz := -pi/4.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 2 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_rotate; - argx := 1.0; - argy := 0.0; - argz := pi/2.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 3 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_rotate; - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := pi/2.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 4 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_rotate; - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := -pi/4.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*[X0*cos(Z0) - Y0*sin(Z0)]\n"); - fprint(RESULT, L,"Yn = An*[Y0*cos(Z0) + X0*sin(Z0)]\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 5 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_vector; - argx := 1.0; - argy := 1.0; - argz := 0.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 6 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_vector; - argx := sqrt2_inv; - argy := -sqrt2_inv; - argz := 0.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 7 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_vector; - argx := -sqrt2_inv; - argy := sqrt2_inv; - argz := 0.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- 8 - wait until rising_edge(clk) and ready = '1'; - - cordic_mode <= cordic_mode_vector; - argx := -sqrt2_inv; - argy := -sqrt2_inv; - argz := 0.0; - - xin <= to_sfixed(argx, xin); - yin <= to_sfixed(argy, yin); - zin <= to_sfixed(argz, zin); - - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT, L,"--------------------------------\n"); - fprint(RESULT, L,"%s\n", cordic_mode_t'image(cordic_mode)); - fprint(RESULT, L,"Xn = An*sqrt(X0^2 + Y0^2)\n"); - fprint(RESULT, L,"Zn = Z0 + arctan(Y0/X0)\n"); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"X0 = %s\n", REAL'image(to_real(xin))); - fprint(RESULT, L,"Y0 = %s\n", REAL'image(to_real(yin))); - fprint(RESULT, L,"Z0 = %s\n", REAL'image(to_real(zin))); - fprint(RESULT, L,"\n"); - fprint(RESULT, L,"Xn = %s\n", REAL'image(to_real(xout))); - fprint(RESULT, L,"Yn = %s\n", REAL'image(to_real(yout))); - fprint(RESULT, L,"Zn = %s\n", REAL'image(to_real(zout))); - fprint(RESULT, L,"\n"); - - ------------------------------------------- - -- Place stimulus here - wait for 10*PERIOD; - j := 0; - cordic_mode <= cordic_mode_rotate; - dphi := 2.0*pi/real(num_steps_per_cycle); - for k in 0 to num_cycles-1 loop - phi := -pi; - for i in 0 to num_steps_per_cycle-1 loop - xin <= one_sfix; - yin <= zero_sfix; - zin <= to_sfixed(phi, zin, fixed_wrap, fixed_round); - - wait until rising_edge(clk) and ready = '1'; - ce <= '1'; - wait until rising_edge(clk); - ce <= '0'; - - wait until rising_edge(clk) and ready = '0'; - wait until rising_edge(clk) and valid = '1'; - - fprint(RESULT_X, L,"%s\n", REAL'image(to_real(xout))); - fprint(RESULT_Y, L,"%s\n", REAL'image(to_real(yout))); - fprint(RESULT_Z, L,"%s\n", REAL'image(to_real(zout))); - --- fprint(RESULT_X, L,"%s\n", REAL'image(cos(phi))); --- fprint(RESULT_Y, L,"%s\n", REAL'image(sin(phi))); --- fprint(RESULT_Z, L,"%s\n", REAL'image(0.0)); - - xerr(j) := to_real(xout) - cos(phi); - yerr(j) := to_real(yout) - sin(phi); - zerr(j) := to_real(zout); - j := j + 1; - phi := (phi + dphi); - end loop; - end loop; - xmean := mean(xerr, j); - ymean := mean(yerr, j); - zmean := mean(zerr, j); - xvar := var(xerr, j); - yvar := var(yerr, j); - zvar := var(zerr, j); - xstd := stddev(xerr, j); - ystd := stddev(yerr, j); - zstd := stddev(zerr, j); - fprint(RESULT, L,"------------------------------------------\n"); - fprint(RESULT, L,"Results: \n"); - fprint(RESULT, L,"xmean = %s\n", REAL'image(xmean)); - fprint(RESULT, L,"ymean = %s\n", REAL'image(ymean)); - fprint(RESULT, L,"zmean = %s\n", REAL'image(zmean)); - fprint(RESULT, L,"xvar = %s\n", REAL'image(xvar)); - fprint(RESULT, L,"yvar = %s\n", REAL'image(yvar)); - fprint(RESULT, L,"zvar = %s\n", REAL'image(zvar)); - fprint(RESULT, L,"xstd = %s\n", REAL'image(xstd)); - fprint(RESULT, L,"ystd = %s\n", REAL'image(ystd)); - fprint(RESULT, L,"zstd = %s\n", REAL'image(zstd)); - fprint(RESULT, L,"------------------------------------------\n"); - - assert false report "Test finished" severity error; - wait; - END PROCESS; - -END; diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo deleted file mode 100644 index 0a69c83..0000000 --- a/lib/radio/ddc/sim/tb_ddc.fdo +++ /dev/null @@ -1,34 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../../filter/src/filter_pkg.vhd" -vcom -explicit -93 "../../../filter/src/fir_pkg.vhd" -vcom -explicit -93 "../../../filter/src/fir_stage_sys.vhd" -vcom -explicit -93 "../../../filter/src/delay_line.vhd" -vcom -explicit -93 "../../../filter/src/fir_semi_parallel.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd" -vcom -explicit -93 "../../nco/src/mix_cordic.vhd" -vcom -explicit -93 "../../decimator/CIC/src/cic_i_pipe.vhd" -vcom -explicit -93 "../../decimator/CIC/src/cic_c_pipe.vhd" -vcom -explicit -93 "../../decimator/CIC/src/cic_decim_pipe.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../src/ddc.vhd" -vcom -explicit -93 "../src/tb_ddc.vhd" -vsim -t 1ps -lib work tb_ddc -do {tb_ddc.wdo} -view wave -view structure -view signals -run 1000us - diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo deleted file mode 100644 index ce7f996..0000000 --- a/lib/radio/ddc/sim/tb_ddc.wdo +++ /dev/null @@ -1,126 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_ddc/clk -add wave -noupdate -format Logic /tb_ddc/rst -add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst -add wave -noupdate -format Logic /tb_ddc/ddc_nco_en -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q -add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld -add wave -noupdate -format Logic /tb_ddc/ddc_din_vld -add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst -add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q -add wave -noupdate -format Logic /tb_ddc/fileout_enable -add wave -noupdate -divider DDC -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q -add wave -noupdate -format Logic /tb_ddc/uut/din_vld -add wave -noupdate -format Logic /tb_ddc/uut/dout_vld -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q -add wave -noupdate -format Logic /tb_ddc/ddc_din_vld -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f -add wave -noupdate -format Logic /tb_ddc/clk -add wave -noupdate -format Logic /tb_ddc/rst -add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst -add wave -noupdate -format Logic /tb_ddc/ddc_nco_en -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q -add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld -add wave -noupdate -format Logic /tb_ddc/ddc_din_vld -add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst -add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q -add wave -noupdate -format Logic /tb_ddc/fileout_enable -add wave -noupdate -divider DDC -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q -add wave -noupdate -format Logic /tb_ddc/uut/din_vld -add wave -noupdate -format Logic /tb_ddc/uut/dout_vld -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q -add wave -noupdate -format Logic /tb_ddc/ddc_din_vld -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f -add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f -add wave -noupdate -divider CFIR -add wave -noupdate -format Logic /tb_ddc/uut/cfir_write_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q -add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_start_q -add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_din_vld_q -add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i -add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q -add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_i -add wave -noupdate -format Logic /tb_ddc/uut/fifo_empty_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_din_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_vld_q -add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_i -add wave -noupdate -format Logic /tb_ddc/uut/cfir_ready_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i -add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_h_data -add wave -noupdate -format Literal /tb_ddc/uut/cfir_h_addr -add wave -noupdate -format Logic /tb_ddc/uut/cfir_h_we -add wave -noupdate -format Logic /tb_ddc/uut/hclr_mode -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_addr -add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_we -add wave -noupdate -format Literal /tb_ddc/uut/cfir_i/coef_din -add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/cfir_i/coef_dout -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2590000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {98190775 ps} {100095223 ps} diff --git a/lib/radio/ddc/sim/tb_results.m b/lib/radio/ddc/sim/tb_results.m deleted file mode 100644 index c5111ec..0000000 --- a/lib/radio/ddc/sim/tb_results.m +++ /dev/null @@ -1,56 +0,0 @@ -% Read data -function tb_results() -fa = 100.0; -R = TEXTREAD('ratio.txt'); -N = TEXTREAD('nstages.txt');; -M = 1; -fa_dec = fa/R -N_pfir = 63; - -I_out_dec = TEXTREAD('i_dec.txt')'; -Q_out_dec = TEXTREAD('q_dec.txt')'; -I_out_fir = TEXTREAD('i_fir.txt')'; -Q_out_fir = TEXTREAD('q_fir.txt')'; - -N_dec = length(I_out_dec)-2*N_pfir; -N_fft_dec = N_dec -N_fft2_dec = N_fft_dec/2; - -N_fir = length(I_out_fir)-2*N_pfir; -N_fft_fir = N_fir -N_fft2_fir = N_fft_fir/2; - -fft_y2_fir = 2/N_fft_fir*abs(fft(I_out_fir(2*N_pfir+1:N_fft_fir+2*N_pfir).*hann(N_fft_fir)')); - -fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)')); - -f = (1:N_fft_dec)/N_fft_dec; -g = (R*M)^N; -H = abs(sin(pi*M.*f)./sin(pi.*f/R)).^N; - -[v, j] = max(fft_y2_dec(1:N_fft2_dec/2)) -H = v*H/H(j); - -wavwrite(0.5*[I_out_dec' Q_out_dec'], 16000, 16, 'iq.wav'); -wavwrite(0.5*[I_out_fir' Q_out_fir'], 8000, 16, 'iq_cfir.wav'); - -% Output -close all; - -plot(1:length(I_out_dec), I_out_dec, 1:length(Q_out_dec), Q_out_dec); grid; - -figure; -cic_plot(M, N, R); - -figure; -subplot(2,1,1) -plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(H(1:N_fft2_dec+1)), 'r-'); -legend('CIC', 'Droop'); -xlabel('MHz'); -grid; -subplot(2,1,2) -plot(fa/(2*R*N_fft_fir)*(0:N_fft2_fir),20*log10(fft_y2_fir(1:N_fft2_fir+1)), '-'); -legend('CFIR'); -xlabel('MHz'); -grid; - diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd deleted file mode 100644 index a70b50b..0000000 --- a/lib/radio/ddc/src/ddc.vhd +++ /dev/null @@ -1,508 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.utils_pkg.all; -use work.fixed_util_pkg.all; -use work.filter_pkg.all; -use work.fir_pkg.all; - -ENTITY ddc IS - Generic - ( - nbits_in : integer := 18; - nbits_in_frac : integer := 16; - nbits_out : integer := 18; - nbits_out_frac : integer := 16; - lo_nbits_phase : integer := 20; - lo_nbits_freq : integer := 20; - cic_nstages : integer := 3; - cic_ratio : integer := 64; - cic_scale_nbits : integer := 18 - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - lo_nco_rst : in std_logic; - lo_nco_en : in std_logic; - lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); - lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - din_vld : in std_logic; - dec_i : out sfixed; - dec_q : out sfixed; - dec_vld : out std_logic; - dout_i : out sfixed; - dout_q : out sfixed; - dout_vld : out std_logic - ); -END ddc; - -ARCHITECTURE behavior OF ddc IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix - GENERIC - ( - nbits_din : integer; - nbits_din_frac : integer; - nbits_dout : integer; - nbits_dout_frac : integer; - nbits_phase : integer; - nbits_freq : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - nco_rst : in std_logic; - nco_en : in std_logic; - freq_in : in unsigned(nbits_freq-1 downto 0); - phase_in : in unsigned(nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - dout_i : out sfixed; - dout_q : out sfixed; - din_vld : in std_logic; - dout_vld : out std_logic - ); - END COMPONENT; - - COMPONENT cic_decim_pipe - GENERIC - ( - nstages : integer; - ratio : integer; - scale_nbits : integer; - in_width : integer; - in_width_frac : integer; - out_width : integer; - out_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - COMPONENT fifo_sync - GENERIC - ( - addr_width : natural; - data_width : natural; - almost_full_thresh : integer; - almost_empty_thresh : integer - ); - PORT - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT fir_semi_parallel - GENERIC - ( - ntaps_per_stage : integer; - nstages : integer; - pipe_latency : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - h_addr : in natural range 0 to nstages*ntaps_per_stage-1; - h_we : in std_logic; - h_in : in sfixed; - din_vld : in std_logic; - din : in sfixed; - dout_vld : out std_logic; - rdy : out std_logic; - dout : out sfixed - ); - END COMPONENT; - - constant lo_nbits_in : integer := nbits_in; - constant lo_nbits_in_frac : integer := nbits_in_frac; - constant lo_nbits_out : integer := nbits_in; - constant lo_nbits_out_frac : integer := nbits_in_frac; - - constant cic_nbits_in : integer := lo_nbits_out; - constant cic_nbits_in_frac : integer := lo_nbits_out_frac; - constant cic_nbits_out : integer := nbits_out; - constant cic_nbits_out_frac : integer := nbits_out_frac; - - constant cfir_pipe_latency : integer := 5; - constant cfir_ntaps : integer := 63; - constant cfir_nstages : integer := 2; - constant cfir_nbits_in : integer := cic_nbits_out; - constant cfir_nbits_in_frac : integer := cic_nbits_out_frac; - constant cfir_nbits_out : integer := nbits_out; - constant cfir_nbits_out_frac : integer := nbits_out_frac; - constant cfir_nbits_stages : integer := cfir_nbits_in; - constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac; - - constant cfir_ntaps_per_stage : integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages; - - SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); - SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); - SIGNAL mix_dout_vld : std_logic; - - SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); - SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac)); - SIGNAL dec_dout_vld_i : std_logic; - SIGNAL dec_dout_vld_q : std_logic; - - SIGNAL cfir_h_data : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); - SIGNAL cfir_h_addr : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1; - SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL cfir_h_we : std_logic; - SIGNAL cfir_vld_i : std_logic; - SIGNAL cfir_vld_q : std_logic; - SIGNAL cfir_ready_i : std_logic; - SIGNAL cfir_ready_q : std_logic; - SIGNAL cfir_start_i : std_logic; - SIGNAL cfir_start_q : std_logic; - SIGNAL cfir_din_vld_i : std_logic; - SIGNAL cfir_din_vld_q : std_logic; - SIGNAL cfir_din_i : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac)); - SIGNAL cfir_din_q : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac)); - SIGNAL cfir_write_i : std_logic; - SIGNAL cfir_write_q : std_logic; - - SIGNAL fifo_empty_i : std_logic; - SIGNAL fifo_empty_q : std_logic; - SIGNAL fifo_full_i : std_logic; - SIGNAL fifo_full_q : std_logic; - SIGNAL fifo_din_i : unsigned(cfir_nbits_in-1 downto 0); - SIGNAL fifo_din_q : unsigned(cfir_nbits_in-1 downto 0); - SIGNAL fifo_dout_i : unsigned(cfir_nbits_in-1 downto 0); - SIGNAL fifo_dout_q : unsigned(cfir_nbits_in-1 downto 0); - - constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.40, 1.0); - - type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac)); - - function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is - variable res : h_mem_t; - begin - for i in 0 to ntaps-1 loop - res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round); - end loop; - - return res; - end to_h_mem; - - SIGNAL hclr_mode : std_logic; - CONSTANT h_mem : h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data); - -BEGIN - --- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note; - dec_vld <= dec_dout_vld_i and dec_dout_vld_q; - dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - - dout_vld <= cfir_vld_i and cfir_vld_q; - dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round); - --- cfir_start <= dec_dout_vld_i and dec_dout_vld_q; - - -- Instantiate the Unit Under Test (UUT) - inst_mixer: mix - GENERIC MAP - ( - nbits_din => lo_nbits_in, - nbits_din_frac => lo_nbits_in_frac, - nbits_dout => lo_nbits_out, - nbits_dout_frac => lo_nbits_out_frac, - nbits_phase => lo_nbits_phase, - nbits_freq => lo_nbits_freq - ) - PORT MAP - ( - rst => rst, - clk => clk, - nco_rst => lo_nco_rst, - nco_en => lo_nco_en, - freq_in => lo_freq_in, - phase_in => lo_phase_in, - din_i => din_i, - din_q => din_q, - dout_i => mix_dout_i, - dout_q => mix_dout_q, - din_vld => din_vld, - dout_vld => mix_dout_vld - ); - - inst_cic_decim_pipe_I : cic_decim_pipe - GENERIC MAP - ( - nstages => cic_nstages, - ratio => cic_ratio, - scale_nbits => cic_scale_nbits, - in_width => cic_nbits_in, - in_width_frac => cic_nbits_in_frac, - out_width => cic_nbits_out, - out_width_frac => cic_nbits_out_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => mix_dout_vld, - din => mix_dout_i, - dout => dec_dout_i, - vld_out => dec_dout_vld_i - ); - - inst_cic_decim_pipe_Q : cic_decim_pipe - GENERIC MAP - ( - nstages => cic_nstages, - ratio => cic_ratio, - scale_nbits => cic_scale_nbits, - in_width => cic_nbits_in, - in_width_frac => cic_nbits_in_frac, - out_width => cic_nbits_out, - out_width_frac => cic_nbits_out_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => mix_dout_vld, - din => mix_dout_q, - dout => dec_dout_q, - vld_out => dec_dout_vld_q - ); - - cfir_I : entity work.fir_semi_parallel - GENERIC MAP - ( - ntaps_per_stage => cfir_ntaps_per_stage, - nstages => cfir_nstages, - pipe_latency => cfir_pipe_latency, - nbits_in => cfir_nbits_in, - nbits_in_frac => cfir_nbits_in_frac, - nbits_stages => cfir_nbits_stages, - nbits_stages_frac => cfir_nbits_stages_frac, - nbits_out => cfir_nbits_out, - nbits_out_frac => cfir_nbits_out_frac - ) - PORT MAP - ( - rst => rst, - clk => clk, - h_addr => cfir_h_addr, - h_we => cfir_h_we, - h_in => cfir_h_data, - din_vld => cfir_din_vld_i, - din => cfir_din_i, - dout_vld => cfir_vld_i, - start => cfir_start_i, - rdy => cfir_ready_i, - dout => cfir_dout_i - ); - - cfir_Q : entity work.fir_semi_parallel - GENERIC MAP - ( - ntaps_per_stage => cfir_ntaps_per_stage, - nstages => cfir_nstages, - pipe_latency => cfir_pipe_latency, - nbits_in => cfir_nbits_in, - nbits_in_frac => cfir_nbits_in_frac, - nbits_stages => cfir_nbits_stages, - nbits_stages_frac => cfir_nbits_stages_frac, - nbits_out => cfir_nbits_out, - nbits_out_frac => cfir_nbits_out_frac - ) - PORT MAP - ( - rst => rst, - clk => clk, - h_addr => cfir_h_addr, - h_we => cfir_h_we, - h_in => cfir_h_data, - din_vld => cfir_din_vld_q, - din => cfir_din_q, - dout_vld => cfir_vld_q, - start => cfir_start_q, - rdy => cfir_ready_q, - dout => cfir_dout_q - ); - - cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i; - cfir_start_i <= fifo_empty_i and cfir_write_i; - - fifo_din_i <= to_unsigned(ufixed(dec_dout_i)); - cfir_din_i <= sfixed(fifo_dout_i); - --- cfir_din_vld_i <= dec_dout_vld_i; --- cfir_start_i <= dec_dout_vld_i; --- --- cfir_din_i <= dec_dout_i; - -inst_fifo_sync_i : fifo_sync - GENERIC MAP - ( - addr_width => 1, - data_width => cfir_nbits_in, - almost_full_thresh => 1, - almost_empty_thresh => 1 - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => dec_dout_vld_i, - re => cfir_write_i, - fifo_full => fifo_full_i, - fifo_empty => fifo_empty_i, - fifo_afull => open, - fifo_aempty => open, - data_w => fifo_din_i, - data_r => fifo_dout_i - ); - - cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q; - cfir_start_q <= fifo_empty_q and cfir_write_q; - - fifo_din_q <= to_unsigned(ufixed(dec_dout_q)); - cfir_din_q <= sfixed(fifo_dout_q); - --- cfir_din_vld_q <= dec_dout_vld_q; --- cfir_start_q <= dec_dout_vld_q; --- --- cfir_din_q <= dec_dout_q; - -inst_fifo_sync_q : fifo_sync - GENERIC MAP - ( - addr_width => 1, - data_width => cfir_nbits_in, - almost_full_thresh => 1, - almost_empty_thresh => 1 - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => dec_dout_vld_q, - re => cfir_write_q, - fifo_full => fifo_full_q, - fifo_empty => fifo_empty_q, - fifo_afull => open, - fifo_aempty => open, - data_w => fifo_din_q, - data_r => fifo_dout_q - ); - -cfir_write_logic_i: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cfir_write_i <= '0'; - elsif fifo_full_i = '1' then - cfir_write_i <= '1'; - elsif fifo_empty_i = '1' then - cfir_write_i <= '0'; - end if; - end if; - end process; - -cfir_write_logic_q: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cfir_write_q <= '0'; - elsif fifo_full_q = '1' then - cfir_write_q <= '1'; - elsif fifo_empty_q = '1' then - cfir_write_q <= '0'; - end if; - end if; - end process; - -coef_load_counter: - process(clk) - variable count : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1; - variable we : std_logic; - begin - if rising_edge(clk) then - cfir_h_addr <= count; - cfir_h_we <= we; - if rst = '1' then - we := '1'; - hclr_mode <= '1'; - count := 0; - else - if hclr_mode = '1' then - cfir_h_data <= to_sfixed(0.0, cfir_h_data); - if count /= NextPowerOfTwo(cfir_ntaps)-1 then - we := '1'; - count := count + 1; - else - count := 0; - hclr_mode <= '0'; - end if; - else - cfir_h_data <= h_mem(count); - if count /= cfir_ntaps-1 then - we := '1'; - count := count + 1; - else - we := '0'; - end if; - end if; - end if; - end if; - end process; - - -END; diff --git a/lib/radio/ddc/src/syn_ddc.vhd b/lib/radio/ddc/src/syn_ddc.vhd deleted file mode 100644 index 914639a..0000000 --- a/lib/radio/ddc/src/syn_ddc.vhd +++ /dev/null @@ -1,143 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - - ENTITY syn_ddc IS - Generic - ( - nbits_in : integer := 16; - nbits_in_frac : integer := 14; - nbits_out : integer := 32; - nbits_out_frac : integer := 30; - lo_nbits_phase : integer := 20; - lo_nbits_freq : integer := 20; - cic_nstages : integer := 5; - cic_ratio : integer := 25; - cic_scale_nbits : integer := 22 - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - lo_nco_rst : in std_logic; - lo_nco_en : in std_logic; - lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); - lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); - din_i : in signed(nbits_in-1 downto 0); - din_q : in signed(nbits_in-1 downto 0); - dout_i : out signed(nbits_out-1 downto 0); - dout_q : out signed(nbits_out-1 downto 0); - din_vld : in std_logic; - dout_vld : out std_logic - ); - END syn_ddc; - -ARCHITECTURE behavior OF syn_ddc IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ddc - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - lo_nbits_phase : integer; - lo_nbits_freq : integer; - cic_nstages : integer; - cic_ratio : integer; - cic_scale_nbits : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - lo_nco_rst : in std_logic; - lo_nco_en : in std_logic; - lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); - lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); - din_vld : in std_logic; - din_i : in sfixed; - din_q : in sfixed; - dec_vld : out std_logic; - dec_i : out sfixed; - dec_q : out sfixed; - dout_vld : out std_logic; - dout_i : out sfixed; - dout_q : out sfixed - ); - END COMPONENT; - - --Outputs - SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - - SIGNAL dec_vld : std_logic; - SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - inst_ddc : ddc - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - lo_nbits_phase => lo_nbits_phase, - lo_nbits_freq => lo_nbits_freq, - cic_nstages => cic_nstages, - cic_ratio => cic_ratio, - cic_scale_nbits => cic_scale_nbits - ) - PORT MAP - ( - rst => rst, - clk => clk, - lo_nco_rst => lo_nco_rst, - lo_nco_en => lo_nco_en, - lo_freq_in => lo_freq_in, - lo_phase_in => lo_phase_in, - din_vld => din_vld, - din_i => ddc_din_i, - din_q => ddc_din_q, - dec_vld => dec_vld, - dec_i => ddc_dec_i, - dec_q => ddc_dec_q, - dout_vld => dout_vld, - dout_i => ddc_dout_i, - dout_q => ddc_dout_q - ); - - ddc_din_i <= sfixed(din_i); - ddc_din_q <= sfixed(din_q); - - dout_i <= signed(ddc_dout_i); - dout_q <= signed(ddc_dout_q); - -END; diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd deleted file mode 100644 index 37d6fca..0000000 --- a/lib/radio/ddc/src/tb_ddc.vhd +++ /dev/null @@ -1,395 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_ddc IS - Generic - ( - nbits_in : integer := 16; - nbits_in_frac : integer := 14; - nbits_out : integer := 32; - nbits_out_frac : integer := 30; - lo_nbits_phase : integer := 20; - lo_nbits_freq : integer := 20; - cic_nstages : integer := 5; - cic_ratio : integer := 25; - cic_scale_nbits : integer := 22; - rfgen_nbits_phase : integer := 20; - rfgen_nbits_freq : integer := 20 - ); -END tb_ddc; - -ARCHITECTURE behavior OF tb_ddc IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT ddc - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - lo_nbits_phase : integer; - lo_nbits_freq : integer; - cic_nstages : integer; - cic_ratio : integer; - cic_scale_nbits : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - lo_nco_rst : in std_logic; - lo_nco_en : in std_logic; - lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); - lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - din_vld : in std_logic; - dec_i : out sfixed; - dec_q : out sfixed; - dec_vld : out std_logic; - dout_i : out sfixed; - dout_q : out sfixed; - dout_vld : out std_logic - ); - END COMPONENT; - - -- Rf-Generator - COMPONENT mix - GENERIC - ( - nbits_din : integer; - nbits_din_frac : integer; - nbits_dout : integer; - nbits_dout_frac : integer; - nbits_phase : integer; - nbits_freq : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - nco_rst : in std_logic; - nco_en : in std_logic; - freq_in : in unsigned(nbits_freq-1 downto 0); - phase_in : in unsigned(nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - dout_i : out sfixed; - dout_q : out sfixed; - din_vld : in std_logic; - dout_vld : out std_logic - ); - END COMPONENT; - - --Constants - constant fa : REAL := 100.0E6; - constant frf1 : REAL := 33.99E6; - constant frf2 : REAL := 2.1E6; - constant frf3 : REAL := 19.01E6; - constant flo : REAL := 2.00E6; - constant PERIOD : time := 10 ns; - - SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq); - SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq); - SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq); - SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL rst : std_logic := '1'; - SIGNAL ddc_nco_rst : std_logic := '0'; - SIGNAL ddc_nco_en : std_logic := '0'; - SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0'); - SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0'); - - --Outputs - SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL ddc_din_vld : std_logic := '0'; - - SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dec_vld : std_logic; - - SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); - SIGNAL ddc_dout_vld : std_logic; - - SIGNAL rfgen_nco_rst : std_logic := '0'; - SIGNAL rfgen_nco_en : std_logic := '0'; - SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0'); - SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0'); - SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0'); - SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0'); - SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0'); - SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0'); - - --Outputs - signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac)); - signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen1_dout_vld : std_logic; - SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen2_dout_vld : std_logic; - SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); - SIGNAL rfgen3_dout_vld : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - - -- Debug - signal ddc_i_out_f : real; - signal ddc_q_out_f : real; - signal rfgen_i_out_f : real; - signal rfgen_q_out_f : real; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut : ddc - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - lo_nbits_phase => lo_nbits_phase, - lo_nbits_freq => lo_nbits_freq, - cic_nstages => cic_nstages, - cic_ratio => cic_ratio, - cic_scale_nbits => cic_scale_nbits - ) - PORT MAP - ( - rst => rst, - clk => clk, - lo_nco_rst => ddc_nco_rst, - lo_nco_en => ddc_nco_en, - lo_freq_in => ddc_freq_in, - lo_phase_in => ddc_phase_in, - din_i => ddc_din_i, - din_q => ddc_din_q, - din_vld => ddc_din_vld, - dec_i => ddc_dec_i, - dec_q => ddc_dec_q, - dec_vld => ddc_dec_vld, - dout_i => ddc_dout_i, - dout_q => ddc_dout_q, - dout_vld => ddc_dout_vld - ); - - rfgen1: mix - GENERIC MAP - ( - nbits_din => nbits_in, - nbits_din_frac => nbits_in_frac, - nbits_dout => nbits_in, - nbits_dout_frac => nbits_in_frac, - nbits_phase => rfgen_nbits_phase, - nbits_freq => rfgen_nbits_freq - ) - PORT MAP - ( - rst => rst, - clk => clk, - nco_rst => rfgen_nco_rst, - nco_en => rfgen_nco_en, - freq_in => rfgen1_freq_in, - phase_in => rfgen1_phase_in, - din_i => rfgen_din_i, - din_q => rfgen_din_q, - dout_i => rfgen1_dout_i, - dout_q => rfgen1_dout_q, - din_vld => '1', - dout_vld => rfgen1_dout_vld - ); - - rfgen2: mix - GENERIC MAP - ( - nbits_din => nbits_in, - nbits_din_frac => nbits_in_frac, - nbits_dout => nbits_in, - nbits_dout_frac => nbits_in_frac, - nbits_phase => rfgen_nbits_phase, - nbits_freq => rfgen_nbits_freq - ) - PORT MAP - ( - rst => rst, - clk => clk, - nco_rst => rfgen_nco_rst, - nco_en => rfgen_nco_en, - freq_in => rfgen2_freq_in, - phase_in => rfgen2_phase_in, - din_i => rfgen_din_i, - din_q => rfgen_din_q, - dout_i => rfgen2_dout_i, - dout_q => rfgen2_dout_q, - din_vld => '1', - dout_vld => rfgen2_dout_vld - ); - - rfgen3: mix - GENERIC MAP - ( - nbits_din => nbits_in, - nbits_din_frac => nbits_in_frac, - nbits_dout => nbits_in, - nbits_dout_frac => nbits_in_frac, - nbits_phase => rfgen_nbits_phase, - nbits_freq => rfgen_nbits_freq - ) - PORT MAP - ( - rst => rst, - clk => clk, - nco_rst => rfgen_nco_rst, - nco_en => rfgen_nco_en, - freq_in => rfgen3_freq_in, - phase_in => rfgen3_phase_in, - din_i => rfgen_din_i, - din_q => rfgen_din_q, - dout_i => rfgen3_dout_i, - dout_q => rfgen3_dout_q, - din_vld => '1', - dout_vld => rfgen3_dout_vld - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i); - rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q); - - ddc_din_i <= rfgen_dout_i; - ddc_din_q <= to_sfixed(0.0, ddc_din_q); - ddc_din_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld; - - ddc_i_out_f <= to_real(ddc_dout_i); - ddc_q_out_f <= to_real(ddc_dout_q); - - rfgen_i_out_f <= to_real(rfgen_dout_i); - rfgen_q_out_f <= to_real(rfgen_dout_q); - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - rst <= '0'; - - wait for 2*PERIOD; - ------------------------------------------- - -- Program gains - wait for 2*PERIOD; - wait until rising_edge(clk); - - -- start DDC - ddc_phase_in <= to_unsigned(0,lo_nbits_phase); - ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq); - wait until rising_edge(clk); - ddc_nco_en <= '1'; - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait; - END PROCESS; - - - rfgen_ctrl : PROCESS - - BEGIN - wait until rising_edge(clk) and rst = '0'; - rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq); - rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase); - rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq); - rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase); - rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq); - rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase); - wait until rising_edge(clk); - rfgen_nco_en <= '1'; - - - wait; - END PROCESS; - - tb_param : PROCESS - file RESULT_R: text open write_mode is "ratio.txt"; - file RESULT_N: text open write_mode is "nstages.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait until rising_edge(clk) and rst = '0'; - fprint(RESULT_R, L,"%s\n", natural'image(cic_ratio)); - fprint(RESULT_N, L,"%s\n", natural'image(cic_nstages)); - wait; - - END PROCESS; - - tb_fo : PROCESS(clk) - file RESULT_Ii: text open write_mode is "i_in.txt"; - file RESULT_Qi: text open write_mode is "q_in.txt"; - file RESULT_Ifir: text open write_mode is "i_fir.txt"; - file RESULT_Qfir: text open write_mode is "q_fir.txt"; - file RESULT_Idec: text open write_mode is "i_dec.txt"; - file RESULT_Qdec: text open write_mode is "q_dec.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) then - if fileout_enable = '1' then - if ddc_din_vld = '1' then - fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i))); - fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q))); - end if; - if ddc_dout_vld = '1' then - fprint(RESULT_Ifir, L,"%s\n", REAL'image(to_real(ddc_dout_i))); - fprint(RESULT_Qfir, L,"%s\n", REAL'image(to_real(ddc_dout_q))); - end if; - if ddc_dec_vld = '1' then - fprint(RESULT_Idec, L,"%s\n", REAL'image(to_real(ddc_dec_i))); - fprint(RESULT_Qdec, L,"%s\n", REAL'image(to_real(ddc_dec_q))); - end if; - end if; - end if; - END PROCESS; - -END; diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo deleted file mode 100644 index 40910c8..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo +++ /dev/null @@ -1,14 +0,0 @@ -vmap ieee_proposed ../../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/cic_c_pipe.vhd" -vcom -explicit -93 "../src/tb_cic_c_pipe.vhd" -vsim -t 1ps -lib work tb_cic_c_pipe -do {tb_cic_c_pipe.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo deleted file mode 100644 index 901e089..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo +++ /dev/null @@ -1,26 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cic_c_pipe/clk -add wave -noupdate -format Logic /tb_cic_c_pipe/srst -add wave -noupdate -format Logic /tb_cic_c_pipe/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/din -add wave -noupdate -format Literal /tb_cic_c_pipe/diff_delay -add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/dout -add wave -noupdate -format Logic /tb_cic_c_pipe/vld_out -add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/uut/word_pipe -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {250000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {500608 ps} diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo deleted file mode 100644 index b0525de..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo +++ /dev/null @@ -1,17 +0,0 @@ -vmap ieee_proposed ../../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/cic_i_pipe.vhd" -vcom -explicit -93 "../src/cic_c_pipe.vhd" -vcom -explicit -93 "../src/cic_decim_pipe.vhd" -vcom -explicit -93 "../src/tb_cic_decim_pipe.vhd" -vsim -t 1ps -lib work tb_cic_decim_pipe -do {tb_cic_decim_pipe.wdo} -view wave -view structure -view signals -run 140us diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo deleted file mode 100644 index 0296151..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo +++ /dev/null @@ -1,39 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cic_decim_pipe/clk -add wave -noupdate -format Logic /tb_cic_decim_pipe/srst -add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout -add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out -add wave -noupdate -divider Debug -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/xr -add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/yr -add wave -noupdate -divider -height 50 Trenn -add wave -noupdate -format Literal -radix decimal -expand /tb_cic_decim_pipe/uut/word_i_pipe -add wave -noupdate -format Literal /tb_cic_decim_pipe/uut/vld_i_pipe -add wave -noupdate -format Logic /tb_cic_decim_pipe/clk -add wave -noupdate -format Logic /tb_cic_decim_pipe/srst -add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout -add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out -add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/uut/word_c_pipe -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {34745455 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {147 us} diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo deleted file mode 100644 index b1c190a..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo +++ /dev/null @@ -1,14 +0,0 @@ -vmap ieee_proposed ../../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/cic_i_pipe.vhd" -vcom -explicit -93 "../src/tb_cic_i_pipe.vhd" -vsim -t 1ps -lib work tb_cic_i_pipe -do {tb_cic_i_pipe.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo deleted file mode 100644 index 140032c..0000000 --- a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo +++ /dev/null @@ -1,30 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cic_i_pipe/srst -add wave -noupdate -format Logic /tb_cic_i_pipe/clk -add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din -add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out -add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout -add wave -noupdate -format Logic /tb_cic_i_pipe/srst -add wave -noupdate -format Logic /tb_cic_i_pipe/clk -add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in -add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din -add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out -add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {373333 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {1050 ns} diff --git a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd deleted file mode 100644 index 41063f0..0000000 --- a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd +++ /dev/null @@ -1,104 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_pre - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cic_c_pipe is -Generic -( - max_diff_delay : integer := 1; - max_width : integer := 32; - max_width_frac : integer := 20 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - diff_delay : in natural range 1 to max_diff_delay; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic -); -end cic_c_pipe; - -architecture Behavioral of cic_c_pipe is - -subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); -type word_pipe_t is array (1 to max_diff_delay) of word_t; - -signal word_pipe : word_pipe_t; - ------------------------------------------------------------- -begin - ------------------------------------------------------------- -delay_pipe_proc: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then --- for i in 1 to max_diff_delay loop --- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0'); --- end loop; - elsif vld_in = '1' then - word_pipe(1) <= resize(din, word_pipe(1)); - for i in 2 to max_diff_delay loop - word_pipe(i) <= word_pipe(i-1); - end loop; - end if; - end if; - end process; - ------------------------------------------------------------- -comb_proc: - process(clk) - variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - - begin - if rising_edge(clk) then - vld_out <= '0'; - x0 := resize(din, x0); - x1 := word_pipe(diff_delay); - if rst = '1' then - dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0'); - elsif vld_in = '1' then - vld_out <= '1'; - dout <= resize(x0 - x1, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; - diff --git a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd deleted file mode 100644 index 139c81a..0000000 --- a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd +++ /dev/null @@ -1,203 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.utils_pkg.all; - -ENTITY cic_decim_pipe IS - Generic - ( - nstages : integer := 3; - diff_delay : integer := 1; - ratio : integer := 64; - scale_nbits : integer := 9; - in_width : integer := 32; - in_width_frac : integer := 20; - out_width : integer := 32; - out_width_frac : integer := 20 - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); -END cic_decim_pipe; - -ARCHITECTURE behavior OF cic_decim_pipe IS - - COMPONENT cic_i_pipe - GENERIC - ( - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - COMPONENT cic_c_pipe - GENERIC - ( - max_diff_delay : integer; - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - diff_delay : in natural range 1 to max_diff_delay; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages))); - - constant integ_nbits : natural := in_width + max_gain_bits; - constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac); - - constant comb_nbits : natural := out_width+1; - constant comb_nbits_frac : natural := out_width_frac+1; - - subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - type word_i_pipe_t is array (0 to nstages) of word_i_t; - - signal word_i_pipe : word_i_pipe_t; - signal vld_i_pipe : unsigned (0 to nstages); - signal vld_i : std_logic; - - subtype word_c_t is sfixed(shi(comb_nbits, comb_nbits_frac) downto slo(comb_nbits, comb_nbits_frac)); - type word_c_pipe_t is array (0 to nstages) of word_c_t; - - signal word_c_pipe : word_c_pipe_t; - signal vld_c_pipe : unsigned (0 to nstages); - signal vld_c : std_logic; - - signal resample_cnt : natural range 1 to ratio; - signal resample_vld : std_logic; - -BEGIN - - assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note; - assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note; - assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note; - - vld_i <= vld_i_pipe(nstages); - -input_scale: - process(clk) - variable x : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - variable xs : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - variable xsi : sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); - begin - if rising_edge(clk) then - x := resize(din, x); - xs := x sra scale_nbits; - word_i_pipe(0) <= xs; - vld_i_pipe(0) <= vld_in; - end if; - end process; - - gen_i_stages: - for i in 1 to nstages generate - begin - inst_cic_i_pipe: cic_i_pipe - GENERIC MAP - ( - max_width => integ_nbits, - max_width_frac => integ_nbits_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => vld_i_pipe(i-1), - din => word_i_pipe(i-1), - dout => word_i_pipe(i), - vld_out => vld_i_pipe(i) - ); - end generate; - - word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate); - vld_c_pipe(0) <= resample_vld; - vld_c <= vld_c_pipe(nstages); - - vld_out <= vld_c; - - gen_c_stages: - for i in 1 to nstages generate - begin - inst_cic_c_pipe: cic_c_pipe - GENERIC MAP - ( - max_diff_delay => diff_delay, - max_width => comb_nbits, - max_width_frac => comb_nbits_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => vld_c_pipe(i-1), - diff_delay => diff_delay, - din => word_c_pipe(i-1), - dout => word_c_pipe(i), - vld_out => vld_c_pipe(i) - ); - end generate; - -resampler_proc: - process(clk) - begin - if rising_edge(clk) then - resample_vld <= '0'; - if rst = '1' then - resample_cnt <= 1; - elsif vld_i = '1' then - if resample_cnt = ratio then - resample_vld <= '1'; - resample_cnt <= 1; - else - resample_cnt <= resample_cnt + 1; - end if ; - end if; - end if; - end process; - - dout <= resize(word_c_pipe(nstages), shi(out_width, out_width_frac), slo(out_width, out_width_frac)); - -END; diff --git a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd deleted file mode 100644 index 0880ca3..0000000 --- a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage_pre - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity cic_i_pipe is -Generic -( - max_width : integer := 32; - max_width_frac : integer := 20 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic -); -end cic_i_pipe; - -architecture Behavioral of cic_i_pipe is - -signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - ------------------------------------------------------------- -begin - - dout <= resize(accu, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); - ------------------------------------------------------------- -integ_proc: - process(clk) - variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - begin - if rising_edge(clk) then - vld_out <= '0'; - if rst = '1' then - accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0'); - elsif vld_in = '1' then - vld_out <= '1'; - x := resize(din, x); - accu <= resize(x + accu, accu); - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; - diff --git a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd deleted file mode 100644 index 70e3007..0000000 --- a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd +++ /dev/null @@ -1,98 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - -entity syn_cic_c_pipe is -Generic -( - max_diff_delay : integer := 2; - max_width : integer := 32; - max_width_frac : integer := 20 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - diff_delay : in natural range 1 to max_diff_delay; - din : in signed(max_width-1 downto 0); - dout : out signed(max_width-1 downto 0); - vld_out : out std_logic -); -end syn_cic_c_pipe; - -ARCHITECTURE behavior OF syn_cic_c_pipe IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cic_c_pipe - GENERIC - ( - max_diff_delay : integer; - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - diff_delay : in natural range 1 to max_diff_delay; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Inputs - SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - - --Outputs - SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cic_c_pipe - GENERIC MAP - ( - max_diff_delay => max_diff_delay, - max_width => max_width, - max_width_frac => max_width_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => vld_in, - diff_delay => diff_delay, - din => sdin, - dout => sdout, - vld_out => vld_out - ); - - sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); - dout <= signed(sdout); - -END; diff --git a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd deleted file mode 100644 index 52428ed..0000000 --- a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd +++ /dev/null @@ -1,92 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - -entity syn_cic_i_pipe is -Generic -( - max_width : integer := 32; - max_width_frac : integer := 20 -); -Port -( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in signed(max_width-1 downto 0); - dout : out signed(max_width-1 downto 0); - vld_out : out std_logic -); -end syn_cic_i_pipe; - -ARCHITECTURE behavior OF syn_cic_i_pipe IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cic_i_pipe - GENERIC - ( - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Inputs - SIGNAL sdin : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - - --Outputs - SIGNAL sdout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cic_i_pipe - GENERIC MAP - ( - max_width => max_width, - max_width_frac => max_width_frac - ) - PORT MAP - ( - clk => clk, - rst => rst, - vld_in => vld_in, - din => sdin, - dout => sdout, - vld_out => vld_out - ); - - sdin <= to_sfixed(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac)); - dout <= signed(sdout); - -END; diff --git a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd deleted file mode 100644 index d36268d..0000000 --- a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd +++ /dev/null @@ -1,136 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.PCK_FIO.all; -use work.fixed_util_pkg.all; - -ENTITY tb_cic_c_pipe IS - Generic - ( - max_width : integer := 32; - max_width_frac : integer := 20 - ); -END tb_cic_c_pipe; - -ARCHITECTURE behavior OF tb_cic_c_pipe IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cic_c_pipe - GENERIC - ( - max_diff_delay : integer; - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - diff_delay : in natural range 1 to max_diff_delay; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL vld_in : std_logic := '0'; - SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - SIGNAL diff_delay : natural := 1; - - --Outputs - SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - SIGNAL vld_out : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cic_c_pipe - GENERIC MAP - ( - max_diff_delay => 2, - max_width => max_width, - max_width_frac => max_width_frac - ) - PORT MAP - ( - clk => clk, - rst => srst, - vld_in => vld_in, - diff_delay => diff_delay, - din => din, - dout => dout, - vld_out => vld_out - ); - - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.0, din); - vld_in <= '1'; - - wait for 9*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(0.5, din); - - wait for 9*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(0.0, din); - - wait for 9*PERIOD; - wait until rising_edge(clk); - vld_in <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - -END; diff --git a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd deleted file mode 100644 index f6f1d91..0000000 --- a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd +++ /dev/null @@ -1,153 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.PCK_FIO.all; -use work.fixed_util_pkg.all; - -ENTITY tb_cic_decim_pipe IS - Generic - ( - nstages : integer := 3; - ratio : integer := 64; - scale_nbits : integer := 18; - in_width : integer := 18; - in_width_frac : integer := 16; - out_width : integer := 18; - out_width_frac : integer := 16 - ); -END tb_cic_decim_pipe; - -ARCHITECTURE behavior OF tb_cic_decim_pipe IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cic_decim_pipe - GENERIC - ( - nstages : integer; - ratio : integer; - scale_nbits : integer; - in_width : integer; - in_width_frac : integer; - out_width : integer; - out_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL vld_in : std_logic := '0'; - SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac)); - - --Outputs - SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac)); - SIGNAL vld_out : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - - signal XR, YR : real; - -BEGIN - - XR <= to_real(din); - YR <= to_real(dout); - - -- Instantiate the Unit Under Test (UUT) - uut : cic_decim_pipe - GENERIC MAP - ( - nstages => nstages, - ratio => ratio, - scale_nbits => scale_nbits, - in_width => in_width, - in_width_frac => in_width_frac, - out_width => out_width, - out_width_frac => out_width_frac - ) - PORT MAP - ( - clk => clk, - rst => srst, - vld_in => vld_in, - din => din, - dout => dout, - vld_out => vld_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.0, din); - vld_in <= '1'; - - wait for 49*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(0.5, din); - - wait for 4999*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(-0.5, din); - - wait for 99*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(0.0, din); - - wait for 499*PERIOD; - wait until rising_edge(clk); - vld_in <= '0'; - - wait; - END PROCESS; - -END; diff --git a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd deleted file mode 100644 index b3ae7d5..0000000 --- a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd +++ /dev/null @@ -1,126 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.PCK_FIO.all; -use work.fixed_util_pkg.all; - -ENTITY tb_cic_i_pipe IS - Generic - ( - max_width : integer := 32; - max_width_frac : integer := 20 - ); -END tb_cic_i_pipe; - -ARCHITECTURE behavior OF tb_cic_i_pipe IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT cic_i_pipe - GENERIC - ( - max_width : integer; - max_width_frac : integer - ); - PORT - ( - clk : in std_logic; - rst : in std_logic; - vld_in : in std_logic; - din : in sfixed; - dout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL vld_in : std_logic := '0'; - SIGNAL din : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - - --Outputs - SIGNAL dout : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac)); - SIGNAL vld_out : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: cic_i_pipe - GENERIC MAP - ( - max_width => max_width, - max_width_frac => max_width_frac - ) - PORT MAP - ( - clk => clk, - rst => srst, - vld_in => vld_in, - din => din, - dout => dout, - vld_out => vld_out - ); - - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.0, din); - vld_in <= '1'; - - wait for 9*PERIOD; - wait until rising_edge(clk); - - din <= to_sfixed(0.5, din); - - wait for 9*PERIOD; - wait until rising_edge(clk); - vld_in <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - -END; diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo deleted file mode 100644 index 78a7729..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.fdo +++ /dev/null @@ -1,15 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_cpx.vhd" -vcom -explicit -93 "../src/tb_mix_cpx.vhd" -vsim -t 1ps -lib work tb_mix_cpx -do {tb_mix_cpx.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo deleted file mode 100644 index c84c651..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.wdo +++ /dev/null @@ -1,42 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_cpx/clk -add wave -noupdate -format Logic /tb_mix_cpx/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_cpx/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_cpx/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_cpx/x_re -add wave -noupdate -format Literal /tb_mix_cpx/x_im -add wave -noupdate -format Literal /tb_mix_cpx/y_re -add wave -noupdate -format Literal /tb_mix_cpx/y_im -add wave -noupdate -format Literal /tb_mix_cpx/z_re -add wave -noupdate -format Literal /tb_mix_cpx/z_im -add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {90000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo deleted file mode 100644 index 0dbc45f..0000000 --- a/lib/radio/mix/sim/tb_mix_real.fdo +++ /dev/null @@ -1,15 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_real.vhd" -vcom -explicit -93 "../src/tb_mix_real.vhd" -vsim -t 1ps -lib work tb_mix_real -do {tb_mix_real.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo deleted file mode 100644 index 6643ce3..0000000 --- a/lib/radio/mix/sim/tb_mix_real.wdo +++ /dev/null @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_real/clk -add wave -noupdate -format Logic /tb_mix_real/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_real/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_real/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_real/x_re -add wave -noupdate -format Literal /tb_mix_real/y_re -add wave -noupdate -format Literal /tb_mix_real/y_im -add wave -noupdate -format Literal /tb_mix_real/z_re -add wave -noupdate -format Literal /tb_mix_real/z_im -add wave -noupdate -format Logic /tb_mix_real/fileout_enable -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {120000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo deleted file mode 100644 index 2450220..0000000 --- a/lib/radio/mix/sim/tb_undc_real.fdo +++ /dev/null @@ -1,15 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/undc_real.vhd" -vcom -explicit -93 "../src/tb_undc_real.vhd" -vsim -t 1ps -lib work tb_undc_real -do {tb_undc_real.wdo} -view wave -view structure -view signals -run 500us diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo deleted file mode 100644 index f965905..0000000 --- a/lib/radio/mix/sim/tb_undc_real.wdo +++ /dev/null @@ -1,38 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_undc_real/clk -add wave -noupdate -format Logic /tb_undc_real/srst -add wave -noupdate -format Logic /tb_undc_real/din_valid -add wave -noupdate -format Logic /tb_undc_real/kin_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out -add wave -noupdate -format Logic /tb_undc_real/dout_valid -add wave -noupdate -format Literal /tb_undc_real/k -add wave -noupdate -format Literal /tb_undc_real/x -add wave -noupdate -format Literal /tb_undc_real/y -add wave -noupdate -format Literal /tb_undc_real/dc -add wave -noupdate -divider UUT -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {97905405 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {157500 ns} diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd deleted file mode 100644 index 3df161e..0000000 --- a/lib/radio/mix/src/mix_cpx.vhd +++ /dev/null @@ -1,171 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_cpx is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed -); -end mix_cpx; - -architecture Behavioral of mix_cpx is -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - x_im <= to_sfixed(0, x_im); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - end if; - end if; - end if; - else - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im) - variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - re_right := resize(x_im * y_im, re_right); - im_left := resize(x_re * y_im, im_left); - im_right := resize(x_im * y_re, im_right); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_re_right <= to_sfixed(0, p_re_right); - p_im_left <= to_sfixed(0, p_im_left); - p_im_right <= to_sfixed(0, p_im_right); - p_valid <= '0'; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, saturating, rounding); - sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, saturating, rounding); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_out <= to_sfixed(0, re); - z_im_out <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_out <= sum_re; - z_im_out <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_out <= re; - z_im_out <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd deleted file mode 100644 index 37e96de..0000000 --- a/lib/radio/mix/src/mix_real.vhd +++ /dev/null @@ -1,160 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_real is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed -); -end mix_real; - -architecture Behavioral of mix_real is - -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - end if; - end if; - end if; - else - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im) - variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - im_left := resize(x_re * y_im, im_left); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_im_left <= to_sfixed(0, p_im_left); - p_valid <= '0'; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left, nbits_scale_z), re, saturating, rounding); - sum_im := resize(scalb(p_im_left, nbits_scale_z), im, saturating, rounding); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_dout <= to_sfixed(0, re); - z_im_dout <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_dout <= sum_re; - z_im_dout <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_dout <= re; - z_im_dout <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd deleted file mode 100644 index 5eac130..0000000 --- a/lib/radio/mix/src/tb_mix_cpx.vhd +++ /dev/null @@ -1,211 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_cpx IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate - ); -END tb_mix_cpx; - -ARCHITECTURE behavior OF tb_mix_cpx IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_cpx - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : fixed_round_style_type; - saturating : fixed_overflow_style_type - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL x_im : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_cpx - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_in => x_re_in, - x_im_in => x_im_in, - y_re_in => y_re_in, - y_im_in => y_im_in, - out_valid => out_valid, - z_re_out => z_re_out, - z_im_out => z_im_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.5, x_re_in); - x_im_in <= to_sfixed(0.5, x_im_in); - y_re_in <= to_sfixed(0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.3, x_re_in); - x_im_in <= to_sfixed(0.0, x_im_in); - y_re_in <= to_sfixed(-0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.0, x_re_in); - x_im_in <= to_sfixed(-0.7071, x_im_in); - y_re_in <= to_sfixed(0.0, y_re_in); - y_im_in <= to_sfixed(-0.7071, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_in); - x_im <= to_real(x_im_in); - y_re <= to_real(y_re_in); - y_im <= to_real(y_im_in); - z_re <= to_real(z_re_out); - z_im <= to_real(z_im_out); - -END; diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd deleted file mode 100644 index 8f0ce40..0000000 --- a/lib/radio/mix/src/tb_mix_real.vhd +++ /dev/null @@ -1,200 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_real IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate - ); -END tb_mix_real; - -ARCHITECTURE behavior OF tb_mix_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_real - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : fixed_round_style_type; - saturating : fixed_overflow_style_type - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_real - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_din => x_re_din, - y_re_din => y_re_din, - y_im_din => y_im_din, - out_valid => out_valid, - z_re_dout => z_re_dout, - z_im_dout => z_im_dout - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.5, x_re_din); - y_re_din <= to_sfixed(0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.3, x_re_din); - y_re_din <= to_sfixed(-0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.0, x_re_din); - y_re_din <= to_sfixed(0.0, y_re_din); - y_im_din <= to_sfixed(-0.7071, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_din); - y_re <= to_real(y_re_din); - y_im <= to_real(y_im_din); - z_re <= to_real(z_re_dout); - z_im <= to_real(z_im_dout); - -END; diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd deleted file mode 100644 index 3fc872b..0000000 --- a/lib/radio/mix/src/tb_undc_real.vhd +++ /dev/null @@ -1,161 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_undc_real IS - Generic ( - nbits_data : integer := 24; - nbits_data_frac : integer := 24; - nbits_k : integer := 24; - nbits_k_frac : integer := 24; - has_in_reg : boolean := true; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate - ); -END tb_undc_real; - -ARCHITECTURE behavior OF tb_undc_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT undc_real - Generic - ( - nbits_data : integer; - nbits_data_frac : integer; - nbits_k : integer; - nbits_k_frac : integer; - has_in_reg : boolean; - rounding : fixed_round_style_type; - saturating : fixed_overflow_style_type - ); - Port - ( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL din_valid : std_logic := '0'; - SIGNAL kin_valid : std_logic := '0'; - SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); - - --Outputs - SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dout_valid : std_logic; - - SIGNAL k : real := 0.0; - SIGNAL x : real := 0.0; - SIGNAL y : real := 0.0; - SIGNAL dc : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: undc_real - GENERIC MAP - ( - nbits_data => nbits_data, - nbits_data_frac => nbits_data_frac, - nbits_k => nbits_k, - nbits_k_frac => nbits_k_frac, - has_in_reg => has_in_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - din_valid => din_valid, - din => din, - kin_valid => kin_valid, - kin => kin, - dout_valid => dout_valid, - dout => dout, - dc_out => dc_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - -- Load k - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - kin <= to_sfixed(0.0005, kin); - kin_valid <= '1'; - wait until rising_edge(clk); - kin_valid <= '1'; - ------------------------------------------ - -- Process - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.5, din); - din_valid <= '1'; - wait until rising_edge(clk); - din_valid <= '1'; - wait for 5*PERIOD; - - wait for 200*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - k <= to_real(kin); - x <= to_real(din); - y <= to_real(dout); - dc <= to_real(dc_out); - -END; diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd deleted file mode 100644 index e4a3bba..0000000 --- a/lib/radio/mix/src/undc_real.vhd +++ /dev/null @@ -1,143 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -use work.fixed_util_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity undc_real is -Generic -( - nbits_data : integer := 12; - nbits_data_frac : integer := 12; - nbits_k : integer := 12; - nbits_k_frac : integer := 12; - has_in_reg : boolean := false; - rounding : fixed_round_style_type := fixed_round; - saturating : fixed_overflow_style_type := fixed_saturate -); -Port -( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed -); -end undc_real; - -architecture Behavioral of undc_real is - -constant nbits_internal : integer := nbits_data + nbits_data; -constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac; - -signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); -signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); -signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); - -begin - -dout <= resize(y, sproto(nbits_data, nbits_data_frac), saturating, rounding); -dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), fixed_wrap, fixed_truncate); - ------------------------------------------------------------- - proc_din_reg: process(clk, din_valid, din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x <= to_sfixed(0, x); - else - if din_valid = '1' then - x <= din; - end if; - end if; - end if; - else - x <= din; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, din_valid) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - dout_valid <= '0'; - else - dout_valid <= din_valid; - end if; - end if; - else - dout_valid <= din_valid; - end if; - end process; - ------------------------------------------------------------- - proc_kin_reg: process(clk, kin_valid, kin) - begin - if rising_edge(clk) then - if srst = '1' then - k <= to_sfixed(0, k); - else - if kin_valid = '1' then - k <= kin; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_y: process(clk, x, dc) - begin - y <= resize(x - dc, y, fixed_wrap, fixed_truncate); - if rising_edge(clk) then - if srst = '1' then - y1 <= to_sfixed(0, y1); - y2 <= to_sfixed(0, y2); - dc <= to_sfixed(0, dc); - else - y1 <= y; - y2 <= resize(y1 * k, y2, fixed_wrap, fixed_truncate); - dc <= resize(y2 + dc, dc, fixed_wrap, fixed_truncate); - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/sim/tb_mix_cordic.fdo b/lib/radio/nco/sim/tb_mix_cordic.fdo deleted file mode 100644 index 3bd3ff4..0000000 --- a/lib/radio/nco/sim/tb_mix_cordic.fdo +++ /dev/null @@ -1,19 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd" -vcom -explicit -93 "../src/mix_cordic.vhd" -vcom -explicit -93 "../src/tb_mix_cordic.vhd" -vsim -t 1ps -lib work tb_mix -do {tb_mix_cordic.wdo} -view wave -view structure -view signals -run 400us diff --git a/lib/radio/nco/sim/tb_mix_cordic.wdo b/lib/radio/nco/sim/tb_mix_cordic.wdo deleted file mode 100644 index dc928bd..0000000 --- a/lib/radio/nco/sim/tb_mix_cordic.wdo +++ /dev/null @@ -1,42 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix/clk -add wave -noupdate -format Logic /tb_mix/srst -add wave -noupdate -format Logic /tb_mix/clk -add wave -noupdate -format Logic /tb_mix/srst -add wave -noupdate -format Logic /tb_mix/mix_nco_rst -add wave -noupdate -format Logic /tb_mix/mix_nco_en -add wave -noupdate -format Literal /tb_mix/mix_freq_in -add wave -noupdate -format Literal /tb_mix/mix_phase_in -add wave -noupdate -format Literal /tb_mix/mix_din_i -add wave -noupdate -format Literal /tb_mix/mix_din_q -add wave -noupdate -format Literal /tb_mix/mix_dout_i -add wave -noupdate -format Literal /tb_mix/mix_dout_q -add wave -noupdate -format Logic /tb_mix/mix_dout_vld -add wave -noupdate -format Logic /tb_mix/mix_din_vld -add wave -noupdate -format Logic /tb_mix/rfgen_nco_rst -add wave -noupdate -format Logic /tb_mix/rfgen_nco_en -add wave -noupdate -format Literal /tb_mix/rfgen_freq_in -add wave -noupdate -format Literal /tb_mix/rfgen_phase_in -add wave -noupdate -format Literal /tb_mix/rfgen_din_i -add wave -noupdate -format Literal /tb_mix/rfgen_din_q -add wave -noupdate -format Literal /tb_mix/rfgen_dout_i -add wave -noupdate -format Literal /tb_mix/rfgen_dout_q -add wave -noupdate -format Logic /tb_mix/rfgen_dout_vld -add wave -noupdate -format Logic /tb_mix/fileout_enable -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {249834550 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {146645950 ps} {228944950 ps} diff --git a/lib/radio/nco/sim/tb_mix_results.m b/lib/radio/nco/sim/tb_mix_results.m deleted file mode 100644 index 5997fea..0000000 --- a/lib/radio/nco/sim/tb_mix_results.m +++ /dev/null @@ -1,90 +0,0 @@ -% Read data -function tb_mix_results() -fa = 100.0; -f = TEXTREAD('freq.txt')*1E-6 -R = 128; -fa_dec = fa/R -N_pfir = 63; - -I_in = TEXTREAD('i_in.txt')'; -I_out = TEXTREAD('i_out.txt')'; -Q_out = TEXTREAD('q_out.txt')'; - -N= length(I_out) -N_fft = N; -N_fft2 = N_fft/2; - -fft_y2 = 2/N_fft*abs(fft(I_out(1:N_fft).*hann(N_fft)')); - -[i, v] = get_maxpur(fft_y2, fa, f); -max_spur_freq = (i*fa/N_fft); -max_spur_value = 20*log10(v); - -fft_y3 = 2/N_fft*abs(fft(I_in(1:N_fft).*hann(N_fft)')); - -[i, v] = get_maxpur(fft_y3, fa, f); -max_ditherd_spur_freq = (i*fa/N_fft); -max_ditherd_spur_value = 20*log10(v); - -I_out_dec = cic_filter(R, 1, 3, I_out); -Q_out_dec = cic_filter(R, 1, 3, Q_out); -N_dec = length(I_out_dec)-2*N_pfir; -N_fft_dec = N_dec -N_fft2_dec = N_fft_dec/2; -fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)')); - -pfir_b = sinc(0.1*(-(N_pfir-1)/2:1:(N_pfir)/2)); -pfir_b = pfir_b/sum(pfir_b).*blackman(N_pfir)'; -I_out_dec_pfir = filter(pfir_b, 1, I_out_dec); -Q_out_dec_pfir = filter(pfir_b, 1, Q_out_dec); -fft_y2_dec_pfir = 2/N_fft_dec*abs(fft(I_out_dec_pfir(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)')); - -% Output -close all; - -plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec_pfir(1:N_fft2_dec+1)), '-'); grid; - -figure; -plot(1:length(I_out_dec_pfir), I_out_dec_pfir, 1:length(Q_out_dec_pfir), Q_out_dec_pfir); grid; - -figure; -freqz(pfir_b, 1, 1000); - -figure; -plot(pfir_b); grid; - - -figure; -subplot(2,1,1) -plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_spur_value, max_spur_freq); -legend('With dithering', spur_legend); -legend('No dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -140 0]); -subplot(2,1,2) -plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.3fMHz', max_ditherd_spur_value, max_ditherd_spur_freq); -legend('With dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -140 0]); - -plot(1:N, I_out, 1:N, Q_out); grid; - -function [max_i, max_v] = get_maxpur(spec, fa, f) -max_v = 0; -max_i = 0; -for ii=1:fix(length(spec)/2+1), - fi = ii*fa/length(spec); - dfi = fi - f; - if abs(dfi) > 0.005*f - if spec(ii) > max_v - max_v = spec(ii); - max_i = ii-1; - end - end; -end; diff --git a/lib/radio/nco/sim/tb_nco_cordic.fdo b/lib/radio/nco/sim/tb_nco_cordic.fdo deleted file mode 100644 index 5c5e619..0000000 --- a/lib/radio/nco/sim/tb_nco_cordic.fdo +++ /dev/null @@ -1,19 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd" -vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd" -vcom -explicit -93 "../src/mix_cordic.vhd" -vcom -explicit -93 "../src/tb_nco_cordic.vhd" -vsim -t 1ps -lib work tb_nco -do {tb_nco_cordic.wdo} -view wave -view structure -view signals -run 250us diff --git a/lib/radio/nco/sim/tb_nco_cordic.wdo b/lib/radio/nco/sim/tb_nco_cordic.wdo deleted file mode 100644 index d41d308..0000000 --- a/lib/radio/nco/sim/tb_nco_cordic.wdo +++ /dev/null @@ -1,32 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_nco/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase -add wave -noupdate -divider Cordic -add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin -add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin -add wave -noupdate -format Literal /tb_nco/mix_din_i -add wave -noupdate -format Literal /tb_nco/mix_din_q -add wave -noupdate -format Literal /tb_nco/mix_dout_i -add wave -noupdate -format Literal /tb_nco/mix_dout_q -add wave -noupdate -format Logic /tb_nco/mix_dout_vld -add wave -noupdate -format Logic /tb_nco/mix_din_vld -add wave -noupdate -format Logic /tb_nco/fileout_enable -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {243331511 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {239972168 ps} {248698737 ps} diff --git a/lib/radio/nco/sim/tb_nco_lut.fdo b/lib/radio/nco/sim/tb_nco_lut.fdo deleted file mode 100644 index 12f120e..0000000 --- a/lib/radio/nco/sim/tb_nco_lut.fdo +++ /dev/null @@ -1,17 +0,0 @@ -vmap ieee_proposed ../../../../Common/sim/ieee_proposed - -vlib work -vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/nco_pkg.vhd" -vcom -explicit -93 "../src/waverom_dual.vhd" -vcom -explicit -93 "../src/wavelut.vhd" -vcom -explicit -93 "../src/nco_lut_dbg.vhd" -vcom -explicit -93 "../src/tb_nco_lut.vhd" -vsim -t 1ps -lib work tb_nco -do {tb_nco_lut.wdo} -view wave -view structure -view signals -run 250us diff --git a/lib/radio/nco/sim/tb_nco_lut.wdo b/lib/radio/nco/sim/tb_nco_lut.wdo deleted file mode 100644 index 0fd0917..0000000 --- a/lib/radio/nco/sim/tb_nco_lut.wdo +++ /dev/null @@ -1,46 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_nco/uut/srst -add wave -noupdate -format Logic /tb_nco/uut/clk -add wave -noupdate -format Logic /tb_nco/uut/pacc_clr -add wave -noupdate -format Logic /tb_nco/uut/pacc_inc -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in -add wave -noupdate -format Logic /tb_nco/uut/freq_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in -add wave -noupdate -format Logic /tb_nco/uut/phase_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q -add wave -noupdate -format Logic /tb_nco/uut/out_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_d -add wave -noupdate -format Literal /tb_nco/uut/wave_q_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud -add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud -add wave -noupdate -format Literal /tb_nco/uut/lfsr -add wave -noupdate -format Literal /tb_nco/uut/lfsr_out -add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid -add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {249141632 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {249024188 ps} {250051359 ps} diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m deleted file mode 100644 index b3fe27a..0000000 --- a/lib/radio/nco/sim/tb_nco_results.m +++ /dev/null @@ -1,61 +0,0 @@ -% Read data -function tb_nco_results(nbins) -fa = 100.0; -f = TEXTREAD('freq.txt')*1E-6 - -I_ud = TEXTREAD('q_ud.txt')'; -I_d = TEXTREAD('q_d.txt')'; -LFSR = TEXTREAD('lfsr.txt'); - -N= length(I_ud); -N_fft = min(16384, N); -N_fft2 = N_fft/2; - -fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)')); -fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)')); - -[i, v] = get_maxpur(fft_y2, fa, f); -max_spur_freq = (i*fa/N_fft); -max_spur_value = 20*log10(v); - -[i, v] = get_maxpur(fft_y3, fa, f); -max_ditherd_spur_freq = (i*fa/N_fft); -max_ditherd_spur_value = 20*log10(v); - -% Output -close all; - -subplot(2,1,1) -plot(fa/N_fft*(0:N_fft2),20*log10(fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq); -legend('With dithering', spur_legend); -legend('No dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -140 0]); -subplot(2,1,2) -plot(fa/N_fft*(0:N_fft2),20*log10(fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq); -legend('With dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -140 0]); - -figure; -hist(LFSR, nbins) - -function [max_i, max_v] = get_maxpur(spec, fa, f) -max_v = 0; -max_i = 0; -for ii=1:fix(length(spec)/2+1), - fi = ii*fa/length(spec); - dfi = fi - f; - if abs(dfi) > 0.05*f - if spec(ii) > max_v - max_v = spec(ii); - max_i = ii; - end - end; -end; diff --git a/lib/radio/nco/src/mix_cordic.vhd b/lib/radio/nco/src/mix_cordic.vhd deleted file mode 100644 index ad002a0..0000000 --- a/lib/radio/nco/src/mix_cordic.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity mix is -Generic -( - nbits_din : integer := 18; - nbits_din_frac : integer := 16; - nbits_dout : integer := 18; - nbits_dout_frac : integer := 16; - nbits_phase : integer := 16; - nbits_freq : integer := 16 -); -Port -( - rst : in std_logic; - clk : in std_logic; - nco_rst : in std_logic; - nco_en : in std_logic; - freq_in : in unsigned(nbits_freq-1 downto 0); - phase_in : in unsigned(nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - dout_i : out sfixed; - dout_q : out sfixed; - din_vld : in std_logic; - dout_vld : out std_logic -); -end mix; - -architecture Behavioral of mix is - - COMPONENT cordic_pipe_top - GENERIC - ( - cordic_mode : cordic_mode_t; - z_range : real; - gain_corr_mode : gain_corr_mode_t; - nstages : integer; - nbits_x_in : integer; - nbits_y_in : integer; - nbits_z_in : integer; - nbits_frac_x_in : integer; - nbits_frac_y_in : integer; - nbits_frac_z_in : integer; - nbits_x_out : integer; - nbits_y_out : integer; - nbits_z_out : integer; - nbits_frac_x_out : integer; - nbits_frac_y_out : integer; - nbits_frac_z_out : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - vld_in : in std_logic; - xin : in sfixed; - yin : in sfixed; - zin : in sfixed; - xout : out sfixed; - yout : out sfixed; - zout : out sfixed; - vld_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_phase_frac : integer := nbits_phase; - -------------------------------------------------------------------------------- - signal phase : signed(nbits_phase-1 downto 0); - signal xin, yin : sfixed(shi(nbits_din, nbits_din_frac) downto slo(nbits_din, nbits_din_frac)); - signal xout, yout : sfixed(shi(nbits_dout, nbits_dout_frac) downto slo(nbits_dout, nbits_dout_frac)); - - signal dout_valid : std_logic; - - signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); - -------------------------------------------------------------------------------- -begin - - dout_i <= xout; - dout_q <= yout; - xin <= din_i; - yin <= din_q; - - dout_vld <= dout_valid; - ------------------------------------------------------------- - proc_phase_accu: process(clk) - variable phase_accu : signed(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if rst = '1' or nco_rst = '1' then - phase_accu := (others => '0'); - elsif nco_en = '1' then - phase <= phase_accu + signed(phase_in); - phase_accu := phase_accu + signed(freq_in); - end if; - end if; - zin <= sfixed(phase); - end process; - ------------------------------------------------------------- - inst_cordic: cordic_pipe_top - GENERIC MAP - ( - cordic_mode => cordic_mode_rotate, - z_range => 1.0, - gain_corr_mode => gain_mode_disabled, - nstages => nbits_phase, - nbits_x_in => nbits_din, - nbits_frac_x_in => nbits_din_frac, - nbits_y_in => nbits_din, - nbits_frac_y_in => nbits_din_frac, - nbits_z_in => nbits_phase, - nbits_frac_z_in => nbits_phase_frac, - nbits_x_out => nbits_dout, - nbits_frac_x_out => nbits_dout_frac, - nbits_y_out => nbits_dout, - nbits_frac_y_out => nbits_dout_frac, - nbits_z_out => nbits_phase, - nbits_frac_z_out => nbits_phase_frac - ) - PORT MAP - ( - rst => rst, - clk => clk, - vld_in => din_vld, - xin => xin, - yin => yin, - zin => zin, - xout => xout, - yout => yout, - zout => zout, - vld_out => dout_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak deleted file mode 100644 index 657b97a..0000000 --- a/lib/radio/nco/src/nco.vhd.bak +++ /dev/null @@ -1,240 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 12; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal valid : std_logic_vector(3 downto 0); - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lsfr_sum : unsigned(nbits_phase-1 downto 0); - signal lut_addr : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid _ std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i; - wave_out_q <= wave_q; - ------------------------------------------------------------- - proc_ctrl: process(srst, clk, pacc_inc, pacc_clr) - begin - if rising_edge(clk) then - if srst = '1' then - valid <= (others => '0'); - else - valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - for i in lfsr'range loop - lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr); - end loop; - elsif pacc_inc ='1' then - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; --- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - begin - if rising_edge(clk) then - lsfr_sum <= lfsr_out + phase; - lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(clk, phase) - begin - if has_out_reg = true then - if rising_edge(clk) then - phase_out <= phase; - end if; - else - phase_out <= phase; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, valid) - begin - out_valid <= valid(valid'right+1); - if has_out_reg = true then - out_valid <= valid(valid'right+2); - if has_pipe_reg = true then - out_valid <= valid(valid'right+3); - end if; - elsif has_pipe_reg = true then - out_valid <= valid(valid'right+2); - end if; - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - has_out_reg => has_out_reg - ) - PORT MAP - ( - clk => clk, - addr => lut_addr, - addr_valid => lut_addr_valid, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_lut.vhd b/lib/radio/nco/src/nco_lut.vhd deleted file mode 100644 index 09e1e87..0000000 --- a/lib/radio/nco/src/nco_lut.vhd +++ /dev/null @@ -1,229 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(clk, phase) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_lut_dbg.vhd b/lib/radio/nco/src/nco_lut_dbg.vhd deleted file mode 100644 index a766e7d..0000000 --- a/lib/radio/nco/src/nco_lut_dbg.vhd +++ /dev/null @@ -1,259 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - - debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out; - debug_out.i_d <= to_real(wave_i_d); - debug_out.q_d <= to_real(wave_q_d); - debug_out.i_ud <= to_real(wave_i_ud); - debug_out.q_ud <= to_real(wave_q_ud); - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_ud: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_ud, - wave_i_out => wave_i_ud, - wave_q_out => wave_q_ud, - valid_out => wave_ud_valid - ); - - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd deleted file mode 100644 index d64b23a..0000000 --- a/lib/radio/nco/src/nco_pkg.vhd +++ /dev/null @@ -1,95 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; - -------------------------------------------------------------------------------- -package nco_pkg is - - constant tpd : time := 0 ns; - - type real_array_t is array (natural range <>) of real; - type natural_array_t is array (natural range <>) of natural; - type phase_relation_t is (phase_90deg, phase_270deg); - - type debug_out_t is record - lfsr : unsigned(31 downto 0); - i_ud : real; - q_ud : real; - i_d : real; - q_d : real; - end record; - - constant lfsr_poly : natural_array_t(3 to 24) := - ( - 12, -- 3 - 24, -- 4 - 58, -- 5 - 114, -- 6 - 210, -- 7 - 500, -- 8 - 1000, -- 9 - 1824, -- 10 - 3712, -- 11 - 7184, -- 12 - 14592, -- 13 - 28674, -- 14 - 59392, -- 15 - 106512, -- 16 - 245760, -- 17 - 466944, -- 18 - 933888, -- 19 - 1654784, -- 20 - 3735552, -- 21 - 7342080, -- 22 - 14745600, -- 23 - 14811138 -- 24 - ); - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - -end; -- package nco_pkg; - -------------------------------------------------------------------------------- -package body nco_pkg is - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := sin(phi); - phi := phi + dphi; - end loop; - - return tbl; - end sin_tbl; - - ------------------------------------------------------------- - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := cos(phi); - phi := phi + dphi; - end loop; - - return tbl; - end cos_tbl; - -------------------------------------------------------------------------------- -end; -- package nco_pkg; diff --git a/lib/radio/nco/src/tb_mix_cordic.vhd b/lib/radio/nco/src/tb_mix_cordic.vhd deleted file mode 100644 index 335c619..0000000 --- a/lib/radio/nco/src/tb_mix_cordic.vhd +++ /dev/null @@ -1,331 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.cordic_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix IS - Generic - ( - nbits_wave_in : integer := 16; - nbits_wave_out : integer := 18; -- Gain of 2.6 (mix + rfgen) - nbits_phase : integer := 20; - nbits_freq : integer := 20 - ); -END tb_mix; - -ARCHITECTURE behavior OF tb_mix IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix - GENERIC - ( - nbits_din : integer; - nbits_din_frac : integer; - nbits_dout : integer; - nbits_dout_frac : integer; - nbits_phase : integer; - nbits_freq : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - nco_rst : in std_logic; - nco_en : in std_logic; - freq_in : in unsigned(nbits_freq-1 downto 0); - phase_in : in unsigned(nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - dout_i : out sfixed; - dout_q : out sfixed; - din_vld : in std_logic; - dout_vld : out std_logic - ); - END COMPONENT; - - --Constants - constant fa : REAL := 100.0E6; - constant frf : REAL := 3.333E5; - constant flo : REAL := 3.333E5; - constant df : REAL := 10.0E3; - constant PERIOD : time := 10 ns; - constant num_steps : integer := 1000000; - - constant nbits_wave_in_frac : integer := nbits_wave_in-2; - constant nbits_wave_out_frac : integer := nbits_wave_out-2; - - SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_freq); - SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_freq); - SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_freq); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL mix_nco_rst : std_logic := '0'; - SIGNAL mix_nco_en : std_logic := '0'; - SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0'); - SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0'); - - --Outputs - SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); - SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); - SIGNAL mix_dout_vld : std_logic; - SIGNAL mix_din_vld : std_logic := '0'; - - SIGNAL rfgen_nco_rst : std_logic := '0'; - SIGNAL rfgen_nco_en : std_logic := '0'; - SIGNAL rfgen_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0'); - SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0'); - - --Outputs - signal rfgen_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac)); - signal rfgen_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL rfgen_dout_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL rfgen_dout_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL rfgen_dout_vld : std_logic; - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix - GENERIC MAP - ( - nbits_din => nbits_wave_in, - nbits_din_frac => nbits_wave_in_frac, - nbits_dout => nbits_wave_out, - nbits_dout_frac => nbits_wave_out_frac, - nbits_phase => nbits_phase, - nbits_freq => nbits_freq - ) - PORT MAP - ( - rst => srst, - clk => clk, - nco_rst => mix_nco_rst, - nco_en => mix_nco_en, - freq_in => mix_freq_in, - phase_in => mix_phase_in, - din_i => mix_din_i, - din_q => mix_din_q, - dout_i => mix_dout_i, - dout_q => mix_dout_q, - din_vld => mix_din_vld, - dout_vld => mix_dout_vld - ); - - rfgen1: mix - GENERIC MAP - ( - nbits_din => nbits_wave_in, - nbits_din_frac => nbits_wave_in_frac, - nbits_dout => nbits_wave_in, - nbits_dout_frac => nbits_wave_in_frac, - nbits_phase => nbits_phase, - nbits_freq => nbits_freq - ) - PORT MAP - ( - rst => srst, - clk => clk, - nco_rst => rfgen_nco_rst, - nco_en => rfgen_nco_en, - freq_in => rfgen_freq_in, - phase_in => rfgen_phase_in, - din_i => rfgen_din_i, - din_q => rfgen_din_q, - dout_i => rfgen_dout_i, - dout_q => rfgen_dout_q, - din_vld => '1', - dout_vld => rfgen_dout_vld - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - mix_din_i <= rfgen_dout_i; - mix_din_q <= to_sfixed(0.0, mix_din_q); - mix_din_vld <= rfgen_dout_vld; - - tb : PROCESS - file RESULT_FREQ: text open write_mode is "freq.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo)); - - wait for 2*PERIOD; - ------------------------------------------- - -- 1 - mix_phase_in <= to_unsigned(0,nbits_phase); - wait until rising_edge(clk); - - mix_freq_in <= to_unsigned(1411,nbits_freq); - wait until rising_edge(clk); - - wait for 2*PERIOD; - mix_nco_en <= '1'; - - wait for 2*PERIOD; - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - mix_freq_in <= to_unsigned(643,nbits_freq); - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(800,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(45072,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(20593,nbits_phase); - wait until rising_edge(clk); - - ------------------------------------------- - mix_freq_in <= to_unsigned(freq_word,nbits_freq); - wait until rising_edge(clk); - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait for 200000*PERIOD; - fileout_enable <= '0'; - - ------------------------------------------- - -- Sweep - freq_word <= 100; - for i in 1 to 200 loop - wait for 20*PERIOD; - freq_word <= freq_word + dfreq_word; - - mix_freq_in <= to_unsigned(freq_word,nbits_freq); - wait until rising_edge(clk); - - end loop; - - mix_nco_en <= '0'; - wait for 20*PERIOD; - fileout_enable <= '0'; - wait until rising_edge(clk); - mix_nco_rst <= '1'; - wait until rising_edge(clk); - mix_nco_rst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - mix_nco_rst <= '1'; - wait until rising_edge(clk); - mix_nco_rst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - mix_nco_en <= '1'; - wait until rising_edge(clk); - mix_nco_en <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - mix_freq_in <= to_unsigned(freq_word,nbits_freq); - wait until rising_edge(clk); - - wait for 20*PERIOD; - mix_nco_en <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - - rfgen_ctrl : PROCESS - - BEGIN - wait for 20*PERIOD; - wait until rising_edge(clk) and srst = '0'; - rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_freq); - wait until rising_edge(clk); - - wait for 20*PERIOD; - rfgen_nco_en <= '1'; - - wait for 20*PERIOD; - - wait; - END PROCESS; - - tb_fo : PROCESS(clk) - file RESULT_Ii: text open write_mode is "i_in.txt"; - file RESULT_Qi: text open write_mode is "q_in.txt"; - file RESULT_Io: text open write_mode is "i_out.txt"; - file RESULT_Qo: text open write_mode is "q_out.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' then - if rfgen_dout_vld = '1' then - fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i))); - fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q))); - end if; - if mix_dout_vld = '1' then - fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(mix_dout_i))); - fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(mix_dout_q))); - end if; - end if; - - END PROCESS; - - -END; diff --git a/lib/radio/nco/src/tb_nco_cordic.vhd b/lib/radio/nco/src/tb_nco_cordic.vhd deleted file mode 100644 index 0bcfd93..0000000 --- a/lib/radio/nco/src/tb_nco_cordic.vhd +++ /dev/null @@ -1,265 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_nco IS - Generic - ( - nbits_wave_in : integer := 16; - nbits_wave_out : integer := 16; - nbits_phase : integer := 20; - nbits_freq : integer := 20 - ); -END tb_nco; - -ARCHITECTURE behavior OF tb_nco IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix - GENERIC - ( - nbits_din : integer; - nbits_din_frac : integer; - nbits_dout : integer; - nbits_dout_frac : integer; - nbits_phase : integer; - nbits_freq : integer - ); - PORT - ( - rst : in std_logic; - clk : in std_logic; - nco_rst : in std_logic; - nco_en : in std_logic; - freq_in : in unsigned(nbits_freq-1 downto 0); - phase_in : in unsigned(nbits_phase-1 downto 0); - din_i : in sfixed; - din_q : in sfixed; - dout_i : out sfixed; - dout_q : out sfixed; - din_vld : in std_logic; - dout_vld : out std_logic - ); - END COMPONENT; - - --Constants - constant fa : REAL := 100.0E6; - constant f : REAL := 5.0*fa/24.0; - constant df : REAL := 10.0E3; - constant PERIOD : time := 10 ns; - - constant nbits_wave_in_frac : integer := nbits_wave_in-2; - constant nbits_wave_out_frac : integer := nbits_wave_out-2; - - SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); - SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL mix_nco_rst : std_logic := '0'; - SIGNAL mix_nco_en : std_logic := '0'; - SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0'); - SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0'); - - --Outputs - SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac)); - SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); - SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); - SIGNAL mix_dout_vld : std_logic; - SIGNAL mix_din_vld : std_logic := '1'; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix - GENERIC MAP - ( - nbits_din => nbits_wave_in, - nbits_din_frac => nbits_wave_in_frac, - nbits_dout => nbits_wave_out, - nbits_dout_frac => nbits_wave_out_frac, - nbits_phase => nbits_phase, - nbits_freq => nbits_freq - ) - PORT MAP - ( - rst => srst, - clk => clk, - nco_rst => mix_nco_rst, - nco_en => mix_nco_en, - freq_in => mix_freq_in, - phase_in => mix_phase_in, - din_i => mix_din_i, - din_q => mix_din_q, - dout_i => mix_dout_i, - dout_q => mix_dout_q, - din_vld => mix_din_vld, - dout_vld => mix_dout_vld - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file RESULT_FREQ: text open write_mode is "freq.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - fprint(RESULT_FREQ, L,"%s\n", REAL'image(f)); - - wait for 2*PERIOD; - ------------------------------------------- - -- 1 - mix_phase_in <= to_unsigned(0,nbits_phase); - wait until rising_edge(clk); - - mix_freq_in <= to_unsigned(1411,nbits_phase); - wait until rising_edge(clk); - - wait for 2*PERIOD; - mix_nco_en <= '1'; - - wait for 2*PERIOD; - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - mix_freq_in <= to_unsigned(643,nbits_phase); - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(800,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(45072,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - ------------------------------------------- - mix_phase_in <= to_unsigned(20593,nbits_phase); - wait until rising_edge(clk); - - ------------------------------------------- - mix_freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait for 20000*PERIOD; - fileout_enable <= '0'; - - ------------------------------------------- - -- Sweep - freq_word <= 100; - for i in 1 to 200 loop - wait for 20*PERIOD; - freq_word <= freq_word + dfreq_word; - - mix_freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - - end loop; - - mix_nco_en <= '0'; - wait for 20*PERIOD; - fileout_enable <= '0'; - wait until rising_edge(clk); - mix_nco_rst <= '1'; - wait until rising_edge(clk); - mix_nco_rst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - mix_nco_rst <= '1'; - wait until rising_edge(clk); - mix_nco_rst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - mix_nco_en <= '1'; - wait until rising_edge(clk); - mix_nco_en <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - mix_freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - - wait for 20*PERIOD; - mix_nco_en <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - wait for 20*PERIOD; - mix_nco_en <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk) - file RESULT_I: text open write_mode is "i_ud.txt"; - file RESULT_Q: text open write_mode is "q_ud.txt"; - file RESULT_ID: text open write_mode is "i_d.txt"; - file RESULT_QD: text open write_mode is "q_d.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and mix_dout_vld = '1' then - fprint(RESULT_I, L,"%s\n", REAL'image(to_real(mix_dout_i))); - fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(mix_dout_q))); - fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(mix_dout_i))); - fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(mix_dout_q))); - end if; - - END PROCESS; - - -END; diff --git a/lib/radio/nco/src/tb_nco_lut.vhd b/lib/radio/nco/src/tb_nco_lut.vhd deleted file mode 100644 index 53a480d..0000000 --- a/lib/radio/nco/src/tb_nco_lut.vhd +++ /dev/null @@ -1,303 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.nco_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_nco IS - Generic ( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_270deg; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true - ); -END tb_nco; - -ARCHITECTURE behavior OF tb_nco IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT nco - GENERIC ( - nbits_wave : integer; - nbits_phase : integer; - nbits_lut_depth : integer; - nbits_dither : integer; - nbits_lfsr : integer; - q_phase : phase_relation_t; - has_pipe_reg : boolean; - has_out_reg : boolean - ); - PORT( - srst : in std_logic; - clk : in std_logic; --- ce : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t - ); - END COMPONENT; - - --Constants - constant fa : REAL := 100.0E6; - constant f : REAL := 5.0*fa/24.0; - constant df : REAL := 10.0E3; - constant PERIOD : time := 10 ns; - constant nbits_wave_frac : integer := nbits_wave; - - SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); - SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); - - --Inputs - SIGNAL clk : std_logic := '0'; --- SIGNAL ce : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL pacc_clr : std_logic := '0'; - SIGNAL pacc_inc : std_logic := '0'; - SIGNAL phase_load : std_logic := '0'; - SIGNAL freq_load : std_logic := '0'; - SIGNAL freq_in : unsigned(nbits_phase-1 downto 0); - SIGNAL phase_in : unsigned(nbits_phase-1 downto 0); - - --Outputs - SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL out_valid : std_logic; - SIGNAL phase_out : unsigned(nbits_phase-1 downto 0); - SIGNAL debug_out : debug_out_t; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: nco - GENERIC MAP ( - nbits_wave => nbits_wave, - nbits_phase => nbits_phase, - nbits_lut_depth => nbits_lut_depth, - nbits_dither => nbits_dither, - nbits_lfsr => nbits_lfsr, - q_phase => q_phase, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg - ) - PORT MAP( - srst => srst, - clk => clk, --- ce => ce, - pacc_clr => pacc_clr, - pacc_inc => pacc_inc, - freq_in => freq_in, - freq_load => freq_load, - phase_in => phase_in, - phase_load => phase_load, - phase_out => phase_out, - wave_out_i => wave_out_i, - wave_out_q => wave_out_q, - out_valid => out_valid, - debug_out => debug_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file RESULT_FREQ: text open write_mode is "freq.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - fprint(RESULT_FREQ, L,"%s\n", REAL'image(f)); - - wait for 2*PERIOD; --- ce <= '1'; - ------------------------------------------- - -- 1 - phase_in <= to_unsigned(0,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - freq_in <= to_unsigned(1411,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 2*PERIOD; - pacc_inc <= '1'; - - wait for 2*PERIOD; - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - freq_in <= to_unsigned(643,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 40*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(800,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(45072,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(20593,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - ------------------------------------------- - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait for 20000*PERIOD; - fileout_enable <= '0'; - - ------------------------------------------- - -- Sweep - freq_word <= 100; - for i in 1 to 200 loop - wait for 20*PERIOD; - freq_word <= freq_word + dfreq_word; - - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - end loop; - - pacc_inc <= '0'; - wait for 20*PERIOD; - fileout_enable <= '0'; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_inc <= '1'; - wait until rising_edge(clk); - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_I: text open write_mode is "i_ud.txt"; - file RESULT_Q: text open write_mode is "q_ud.txt"; - file RESULT_ID: text open write_mode is "i_d.txt"; - file RESULT_QD: text open write_mode is "q_d.txt"; - file RESULT_LFSR: text open write_mode is "lfsr.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud)); - fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud)); - fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d)); - fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d)); - fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr))); - end if; - - END PROCESS; - - -END; diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd deleted file mode 100644 index 6f8eaed..0000000 --- a/lib/radio/nco/src/wavelut.vhd +++ /dev/null @@ -1,245 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity wavelut is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_lut_depth : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_out_reg : boolean := false -); -Port -( - rst : in std_logic; - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic -); -end wavelut; - -architecture Behavioral of wavelut is - - COMPONENT waverom_dual - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_rom_depth : integer - ); - Port - ( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- -constant nbits_rom_depth : integer := nbits_lut_depth-2; - -------------------------------------------------------------------------------- -signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal inv_i : std_logic; -signal inv_q : std_logic; -signal addr_i : unsigned(nbits_rom_depth-1 downto 0); -signal addr_q : unsigned(nbits_rom_depth-1 downto 0); -signal zero_i : std_logic; -signal zero_q : std_logic; - -------------------------------------------------------------------------------- -begin - - inst_waverom_dual: waverom_dual - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_rom_depth => nbits_rom_depth - ) - PORT MAP - ( - clk => clk, - addr_i => addr_i, - addr_q => addr_q, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -proc_valid: process(clk) - variable v : unsigned(0 to 1); - begin - if rising_edge(clk) then - if rst = '1' then - v := (others => '0'); - valid_out <= '0'; - else - valid_out <= v(1); - v(1) := v(0); - v(0) := addr_valid; - end if; - end if; - end process; - ------------------------------------------------------------- -proc_tbl_addr_i: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_2 : integer := 2**(nbits_lut_depth-1); - constant N_4 : integer := 2**(nbits_lut_depth-2); - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(N_2 - n2, index'length); - else - index := to_unsigned(n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_i <= (others => '0'); - zero_i <= '0'; - inv_i <= '0'; - elsif addr_valid = '1' then - addr_i <= index(addr'left-2 downto addr'right); - zero_i <= index(addr'left-1); - inv_i <= addr(addr'left) xor addr(addr'left-1); - end if; - end if; - - end process; - -------------------------------------------------------------------------------- -proc_tbl_addr_q: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_4 : integer := 2**(nbits_lut_depth-2); - - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(n2 - N_4, index'length); - else - index := to_unsigned(N_4 - n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_q <= (others => '0'); - zero_q <= '0'; - inv_q <= '0'; - elsif addr_valid = '1' then - addr_q <= index(addr'left-2 downto addr'right); - zero_q <= index(addr'left-1); - if q_phase = phase_90deg then - inv_q <= addr(addr'left); - elsif q_phase = phase_270deg then - inv_q <= not addr(addr'left); - end if; - end if; - end if; - - end process; - ------------------------------------------------------------- -proc_out_i: process(clk, wave_i, inv_i, zero_i) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_i; - if inv = '1' then - w := resize(-wave_i, w, fixed_wrap, fixed_truncate); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_i_out <= w; - end if; - else - wave_i_out <= w; - end if; - - if rising_edge(clk) then - z := zero_i; - inv := inv_i; - end if; - - end process; - ------------------------------------------------------------- -proc_out_q: process(clk, wave_q, inv_q, zero_q) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_q; - if inv = '1' then - w := resize(-wave_q, w, fixed_wrap, fixed_truncate); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_q_out <= w; - end if; - else - wave_q_out <= w; - end if; - - if rising_edge(clk) then - z := zero_q; - inv := inv_q; - end if; - - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd deleted file mode 100644 index b39e2a7..0000000 --- a/lib/radio/nco/src/waverom_dual.vhd +++ /dev/null @@ -1,92 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; - -library ieee_proposed; -use ieee_proposed.math_utility_pkg.all; -use ieee_proposed.fixed_pkg.all; - -library work; -use work.fixed_util_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity waverom_dual is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_rom_depth : integer := 12 -); -Port -( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed -); -end waverom_dual; - -architecture Behavioral of waverom_dual is - -------------------------------------------------------------------------------- -constant rom_depth : integer := 2**nbits_rom_depth; -type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - -constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0'); - -------------------------------------------------------------------------------- -function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is -variable res : wave_mem_t; -begin - for i in 0 to len-1 loop - res(i) := to_sfixed(wave_real(i), proto, fixed_saturate, fixed_round); - end loop; - - return res; -end to_wave_mem; - -------------------------------------------------------------------------------- --- Create ROM -constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0); -constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto); - -------------------------------------------------------------------------------- -begin - -------------------------------------------------------------------------------- -proc_wave: process(clk) - begin - if rising_edge(clk) then - wave_i_out <= wave_tbl(to_integer(addr_i)); - wave_q_out <= wave_tbl(to_integer(addr_q)); - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/uart/bbfifo_16x8.vhd b/lib/uart/bbfifo_16x8.vhd deleted file mode 100644 index d6604a6..0000000 --- a/lib/uart/bbfifo_16x8.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- 'Bucket Brigade' FIFO --- 16 deep --- 8-bit data --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for BBFIFO_16x8 --- -entity bbfifo_16x8 is - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end bbfifo_16x8; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for BBFIFO_16x8 --- -architecture low_level_definition of bbfifo_16x8 is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in BBFIFO_16x8 --- ------------------------------------------------------------------------------------- --- -signal pointer : std_logic_vector(3 downto 0); -signal next_count : std_logic_vector(3 downto 0); -signal half_count : std_logic_vector(3 downto 0); -signal count_carry : std_logic_vector(2 downto 0); - -signal pointer_zero : std_logic; -signal pointer_full : std_logic; -signal decode_data_present : std_logic; -signal data_present_int : std_logic; -signal valid_write : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of zero_lut : label is "0001"; -attribute INIT of full_lut : label is "8000"; -attribute INIT of dp_lut : label is "BFA0"; -attribute INIT of valid_lut : label is "C4"; --- ------------------------------------------------------------------------------------- --- --- Start of BBFIFO_16x8 circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- SRL16E data storage - - data_width_loop: for i in 0 to 7 generate - -- - attribute INIT : string; - attribute INIT of data_srl : label is "0000"; - -- - begin - - data_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_in(i), - CE => valid_write, - CLK => clk, - A0 => pointer(0), - A1 => pointer(1), - A2 => pointer(2), - A3 => pointer(3), - Q => data_out(i) ); - - end generate data_width_loop; - - -- 4-bit counter to act as data pointer - -- Counter is clock enabled by 'data_present' - -- Counter will be reset when 'reset' is active - -- Counter will increment when 'valid_write' is active - - count_width_loop: for i in 0 to 3 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "6606"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => pointer(i), - CE => data_present_int, - R => reset, - C => clk); - - count_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"6606") - --synthesis translate_on - port map( I0 => pointer(i), - I1 => read, - I2 => pointer_zero, - I3 => write, - O => half_count(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => valid_write, - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => valid_write, - O => next_count(i)); - - end generate lsb_count; - - mid_count: if i>0 and i<3 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => count_carry(i-1), - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate mid_count; - - upper_count: if i=3 generate - begin - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - - -- Detect when pointer is zero and maximum - - zero_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0001") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_zero ); - - - full_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"8000") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_full ); - - - -- Data Present status - - dp_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"BFA0") - --synthesis translate_on - port map( I0 => write, - I1 => read, - I2 => pointer_zero, - I3 => data_present_int, - O => decode_data_present ); - - dp_flop: FDR - port map ( D => decode_data_present, - Q => data_present_int, - R => reset, - C => clk); - - -- Valid write signal - - valid_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"C4") - --synthesis translate_on - port map( I0 => pointer_full, - I1 => write, - I2 => read, - O => valid_write ); - - - -- assign internal signals to outputs - - full <= pointer_full; - half_full <= pointer(3); - data_present <= data_present_int; - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE BBFIFO_16x8.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_rx.vhd b/lib/uart/kcuart_rx.vhd deleted file mode 100644 index a7ac1a2..0000000 --- a/lib/uart/kcuart_rx.vhd +++ /dev/null @@ -1,352 +0,0 @@ --- Constant (K) Compact UART Receiver --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_RX --- -entity kcuart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end kcuart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_RX --- -architecture low_level_definition of kcuart_rx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_RX --- ------------------------------------------------------------------------------------- --- -signal sync_serial : std_logic; -signal stop_bit : std_logic; -signal data_int : std_logic_vector(7 downto 0); -signal data_delay : std_logic_vector(7 downto 0); -signal start_delay : std_logic; -signal start_bit : std_logic; -signal edge_delay : std_logic; -signal start_edge : std_logic; -signal decode_valid_char : std_logic; -signal valid_char : std_logic; -signal decode_purge : std_logic; -signal purge : std_logic; -signal valid_srl_delay : std_logic_vector(8 downto 0); -signal valid_reg_delay : std_logic_vector(8 downto 0); -signal decode_data_strobe : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of start_srl : label is "0000"; -attribute INIT of edge_srl : label is "0000"; -attribute INIT of valid_lut : label is "0040"; -attribute INIT of purge_lut : label is "54"; -attribute INIT of strobe_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- Synchronise input serial data to system clock - - sync_reg: FD - port map ( D => serial_in, - Q => sync_serial, - C => clk); - - stop_reg: FD - port map ( D => sync_serial, - Q => stop_bit, - C => clk); - - - -- Data delays to capture data at 16 time baud rate - -- Each SRL16E is followed by a flip-flop for best timing - - data_loop: for i in 0 to 7 generate - begin - - lsbs: if i<7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(i+1), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate lsbs; - - msb: if i=7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => stop_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate msb; - - data_reg: FDE - port map ( D => data_delay(i), - Q => data_int(i), - CE => en_16_x_baud, - C => clk); - - end generate data_loop; - - -- Assign internal signals to outputs - - data_out <= data_int; - - -- Data delays to capture start bit at 16 time baud rate - - start_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(0), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => start_delay ); - - start_reg: FDE - port map ( D => start_delay, - Q => start_bit, - CE => en_16_x_baud, - C => clk); - - - -- Data delays to capture start bit leading edge at 16 time baud rate - -- Delay ensures data is captured at mid-bit position - - edge_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => start_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '0', - Q => edge_delay ); - - edge_reg: FDE - port map ( D => edge_delay, - Q => start_edge, - CE => en_16_x_baud, - C => clk); - - -- Detect a valid character - - valid_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0040") - --synthesis translate_on - port map( I0 => purge, - I1 => stop_bit, - I2 => start_edge, - I3 => edge_delay, - O => decode_valid_char ); - - valid_reg: FDE - port map ( D => decode_valid_char, - Q => valid_char, - CE => en_16_x_baud, - C => clk); - - -- Purge of data status - - purge_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"54") - --synthesis translate_on - port map( I0 => valid_reg_delay(8), - I1 => valid_char, - I2 => purge, - O => decode_purge ); - - purge_reg: FDE - port map ( D => decode_purge, - Q => purge, - CE => en_16_x_baud, - C => clk); - - -- Delay of valid_char pulse of length equivalent to the time taken - -- to purge data shift register of all data which has been used. - -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with - -- up to 16 delays and utilising the dedicated flip flop in each stage. - - valid_loop: for i in 0 to 8 generate - begin - - lsb: if i=0 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_char, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate lsb; - - msbs: if i>0 generate - -- - attribute INIT : string; - attribute INIT of delay16_srl : label is "0000"; - -- - begin - - delay16_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_reg_delay(i-1), - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate msbs; - - data_reg: FDE - port map ( D => valid_srl_delay(i), - Q => valid_reg_delay(i), - CE => en_16_x_baud, - C => clk); - - end generate valid_loop; - - -- Form data strobe - - strobe_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => valid_char, - I1 => en_16_x_baud, - O => decode_data_strobe ); - - strobe_reg: FD - port map ( D => decode_data_strobe, - Q => data_strobe, - C => clk); - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_tx.vhd b/lib/uart/kcuart_tx.vhd deleted file mode 100644 index 556ac58..0000000 --- a/lib/uart/kcuart_tx.vhd +++ /dev/null @@ -1,394 +0,0 @@ --- Constant (K) Compact UART Transmitter --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 2nd October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_TX --- -entity kcuart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end kcuart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_TX --- -architecture low_level_definition of kcuart_tx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_TX --- ------------------------------------------------------------------------------------- --- -signal data_01 : std_logic; -signal data_23 : std_logic; -signal data_45 : std_logic; -signal data_67 : std_logic; -signal data_0123 : std_logic; -signal data_4567 : std_logic; -signal data_01234567 : std_logic; -signal bit_select : std_logic_vector(2 downto 0); -signal next_count : std_logic_vector(2 downto 0); -signal mask_count : std_logic_vector(2 downto 0); -signal mask_count_carry : std_logic_vector(2 downto 0); -signal count_carry : std_logic_vector(2 downto 0); -signal ready_to_start : std_logic; -signal decode_Tx_start : std_logic; -signal Tx_start : std_logic; -signal decode_Tx_run : std_logic; -signal Tx_run : std_logic; -signal decode_hot_state : std_logic; -signal hot_state : std_logic; -signal hot_delay : std_logic; -signal Tx_bit : std_logic; -signal decode_Tx_stop : std_logic; -signal Tx_stop : std_logic; -signal decode_Tx_complete : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of mux1_lut : label is "E4FF"; -attribute INIT of mux2_lut : label is "E4FF"; -attribute INIT of mux3_lut : label is "E4FF"; -attribute INIT of mux4_lut : label is "E4FF"; -attribute INIT of ready_lut : label is "10"; -attribute INIT of start_lut : label is "0190"; -attribute INIT of run_lut : label is "1540"; -attribute INIT of hot_state_lut : label is "94"; -attribute INIT of delay14_srl : label is "0000"; -attribute INIT of stop_lut : label is "0180"; -attribute INIT of complete_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - mux1_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(0), - I2 => data_in(1), - I3 => Tx_run, - O => data_01 ); - - mux2_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(2), - I2 => data_in(3), - I3 => Tx_run, - O => data_23 ); - - mux3_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(4), - I2 => data_in(5), - I3 => Tx_run, - O => data_45 ); - - mux4_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(6), - I2 => data_in(7), - I3 => Tx_run, - O => data_67 ); - - mux5_muxf5: MUXF5 - port map( I1 => data_23, - I0 => data_01, - S => bit_select(1), - O => data_0123 ); - - mux6_muxf5: MUXF5 - port map( I1 => data_67, - I0 => data_45, - S => bit_select(1), - O => data_4567 ); - - mux7_muxf6: MUXF6 - port map( I1 => data_4567, - I0 => data_0123, - S => bit_select(2), - O => data_01234567 ); - - -- Register serial output and force start and stop bits - - pipeline_serial: FDRS - port map ( D => data_01234567, - Q => serial_out, - R => Tx_start, - S => Tx_stop, - C => clk); - - -- 3-bit counter - -- Counter is clock enabled by en_16_x_baud - -- Counter will be reset when 'Tx_start' is active - -- Counter will increment when Tx_bit is active - -- Tx_run must be active to count - -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow) - - count_width_loop: for i in 0 to 2 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "8"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => bit_select(i), - CE => en_16_x_baud, - R => Tx_start, - C => clk); - - count_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => bit_select(i), - I1 => Tx_run, - O => mask_count(i)); - - mask_and: MULT_AND - port map( I0 => bit_select(i), - I1 => Tx_run, - LO => mask_count_carry(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => Tx_bit, - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => Tx_bit, - O => next_count(i)); - - end generate lsb_count; - - upper_count: if i>0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => count_carry(i-1), - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - -- Ready to start decode - - ready_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"10") - --synthesis translate_on - port map( I0 => Tx_run, - I1 => Tx_start, - I2 => send_character, - O => ready_to_start ); - - -- Start bit enable - - start_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0190") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_stop, - I2 => ready_to_start, - I3 => Tx_start, - O => decode_Tx_start ); - - Tx_start_reg: FDE - port map ( D => decode_Tx_start, - Q => Tx_start, - CE => en_16_x_baud, - C => clk); - - - -- Run bit enable - - run_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"1540") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => Tx_bit, - I2 => Tx_start, - I3 => Tx_run, - O => decode_Tx_run ); - - Tx_run_reg: FDE - port map ( D => decode_Tx_run, - Q => Tx_run, - CE => en_16_x_baud, - C => clk); - - -- Bit rate enable - - hot_state_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"94") - --synthesis translate_on - port map( I0 => Tx_stop, - I1 => ready_to_start, - I2 => Tx_bit, - O => decode_hot_state ); - - hot_state_reg: FDE - port map ( D => decode_hot_state, - Q => hot_state, - CE => en_16_x_baud, - C => clk); - - delay14_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => hot_state, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '1', - Q => hot_delay ); - - Tx_bit_reg: FDE - port map ( D => hot_delay, - Q => Tx_bit, - CE => en_16_x_baud, - C => clk); - - -- Stop bit enable - - stop_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0180") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_run, - I2 => count_carry(2), - I3 => Tx_stop, - O => decode_Tx_stop ); - - Tx_stop_reg: FDE - port map ( D => decode_Tx_stop, - Q => Tx_stop, - CE => en_16_x_baud, - C => clk); - - -- Tx_complete strobe - - complete_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => en_16_x_baud, - O => decode_Tx_complete ); - - Tx_complete_reg: FD - port map ( D => decode_Tx_complete, - Q => Tx_complete, - C => clk); - - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_TX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd deleted file mode 100644 index 69eb70e..0000000 --- a/lib/uart/uart_rx.vhd +++ /dev/null @@ -1,146 +0,0 @@ --- UART Receiver with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_RX --- -entity uart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic); - end uart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_RX --- -architecture macro_level_definition of uart_rx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_RX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Receiver --- -component kcuart_rx - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_RX --- ------------------------------------------------------------------------------------- --- -signal uart_data_out : std_logic_vector(7 downto 0); -signal fifo_write : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_rx - port map ( serial_in => serial_in, - data_out => uart_data_out, - data_strobe => fifo_write, - en_16_x_baud => en_16_x_baud, - clk => clk ); - - - buf: bbfifo_16x8 - port map ( data_in => uart_data_out, - data_out => data_out, - reset => reset_buffer, - write => fifo_write, - read => read_buffer, - full => buffer_full, - half_full => buffer_half_full, - data_present => buffer_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd deleted file mode 100644 index ca42d04..0000000 --- a/lib/uart/uart_tx.vhd +++ /dev/null @@ -1,153 +0,0 @@ --- UART Transmitter with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_TX --- -entity uart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - tx_complete : out std_logic; - tx_empty : out std_logic; - clk : in std_logic); - end uart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_TX --- -architecture macro_level_definition of uart_tx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_TX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Transmitter --- -component kcuart_tx - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_TX --- ------------------------------------------------------------------------------------- --- -signal fifo_data_out : std_logic_vector(7 downto 0); -signal fifo_data_present : std_logic; -signal fifo_read : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - tx_complete <= fifo_read; - tx_empty <= not fifo_data_present; - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_tx - port map ( data_in => fifo_data_out, - send_character => fifo_data_present, - en_16_x_baud => en_16_x_baud, - serial_out => serial_out, - Tx_complete => fifo_read, - clk => clk); - - - buf: bbfifo_16x8 - port map ( data_in => data_in, - data_out => fifo_data_out, - reset => reset_buffer, - write => write_buffer, - read => fifo_read, - full => buffer_full, - half_full => buffer_half_full, - data_present => fifo_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_TX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd deleted file mode 100644 index f5acad0..0000000 --- a/lib/uart/uart_wb.vhd +++ /dev/null @@ -1,198 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY uart_wb IS - Port - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - ser_rx : in std_logic; - ser_tx : out std_logic - ); -END uart_wb; - -ARCHITECTURE behavior OF uart_wb IS - - COMPONENT uart_tx - Port - ( - data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - tx_complete : out std_logic; - tx_empty : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - COMPONENT uart_rx - Port - ( - serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - -- Signals for UART connections - signal baud_count : unsigned(15 downto 0); - signal en_16_x_baud : std_logic; - signal reg_we_uart_tx : std_logic; - signal tx_full : std_logic; - signal tx_half_full : std_logic; - signal reg_re_uart_rx : std_logic; - signal reg_uart_tx : unsigned(7 downto 0); - signal reg_uart_rx : std_logic_vector(7 downto 0); - signal rx_data_present : std_logic; - signal rx_full : std_logic; - signal rx_half_full : std_logic; - signal uart_status_port : unsigned(15 downto 0); - signal reg_uart_baud : unsigned(15 downto 0); - signal rx_int_en : std_logic; - signal tx_int_en : std_logic; - signal irq_rx : std_logic; - signal irq_tx : std_logic; - signal tx_complete : std_logic; - signal tx_empty : std_logic; - -begin - - SRDY_O <= CYC_I; - ------------------------------------------------------------------- -registers_write: - process(CLK_I) - begin - if rising_edge(CLK_I) then - reg_we_uart_tx <= '0'; - if RST_I = '1' then - reg_uart_baud <= to_unsigned(53, 16); - rx_int_en <= '0'; - tx_int_en <= '0'; - elsif (STB_I and CYC_I and WE_I) = '1' then - case ADDR_I(5 downto 2) is - - when "0000" => - reg_we_uart_tx <= '1'; - reg_uart_tx <= DAT_I(7 downto 0); - - when "0001" => - rx_int_en <= DAT_I(6); - tx_int_en <= DAT_I(5); - - when "0010" => - reg_uart_baud <= DAT_I(15 downto 0); - - when others => null; - end case; - end if; - end if; - end process; - -registers_read: - process(CLK_I) - begin - if rising_edge(CLK_I) then - reg_re_uart_rx <= '0'; - ACK_O <= '0'; - if (STB_I and CYC_I) = '1' then - ACK_O <= not WE_I; - DAT_O <= (others => '0'); - case ADDR_I(5 downto 2) is - - when "0000" => - reg_re_uart_rx <= not WE_I; - DAT_O(7 downto 0) <= unsigned(reg_uart_rx); - - when "0001" => - DAT_O(15 downto 0) <= uart_status_port; - - when "0010" => - DAT_O(15 downto 0) <= reg_uart_baud; - - when others => null; - end case; - end if; - end if; - end process; - -baud_timer: - process(CLK_I) - begin - if rising_edge(CLK_I) then - if RST_I = '1' then - baud_count <= (others => '0'); - elsif baud_count = reg_uart_baud then - baud_count <= (others => '0'); - en_16_x_baud <= '1'; - else - baud_count <= baud_count + 1; - en_16_x_baud <= '0'; - end if; - end if; - end process; - -irq_register: - process(CLK_I) - begin - if rising_edge(CLK_I) then - irq_tx <= tx_empty and tx_int_en; - irq_rx <= rx_data_present and rx_int_en; - end if; - end process; - -inst_uart_tx: uart_tx - port map - ( - data_in => std_logic_vector(reg_uart_tx), - write_buffer => reg_we_uart_tx, - reset_buffer => RST_I, - en_16_x_baud => en_16_x_baud, - serial_out => ser_tx, - buffer_full => tx_full, - buffer_half_full => tx_half_full, - tx_complete => tx_complete, - tx_empty => tx_empty, - clk => CLK_I - ); - -inst_uart_rx: uart_rx - port map - ( - serial_in => ser_rx, - data_out => reg_uart_rx, - read_buffer => reg_re_uart_rx, - reset_buffer => RST_I, - en_16_x_baud => en_16_x_baud, - buffer_data_present => rx_data_present, - buffer_full => rx_full, - buffer_half_full => rx_half_full, - clk => CLK_I - ); - - uart_status_port <= "000000" & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - INT_O <= irq_rx or irq_tx; - -end behavior; diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj deleted file mode 100644 index ce7b8ab..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj +++ /dev/null @@ -1,45 +0,0 @@ -vhdl work "../../src/sdram_config.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vhdl work "../../../../lib/misc/utils_pkg.vhd" -vhdl work "../../../../lib/misc/singleshot.vhd" -vhdl work "../../../../lib/misc/dpram_1w1r.vhd" -vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" -vhdl work "../../../../lib/uart/kcuart_tx.vhd" -vhdl work "../../../../lib/uart/kcuart_rx.vhd" -vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd" -vhdl work "../../src/bootloader.ROM_ld.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" -vhdl work "../../../../lib/uart/uart_tx.vhd" -vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vhdl work "../../../../lib/misc/async_types.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd" -vhdl work "../../src/async_defs.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" -vhdl work "../../../../lib/uart/uart_wb.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" -vhdl work "../../../../lib/misc/rom_wb.vhd" -vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/misc/gpio_wb.vhd" -vhdl work "../../../../lib/misc/clockgen_virtex4.vhd" -vhdl work "../../../../lib/misc/async_port_wb.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" -vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj deleted file mode 100644 index b62311a..0000000 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj +++ /dev/null @@ -1,45 +0,0 @@ -vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\misc\singleshot.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" -vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd" -vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd" -vhdl work "W:\vhdl\lib\misc\async_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd" -vhdl work "W:\vhdl\lib\uart\uart_wb.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd" -vhdl work "W:\vhdl\lib\misc\rom_wb.vhd" -vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" -vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd" -vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf deleted file mode 100644 index f8198e9..0000000 --- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ssram.ucf +++ /dev/null @@ -1,503 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %; - -NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "rst" TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_rx LOC = W2; -NET sys_rx IOSTANDARD = LVCMOS33; -NET sys_rx TIG; -NET "sys_tx" LOC = "W1"; -NET sys_tx IOSTANDARD = LVCMOS33; -NET "sys_tx" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_ssram_a<24> LOC = T21; -NET sys_flash_ssram_a<23> LOC = U20; -NET sys_flash_ssram_a<22> LOC = T19; -NET sys_flash_ssram_a<21> LOC = AC5; -NET sys_flash_ssram_a<20> LOC = AB5; -NET sys_flash_ssram_a<19> LOC = AC4; -NET sys_flash_ssram_a<18> LOC = AB4; -NET sys_flash_ssram_a<17> LOC = AB3; -NET sys_flash_ssram_a<16> LOC = AA4; -NET sys_flash_ssram_a<15> LOC = AA3; -NET sys_flash_ssram_a<14> LOC = W5; -NET sys_flash_ssram_a<13> LOC = W6; -NET sys_flash_ssram_a<12> LOC = W3; -NET sys_flash_ssram_a<11> LOC = AF3; -NET sys_flash_ssram_a<10> LOC = AE3; -NET sys_flash_ssram_a<9> LOC = AD2; -NET sys_flash_ssram_a<8> LOC = AD1; -NET sys_flash_ssram_a<7> LOC = AC2; -NET sys_flash_ssram_a<6> LOC = AC1; -NET sys_flash_ssram_a<5> LOC = AB2; -NET sys_flash_ssram_a<4> LOC = AB1; -NET sys_flash_ssram_a<3> LOC = AA1; -NET sys_flash_ssram_a<2> LOC = Y2; -NET sys_flash_ssram_a<1> LOC = Y1; -NET sys_flash_ssram_a<0> LOC = T20; -NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_a<*> SLEW = FAST; -NET sys_flash_ssram_a<*> DRIVE = 8; - - -NET sys_flash_ssram_d<31> LOC = F14; -NET sys_flash_ssram_d<30> LOC = F13; -NET sys_flash_ssram_d<29> LOC = F12; -NET sys_flash_ssram_d<28> LOC = F11; -NET sys_flash_ssram_d<27> LOC = F16; -NET sys_flash_ssram_d<26> LOC = F15; -NET sys_flash_ssram_d<25> LOC = D14; -NET sys_flash_ssram_d<24> LOC = D13; -NET sys_flash_ssram_d<23> LOC = D15; -NET sys_flash_ssram_d<22> LOC = E14; -NET sys_flash_ssram_d<21> LOC = C11; -NET sys_flash_ssram_d<20> LOC = D11; -NET sys_flash_ssram_d<19> LOC = D16; -NET sys_flash_ssram_d<18> LOC = C16; -NET sys_flash_ssram_d<17> LOC = E13; -NET sys_flash_ssram_d<16> LOC = D12; -NET sys_flash_ssram_d<15> LOC = AA14; -NET sys_flash_ssram_d<14> LOC = AB14; -NET sys_flash_ssram_d<13> LOC = AC12; -NET sys_flash_ssram_d<12> LOC = AC11; -NET sys_flash_ssram_d<11> LOC = AA16; -NET sys_flash_ssram_d<10> LOC = AA15; -NET sys_flash_ssram_d<9> LOC = AB13; -NET sys_flash_ssram_d<8> LOC = AA13; -NET sys_flash_ssram_d<7> LOC = AC14; -NET sys_flash_ssram_d<6> LOC = AD14; -NET sys_flash_ssram_d<5> LOC = AA12; -NET sys_flash_ssram_d<4> LOC = AA11; -NET sys_flash_ssram_d<3> LOC = AC16; -NET sys_flash_ssram_d<2> LOC = AC15; -NET sys_flash_ssram_d<1> LOC = AC13; -NET sys_flash_ssram_d<0> LOC = AD13; -NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_ssram_d<*> DRIVE = 12; -NET sys_flash_ssram_d<*> SLEW = FAST; -NET sys_flash_ssram_d<*> PULLDOWN; - -NET sys_flash_ssram_oe_n LOC = AC6; -NET sys_flash_ssram_oe_n IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_oe_n SLEW = FAST; -NET sys_flash_ssram_oe_n DRIVE = 8; - -NET sys_flash_ssram_we_n LOC = AB6; -NET sys_flash_ssram_we_n IOSTANDARD = LVDCI_33; -NET sys_flash_ssram_we_n SLEW = FAST; -NET sys_flash_ssram_we_n DRIVE = 8; - -NET sys_flash_ce LOC = W7; -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_rstn LOC = AD10; -NET sys_flash_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_rstn DRIVE = 8; -NET sys_flash_rstn SLEW = FAST; -NET sys_flash_rstn TIG; - -NET sys_flash_byten LOC = N22; -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# SSRAM -NET sys_ssram_clk LOC = AF7; -NET sys_ssram_clk IOSTANDARD = LVCMOS33; -NET sys_ssram_clk DRIVE = 16; -NET sys_ssram_clk SLEW = FAST; - -NET "sys_ssram_clk" TNM_NET = "ssram_clk"; -#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %; - - -NET sys_ssram_clk_fb LOC = AD17; -NET sys_ssram_clk_fb IOSTANDARD = LVCMOS33; - -# Timing Constraint for Feedback Clock -NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk; - -NET sys_ssram_ce_n LOC = V7; -NET sys_ssram_ce_n IOSTANDARD = LVDCI_33; -NET sys_ssram_ce_n SLEW = FAST; -NET sys_ssram_ce_n DRIVE = 8; - -NET sys_ssram_bw_n<3> LOC = Y3; #Y4; -NET sys_ssram_bw_n<2> LOC = Y4; #Y3; -NET sys_ssram_bw_n<1> LOC = Y5; #Y6; -NET sys_ssram_bw_n<0> LOC = Y6; #Y5; -NET sys_ssram_bw_n<*> IOSTANDARD = LVDCI_33; -NET sys_ssram_bw_n<*> SLEW = FAST; -NET sys_ssram_bw_n<*> DRIVE = 8; - -NET sys_ssram_adv LOC = W4; -NET sys_ssram_adv IOSTANDARD = LVDCI_33; -NET sys_ssram_adv SLEW = FAST; -NET sys_ssram_adv DRIVE = 8; - -NET sys_ssram_mode LOC = V26; -NET sys_ssram_mode IOSTANDARD = LVDCI_33; -NET sys_ssram_mode SLEW = FAST; -NET sys_ssram_mode DRIVE = 8; - - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf deleted file mode 100644 index 0eab88d..0000000 --- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf +++ /dev/null @@ -1,523 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %; - -NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "rst" TIG; - -NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; - -NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE; -PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; - -INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ; -# GOOD 1 -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ; - -# GOOD 2 (smaller) -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ; - -# GOOD 3 (even smaller) -#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ; -#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ; - -# GOOD 4 (even more smaller) -AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ; -AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_uart0_rx LOC = W2; -NET sys_uart0_rx IOSTANDARD = LVCMOS33; -NET sys_uart0_rx TIG; -NET sys_uart0_tx LOC = W1; -NET sys_uart0_tx IOSTANDARD = LVCMOS33; -NET sys_uart0_tx TIG; - -NET sys_uart1_rx LOC = AF24; -NET sys_uart1_rx IOSTANDARD = LVCMOS33; -NET sys_uart1_rx TIG; -NET sys_uart1_tx LOC = AE24; -NET sys_uart1_tx IOSTANDARD = LVCMOS33; -NET sys_uart1_tx TIG; - -NET sys_uart2_rx LOC = AD22; -NET sys_uart2_rx IOSTANDARD = LVCMOS33; -NET sys_uart2_rx TIG; -NET sys_uart2_tx LOC = AB21; -NET sys_uart2_tx IOSTANDARD = LVCMOS33; -NET sys_uart2_tx TIG; - -NET sys_uart3_rx LOC = W20; -NET sys_uart3_rx IOSTANDARD = LVCMOS33; -NET sys_uart3_rx TIG; -NET sys_uart3_tx LOC = W21; -NET sys_uart3_tx IOSTANDARD = LVCMOS33; -NET sys_uart3_tx TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; -NET sys_usb_d<*> IOBDELAY = NONE; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_a<24> LOC = T21; -NET sys_flash_a<23> LOC = U20; -NET sys_flash_a<22> LOC = T19; -NET sys_flash_a<21> LOC = AC5; -NET sys_flash_a<20> LOC = AB5; -NET sys_flash_a<19> LOC = AC4; -NET sys_flash_a<18> LOC = AB4; -NET sys_flash_a<17> LOC = AB3; -NET sys_flash_a<16> LOC = AA4; -NET sys_flash_a<15> LOC = AA3; -NET sys_flash_a<14> LOC = W5; -NET sys_flash_a<13> LOC = W6; -NET sys_flash_a<12> LOC = W3; -NET sys_flash_a<11> LOC = AF3; -NET sys_flash_a<10> LOC = AE3; -NET sys_flash_a<9> LOC = AD2; -NET sys_flash_a<8> LOC = AD1; -NET sys_flash_a<7> LOC = AC2; -NET sys_flash_a<6> LOC = AC1; -NET sys_flash_a<5> LOC = AB2; -NET sys_flash_a<4> LOC = AB1; -NET sys_flash_a<3> LOC = AA1; -NET sys_flash_a<2> LOC = Y2; -NET sys_flash_a<1> LOC = Y1; -NET sys_flash_a<0> LOC = T20; - -NET sys_flash_d<31> LOC = F14; -NET sys_flash_d<30> LOC = F13; -NET sys_flash_d<29> LOC = F12; -NET sys_flash_d<28> LOC = F11; -NET sys_flash_d<27> LOC = F16; -NET sys_flash_d<26> LOC = F15; -NET sys_flash_d<25> LOC = D14; -NET sys_flash_d<24> LOC = D13; -NET sys_flash_d<23> LOC = D15; -NET sys_flash_d<22> LOC = E14; -NET sys_flash_d<21> LOC = C11; -NET sys_flash_d<20> LOC = D11; -NET sys_flash_d<19> LOC = D16; -NET sys_flash_d<18> LOC = C16; -NET sys_flash_d<17> LOC = E13; -NET sys_flash_d<16> LOC = D12; -NET sys_flash_d<15> LOC = AA14; -NET sys_flash_d<14> LOC = AB14; -NET sys_flash_d<13> LOC = AC12; -NET sys_flash_d<12> LOC = AC11; -NET sys_flash_d<11> LOC = AA16; -NET sys_flash_d<10> LOC = AA15; -NET sys_flash_d<9> LOC = AB13; -NET sys_flash_d<8> LOC = AA13; -NET sys_flash_d<7> LOC = AC14; -NET sys_flash_d<6> LOC = AD14; -NET sys_flash_d<5> LOC = AA12; -NET sys_flash_d<4> LOC = AA11; -NET sys_flash_d<3> LOC = AC16; -NET sys_flash_d<2> LOC = AC15; -NET sys_flash_d<1> LOC = AC13; -NET sys_flash_d<0> LOC = AD13; -NET sys_flash_rdn LOC = AC6; -NET sys_flash_wrn LOC = AB6; -NET sys_flash_ce LOC = W7; -NET sys_flash_ac97_rstn LOC = AD10; -NET sys_flash_byten LOC = N22; - -NET sys_flash_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_a<*> SLEW = FAST; -NET sys_flash_a<*> DRIVE = 8; - -NET sys_flash_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_d<*> DRIVE = 12; -NET sys_flash_d<*> SLEW = FAST; -NET sys_flash_d<*> IOBDELAY = NONE; -NET sys_flash_d<*> PULLDOWN; - -NET sys_flash_rdn IOSTANDARD = LVDCI_33; -NET sys_flash_rdn SLEW = FAST; -NET sys_flash_rdn DRIVE = 8; - -NET sys_flash_wrn IOSTANDARD = LVDCI_33; -NET sys_flash_wrn SLEW = FAST; -NET sys_flash_wrn DRIVE = 8; - -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_ac97_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_ac97_rstn DRIVE = 8; -NET sys_flash_ac97_rstn SLEW = FAST; -NET sys_flash_ac97_rstn TIG; - -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for AC97 Sound Controller -#------------------------------------------------------------------------------ -NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk"; -TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %; - -NET sys_ac97_bit_clk LOC = AE10; -NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33; -NET sys_ac97_bit_clk PERIOD = 80; -NET sys_ac97_sdata_in LOC = AD16; -NET sys_ac97_sdata_in IOSTANDARD = LVCMOS33; -NET sys_ac97_sdata_out LOC = C8; -NET sys_ac97_sdata_out SLEW = FAST; -NET sys_ac97_ssync LOC = D9; -NET sys_ac97_ssync SLEW = FAST; diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj deleted file mode 100644 index 0916a32..0000000 --- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj +++ /dev/null @@ -1,43 +0,0 @@ -vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vhdl work "../../src/sdram_config.vhd" -vhdl work "../../../../lib/misc/utils_pkg.vhd" -vhdl work "../../../../lib/misc/dpram_1w1r.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd" -vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" -vhdl work "../../../../lib/uart/kcuart_tx.vhd" -vhdl work "../../../../lib/uart/kcuart_rx.vhd" -vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" -vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd" -vhdl work "../../src/sys_types.vhd" -vhdl work "../../src/ram_ld.vhd" -vhdl work "../../src/bootloader.ROM_ld.vhd" -vhdl work "../../../../lib/uart/uart_tx.vhd" -vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" -vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vhdl work "../../../../lib/uart/uart_wb.vhd" -vhdl work "../../../../lib/misc/rom_wb.vhd" -vhdl work "../../../../lib/misc/ram_wb.vhd" -vhdl work "../../../../lib/misc/lcd_port.vhd" -vhdl work "../../../../lib/misc/gpio_wb.vhd" -vhdl work "../../../../lib/misc/clockgen_virtex4.vhd" -vhdl work "../../../../lib/misc/async_port_wb.vhd" -vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" -vhdl work "../../src/mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj deleted file mode 100644 index 49db644..0000000 --- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj +++ /dev/null @@ -1,43 +0,0 @@ -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" -vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" -vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd" -vhdl work "W:\vhdl\lib\uart\uart_tx.vhd" -vhdl work "W:\vhdl\lib\uart\uart_rx.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" -vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd" -vhdl work "W:\vhdl\lib\uart\uart_wb.vhd" -vhdl work "W:\vhdl\lib\misc\rom_wb.vhd" -vhdl work "W:\vhdl\lib\misc\ram_wb.vhd" -vhdl work "W:\vhdl\lib\misc\lcd_port.vhd" -vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd" -vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd" -vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd" -vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd" diff --git a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf deleted file mode 100644 index 07b8d92..0000000 --- a/projects/mips_sys/ise92/mips_sys/ucf/systest.ucf +++ /dev/null @@ -1,469 +0,0 @@ -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE. -# -# (c) Copyright 2005 Xilinx, Inc. -# All rights reserved. -# - -CONFIG STEPPING = "ES"; - -# Bus clock nets -NET "clk" TNM_NET = "clk"; -TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %; - -NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG; - -NET "sys_clk_in" LOC = "AE14"; -NET sys_clk_in IOSTANDARD = LVCMOS33; -NET "sys_rst_n_in" LOC = "D6"; -NET sys_rst_n_in PULLUP; -NET "sys_rst_n_in" TIG; -NET "rst" TIG; - -# Locate DCM/BUFG - Tools can probably figure them out automatically -# but just LOC them down to be safe -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2; -#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1; - -# GOOD -INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ; -AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ; -AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ; - -//////////////////////////////////////////////////////////////////////////// -// Misc Board Signals -//////////////////////////////////////////////////////////////////////////// - -NET sys_error<0> LOC = V6; -NET sys_error<1> LOC = L24; -NET sys_error<*> IOSTANDARD = LVCMOS33; -NET sys_error<*> DRIVE = 2; -NET sys_error<*> TIG; - -//////////////////////////////////////////////////////////////////////////// -// RS-232 -//////////////////////////////////////////////////////////////////////////// -NET sys_rx LOC = W2; -NET sys_rx IOSTANDARD = LVCMOS33; -NET sys_rx TIG; -NET "sys_tx" LOC = "W1"; -NET sys_tx IOSTANDARD = LVCMOS33; -NET "sys_tx" TIG; - -//////////////////////////////////////////////////////////////////////////// -// Buttons, LEDs, and DIP Switches -//////////////////////////////////////////////////////////////////////////// -# GPLED 0-3 -NET "sys_led<0>" LOC = "G5"; #GPLED0 -NET "sys_led<1>" LOC = "G6"; #GPLED1 -NET "sys_led<2>" LOC = "A11"; #GPLED2 -NET "sys_led<3>" LOC = "A12"; #GPLED3 -# North-East-South-West-Center LEDs -NET "sys_led<4>" LOC = "F9"; # W LED -NET "sys_led<5>" LOC = "E2"; # N LED -NET "sys_led<6>" LOC = "E10"; # E LED -NET "sys_led<7>" LOC = "A5"; # S LED -NET "sys_led<8>" LOC = "C6"; # C LED -NET "sys_led<*>" TIG; -NET "sys_led<*>" SLEW = SLOW; -NET "sys_led<*>" DRIVE = 2; -#NET "sys_led<*>" IOSTANDARD = LVCMOS33; -# North-East-South-West-Center Buttons -NET "sys_btn<0>" LOC = "E9"; # W Button -NET "sys_btn<1>" LOC = "E7"; # N Button -NET "sys_btn<2>" LOC = "F10"; # E Button -NET "sys_btn<3>" LOC = "A6"; # S Button -NET "sys_btn<4>" LOC = "B6"; # C Button -NET "sys_btn<*>" TIG; -NET "sys_btn<*>" PULLDOWN; -#NET "sys_btn<*>" IOSTANDARD = LVCMOS33; -# Dip Switches 1-8 -NET "sys_dip<7>" LOC = "U24"; # DIP SW 8 -NET "sys_dip<6>" LOC = "U25"; # DIP SW 7 -NET "sys_dip<5>" LOC = "V23"; # DIP SW 6 -NET "sys_dip<4>" LOC = "U23"; # DIP SW 5 -NET "sys_dip<3>" LOC = "U26"; # DIP SW 4 -NET "sys_dip<2>" LOC = "T26"; # DIP SW 3 -NET "sys_dip<1>" LOC = "R19"; # DIP SW 2 -NET "sys_dip<0>" LOC = "R20"; # DIP SW 1 -NET "sys_dip<*>" PULLDOWN; -NET "sys_dip<*>" IOSTANDARD = LVCMOS33; -NET "sys_dip<*>" TIG; -//////////////////////////////////////////////////////////////////////////// -// LCD -//////////////////////////////////////////////////////////////////////////// -NET sys_lcd_e LOC = AE13; # LCD_E -NET sys_lcd_e IOSTANDARD = LVCMOS33; -NET sys_lcd_e SLEW = SLOW; -NET sys_lcd_e DRIVE = 2; -NET sys_lcd_e TIG; -NET sys_lcd_rs LOC = AC17; # LCD_RS -NET sys_lcd_rs IOSTANDARD = LVCMOS33; -NET sys_lcd_rs SLEW = SLOW; -NET sys_lcd_rs DRIVE = 2; -NET sys_lcd_rs TIG; -NET sys_lcd_rw LOC = AB17; # LCD_RW -NET sys_lcd_rw IOSTANDARD = LVCMOS33; -NET sys_lcd_rw SLEW = SLOW; -NET sys_lcd_rw DRIVE = 2; -NET sys_lcd_rw TIG; -NET sys_lcd_d<3> LOC = AF12; # LCD_DB7 -NET sys_lcd_d<2> LOC = AE12; # LCD_DB6 -NET sys_lcd_d<1> LOC = AC10; # LCD_DB5 -NET sys_lcd_d<0> LOC = AB10; # LCD_DB4 -NET sys_lcd_d<*> IOSTANDARD = LVCMOS33; -NET sys_lcd_d<*> SLEW = SLOW; -NET sys_lcd_d<*> DRIVE = 2; -NET sys_lcd_d<*> PULLDOWN; -NET sys_lcd_d<*> TIG; - -#------------------------------------------------------------------------------ -# IO Pad Location Constraints / Properties for DDR Controllers -#------------------------------------------------------------------------------ - -NET sys_sdr_a_q<0> LOC = C26; # DDR_A0 -NET sys_sdr_a_q<1> LOC = E17; # DDR_A1 -NET sys_sdr_a_q<2> LOC = D18; # DDR_A2 -NET sys_sdr_a_q<3> LOC = C19; # DDR_A3 -NET sys_sdr_a_q<4> LOC = F17; # DDR_A4 -NET sys_sdr_a_q<5> LOC = B18; # DDR_A5 -NET sys_sdr_a_q<6> LOC = B20; # DDR_A6 -NET sys_sdr_a_q<7> LOC = C20; # DDR_A7 -NET sys_sdr_a_q<8> LOC = D20; # DDR_A8 -NET sys_sdr_a_q<9> LOC = C21; # DDR_A9 -NET sys_sdr_a_q<10> LOC = A18; # DDR_A10 -NET sys_sdr_a_q<11> LOC = B21; # DDR_A11 -NET sys_sdr_a_q<12> LOC = A24; # DDR_A12 -NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0 -NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1 -NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N -NET sys_sdr_cke_q LOC = G22; # DDR_CKE -NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N -NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N -NET sys_sdr_we_qn LOC = A23; # DDR_WE_N - -NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P -NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK) -NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N - -NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0 -NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1 -NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2 -NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3 - -NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0 -NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1 -NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2 -NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3 - -NET sys_sdr_data<0> LOC = H20; # DDR_D0 -NET sys_sdr_data<1> LOC = E23; # DDR_D1 -NET sys_sdr_data<2> LOC = H26; # DDR_D2 -NET sys_sdr_data<3> LOC = H22; # DDR_D3 -NET sys_sdr_data<4> LOC = E25; # DDR_D4 -NET sys_sdr_data<5> LOC = E26; # DDR_D5 -NET sys_sdr_data<6> LOC = F26; # DDR_D6 -NET sys_sdr_data<7> LOC = E24; # DDR_D7 -NET sys_sdr_data<8> LOC = E20; # DDR_D8 -NET sys_sdr_data<9> LOC = A22; # DDR_D9 -NET sys_sdr_data<10> LOC = C23; # DDR_D10 -NET sys_sdr_data<11> LOC = C24; # DDR_D11 -NET sys_sdr_data<12> LOC = A20; # DDR_D12 -NET sys_sdr_data<13> LOC = A21; # DDR_D13 -NET sys_sdr_data<14> LOC = D24; # DDR_D14 -NET sys_sdr_data<15> LOC = E18; # DDR_D15 -NET sys_sdr_data<16> LOC = F18; # DDR_D16 -NET sys_sdr_data<17> LOC = A19; # DDR_D17 -NET sys_sdr_data<18> LOC = F19; # DDR_D18 -NET sys_sdr_data<19> LOC = B23; # DDR_D19 -NET sys_sdr_data<20> LOC = E21; # DDR_D20 -NET sys_sdr_data<21> LOC = D22; # DDR_D21 -NET sys_sdr_data<22> LOC = D23; # DDR_D22 -NET sys_sdr_data<23> LOC = B24; # DDR_D23 -NET sys_sdr_data<24> LOC = E22; # DDR_D24 -NET sys_sdr_data<25> LOC = F20; # DDR_D25 -NET sys_sdr_data<26> LOC = H23; # DDR_D26 -NET sys_sdr_data<27> LOC = G25; # DDR_D27 -NET sys_sdr_data<28> LOC = G26; # DDR_D28 -NET sys_sdr_data<29> LOC = H25; # DDR_D29 -NET sys_sdr_data<30> LOC = H24; # DDR_D30 -NET sys_sdr_data<31> LOC = H21; # DDR_D31 - -NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_a_q<*> FAST; - -NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I; -NET sys_sdr_ba_q<*> FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cke_q IOSTANDARD = SSTL2_I; -NET sys_sdr_cke_q FAST; - -NET sys_sdr_clk_p IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_p FAST; -NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25; -NET sys_sdr_clk_fb IOBDELAY = NONE; -NET sys_sdr_clk_n IOSTANDARD = SSTL2_I; -NET sys_sdr_clk_n FAST; - -NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cas_qn FAST; - -NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_cs_qn FAST; - -NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_ras_qn FAST; - -NET sys_sdr_we_qn IOSTANDARD = SSTL2_I; -NET sys_sdr_we_qn FAST; - -NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dqs_q<*> IOBDELAY = NONE; -NET sys_sdr_dqs_q<*> FAST; - -NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_dm_q<*> IOBDELAY = NONE; -NET sys_sdr_dm_q<*> FAST; - -NET sys_sdr_data<*> IOSTANDARD = SSTL2_II; -NET sys_sdr_data<*> IOBDELAY = NONE; -NET sys_sdr_data<*> FAST; - -#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n"; - -NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p"; -NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n"; - -# Timing Constraint for DDR Feedback Clock -NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p; - -# USB -NET sys_usb_a<0> LOC = Y10; -NET sys_usb_a<1> LOC = AA10; -NET sys_usb_a<*> IOSTANDARD = LVCMOS33; - -NET sys_usb_d<0> LOC = AB7; -NET sys_usb_d<1> LOC = AC9; -NET sys_usb_d<2> LOC = AB9; -NET sys_usb_d<3> LOC = AE6; -NET sys_usb_d<4> LOC = AD6; -NET sys_usb_d<5> LOC = AF9; -NET sys_usb_d<6> LOC = AE9; -NET sys_usb_d<7> LOC = AD8; -NET sys_usb_d<8> LOC = AC8; -NET sys_usb_d<9> LOC = AF4; -NET sys_usb_d<10> LOC = AE4; -NET sys_usb_d<11> LOC = AD3; -NET sys_usb_d<12> LOC = AC3; -NET sys_usb_d<13> LOC = AF6; -NET sys_usb_d<14> LOC = AF5; -NET sys_usb_d<15> LOC = AA7; -NET sys_usb_d<*> IOSTANDARD = LVCMOS33; -NET sys_usb_d<*> SLEW = FAST; -NET sys_usb_d<*> DRIVE = 8; -NET sys_usb_d<*> PULLDOWN; - -NET sys_usb_rdn LOC = AA8; -NET sys_usb_rdn IOSTANDARD = LVCMOS33; -NET sys_usb_rdn SLEW = FAST; -NET sys_usb_rdn DRIVE = 8; - -NET sys_usb_wrn LOC = Y8; -NET sys_usb_wrn IOSTANDARD = LVCMOS33; -NET sys_usb_wrn SLEW = FAST; -NET sys_usb_wrn DRIVE = 8; - -NET sys_usb_csn LOC = AF10; -NET sys_usb_csn IOSTANDARD = LVCMOS33; -NET sys_usb_csn SLEW = FAST; -NET sys_usb_csn DRIVE = 8; - -NET sys_usb_rstn LOC = A7; -NET sys_usb_rstn IOSTANDARD = LVCMOS25; -NET sys_usb_rstn TIG; - -NET sys_usb_int LOC = V5; -NET sys_usb_int IOSTANDARD = LVCMOS33; -NET sys_usb_int PULLDOWN; -NET sys_usb_int TIG; - -# FLASH -NET sys_flash_a<24> LOC = T21; -NET sys_flash_a<23> LOC = U20; -NET sys_flash_a<22> LOC = T19; -NET sys_flash_a<21> LOC = AC5; -NET sys_flash_a<20> LOC = AB5; -NET sys_flash_a<19> LOC = AC4; -NET sys_flash_a<18> LOC = AB4; -NET sys_flash_a<17> LOC = AB3; -NET sys_flash_a<16> LOC = AA4; -NET sys_flash_a<15> LOC = AA3; -NET sys_flash_a<14> LOC = W5; -NET sys_flash_a<13> LOC = W6; -NET sys_flash_a<12> LOC = W3; -NET sys_flash_a<11> LOC = AF3; -NET sys_flash_a<10> LOC = AE3; -NET sys_flash_a<9> LOC = AD2; -NET sys_flash_a<8> LOC = AD1; -NET sys_flash_a<7> LOC = AC2; -NET sys_flash_a<6> LOC = AC1; -NET sys_flash_a<5> LOC = AB2; -NET sys_flash_a<4> LOC = AB1; -NET sys_flash_a<3> LOC = AA1; -NET sys_flash_a<2> LOC = Y2; -NET sys_flash_a<1> LOC = Y1; -NET sys_flash_a<0> LOC = T20; - -NET sys_flash_d<31> LOC = F14; -NET sys_flash_d<30> LOC = F13; -NET sys_flash_d<29> LOC = F12; -NET sys_flash_d<28> LOC = F11; -NET sys_flash_d<27> LOC = F16; -NET sys_flash_d<26> LOC = F15; -NET sys_flash_d<25> LOC = D14; -NET sys_flash_d<24> LOC = D13; -NET sys_flash_d<23> LOC = D15; -NET sys_flash_d<22> LOC = E14; -NET sys_flash_d<21> LOC = C11; -NET sys_flash_d<20> LOC = D11; -NET sys_flash_d<19> LOC = D16; -NET sys_flash_d<18> LOC = C16; -NET sys_flash_d<17> LOC = E13; -NET sys_flash_d<16> LOC = D12; -NET sys_flash_d<15> LOC = AA14; -NET sys_flash_d<14> LOC = AB14; -NET sys_flash_d<13> LOC = AC12; -NET sys_flash_d<12> LOC = AC11; -NET sys_flash_d<11> LOC = AA16; -NET sys_flash_d<10> LOC = AA15; -NET sys_flash_d<9> LOC = AB13; -NET sys_flash_d<8> LOC = AA13; -NET sys_flash_d<7> LOC = AC14; -NET sys_flash_d<6> LOC = AD14; -NET sys_flash_d<5> LOC = AA12; -NET sys_flash_d<4> LOC = AA11; -NET sys_flash_d<3> LOC = AC16; -NET sys_flash_d<2> LOC = AC15; -NET sys_flash_d<1> LOC = AC13; -NET sys_flash_d<0> LOC = AD13; -NET sys_flash_rdn LOC = AC6; -NET sys_flash_wrn LOC = AB6; -NET sys_flash_ce LOC = W7; -NET sys_flash_rstn LOC = AD10; -NET sys_flash_byten LOC = N22; - -NET sys_flash_a<*> IOSTANDARD = LVDCI_33; -NET sys_flash_a<*> SLEW = FAST; -NET sys_flash_a<*> DRIVE = 8; - -NET sys_flash_d<*> IOSTANDARD = LVCMOS33; -NET sys_flash_d<*> DRIVE = 12; -NET sys_flash_d<*> SLEW = FAST; -NET sys_flash_d<*> PULLDOWN; - -NET sys_flash_rdn IOSTANDARD = LVDCI_33; -NET sys_flash_rdn SLEW = FAST; -NET sys_flash_rdn DRIVE = 8; - -NET sys_flash_wrn IOSTANDARD = LVDCI_33; -NET sys_flash_wrn SLEW = FAST; -NET sys_flash_wrn DRIVE = 8; - -NET sys_flash_ce IOSTANDARD = LVDCI_33; -NET sys_flash_ce SLEW = FAST; -NET sys_flash_ce DRIVE = 8; - -NET sys_flash_rstn IOSTANDARD = LVCMOS33; -NET sys_flash_rstn DRIVE = 8; -NET sys_flash_rstn SLEW = FAST; -NET sys_flash_rstn TIG; - -NET sys_flash_byten IOSTANDARD = LVCMOS33; -NET sys_flash_byten DRIVE = 8; -NET sys_flash_byten SLEW = FAST; -NET sys_flash_byten TIG; - -# VGA -NET sys_vga_blue<0> LOC = M21; # VGA_B0 -NET sys_vga_blue<1> LOC = M26; # VGA_B1 -NET sys_vga_blue<2> LOC = L26; # VGA_B2 -NET sys_vga_blue<3> LOC = C5; # VGA_B3 -NET sys_vga_blue<4> LOC = C7; # VGA_B4 -NET sys_vga_blue<5> LOC = B7; # VGA_B5 -NET sys_vga_blue<6> LOC = G8; # VGA_B6 -NET sys_vga_blue<7> LOC = F8; # VGA_B7 -NET sys_vga_blue<0> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<1> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<2> IOSTANDARD = LVCMOS33; -NET sys_vga_blue<*> SLEW = FAST; -NET sys_vga_blue<*> DRIVE = 8; - -NET sys_vga_clk LOC = AF8; -NET sys_vga_clk IOSTANDARD = LVDCI_33; -NET sys_vga_clk SLEW = FAST; -NET sys_vga_clk DRIVE = 8; - -NET sys_vga_green<0> LOC = M22; # VGA_G0 -NET sys_vga_green<1> LOC = M23; # VGA_G1 -NET sys_vga_green<2> LOC = M20; # VGA_G2 -NET sys_vga_green<3> LOC = E4; # VGA_G3 -NET sys_vga_green<4> LOC = D3; # VGA_G4 -NET sys_vga_green<5> LOC = H7; # VGA_G5 -NET sys_vga_green<6> LOC = H8; # VGA_G6 -NET sys_vga_green<7> LOC = C1; # VGA_G7 -NET sys_vga_green<0> IOSTANDARD = LVCMOS33; -NET sys_vga_green<1> IOSTANDARD = LVCMOS33; -NET sys_vga_green<2> IOSTANDARD = LVCMOS33; -NET sys_vga_green<*> SLEW = FAST; -NET sys_vga_green<*> DRIVE = 8; - -NET sys_vga_hsync LOC = C10; -NET sys_vga_hsync SLEW = FAST; -NET sys_vga_hsync DRIVE = 8; -#NET sys_vga_hsync IOSTANDARD = LVCMOS33; - -NET sys_vga_red<0> LOC = N23; #VGA_R0 -NET sys_vga_red<1> LOC = N24; #VGA_R1 -NET sys_vga_red<2> LOC = N25; #VGA_R2 -NET sys_vga_red<3> LOC = C2; #VGA_R3 -NET sys_vga_red<4> LOC = G7; #VGA_R4 -NET sys_vga_red<5> LOC = F7; #VGA_R5 -NET sys_vga_red<6> LOC = E5; #VGA_R6 -NET sys_vga_red<7> LOC = E6; #VGA_R7 -NET sys_vga_red<0> IOSTANDARD = LVCMOS33; -NET sys_vga_red<1> IOSTANDARD = LVCMOS33; -NET sys_vga_red<2> IOSTANDARD = LVCMOS33; -NET sys_vga_red<*> SLEW = FAST; -NET sys_vga_red<*> DRIVE = 8; - -NET sys_vga_vsync LOC = A8; -NET sys_vga_vsync SLEW = FAST; -NET sys_vga_vsync DRIVE = 8; -#NET sys_vga_vsync IOSTANDARD = LVCMOS33; - -NET sys_vga_blank_n LOC = M24; -NET sys_vga_blank_n SLEW = FAST; -NET sys_vga_blank_n DRIVE = 8; -NET sys_vga_blank_n IOSTANDARD = LVCMOS33; - -NET sys_vga_sync_n LOC = L23; -NET sys_vga_sync_n SLEW = FAST; -NET sys_vga_sync_n DRIVE = 8; -NET sys_vga_sync_n IOSTANDARD = LVCMOS33; diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo deleted file mode 100644 index a040e2f..0000000 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ /dev/null @@ -1,101 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -# Configs -vcom -explicit -93 "../src/sdram_config_sim.vhd" - -# Packages -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" -vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" - -# RAMs -vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" -vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" - -# FIFOS -vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd" - -# CPU -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd" -vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd" -vcom -explicit -93 "../src/bootloader.ROM.vhd" -vcom -explicit -93 "../../../lib/misc/rom_wb.vhd" - -# VGA -vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd" -vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd" - -# UART -vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_rx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_tx.vhd" -vcom -explicit -93 "../../../lib/uart/uart_wb.vhd" - -# GPIO -vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd" - -# LCD -vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" - -# Flash and USB -vcom -explicit -93 "../../../lib/misc/async_types.vhd" -vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd" -vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd" -vcom -explicit -93 "../src/async_defs.vhd" - -# Sync SRAM -vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd" -vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" - -# SDRAM -vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" - -# AC-97 -vcom -explicit -93 "../../../lib/misc/singleshot.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd" -vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd" - -# Top and TB -vcom -explicit -93 "../src/mips_sys_sim.vhd" -vcom -explicit -93 "../src/tb_mips_sys.vhd" - -vsim -t 1ps -lib work tb_mips_sys -do {tb_mips_sys.wdo} -view wave -view structure -view signals -run 50ms diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo deleted file mode 100644 index e2e249e..0000000 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ /dev/null @@ -1,213 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_mips_sys/uut/rst -add wave -noupdate -format Logic /tb_mips_sys/uut/nmi -add wave -noupdate -format Logic /tb_mips_sys/uut/rst_in -add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in -add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in -add wave -noupdate -format Literal /tb_mips_sys/dip -add wave -noupdate -format Literal /tb_mips_sys/btn -add wave -noupdate -format Literal /tb_mips_sys/led -add wave -noupdate -format Logic /tb_mips_sys/sys_rx -add wave -noupdate -format Logic /tb_mips_sys/sys_tx -add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs -add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw -add wave -noupdate -format Logic /tb_mips_sys/refresh -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn -add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q -add wave -noupdate -format Literal /tb_mips_sys/sys_error -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o -add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -divider Arbiter -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req -add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt -add wave -noupdate -divider AC97 -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk -add wave -noupdate -format Logic /tb_mips_sys/ac_synced -add wave -noupdate -divider {CPU Master} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu -add wave -noupdate -divider {VGA Master} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga -add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga -add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga -add wave -noupdate -divider BUI -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op -add wave -noupdate -divider USB -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn -add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s -add wave -noupdate -divider Flash -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a -add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv -add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy -add wave -noupdate -divider {Sync SRAM} -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n -add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv -add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode -add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv -add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy -add wave -noupdate -divider {MIPS TOP} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -divider {CPU DMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -divider {CPU IMEM} -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -divider {User ROM} -add wave -noupdate -divider UUT -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q -add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn -add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn -add wave -noupdate -divider I-Cache -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch -add wave -noupdate -divider D-Cache -add wave -noupdate -format Logic /tb_mips_sys/uut/clk -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {0 ps} 0} {{Cursor 100} {0 ps} 0} -configure wave -namecolwidth 187 -configure wave -valuecolwidth 64 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {27462813 ns} diff --git a/projects/mips_sys/src/.directory_history b/projects/mips_sys/src/.directory_history deleted file mode 100644 index 2f56f3d..0000000 --- a/projects/mips_sys/src/.directory_history +++ /dev/null @@ -1,4 +0,0 @@ -VHDL/projects/mips_sys/src/async_defs.vhd - -VHDL/projects/mips_sys/src/sys_types.vhd -VHDL/projects/mips_sys/src/async_defs.vhd diff --git a/projects/mips_sys/src/bootloader.ROM.vhd b/projects/mips_sys/src/bootloader.ROM.vhd deleted file mode 100644 index 506d76d..0000000 --- a/projects/mips_sys/src/bootloader.ROM.vhd +++ /dev/null @@ -1,2082 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - constant word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A112C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 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00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - -end data; diff --git a/projects/mips_sys/src/bootloader.ROM_ld.vhd b/projects/mips_sys/src/bootloader.ROM_ld.vhd deleted file mode 100644 index 735d7ef..0000000 --- a/projects/mips_sys/src/bootloader.ROM_ld.vhd +++ /dev/null @@ -1,2174 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"3C1D8000", -- 00000000 - X"27BDEFF0", -- 00000004 - X"3C1A1040", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"241A0000", -- 00000014 - X"409A6800", -- 00000018 - X"401A7800", -- 0000001C - X"00000000", -- 00000020 - X"409AF800", -- 00000024 - X"42000020", -- 00000028 - X"42000022", -- 0000002C - X"3C1ABFC0", -- 00000030 - X"275A005C", -- 00000034 - X"0340F809", -- 00000038 - X"00000000", -- 0000003C - X"3C1ABFC0", -- 00000040 - X"275A112C", -- 00000044 - X"0340F809", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"0BF00014", -- 00000054 - X"00000000", -- 00000058 - X"3C1AA001", -- 0000005C - X"275A0008", -- 00000060 - X"241B000D", -- 00000064 - X"AF5B0000", -- 00000068 - X"03E00008", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1BC000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"3C1BA000", -- 00000194 - X"277B0000", -- 00000198 - X"AF7A0000", -- 0000019C - X"401A6800", -- 000001A0 - X"00000000", -- 000001A4 - X"001AD202", -- 000001A8 - X"335A00FF", -- 000001AC - X"1740FFFB", -- 000001B0 - X"00000000", -- 000001B4 - X"401A7000", -- 000001B8 - X"00000000", -- 000001BC - X"03400008", -- 000001C0 - X"42000010", -- 000001C4 - X"40026000", -- 000001C8 - X"03E00008", -- 000001CC - X"00000000", -- 000001D0 - X"40846000", -- 000001D4 - X"03E00008", -- 000001D8 - X"00000000", -- 000001DC - X"40026800", -- 000001E0 - X"03E00008", -- 000001E4 - X"00000000", -- 000001E8 - X"40846800", -- 000001EC - X"03E00008", -- 000001F0 - X"00000000", -- 000001F4 - X"40027800", -- 000001F8 - X"03E00008", -- 000001FC - X"00000000", -- 00000200 - X"3C02A001", -- 00000204 - X"34430004", -- 00000208 - X"8C620000", -- 0000020C - X"00000000", -- 00000210 - X"30420010", -- 00000214 - X"1040FFFC", -- 00000218 - X"3C02A001", -- 0000021C - X"8C420000", -- 00000220 - X"00000000", -- 00000224 - X"00021600", -- 00000228 - X"03E00008", -- 0000022C - X"00021603", -- 00000230 - X"00042600", -- 00000234 - X"3C02A001", -- 00000238 - X"00042603", -- 0000023C - X"34430004", -- 00000240 - X"8C620000", -- 00000244 - X"00000000", -- 00000248 - X"30420002", -- 0000024C - X"1440FFFC", -- 00000250 - X"3C02A001", -- 00000254 - X"AC440000", -- 00000258 - X"03E00008", -- 0000025C - X"00000000", -- 00000260 - X"00042600", -- 00000264 - X"00042603", -- 00000268 - X"2402000A", -- 0000026C - X"1482000A", -- 00000270 - X"3C02A001", -- 00000274 - X"34430004", -- 00000278 - X"8C620000", -- 0000027C - X"00000000", -- 00000280 - X"30420002", -- 00000284 - X"1440FFFC", -- 00000288 - X"3C02A001", -- 0000028C - X"2403000D", -- 00000290 - X"AC430000", -- 00000294 - X"3C02A001", -- 00000298 - X"34430004", -- 0000029C - X"8C620000", -- 000002A0 - X"00000000", -- 000002A4 - X"30420002", -- 000002A8 - X"1440FFFC", -- 000002AC - X"3C02A001", -- 000002B0 - X"AC440000", -- 000002B4 - X"03E00008", -- 000002B8 - X"00000000", -- 000002BC - X"3C02A001", -- 000002C0 - X"34470004", -- 000002C4 - X"00802821", -- 000002C8 - X"2409000A", -- 000002CC - X"3C06A001", -- 000002D0 - X"0BF000C6", -- 000002D4 - X"2408000D", -- 000002D8 - X"14690007", -- 000002DC - X"00000000", -- 000002E0 - X"8CE20000", -- 000002E4 - X"00000000", -- 000002E8 - X"30420002", -- 000002EC - X"1440FFFC", -- 000002F0 - X"00000000", -- 000002F4 - X"ACC80000", -- 000002F8 - X"8CE20000", -- 000002FC - X"00000000", -- 00000300 - X"30420002", -- 00000304 - X"1440FFFC", -- 00000308 - X"00000000", -- 0000030C - X"ACC30000", -- 00000310 - X"24A50001", -- 00000314 - X"80A30000", -- 00000318 - X"00000000", -- 0000031C - X"1460FFEE", -- 00000320 - X"00A41023", -- 00000324 - X"03E00008", -- 00000328 - X"00000000", -- 0000032C - X"00042600", -- 00000330 - X"3C02A001", -- 00000334 - X"00042603", -- 00000338 - X"344A0004", -- 0000033C - X"00003821", -- 00000340 - X"3C09A001", -- 00000344 - X"24080002", -- 00000348 - X"308200FF", -- 0000034C - X"00022902", -- 00000350 - X"00041100", -- 00000354 - X"00022600", -- 00000358 - X"2CA3000A", -- 0000035C - X"00042603", -- 00000360 - X"14600002", -- 00000364 - X"24A60030", -- 00000368 - X"24A60037", -- 0000036C - X"8D420000", -- 00000370 - X"00000000", -- 00000374 - X"30420002", -- 00000378 - X"1440FFFC", -- 0000037C - X"00061600", -- 00000380 - X"00021603", -- 00000384 - X"24E70001", -- 00000388 - X"AD220000", -- 0000038C - X"14E8FFEF", -- 00000390 - X"308200FF", -- 00000394 - X"03E00008", -- 00000398 - X"00000000", -- 0000039C - X"27BDFFE0", -- 000003A0 - X"AFB20018", -- 000003A4 - X"AFB10014", -- 000003A8 - X"AFB00010", -- 000003AC - X"AFBF001C", -- 000003B0 - X"00808821", -- 000003B4 - X"00008021", -- 000003B8 - X"24120004", -- 000003BC - X"00112603", -- 000003C0 - X"0FF000CC", -- 000003C4 - X"26100001", -- 000003C8 - X"1612FFFC", -- 000003CC - X"00118A00", -- 000003D0 - X"8FBF001C", -- 000003D4 - X"8FB20018", -- 000003D8 - X"8FB10014", -- 000003DC - X"8FB00010", -- 000003E0 - X"03E00008", -- 000003E4 - X"27BD0020", -- 000003E8 - X"27BDFFC8", -- 000003EC - X"AFB60028", -- 000003F0 - X"AFBF0034", -- 000003F4 - X"AFBE0030", -- 000003F8 - X"AFB7002C", -- 000003FC - X"AFB50024", -- 00000400 - X"AFB40020", -- 00000404 - X"AFB3001C", -- 00000408 - X"AFB20018", -- 0000040C - X"AFB10014", -- 00000410 - X"AFB00010", -- 00000414 - X"00801021", -- 00000418 - X"10A00002", -- 0000041C - X"00C0B021", -- 00000420 - X"00002021", -- 00000424 - X"00409821", -- 00000428 - X"3C02A001", -- 0000042C - X"00E09021", -- 00000430 - X"0080A821", -- 00000434 - X"345E0004", -- 00000438 - X"00E0A021", -- 0000043C - X"3C17A001", -- 00000440 - X"0FF000E8", -- 00000444 - X"02A02021", -- 00000448 - X"3C04BFC0", -- 0000044C - X"0FF000B0", -- 00000450 - X"24841674", -- 00000454 - X"02608821", -- 00000458 - X"0BF00128", -- 0000045C - X"00008021", -- 00000460 - X"12400009", -- 00000464 - X"00000000", -- 00000468 - X"82240000", -- 0000046C - X"0FF000CC", -- 00000470 - X"2652FFFF", -- 00000474 - X"3C04BFC0", -- 00000478 - X"0FF000B0", -- 0000047C - X"2484174C", -- 00000480 - X"0BF00128", -- 00000484 - X"26310001", -- 00000488 - X"3C04BFC0", -- 0000048C - X"0FF000B0", -- 00000490 - X"24841678", -- 00000494 - X"0BF0012C", -- 00000498 - X"3C04BFC0", -- 0000049C - X"0216102A", -- 000004A0 - X"1440FFEF", -- 000004A4 - X"26100001", -- 000004A8 - X"3C04BFC0", -- 000004AC - X"0FF000B0", -- 000004B0 - X"24841678", -- 000004B4 - X"02602821", -- 000004B8 - X"0BF00155", -- 000004BC - X"00002021", -- 000004C0 - X"1280001E", -- 000004C4 - X"00000000", -- 000004C8 - X"90A30000", -- 000004CC - X"00000000", -- 000004D0 - X"2462FFE0", -- 000004D4 - X"304200FF", -- 000004D8 - X"2C420060", -- 000004DC - X"14400003", -- 000004E0 - X"00031E00", -- 000004E4 - X"2403002E", -- 000004E8 - X"00031E00", -- 000004EC - X"00031E03", -- 000004F0 - X"2402000A", -- 000004F4 - X"14620007", -- 000004F8 - X"00000000", -- 000004FC - X"8FC20000", -- 00000500 - X"00000000", -- 00000504 - X"30420002", -- 00000508 - X"1440FFFC", -- 0000050C - X"2402000D", -- 00000510 - X"AEE20000", -- 00000514 - X"8FC20000", -- 00000518 - X"00000000", -- 0000051C - X"30420002", -- 00000520 - X"1440FFFC", -- 00000524 - X"00000000", -- 00000528 - X"AEE30000", -- 0000052C - X"2694FFFF", -- 00000530 - X"24840001", -- 00000534 - X"0BF00155", -- 00000538 - X"24A50001", -- 0000053C - X"3C04BFC0", -- 00000540 - X"0FF000B0", -- 00000544 - X"2484174C", -- 00000548 - X"0BF00159", -- 0000054C - X"3C04BFC0", -- 00000550 - X"0096102A", -- 00000554 - X"1440FFDA", -- 00000558 - X"00000000", -- 0000055C - X"3C04BFC0", -- 00000560 - X"0FF000B0", -- 00000564 - X"248416A0", -- 00000568 - X"02B6A821", -- 0000056C - X"1640FFB4", -- 00000570 - X"02769821", -- 00000574 - X"8FBF0034", -- 00000578 - X"8FBE0030", -- 0000057C - X"8FB7002C", -- 00000580 - X"8FB60028", -- 00000584 - X"8FB50024", -- 00000588 - X"8FB40020", -- 0000058C - X"8FB3001C", -- 00000590 - X"8FB20018", -- 00000594 - X"8FB10014", -- 00000598 - X"8FB00010", -- 0000059C - X"03E00008", -- 000005A0 - X"27BD0038", -- 000005A4 - X"00C03821", -- 000005A8 - X"00A03021", -- 000005AC - X"0BF000FB", -- 000005B0 - X"24050001", -- 000005B4 - X"8C840000", -- 000005B8 - X"3C020070", -- 000005BC - X"34420070", -- 000005C0 - X"3C0300FF", -- 000005C4 - X"AC820000", -- 000005C8 - X"346300FF", -- 000005CC - X"8C820000", -- 000005D0 - X"AC830000", -- 000005D4 - X"03E00008", -- 000005D8 - X"00000000", -- 000005DC - X"27BDFFF8", -- 000005E0 - X"AC850000", -- 000005E4 - X"24820008", -- 000005E8 - X"0BF0017F", -- 000005EC - X"24830020", -- 000005F0 - X"A0400000", -- 000005F4 - X"24420001", -- 000005F8 - X"1443FFFD", -- 000005FC - X"00000000", -- 00000600 - X"24020001", -- 00000604 - X"AC820004", -- 00000608 - X"03E00008", -- 0000060C - X"27BD0008", -- 00000610 - X"8C870000", -- 00000614 - X"3C020098", -- 00000618 - X"34420098", -- 0000061C - X"ACE20000", -- 00000620 - X"3C0200FF", -- 00000624 - X"344200FF", -- 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00001814 - X"00000000", -- 00001818 - X"00000000", -- 0000181C - X"00000000", -- 00001820 - X"00000000", -- 00001824 - X"00000000", -- 00001828 - X"00000000", -- 0000182C - X"00000000", -- 00001830 - X"00000000", -- 00001834 - X"00000000", -- 00001838 - X"00000000", -- 0000183C - X"00000000", -- 00001840 - X"00000000", -- 00001844 - X"00000000", -- 00001848 - X"00000000", -- 0000184C - X"00000000", -- 00001850 - X"00000000", -- 00001854 - X"00000000", -- 00001858 - X"00000000", -- 0000185C - X"00000000", -- 00001860 - X"00000000", -- 00001864 - X"00000000", -- 00001868 - X"00000000", -- 0000186C - X"00000000", -- 00001870 - X"00000000", -- 00001874 - X"00000000", -- 00001878 - X"00000000", -- 0000187C - X"00000000", -- 00001880 - X"00000000", -- 00001884 - X"00000000", -- 00001888 - X"00000000", -- 0000188C - X"00000000", -- 00001890 - X"00000000", -- 00001894 - X"00000000", -- 00001898 - X"00000000", -- 0000189C - X"00000000", -- 000018A0 - X"00000000", -- 000018A4 - X"00000000", -- 000018A8 - X"00000000", -- 000018AC - X"00000000", -- 000018B0 - X"00000000", -- 000018B4 - X"00000000", -- 000018B8 - X"00000000", -- 000018BC - X"00000000", -- 000018C0 - X"00000000", -- 000018C4 - X"00000000", -- 000018C8 - X"00000000", -- 000018CC - X"00000000", -- 000018D0 - X"00000000", -- 000018D4 - X"00000000", -- 000018D8 - X"00000000", -- 000018DC - X"00000000", -- 000018E0 - X"00000000", -- 000018E4 - X"00000000", -- 000018E8 - X"00000000", -- 000018EC - X"00000000", -- 000018F0 - X"00000000", -- 000018F4 - X"00000000", -- 000018F8 - X"00000000", -- 000018FC - X"00000000", -- 00001900 - X"00000000", -- 00001904 - X"00000000", -- 00001908 - X"00000000", -- 0000190C - X"00000000", -- 00001910 - X"00000000", -- 00001914 - X"00000000", -- 00001918 - X"00000000", -- 0000191C - X"00000000", -- 00001920 - X"00000000", -- 00001924 - X"00000000", -- 00001928 - X"00000000", -- 0000192C - X"00000000", -- 00001930 - X"00000000", -- 00001934 - X"00000000", -- 00001938 - X"00000000", -- 0000193C - X"00000000", -- 00001940 - X"00000000", -- 00001944 - X"00000000", -- 00001948 - X"00000000", -- 0000194C - X"00000000", -- 00001950 - X"00000000", -- 00001954 - X"00000000", -- 00001958 - X"00000000", -- 0000195C - X"00000000", -- 00001960 - X"00000000", -- 00001964 - X"00000000", -- 00001968 - X"00000000", -- 0000196C - X"00000000", -- 00001970 - X"00000000", -- 00001974 - X"00000000", -- 00001978 - X"00000000", -- 0000197C - X"00000000", -- 00001980 - X"00000000", -- 00001984 - X"00000000", -- 00001988 - X"00000000", -- 0000198C - X"00000000", -- 00001990 - X"00000000", -- 00001994 - X"00000000", -- 00001998 - X"00000000", -- 0000199C - X"00000000", -- 000019A0 - X"00000000", -- 000019A4 - X"00000000", -- 000019A8 - X"00000000", -- 000019AC - X"00000000", -- 000019B0 - X"00000000", -- 000019B4 - X"00000000", -- 000019B8 - X"00000000", -- 000019BC - X"00000000", -- 000019C0 - X"00000000", -- 000019C4 - X"00000000", -- 000019C8 - X"00000000", -- 000019CC - X"00000000", -- 000019D0 - X"00000000", -- 000019D4 - X"00000000", -- 000019D8 - X"00000000", -- 000019DC - X"00000000", -- 000019E0 - X"00000000", -- 000019E4 - X"00000000", -- 000019E8 - X"00000000", -- 000019EC - X"00000000", -- 000019F0 - X"00000000", -- 000019F4 - X"00000000", -- 000019F8 - X"00000000", -- 000019FC - X"00000000", -- 00001A00 - X"00000000", -- 00001A04 - X"00000000", -- 00001A08 - X"00000000", -- 00001A0C - X"00000000", -- 00001A10 - X"00000000", -- 00001A14 - X"00000000", -- 00001A18 - X"00000000", -- 00001A1C - X"00000000", -- 00001A20 - X"00000000", -- 00001A24 - X"00000000", -- 00001A28 - X"00000000", -- 00001A2C - X"00000000", -- 00001A30 - X"00000000", -- 00001A34 - X"00000000", -- 00001A38 - X"00000000", -- 00001A3C - X"00000000", -- 00001A40 - X"00000000", -- 00001A44 - X"00000000", -- 00001A48 - X"00000000", -- 00001A4C - X"00000000", -- 00001A50 - X"00000000", -- 00001A54 - X"00000000", -- 00001A58 - X"00000000", -- 00001A5C - X"00000000", -- 00001A60 - X"00000000", -- 00001A64 - X"00000000", -- 00001A68 - X"00000000", -- 00001A6C - X"00000000", -- 00001A70 - X"00000000", -- 00001A74 - X"00000000", -- 00001A78 - X"00000000", -- 00001A7C - X"00000000", -- 00001A80 - X"00000000", -- 00001A84 - X"00000000", -- 00001A88 - X"00000000", -- 00001A8C - X"00000000", -- 00001A90 - X"00000000", -- 00001A94 - X"00000000", -- 00001A98 - X"00000000", -- 00001A9C - X"00000000", -- 00001AA0 - X"00000000", -- 00001AA4 - X"00000000", -- 00001AA8 - X"00000000", -- 00001AAC - X"00000000", -- 00001AB0 - X"00000000", -- 00001AB4 - X"00000000", -- 00001AB8 - X"00000000", -- 00001ABC - X"00000000", -- 00001AC0 - X"00000000", -- 00001AC4 - X"00000000", -- 00001AC8 - X"00000000", -- 00001ACC - X"00000000", -- 00001AD0 - X"00000000", -- 00001AD4 - X"00000000", -- 00001AD8 - X"00000000", -- 00001ADC - X"00000000", -- 00001AE0 - X"00000000", -- 00001AE4 - X"00000000", -- 00001AE8 - X"00000000", -- 00001AEC - X"00000000", -- 00001AF0 - X"00000000", -- 00001AF4 - X"00000000", -- 00001AF8 - X"00000000", -- 00001AFC - X"00000000", -- 00001B00 - X"00000000", -- 00001B04 - X"00000000", -- 00001B08 - X"00000000", -- 00001B0C - X"00000000", -- 00001B10 - X"00000000", -- 00001B14 - X"00000000", -- 00001B18 - X"00000000", -- 00001B1C - X"00000000", -- 00001B20 - X"00000000", -- 00001B24 - X"00000000", -- 00001B28 - X"00000000", -- 00001B2C - X"00000000", -- 00001B30 - X"00000000", -- 00001B34 - X"00000000", -- 00001B38 - X"00000000", -- 00001B3C - X"00000000", -- 00001B40 - X"00000000", -- 00001B44 - X"00000000", -- 00001B48 - X"00000000", -- 00001B4C - X"00000000", -- 00001B50 - X"00000000", -- 00001B54 - X"00000000", -- 00001B58 - X"00000000", -- 00001B5C - X"00000000", -- 00001B60 - X"00000000", -- 00001B64 - X"00000000", -- 00001B68 - X"00000000", -- 00001B6C - X"00000000", -- 00001B70 - X"00000000", -- 00001B74 - X"00000000", -- 00001B78 - X"00000000", -- 00001B7C - X"00000000", -- 00001B80 - X"00000000", -- 00001B84 - X"00000000", -- 00001B88 - X"00000000", -- 00001B8C - X"00000000", -- 00001B90 - X"00000000", -- 00001B94 - X"00000000", -- 00001B98 - X"00000000", -- 00001B9C - X"00000000", -- 00001BA0 - X"00000000", -- 00001BA4 - X"00000000", -- 00001BA8 - X"00000000", -- 00001BAC - X"00000000", -- 00001BB0 - X"00000000", -- 00001BB4 - X"00000000", -- 00001BB8 - X"00000000", -- 00001BBC - X"00000000", -- 00001BC0 - X"00000000", -- 00001BC4 - X"00000000", -- 00001BC8 - X"00000000", -- 00001BCC - X"00000000", -- 00001BD0 - X"00000000", -- 00001BD4 - X"00000000", -- 00001BD8 - X"00000000", -- 00001BDC - X"00000000", -- 00001BE0 - X"00000000", -- 00001BE4 - X"00000000", -- 00001BE8 - X"00000000", -- 00001BEC - X"00000000", -- 00001BF0 - X"00000000", -- 00001BF4 - X"00000000", -- 00001BF8 - X"00000000", -- 00001BFC - X"00000000", -- 00001C00 - X"00000000", -- 00001C04 - X"00000000", -- 00001C08 - X"00000000", -- 00001C0C - X"00000000", -- 00001C10 - X"00000000", -- 00001C14 - X"00000000", -- 00001C18 - X"00000000", -- 00001C1C - X"00000000", -- 00001C20 - X"00000000", -- 00001C24 - X"00000000", -- 00001C28 - X"00000000", -- 00001C2C - X"00000000", -- 00001C30 - X"00000000", -- 00001C34 - X"00000000", -- 00001C38 - X"00000000", -- 00001C3C - X"00000000", -- 00001C40 - X"00000000", -- 00001C44 - X"00000000", -- 00001C48 - X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd deleted file mode 100644 index 6f2be44..0000000 --- a/projects/mips_sys/src/mips_sys.vhd +++ /dev/null @@ -1,939 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -Library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.mips_types.all; -use work.sdram_config.all; -use work.sdram_types.all; -use work.vga_types.all; -use work.async_types.all; -use work.async_defs.all; - - -ENTITY mips_sys IS -GENERIC -( - sys_freq : integer := 100E6; - ddr_phaseshift : integer := 0; - ddr_frequency_hz : integer := 100E6 -); -PORT -( - sys_rst_n_in : in std_logic; - sys_clk_in : in std_logic; - - -- Buttons and LEDs - sys_btn : in unsigned(4 downto 0); - sys_dip : in unsigned(7 downto 0); - sys_led : out unsigned(8 downto 0); - - -- UART - sys_uart0_rx : in std_logic; - sys_uart0_tx : out std_logic; - sys_uart1_rx : in std_logic; - sys_uart1_tx : out std_logic; - sys_uart2_rx : in std_logic; - sys_uart2_tx : out std_logic; - sys_uart3_rx : in std_logic; - sys_uart3_tx : out std_logic; - - -- LCD - sys_lcd_d : inout unsigned(3 downto 0); - sys_lcd_e : out std_logic; - sys_lcd_rs : out std_logic; - sys_lcd_rw : out std_logic; - - -- DDR SDRAM - sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock - sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock - sys_sdr_cke_q : out std_logic; -- clock enable - sys_sdr_cs_qn : out std_logic; -- /chip select - sys_sdr_ras_qn : out std_logic; -- /ras - sys_sdr_cas_qn : out std_logic; -- /cas - sys_sdr_we_qn : out std_logic; -- /write enable - sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - sys_sdr_clk_fb : in std_logic; - - -- VGA - sys_vga_clk : out std_logic; - sys_vga_red : out unsigned(7 downto 0); - sys_vga_green : out unsigned(7 downto 0); - sys_vga_blue : out unsigned(7 downto 0); - sys_vga_blank_n : out std_logic; - sys_vga_sync_n : out std_logic; - sys_vga_hsync : out std_logic; - sys_vga_vsync : out std_logic; - - sys_usb_d : inout unsigned(15 downto 0); - sys_usb_a : out unsigned(1 downto 0); - sys_usb_csn : out std_logic; - sys_usb_wrn : out std_logic; - sys_usb_rdn : out std_logic; - sys_usb_rstn : out std_logic; - sys_usb_int : in std_logic; - - sys_flash_d : inout unsigned(31 downto 0); - sys_flash_a : out unsigned(24 downto 0); - sys_flash_ce : out std_logic; - sys_flash_wrn : out std_logic; - sys_flash_rdn : out std_logic; - sys_flash_ac97_rstn : out std_logic; - sys_flash_byten : out std_logic; - - sys_ac97_sdata_in : in std_logic; - sys_ac97_bit_clk : in std_logic; - sys_ac97_sdata_out : out std_logic; - sys_ac97_ssync : out std_logic; - - sys_error : out unsigned(1 downto 0) -- indicates Errors - -); --- attribute BUFFER_TYPE : string; --- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; --- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; - -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - COMPONENT mips_top - Port - ( - debug : out unsigned(1 downto 0); - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - DAT_O : out word_t; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - - ); - END COMPONENT; - - COMPONENT rom_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT lcd_port - PORT - ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - END COMPONENT; - - COMPONENT async_port_wb - GENERIC - ( - addr_width : natural := 32; - data_width : natural := 32; - byte_sel_width : natural := 4; - async_timespec : async_timespec_t - ); - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - page_mode_en : in STD_LOGIC; - async_a : out unsigned(addr_width-1 downto 0); - async_d : inout unsigned(data_width-1 downto 0); - async_cs : out std_logic; - async_wr : out std_logic; - async_rd : out std_logic; - async_be : out unsigned(byte_sel_width-1 downto 0); - async_rst : out std_logic - ); - END COMPONENT; - - COMPONENT uart_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - ser_rx : in std_logic; - ser_tx : out std_logic - ); - END COMPONENT; - - COMPONENT gpio_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_TIM_O : out STD_LOGIC; - - sys_gpo0 : out unsigned(31 downto 0); - sys_gpo1 : out unsigned(31 downto 0); - sys_gpi0 : in unsigned(31 downto 0); - sys_gpi1 : in unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT vga_frontend64 - GENERIC - ( - sys_freq : integer; - fifo_depth : integer; - fifo_almost_full_thresh : natural; - fifo_almost_empty_thresh : natural; - tsvga : vga_timespec_t - ); - PORT - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(7 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(63 downto 0); - MDAT_O : out unsigned(63 downto 0); - - -- JBUS Slave signals - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_out : out std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); - END COMPONENT; - - signal nmi : std_logic; - signal rst : std_logic; - signal clk : std_logic; - signal eb : std_logic; - signal clk270 : std_logic; - signal clk270var : std_logic; - signal rst_in : std_logic; - signal int_timer : std_logic; - signal int_uart0 : std_logic; - signal int_uart1 : std_logic; - signal uart1_tx : std_logic; - signal uart1_rx : std_logic; - signal locked : std_logic; - signal usb_addr : unsigned(31 downto 0); - signal flash_addr : unsigned(31 downto 0); - signal ac97_rstn : std_logic; - signal mem_mapped_io : std_logic; - signal flash_rstn : std_logic; - signal flash_page_mode_en : std_logic; - - -- Arbiter - constant ARB_MAX_MASTER : natural := 2; - signal arb_idx : natural range 0 to ARB_MAX_MASTER-1; - signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0); - signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); - - -- J-Bus signals - signal INT : unsigned(5 downto 0); - signal MDAT_I : word_t; - signal MDAT_O : word_t; - signal ADDR_O : word_t; - signal SEL_O : unsigned(3 downto 0); - signal WE_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal ACK_I : std_logic; - signal SRDY_I : std_logic; - signal MRDY_O : std_logic; - - -- CPU Master - signal MRDY_O_cpu : std_logic; - signal MDAT_O_cpu : word_t; - signal ADDR_O_cpu : word_t; - signal SEL_O_cpu : unsigned(3 downto 0); - signal WE_O_cpu : std_logic; - signal CYC_O_cpu : std_logic; - signal STB_O_cpu : std_logic; - signal SRDY_I_cpu : std_logic; - signal ACK_I_cpu : std_logic; - - -- VGA Master - signal MRDY_O_vga : std_logic; - signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(7 downto 0); - signal WE_O_vga : std_logic; - signal CYC_O_vga : std_logic; - signal STB_O_vga : std_logic; - signal SRDY_I_vga : std_logic; - signal ACK_I_vga : std_logic; - signal MDAT_I_vga : unsigned(63 downto 0); - signal MDAT_O_vga : unsigned(63 downto 0); - - -- Slaves - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal SDAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_usb : std_logic; - signal ACK_O_usb : std_logic; - signal SRDY_O_usb : std_logic; - signal SDAT_O_usb : unsigned(31 downto 0); - - signal CYC_I_sdram : std_logic; - signal ACK_O_sdram : std_logic; - signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(63 downto 0); - signal SDAT_I_sdram : unsigned(63 downto 0); - signal SEL_I_sdram : unsigned(7 downto 0); - - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal SDAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal SDAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart0 : std_logic; - signal ACK_O_uart0 : std_logic; - signal SRDY_O_uart0 : std_logic; - signal SDAT_O_uart0 : unsigned(31 downto 0); - signal CYC_I_uart1 : std_logic; - signal ACK_O_uart1 : std_logic; - signal SRDY_O_uart1 : std_logic; - signal SDAT_O_uart1 : unsigned(31 downto 0); - - signal CYC_I_vga : std_logic; - signal ACK_O_vga : std_logic; - signal SRDY_O_vga : std_logic; - signal SDAT_O_vga : unsigned(31 downto 0); - - signal INT_O_ac97 : std_logic; - signal CYC_I_ac97 : std_logic; - signal ACK_O_ac97 : std_logic; - signal SRDY_O_ac97 : std_logic; - signal SDAT_O_ac97 : unsigned(31 downto 0); - - signal gpo0 : unsigned(31 downto 0); - signal gpo1 : unsigned(31 downto 0); - signal gpi0 : unsigned(31 downto 0); - signal gpi1 : unsigned(31 downto 0); - - signal debug : unsigned(1 downto 0); - - -- DDR SDRAM - constant BURST_LEN : natural := 2; - - --- attribute rom_style: string; --- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - - type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_sdram, mem_vga, mem_ac97); - signal mem_area : mem_area_t; - -BEGIN - - ------------------------------------ - -- GPO1 bits used for - -- 0 : USB reset - -- 1 : USB interrupt enable - -- 2 : AC97 interrupt enable - -- others : reserved - ------------------------------------ - eb <= sys_dip(7); - gpi0(4 downto 0) <= sys_btn; - gpi1(7 downto 0) <= sys_dip; - sys_led <= gpo0(8 downto 0); - sys_error <= debug; - nmi <= not sys_rst_n_in; - rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); - rst <= not locked; - sys_usb_rstn <= not gpo1(0); - sys_flash_byten <= '1'; - usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2); - flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0'; - flash_page_mode_en <= not mem_mapped_io; - - SDAT_I_sdram <= MDAT_O & MDAT_O; - SEL_I_sdram <= "0000" & SEL_O; - - sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; - sys_uart1_tx <= uart1_tx; - sys_uart2_tx <= uart1_tx; - uart1_rx <= sys_uart1_rx and sys_uart2_rx; - sys_uart3_tx <= sys_uart3_rx; - - --------------------------------------------------------------- - -- Arbiter - MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); - ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); - WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; - CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; - STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; - SRDY_I_cpu <= SRDY_I and arb_gnt(0); - SRDY_I_vga <= SRDY_I and arb_gnt(1); - ACK_I_cpu <= ACK_I and arb_gnt(0); - ACK_I_vga <= ACK_I and arb_gnt(1); - - arb_req(0) <= CYC_O_cpu; - arb_req(1) <= CYC_O_vga; - - MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; - -arbiter_proc: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - arb_gnt <= (others => '0'); - arb_idx <= 0; - elsif arb_req(arb_idx) = '0' then - if arb_idx /= ARB_MAX_MASTER-1 then - arb_idx <= arb_idx + 1; - else - arb_idx <= 0; - end if; - else - arb_gnt <= (others => '0'); - arb_gnt(arb_idx) <= '1'; - end if; - end if; - end process; - -int_sample: - process(clk) - begin - if rising_edge(clk) then - INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4); - end if; - end process; - -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - mem_mapped_io <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - elsif ADDR_O(31 downto 28) = X"A" then - mem_mapped_io <= '1'; - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - if ADDR_O(9 downto 8) = "00" then - mem_area <= mem_uart0; - elsif ADDR_O(9 downto 8) = "01" then - mem_area <= mem_uart1; - end if; - elsif ADDR_O(18 downto 16) = "010" then - mem_area <= mem_usb; - elsif ADDR_O(18 downto 16) = "011" then - mem_area <= mem_vga; - elsif ADDR_O(18 downto 16) = "100" then - mem_area <= mem_ac97; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sdram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart0 <= '0'; - CYC_I_uart1 <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_usb <= '0'; - CYC_I_rom <= '0'; - CYC_I_sdram <= '0'; - CYC_I_vga <= '0'; - CYC_I_ac97 <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart0 => - CYC_I_uart0 <= CYC_O; - - when mem_uart1 => - CYC_I_uart1 <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_usb => - CYC_I_usb <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sdram => - CYC_I_sdram <= CYC_O; - - when mem_vga => - CYC_I_vga <= CYC_O; - - when mem_ac97 => - CYC_I_ac97 <= CYC_O; - - when others => null; - - end case; - - end process; - ------------------------------------------------------------------- - SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; - MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else - SDAT_O_rom when CYC_I_rom = '1' else - SDAT_O_flash when CYC_I_flash = '1' else - SDAT_O_usb when CYC_I_usb = '1' else - SDAT_O_uart0 when CYC_I_uart0 = '1' else - SDAT_O_uart1 when CYC_I_uart1 = '1' else - SDAT_O_vga when CYC_I_vga = '1' else - SDAT_O_ac97 when CYC_I_ac97 = '1' else - SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - ------------------------------------------------------------------- -inst_mips_top: mips_top - PORT MAP - ( - debug => debug, - eb => eb, - nmi => nmi, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I_cpu, - SRDY_I => SRDY_I_cpu, - MRDY_O => MRDY_O_cpu, - CYC_O => CYC_O_cpu, - STB_O => STB_O_cpu, - WE_O => WE_O_cpu, - SEL_O => SEL_O_cpu, - DAT_I => MDAT_I, - DAT_O => MDAT_O_cpu, - ADDR_O => ADDR_O_cpu, - INT => INT - ); - -inst_rom_wb : rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => SDAT_O_rom - ); - - -inst_lcd_port: lcd_port - PORT MAP - ( - clk => clk, - rst => rst, - we => '0', - din => X"00", - dout => open, - lcd_d => sys_lcd_d, - lcd_e => sys_lcd_e, - lcd_rs => sys_lcd_rs, - lcd_rw => sys_lcd_rw - ); - -inst_gpio_wb : gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpo0 => gpo0, - sys_gpo1 => gpo1, - sys_gpi0 => gpi0, - sys_gpi1 => gpi1 - ); - -inst_flash_port : async_port_wb - GENERIC MAP - ( - addr_width => 25, - data_width => 32, - byte_sel_width => 1, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => flash_addr, - DAT_I => MDAT_O, - DAT_O => SDAT_O_flash, - page_mode_en => flash_page_mode_en, - async_a => sys_flash_a, - async_d => sys_flash_d, - async_cs => sys_flash_ce, - async_wr => sys_flash_wrn, - async_rd => sys_flash_rdn, - async_be => open, - async_rst => flash_rstn - ); - -inst_usb_port : async_port_wb - GENERIC MAP - ( - addr_width => 2, - data_width => 16, - byte_sel_width => 1, - async_timespec => ts_usb - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_usb, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_usb, - SRDY_O => SRDY_O_usb, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => usb_addr, - DAT_I => MDAT_O, - DAT_O => SDAT_O_usb, - page_mode_en => '0', - async_a => sys_usb_a, - async_d => sys_usb_d, - async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, - async_rd => sys_usb_rdn, - async_be => open, - async_rst => open - ); - -inst_uart_wb_0 : uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart0, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart0, - SRDY_O => SRDY_O_uart0, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart0, - INT_O => int_uart0, - ser_rx => sys_uart0_rx, - ser_tx => sys_uart0_tx - ); - -inst_uart_wb_1 : uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart1, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart1, - SRDY_O => SRDY_O_uart1, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart1, - INT_O => int_uart1, - ser_rx => uart1_rx, - ser_tx => uart1_tx - ); - - -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => ddr_frequency_hz, - fifo_depth => 5 - ) - PORT MAP - ( - RST_I => rst, - CLK_I => clk, - CLK270_I => clk270, - CLK270VAR_I => clk270var, - - CYC_I => CYC_I_sdram, - STB_I => STB_O, - SEL_I => SEL_I_sdram, - WE_I => WE_O, - ACK_O => ACK_O_sdram, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_sdram, - ADDR_I => ADDR_O, - DAT_I => SDAT_I_sdram, - DAT_O => SDAT_O_sdram, - - -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data - - ); - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - sys1_phaseshift => 0, - frequency_hz => 100E6 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst_in, -- external async reset, low active - clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board - clk_fb_in => sys_sdr_clk_fb, -- feedback clock - sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° - sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° - locked_out => locked, -- DCM locked status - error_out => open - ); - -inst_vga_frontend : vga_frontend64 - GENERIC MAP - ( - sys_freq => 100E6, - fifo_depth => 2048, - fifo_almost_full_thresh => 1860, - fifo_almost_empty_thresh => 256, - tsvga => ts_vga_800_600_72 - ) - PORT MAP - ( - -- System signals - RST_I => rst, - CLK_I => clk, - - -- JBUS Master signals - CYC_O => CYC_O_vga, - STB_O => STB_O_vga, - WE_O => WE_O_vga, - SEL_O => SEL_O_vga, - ACK_I => ACK_I_vga, - SRDY_I => SRDY_I_vga, - MRDY_O => MRDY_O_vga, - ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I_vga, - MDAT_O => MDAT_O_vga, - - -- JBUS Slave signals - CYC_I => CYC_I_vga, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_O_vga, - SRDY_O => SRDY_O_vga, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => MDAT_O, - SDAT_O => SDAT_O_vga, - - -- VGA signals - vga_clk_out => sys_vga_clk, - vga_red => sys_vga_red, - vga_green => sys_vga_green, - vga_blue => sys_vga_blue, - vga_blank_n => sys_vga_blank_n, - vga_sync_n => sys_vga_sync_n, - vga_hsync => sys_vga_hsync, - vga_vsync => sys_vga_vsync - ); - -inst_ac97_wb : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 8 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_ac97, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_ac97, - SRDY_O => SRDY_O_ac97, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ac97, - INT_O => INT_O_ac97, - - -- AC97 domain - ac97_sdata_in => sys_ac97_sdata_in, - ac97_bit_clk => sys_ac97_bit_clk, - ac97_reset_n => ac97_rstn, - ac97_sdata_out => sys_ac97_sdata_out, - ac97_ssync => sys_ac97_ssync - ); - - ------------------------------------------------------------------ -END; diff --git a/projects/mips_sys/src/mips_sys_sim.vhd b/projects/mips_sys/src/mips_sys_sim.vhd deleted file mode 100644 index 3ea58bc..0000000 --- a/projects/mips_sys/src/mips_sys_sim.vhd +++ /dev/null @@ -1,1094 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -Library UNISIM; -use UNISIM.vcomponents.all; - -library work; -use work.mips_types.all; ---use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; -use work.vga_types.all; -use work.async_types.all; -use work.async_defs.all; - - -ENTITY mips_sys IS -GENERIC -( - sys_freq : integer := 100E6; - ddr_phaseshift : integer := 0; - ddr_frequency_hz : integer := 100E6 -); -PORT -( - sys_rst_n_in : in std_logic; - sys_clk_in : in std_logic; - - -- Buttons and LEDs - sys_btn : in unsigned(4 downto 0); - sys_dip : in unsigned(7 downto 0); - sys_led : out unsigned(8 downto 0); - - -- UART - sys_uart0_rx : in std_logic; - sys_uart0_tx : out std_logic; - sys_uart1_rx : in std_logic; - sys_uart1_tx : out std_logic; - sys_uart2_rx : in std_logic; - sys_uart2_tx : out std_logic; - - -- LCD - sys_lcd_d : inout unsigned(3 downto 0); - sys_lcd_e : out std_logic; - sys_lcd_rs : out std_logic; - sys_lcd_rw : out std_logic; - - -- DDR SDRAM - sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock - sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock - sys_sdr_cke_q : out std_logic; -- clock enable - sys_sdr_cs_qn : out std_logic; -- /chip select - sys_sdr_ras_qn : out std_logic; -- /ras - sys_sdr_cas_qn : out std_logic; -- /cas - sys_sdr_we_qn : out std_logic; -- /write enable - sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - sys_sdr_clk_fb : in std_logic; - - -- VGA - sys_vga_clk : out std_logic; - sys_vga_red : out unsigned(7 downto 0); - sys_vga_green : out unsigned(7 downto 0); - sys_vga_blue : out unsigned(7 downto 0); - sys_vga_blank_n : out std_logic; - sys_vga_sync_n : out std_logic; - sys_vga_hsync : out std_logic; - sys_vga_vsync : out std_logic; - - sys_usb_d : inout unsigned(15 downto 0); - sys_usb_a : out unsigned(1 downto 0); - sys_usb_csn : out std_logic; - sys_usb_wrn : out std_logic; - sys_usb_rdn : out std_logic; - sys_usb_rstn : out std_logic; - sys_usb_int : in std_logic; - - sys_flash_ssram_d : inout unsigned(31 downto 0); - sys_flash_ssram_a : out unsigned(24 downto 0); - sys_flash_ce : out std_logic; - sys_flash_ssram_we_n : out std_logic; - sys_flash_ssram_oe_n : out std_logic; - sys_flash_ac97_rstn : out std_logic; - sys_flash_byten : out std_logic; - - sys_ssram_clk : out std_logic; - sys_ssram_clk_fb : in std_logic; - sys_ssram_cke_n : out std_logic; - sys_ssram_ce_n : out std_logic; - sys_ssram_bw_n : out unsigned(3 downto 0); - sys_ssram_dp : inout unsigned(3 downto 0); - sys_ssram_adv : out std_logic; - sys_ssram_mode : out std_logic; - sys_ssram_zz : out std_logic; - - sys_ac97_sdata_in : in std_logic; - sys_ac97_bit_clk : in std_logic; - sys_ac97_sdata_out : out std_logic; - sys_ac97_ssync : out std_logic; - - sys_error : out unsigned(1 downto 0) -- indicates Errors - -); --- attribute BUFFER_TYPE : string; --- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG"; --- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG"; - -END mips_sys; - -ARCHITECTURE behavior OF mips_sys IS - - COMPONENT mips_top - Port - ( - debug : out unsigned(1 downto 0); - eb : in STD_LOGIC; - nmi : in STD_LOGIC; - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - ADDR_O : out word_t; - DAT_I : in word_t; - DAT_O : out word_t; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(3 downto 0); - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - MRDY_O : out STD_LOGIC; - INT : in unsigned (5 downto 0) - - ); - END COMPONENT; - - COMPONENT rom_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SRDY_O : out STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT lcd_port - PORT - ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - END COMPONENT; - - COMPONENT async_port_wb - GENERIC - ( - addr_width : natural := 32; - data_width : natural := 32; - byte_sel_width : natural := 4; - async_timespec : async_timespec_t - ); - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - page_mode_en : in STD_LOGIC; - async_a : out unsigned(addr_width-1 downto 0); - async_d : inout unsigned(data_width-1 downto 0); - async_cs : out std_logic; - async_wr : out std_logic; - async_rd : out std_logic; - async_be : out unsigned(byte_sel_width-1 downto 0); - async_rst : out std_logic - ); - END COMPONENT; - - COMPONENT flash_port_wb - GENERIC - ( - addr_width : natural := 32; - data_width : natural := 32; - async_timespec : async_timespec_t - ); - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - port_bsyo : out std_logic; - port_bsyi : in std_logic; - port_a : out unsigned(addr_width-1 downto 0); - port_di : in unsigned(data_width-1 downto 0); - port_do : out unsigned(data_width-1 downto 0); - port_d_drv : out STD_LOGIC; - port_wr : out STD_LOGIC; - port_rd : out STD_LOGIC; - flash_cs : out std_logic; - flash_rst : out std_logic - ); - END COMPONENT; - - COMPONENT uart_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_O : out STD_LOGIC; - ser_rx : in std_logic; - ser_tx : out std_logic - ); - END COMPONENT; - - COMPONENT gpio_wb - PORT - ( - CLK_I : in STD_LOGIC; - RST_I : in STD_LOGIC; - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - WE_I : in STD_LOGIC; - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - DAT_I : in unsigned(31 downto 0); - DAT_O : out unsigned(31 downto 0); - INT_TIM_O : out STD_LOGIC; - - sys_gpo0 : out unsigned(31 downto 0); - sys_gpo1 : out unsigned(31 downto 0); - sys_gpi0 : in unsigned(31 downto 0); - sys_gpi1 : in unsigned(31 downto 0) - ); - END COMPONENT; - - COMPONENT vga_frontend64 - GENERIC - ( - sys_freq : integer; - fifo_depth : integer; - fifo_almost_full_thresh : natural; - fifo_almost_empty_thresh : natural; - tsvga : vga_timespec_t - ); - PORT - ( - -- System signals - RST_I : in STD_LOGIC; - CLK_I : in STD_LOGIC; - - -- JBUS Master signals - CYC_O : out STD_LOGIC; - STB_O : out STD_LOGIC; - WE_O : out STD_LOGIC; - SEL_O : out unsigned(7 downto 0); - ACK_I : in STD_LOGIC; - SRDY_I : in STD_LOGIC; - MRDY_O : out STD_LOGIC; - ADDR_O : out unsigned(31 downto 0); - MDAT_I : in unsigned(63 downto 0); - MDAT_O : out unsigned(63 downto 0); - - -- JBUS Slave signals - CYC_I : in STD_LOGIC; - STB_I : in STD_LOGIC; - WE_I : in STD_LOGIC; - SEL_I : in unsigned(3 downto 0); - ACK_O : out STD_LOGIC; - SRDY_O : out STD_LOGIC; - MRDY_I : in STD_LOGIC; - ADDR_I : in unsigned(31 downto 0); - SDAT_I : in unsigned(31 downto 0); - SDAT_O : out unsigned(31 downto 0); - - -- VGA signals - vga_clk_out : out std_logic; - vga_red : out unsigned(7 downto 0); - vga_green : out unsigned(7 downto 0); - vga_blue : out unsigned(7 downto 0); - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); - END COMPONENT; - - signal nmi : std_logic; - signal rst : std_logic; - signal clk : std_logic; - signal eb : std_logic; - signal clk270 : std_logic; - signal clk270var : std_logic; - signal rst_in : std_logic; - signal int_timer : std_logic; - signal int_uart0 : std_logic; - signal int_uart1 : std_logic; - signal int_uart2 : std_logic; - signal locked : std_logic; - signal ac97_rstn : std_logic; - signal flash_rstn : std_logic; - signal ADDR_I_usb : unsigned(31 downto 0); - signal ADDR_I_flash : unsigned(31 downto 0); - signal ADDR_I_ssram : unsigned(31 downto 0); - signal ssram_clk : std_logic; - signal ssram_a : unsigned(24 downto 0); - signal ssram_do : unsigned(31 downto 0); - signal ssram_oe_n : std_logic; - signal ssram_we_n : std_logic; - signal ssram_d_drv : std_logic; - signal ssram_bsy : std_logic; - signal flash_a : unsigned(24 downto 0); - signal flash_do : unsigned(31 downto 0); - signal flash_oe_n : std_logic; - signal flash_we_n : std_logic; - signal flash_d_drv : std_logic; - signal flash_bsy : std_logic; - signal flash_page_mode_en : std_logic; - - -- Arbiter - constant ARB_MAX_MASTER : natural := 2; - signal arb_idx : natural range 0 to ARB_MAX_MASTER-1; - signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0); - signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); - - -- J-Bus signals - signal INT : unsigned(5 downto 0); - signal MDAT_I : word_t; - signal MDAT_O : word_t; - signal ADDR_O : word_t; - signal SEL_O : unsigned(3 downto 0); - signal WE_O : std_logic; - signal CYC_O : std_logic; - signal STB_O : std_logic; - signal ACK_I : std_logic; - signal SRDY_I : std_logic; - signal MRDY_O : std_logic; - - -- CPU Master - signal MRDY_O_cpu : std_logic; - signal MDAT_O_cpu : word_t; - signal ADDR_O_cpu : word_t; - signal SEL_O_cpu : unsigned(3 downto 0); - signal WE_O_cpu : std_logic; - signal CYC_O_cpu : std_logic; - signal STB_O_cpu : std_logic; - signal SRDY_I_cpu : std_logic; - signal ACK_I_cpu : std_logic; - - -- VGA Master - signal MRDY_O_vga : std_logic; - signal ADDR_O_vga : word_t; - signal SEL_O_vga : unsigned(7 downto 0); - signal WE_O_vga : std_logic; - signal CYC_O_vga : std_logic; - signal STB_O_vga : std_logic; - signal SRDY_I_vga : std_logic; - signal ACK_I_vga : std_logic; - signal MDAT_I_vga : unsigned(63 downto 0); - signal MDAT_O_vga : unsigned(63 downto 0); - - -- Slaves - signal CYC_I_flash : std_logic; - signal ACK_O_flash : std_logic; - signal SRDY_O_flash : std_logic; - signal SDAT_O_flash : unsigned(31 downto 0); - - signal CYC_I_usb : std_logic; - signal ACK_O_usb : std_logic; - signal SRDY_O_usb : std_logic; - signal SDAT_O_usb : unsigned(31 downto 0); - - signal CYC_I_sdram : std_logic; - signal ACK_O_sdram : std_logic; - signal SRDY_O_sdram : std_logic; - signal SDAT_O_sdram : unsigned(63 downto 0); - signal SDAT_I_sdram : unsigned(63 downto 0); - signal SEL_I_sdram : unsigned(7 downto 0); - - signal CYC_I_rom : std_logic; - signal ACK_O_rom : std_logic; - signal SRDY_O_rom : std_logic; - signal SDAT_O_rom : unsigned(31 downto 0); - - signal CYC_I_gpio : std_logic; - signal ACK_O_gpio : std_logic; - signal SRDY_O_gpio : std_logic; - signal SDAT_O_gpio : unsigned(31 downto 0); - - signal CYC_I_uart0 : std_logic; - signal ACK_O_uart0 : std_logic; - signal SRDY_O_uart0 : std_logic; - signal SDAT_O_uart0 : unsigned(31 downto 0); - signal CYC_I_uart1 : std_logic; - signal ACK_O_uart1 : std_logic; - signal SRDY_O_uart1 : std_logic; - signal SDAT_O_uart1 : unsigned(31 downto 0); - signal CYC_I_uart2 : std_logic; - signal ACK_O_uart2 : std_logic; - signal SRDY_O_uart2 : std_logic; - signal SDAT_O_uart2 : unsigned(31 downto 0); - - signal CYC_I_vga : std_logic; - signal ACK_O_vga : std_logic; - signal SRDY_O_vga : std_logic; - signal SDAT_O_vga : unsigned(31 downto 0); - - signal CYC_I_ssram : std_logic; - signal ACK_O_ssram : std_logic; - signal SRDY_O_ssram : std_logic; - signal SDAT_O_ssram : unsigned(31 downto 0); - - signal INT_O_ac97 : std_logic; - signal CYC_I_ac97 : std_logic; - signal ACK_O_ac97 : std_logic; - signal SRDY_O_ac97 : std_logic; - signal SDAT_O_ac97 : unsigned(31 downto 0); - - signal gpo0 : unsigned(31 downto 0); - signal gpo1 : unsigned(31 downto 0); - signal gpi0 : unsigned(31 downto 0); - signal gpi1 : unsigned(31 downto 0); - - signal debug : unsigned(1 downto 0); - - -- DDR SDRAM - constant BURST_LEN : natural := 2; - constant topad : time := 3 ns; - - --- attribute rom_style: string; --- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED"; --- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED"; - - type mem_area_t is (mem_dead, mem_flash, mem_ssram, mem_usb, mem_rom, mem_gpio, mem_uart0, mem_uart1, mem_uart2, mem_uart, mem_sdram, mem_vga, mem_ac97); - signal mem_area : mem_area_t; - -BEGIN - - eb <= sys_dip(7); - gpi0(4 downto 0) <= sys_btn; - gpi1(7 downto 0) <= sys_dip; - sys_led <= gpo0(8 downto 0); - sys_error <= debug; - nmi <= not sys_rst_n_in; - rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); - rst <= not locked; - sys_usb_rstn <= not gpo1(0); - sys_flash_byten <= '1'; - ADDR_I_usb <= X"0000000" & "00" & ADDR_O(3 downto 2); - ADDR_I_flash <= "0000000" & ADDR_O(25 downto 2) & '0'; - ADDR_I_ssram <= ("0000000000000" & ADDR_O(19 downto 2)) & '0'; - - SDAT_I_sdram <= MDAT_O & MDAT_O; - SEL_I_sdram <= "0000" & SEL_O; - - sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; - -sys_flash_ssram_out: - process(clk) - begin - if rising_edge(clk) then - sys_flash_ssram_d <= (others => 'Z') after topad; - sys_flash_ssram_oe_n <= '1'; - sys_flash_ssram_we_n <= '1'; - if flash_bsy = '1' then - sys_flash_ssram_oe_n <= flash_oe_n; - sys_flash_ssram_we_n <= flash_we_n; - sys_flash_ssram_a <= flash_a after topad; - if flash_d_drv = '1' then - sys_flash_ssram_d <= flash_do after topad; - end if; - elsif ssram_bsy = '1' then - sys_flash_ssram_oe_n <= ssram_oe_n; - sys_flash_ssram_we_n <= ssram_we_n; - sys_flash_ssram_a <= ssram_a after topad; - if ssram_d_drv = '1' then - sys_flash_ssram_d <= ssram_do after topad; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------- - -- Arbiter - MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0'; - MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0'); - ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0'); - SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0'); - WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0'; - CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0'; - STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0'; - SRDY_I_cpu <= SRDY_I and arb_gnt(0); - SRDY_I_vga <= SRDY_I and arb_gnt(1); - ACK_I_cpu <= ACK_I and arb_gnt(0); - ACK_I_vga <= ACK_I and arb_gnt(1); - - arb_req(0) <= CYC_O_cpu; - arb_req(1) <= CYC_O_vga; - - MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I; - -arbiter_proc: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - arb_gnt <= (others => '0'); - arb_idx <= 0; - elsif arb_req(arb_idx) = '0' then - if arb_idx /= ARB_MAX_MASTER-1 then - arb_idx <= arb_idx + 1; - else - arb_idx <= 0; - end if; - else - arb_gnt <= (others => '0'); - arb_gnt(arb_idx) <= '1'; - end if; - end if; - end process; - -int_sample: - process(clk) - begin - if rising_edge(clk) then - INT <= int_timer & '0' & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1 or int_uart2) & sys_btn(4); - end if; - end process; - -mem_mux: - process(ADDR_O) - begin - mem_area <= mem_dead; - flash_page_mode_en <= '0'; - if ADDR_O(31 downto 28) = X"0" then - mem_area <= mem_flash; - flash_page_mode_en <= '1'; - elsif ADDR_O(31 downto 28) = X"A" then - if ADDR_O(27 downto 26) = "00" then - if ADDR_O(18 downto 16) = "000" then - mem_area <= mem_gpio; - elsif ADDR_O(18 downto 16) = "001" then - if ADDR_O(9 downto 8) = "00" then - mem_area <= mem_uart0; - elsif ADDR_O(9 downto 8) = "01" then - mem_area <= mem_uart1; - elsif ADDR_O(9 downto 8) = "10" then - mem_area <= mem_uart2; - end if; - elsif ADDR_O(18 downto 16) = "010" then - mem_area <= mem_usb; - elsif ADDR_O(18 downto 16) = "011" then - mem_area <= mem_vga; - elsif ADDR_O(18 downto 16) = "100" then - mem_area <= mem_ac97; - end if; - elsif ADDR_O(27 downto 26) = "01" then - mem_area <= mem_flash; - elsif ADDR_O(27 downto 26) = "10" then - mem_area <= mem_ssram; - end if; - elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then - mem_area <= mem_rom; --- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then - -- kernel sram - elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then - mem_area <= mem_sdram; - end if; - end process; - -signal_mux: - process(mem_area, CYC_O) - begin - - CYC_I_uart0 <= '0'; - CYC_I_uart1 <= '0'; - CYC_I_uart2 <= '0'; - CYC_I_gpio <= '0'; - CYC_I_flash <= '0'; - CYC_I_usb <= '0'; - CYC_I_rom <= '0'; - CYC_I_sdram <= '0'; - CYC_I_vga <= '0'; - CYC_I_ssram <= '0'; - CYC_I_ac97 <= '0'; - - case mem_area is - - when mem_gpio => - CYC_I_gpio <= CYC_O; - - when mem_uart0 => - CYC_I_uart0 <= CYC_O; - - when mem_uart1 => - CYC_I_uart1 <= CYC_O; - - when mem_uart2 => - CYC_I_uart2 <= CYC_O; - - when mem_flash => - CYC_I_flash <= CYC_O; - - when mem_usb => - CYC_I_usb <= CYC_O; - - when mem_rom => - CYC_I_rom <= CYC_O; - - when mem_sdram => - CYC_I_sdram <= CYC_O; - - when mem_vga => - CYC_I_vga <= CYC_O; - - when mem_ac97 => - CYC_I_ac97 <= CYC_O; - - when mem_ssram => - CYC_I_ssram <= CYC_O; - - when others => null; - - end case; - - end process; - ------------------------------------------------------------------- - SRDY_I <= SRDY_O_flash or SRDY_O_ssram or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_uart2 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97; - ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ssram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_uart2 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97; - MDAT_I <= SDAT_O_ssram when CYC_I_ssram = '1' else - SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else - SDAT_O_rom when CYC_I_rom = '1' else - SDAT_O_flash when CYC_I_flash = '1' else - SDAT_O_usb when CYC_I_usb = '1' else - SDAT_O_uart0 when CYC_I_uart0 = '1' else - SDAT_O_uart1 when CYC_I_uart1 = '1' else - SDAT_O_uart2 when CYC_I_uart2 = '1' else - SDAT_O_vga when CYC_I_vga = '1' else - SDAT_O_ac97 when CYC_I_ac97 = '1' else - SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF"; - ------------------------------------------------------------------- -inst_mips_top: mips_top - PORT MAP - ( - debug => debug, - eb => eb, - nmi => nmi, - RST_I => rst, - CLK_I => clk, - ACK_I => ACK_I_cpu, - SRDY_I => SRDY_I_cpu, - MRDY_O => MRDY_O_cpu, - CYC_O => CYC_O_cpu, - STB_O => STB_O_cpu, - WE_O => WE_O_cpu, - SEL_O => SEL_O_cpu, - DAT_I => MDAT_I, - DAT_O => MDAT_O_cpu, - ADDR_O => ADDR_O_cpu, - INT => INT - ); - -inst_rom_wb : rom_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_rom, - STB_I => STB_O, - ACK_O => ACK_O_rom, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_rom, - ADDR_I => ADDR_O, - DAT_O => SDAT_O_rom - ); - - -inst_lcd_port: lcd_port - PORT MAP - ( - clk => clk, - rst => rst, - we => '0', - din => X"00", - dout => open, - lcd_d => sys_lcd_d, - lcd_e => sys_lcd_e, - lcd_rs => sys_lcd_rs, - lcd_rw => sys_lcd_rw - ); - -inst_gpio_wb : gpio_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_gpio, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_gpio, - SRDY_O => SRDY_O_gpio, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_gpio, - INT_TIM_O => int_timer, - - sys_gpo0 => gpo0, - sys_gpo1 => gpo1, - sys_gpi0 => gpi0, - sys_gpi1 => gpi1 - ); - -inst_flash_port : flash_port_wb - GENERIC MAP - ( - addr_width => 25, - data_width => 32, - async_timespec => ts_flash - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_flash, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_flash, - SRDY_O => SRDY_O_flash, - MRDY_I => MRDY_O, - ADDR_I => ADDR_I_flash, - DAT_I => MDAT_O, - DAT_O => SDAT_O_flash, - port_bsyo => flash_bsy, - port_bsyi => ssram_bsy, - port_a => flash_a, - port_di => sys_flash_ssram_d, - port_do => flash_do, - port_d_drv => flash_d_drv, - port_wr => flash_we_n, - port_rd => flash_oe_n, - flash_cs => sys_flash_ce, - flash_rst => flash_rstn - ); - -inst_usb_port : async_port_wb - GENERIC MAP - ( - addr_width => 2, - data_width => 16, - byte_sel_width => 1, - async_timespec => ts_usb - ) - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_usb, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_usb, - SRDY_O => SRDY_O_usb, - MRDY_I => MRDY_O, - SEL_I => SEL_O, - ADDR_I => ADDR_I_usb, - DAT_I => MDAT_O, - DAT_O => SDAT_O_usb, - page_mode_en => '0', - async_a => sys_usb_a, - async_d => sys_usb_d, - async_cs => sys_usb_csn, - async_wr => sys_usb_wrn, - async_rd => sys_usb_rdn, - async_be => open, - async_rst => open - ); - -inst_uart_wb_0 : uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart0, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart0, - SRDY_O => SRDY_O_uart0, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart0, - INT_O => int_uart0, - ser_rx => sys_uart0_rx, - ser_tx => sys_uart0_tx - ); - -inst_uart_wb_1 : uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart1, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart1, - SRDY_O => SRDY_O_uart1, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart1, - INT_O => int_uart1, - ser_rx => sys_uart1_rx, - ser_tx => sys_uart1_tx - ); - -inst_uart_wb_2 : uart_wb - PORT MAP - ( - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_uart2, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_uart2, - SRDY_O => SRDY_O_uart2, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_uart2, - INT_O => int_uart2, - ser_rx => sys_uart2_rx, - ser_tx => sys_uart2_tx - ); -inst_ssram_port_wb : entity work.ssram_port_wb - GENERIC MAP - ( - addr_width => 25, - data_width => 32, - parity_width => 4 - ) - PORT MAP - ( - -- J-Bus domain - RST_I => rst, - CLK_I => clk, - CYC_I => CYC_I_ssram, - STB_I => STB_O, - SEL_I => SEL_O, - WE_I => WE_O, - ACK_O => ACK_O_ssram, - SRDY_O => SRDY_O_ssram, - MRDY_I => MRDY_O, - ADDR_I => ADDR_I_ssram, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ssram, - - -- Sync SRAM domain - ssram_clk_o => sys_ssram_clk, - ssram_clk_fb => sys_ssram_clk_fb, - ssram_cke_n => sys_ssram_cke_n, - ssram_ce_n => sys_ssram_ce_n, - port_bsyo => ssram_bsy, - port_bsyi => flash_bsy, - port_di => sys_flash_ssram_d, - port_do => ssram_do, - port_d_drv => ssram_d_drv, - port_wr => ssram_we_n, - port_rd => ssram_oe_n, - port_a => ssram_a, - ssram_adv => sys_ssram_adv, - ssram_mode => sys_ssram_mode, - ssram_zz => sys_ssram_zz, - ssram_dp => sys_ssram_dp, - ssram_bw_n => sys_ssram_bw_n - ); - -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb - GENERIC MAP - ( - BL => BURST_LEN, - f_sysclk => ddr_frequency_hz, - fifo_depth => 5 - ) - PORT MAP - ( - RST_I => rst, - CLK_I => clk, - CLK270_I => clk270, - CLK270VAR_I => clk270var, - - CYC_I => CYC_I_sdram, - STB_I => STB_O, - SEL_I => SEL_I_sdram, - WE_I => WE_O, - ACK_O => ACK_O_sdram, - MRDY_I => MRDY_O, - SRDY_O => SRDY_O_sdram, - ADDR_I => ADDR_O, - DAT_I => SDAT_I_sdram, - DAT_O => SDAT_O_sdram, - - -- SDRAM signals - sd_clk_p => sys_sdr_clk_p, - sd_clk_n => sys_sdr_clk_n, - sd_cke => sys_sdr_cke_q, - sd_cs_n => sys_sdr_cs_qn, - sd_cas_n => sys_sdr_cas_qn, - sd_ras_n => sys_sdr_ras_qn, - sd_we_n => sys_sdr_we_qn, - sd_addr => sys_sdr_a_q, - sd_ba => sys_sdr_ba_q, - sd_dm => sys_sdr_dm_q, - sd_dqs => sys_sdr_dqs_q, - sd_data => sys_sdr_data - - ); - -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - sys1_phaseshift => 0, - frequency_hz => 100E6 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst_in, -- external async reset, low active - clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board - clk_fb_in => sys_sdr_clk_fb, -- feedback clock - sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0° - sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270° - locked_out => locked, -- DCM locked status - error_out => open - ); - -inst_vga_frontend : vga_frontend64 - GENERIC MAP - ( - sys_freq => 100E6, - fifo_depth => 2048, - fifo_almost_full_thresh => 1860, - fifo_almost_empty_thresh => 256, - tsvga => ts_vga_testbench - ) - PORT MAP - ( - -- System signals - RST_I => rst, - CLK_I => clk, - - -- JBUS Master signals - CYC_O => CYC_O_vga, - STB_O => STB_O_vga, - WE_O => WE_O_vga, - SEL_O => SEL_O_vga, - ACK_I => ACK_I_vga, - SRDY_I => SRDY_I_vga, - MRDY_O => MRDY_O_vga, - ADDR_O => ADDR_O_vga, - MDAT_I => MDAT_I_vga, - MDAT_O => MDAT_O_vga, - - -- JBUS Slave signals - CYC_I => CYC_I_vga, - STB_I => STB_O, - WE_I => WE_O, - SEL_I => SEL_O, - ACK_O => ACK_O_vga, - SRDY_O => SRDY_O_vga, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - SDAT_I => MDAT_O, - SDAT_O => SDAT_O_vga, - - -- VGA signals - vga_clk_out => sys_vga_clk, - vga_red => sys_vga_red, - vga_green => sys_vga_green, - vga_blue => sys_vga_blue, - vga_blank_n => sys_vga_blank_n, - vga_sync_n => sys_vga_sync_n, - vga_hsync => sys_vga_hsync, - vga_vsync => sys_vga_vsync - ); - -inst_ac97_wb : entity work.ac97_wb - GENERIC MAP - ( - fifo_depth => 4 - ) - PORT MAP - ( - -- J-Bus domain - CLK_I => clk, - RST_I => rst, - CYC_I => CYC_I_ac97, - STB_I => STB_O, - WE_I => WE_O, - ACK_O => ACK_O_ac97, - SRDY_O => SRDY_O_ac97, - MRDY_I => MRDY_O, - ADDR_I => ADDR_O, - DAT_I => MDAT_O, - DAT_O => SDAT_O_ac97, - INT_O => INT_O_ac97, - - -- AC97 domain - ac97_sdata_in => sys_ac97_sdata_in, - ac97_bit_clk => sys_ac97_bit_clk, - ac97_reset_n => ac97_rstn, - ac97_sdata_out => sys_ac97_sdata_out, - ac97_ssync => sys_ac97_ssync - ); - - ------------------------------------------------------------------ -END; diff --git a/projects/mips_sys/src/ram_ld.vhd b/projects/mips_sys/src/ram_ld.vhd deleted file mode 100644 index 17879e1..0000000 --- a/projects/mips_sys/src/ram_ld.vhd +++ /dev/null @@ -1,173 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY ram IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - COMPONENT dpram_2w2r - Generic - ( - addr_width : integer; - data_width : integer - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - signal jtag_clk : STD_LOGIC; - signal jtag_we : unsigned(3 downto 0); - signal jtag_addr : unsigned (15 downto 0); - signal jtag_dout : unsigned (31 downto 0); - signal jtag_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - -BEGIN - -gen_sram: - for i in 0 to 3 generate - begin - inst_dpram_2w2r : dpram_2w2r - GENERIC MAP - ( - addr_width => 11, - data_width => 8 - ) - PORT MAP - ( - clk_a => clk, - en_a => ce, - we_a => we(i), - addr_a => addr(12 downto 2), - din_a => din((i+1)*8-1 downto i*8), - dout_a => dout((i+1)*8-1 downto i*8), - - clk_b => jtag_clk, - en_b => jtag_we(i), - we_b => jtag_we(i), - addr_b => jtag_addr(10 downto 0), - din_b => jtag_din((i+1)*8-1 downto i*8), - dout_b => jtag_dout((i+1)*8-1 downto i*8) - ); - end generate; - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_addr <= user_regi(user_regi'left downto jtag_dout'length); - jtag_din <= user_regi(jtag_dout'length-1 downto 0); - jtag_clk <= bs_update1; - jtag_we <= (3 downto 0 => bs_sel); - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end behavior; diff --git a/projects/mips_sys/src/ram_sim.vhd b/projects/mips_sys/src/ram_sim.vhd deleted file mode 100644 index 6d26672..0000000 --- a/projects/mips_sys/src/ram_sim.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(31 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram(index)(7 downto 0) <= din(7 downto 0); - end if; - if we(1) = '1' then - sram(index)(15 downto 8) <= din(15 downto 8); - end if; - if we(2) = '1' then - sram(index)(23 downto 16) <= din(23 downto 16); - end if; - if we(3) = '1' then - sram(index)(31 downto 24) <= din(31 downto 24); - end if; - dout <= sram(index); - end if; - end process; - -end behavior; diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd deleted file mode 100644 index 1bdf8e0..0000000 --- a/projects/mips_sys/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 5; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 222; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd deleted file mode 100644 index f698b29..0000000 --- a/projects/mips_sys/src/sdram_config_sim.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 5; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 22; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/projects/mips_sys/src/sys_types.vhd b/projects/mips_sys/src/sys_types.vhd deleted file mode 100644 index b861609..0000000 --- a/projects/mips_sys/src/sys_types.vhd +++ /dev/null @@ -1,70 +0,0 @@ -------------------------------------------------------------------------- --- Project: MIPS System controller --- This file: --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.async_types.all; - -package async_defs is - - constant ts_flash : async_timespec_t := - ( - ncyc_leadin => 1, - ncyc_pulse_rd => 12, - ncyc_pulse_wr => 7, - ncyc_leadout => 1, - ncyc_release => 1, - ncyc_pulse_rst => 8, - can_page_rd => true, - nbits_page_rd => 4, - ncyc_pulse_page_rd => 6, - pol_cs => '1', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - constant ts_usb : async_timespec_t := - ( - ncyc_leadin => 1, - ncyc_pulse_rd => 6, - ncyc_pulse_wr => 6, - ncyc_leadout => 1, - ncyc_release => 6, - ncyc_pulse_rst => 8, - can_page_rd => false, - nbits_page_rd => 0, - ncyc_pulse_page_rd => 0, - pol_cs => '0', - pol_oe => '0', - pol_we => '0', - pol_be => '0', - pol_rst => '0' - ); - - ---------------------------------------------------------------------------------------------- - -end async_defs; diff --git a/projects/mips_sys/src/tb_mips_sys.vhd b/projects/mips_sys/src/tb_mips_sys.vhd deleted file mode 100644 index a50abf3..0000000 --- a/projects/mips_sys/src/tb_mips_sys.vhd +++ /dev/null @@ -1,351 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for system test using Xilinx ML-402 - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.sdram_config.all; -use work.sdram_types.all; - -ENTITY tb_mips_sys IS -END tb_mips_sys; - -ARCHITECTURE behavior OF tb_mips_sys IS - - constant CLK_PERIOD : time := 10 ns; - constant AC97_CLK_PERIOD : time := 83 ns; - signal sys_rst_n_in : std_logic := '0'; - signal sys_clk_in : std_logic := '1'; - signal dip : unsigned(7 downto 0) := (others => '0'); - signal btn : unsigned(4 downto 0) := (others => '0'); - signal led : unsigned(8 downto 0); - signal sys_rx : std_logic := '1'; - signal sys_tx : std_logic; - signal sys_rx1 : std_logic := '1'; - signal sys_tx1 : std_logic; - signal sys_rx2 : std_logic := '1'; - signal sys_tx2 : std_logic; - - signal sys_lcd_d : unsigned(3 downto 0); - signal sys_lcd_e : std_logic; - signal sys_lcd_rs : std_logic; - signal sys_lcd_rw : std_logic; - - signal refresh : boolean:= true; - - signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock - signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock - signal sys_sdr_cke_q : std_logic; -- clock enable - signal sys_sdr_cs_qn : std_logic; -- /chip select - signal sys_sdr_ras_qn : std_logic; -- /ras - signal sys_sdr_cas_qn : std_logic; -- /cas - signal sys_sdr_we_qn : std_logic; -- /write enable - signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00" - signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write - signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select - signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus - signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus - - signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors - signal sys_sdr_clk_fb : std_logic; - - signal sys_usb_d : unsigned(15 downto 0) := (others => '0'); - signal sys_usb_a : unsigned(1 downto 0); - signal sys_usb_csn : std_logic; - signal sys_usb_wrn : std_logic; - signal sys_usb_rdn : std_logic; - signal sys_usb_rstn : std_logic; - signal sys_usb_int : std_logic := '0'; - - signal sys_flash_ssram_d : word_t; - signal sys_flash_ssram_a : unsigned(24 downto 0); - signal sys_flash_ssram_we_n : std_logic; - signal sys_flash_ssram_oe_n : std_logic; - - signal sys_flash_ce : std_logic; - signal sys_flash_ac97_rstn : std_logic; - signal sys_flash_byten : std_logic; - - signal sys_ssram_clk_fb : std_logic; - signal sys_ssram_clk : std_logic; - signal sys_ssram_cke_n : std_logic; - signal sys_ssram_ce_n : std_logic; - signal sys_ssram_bw_n : unsigned(3 downto 0); - signal sys_ssram_dp : unsigned(3 downto 0); - signal sys_ssram_adv : std_logic; - signal sys_ssram_mode : std_logic; - signal sys_ssram_zz : std_logic; - - SIGNAL sys_ac97_bit_clk : std_logic := '0'; - SIGNAL sys_ac97_sdata_out : std_logic; - SIGNAL sys_ac97_ssync : std_logic; - SIGNAL sys_ac97_sdata_in : std_logic; - - signal flash_reg : word_t; - - type flash_data_t is array (natural range 0 to 2**16-1) of word_t; - signal flash_data : flash_data_t; - - signal ac_frame_reg : unsigned(255 downto 0) := (others => '0'); - signal ac_left : unsigned(17 downto 0) := X"0000" & "00"; - signal ac_right : unsigned(17 downto 0) := X"0000" & "01"; - signal ac_synced : std_logic; - -BEGIN - -uut: entity work.mips_sys --- GENERIC MAP --- ( --- ddr_phaseshift => 90, --- ddr_frequency_hz => 100E6 --- ) - PORT MAP - ( - sys_rst_n_in => sys_rst_n_in, - sys_clk_in => sys_clk_in, - sys_btn => btn, - sys_dip => dip, - sys_led => led, - - sys_uart0_rx => sys_rx, - sys_uart0_tx => sys_tx, - sys_uart1_rx => sys_rx1, - sys_uart1_tx => sys_tx1, - sys_uart2_rx => sys_rx2, - sys_uart2_tx => sys_tx2, - - sys_lcd_d => sys_lcd_d, - sys_lcd_e => sys_lcd_e, - sys_lcd_rs => sys_lcd_rs, - sys_lcd_rw => sys_lcd_rw, - - sys_sdr_clk_p => sys_sdr_clk_p, - sys_sdr_clk_n => sys_sdr_clk_n, - sys_sdr_cke_q => sys_sdr_cke_q, - sys_sdr_clk_fb => sys_sdr_clk_fb, - sys_sdr_cs_qn => sys_sdr_cs_qn, - sys_sdr_ras_qn => sys_sdr_ras_qn, - sys_sdr_cas_qn => sys_sdr_cas_qn, - sys_sdr_we_qn => sys_sdr_we_qn, - sys_sdr_dm_q => sys_sdr_dm_q, - sys_sdr_dqs_q => sys_sdr_dqs_q, - sys_sdr_ba_q => sys_sdr_ba_q, - sys_sdr_a_q => sys_sdr_a_q, - sys_sdr_data => sys_sdr_data, - - sys_usb_d => sys_usb_d, - sys_usb_a => sys_usb_a, - sys_usb_csn => sys_usb_csn, - sys_usb_wrn => sys_usb_wrn, - sys_usb_rdn => sys_usb_rdn, - sys_usb_rstn => sys_usb_rstn, - sys_usb_int => sys_usb_int, - - sys_flash_ssram_d => sys_flash_ssram_d, - sys_flash_ssram_a => sys_flash_ssram_a, - sys_flash_ssram_we_n => sys_flash_ssram_we_n, - sys_flash_ssram_oe_n => sys_flash_ssram_oe_n, - sys_flash_ce => sys_flash_ce, - sys_flash_ac97_rstn => sys_flash_ac97_rstn, - sys_flash_byten => sys_flash_byten, - - sys_ssram_clk_fb => sys_ssram_clk_fb, - sys_ssram_clk => sys_ssram_clk, - sys_ssram_cke_n => sys_ssram_cke_n, - sys_ssram_ce_n => sys_ssram_ce_n, - sys_ssram_bw_n => sys_ssram_bw_n, - sys_ssram_dp => sys_ssram_dp, - sys_ssram_adv => sys_ssram_adv, - sys_ssram_mode => sys_ssram_mode, - sys_ssram_zz => sys_ssram_zz, - - sys_ac97_bit_clk => sys_ac97_bit_clk, - sys_ac97_sdata_out => sys_ac97_sdata_out, - sys_ac97_ssync => sys_ac97_ssync, - sys_ac97_sdata_in => sys_ac97_sdata_in, - - sys_error => sys_error - ); - -inst_ssram : entity work.cy7c1354 - PORT MAP - ( - Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O - Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O - Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address - Mode => sys_ssram_mode, -- Burst Mode - Clk => sys_ssram_clk, -- Clk - CEN_n => sys_ssram_cke_n, -- CEN# - AdvLd_n => sys_ssram_adv, -- Adv/Ld# - Bwa_n => sys_ssram_bw_n(0), -- Bwa# - Bwb_n => sys_ssram_bw_n(1), -- BWb# - Bwc_n => sys_ssram_bw_n(2), -- Bwc# - Bwd_n => sys_ssram_bw_n(3), -- BWd# - Rw_n => sys_flash_ssram_we_n, -- RW# - Oe_n => sys_flash_ssram_oe_n, -- OE# - Ce1_n => sys_ssram_ce_n, -- CE1# - Ce2 => '1', -- CE2 - Ce3_n => '0', -- CE3# - Zz => sys_ssram_zz - ); - --- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(sys_sdr_data(15 downto 0)), - dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)), - addr => std_logic_vector(sys_sdr_a_q), - ba => std_logic_vector(sys_sdr_ba_q), - clk => sys_sdr_clk_p, - clk_n => sys_sdr_clk_n, - cke => sys_sdr_cke_q, - cs_n => sys_sdr_cs_qn, - ras_n => sys_sdr_ras_qn, - cas_n => sys_sdr_cas_qn, - we_n => sys_sdr_we_qn, - dm => std_logic_vector(sys_sdr_dm_q(1 downto 0)) - ); - --- MICRON DDR SDRAM Simulation Model -i_mt46v16m16_1 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(sys_sdr_data(31 downto 16)), - dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)), - addr => std_logic_vector(sys_sdr_a_q), - ba => std_logic_vector(sys_sdr_ba_q), - clk => sys_sdr_clk_p, - clk_n => sys_sdr_clk_n, - cke => sys_sdr_cke_q, - cs_n => sys_sdr_cs_qn, - ras_n => sys_sdr_ras_qn, - cas_n => sys_sdr_cas_qn, - we_n => sys_sdr_we_qn, - dm => std_logic_vector(sys_sdr_dm_q(3 downto 2)) - ); - - sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps; - sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns; - - refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false; - - sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns; - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - sys_clk_in <= not sys_clk_in; - end process; - - - sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out; - -ac97_data_gen : - PROCESS(sys_ac97_bit_clk) - begin - if rising_edge(sys_ac97_bit_clk) then - ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0'; - if sys_flash_ac97_rstn = '0' then - ac_synced <= '0'; - elsif sys_ac97_ssync = '1' then - if ac_synced = '0' then - ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000"; - ac_left <= ac_left + 2; - ac_right <= ac_right + 2; - ac_synced <= '1'; - end if; - else - ac_synced <= '0'; - end if; - end if; - END PROCESS; - -ac97_clk_gen : PROCESS - begin - if (sys_flash_ac97_rstn = '0') then - sys_ac97_bit_clk <= '0'; - wait until sys_flash_ac97_rstn = '1'; - wait for 150 us; - end if; - wait for AC97_CLK_PERIOD/2; - sys_ac97_bit_clk <= not sys_ac97_bit_clk; - END PROCESS; - -FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a) - type file_t is file of integer; - file load_flash : file_t open read_mode is "test_ac97.flash.bin"; - variable instr : integer; - variable index : natural; - variable temp : signed(31 downto 0); - begin - if sys_rst_n_in = '0' then - index := 0; - while not endfile(load_flash) loop - read(load_flash, instr); - temp := to_signed(instr, word_t'length); - flash_data(index) <= unsigned(temp); - index := index + 1; - end loop; - else - sys_flash_ssram_d <= (others => 'Z') after 10 ns; - if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then - index := to_integer(sys_flash_ssram_a(24 downto 1)); - sys_flash_ssram_d <= flash_data(index) after 10 ns; - end if; - end if; - end process; - -FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d) - begin - if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then - flash_reg <= sys_flash_ssram_d; - end if; - end process; - -STIMULUS: process - - begin - - btn(0) <= '1'; - btn(2) <= '1'; - wait for 3*CLK_PERIOD; - sys_rst_n_in <= '1'; - btn(0) <= '0'; - btn(2) <= '0'; - wait for 200000*CLK_PERIOD; - - loop - wait for 251*CLK_PERIOD; - btn(4) <= '1'; - wait for 311*CLK_PERIOD; - btn(4) <= '0'; - end loop; - wait; - - end process; - -END; diff --git a/projects/mips_sys/tools/insrom.rb b/projects/mips_sys/tools/insrom.rb deleted file mode 100644 index fdbf1ed..0000000 --- a/projects/mips_sys/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JIPS, a portable 32-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2008 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/projects/mips_sys/tools/irom.vhd.tpl b/projects/mips_sys/tools/irom.vhd.tpl deleted file mode 100644 index 5ffd6d7..0000000 --- a/projects/mips_sys/tools/irom.vhd.tpl +++ /dev/null @@ -1,29 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - --- ROM_INSERT_HERE - diff --git a/projects/mips_sys/tools/irom_ld.vhd.tpl b/projects/mips_sys/tools/irom_ld.vhd.tpl deleted file mode 100644 index 3bd3afb..0000000 --- a/projects/mips_sys/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,147 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/projects/mips_sys/tools/make b/projects/mips_sys/tools/make deleted file mode 100644 index e7f598f..0000000 --- a/projects/mips_sys/tools/make +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/projects/mips_sys/tools/rom.tcl.tpl b/projects/mips_sys/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/projects/mips_sys/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/projects/mips_sys/tools/src/flashgen.c b/projects/mips_sys/tools/src/flashgen.c deleted file mode 100644 index 4b75814..0000000 --- a/projects/mips_sys/tools/src/flashgen.c +++ /dev/null @@ -1,117 +0,0 @@ -#include -#include -#include -#include - -#define INT8 char -#define INT16 short -#define INT32 long -#define UINT8 unsigned char -#define UINT16 unsigned short -#define UINT32 unsigned long -#define INT int -#define UINT unsigned int -#define FLOAT32 float -#define FLOAT64 double - -#define SDRAM_BASE 0x40000000 -#define FLASH_OFFSET 0x00000000 - -// -------------------------------------------------------------- -typedef struct _sflash_img_hdr_t -{ - UINT8 magic[4]; - UINT32 target_addr; - UINT32 img_offset; - UINT32 img_size; - UINT32 hdr_next; - UINT8 img_name[128]; - UINT8 res[108]; - -} flash_img_hdr_t; - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -// -------------------------------------------------------------- -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_flash[1024]; - char name_prj[1024]; - char *pBuf; - flash_img_hdr_t img_hdr = {0}; - - FILE *pFile; - int filesize; - long start, end; - int i; - - if (argc < 2) - { - fprintf(stderr, "Usage: flashgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - pFile = fopen(pFilenameIn, "rb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - basename(pFilenameIn, name_prj); - sprintf(name_flash, "%s.flash.bin", name_prj); - - // determine filesize - fseek(pFile, 0, SEEK_SET); - start = ftell(pFile); - fseek(pFile, 0, SEEK_END); - end = ftell(pFile); - fseek(pFile, 0, SEEK_SET); - filesize = (end-start); - - pBuf = (char*)malloc(filesize); - fread(pBuf, 1, filesize, pFile); - - fclose(pFile); - - pFile = fopen(name_flash, "wb"); - if (!pFile) - { - fprintf(stderr, "Error opening file %s\n", name_flash); - return 1; - } - - img_hdr.magic[0] = 'J'; - img_hdr.magic[1] = 'F'; - img_hdr.magic[2] = 'I'; - img_hdr.magic[3] = '1'; - img_hdr.target_addr = SDRAM_BASE; - img_hdr.img_size = filesize; - img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t); - img_hdr.hdr_next = FLASH_OFFSET; - - fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile); - fwrite(pBuf, 1, filesize, pFile); - - fclose(pFile); - - return 0; -} - diff --git a/projects/mips_sys/tools/src/ramgen.c b/projects/mips_sys/tools/src/ramgen.c deleted file mode 100644 index 8f61118..0000000 --- a/projects/mips_sys/tools/src/ramgen.c +++ /dev/null @@ -1,385 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4); - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal sram : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1); - fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n"); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\t\tdout <= sram(index);\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: ramgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); -// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c deleted file mode 100644 index a59e705..0000000 --- a/projects/mips_sys/tools/src/romgen.c +++ /dev/null @@ -1,368 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "rom" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} -

-Name