diff --git a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd b/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
index 7d7b1c2..76e3bf5 100644
--- a/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
+++ b/lib/CPUs/MIPS/dist/tmpl/mips_sys.vhd
@@ -73,8 +73,6 @@ END mips_sys;
 
 ARCHITECTURE behavior OF mips_sys IS 
 
-	constant CLK_PERIOD 			: time := 10 ns;
-	
 	-- Master 
 	signal ACK_I		: STD_LOGIC := '0';
 	signal SRDY_I		: STD_LOGIC := '0';
@@ -114,6 +112,7 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal SRDY_O_uart	: std_logic;
 	signal DAT_O_uart	: unsigned(31 downto 0);
 
+	signal int_timer	: std_logic;
 	signal int_uart		: std_logic;
 
 	type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
@@ -201,6 +200,7 @@ inst_mips_top: entity work.mips_top
 		debug	=> debug,
 		nmi		=> nmi,
 		eb		=> eb,
+		cpu_clk	=> clk,
 		RST_I	=> rst,
 		CLK_I	=> clk,
 		ACK_I	=> ACK_I,
@@ -216,6 +216,7 @@ inst_mips_top: entity work.mips_top
 		INT		=> INT
 	);
 	INT(1)	<= int_uart;
+	INT(5)	<= int_timer;
 	
 inst_rom : entity work.rom_wb
 	PORT MAP
@@ -246,7 +247,7 @@ inst_gpio : entity work.gpio_wb
 		ADDR_I		=> ADDR_O,
 		DAT_I		=> DAT_O,
 		DAT_O		=> DAT_O_gpio,
-
+		INT_TIM_O	=> int_timer,
 		sys_gpo0	=> gpo0,
 		sys_gpo1	=> gpo1,
 		sys_gpi0	=> gpi0,