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- weird blitter stuff

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git-svn-id: http://moon:8086/svn/vhdl/trunk@955 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-04-27 17:46:26 +00:00
parent 2e8a574d88
commit a6a659904b
2 changed files with 117 additions and 110 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+12 -12
View File
@@ -420,10 +420,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
@@ -456,10 +456,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
@@ -492,10 +492,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
@@ -528,10 +528,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
@@ -563,10 +563,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
@@ -598,10 +598,10 @@ STIMULUS: process
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32)); reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx -- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32)); reg_write(X"0000_0060", to_unsigned(blit_size_x(i), 32));
-- set ny -- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32)); reg_write(X"0000_0064", to_unsigned(blit_size_y(i), 32));
-- set blit request -- set blit request
reg_read(X"0000_0000"); reg_read(X"0000_0000");
lib/VGA_ctrl/src/vga_frontend64.vhd
+104 -97
View File
@@ -22,6 +22,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use work.utils_pkg.all; use work.utils_pkg.all;
use work.align_types.all;
use work.vga_types.all; use work.vga_types.all;
entity vga_frontend64 is entity vga_frontend64 is
@@ -139,7 +140,6 @@ architecture Behavioral of vga_frontend64 is
signal blit_dimx_src_0 : unsigned(31 downto 0); signal blit_dimx_src_0 : unsigned(31 downto 0);
signal blit_dimx_src_1 : unsigned(31 downto 0); signal blit_dimx_src_1 : unsigned(31 downto 0);
signal blit_dimx_dst : unsigned(31 downto 0); signal blit_dimx_dst : unsigned(31 downto 0);
signal host_blit_nx : unsigned(31 downto 0);
signal blit_nx : unsigned(31 downto 0); signal blit_nx : unsigned(31 downto 0);
signal blit_ny : unsigned(31 downto 0); signal blit_ny : unsigned(31 downto 0);
signal blit_func_sel : unsigned(3 downto 0); signal blit_func_sel : unsigned(3 downto 0);
@@ -204,26 +204,21 @@ architecture Behavioral of vga_frontend64 is
signal CYC_O_blit_src : std_logic; signal CYC_O_blit_src : std_logic;
signal STB_O_blit_src : std_logic; signal STB_O_blit_src : std_logic;
signal ADDR_O_blit_src : unsigned(31 downto 0); signal ADDR_O_blit_src : unsigned(31 downto 0);
signal blit_src_nx : unsigned(31 downto 0);
-- Destination alignment register -- Destination alignment register
signal blit_dst_reg : unsigned(63 downto 0); signal blit_dst_cmd_rdy : std_logic;
signal blit_dst_reg_vld : std_logic; signal blit_dst_cmd_vld : std_logic;
signal blit_dst_unaligned : std_logic; signal blit_dst_din_rdy : std_logic;
signal blit_dst_row_cnt : unsigned(31 downto 0); signal blit_dst_din_vld : std_logic;
signal blit_dst_first : std_logic; signal blit_dst_dout_re : std_logic;
signal blit_dst_last : std_logic; signal blit_dst_dout_be : unsigned(7 downto 0);
signal blit_dst_do_extra : std_logic; signal blit_dst_dout_vld : std_logic;
signal blit_dst_reg_be : unsigned(7 downto 0);
signal blit_dst_rdy : std_logic;
signal blit_dst_we : std_logic;
signal blit_dst_re : std_logic;
signal blit_dst_be : unsigned(7 downto 0);
signal blit_dst_vld : std_logic;
signal blit_dst_cnt_x : unsigned(31 downto 0);
signal blit_dst_cnt_y : unsigned(31 downto 0); signal blit_dst_cnt_y : unsigned(31 downto 0);
signal blit_dst_off_y : unsigned(31 downto 0);
signal blit_dst_offset : unsigned(31 downto 0); signal blit_dst_offset : unsigned(31 downto 0);
signal blit_dst_dout : unsigned(63 downto 0);
signal blit_dst_finish : std_logic; signal blit_dst_finish : std_logic;
signal blit_dst_cmd : align_cmd_in_t;
signal blit_const_color : unsigned(31 downto 0); signal blit_const_color : unsigned(31 downto 0);
signal blit_const_color_en : std_logic; signal blit_const_color_en : std_logic;
@@ -462,11 +457,11 @@ inst_busout_fifo: entity work.fifo_sync
busout_fifo_rdy <= not busout_fifo_full; busout_fifo_rdy <= not busout_fifo_full;
busout_fifo_re <= not busout_fifo_empty and SRDY_I; busout_fifo_re <= not busout_fifo_empty and SRDY_I;
busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst); busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
busout_fifo_data_in <= blit_dst_reg; busout_fifo_data_in <= blit_dst_dout;
busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan; ADDR_O_scan;
busout_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1'); busout_fifo_sel_in <= blit_dst_dout_be when CYC_O_blit_dst = '1' else (others => '1');
busout_fifo_we_in <= CYC_O_blit_dst; busout_fifo_we_in <= CYC_O_blit_dst;
CYC_O <= bus_cycle_en; CYC_O <= bus_cycle_en;
@@ -485,7 +480,7 @@ vga_master_next:
end process; end process;
vga_master: vga_master:
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_vld, blit_src_finish, blit_const_color_en) process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_dout_vld, blit_src_finish, blit_const_color_en)
begin begin
CYC_O_scan <= '0'; CYC_O_scan <= '0';
@@ -515,8 +510,8 @@ vga_master:
if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
sn <= scan_bus_request; sn <= scan_bus_request;
elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen elsif blit_request = '1' then -- ToDo: richtig prüfen anhand eines states wer dran ist. Nicht auf FIFO state prüfen
if blitfifo_src_empty = '0' or blit_dst_vld = '1' then if blit_dst_dout_vld = '1' then
sn <= blit_dst_prime_pipe; sn <= blit_dst_bus_request;
elsif blit_const_color_en = '0' then elsif blit_const_color_en = '0' then
sn <= blit_src_bus_request; sn <= blit_src_bus_request;
end if; end if;
@@ -559,21 +554,21 @@ vga_master:
sn <= rdy; sn <= rdy;
end if; end if;
when blit_dst_prime_pipe => -- when blit_dst_prime_pipe =>
bus_cycle_en <= '1'; -- bus_cycle_en <= '1';
CYC_O_blit_dst <= '1'; -- CYC_O_blit_dst <= '1';
STB_O_blit_dst <= blit_dst_vld; -- STB_O_blit_dst <= blit_dst_dout_vld;
blit_chunk_cnt_en <= blit_dst_vld; -- blit_chunk_cnt_en <= blit_dst_dout_vld;
if blit_dst_vld = '1' then -- if blit_dst_dout_vld = '1' then
sn <= blit_dst_bus_request; -- sn <= blit_dst_bus_request;
end if; -- end if;
when blit_dst_bus_request => when blit_dst_bus_request =>
bus_cycle_en <= '1'; bus_cycle_en <= '1';
CYC_O_blit_dst <= '1'; CYC_O_blit_dst <= '1';
STB_O_blit_dst <= blit_dst_vld; STB_O_blit_dst <= blit_dst_dout_vld;
blit_chunk_cnt_en <= blit_dst_vld; blit_chunk_cnt_en <= blit_dst_dout_vld;
if blit_chunk_cnt = 0 or blit_dst_vld = '0' then if blit_chunk_cnt = 0 or blit_dst_dout_vld = '0' then
sn <= bus_fin; sn <= bus_fin;
end if; end if;
@@ -696,7 +691,7 @@ proc_blit_src_counter:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if blit_reset = '1' then if blit_reset = '1' then
blit_src_row_cnt <= (others => '0'); blit_src_row_cnt <= to_unsigned(1, 32);
blit_src_unaligned <= '0'; blit_src_unaligned <= '0';
blit_src_first <= '0'; blit_src_first <= '0';
blit_src_last <= '0'; blit_src_last <= '0';
@@ -706,10 +701,11 @@ proc_blit_src_counter:
blit_src_first <= not blit_const_color_en; blit_src_first <= not blit_const_color_en;
blit_src_do_extra2 <= not blit_const_color_en; blit_src_do_extra2 <= not blit_const_color_en;
end if; end if;
blit_src_nx <= '0' & blit_nx(blit_nx'left downto 1);
elsif blit_src_re = '1' then elsif blit_src_re = '1' then
if blit_src_reg_vld = '1' then if blit_src_reg_vld = '1' then
blit_src_first <= '0'; blit_src_first <= '0';
if blit_src_row_cnt /= blit_nx then if blit_src_row_cnt /= blit_src_nx then
blit_src_row_cnt <= blit_src_row_cnt + 1; blit_src_row_cnt <= blit_src_row_cnt + 1;
elsif blit_src_do_extra2 = '1' then elsif blit_src_do_extra2 = '1' then
blit_src_do_extra2 <= '0'; blit_src_do_extra2 <= '0';
@@ -717,7 +713,7 @@ proc_blit_src_counter:
if blit_src_unaligned = '1' then if blit_src_unaligned = '1' then
blit_src_do_extra2 <= '1'; blit_src_do_extra2 <= '1';
end if; end if;
blit_src_row_cnt <= (others => '0'); blit_src_row_cnt <= to_unsigned(1, 32);
blit_src_first <= blit_src_unaligned; blit_src_first <= blit_src_unaligned;
end if; end if;
end if; end if;
@@ -748,7 +744,7 @@ inst_blitfifo_src: entity work.fifo_sync
blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish); blitfifo_src_we <= (blit_src_reg_vld and not blit_src_first) when blit_const_color_en = '0' else (blit_request and not blit_src_finish);
blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color); blitfifo_src_in <= blit_src_reg when blit_const_color_en = '0' else (blit_const_color & blit_const_color);
blitfifo_src_re <= blit_dst_re; blitfifo_src_re <= blit_dst_din_rdy;
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset; ADDR_O_blit_src <= blit_addr_src_0(31 downto 3) & "000" + blit_src_offset;
@@ -759,8 +755,8 @@ proc_blit_addr_src:
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if blit_reset = '1' then if blit_reset = '1' then
blit_src_cnt_x <= (others => '0'); blit_src_cnt_x <= to_unsigned(1, 32);
blit_src_cnt_y <= (others => '0'); blit_src_cnt_y <= to_unsigned(1, 32);
blit_src_offset <= (others => '0'); blit_src_offset <= (others => '0');
blit_src_off_y <= blit_dimx_src_0; blit_src_off_y <= blit_dimx_src_0;
blit_src_finish <= '0'; blit_src_finish <= '0';
@@ -770,7 +766,7 @@ proc_blit_addr_src:
end if; end if;
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
blit_src_offset <= blit_src_offset + 8; blit_src_offset <= blit_src_offset + 8;
if blit_src_cnt_x /= blit_nx then if blit_src_cnt_x /= blit_src_nx then
blit_src_cnt_x <= blit_src_cnt_x + 1; blit_src_cnt_x <= blit_src_cnt_x + 1;
elsif blit_src_do_extra = '1' then elsif blit_src_do_extra = '1' then
blit_src_do_extra <= '0'; blit_src_do_extra <= '0';
@@ -779,7 +775,7 @@ proc_blit_addr_src:
blit_src_do_extra <= '1'; blit_src_do_extra <= '1';
end if; end if;
if blit_src_cnt_y /= blit_ny then if blit_src_cnt_y /= blit_ny then
blit_src_cnt_x <= (others => '0'); blit_src_cnt_x <= to_unsigned(1, 32);
blit_src_offset <= blit_src_off_y; blit_src_offset <= blit_src_off_y;
blit_src_cnt_y <= blit_src_cnt_y + 1; blit_src_cnt_y <= blit_src_cnt_y + 1;
blit_src_off_y <= blit_src_off_y + blit_dimx_src_0; blit_src_off_y <= blit_src_off_y + blit_dimx_src_0;
@@ -792,78 +788,90 @@ proc_blit_addr_src:
end process; end process;
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
inst_align_dst : entity work.align inst_align_out : entity work.align_out
GENERIC MAP GENERIC MAP
( (
data_width => 64, data_width => 64,
aggregate_size => 8 addr_width => 32,
byte_size => 8
) )
PORT MAP PORT MAP
( (
rst => blit_reset, rst => blit_reset,
clk => CLK_I, clk => CLK_I,
eb => '1', cmd_rdy => blit_dst_cmd_rdy,
ce => blit_dst_re, cmd_vld => blit_dst_cmd_vld,
offset => blit_addr_dst(2 downto 0), cmd_in => blit_dst_cmd,
din_vld => blit_dst_we, din_rdy => blit_dst_din_rdy,
din => blitfifo_src_out, din_vld => blit_dst_din_vld,
dout_vld => blit_dst_reg_vld, din => blitfifo_src_out,
dout => blit_dst_reg, dout_vld => blit_dst_dout_vld,
byte_en => blit_dst_reg_be dout => blit_dst_dout,
dout_be => blit_dst_dout_be,
dout_re => blit_dst_dout_re,
addr_out => ADDR_O_blit_dst
); );
blit_dst_din_vld <= not blitfifo_src_empty;
blit_dst_dout_re <= CYC_O_blit_dst and busout_fifo_rdy;
blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else -- inst_align_dst : entity work.align
not blit_dst_reg_be when blit_dst_last = '1' else -- GENERIC MAP
(others => '1'); -- (
-- data_width => 64,
-- aggregate_size => 8
-- )
-- PORT MAP
-- (
-- rst => blit_reset,
-- clk => CLK_I,
-- eb => '1',
-- ce => blit_dst_re,
-- offset => blit_addr_dst(2 downto 0),
-- din_vld => blit_dst_we,
-- din => blitfifo_src_out,
-- dout_vld => blit_dst_reg_vld,
-- dout => blit_dst_reg,
-- byte_en => blit_dst_reg_be
--
-- );
-- blit_dst_be <= blit_dst_reg_be when blit_dst_first = '1' else
-- not blit_dst_reg_be when blit_dst_last = '1' else
-- (others => '1');
blit_dst_we <= not blitfifo_src_empty; -- blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last; -- blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last; -- blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
ADDR_O_blit_dst <= blit_addr_dst(31 downto 3) & "000" + blit_dst_offset;
proc_blit_addr_dst: proc_blit_addr_dst:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if blit_reset = '1' then if RST_I = '1' then
blit_dst_cnt_y <= (others => '0'); blit_dst_finish <= '1';
blit_dst_offset <= (others => '0'); blit_dst_cmd_vld <= '0';
blit_dst_off_y <= blit_dimx_dst; elsif blit_reset = '1' then
blit_dst_finish <= '0'; blit_dst_cmd.num_bytes <= blit_nx(blit_nx'left-2 downto 0) & "00";
blit_dst_cnt_x <= (others => '0'); blit_dst_cmd.num_bytes_per_word <= 4;
blit_dst_do_extra <= '0'; blit_dst_cmd.addr_start <= blit_addr_dst;
blit_dst_first <= '1'; blit_dst_cmd.eb <= '1';
blit_dst_last <= '0'; blit_dst_cnt_y <= to_unsigned(1, 32);
blit_dst_unaligned <= '0'; blit_dst_offset <= blit_addr_dst;
if blit_addr_dst (2 downto 0) /= "000" then blit_dst_cmd_vld <= '1';
blit_dst_unaligned <= '1'; blit_dst_finish <= '0';
blit_dst_do_extra <= '1'; elsif blit_dst_finish = '0' then
end if; if blit_dst_cnt_y /= blit_ny then
elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then if blit_dst_cmd_rdy = '1' then
blit_dst_first <= blit_dst_last; blit_dst_cmd.addr_start <= blit_dst_cmd.addr_start + blit_dimx_dst;
blit_dst_last <= '0'; blit_dst_cnt_y <= blit_dst_cnt_y + 1;
blit_dst_offset <= blit_dst_offset + 8; end if;
if blit_dst_cnt_x /= blit_nx then
blit_dst_cnt_x <= blit_dst_cnt_x + 1;
elsif blit_dst_do_extra = '1' then
blit_dst_do_extra <= '0';
blit_dst_last <= '1';
else else
if blit_dst_unaligned = '1' then blit_dst_cmd_vld <= '0';
blit_dst_do_extra <= '1'; blit_dst_finish <= '1';
end if;
if blit_dst_cnt_y /= blit_ny then
blit_dst_cnt_x <= (others => '0');
blit_dst_offset <= blit_dst_off_y;
blit_dst_cnt_y <= blit_dst_cnt_y + 1;
blit_dst_off_y <= blit_dst_off_y + blit_dimx_dst;
else
blit_dst_finish <= '1';
end if;
end if; end if;
end if; end if;
end if; end if;
@@ -998,7 +1006,7 @@ registers_read:
-- sys_blit_nx -- sys_blit_nx
-- 0x60 -- 0x60
when "11000" => when "11000" =>
SDAT_O <= host_blit_nx; SDAT_O <= blit_nx;
-- sys_blit_ny -- sys_blit_ny
-- 0x64 -- 0x64
@@ -1124,8 +1132,7 @@ registers_write:
-- sys_blit_nx -- sys_blit_nx
-- 0x60 -- 0x60
when "11000" => when "11000" =>
host_blit_nx <= SDAT_I; blit_nx <= SDAT_I;
blit_nx <= '0' & SDAT_I(31 downto 1);
-- sys_blit_ny -- sys_blit_ny
-- 0x64 -- 0x64