|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES
deleted file mode 100644
index b755a56..0000000
--- a/lib/PCK_FIO-2002.7/CHANGES
+++ /dev/null
@@ -1,86 +0,0 @@
----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-Changes from version 1.16 to version 2002.07
-============================================
-
-PCK_FIO is now distributed under the GNU Lesser General Public Licencse
-instead of the ordinary GPL, to better reflect intended usage.
-
-Cosmetic changes in source code to correct some typos in the testbench output.
-A new testbench is also supplied.
-
-The package now uses IEEE.numeric_std as default.
-
-URL http://www.easics.com has been made part of address.
-
-Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993.
-Because of backwards-incompatibility, it has been necessary to supply
-different sets of files for 1987 and 1993.
-
-Split the packages into a separate file for the header and a
-separate file for the body (in compliance with Easics' guidelines).
-
-These changes resulted in the files:
-
-Files for VHDL-1993:
---------------------
- PCK_FIO_1993.vhd : the source code of the header file for the package
- PCK_FIO_1993_BODY.vhd: the source code of the body of the package
- TB_PCK_FIO_1993.vhd: the testbench for the package
-
-Files for VHDL-1987:
---------------------
- PCK_FIO_1987.vhd: the source code of the header file for the package
- PCK_FIO_1987_BODY.vhd: the source code of the body of the package
- TB_PCK_FIO_1987.vhd: the testbench for the package
-
-Updated README and PCK_FIO.html to support these changes.
-
-Adapted package files to support NUL termination of strings.
-fo(Arg: string) now prints the string until the first NUL.
-Several examples of its use are demonstrated in the supplied testbenches.
-
-Made cosmetic changes to code to improve readability.
-
-Acknowledgment
---------------
-These changes have been implemented by Peter Geens.
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html
deleted file mode 100644
index 6b5fc72..0000000
--- a/lib/PCK_FIO-2002.7/PCK_FIO.html
+++ /dev/null
@@ -1,339 +0,0 @@
-
-
-
- VHDL package for formatted file output
-
-
-
-
-
-
-PCK_FIO - VHDL package for formatted file output
-
-
-Contents
-Usage
-The file output function 'fo'
-Format specifiers
-Special characters
-Things to watch out for
-Methodology notes
-Parametrization
-Test bench
-Known limitations and problems
-Author
-
-
-
-PCK_FIO is a VHDL package that defines fprint, a function
-for formatted file output.
-After installing the package you can call fprint as follows:
-
fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable.
-The argument Format is the format string, which consists of ``normal''
-substrings which are copied verbatim, and format specifiers, starting with
-'%' .
-A typical format string looks as follows:
-
"Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write
-to the file, embedded in fo function calls. There can be 0 to
-32 of such arguments. The expressions can be of any type for which an fo
-function exists. String expressions can also be called directly.
-
-
-'fo'
-The fo (f ile o utput) functions do the trick. They
-return a tagged string representation that is meaningful to format specifiers.
-Here are some examples:
- fo (signed'("1100")) returns "S:1100"
- fo (unsigned'("1100")) returns "U:1100"
- fo (TRUE) returns "L:T"
- fo (127) returns "I:127"
-The internal behavior of fo is irrelevant to the typical user.
-The fo function is currently overloaded as follows:
-
- function fo (Arg: unsigned) return string;
- function fo (Arg: signed) return string;
- function fo (Arg: std_logic_vector) return string;
- function fo (Arg: std_ulogic_vector) return string;
- function fo (Arg: bit_vector) return string;
- function fo (Arg: integer) return string;
- function fo (Arg: std_ulogic) return string;
- function fo (Arg: bit) return string;
- function fo (Arg: boolean) return string;
- function fo (Arg: character) return string;
- function fo (Arg: string) return string;
- function fo (Arg: time) return string;
-
-fo (Arg:
-string) processes Arg up to the first NUL character,
-if any. If you want the whole string to be outputted you can just enter
-the string as a direct argument in fprint . See also the
-examples in the testbench.
-
-
-
-
-
-The general format of a format specifier is:
- %[-][n]c
-The optional - sign specifies left justified output; default is
-right justified.
-The optional number n specifies a field-width. If it is not specified,
-fprint
-does something reasonable.
-
c is the conversion specifier. Currently the following conversion
-specifiers are supported:
-
-
-r
-
-
-reasonable output format (inspired by Synopsys VSS)
-
-Prints the ``most reasonable'' representation e.g. hex for
-unsigned, signed and other bit-like vectors (not preferred for integers)
-
-
-b
-
-
-bit-oriented output
-
-
-d
-
-
-decimal output
-
-
-s
-
-
-string output (e.g. in combination with 'IMAGE for enum types)
-
-
-q
-
-
-``qualified'' string output (shows internal representation from fo )
-
-
-{}
-
-
-Iteration operator, used as follows:
-
-
-%n{<format-string>}
-
-n is the iteration count and is mandatory. Iteration
-can be nested.
-
-
-
-To print a double quote, use '""' in the format string (VHDL
-convention). To print the special characters, '\' , and '%' ,
-escape them with '\' . To prevent '{' and '}'
-from being interpreted as opening and closing brackets in iteration strings,
-escape them with '\' .
-A newline is specified in the format string by '\n' .
-
-
-
-The fprint function expands into VHDL write and writeline
-commands. As in plain VHDL, nothing will be written to the output file
-until a writeline is given. Therefore, don't forget to include
-'\n'
-commands in the format string, or it ``will not work''.
-The preferred format specifier for integers is, naturally, %d .
-This calls the VHDL write for integers. If you specify a field
-width that is too small, the field will automatically be expanded. If you
-use %r for integers, the field is not expanded automatically, which
-means that some digits are simply thrown away. This may sometimes be useful
-but it is also dangerous. Look at the test bench output for differences
-between %d and %r output.
-
When using the %d format specifier, the VHDL constraints for
-the allowed integer range apply.
-
In VHDL, signed/unsigned types have been standardized only relatively
-recently, in the package IEEE.numeric_std . The lack of a standard
-has caused (and is causing) portability issues. The most popular non-standard
-package that defines signed/unsigned is IEEE.std_logic_arith from
-Synopsys. PCK_FIO works with both packages, but refers to the standard
-package IEEE.numeric_std by default. To use IEEE.std_logic_arith
-instead, replace the reference to IEEE.numeric_std in the source
-code. This needs to be done consistently in a design database (e.g.
-in the PCK_FIO test bench as well).
-
-
-
-The obvious application for fprint is in test benches, to produce
-output files that trace the simulation behavior.
-Another interesting application for fprint is to produce info,
-warning and error messages in your models. As it can take arguments, fprint
-is much better suited for this task than VHDL's assert or report
-statements. Actually fprint produces its own (few) warning messages.
-
An advanced usage is the generation of test vectors in a specific format.
-Instead of using the fo functions, you can write your own set
-of functions that return the symbols of a specific test format in a way
-that is understandable to the fprint format specifiers. As an
-example, when a high output value should be represented using the symbol
-'H' it suffices to write a conversion function that returns "B:H" and call
-it in combination with the %b format specifier.
-
-
-
-Prefix and postfix strings for bit-oriented and hex-oriented output are
-parameterizable in the packages to accommodate different output styles.
-The settings in the distribution are such that hex output is indicated
-by the prefix '0x', while bit output prefix and postfix are empty
-strings.
-You can adapt the output style by modifying the following constants
-in the package header:
-
-- prefix string for hex output
- -- VHDL style: "X"""
- -- Verilog style: "h'"
- -- C style: "0x"
- constant FIO_h_PRE: string := "0x";
-
-- postfix string for hex output
- -- VHDL style: """"
- constant FIO_h_POST: string := "";
-
-- prefix string for bit vector output
- -- VHDL style: "B"""
- -- Verilog style: "b'"
- constant FIO_bv_PRE: string := "";
-
-- postfix string for bit vector output
- -- VHDL style: """"
- constant FIO_bv_POST: string := "";
-
-- prefix string for bit output
- -- VHDL style: "'"
- -- Verilog style: "b'"
- constant FIO_b_PRE: string := "";
-
-- postfix string for bit output
- -- VHDL style: "'"
- constant FIO_b_POST: string := "";
-
-
-
-Included in the distribution are the files TB_PCK_FIO_1987.vhd and
-TB_PCK_FIO_1993 with a test bench,depending on the standard you're
-running, for the PCK_FIO package. The file PCK_FIO.out.gold contains
-the expected output. If you run the test bench it should produce the file
-PCK_FIO.out
-that should be identical to PCK_FIO.out.gold . The source files
-should be analyzed in a VHDL library EASICS_PACKAGES .
-A good way to understand fprint is to inspect the test bench
-and what it produces.
-
-
-
-This VHDL package is an implementation of a flexible concept. It is likely
-to be extended and modified in the future. Backward compatibility is not
-guaranteed. Therefore, it is not recommended to give this package the status
-of a company wide standard package (or even worse, a VHDL standard package).
-Rather, it should be linked with a particular project (and it can be regarded
-as a standard package within that project).
-PCK_FIO is available in either standard VHDL Std1076-1987 or standard
-VHDL Std1076-1993. Nevertheless, some simulators/versions have problems
-with the package. The following is an overview of currently known issues:
-
-PCK_FIO_1987 and various simulators/versions
-
-
-Simulator
-
-PCK_FIO_1987
-
-
-
-Synopsys VSS 3.5 and earlier
-
-Incorrect (all zero) output in compiled mode
-
-
-
-Synopsys VSS 97.01
-
-OK
-
-
-
-Synopsys VSS/Scirocco 2000.02
-
-Incorrect output in compiled mode, interpreted mode works
-
-
-
-Mentor quickhdl
-
-OK
-
-
-
-Modeltech modelsim
-
-OK
-
-
-
-Cadence Leapfrog
-
-Should work with 4.4.1
-
-
-
-PCK_FIO_1993 and various simulators/versions
-
-
-Simulator
-
-PCK_FIO_1993
-
-
-
-Synopsys VSS/Scirocco 2000.02
-
-Compile errors due to improper handling of files by Synopsys
-
-
-
-Synopsys VSS/Scirocco 2000.06
-
-works fine
-
-
-
-Modeltech modelsim 5.4c and higher
-
-OK
-
-
Although the package name suggests file IO, it only does file output.
-
-
-
-Jan Decaluwe
-
-
stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-
-fprint(RESULT, L,
- "\n-------------------------------\n" &
- "-- Support for integer types --\n" &
- "-------------------------------\n"
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
-
-
diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
deleted file mode 100644
index 0386a11..0000000
--- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd
+++ /dev/null
@@ -1,536 +0,0 @@
----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----
----- PCK_FIO: a VHDL package for C-style formatted file output
----- Copyright (C) 1995, 2001 Easics NV
-----
----- This library is free software; you can redistribute it and/or
----- modify it under the terms of the GNU Lesser General Public
----- License as published by the Free Software Foundation; either
----- version 2.1 of the License, or (at your option) any later version.
-----
----- This library is distributed in the hope that it will be useful,
----- but WITHOUT ANY WARRANTY; without even the implied warranty of
----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
----- Lesser General Public License for more details.
-----
----- You should have received a copy of the GNU Lesser General Public
----- License along with this library; if not, write to the Free Software
----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----
----- For suggestions, bug reports, enhancement requests, and info about
----- our design services, you can contact us at the following address:
----- http://www.easics.com
----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium
----- tel.: +32 16 395 600 fax : +32 16 395 619
----- e-mail: jand@easics.be (Jan Decaluwe)
-----
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- signed/unsigned definition: use either std_logic_arith or numeric_std
--- use IEEE.std_logic_arith.all; -- the Synopsys one
-use IEEE.numeric_std.all;
-
-use STD.TEXTIO.all;
-
-library EASICS_PACKAGES;
-use EASICS_PACKAGES.PCK_FIO.all;
-
-entity TBE_PCK_FIO is
-
-end TBE_PCK_FIO;
-
-architecture TB of TBE_PCK_FIO is
-
-begin
-
-USAGE: process
-
- file RESULT: text open write_mode is "PCK_FIO.out";
- variable L: line;
- variable Pointer: integer;
- variable BoolTrue: boolean := TRUE;
- variable BoolFalse: boolean := FALSE;
- variable IntPos: integer := 5678;
- variable BigIntPos: integer := 12345678;
- variable IntNeg: integer := -8765;
- variable BigIntNeg: integer := -87654321;
- variable Uns: unsigned(6 downto 0) := unsigned'("1010010");
- variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10");
- variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010");
- variable SigPos: signed(6 downto 0) := signed'("0010010");
- variable SigNeg: signed(6 downto 0) := signed'("1010010");
- variable BitX: std_logic := 'X';
- variable Bit1: std_logic := '1';
- variable Bit0: std_logic := '0';
-
- variable parameter_1: integer := 1234;
- variable parameter_2: integer := 2345;
- variable parameter_3: integer := 4567;
-
- constant TempString: string :="ABC" & NUL & "DEF";
-begin
-
-fprint(RESULT, L,
- "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" &
- "-----------------------------------------\n\n" &
- "This is the result of running the PCK_FIO testbench.\n" &
- "This file should be compared with PCK_FIO.out.gold, which is\n" &
- "the reference output. Any difference indicates a portability\n" &
- "issue or a simulator non-compliance or bug.\n\n"
- );
-
-
-fprint(RESULT, L,
- "\n--------------------\n" &
- "-- Basic features --\n" &
- "--------------------\n\n"
- );
-
-fprint(RESULT, L,
- "-- First some auxiliary declarations\n"
- );
-
-fprint(RESULT, L,
- "> file RESULT: text is out ""PCK_FIO.out"";\n" &
- "> variable L: line;\n" &
- "> variable BoolTrue: boolean := TRUE;\n" &
- "> variable BoolFalse: boolean := FALSE;\n" &
- "> variable IntPos: integer := 5678;\n" &
- "> variable BigIntPos: integer := 12345678;\n" &
- "> variable IntNeg: integer := -8765;\n" &
- "> variable BigIntNeg: integer := -87654321;\n" &
- "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" &
- "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" &
- "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" &
- "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" &
- "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" &
- "> variable BitX: std_logic := 'X';\n" &
- "> variable Bit1: std_logic := '1';\n" &
- "> variable Bit0: std_logic := '0';\n" &
- "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n"
-);
-
-
-fprint(RESULT, L,
- "\n\n-- fprint call with no arguments\n" &
- "> fprint(RESULT, L, ""No arguments.\\n"");\n"
- );
-fprint(RESULT, L, "No arguments.\n");
-
-
-fprint(RESULT, L,
- "\n-- Special characters need to be escaped\n" &
- "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n"
- );
-
-fprint(RESULT, L, "Special characters: \% \\ "" \n");
-
-
-fprint(RESULT, L,
- "\n-- Various format specifiers interprete the same object differently\n" &
- "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" &
- "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Format specifiers: %r %d %b %q\n",
- fo(Uns), fo(Uns), fo(Uns), fo(Uns)
- );
-
-fprint(RESULT, L,
- "\n-- Format string can be shortened by using the iteration specifier\n" &
- "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" &
- "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L, "Iteration specifier: %4{%r }\n",
- fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)
- );
-fprint(RESULT, L,
- "\n-------------------------------\n"&
- "--Testing string manipulation--\n"&
- "-------------------------------\n");
-fprint(RESULT, L, "--testing done using the string TempString : " & """ABC"""
- & " & NUL & ""DEF""\n");
--- TempString: string:="ABC" & NUL & "DEF"
--- test for detecting NUL in string
-fprint(RESULT, L ,"\n--test for NUL ending in strings\n");
-fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n");
-fprint(RESULT, L, fo(TempString));
-
--- direct inclusion of string in fprint should give whole string
-fprint(RESULT, L, "\n--same without fo,so without NUL testing\n");
-fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n");
-fprint(RESULT, L, TempString & "\n");
-
--- influence of given width
-
-fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"&
- "-- pad the remaining with blanco's according to the given justification\n");
-fprint(RESULT, L, "\n--with specified width, justified right,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n");
-fprint(RESULT, L, "%5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width, justified left, using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n");
-fprint(RESULT, L, "%-5s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n");
-fprint(RESULT, L, "%9s", TempString);
-fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"&
- "-- will output the string with the minimum of characters needed\n");
-fprint(RESULT, L, "\n--with specified width,using fo\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n");
-fprint(RESULT, L, "%2s", fo(TempString));
-fprint(RESULT, L, "\n--with specified width without fo\n");
-fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n");
-fprint(RESULT, L, "%4s", TempString);
-
-fprint(RESULT, L,
- "\n\n------------------------------------\n" &
- "-- Support for bit-oriented types --\n" &
- "------------------------------------\n"
- );
-
-fprint (RESULT, L, "\n-- Reasonable format\n" &
- "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Reasonable format: %9{%r }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Decimal format\n" &
- "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Decimal format: %9{%d }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint (RESULT, L, "\n-- Bit format\n" &
- "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" &
- "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" &
- "> );\n"
- );
-
-
-fprint(RESULT, L, "Bit format: %9{%b }\n",
- fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),
- fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse)
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" &
- "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" &
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n",
- fo(Uns), fo(Std), fo(SigPos), fo(SigNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-
-fprint(RESULT, L,
- "\n-------------------------------\n" &
- "-- Support for integer types --\n" &
- "-------------------------------\n"
- );
-
-fprint(RESULT, L,
- "\n\n" &
- "-- Template of the call: ( stands for the format specifier)\n"
- );
-
-
-fprint(RESULT, L, "\n" &
- "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" &
- "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" &
-
- "> );\n"
- );
-
-fprint(RESULT, L,
- "\n" &
- "-- Results of the call with various format specifiers\n\n"
- );
-
-
-fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n",
- fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)
- );
-fprint(RESULT, L, "\n");
-
-
-fprint(RESULT, L,
- "\n----------------------\n" &
- "-- Support for time --\n" &
- "----------------------\n"
- );
-
-fprint (RESULT, L, "-- For portability reasons, time is converted \n" &
- "-- into an integer value (of nanoseconds)\n"
- );
-fprint (RESULT, L, "> wait for 648 ns\n");
-fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n");
-
-wait for 648 ns;
-
-fprint (RESULT, L, "The time is now %d ns\n", fo(now));
-
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Erroneous calls and error messages --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" &
- "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L, "-- Unsupported format specifier\n" &
- "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " &
- "fo(Uns), fo(Std), fo(Uns), fo(Std));\n"
- );
-
-fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std));
-
-fprint(RESULT, L, "\n");
-
-fprint(RESULT, L,
- "\n----------------------------------------\n" &
- "-- Things you wouldn't expect to work --\n" &
- "----------------------------------------\n"
- );
-
-fprint(RESULT, L, "\n-- Nested iteration\n");
-fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n");
-fprint(RESULT, L, "%3{<<%3{_END_}>>}\n");
-
-wait;
-
-end process USAGE;
-
-end TB;
-
-
-
-
-
-
-
-
-
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
deleted file mode 100644
index c5a4a92..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001
-
-ANALYZER = vcom -quiet -nologo
-ANALYZER_C = vcom -quiet -nologo
-all : \
- bin/tbe_pck_fio/tb.dat \
- bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
- bin/pck_fio/body.dat \
- bin/pck_fio/_primary.dat \
- TB_PCK_FIO_1987.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
-
-bin/pck_fio/body.dat : \
- bin/pck_fio/_primary.dat \
- PCK_FIO_1987_BODY.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
-
-bin/pck_fio/_primary.dat : \
- PCK_FIO_1987.vhd
- ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd
-
-
diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
deleted file mode 100644
index 0f9a351..0000000
--- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993
+++ /dev/null
@@ -1,34 +0,0 @@
-### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001
-
-ANALYZER = vcom -quiet -nologo -93
-ANALYZER_C = vcom -quiet -nologo -93
-all : \
- bin/tbe_pck_fio/tb.dat \
- bin/tbe_pck_fio/_primary.dat
-
-# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB)
-# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO
-
-bin/tbe_pck_fio/tb.dat \
-bin/tbe_pck_fio/_primary.dat : \
- bin/pck_fio/body.dat \
- bin/pck_fio/_primary.dat \
- TB_PCK_FIO_1993.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd
-
-
-# Prerequisites for package body EASICS_PACKAGES.PCK_FIO()
-
-bin/pck_fio/body.dat : \
- bin/pck_fio/_primary.dat \
- PCK_FIO_1993_BODY.vhd
- ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd
-
-
-# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO
-
-bin/pck_fio/_primary.dat : \
- PCK_FIO_1993.vhd
- ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd
-
-
diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
deleted file mode 100644
index ba54b14..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj
+++ /dev/null
@@ -1,13 +0,0 @@
-vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd"
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
deleted file mode 100644
index 7af84ba..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl.wdo}
-view wave
-view structure
-view signals
-run 800us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
deleted file mode 100644
index 4a9d3f1..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo
+++ /dev/null
@@ -1,93 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {14963876 ps} 0}
-configure wave -namecolwidth 184
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {14733925 ps} {15711632 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
deleted file mode 100644
index 4f1cf1c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl_fifo
-do {tb_sdr_ctrl_fifo.wdo}
-view wave
-view structure
-view signals
-run 20us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
deleted file mode 100644
index 4088038..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo
+++ /dev/null
@@ -1,68 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy
-add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd
-add wave -noupdate -divider {Read FIFO}
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty
-add wave -noupdate -divider {Write FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw
-add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next
-add wave -noupdate -divider {Command FIFO}
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty
-add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {13893123 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {13879998 ps} {13928553 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
deleted file mode 100644
index eee9b52..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_r_rand_w.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
deleted file mode 100644
index 4716a01..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_lin_w_rand_r.wdo}
-view wave
-view structure
-view signals
-run 1200us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
deleted file mode 100644
index 542c24b..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo
+++ /dev/null
@@ -1,87 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {21813900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {21725359 ps} {22204052 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
deleted file mode 100644
index 9be2261..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 1000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
deleted file mode 100644
index eb20b08..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo
+++ /dev/null
@@ -1,82 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {60573747 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {60552548 ps} {60600861 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
deleted file mode 100644
index c868866..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo
+++ /dev/null
@@ -1,27 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdr_ctrl
-do {tb_sdr_ctrl_rand_rw.wdo}
-view wave
-view structure
-view signals
-run 10000us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
deleted file mode 100644
index e3087e6..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo
+++ /dev/null
@@ -1,84 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst
-add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb
-add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency
-add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p
-add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr
-add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -divider {Main controller}
-add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en
-add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase
-add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk
-add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd
-add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr
-add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0
-add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {16004147 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {15914249 ps} {16324366 ps}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
deleted file mode 100644
index dbf023a..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo
+++ /dev/null
@@ -1,28 +0,0 @@
-## NOTE: Do not edit this file.
-##
-
-vlib work
-vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit -93 "../../../misc/dpram_1w2r.vhd"
-vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd"
-vcom -explicit -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit -93 "../src/fifo_sync.vhd"
-vcom -explicit -93 "../src/sdram_config.vhd"
-vcom -explicit -93 "../src/sdram_types.vhd"
-vcom -explicit -93 "../src/reset_virtex4.vhd"
-vcom -explicit -93 "../src/clockgen_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_cmd.vhd"
-vcom -explicit -93 "../src/sdram_ctrl.vhd"
-vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd"
-vcom -explicit -93 "../src/mt46v16m16.vhd"
-vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd"
-
-#restart -force
-vsim -t 1ps -lib work tb_sdram_ctrl_frontend
-do {tb_sdram_ctrl_frontend.wdo}
-view wave
-view structure
-view signals
-run 40us
diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
deleted file mode 100644
index 565f89c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo
+++ /dev/null
@@ -1,45 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 4} {27951315 ps} 0}
-configure wave -namecolwidth 172
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {42 us}
diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
deleted file mode 100644
index c924c8c..0000000
--- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd
+++ /dev/null
@@ -1,240 +0,0 @@
--------------------------------------------------------------------------
--- Project: SDRAM controller
--- This file: Clock generator (Virtex-4 specific)
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/count0
-add wave -noupdate -format Logic /tb_fir_semi_parallel/din_vld
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/start
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/count_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/en_array
-add wave -noupdate -format Literal -expand /tb_fir_semi_parallel/uut/ce_array
-add wave -noupdate -format Literal /tb_fir_semi_parallel/uut/h_addr
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/h_we
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/x
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/accu_load
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu
-add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y
-add wave -noupdate -divider {stage 1}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram
-add wave -noupdate -divider {stage 2}
-add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out
-add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 1
-update
-WaveRestoreZoom {0 ps} {52500 ns}
diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo
deleted file mode 100644
index e9fefb8..0000000
--- a/lib/filter/sim/tb_fir_stage.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage.vhd"
-vcom -explicit -93 "../src/tb_fir_stage.vhd"
-vsim -t 1ps -lib work tb_fir_stage
-do {tb_fir_stage.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo
deleted file mode 100644
index 916de83..0000000
--- a/lib/filter/sim/tb_fir_stage.wdo
+++ /dev/null
@@ -1,31 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage/clk
-add wave -noupdate -format Logic /tb_fir_stage/srst
-add wave -noupdate -divider Input
-add wave -noupdate -format Logic /tb_fir_stage/in_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in
-add wave -noupdate -format Literal /tb_fir_stage/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Logic /tb_fir_stage/out_valid
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out
-add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1655000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {2100 ns}
diff --git a/lib/filter/sim/tb_fir_stage_sys.fdo b/lib/filter/sim/tb_fir_stage_sys.fdo
deleted file mode 100644
index b2417c3..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.fdo
+++ /dev/null
@@ -1,17 +0,0 @@
-vmap ieee_proposed ../../../Common/sim/ieee_proposed
-
-vlib work
-vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
-vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
-vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
-vcom -explicit -93 "../src/filter_pkg.vhd"
-vcom -explicit -93 "../src/fir_pkg.vhd"
-vcom -explicit -93 "../src/fir_stage_sys.vhd"
-vcom -explicit -93 "../src/tb_fir_stage_sys.vhd"
-vsim -t 1ps -lib work tb_fir_stage_sys
-do {tb_fir_stage_sys.wdo}
-view wave
-view structure
-view signals
-run 2us
diff --git a/lib/filter/sim/tb_fir_stage_sys.wdo b/lib/filter/sim/tb_fir_stage_sys.wdo
deleted file mode 100644
index 21e822e..0000000
--- a/lib/filter/sim/tb_fir_stage_sys.wdo
+++ /dev/null
@@ -1,28 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_fir_stage_sys/clk
-add wave -noupdate -divider Input
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x_in
-add wave -noupdate -format Literal /tb_fir_stage_sys/xi
-add wave -noupdate -divider Output
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y_out
-add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_fir_stage_sys/yo
-add wave -noupdate -divider {Stage signals}
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/x
-add wave -noupdate -format Literal -radix decimal /tb_fir_stage_sys/y
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1060000 ps} 0}
-configure wave -namecolwidth 140
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {706931 ps} {1268317 ps}
diff --git a/lib/filter/src/delay_line.vhd b/lib/filter/src/delay_line.vhd
deleted file mode 100644
index a05e317..0000000
--- a/lib/filter/src/delay_line.vhd
+++ /dev/null
@@ -1,129 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-
-entity delay_line is
-Generic
-(
- nbits : integer := 12;
- nbits_frac : integer := 11;
- ntaps : integer := 4;
- delay_fix : integer := 1
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- shift_en : in std_logic;
- delay : in natural range 0 to ntaps-1;
- din : in sfixed;
- dout : out sfixed
-);
-end delay_line;
-
-architecture ram_based of delay_line is
-
- -------------------------------------------------------------------------------
- signal count : natural range 0 to ntaps-1;
- signal addr_w : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
- signal addr_r : unsigned(NextExpBaseTwo(ntaps)-1 downto 0);
- signal ram_w : unsigned(nbits-1 downto 0);
- signal ram_r : unsigned(nbits-1 downto 0);
-
- -------------------------------------------------------------------------------
-begin
-
- addr_w <= to_unsigned(count, addr_w'length);
- addr_r <= addr_w + not to_unsigned(delay, addr_w'length);
-
- ram_w <= unsigned(din);
- dout <= sfixed(ram_r);
-
-counter:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- count <= 0;
- elsif shift_en = '1' then
- if count /= ntaps-1 then
- count <= count + 1;
- else
- count <= 0;
- end if;
- end if;
- end if;
- end process;
-
- inst_dpram_1w1r: entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(ntaps),
- data_width => nbits
- )
- PORT MAP (
- clka => clk,
- clkb => clk,
- en_a => '1',
- en_b => '1',
- we_a => shift_en,
- addr_a => addr_w,
- addr_b => addr_r,
- din_a => ram_w,
- dout_b => ram_r
- );
-
-end ram_based;
-
-architecture reg_based of delay_line is
-
- -------------------------------------------------------------------------------
- subtype word_t is sfixed(shi(nbits, nbits_frac) downto slo(nbits, nbits_frac));
- type delay_pipe_t is array (ntaps-1 downto 0) of word_t;
- type delay_fix_pipe_t is array (delay_fix downto 0) of word_t;
-
- -------------------------------------------------------------------------------
-begin
-
-shift_register:
- process(clk)
- variable delay_pipe : delay_pipe_t;
- begin
- if rising_edge(clk) then
- dout <= delay_pipe(delay);
- if shift_en = '1' then
- delay_pipe := delay_pipe(delay_pipe'left-1 downto 0) & din;
- end if;
- end if;
- end process;
-
-end reg_based;
-
diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd
deleted file mode 100644
index 1359d25..0000000
--- a/lib/filter/src/filter_pkg.vhd
+++ /dev/null
@@ -1,219 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use IEEE.MATH_REAL.ALL;
-
-library work;
-use work.fixed_util_pkg.all;
-
--------------------------------------------------------------------------------
-package filter_pkg is
-
- function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t;
- function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t;
- function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t;
- function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t;
- function Window_Hamming (x : real_array_t) return real_array_t;
- function Window_VonHann (x : real_array_t) return real_array_t;
- function Window_Blackman (x : real_array_t) return real_array_t;
- function Sinc (x : real) return real;
- function FilterEnergy (x : real_array_t) return real;
- function FilterMean (x : real_array_t) return real;
- function FilterScale (x : real_array_t; scale : real) return real_array_t;
- function FilterTestCoef (N : positive) return real_array_t;
-
-end; -- package filter_pkg;
-
--------------------------------------------------------------------------------
-package body filter_pkg is
-
- function Prototype_Lowpass (N : positive; omega : real) return real_array_t is
- variable res : real_array_t(0 to N-1);
- variable M : positive;
- variable phi : real := 0.0;
- variable dphi : real := pi*omega;
- begin
- if (N mod 2) = 0 then
- M := N/2;
- for i in 0 to M-1 loop
- phi := phi + dphi;
- res(M+i) := Sinc(phi);
- res(M-i-1) := res(M+i);
- end loop;
- else
- M := (N-1)/2;
- for i in 1 to M loop
- phi := phi + dphi;
- res(M+i) := Sinc(phi);
- res(M-i) := res(M+i);
- end loop;
- res(M) := Sinc(0.0);
- end if;
- return res;
-
- end Prototype_Lowpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Lowpass (N : positive; omega, gain : real) return real_array_t is
- variable lp : real_array_t(0 to N-1);
- begin
- lp := Prototype_Lowpass(N, omega);
-
- return Window_VonHann(FilterScale(lp, gain/FilterEnergy(lp)));
-
- end FilterCoef_Lowpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Highpass (N : positive; omega, gain : real) return real_array_t is
- variable lp, res : real_array_t(0 to N-1);
- variable phi : real := 0.0;
- variable dphi : real := pi;
- begin
- lp := Prototype_Lowpass(N, 0.5-omega);
-
- for i in 0 to N-1 loop
- res(i) := lp(i) * cos(phi);
- phi := phi + dphi;
- end loop;
-
- return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-
- end FilterCoef_Highpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Bandpass (N : positive; bw2, omega_m, gain : real) return real_array_t is
- variable lp, res, mean, sum : real_array_t(0 to N-1);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi*omega_m;
- begin
- lp := Prototype_Lowpass(N, bw2/2.0);
-
- for i in 0 to N-1 loop
- res(i) := lp(i) * cos(phi);
- phi := phi + dphi;
- end loop;
-
- return Window_VonHann(FilterScale(res, gain/FilterEnergy(lp)));
-
- end FilterCoef_Bandpass;
-
- -------------------------------------------------------------------------------
- function FilterCoef_Delta (N:positive; delay:natural; gain:real) return real_array_t is
- variable res : real_array_t(0 to N-1);
- begin
- for i in 0 to N-1 loop
- res(i) := 0.0;
- end loop;
- res(delay) := gain;
-
- return res;
-
- end FilterCoef_Delta;
-
- -------------------------------------------------------------------------------
- function FilterTestCoef (N : positive) return real_array_t is
- variable phi : real := 0.0;
- variable dphi : real := 1.0/real(N);
- variable res : real_array_t(0 to N-1);
- begin
- for i in 0 to N-1 loop
- res(i) := phi;
- phi := phi + dphi;
- end loop;
- return res;
-
- end FilterTestCoef;
-
- -------------------------------------------------------------------------------
- function Window_Hamming (x : real_array_t) return real_array_t is
- variable res : real_array_t(x'range);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := x(i) * (0.54 - 0.46*(cos(phi)));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_Hamming;
-
- -------------------------------------------------------------------------------
- function Window_VonHann (x : real_array_t) return real_array_t is
- variable res : real_array_t(x'range);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := 0.5 * x(i) * (1.0 - (cos(phi)));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_VonHann;
-
- -------------------------------------------------------------------------------
- function Window_Blackman (x : real_array_t) return real_array_t is
- variable res : real_array_t(0 to x'length-1);
- variable phi : real := 0.0;
- variable dphi : real := 2.0*pi/real(x'length-1);
- begin
- for i in x'range loop
- res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi));
- phi := phi + dphi;
- end loop;
- return res;
-
- end Window_Blackman;
-
- -------------------------------------------------------------------------------
- function Sinc (x : real) return real is
- variable res : real := 1.0;
- begin
- if x /= 0.0 then
- res := sin(x)/x;
- end if;
-
- return res;
-
- end Sinc;
-
- -------------------------------------------------------------------------------
- function FilterScale (x : real_array_t; scale : real) return real_array_t is
- variable res : real_array_t(x'range);
- begin
- for i in x'range loop
- res(i) := scale * x(i);
- end loop;
-
- return res;
-
- end FilterScale;
-
- -------------------------------------------------------------------------------
- function FilterEnergy (x : real_array_t) return real is
- variable res : real := 0.0;
- begin
- for i in x'range loop
- res := res + x(i)*x(i);
- end loop;
-
- return res;
-
- end FilterEnergy;
-
- -------------------------------------------------------------------------------
- function FilterMean (x : real_array_t) return real is
- variable res : real := 0.0;
- begin
- for i in x'range loop
- res := res + x(i);
- end loop;
-
- return res/real(x'length);
-
- end FilterMean;
-
--------------------------------------------------------------------------------
-end; -- package filter_pkg;
diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd
deleted file mode 100644
index bc1dba5..0000000
--- a/lib/filter/src/fir_iterative.vhd
+++ /dev/null
@@ -1,323 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_iterative is
-Generic
-(
- ntaps : integer := 33;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11;
- fir_mode : fir_iterative_mode_t := normal;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- h_din : in sfixed;
- h_addr_out : out natural;
- ready : out std_logic;
- x_valid : in std_logic;
- x_din : in sfixed;
- y_dout_valid : out std_logic;
- y_dout : out sfixed
-);
-end fir_iterative;
-
-architecture Behavioral of fir_iterative is
-
--------------------------------------------------------------------------------
- constant fir_stage_mode : fir_stage_mode_t := transposed;
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode);
-
- subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- type state_t is (init, idle, start, proc, p1, p2, output);
- signal s, sn : state_t;
- signal x_stage, xo, y_stage : stage_t;
- signal stage_en, cnt_en, new_round : std_logic;
-
- subtype tap_cnt_t is natural range 0 to ntaps-1;
- signal htap_cnt : tap_cnt_t;
- signal xtap_cnt_w : tap_cnt_t;
- signal xtap_cnt_r : tap_cnt_t;
- signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic;
- subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1;
- signal h_addr : tap_range_t;
- signal xmem_din, xmem_dout : in_t;
- signal xmem_we, y_valid : std_logic;
-
- type xmem_t is array (0 to ntaps-1) of in_t;
- signal xmem : xmem_t;
- signal y_out_reg : out_t;
- signal y_reg_valid : std_logic;
-
- -------------------------------------------------------------------------------
-begin
-
- h_addr_out <= h_addr;
- x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate);
-
- ----------------------------------------
- process (clk)
- begin
- if rising_edge(clk) then
- y_reg_valid <= '0';
- if srst = '1' then
- y_out_reg <= to_sfixed(0, y_out_reg);
- elsif y_valid = '1' then
- y_out_reg <= resize(y_stage, y_out_reg);
- y_reg_valid <= '1';
- end if;
- end if;
- end process;
-
- process (clk)
- begin
- if rising_edge(clk) then
- y_dout_valid <= '0';
- if srst = '1' then
- y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac));
- elsif y_reg_valid = '1' then
- y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
- y_dout_valid <= '1';
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_rw: process (clk)
- begin
- if rising_edge(clk) then
- if xmem_we = '1' then
- xmem(xtap_cnt_w) <= xmem_din;
- end if;
- xmem_dout <= xmem(xtap_cnt_r);
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout)
- begin
- xmem_din <= to_sfixed(0, xmem_din);
- if new_round = '1' and clr_xmem = '0' then
- xmem_din <= sfixed(x_din);
- end if;
- end process;
-
- ----------------------------------------
- proc_xmem_pointer: process(clk, new_round ,clr_xmem)
- begin
- xmem_we <= clr_xmem or new_round;
- if rising_edge(clk) then
- if srst = '1' then
- xtap_cnt_w <= tap_cnt_t'high;
- elsif xmem_we = '1' then
- if xtap_cnt_w /= tap_cnt_t'low then
- xtap_cnt_w <= xtap_cnt_w - 1;
- else
- xtap_cnt_w <= tap_cnt_t'high;
- end if;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_h_addr: process(htap_cnt)
- begin
- if fir_mode = symmetric then
- if ntaps_is_even then
- if htap_cnt > ntaps/2-1 then
- h_addr <= ntaps - htap_cnt - 1;
- else
- h_addr <= htap_cnt;
- end if;
- else
- if htap_cnt > (ntaps-1)/2 then
- h_addr <= ntaps - htap_cnt - 1;
- else
- h_addr <= htap_cnt;
- end if;
- end if;
- else
- h_addr <= htap_cnt;
- end if;
- end process;
-
- ----------------------------------------
- proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en)
- begin
- if rising_edge(clk) then
- if cnt_reset = '1' then
- htap_cnt <= tap_cnt_t'low;
- xtap_cnt_r <= xtap_cnt_w;
- elsif cnt_en = '1' then
- if htap_cnt /= tap_cnt_t'high then
- htap_cnt <= htap_cnt + 1;
- else
- htap_cnt <= tap_cnt_t'low;
- end if;
- if xtap_cnt_r /= tap_cnt_t'high then
- xtap_cnt_r <= xtap_cnt_r + 1;
- else
- xtap_cnt_r <= tap_cnt_t'low;
- end if;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- proc_valid_out: process(srst, clk, valid, new_round)
- variable val_pipe : unsigned(4 downto 0);
- variable ctrl_pipe : unsigned(2 downto 0);
-
- begin
- if rising_edge(clk) then
- if srst = '1' then
- ctrl_pipe := (others => '0');
- fir_stage_en <= '0';
- fir_stage_clr <= '0';
- else
- ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round;
- fir_stage_en <= stage_en;
- fir_stage_clr <= ctrl_pipe(2);
- end if;
- end if;
- cnt_reset <= new_round;
- end process;
-
- ----------------------------------------
- proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w)
- begin
- clr_xmem <= '0';
- new_round <= '0';
- cnt_en <= '0';
- ready <= '0';
- valid <= '0';
- sn <= s;
- stage_en <= '0';
- y_valid <= '0';
-
- case s is
- when init =>
- clr_xmem <= '1';
- if xtap_cnt_w = tap_cnt_t'low then
- sn <= idle;
- end if;
-
- when idle =>
- ready <= '1';
- if x_valid = '1' then
- sn <= start;
- end if;
-
- when start =>
- new_round <= '1';
- sn <= proc;
-
- when proc =>
- stage_en <= '1';
- cnt_en <= '1';
- if htap_cnt = tap_cnt_t'high then
- sn <= p1;
- end if;
-
- when p1 =>
- sn <= p2;
-
- when p2 =>
- sn <= output;
- ready <= '1';
-
- when output =>
- sn <= idle;
- y_valid <= '1';
- ready <= '1';
- if x_valid = '1' then
- sn <= start;
- end if;
-
- when others => null;
- end case;
- end process;
-
- proc_fsm_next: process(srst, clk, sn)
- begin
- if rising_edge(clk) then
- if srst = '1' then
- s <= init;
- else
- s <= sn;
- end if;
- end if;
- end process;
-
- ----------------------------------------
- inst_fir_stage: entity work.fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 1,
- coef_latency => 1,
- pipe_latency => 3
- )
- PORT MAP
- (
- rst => fir_stage_clr,
- clk => clk,
- x_in => x_stage,
- y_in => y_stage,
- h_in => h_din,
- x_out => xo,
- y_out => y_stage
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
-
-end Behavioral;
diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd
deleted file mode 100644
index af8bb68..0000000
--- a/lib/filter/src/fir_iterative_pkg.vhd
+++ /dev/null
@@ -1,52 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_iterative_pkg is
-
- type fir_iterative_mode_t is (normal, symmetric);
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
-package body fir_iterative_pkg is
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- variable res : integer;
- begin
- res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
- return res;
- end taps_nbits;
-
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- variable res : integer := ntaps;
- begin
- if mode = symmetric then
- if ntaps_is_even then
- res := ntaps/2;
- else
- res := (ntaps-1)/2 + 1;
- end if;
- end if;
- return res;
- end ntaps_addr;
-
-end; -- package fir_iterative_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd
deleted file mode 100644
index 2561848..0000000
--- a/lib/filter/src/fir_parallel.vhd
+++ /dev/null
@@ -1,218 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_parallel is
-Generic
-(
- ntaps : integer := 33;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- fir_mode : fir_parallel_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- h_in : in sfixed_array_t;
- in_valid : in std_logic;
- d_in : in sfixed;
- out_valid : out std_logic;
- d_out : out sfixed
-);
-end fir_parallel;
-
-architecture Behavioral of fir_parallel is
-
--------------------------------------------------------------------------------
- -- Component Declaration for FIR stage
- COMPONENT fir_stage
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_stage_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- type coeff_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- type stages_array_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
- constant fir_stage_mode : fir_stage_mode_t := transposed;
-
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
- SIGNAL x : stages_array_t(0 to ntaps-2);
- SIGNAL y : stages_array_t(0 to ntaps-2);
- SIGNAL h : coeff_array_t(0 to ntaps-1);
-
- -------------------------------------------------------------------------------
-begin
-
- -- Assign coefficients
- assign_coeffs:
- for i in 0 to ntaps-1 generate
- h(i) <= to_sfixed(h_in, i);
- end generate;
-
- ----------------------------------------
- -- Instantiate the FIR stages
- ----------------------------------------
- uut_first_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => d_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- out_valid => out_valid,
- x_out => x(0),
- y_out => y(0),
- y_out_clr => '0'
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- out_valid => open,
- x_out => x(i),
- y_out => y(i),
- y_out_clr => '0'
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_stage_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- in_valid => in_valid,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- out_valid => open,
- x_out => x_out,
- y_out => d_out,
- y_out_clr => '0'
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
-
-end Behavioral;
diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd
deleted file mode 100644
index 9243d8c..0000000
--- a/lib/filter/src/fir_parallel_pkg.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_stage_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_parallel_pkg is
-
- type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
-package body fir_parallel_pkg is
-
-
-end; -- package fir_parallel_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_pkg.vhd b/lib/filter/src/fir_pkg.vhd
deleted file mode 100644
index 9e904b5..0000000
--- a/lib/filter/src/fir_pkg.vhd
+++ /dev/null
@@ -1,54 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-
--------------------------------------------------------------------------------
-package fir_pkg is
-
- type fir_stage_mode_t is (transposed, systolic);
- type fir_iterative_mode_t is (normal, symmetric);
- type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym);
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer;
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer;
-
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
-package body fir_pkg is
-
- function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- variable res : integer;
- begin
- res := integer(NextExpBaseTwo(real(ntaps_addr(ntaps, mode))));
- return res;
- end taps_nbits;
-
- function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is
- constant ntaps_is_even : boolean := (ntaps mod 2) = 0;
- variable res : integer := ntaps;
- begin
- if mode = symmetric then
- if ntaps_is_even then
- res := ntaps/2;
- else
- res := (ntaps-1)/2 + 1;
- end if;
- end if;
- return res;
- end ntaps_addr;
-
-end; -- package fir_pkg;
-
--------------------------------------------------------------------------------
diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
deleted file mode 100644
index 68493c1..0000000
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ /dev/null
@@ -1,300 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_parallel - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_semi_parallel is
-Generic
-(
- ntaps_per_stage : integer := 32;
- nstages : integer := 2;
- pipe_latency : integer := 4;
- nbits_in : integer := 12;
- nbits_in_frac : integer := 11;
- nbits_stages : integer := 13;
- nbits_stages_frac : integer := 11;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 11
-);
-Port
-(
- rst : in std_logic;
- clk : in std_logic;
- h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
- h_we : in std_logic;
- h_in : in sfixed;
- din_vld : in std_logic;
- din : in sfixed;
- dout_vld : out std_logic;
- start : in std_logic;
- rdy : out std_logic;
- dout : out sfixed
-);
-end fir_semi_parallel;
-
-architecture Behavioral of fir_semi_parallel is
-
- -------------------------------------------------------------------------------
- constant coef_addr_nbits : natural := NextExpBaseTwo(ntaps_per_stage) + NextExpBaseTwo(nstages);
-
- subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- subtype count_t is natural range 0 to ntaps_per_stage-1;
- type count_array_t is array (nstages-1 downto 0) of count_t;
-
- subtype stage_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- type stage_array_t is array (0 to nstages) of stage_t;
-
- signal count_array : count_array_t;
- signal count0 : count_t;
- signal ce_array : unsigned(nstages downto 0);
- signal en_array : unsigned(nstages downto 0);
- signal coef_addr : unsigned(coef_addr_nbits-1 downto 0);
-
- SIGNAL x : stage_array_t;
- SIGNAL xo : stage_array_t;
- SIGNAL y : stage_array_t;
- SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- SIGNAL act : std_logic := '0';
- SIGNAL start_r : std_logic := '0';
- signal accu_load : std_logic;
- signal accu_ld_pipe : unsigned(nstages+pipe_latency-1 downto 0);
-
- signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- signal coef_we : unsigned(nstages-1 downto 0);
-
- type coef_array_t is array (0 to nstages-1) of unsigned(nbits_stages-1 downto 0);
- signal coef_din : unsigned(nbits_stages-1 downto 0);
- signal coef_dout : coef_array_t;
-
- -------------------------------------------------------------------------------
-begin
-
- assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure;
- assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure;
-
- x(0) <= resize(din_r, x(0));
- y(0) <= to_sfixed(0.0, y(0));
-
- accu_load <= accu_ld_pipe(accu_ld_pipe'left);
- start_r <= act and ce_array(ce_array'left) and not ce_array(ce_array'left-1);
-
-din_register:
- process(clk)
- begin
- if rising_edge(clk) then
- if din_vld = '1' then
- din_r <= din;
- end if;
- end if;
- end process;
-
-accu_load_pipe:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- accu_ld_pipe <= (others => '0');
- else
- accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & start_r;
- end if;
- end if;
- end process;
-
-coef_we_gen:
- process(clk)
- variable i : natural range 0 to nstages-1;
- variable caddr : unsigned(coef_addr_nbits-1 downto 0);
- variable saddr : unsigned(NextExpBaseTwo(nstages)-1 downto 0);
- begin
- if rising_edge(clk) then
- caddr := to_unsigned(h_addr, coef_addr_nbits);
- saddr := caddr(caddr'left downto NextExpBaseTwo(ntaps_per_stage));
- i := to_integer(saddr);
- coef_we <= (others => '0');
- coef_we(i) <= '1';
- coef_din <= unsigned(h_in);
- coef_addr <= caddr;
- end if;
- end process;
-
-rdy_logic:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- rdy <= '1';
- act <= '0';
- elsif start = '1' then
- rdy <= '0';
- act <= '1';
- elsif count0 = count_t'high-2 then
- rdy <= '1';
- act <= '0';
- end if;
- end if;
- end process;
-
-counter:
- process(clk)
- variable cnt : count_t;
- variable enable : std_logic;
- begin
- if rising_edge(clk) then
- if rst = '1' then
- cnt := count_t'high;
- elsif cnt /= count_t'high then
- cnt := cnt + 1;
- else
- enable := '0';
- if start_r = '1' then
- enable := '1';
- cnt := 0;
- end if;
- end if;
- count0 <= cnt;
- count_array <= count_array(count_array'left-1 downto 0) & cnt;
- en_array <= en_array(en_array'left-1 downto 0) & enable;
- end if;
- end process;
-
-ce_pipe:
- process(clk)
- begin
- if rising_edge(clk) then
- if rst = '1' then
- ce_array <= (others => '0');
- else
- ce_array <= ce_array(ce_array'left-1 downto 0) & din_vld;
- end if;
- end if;
- end process;
-
-gen_coef_ram:
- for i in 0 to nstages-1 generate
- signal addr_a : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
- signal addr_b : unsigned (NextExpBaseTwo(ntaps_per_stage)-1 downto 0);
- begin
- addr_a <= coef_addr(addr_a'length-1 downto 0);
- addr_b <= to_unsigned(count_array(i), addr_b'length);
- inst_coef_ram: entity work.dpram_1w1r
- GENERIC MAP
- (
- addr_width => NextExpBaseTwo(ntaps_per_stage),
- data_width => nbits_stages
- )
- PORT MAP (
- clka => clk,
- clkb => clk,
- en_a => '1',
- en_b => '1',
- we_a => coef_we(i),
- addr_a => addr_a,
- addr_b => addr_b,
- din_a => coef_din,
- dout_b => coef_dout(i)
- );
- end generate;
-
-
-gen_stages:
- for i in 0 to nstages-1 generate
- signal h_in : coef_t;
- begin
- h_in <= sfixed(coef_dout(i));
- inst_fir_stage: entity work.fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- pipe_latency => pipe_latency
- )
- PORT MAP
- (
- clk => clk,
- ce => en_array(i),
- x_in => x(i+1),
- y_in => y(i),
- h_in => h_in,
- x_out => xo(i+1),
- y_out => y(i+1)
- );
- end generate;
-
-
-gen_delays:
- for i in 0 to nstages-1 generate
- begin
- inst_delay_line : entity work.delay_line(ram_based)
- GENERIC MAP
- (
- nbits => nbits_stages,
- nbits_frac => nbits_stages_frac,
- ntaps => ntaps_per_stage,
- delay_fix => 0
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- shift_en => ce_array(i),
- delay => count_array(i),
- din => x(i),
- dout => x(i+1)
- );
- end generate;
-
-acumulator:
- process(clk)
- begin
- if rising_edge(clk) then
- dout_vld <= accu_load;
- if rst = '1' then
- dout_vld <= '0';
- elsif en_array(en_array'left) = '1' then
- if accu_load = '1' then
- dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
- accu <= y(nstages);
- else
- accu <= resize(accu + y(nstages), accu);
- end if;
- end if;
- end if;
- end process;
-
-
-end Behavioral;
diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd
deleted file mode 100644
index a519cf4..0000000
--- a/lib/filter/src/fir_stage.vhd
+++ /dev/null
@@ -1,157 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := false;
- has_out_reg : boolean := false;
- fir_mode : fir_stage_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
-);
-Port
-(
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
-);
-end fir_stage;
-
-architecture Behavioral of fir_stage is
-
-signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-signal valid, p_valid : std_logic;
-------------------------------------------------------------
-begin
-
-
-------------------------------------------------------------
- proc_in_reg_y: process(clk)
- begin
- if rising_edge(clk) then
- if srst = '1' or y_out_clr = '1' then
- yin <= to_sfixed(0, yin);
- else
- yin <= resize(y_in, yin);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in)
- variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- if has_in_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- xin <= to_sfixed(0, xin);
- hin <= to_sfixed(0, hin);
- valid <= '0';
- else
- valid <= in_valid;
- if in_valid = '1' then
- xin <= resize(x_in, xin);
- hin <= resize(h_in, hin);
- end if;
- end if;
- end if;
- else
- xin <= resize(x_in, xin);
- hin <= resize(h_in, hin);
- valid <= in_valid;
- end if;
- x_out <= resize(x_in, p);
-
- end process;
-
-------------------------------------------------------------
- proc_pipe_reg: process(srst, clk, valid, xin, hin)
- variable p : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- p := resize(xin * hin, p);
- if has_pipe_reg = true then
- if rising_edge(clk) then
- if srst = '1' then
- prod <= to_sfixed(0, prod);
- p_valid <= '0';
- else
- prod <= p;
- p_valid <= valid;
- end if;
- end if;
- else
- prod <= p;
- p_valid <= valid;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(srst, clk, p_valid, prod, yin)
- variable yout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- begin
- yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
--- if rising_edge(clk) then
--- if srst = '1' or y_out_clr = '1' then
--- y_out <= to_sfixed(0, yout);
--- out_valid <= '0';
--- else
--- y_out <= yout;
--- out_valid <= p_valid;
--- end if;
--- end if;
- out_valid <= p_valid;
- y_out <= yout;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd
deleted file mode 100644
index c6408b8..0000000
--- a/lib/filter/src/fir_stage_pkg.vhd
+++ /dev/null
@@ -1,18 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fir_stage_pkg is
-
-type fir_stage_mode_t is (transposed, systolic);
-
-end; -- package fir_stage_pkg;
-
-package body fir_stage_pkg is
-
-end; -- package fir_stage_pkg;
diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
deleted file mode 100644
index af0f74a..0000000
--- a/lib/filter/src/fir_stage_sys.vhd
+++ /dev/null
@@ -1,109 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 12:16:14 10/02/05
--- Design Name:
--- Module Name: fir_stage - Behavioral
--- Project Name:
--- Target Device:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
---------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.utils_pkg.all;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-
----- Uncomment the following library declaration if instantiating
----- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-entity fir_stage_sys is
-Generic
-(
- nbits_in : integer := 12;
- nbits_in_frac : integer := 12;
- nbits_out : integer := 12;
- nbits_out_frac : integer := 12;
- pipe_latency : integer := 4
-);
-Port
-(
- clk : in std_logic;
- ce : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- x_out : out sfixed;
- y_out : out sfixed
-);
-end fir_stage_sys;
-
-architecture Behavioral of fir_stage_sys is
-
-constant min_pipe_lat : integer := 4;
-
-subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
-type input_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-type coef_pipe_t is array (pipe_latency-2 downto 0) of in_t;
-
-signal yin : in_t;
-signal prod : out_t;
-
-------------------------------------------------------------
-begin
-
- assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure;
-
- yin <= resize(y_in, yin);
-
-------------------------------------------------------------
- proc_pipe_reg: process(clk)
- variable h_pipe : coef_pipe_t;
- variable x_pipe : input_pipe_t;
- begin
- if rising_edge(clk) then
- if ce = '1' then
- x_pipe := x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0));
- h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0));
- prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate);
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
- proc_out_reg: process(clk)
- variable yout : out_t;
- variable xout : in_t;
- begin
- if rising_edge(clk) then
- if ce = '1' then
- yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
- y_out <= yout;
- xout := resize(x_in, xout, fixed_wrap, fixed_truncate);
- x_out <= xout;
- end if;
- end if;
- end process;
-
-------------------------------------------------------------
-end Behavioral;
diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd
deleted file mode 100644
index 76b6024..0000000
--- a/lib/filter/src/tb_fir_iterative.vhd
+++ /dev/null
@@ -1,234 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_iterative IS
- Generic (
- ntaps : integer := 11;
- nbits_in : integer := 15;
- nbits_in_frac : integer := 15;
- nbits_stages : integer := 15;
- nbits_stages_frac : integer := 15;
- nbits_out : integer := 15;
- nbits_out_frac : integer := 15;
- fir_mode : fir_iterative_mode_t := symmetric;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_iterative;
-
-ARCHITECTURE behavior OF tb_fir_iterative IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_iterative
- GENERIC
- (
- ntaps : integer;
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_stages : integer;
- nbits_stages_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- fir_mode : fir_iterative_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- h_din : in sfixed;
- h_addr_out : out natural;
- ready : out std_logic;
- x_valid : in std_logic;
- x_din : in sfixed;
- y_dout_valid : out std_logic;
- y_dout : out sfixed
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- --Constants
- constant nsamples : integer := 32;
-
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL x_valid : std_logic := '0';
- SIGNAL h_din : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- SIGNAL x_din : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL y_dout : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_valid : std_logic;
- SIGNAL ready : std_logic;
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
--- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1);
- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1);
--- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps);
- signal x_input : real_array_t(0 to nsamples-1) :=
- (
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.9999,
- -0.0000,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0
-
- );
- type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- signal ymem : ymem_t;
-
- signal y_cnt : integer ;
- SIGNAL xi, yo : real := 0.0;
- SIGNAL h_addr : natural;
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(x_din);
- yo <= to_real(y_dout);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_fir_iterative: fir_iterative
- GENERIC MAP
- (
- ntaps => ntaps,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- h_din => h_din,
- h_addr_out => h_addr,
- ready => ready,
- x_valid => x_valid,
- x_din => x_din,
- y_dout_valid => y_valid,
- y_dout => y_dout
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- for i in 0 to nsamples-1 loop
- if i = nsamples/2 then
- wait for 43*PERIOD;
- end if;
- ------------------------------------------
- wait until rising_edge(clk) and ready = '1';
- x_din <= to_sfixed(x_input(i), x_din);
- x_valid <= '1';
- ------------------------------------------
- wait until rising_edge(clk);
- x_valid <= '0';
- end loop;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- process(srst, clk, y_valid)
- begin
- if rising_edge(clk) then
- h_din <= to_sfixed(coeffs(h_addr), h_din);
- if srst = '1' then
- y_cnt <= 0;
-
- elsif y_valid = '1' then
- ymem(y_cnt) <= y_dout;
- y_cnt <= y_cnt + 1;
- end if;
- end if;
- end process;
-
-END;
diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd
deleted file mode 100644
index e1ff939..0000000
--- a/lib/filter/src/tb_fir_parallel.vhd
+++ /dev/null
@@ -1,193 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_parallel IS
- Generic (
- ntaps : integer := 33;
- nbits_in : integer := 16;
- nbits_in_frac : integer := 16;
- nbits_stages : integer := 16;
- nbits_stages_frac : integer := 15;
- nbits_out : integer := 16;
- nbits_out_frac : integer := 16;
- has_in_reg : boolean := false;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := false;
- fir_mode : fir_parallel_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_parallel;
-
-ARCHITECTURE behavior OF tb_fir_parallel IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_parallel
- GENERIC
- (
- ntaps : integer;
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_stages : integer;
- nbits_stages_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_parallel_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- h_in : in sfixed_array_t;
- in_valid : in std_logic;
- d_in : in sfixed;
- out_valid : out std_logic;
- d_out : out sfixed
- );
- END COMPONENT;
-
- -------------------------------------------------------------------------------
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL out_valid : std_logic := '0';
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac);
-
- SIGNAL xi, yo : real := 0.0;
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_fir_parallel: fir_parallel
- GENERIC MAP
- (
- ntaps => ntaps,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- clk => clk,
- h_in => coeff_in,
- in_valid => in_valid,
- d_in => x_in,
- out_valid => out_valid,
- d_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file fi : file_t open read_mode is "wav_in.dat";
- variable si : sample_t;
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- while not endfile(fi) loop
- read(fi, si);
- x_in <= to_sfixed(to_signed(si, x_in'length));
- in_valid <= '1';
- wait for PERIOD;
- wait until rising_edge(clk);
- end loop;
- ------------------------------------------
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable, out_valid)
- file fo : file_t open write_mode is "wav_out.dat";
- variable so : sample_t;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
- so := to_integer(y_out);
- write(fo, so);
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd
deleted file mode 100644
index e540caf..0000000
--- a/lib/filter/src/tb_fir_semi_parallel.vhd
+++ /dev/null
@@ -1,289 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.filter_pkg.all;
-use work.fir_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_semi_parallel IS
- Generic
- (
- ntaps_per_stage : integer := 16;
- nstages : integer := 4;
- nbits_in : integer := 32;
- nbits_in_frac : integer := 30;
- nbits_stages : integer := 32;
- nbits_stages_frac : integer := 30;
- nbits_out : integer := 32;
- nbits_out_frac : integer := 30
- );
-END tb_fir_semi_parallel;
-
-ARCHITECTURE behavior OF tb_fir_semi_parallel IS
-
- -------------------------------------------------------------------------------
- --Constants
- constant PERIOD : time := 10 ns;
- constant nsamples : integer := 32;
- constant M : integer := 1;
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL rst : std_logic := '1';
- SIGNAL din_vld : std_logic := '0';
- SIGNAL d_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
- signal h_addr : natural := 0;
- SIGNAL h_we : std_logic := '0';
- SIGNAL h_in : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
- SIGNAL start : std_logic := '0';
-
- --Outputs
- SIGNAL d_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL dout_vld : std_logic;
- SIGNAL rdy : std_logic;
-
- SIGNAL fileout_enable : std_logic := '1';
-
-
- SIGNAL xi, yo : real := 0.0;
-
- CONSTANT ntaps : natural := nstages*ntaps_per_stage;
- type h_mem_t is array (0 to ntaps-1) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
- variable res : h_mem_t;
- begin
- for i in 0 to ntaps-1 loop
- res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_h_mem;
-
- CONSTANT coeffs : real_array_t(0 to ntaps-1) := FilterCoef_Lowpass(ntaps, 0.1, 4.0);
- CONSTANT h_mem : h_mem_t := to_h_mem(coeffs, ntaps, h_in);
-
- -- file I/O
- subtype sample_t is integer range -32768 to 32767;
- type file_t is file of sample_t;
-
- signal x_input : real_array_t(0 to nsamples-1) :=
- (
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 1.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0,
- 0.0
-
- );
-
- -------------------------------------------------------------------------------
-BEGIN
-
- xi <= to_real(d_in);
- yo <= to_real(d_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut : entity work.fir_semi_parallel
- GENERIC MAP
- (
- ntaps_per_stage => ntaps_per_stage,
- nstages => nstages,
- pipe_latency => 4,
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_stages => nbits_stages,
- nbits_stages_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac
- )
- PORT MAP
- (
- rst => rst,
- clk => clk,
- h_addr => h_addr,
- h_we => h_we,
- h_in => h_in,
- din_vld => din_vld,
- din => d_in,
- dout_vld => dout_vld,
- rdy => rdy,
- start => start,
- dout => d_out
- );
-
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
- file fi : file_t open read_mode is "wav_in.dat";
- variable si : sample_t;
- variable remain : integer;
- variable j : integer;
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- rst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- -- write coeffs
- for i in 0 to ntaps-1 loop
- wait until rising_edge(clk);
- h_addr <= i;
- h_in <= h_mem(i);
- h_we <= '1';
- end loop;
- wait until rising_edge(clk);
--- h_addr <= 0;
--- h_in <= to_sfixed(0.25, h_in);
--- h_we <= '1';
--- wait until rising_edge(clk);
- h_we <= '0';
-
- -- Write zeros
- remain := ntaps_per_stage*nstages;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(0.0, d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- ------------------------------------------
- -- Write data
- remain := nsamples;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(x_input(j), d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- -- Write zeros
- remain := 100;
- j := 0;
- while remain /= 0 loop
- wait until rising_edge(clk) and rdy = '1';
- for i in 0 to M-1 loop
- d_in <= to_sfixed(0.0, d_in);
- din_vld <= '1';
- j := j + 1;
- remain := remain - 1;
- wait until rising_edge(clk);
- end loop;
- din_vld <= '0';
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
--- wait until rising_edge(clk);
- start <= '1';
- wait until rising_edge(clk);
- start <= '0';
- end loop;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable)
- file fo : file_t open write_mode is "wav_out.dat";
- variable so : sample_t;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' then
- if dout_vld = '1' then
- so := to_integer(d_out);
- write(fo, so);
- end if;
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd
deleted file mode 100644
index 04bb03f..0000000
--- a/lib/filter/src/tb_fir_stage.vhd
+++ /dev/null
@@ -1,276 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage IS
- Generic (
- ntaps : integer := 33;
- nbits_in : integer := 24;
- nbits_in_frac : integer := 23;
- nbits_stages : integer := 25;
- nbits_stages_frac : integer := 23;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 22;
- has_in_reg : boolean := true;
- has_pipe_reg : boolean := true;
- has_out_reg : boolean := false;
- fir_mode : fir_stage_mode_t := transposed;
- rounding : boolean := true;
- saturating : boolean := true
- );
-END tb_fir_stage;
-
-ARCHITECTURE behavior OF tb_fir_stage IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_stage
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- has_in_reg : boolean;
- has_pipe_reg : boolean;
- has_out_reg : boolean;
- fir_mode : fir_stage_mode_t;
- rounding : boolean;
- saturating : boolean
- );
- PORT
- (
- srst : in std_logic;
- clk : in std_logic;
- in_valid : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- out_valid : out std_logic;
- x_out : out sfixed;
- y_out : out sfixed;
- y_out_clr : in std_logic
- );
- END COMPONENT;
-
- type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL clk : std_logic := '0';
- SIGNAL srst : std_logic := '1';
- SIGNAL in_valid : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL out_valid : std_logic := '0';
-
- SIGNAL x : stages_t(0 to ntaps-2);
- SIGNAL y : stages_t(0 to ntaps-2);
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- function to_sfixed(x_real : real_array_t) return stages_t is
- variable res : stages_t(x_real'range);
- begin
- for i in x_real'range loop
- res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_sfixed;
-
- constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-
- SIGNAL xi, yo : real := 0.0;
-
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_first_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- out_valid => out_valid,
- x_out => x(0),
- y_out => y(0)
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => false,
- saturating => false
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- out_valid => open,
- x_out => x(i),
- y_out => y(i)
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- has_in_reg => has_in_reg,
- has_pipe_reg => has_pipe_reg,
- has_out_reg => has_out_reg,
- fir_mode => fir_mode,
- rounding => rounding,
- saturating => saturating
- )
- PORT MAP
- (
- srst => srst,
- y_out_clr => '0',
- clk => clk,
- in_valid => in_valid,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- out_valid => open,
- x_out => x_out,
- y_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- srst <= '0';
- ------------------------------------------
- wait for 2*PERIOD;
-
- x_in <= to_sfixed(0.0, x_in);
-
- wait until rising_edge(clk);
- in_valid <= '1';
-
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 20*PERIOD;
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(1.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 150*PERIOD;
-
- wait until rising_edge(clk);
- in_valid <= '0';
-
- wait for 20*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable, out_valid)
- file RESULT_FIR: text open write_mode is "fir.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then
- fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/filter/src/tb_fir_stage_sys.vhd b/lib/filter/src/tb_fir_stage_sys.vhd
deleted file mode 100644
index b0afe32..0000000
--- a/lib/filter/src/tb_fir_stage_sys.vhd
+++ /dev/null
@@ -1,230 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 17:16:42 13.05.2007
--- Design Name: tb_fir_stage
--- Module Name: tb_fir_stage.vhd
--- Project Name: fir_stage
--- Target Device:
--- Tool versions:
--- Description:
---
---------------------------------------------------------------------------------
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.MATH_REAL.ALL;
-USE ieee.numeric_std.ALL;
-use std.textio.all; -- Imports the standard textio package.
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-library work;
-use work.fixed_util_pkg.all;
-use work.fir_pkg.all;
-use work.filter_pkg.all;
-
-use work.PCK_FIO.all;
-
-ENTITY tb_fir_stage_sys IS
- Generic
- (
- ntaps : integer := 33;
- nbits_in : integer := 24;
- nbits_in_frac : integer := 23;
- nbits_stages : integer := 25;
- nbits_stages_frac : integer := 23;
- nbits_out : integer := 24;
- nbits_out_frac : integer := 22
- );
-END tb_fir_stage_sys;
-
-ARCHITECTURE behavior OF tb_fir_stage_sys IS
-
- -- Component Declaration for the Unit Under Test (UUT)
- COMPONENT fir_stage_sys
- GENERIC
- (
- nbits_in : integer;
- nbits_in_frac : integer;
- nbits_out : integer;
- nbits_out_frac : integer;
- input_latency : integer;
- coef_latency : integer;
- pipe_latency : integer
- );
- PORT
- (
- clk : in std_logic;
- ce : in std_logic;
- x_in : in sfixed;
- y_in : in sfixed;
- h_in : in sfixed;
- x_out : out sfixed;
- y_out : out sfixed
- );
- END COMPONENT;
-
- type stages_t is array (natural range <>) of sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
-
- --Constants
- constant PERIOD : time := 10 ns;
- constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac);
-
- --Inputs
- SIGNAL ce : std_logic := '1';
- SIGNAL clk : std_logic := '0';
- SIGNAL x_in : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
-
- --Outputs
- SIGNAL x_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
- SIGNAL y_out : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
-
- SIGNAL x : stages_t(0 to ntaps-2);
- SIGNAL y : stages_t(0 to ntaps-2);
-
- SIGNAL fileout_enable : std_logic := '1';
-
- -- Test coefficients
- function to_sfixed(x_real : real_array_t) return stages_t is
- variable res : stages_t(x_real'range);
- begin
- for i in x_real'range loop
- res(i) := to_sfixed(x_real(i), res(i), fixed_wrap, fixed_round);
- end loop;
-
- return res;
- end to_sfixed;
-
- constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0));
-
- SIGNAL xi, yo : real := 0.0;
-
-BEGIN
-
- xi <= to_real(x_in);
- yo <= to_real(y_out);
-
- ----------------------------------------
- -- Instantiate the Unit Under Test (UUT)
- ----------------------------------------
- uut_first_stage_sys: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_in,
- nbits_in_frac => nbits_in_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 1,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x_in,
- y_in => zero_in,
- h_in => h(ntaps-1),
- x_out => x(0),
- y_out => y(0)
- );
-
- ----------------------------------------
- gen_stages:
- for i in 1 to ntaps-2 generate
- uut_stages: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_stages,
- nbits_out_frac => nbits_stages_frac,
- input_latency => 2,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x(i-1),
- y_in => y(i-1),
- h_in => h(ntaps-i-1),
- x_out => x(i),
- y_out => y(i)
- );
- end generate;
-
- ----------------------------------------
- uut_last_stage: fir_stage_sys
- GENERIC MAP
- (
- nbits_in => nbits_stages,
- nbits_in_frac => nbits_stages_frac,
- nbits_out => nbits_out,
- nbits_out_frac => nbits_out_frac,
- input_latency => 2,
- coef_latency => 1,
- pipe_latency => 2
- )
- PORT MAP
- (
- clk => clk,
- ce => ce,
- x_in => x(ntaps-2),
- y_in => y(ntaps-2),
- h_in => h(0),
- x_out => x_out,
- y_out => y_out
- );
-
- ----------------------------------------
- -- Finished instantiation
- ----------------------------------------
- tb_clk : PROCESS
- BEGIN
- clk <= not clk;
- wait for PERIOD/2;
- END PROCESS;
-
- tb : PROCESS
-
- BEGIN
-
- -- Wait 100 ns for global reset to finish
- wait for 4*PERIOD;
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 40*PERIOD;
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(1.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
- wait until rising_edge(clk);
- x_in <= to_sfixed(0.0, x_in);
-
- wait for 150*PERIOD;
-
- assert false report "Test finished" severity error;
- wait;
- END PROCESS;
-
- tb_fo : PROCESS(clk, fileout_enable)
- file RESULT_FIR: text open write_mode is "fir.txt";
- variable L: line;
-
- BEGIN
- if rising_edge(clk) and fileout_enable = '1' then
- fprint(RESULT_FIR, L,"%s\n", REAL'image(yo));
- end if;
-
- END PROCESS;
-
-END;
diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd
deleted file mode 100644
index 6397ebc..0000000
--- a/lib/fix_std/fix_std.vhd
+++ /dev/null
@@ -1,1007 +0,0 @@
----------------------------------------------------------------------
---
--- Package fix_std
--- Fixed point arithmetic based on numeric_std
---
----------------------------------------------------------------------
---
--- This document describes a VHDL package of definitions and subprograms
--- intended to support the use of fixed-point arithmetic in test benches
--- and synthesisable designs. This document and the package it describes
--- are made freely available to the HDL design community without warranty
--- of any kind. You are welcome to make use of this information for your
--- own private study and in your own designs. If you make use of the
--- package, you accept sole responsibility for its fitness for purpose
--- and its suitability in your application. You are free to modify the
--- package in any way, and to record your contribution to it, but this
--- notice must appear in a prominent place in any modified or derived
--- version of the package or its supporting documentation.
---
--- The author wishes to thank his employer Doulos Ltd for making
--- available the facilities used to develop, test and distribute this
--- package. However, Doulos Ltd accepts no responsibility for the
--- package's contents and cannot support it in any way.
---
----------------------------------------------------------------------
--- Revision information:
---
--- Version 0.1 06-May-2003
--- Alpha version, for review
--- No division operators are provided, pending detailed
--- consultation on their functionality.
--- Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2 11-Jun-2003
--- Fixes aiming to make the package portable across all synthesis tools:
--- * Removed deferred constants, made them package constants
--- * Removed all variable initialisations in procedures, made them
--- procedural initialisations in the code
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package fix_std is
-
- --------------------------------------------------------------------
-
- -- Integer subtype specifying legal values for a bit index.
- -- At present it's restricted to 'natural' to conform with
- -- the behaviour of mainstream synthesis tools. For simulation,
- -- or in the future when synthesis tools are able to cope, it
- -- would be possible to change this subtype to be the full
- -- integer range, thus allowing negative subscripts for
- -- fraction bits.
- --
- subtype Fix_Subscr is natural;
-
- -- Fixed-point offset, the bit number (subscript) used for
- -- the bit in a UFix or SFix vector having binary weight 2^0
- -- (the units bit).
- --
- constant FixP: Fix_Subscr := 100;
-
- -- Type declarations for the basic unsigned and signed fixed point
- -- data types:
- --
- type UFix is array (Fix_Subscr range <>) of std_logic;
- type SFix is array (Fix_Subscr range <>) of std_logic;
-
- -- Type declarations for control of rounding and overflow modes:
- --
- type Fix_Rounding_Mode is (
- clip_LS, -- Throw away unwanted least significant bits
- towards_zero, -- Round towards zero - same as clip_LS for UFix
- to_nearest -- Round to nearest. Exact halves round up.
- );
- type Fix_Overflow_Mode is (
- clip_MS, -- Throw away unwanted most significant bits
- saturate -- Saturate overflow to nearest representable value
- );
-
- -- Defaults for these modes:
- --
- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
- --------------------------------------------------------------------
-
- ---------------------------
- -- E. Extraction functions
- ---------------------------
-
- -- E.1. Return the integral part of a UFix value
- function Int(U: UFix) return UFix;
-
- -- E.2. Return the fractional part of a UFix value
- function Frac(U: UFix) return UFix;
-
- -- E.3. Return the integral part of a SFix value
- function Int(S: SFix) return SFix;
-
- -- E.4. Return the fractional part of a SFix value
- function Frac(S: SFix) return UFix;
-
- -- E.5. Widen a SFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(S: SFix) return SFix;
-
- -- E.6. Widen a UFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(U: UFix) return UFix;
-
- ---------------------------
- -- T. Conversion functions
- ---------------------------
-
- -- T.1 to T.8: Unsigned conversions
- --
- -- T.1. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.2. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.3. Conversion from integer to UFix. Provide number of
- -- integer bits and number of fraction bits. Note that
- -- negative input is tolerated!
- --
- function to_UFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.4. Conversion from unsigned to UFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting UFix.
- --
- function to_UFix(
- N : unsigned;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix;
-
- -- T.5. Conversion from unsigned to UFix. Automatically set the
- -- range of the resulting UFix to match the unsigned value,
- -- as an integral UFix value with no fraction bits.
- --
- function to_UFix( N : unsigned ) return UFix;
-
- -- T.6. Conversion from UFix to unsigned. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_unsigned(
- N : UFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned;
-
- -- T.7. Conversion from UFix to unsigned. Caller specifies
- -- required number of bits in unsigned result.
- --
- function to_unsigned(
- N : UFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned;
-
- -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer;
-
-
- -- T.9 to T.16: Signed conversions
- --
- -- T.9. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.10. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.11. Conversion from integer to SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.12. Conversion from signed to SFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting SFix.
- --
- function to_SFix(
- N : signed;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix;
-
- -- T.13. Conversion from signed to SFix. Automatically set the
- -- range of the resulting SFix to match the signed value,
- -- as an integral SFix value with no fraction bits.
- --
- function to_SFix( N : signed ) return SFix;
-
- -- T.14. Conversion from SFix to signed. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_signed(
- N : SFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed;
-
- -- T.15. Conversion from SFix to signed. Caller specifies
- -- required number of bits in signed result.
- --
- function to_signed(
- N : SFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed;
-
- -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer;
-
- -- T.17. Conversion from UFix to SFix. This simply adds
- -- an extra more significant bit, set to zero.
- --
- function to_SFix(U: UFix) return SFix;
-
- ----------------------------------
- -- V. Copy-to-variable procedures
- ----------------------------------
-
- -- Range-aware copying of an expression into a variable. The
- -- ranges of destination variable and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- V.1 to V.5: Copy an expression into a UFix variable
- --
-
- -- V.1. Copy UFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
- --
- -- V.2. Copy SFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.3. Copy UNSIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.4. Copy SIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.5. Copy integer to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.6 to V.10: Copy an expression into a SFix variable
- --
-
- -- V.6. Copy UFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.7. Copy SFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.8. Copy UNSIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.9. Copy SIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- V.10. Copy integer to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
-
- --------------------------------
- -- S. Copy-to-signal procedures
- --------------------------------
- --
- -- Range-aware copying of an expression into a signal. The
- -- ranges of destination signal and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- S.1 to S.5: Copy an expression into a UFix signal
- --
-
- -- S.1. Copy UFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.1. Copy SFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.3. Copy UNSIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.4. Copy SIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.5. Copy integer to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.6 to S.10: Copy an expression into a SFix signal
- --
-
- -- S.6. Copy UFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.7. Copy SFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.8. Copy UNSIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.9. Copy SIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
- -- S.10. Copy integer to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- );
-
-
- ------------------------------------------------------------------
- -- A. Arithmetic operations involving UFix, SFix and other
- -- numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- --
- -- IMPORTANT NOTE:
- -- Arithmetic operators return a result that is wide enough
- -- and precise enough so that no information is lost. THIS IS
- -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
- -- In the detailed description that follow, "scaling" means
- -- the numerical value (weight) of the least significant bit
- -- in a fixed-point value.
- --
- -- ADDITION returns a result whose least significant bit
- -- is the same as the least significant bit in either operand,
- -- and whose most significant bit is one position higher than
- -- the most significant bit in either operand. Addition of
- -- two operands having the same bounds therefore results in
- -- a growth of one bit at the most significant end.
- --
- -- SUBTRACTION where one or both operands are signed behaves
- -- in the same way as addition. Subtraction where both operands
- -- are unsigned returns a result whose most significant bit
- -- position is the same as the most significant bit in either
- -- operand, and whose least significant bit is the same as the
- -- least significant bit in either operand.
- --
- -- MULTIPLICATION returns a result whose width is the sum of
- -- the widths of its two operands, and whose scaling is the
- -- product of its two operands' scalings.
- --
- -- UNARY NEGATION always gives a result having one more
- -- significant bit than the operand.
- --
- -- ABSOLUTE VALUE always gives a result having exactly the
- -- same subtype as its operand.
- --
- -- In binary operations where one operand is a fixed-point type
- -- and the other is an integer numeric type, the integer operand
- -- is first converted to a fixed-point type of the same subtype
- -- as the other operand using Copy_V with default rounding and
- -- overflow modes. The operation is then performed between two
- -- fixed-point operands in the normal way.
- --
- ------------------------------------------------------------------
-
-
- ------------------------------------
- -- A.1. Unary "-" negation operator
- ------------------------------------
-
- -- A.1.1. SFix := - UFix
- function "-" (R: UFix) return SFix;
-
- -- A.1.2. SFix := - SFix
- function "-" (R: SFix) return SFix;
-
-
- --------------------------------------------
- -- A.2. Unary "abs" absolute-value operator
- --------------------------------------------
-
- -- A.2.1. SFix := abs SFix
- function "abs" (R: SFix) return SFix;
-
-
- -------------------------------------
- -- A.3. Binary "+" addition operator
- -------------------------------------
-
- -- A.3.1. UFix := UFix + UFix
- function "+" (L: UFix; R: UFix) return UFix;
-
- -- A.3.2. UFix := UFix + unsigned
- function "+" (L: UFix; R: unsigned) return UFix;
-
- -- A.3.3. UFix := unsigned + UFix
- function "+" (L: unsigned; R: UFix) return UFix;
-
- -- A.3.4. UFix := UFix + natural
- function "+" (L: UFix; R: natural) return UFix;
-
- -- A.3.5. UFix := natural + UFix
- function "+" (L: natural; R: UFix) return UFix;
-
- -- A.3.6. SFix := SFix + SFix
- function "+" (L: SFix; R: SFix) return SFix;
-
- -- A.3.7. SFix := SFix + UFix
- function "+" (L: SFix; R: UFix) return SFix;
-
- -- A.3.8. SFix := UFix + SFix
- function "+" (L: UFix; R: SFix) return SFix;
-
- -- A.3.9. SFix := SFix + signed
- function "+" (L: SFix; R: signed) return SFix;
-
- -- A.3.10. SFix := signed + SFix
- function "+" (L: signed; R: SFix) return SFix;
-
- -- A.3.11. SFix := SFix + integer
- function "+" (L: SFix; R: integer) return SFix;
-
- -- A.3.12. SFix := integer + SFix
- function "+" (L: integer; R: SFix) return SFix;
-
-
- ----------------------------------------
- -- A.4. Binary "-" subtraction operator
- ----------------------------------------
- --
- -- NOTE: There is a special problem with subtraction
- -- operators that return a UFix result if that result
- -- goes negative. Our arbitrary decision is that we
- -- truncate most-significant bits in this case. If you
- -- wish to avoid the risk of this arbitrarily-defined
- -- truncation behaviour, change one or more of your
- -- operands to SFix and get a SFix result using this
- -- idiom:
- -- SFix := UFix + (-UFix)
- -- or copy one of the UFix operands into a SFix that's
- -- one bit wider, before performing the operation.
- --
- -- Subtractions returning a UFix result take unsigned
- -- operands and do not exhibit bit growth.
- -- Subtractions returning a SFix result take signed or
- -- unsigned operands and exhibit one-bit growth like addition.
-
- -- A.4.1. UFix := UFix - UFix
- function "-" (L: UFix; R: UFix) return UFix;
-
- -- A.4.2. UFix := UFix - unsigned
- function "-" (L: UFix; R: unsigned) return UFix;
-
- -- A.4.3. UFix := unsigned - UFix
- function "-" (L: unsigned; R: UFix) return UFix;
-
- -- A.4.4. UFix := UFix - natural
- function "-" (L: UFix; R: natural) return UFix;
-
- -- A.4.5. UFix := natural - UFix
- function "-" (L: natural; R: UFix) return UFix;
-
- -- A.4.6. SFix := SFix - SFix
- function "-" (L: SFix; R: SFix) return SFix;
-
- -- A.4.7. SFix := SFix - UFix
- function "-" (L: SFix; R: UFix) return SFix;
-
- -- A.4.8. SFix := UFix - SFix
- function "-" (L: UFix; R: SFix) return SFix;
-
- -- A.4.9. SFix := SFix - signed
- function "-" (L: SFix; R: signed) return SFix;
-
- -- A.4.10. SFix := signed - SFix
- function "-" (L: signed; R: SFix) return SFix;
-
- -- A.4.11. SFix := SFix - integer
- function "-" (L: SFix; R: integer) return SFix;
-
- -- A.4.12. SFix := integer - SFix
- function "-" (L: integer; R: SFix) return SFix;
-
-
- -------------------------------------------
- -- A.5. Binary "*" multiplication operator
- -------------------------------------------
-
- -- A.5.1. UFix := UFix * UFix
- function "*" (L: UFix; R: UFix) return UFix;
-
- -- A.5.2. UFix := UFix * unsigned
- function "*" (L: UFix; R: unsigned) return UFix;
-
- -- A.5.3. UFix := unsigned * UFix
- function "*" (L: unsigned; R: UFix) return UFix;
-
- -- A.5.4. UFix := UFix * natural
- function "*" (L: UFix; R: natural) return UFix;
-
- -- A.5.5. UFix := natural * UFix
- function "*" (L: natural; R: UFix) return UFix;
-
- -- A.5.6. SFix := SFix * SFix
- function "*" (L: SFix; R: SFix) return SFix;
-
- -- A.5.7. SFix := SFix * UFix
- function "*" (L: SFix; R: UFix) return SFix;
-
- -- A.5.8. SFix := UFix * SFix
- function "*" (L: UFix; R: SFix) return SFix;
-
- -- A.5.9. SFix := SFix * signed
- function "*" (L: SFix; R: signed) return SFix;
-
- -- A.5.10. SFix := signed * SFix
- function "*" (L: signed; R: SFix) return SFix;
-
- -- A.5.11. SFix := SFix * integer
- function "*" (L: SFix; R: integer) return SFix;
-
- -- A.5.12. SFix := integer * SFix
- function "*" (L: integer; R: SFix) return SFix;
-
-
- ------------------------------------------------------------------
- -- R. Relational operators - arithmetic comparisons involving
- -- UFix, SFix and other numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- -- Note that in all cases comparisons are exact; if one
- -- operand has more fraction bits than the other, the less
- -- precise operand will have its LSBs zero-extended, and
- -- these zero bits will take part in comparison with whatever
- -- LSBs exist in the more precise operand.
- ------------------------------------------------------------------
-
- -------------------------------------
- -- R.1. Binary "=" equality operator
- -------------------------------------
-
- -- R.1.1. UFix = UFix
- function "=" (L: UFix; R: UFix) return boolean;
-
- -- R.1.2. UFix = unsigned
- function "=" (L: UFix; R: unsigned) return boolean;
-
- -- R.1.3. unsigned = UFix
- function "=" (L: unsigned; R: UFix) return boolean;
-
- -- R.1.4. UFix = integer
- function "=" (L: UFix; R: integer) return boolean;
-
- -- R.1.5. integer = UFix
- function "=" (L: integer; R: UFix) return boolean;
-
- -- R.1.6. SFix = SFix
- function "=" (L: SFix; R: SFix) return boolean;
-
- -- R.1.7. SFix = UFix
- function "=" (L: SFix; R: UFix) return boolean;
-
- -- R.1.8. UFix = SFix
- function "=" (L: UFix; R: SFix) return boolean;
-
- -- R.1.9. SFix = signed
- function "=" (L: SFix; R: signed) return boolean;
-
- -- R.1.10. signed = SFix
- function "=" (L: signed; R: SFix) return boolean;
-
- -- R.1.11. SFix = integer
- function "=" (L: SFix; R: integer) return boolean;
-
- -- R.1.12. integer = SFix
- function "=" (L: integer; R: SFix) return boolean;
-
-
- --------------------------------------
- -- R.2. Binary "<" less-than operator
- --------------------------------------
-
- -- R.2.1. UFix < UFix
- function "<" (L: UFix; R: UFix) return boolean;
-
- -- R.2.2. UFix < unsigned
- function "<" (L: UFix; R: unsigned) return boolean;
-
- -- R.2.3. unsigned < UFix
- function "<" (L: unsigned; R: UFix) return boolean;
-
- -- R.2.4. UFix < integer
- function "<" (L: UFix; R: integer) return boolean;
-
- -- R.2.5. integer < UFix
- function "<" (L: integer; R: UFix) return boolean;
-
- -- R.2.6. SFix < SFix
- function "<" (L: SFix; R: SFix) return boolean;
-
- -- R.2.7. SFix < UFix
- function "<" (L: SFix; R: UFix) return boolean;
-
- -- R.2.8. UFix < SFix
- function "<" (L: UFix; R: SFix) return boolean;
-
- -- R.2.9. SFix < signed
- function "<" (L: SFix; R: signed) return boolean;
-
- -- R.2.10. signed < SFix
- function "<" (L: signed; R: SFix) return boolean;
-
- -- R.2.11. SFix < integer
- function "<" (L: SFix; R: integer) return boolean;
-
- -- R.2.12. integer < SFix
- function "<" (L: integer; R: SFix) return boolean;
-
-
- ----------------------------------------
- -- R.3. Binary "/=" inequality operator
- ----------------------------------------
-
- -- R.3.1. UFix /= UFix
- function "/=" (L: UFix; R: UFix) return boolean;
-
- -- R.3.2. UFix /= unsigned
- function "/=" (L: UFix; R: unsigned) return boolean;
-
- -- R.3.3. unsigned /= UFix
- function "/=" (L: unsigned; R: UFix) return boolean;
-
- -- R.3.4. UFix /= integer
- function "/=" (L: UFix; R: integer) return boolean;
-
- -- R.3.5. integer /= UFix
- function "/=" (L: integer; R: UFix) return boolean;
-
- -- R.3.6. SFix /= SFix
- function "/=" (L: SFix; R: SFix) return boolean;
-
- -- R.3.7. SFix /= UFix
- function "/=" (L: SFix; R: UFix) return boolean;
-
- -- R.3.8. UFix /= SFix
- function "/=" (L: UFix; R: SFix) return boolean;
-
- -- R.3.9. SFix /= signed
- function "/=" (L: SFix; R: signed) return boolean;
-
- -- R.3.10. signed /= SFix
- function "/=" (L: signed; R: SFix) return boolean;
-
- -- R.3.11. SFix /= integer
- function "/=" (L: SFix; R: integer) return boolean;
-
- -- R.3.12. integer /= SFix
- function "/=" (L: integer; R: SFix) return boolean;
-
-
- -----------------------------------------
- -- R.4. Binary ">" greater-than operator
- -----------------------------------------
-
- -- R.4.1. UFix > UFix
- function ">" (L: UFix; R: UFix) return boolean;
-
- -- R.4.2. UFix > unsigned
- function ">" (L: UFix; R: unsigned) return boolean;
-
- -- R.4.3. unsigned > UFix
- function ">" (L: unsigned; R: UFix) return boolean;
-
- -- R.4.4. UFix > integer
- function ">" (L: UFix; R: integer) return boolean;
-
- -- R.4.5. integer > UFix
- function ">" (L: integer; R: UFix) return boolean;
-
- -- R.4.6. SFix > SFix
- function ">" (L: SFix; R: SFix) return boolean;
-
- -- R.4.7. SFix > UFix
- function ">" (L: SFix; R: UFix) return boolean;
-
- -- R.4.8. UFix > SFix
- function ">" (L: UFix; R: SFix) return boolean;
-
- -- R.4.9. SFix > signed
- function ">" (L: SFix; R: signed) return boolean;
-
- -- R.4.10. signed > SFix
- function ">" (L: signed; R: SFix) return boolean;
-
- -- R.4.11. SFix > integer
- function ">" (L: SFix; R: integer) return boolean;
-
- -- R.4.12. integer > SFix
- function ">" (L: integer; R: SFix) return boolean;
-
-
- ----------------------------------------------
- -- R.5. Binary ">=" greater-or-equal operator
- ----------------------------------------------
-
- -- R.5.1. UFix >= UFix
- function ">=" (L: UFix; R: UFix) return boolean;
-
- -- R.5.2. UFix >= unsigned
- function ">=" (L: UFix; R: unsigned) return boolean;
-
- -- R.5.3. unsigned >= UFix
- function ">=" (L: unsigned; R: UFix) return boolean;
-
- -- R.5.4. UFix >= integer
- function ">=" (L: UFix; R: integer) return boolean;
-
- -- R.5.5. integer >= UFix
- function ">=" (L: integer; R: UFix) return boolean;
-
- -- R.5.6. SFix >= SFix
- function ">=" (L: SFix; R: SFix) return boolean;
-
- -- R.5.7. SFix >= UFix
- function ">=" (L: SFix; R: UFix) return boolean;
-
- -- R.5.8. UFix >= SFix
- function ">=" (L: UFix; R: SFix) return boolean;
-
- -- R.5.9. SFix >= signed
- function ">=" (L: SFix; R: signed) return boolean;
-
- -- R.5.10. signed >= SFix
- function ">=" (L: signed; R: SFix) return boolean;
-
- -- R.5.11. SFix >= integer
- function ">=" (L: SFix; R: integer) return boolean;
-
- -- R.5.12. integer >= SFix
- function ">=" (L: integer; R: SFix) return boolean;
-
-
- -------------------------------------------
- -- R.6. Binary "<=" less-or-equal operator
- -------------------------------------------
-
- -- R.6.1. UFix <= UFix
- function "<=" (L: UFix; R: UFix) return boolean;
-
- -- R.6.2. UFix <= unsigned
- function "<=" (L: UFix; R: unsigned) return boolean;
-
- -- R.6.3. unsigned <= UFix
- function "<=" (L: unsigned; R: UFix) return boolean;
-
- -- R.6.4. UFix <= integer
- function "<=" (L: UFix; R: integer) return boolean;
-
- -- R.6.5. integer <= UFix
- function "<=" (L: integer; R: UFix) return boolean;
-
- -- R.6.6. SFix <= SFix
- function "<=" (L: SFix; R: SFix) return boolean;
-
- -- R.6.7. SFix <= UFix
- function "<=" (L: SFix; R: UFix) return boolean;
-
- -- R.6.8. UFix <= SFix
- function "<=" (L: UFix; R: SFix) return boolean;
-
- -- R.6.9. SFix <= signed
- function "<=" (L: SFix; R: signed) return boolean;
-
- -- R.6.10. signed <= SFix
- function "<=" (L: signed; R: SFix) return boolean;
-
- -- R.6.11. SFix <= integer
- function "<=" (L: SFix; R: integer) return boolean;
-
- -- R.6.12. integer <= SFix
- function "<=" (L: integer; R: SFix) return boolean;
-
-
- ------------------------------------------------------------------
- -- C. Concatenation operators between fixed-point operands, and
- -- between fixed-point operands and other reasonable types.
- -- Unlike the implicitly defined "&" operator, they preserve
- -- place value and return an appropriately aligned subtype.
- -- Preservation of place value means that some concatenation
- -- operations are illegal. In particular, operations
- -- [SFix & SFix] and [UFix & SFix] are illegal, and
- -- the place values of operands in [SFix & UFix] and
- -- [UFix & UFix] must match up - the rightmost subscript of
- -- the left operand must be one higher than the leftmost
- -- subscript of the right operand.
- -- Single bits of type std_ulogic may be concatenated with
- -- fixed-point types where there is no risk of losing
- -- sign-extension information.
- -- Because of the way VHDL defines implicit concatenation,
- -- it is impossible to detect all these errors at compile time.
- -- Instead they are detected by assertion statements at run time.
- -- Tool vendors may choose to implement compile-time checks
- -- so that the run-time checking overhead can be avoided.
- ------------------------------------------------------------------
-
- -- C.1.1. UFix := UFix & UFix
- function "&" (L: UFix; R: UFix) return UFix;
-
- -- No need to define "&"[UFix, SFix] explicitly, because
- -- the types are incompatible and so there's no default
-
- -- C.1.2. UFix := UFix & std_ulogic
- function "&" (L: UFix; R: std_ulogic) return UFix;
-
- -- C.1.3. UFix := std_ulogic & UFix
- function "&" (L: std_ulogic; R: UFix) return UFix;
-
-
- -- C.2.1. SFix := SFix & UFix
- function "&" (L: SFix; R: UFix) return SFix;
-
- -- C.2.2. SFix := SFix & SFix -- ILLEGAL
- function "&" (L: SFix; R: SFix) return SFix;
-
- -- C.2.3. SFix := SFix & std_ulogic
- function "&" (L: SFix; R: std_ulogic) return SFix;
-
- -- C.2.4. SFix := std_ulogic & SFix
- function "&" (L: std_ulogic; R: SFix) return SFix;
-
-
-end; -- package fix_std;
diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd
deleted file mode 100644
index 695cd11..0000000
--- a/lib/fix_std/fix_stdb.vhd
+++ /dev/null
@@ -1,1910 +0,0 @@
----------------------------------------------------------------------
---
--- Package body fix_std
--- Fixed point arithmetic based on numeric_std
--- Compile using VHDL-93 (required to support 'ASCENDING
--- array attribute).
---
----------------------------------------------------------------------
---
--- This document describes a VHDL package of definitions and subprograms
--- intended to support the use of fixed-point arithmetic in test benches
--- and synthesisable designs. This document and the package it describes
--- are made freely available to the HDL design community without warranty
--- of any kind. You are welcome to make use of this information for your
--- own private study and in your own designs. If you make use of the
--- package, you accept sole responsibility for its fitness for purpose
--- and its suitability in your application. You are free to modify the
--- package in any way, and to record your contribution to it, but this
--- notice must appear in a prominent place in any modified or derived
--- version of the package or its supporting documentation.
---
--- The author wishes to thank his employer Doulos Ltd for making
--- available the facilities used to develop, test and distribute this
--- package. However, Doulos Ltd accepts no responsibility for the
--- package's contents and cannot support it in any way.
---
----------------------------------------------------------------------
--- Revision information:
---
--- Version 0.1 06-May-2003
--- Alpha version, for review
--- No division operators are provided, pending detailed
--- consultation on their functionality.
--- Some subprogram implementations are unnecessarily inefficient.
--- Version 0.2 11-Jun-2003
--- Fixes aiming to make the package portable across all synthesis tools:
--- * Removed deferred constants, made them package constants
--- * Removed all variable initialisations in procedures, made them
--- procedural initialisations in the code
--- * Fixed definition of extract functions to return just one bit
--- if their results would otherwise be null
----------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package body fix_std is
-
- --------------------------------------------------------------------
- -- DEFERRED CONSTANTS
- --------------------------------------------------------------------
- -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
- -- IMPLEMENTATIONS OR APPLICATIONS.
- --------------------------------------------------------------------
-
- -- Fixed-point offset, the bit number (subscript) used for
- -- the bit in a UFix or SFix vector having binary weight 2^0
- -- (the units bit).
- --
- -- constant FixP : Fix_Subscr := 100;
-
- -- Default values for overflow and rounding modes:
- --
- -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS;
- -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS;
-
- --------------------------------------------------------------------
- -- END OF DEFERRED CONSTANTS
- --------------------------------------------------------------------
-
- --------------------------------------------------------------------
- -- IMPLEMENTATION CONSTANTS
- --------------------------------------------------------------------
- -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC
- -- IMPLEMENTATIONS OR APPLICATIONS.
- --------------------------------------------------------------------
-
- -- Severity levels for various errors
-
- -- Concatenation errors - bad sign extension, discontiguous range etc
- -- These are only warnings - they just give the wrong answer.
- --
- constant concat_severity : severity_level := WARNING;
-
- -- Subtype direction errors - the present implementation can't
- -- handle fixed-point objects with ascending ranges. These messages
- -- are intended to give early warning of problems that would
- -- definitely cause other fatal errors at elaboration or run time.
- --
- constant direction_severity : severity_level := FAILURE;
-
- -- Assertion error message constants
-
- constant bad_direction_msg : string :=
- " has ascending range";
-
- constant concat_range_msg : string :=
- "Concatenation bounds should have contiguous ranges";
-
- constant concat_sxt_msg : string :=
- "Concatenation corrupts sign of result";
-
- constant concat_signLS_msg : string :=
- "RHS of concatenation should be unsigned";
-
- constant compare_meta_msg : string :=
- "Metavalue detected in FIX_STD comparison, returning FALSE";
-
- --------------------------------------------------------------------
- -- END OF IMPLEMENTATION CONSTANTS
- --------------------------------------------------------------------
-
- --------------------------------------------------------------------
- -- DO NOT MODIFY ANY CODE BELOW THIS POINT.
- --------------------------------------------------------------------
-
- -- Assumed bit width of INTEGER type in VHDL
- --
- constant INT_WIDTH : positive := 32;
-
- -- Single-bit zero values
- subtype Izero_UFixT is UFix(FixP downto FixP);
- subtype Izero_SFixT is SFix(FixP downto FixP);
- subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1);
- constant Izero_UFix: Izero_UFixT := "0";
- constant Izero_SFix: Izero_SFixT := "0";
- constant Fzero_UFix: Fzero_UFixT := "0";
-
- --------------------------------------------------------------------
- -- LOCAL PRIVATE SUBPROGRAMS
- --------------------------------------------------------------------
-
- -- Min, Max: Find minimum and maximum of two integers.
- -- Useful for determining appropriate range for operation results.
- --
- function Max(L, R: Fix_Subscr) return Fix_Subscr is
- begin
- if L>R then
- return L;
- else
- return R;
- end if;
- end;
- --
- function Min(L, R: Fix_Subscr) return Fix_Subscr is
- begin
- if L FixP then
- return Span(U);
- else
- return U(U'LEFT downto FixP);
- end if;
- end;
-
- -- E.2. Return the fractional part of a UFix value
- function Frac(U: UFix) return UFix is
- begin
- if U'LEFT < FixP-1 then
- return Span(U);
- elsif U'RIGHT >= FixP then
- return Fzero_UFix;
- else
- return U(FixP-1 downto U'RIGHT);
- end if;
- end;
-
- -- E.3. Return the integral part of a SFix value
- function Int(S: SFix) return SFix is
- begin
- if S'LENGTH = 0 then
- return Izero_SFix;
- elsif S'LEFT <= FixP then
- return SFix'(FixP => S(S'LEFT));
- elsif S'RIGHT > FixP then
- return Span(S);
- else
- return S(S'LEFT downto FixP);
- end if;
- end;
-
- -- E.4. Return the fractional part of a SFix value
- function Frac(S: SFix) return UFix is
- variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
- begin
- if S'LEFT < FixP then
- for I in FixP-1 downto S'LEFT+1 loop
- P(I) := S(S'LEFT);
- end loop;
- P(S'RANGE) := S;
- return UFix(S(FixP-1 downto S'RIGHT));
- elsif S'RIGHT >= FixP then
- return Fzero_UFix;
- else
- return UFix(S(FixP-1 downto S'RIGHT));
- end if;
- end;
-
- -- E.5. Widen a SFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(S: SFix) return SFix is
- variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP));
- begin
- F(S'RANGE) := S;
- for I in F'LEFT downto S'LEFT+1 loop
- F(I) := S(S'LEFT);
- end loop;
- for I in S'RIGHT-1 downto F'RIGHT loop
- F(I) := '0';
- end loop;
- return F;
- end;
-
- -- E.6. Widen a UFix value if necessary so that
- -- its range adjoins or spans the binary point
- function Span(U: UFix) return UFix is
- variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP));
- begin
- F(U'RANGE) := U;
- for I in F'LEFT downto U'LEFT+1 loop
- F(I) := '0';
- end loop;
- for I in U'RIGHT-1 downto F'RIGHT loop
- F(I) := '0';
- end loop;
- return F;
- end;
-
- ---------------------------
- -- T. Conversion functions
- ---------------------------
-
- -- T.1 to T.8: Unsigned conversions
-
- -- T.1. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.2. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_UFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.3. Conversion from integer to UFix. Provide number of
- -- integer bits and number of fraction bits. Note that
- -- negative input is tolerated!
- --
- function to_UFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.4. Conversion from unsigned to UFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting UFix.
- --
- function to_UFix(
- N : unsigned;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return UFix is
- variable F: UFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.5. Conversion from unsigned to UFix. Automatically set the
- -- range of the resulting UFix to match the unsigned value,
- -- as an integral UFix value with no fraction bits.
- --
- function to_UFix( N : unsigned ) return UFix is
- variable F: UFix(FixP+N'LENGTH-1 downto FixP);
- begin
- F := UFix(N);
- return F;
- end;
-
- -- T.6. Conversion from UFix to unsigned. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_unsigned(
- N : UFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned is
- variable F_UFix: UFix(N'LEFT downto FixP);
- variable F: unsigned(F_UFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_UFix, N, rounding=>rounding);
- F := unsigned(F_UFix);
- return F;
- end;
-
- -- T.7. Conversion from UFix to unsigned. Caller specifies
- -- required number of bits in unsigned result.
- --
- function to_unsigned(
- N : UFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return unsigned is
- variable F_UFix: UFix(FixP+bits-1 downto FixP);
- variable F: unsigned(F_UFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_UFix, N, overflow, rounding);
- F := unsigned(F_UFix);
- return F;
- end;
-
- -- T.8. Conversion from UFix to integer. Up to 31 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer is
- variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP);
- begin
- Copy_V(F_UFix, N, overflow, rounding);
- return to_integer(unsigned(F_UFix));
- end;
-
- -- T.9 to T.16: Signed conversions
-
- -- T.9. Resizing an existing UFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : UFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.10. Resizing an existing SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : SFix;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.11. Conversion from integer to SFix. Provide number of
- -- integer bits and number of fraction bits.
- --
- function to_SFix(
- N : integer;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.12. Conversion from signed to SFix. Provide subscripts of
- -- MS and (optionally) LS bit of the resulting SFix.
- --
- function to_SFix(
- N : signed;
- MSB_index : Fix_Subscr;
- LSB_index : Fix_Subscr := FixP;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return SFix is
- variable F: SFix(MSB_index downto LSB_index);
- begin
- Copy_V(F, N, overflow, rounding);
- return F;
- end;
-
- -- T.13. Conversion from signed to SFix. Automatically set the
- -- range of the resulting SFix to match the signed value,
- -- as an integral SFix value with no fraction bits.
- --
- function to_SFix( N : signed ) return SFix is
- variable F: SFix(FixP+N'LENGTH-1 downto FixP);
- begin
- F := SFix(N);
- return F;
- end;
-
- -- T.14. Conversion from SFix to signed. All integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_signed(
- N : SFix;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed is
- variable F_SFix: SFix(N'LEFT downto FixP);
- variable F: signed(F_SFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_SFix, N, rounding=>rounding);
- F := signed(F_SFix);
- return F;
- end;
-
- -- T.15. Conversion from SFix to signed. Caller specifies
- -- required number of bits in signed result.
- --
- function to_signed(
- N : SFix;
- bits : positive;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return signed is
- variable F_SFix: UFix(FixP+bits-1 downto FixP);
- variable F: signed(F_SFix'LENGTH-1 downto 0);
- begin
- Copy_V(F_SFix, N, overflow, rounding);
- F := signed(F_SFix);
- return F;
- end;
-
- -- T.16. Conversion from SFix to integer. Up to 32 integer bits are
- -- preserved (including adding LS scale bits if necessary).
- --
- function to_integer(
- N : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) return integer is
- variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP);
- begin
- Copy_V(F_SFix, N, overflow, rounding);
- return to_integer(signed(F_SFix));
- end;
-
- -- T.17. Conversion from UFix to SFix. This simply adds
- -- an extra more significant bit, set to zero.
- --
- function to_SFix(U: UFix) return SFix is
- variable F: SFix(U'LEFT+1 downto U'RIGHT);
- begin
- F := SFix('0' & U);
- return F;
- end;
-
-
- ----------------------------------
- -- V. Copy-to-variable procedures
- ----------------------------------
-
- -- Range-aware copying of an expression into a variable. The
- -- ranges of destination variable and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- V.1 to V.5: Copy an expression into a UFix variable
-
- -- V.1. Copy UFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- subtype target_T is UFix(target'RANGE);
- variable W: UFix(Max(target'LEFT, source'LEFT+1) downto
- Min(target'RIGHT, source'RIGHT));
- constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0');
- begin
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- W := (others => '0');
- W(source'RANGE) := source;
- if target'RIGHT > source'RIGHT then
- case rounding is
- when clip_LS | towards_zero =>
- null;
- when to_nearest =>
- W(W'LEFT downto target'RIGHT-1) := UFix(
- unsigned(W(W'LEFT downto target'RIGHT-1)) + 1
- );
- end case;
- end if;
- target := W(target'RANGE);
- if HighZero'LENGTH > 0 then
- if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then
- case overflow is
- when clip_MS =>
- null;
- when saturate =>
- target := target_T'(others => '1');
- end case;
- end if;
- end if;
- end;
-
- -- V.2. Copy SFix to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT);
- constant target_zero: UFix(target'RANGE) := (others => '0');
- begin
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- W := (others => '0');
- -- Rounding & sign-extend
- Copy_V(W, source, clip_MS, rounding);
- -- Saturation?
- if W < 0 and overflow = saturate then
- target := target_zero;
- else
- Copy_V(target, UFix(W), overflow, clip_LS);
- end if;
- end;
-
- -- V.3. Copy UNSIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source);
- begin
- Copy_V(target, U, overflow, rounding);
- end;
-
- -- V.4. Copy SIGNED to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.5. Copy integer to UFix
- --
- procedure Copy_V(
- target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant N: signed(FixP+INT_WIDTH-1 downto FixP)
- := to_signed(source, INT_WIDTH);
- begin
- -- Cop-out, this is very inefficient, but will do for now.
- Copy_V(target, N, overflow, rounding);
- end;
-
- -- V.6 to V.10: Copy an expression into a SFix variable
-
- -- V.6. Copy UFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.7. Copy SFix to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- subtype target_T is SFix(target'RANGE);
- variable W: SFix(Max(target'LEFT, source'LEFT+1) downto
- Min(target'RIGHT, source'RIGHT));
- variable HighSX: SFix(W'LEFT downto target'LEFT+1);
- begin
- for i in HighSX'RANGE loop
- HighSX(i) := source(source'LEFT);
- end loop;
- assert not target'ASCENDING
- report "target" & bad_direction_msg
- severity direction_severity;
- assert not source'ASCENDING
- report "source" & bad_direction_msg
- severity direction_severity;
- -- Make W a copy of source, duly extended at both ends
- W := (others => '0');
- W(source'RANGE) := source;
- W(HighSX'RANGE) := HighSX;
- -- Do any rounding required
- if target'RIGHT > source'RIGHT then
- case rounding is
- when clip_LS =>
- null;
- when towards_zero =>
- if
- (to_UX01(W(W'LEFT)) = '1') -- it's negative?
- and
- (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up?
- then
- W(W'LEFT downto target'RIGHT) := SFix(
- signed(W(W'LEFT downto target'RIGHT)) + 1
- );
- end if;
- when to_nearest =>
- W(W'LEFT downto target'RIGHT-1) := SFix(
- signed(W(W'LEFT downto target'RIGHT-1)) + 1
- );
- end case;
- end if;
- -- Do any overflow required
- target := W(target'RANGE);
- if HighSX'LENGTH > 0 then
- if signed(W(HighSX'RANGE)) /= signed(HighSX) then
- case overflow is
- when clip_MS =>
- null;
- when saturate =>
- target := Target_T'(others => not W(W'LEFT));
- target(target'LEFT) := W(W'LEFT);
- end case;
- end if;
- end if;
- end;
-
- -- V.8. Copy UNSIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.9. Copy SIGNED to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source);
- begin
- Copy_V(target, S, overflow, rounding);
- end;
-
- -- V.10. Copy integer to SFix
- --
- procedure Copy_V(
- target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- constant N: signed(FixP+INT_WIDTH-1 downto FixP)
- := to_signed(source, INT_WIDTH);
- begin
- -- Cop-out, this is very inefficient, but will do for now.
- Copy_V(target, N, overflow, rounding);
- end;
-
-
- --------------------------------
- -- S. Copy-to-signal procedures
- --------------------------------
- --
- -- Range-aware copying of an expression into a signal. The
- -- ranges of destination signal and source expression are
- -- used to determine correct rounding, overflow and scaling
- -- behaviour.
-
- -- S.1 to S.5: Copy an expression into a UFix signal
- --
-
- -- S.1. Copy UFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.1. Copy SFix to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.3. Copy UNSIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.4. Copy SIGNED to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.5. Copy integer to UFix
- --
- procedure Copy_S(
- signal target : out UFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: UFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.6 to S.10: Copy an expression into a SFix signal
- --
-
- -- S.6. Copy UFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : UFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.7. Copy SFix to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : SFix;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.8. Copy UNSIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : unsigned;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.9. Copy SIGNED to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : signed;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
- -- S.10. Copy integer to SFix
- --
- procedure Copy_S(
- signal target : out SFix;
- source : integer;
- overflow : Fix_Overflow_Mode := Fix_Default_Overflow;
- rounding : Fix_Rounding_Mode := Fix_Default_Rounding
- ) is
- variable V: SFix(target'RANGE);
- begin
- Copy_V(V, source, overflow, rounding);
- target <= V;
- end;
-
-
- ------------------------------------------------------------------
- -- A. Arithmetic operations involving UFix, SFix and other
- -- numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- --
- -- IMPORTANT NOTE:
- -- Arithmetic operators return a result that is wide enough
- -- and precise enough so that no information is lost. THIS IS
- -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std.
- -- In the detailed description that follow, "scaling" means
- -- the numerical value (weight) of the least significant bit
- -- in a fixed-point value.
- --
- -- ADDITION returns a result whose least significant bit
- -- is the same as the least significant bit in either operand,
- -- and whose most significant bit is one position higher than
- -- the most significant bit in either operand. Addition of
- -- two operands having the same bounds therefore results in
- -- a growth of one bit at the most significant end. Addition
- -- of an integer to a UFix or SFix is accomplished by first
- -- converting the integer to the same subtype as the other
- -- operand, thereby giving rise to one-bit growth; default
- -- truncation and rounding modes are used for the conversion.
- --
- -- SUBTRACTION where one or both operands are signed behaves
- -- in the same way as addition. Subtraction where both operands
- -- are unsigned returns a result whose most significant bit
- -- position is the same as the most significant bit in either
- -- operand, and whose least significant bit is the same as the
- -- least significant bit in either operand.
- --
- -- MULTIPLICATION returns a result whose width is the sum of
- -- the widths of its two operands, and whose scaling is the
- -- product of its two operands' scalings.
- --
- -- UNARY NEGATION always gives a result having one more
- -- significant bit than the operand.
- --
- -- ABSOLUTE VALUE always gives a result having exactly the
- -- same subtype as its operand.
- --
- -- In binary operations where one operand is a fixed-point type
- -- and the other is an integer numeric type, the integer operand
- -- is first converted to a fixed-point type of the same subtype
- -- as the other operand using Copy_V with default rounding and
- -- overflow modes. The operation is then performed between two
- -- fixed-point operands in the normal way.
- --
- ------------------------------------------------------------------
-
-
- ------------------------------------
- -- A.1. Unary "-" negation operator
- ------------------------------------
-
- -- A.1.1. SFix := - UFix
- function "-" (R: UFix) return SFix is
- variable F: SFix(R'LEFT+1 downto R'RIGHT);
- begin
- F := SFix(-(signed('0' & R)));
- return F;
- end;
-
- -- A.1.2. SFix := - SFix
- function "-" (R: SFix) return SFix is
- variable F: SFix(R'LEFT+1 downto R'RIGHT);
- begin
- F := SFix(-(signed(R(R'LEFT) & R)));
- return F;
- end;
-
-
- --------------------------------------------
- -- A.2. Unary "abs" absolute-value operator
- --------------------------------------------
-
- -- A.2.1. SFix := abs SFix
- function "abs" (R: SFix) return SFix is
- variable F: SFix(R'RANGE);
- begin
- F := R;
- if to_X01(R(R'LEFT)) = '1' then
- F := SFix(-(signed(R)));
- end if;
- return F;
- end;
-
-
- -------------------------------------
- -- A.3. Binary "+" addition operator
- -------------------------------------
-
- -- A.3.1. UFix := UFix + UFix
- function "+" (L: UFix; R: UFix) return UFix is
- variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
- variable LU, RU: unsigned(F'RANGE);
- begin
- LU := (others => '0');
- RU := (others => '0');
- LU(L'RANGE) := unsigned(L);
- RU(R'RANGE) := unsigned(R);
- F := UFix(LU + RU);
- return F;
- end;
-
- -- A.3.2. UFix := UFix + unsigned
- function "+" (L: UFix; R: unsigned) return UFix is
- begin
- return L + to_UFix(R);
- end;
-
- -- A.3.3. UFix := unsigned + UFix
- function "+" (L: unsigned; R: UFix) return UFix is
- begin
- return R+L;
- end;
-
- -- A.3.4. UFix := UFix + natural
- function "+" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L + R_fp;
- end;
-
- -- A.3.5. UFix := natural + UFix
- function "+" (L: natural; R: UFix) return UFix is
- begin
- return R+L;
- end;
-
- -- A.3.6. SFix := SFix + SFix
- function "+" (L: SFix; R: SFix) return SFix is
- variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right));
- variable LS, RS: signed(F'RANGE);
- begin
- LS := (others => '0');
- RS := (others => '0');
- LS(L'RANGE) := signed(L);
- RS(R'RANGE) := signed(R);
- for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop;
- for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop;
- F := SFix(LS + RS);
- return F;
- end;
-
- -- A.3.7. SFix := SFix + UFix
- function "+" (L: SFix; R: UFix) return SFix is
- begin
- return L + SFix('0' & R);
- end;
-
- -- A.3.8. SFix := UFix + SFix
- function "+" (L: UFix; R: SFix) return SFix is
- begin
- return SFix('0' & L) + R;
- end;
-
- -- A.3.9. SFix := SFix + signed
- function "+" (L: SFix; R: signed) return SFix is
- begin
- return L + to_SFix(R);
- end;
-
- -- A.3.10. SFix := signed + SFix
- function "+" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) + R;
- end;
-
- -- A.3.11. SFix := SFix + integer
- function "+" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L + R_fp;
- end;
-
- -- A.3.12. SFix := integer + SFix
- function "+" (L: integer; R: SFix) return SFix is
- begin
- return R + L;
- end;
-
-
- ----------------------------------------
- -- A.4. Binary "-" subtraction operator
- ----------------------------------------
- --
- -- NOTE: There is a special problem with subtraction
- -- operators that return a UFix result if that result
- -- goes negative. Our arbitrary decision is that we
- -- truncate most-significant bits in this case. If you
- -- wish to avoid the risk of this arbitrarily-defined
- -- truncation behaviour, change one or more of your
- -- operands to SFix and get a SFix result using this
- -- idiom:
- -- SFix := UFix + (-UFix)
- -- or copy one of the UFix operands into a SFix that's
- -- one bit wider, before performing the operation.
- --
- -- Subtractions returning a UFix result take unsigned
- -- operands and do not exhibit bit growth.
- -- Subtractions returning a SFix result take signed or
- -- unsigned operands and exhibit one-bit growth like addition.
-
- -- A.4.1. UFix := UFix - UFix
- function "-" (L: UFix; R: UFix) return UFix is
- variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := L;
- RW(R'RANGE) := R;
- F := UFix(unsigned(LW) - unsigned(RW));
- return F;
- end;
-
- -- A.4.2. UFix := UFix - unsigned
- function "-" (L: UFix; R: unsigned) return UFix is
- begin
- return L - to_UFix(R);
- end;
-
- -- A.4.3. UFix := unsigned - UFix
- function "-" (L: unsigned; R: UFix) return UFix is
- begin
- return to_UFix(L) - R;
- end;
-
- -- A.4.4. UFix := UFix - integer
- function "-" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L - R_fp;
- end;
-
- -- A.4.5. UFix := natural - UFix
- function "-" (L: natural; R: UFix) return UFix is
- variable L_fp: UFix(R'RANGE);
- begin
- Copy_V(L_fp, L);
- return L_fp - R;
- end;
-
- -- A.4.6. SFix := SFix - SFix
- function "-" (L: SFix; R: SFix) return SFix is
- begin
- return L + (-R);
- end;
-
- -- A.4.7. SFix := SFix - UFix
- function "-" (L: SFix; R: UFix) return SFix is
- begin
- return L + (-R);
- end;
-
- -- A.4.8. SFix := UFix - SFix
- function "-" (L: UFix; R: SFix) return SFix is
- begin
- return To_SFix(L) - R;
- end;
-
- -- A.4.9. SFix := SFix - signed
- function "-" (L: SFix; R: signed) return SFix is
- begin
- return L - to_SFix(R);
- end;
-
- -- A.4.10. SFix := signed - SFix
- function "-" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) - R;
- end;
-
- -- A.4.11. SFix := SFix - integer
- function "-" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L - R_fp;
- end;
-
- -- A.4.12. SFix := integer - SFix
- function "-" (L: integer; R: SFix) return SFix is
- variable L_fp: SFix(R'RANGE);
- begin
- Copy_V(L_fp, L);
- return L_fp - R;
- end;
-
-
- -------------------------------------------
- -- A.5. Binary "*" multiplication operator
- -------------------------------------------
-
- -- A.5.1. UFix := UFix * UFix
- function "*" (L: UFix; R: UFix) return UFix is
- variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- begin
- F := UFix(unsigned(L) * unsigned(R));
- return F;
- end;
-
- -- A.5.2. UFix := UFix * unsigned
- function "*" (L: UFix; R: unsigned) return UFix is
- begin
- return L * to_UFix(R);
- end;
-
- -- A.5.3. UFix := unsigned * UFix
- function "*" (L: unsigned; R: UFix) return UFix is
- begin
- return to_UFix(L) * R;
- end;
-
- -- A.5.4. UFix := UFix * natural
- function "*" (L: UFix; R: natural) return UFix is
- variable R_fp: UFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L * R_fp;
- end;
-
- -- A.5.5. UFix := natural * UFix
- function "*" (L: natural; R: UFix) return UFix is
- begin
- return R * L;
- end;
-
- -- A.5.6. SFix := SFix * SFix
- function "*" (L: SFix; R: SFix) return SFix is
- variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- begin
- F := SFix(signed(L) * signed(R));
- return F;
- end;
-
- -- A.5.7. SFix := SFix * UFix
- function "*" (L: SFix; R: UFix) return SFix is
- constant RS: SFix := SFix('0' & R);
- variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP);
- variable FW: SFix(F'LEFT+1 downto F'RIGHT);
- begin
- FW := SFix(signed(L) * signed(RS));
- Copy_V(F, FW); -- never overflows
- return F;
- end;
-
- -- A.5.8. SFix := UFix * SFix
- function "*" (L: UFix; R: SFix) return SFix is
- begin
- return R * L;
- end;
-
- -- A.5.9. SFix := SFix * signed
- function "*" (L: SFix; R: signed) return SFix is
- begin
- return L * to_SFix(R);
- end;
-
- -- A.5.10. SFix := signed * SFix
- function "*" (L: signed; R: SFix) return SFix is
- begin
- return to_SFix(L) * R;
- end;
-
- -- A.5.11. SFix := SFix * integer
- function "*" (L: SFix; R: integer) return SFix is
- variable R_fp: SFix(L'RANGE);
- begin
- Copy_V(R_fp, R);
- return L * R_fp;
- end;
-
- -- A.5.12. SFix := integer * SFix
- function "*" (L: integer; R: SFix) return SFix is
- begin
- return R * L;
- end;
-
-
- ------------------------------------------------------------------
- -- R. Relational operators - arithmetic comparisons involving
- -- UFix, SFix and other numeric types.
- -- The operators are overloaded for most of the sensible
- -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER.
- -- Note that in all cases comparisons are exact; if one
- -- operand has more fraction bits than the other, the less
- -- precise operand will have its LSBs zero-extended, and
- -- these zero bits will take part in comparison with whatever
- -- LSBs exist in the more precise operand.
- --
- -- Our implementation is based on only two operators, "=" and "<".
- -- All other operators are derived from these two, either by
- -- logical inversion of the result or by swapping operands.
- ------------------------------------------------------------------
-
- -------------------------------------
- -- R.1. Binary "=" equality operator
- -------------------------------------
-
- -- R.1.1. UFix = UFix
- function "=" (L: UFix; R: UFix) return boolean is
- variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := L;
- RW(R'RANGE) := R;
- return unsigned(LW) = unsigned(RW);
- end;
-
- -- R.1.2. UFix = unsigned
- function "=" (L: UFix; R: unsigned) return boolean is
- begin
- return L = to_UFix(R);
- end;
-
- -- R.1.3. unsigned = UFix
- function "=" (L: unsigned; R: UFix) return boolean is
- begin
- return to_UFix(L) = R;
- end;
-
- -- R.1.4. UFix = integer
- function "=" (L: UFix; R: integer) return boolean is
- variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(RS, R, clip_MS, clip_LS);
- return To_SFix(L) = RS;
- end;
-
- -- R.1.5. integer = UFix
- function "=" (L: integer; R: UFix) return boolean is
- begin
- return R = L;
- end;
-
- -- R.1.6. SFix = SFix
- function "=" (L: SFix; R: SFix) return boolean is
- variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT));
- begin
- -- clip modes are OK because we aren't losing any bits
- Copy_V(LW, L, clip_MS, clip_LS);
- Copy_V(RW, R, clip_MS, clip_LS);
- return signed(LW) = signed(RW);
- end;
-
- -- R.1.7. SFix = UFix
- function "=" (L: SFix; R: UFix) return boolean is
- begin
- return L = To_SFix(R);
- end;
-
- -- R.1.8. UFix = SFix
- function "=" (L: UFix; R: SFix) return boolean is
- begin
- return R = L;
- end;
-
- -- R.1.9. SFix = signed
- function "=" (L: SFix; R: signed) return boolean is
- begin
- return L = to_SFix(R);
- end;
-
- -- R.1.10. signed = SFix
- function "=" (L: signed; R: SFix) return boolean is
- begin
- return to_SFix(L) = R;
- end;
-
- -- R.1.11. SFix = integer
- function "=" (L: SFix; R: integer) return boolean is
- variable RS: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(RS, R, clip_MS, clip_LS);
- return L = RS;
- end;
-
- -- R.1.12. integer = SFix
- function "=" (L: integer; R: SFix) return boolean is
- begin
- return R = L;
- end;
-
-
- --------------------------------------
- -- R.2. Binary "<" less-than operator
- --------------------------------------
-
- -- R.2.1. UFix < UFix
- function "<" (L: UFix; R: UFix) return boolean is
- variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- LW := (others => '0');
- RW := (others => '0');
- LW(L'RANGE) := unsigned(L);
- RW(R'RANGE) := unsigned(R);
- return unsigned(LW) < unsigned(RW);
- end;
-
- -- R.2.2. UFix < unsigned
- function "<" (L: UFix; R: unsigned) return boolean is
- begin
- return L < To_UFix(R);
- end;
-
- -- R.2.3. unsigned < UFix
- function "<" (L: unsigned; R: UFix) return boolean is
- begin
- return To_UFix(L) < R;
- end;
-
- -- R.2.4. UFix < integer
- function "<" (L: UFix; R: integer) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, R, clip_MS, clip_LS);
- return L < S;
- end;
-
- -- R.2.5. integer < UFix
- function "<" (L: integer; R: UFix) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, L, clip_MS, clip_LS);
- return S < R;
- end;
-
- -- R.2.6. SFix < SFix
- function "<" (L: SFix; R: SFix) return boolean is
- variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto
- Min(L'RIGHT, R'RIGHT));
- begin
- Copy_V(LW, L, clip_MS, clip_LS);
- Copy_V(RW, R, clip_MS, clip_LS);
- return signed(LW) < signed(RW);
- end;
-
- -- R.2.7. SFix < UFix
- function "<" (L: SFix; R: UFix) return boolean is
- begin
- return L < To_SFix(R);
- end;
-
- -- R.2.8. UFix < SFix
- function "<" (L: UFix; R: SFix) return boolean is
- begin
- return To_SFix(L) < R;
- end;
-
- -- R.2.9. SFix < signed
- function "<" (L: SFix; R: signed) return boolean is
- begin
- return L < To_SFix(R);
- end;
-
- -- R.2.10. signed < SFix
- function "<" (L: signed; R: SFix) return boolean is
- begin
- return To_SFix(L) < R;
- end;
-
- -- R.2.11. SFix < integer
- function "<" (L: SFix; R: integer) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, R, clip_MS, clip_LS);
- return L < S;
- end;
-
- -- R.2.12. integer < SFix
- function "<" (L: integer; R: SFix) return boolean is
- variable S: SFix(FixP+INT_WIDTH-1 downto FixP);
- begin
- Copy_V(S, L, clip_MS, clip_LS);
- return S < R;
- end;
-
-
- ----------------------------------------
- -- R.3. Binary "/=" inequality operator
- ----------------------------------------
-
- -- R.3.1. UFix /= UFix
- function "/=" (L: UFix; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.2. UFix /= unsigned
- function "/=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.3. unsigned /= UFix
- function "/=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.4. UFix /= integer
- function "/=" (L: UFix; R: integer) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.5. integer /= UFix
- function "/=" (L: integer; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.6. SFix /= SFix
- function "/=" (L: SFix; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.7. SFix /= UFix
- function "/=" (L: SFix; R: UFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.8. UFix /= SFix
- function "/=" (L: UFix; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.9. SFix /= signed
- function "/=" (L: SFix; R: signed) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.10. signed /= SFix
- function "/=" (L: signed; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.11. SFix /= integer
- function "/=" (L: SFix; R: integer) return boolean is
- begin
- return not (L = R);
- end;
-
- -- R.3.12. integer /= SFix
- function "/=" (L: integer; R: SFix) return boolean is
- begin
- return not (L = R);
- end;
-
-
- -----------------------------------------
- -- R.4. Binary ">" greater-than operator
- -----------------------------------------
-
- -- R.4.1. UFix > UFix
- function ">" (L: UFix; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.2. UFix > unsigned
- function ">" (L: UFix; R: unsigned) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.3. unsigned > UFix
- function ">" (L: unsigned; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.4. UFix > integer
- function ">" (L: UFix; R: integer) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.5. integer > UFix
- function ">" (L: integer; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.6. SFix > SFix
- function ">" (L: SFix; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.7. SFix > UFix
- function ">" (L: SFix; R: UFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.8. UFix > SFix
- function ">" (L: UFix; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.9. SFix > signed
- function ">" (L: SFix; R: signed) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.10. signed > SFix
- function ">" (L: signed; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.11. SFix > integer
- function ">" (L: SFix; R: integer) return boolean is
- begin
- return R < L;
- end;
-
- -- R.4.12. integer > SFix
- function ">" (L: integer; R: SFix) return boolean is
- begin
- return R < L;
- end;
-
-
- ----------------------------------------------
- -- R.5. Binary ">=" greater-or-equal operator
- ----------------------------------------------
-
- -- R.5.1. UFix >= UFix
- function ">=" (L: UFix; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.2. UFix >= unsigned
- function ">=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.3. unsigned >= UFix
- function ">=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.4. UFix >= integer
- function ">=" (L: UFix; R: integer) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.5. integer >= UFix
- function ">=" (L: integer; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.6. SFix >= SFix
- function ">=" (L: SFix; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.7. SFix >= UFix
- function ">=" (L: SFix; R: UFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.8. UFix >= SFix
- function ">=" (L: UFix; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.9. SFix >= signed
- function ">=" (L: SFix; R: signed) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.10. signed >= SFix
- function ">=" (L: signed; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.11. SFix >= integer
- function ">=" (L: SFix; R: integer) return boolean is
- begin
- return not (L < R);
- end;
-
- -- R.5.12. integer >= SFix
- function ">=" (L: integer; R: SFix) return boolean is
- begin
- return not (L < R);
- end;
-
-
- -------------------------------------------
- -- R.6. Binary "<=" less-or-equal operator
- -------------------------------------------
-
- -- R.6.1. UFix <= UFix
- function "<=" (L: UFix; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.2. UFix <= unsigned
- function "<=" (L: UFix; R: unsigned) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.3. unsigned <= UFix
- function "<=" (L: unsigned; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.4. UFix <= integer
- function "<=" (L: UFix; R: integer) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.5. integer <= UFix
- function "<=" (L: integer; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.6. SFix <= SFix
- function "<=" (L: SFix; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.7. SFix <= UFix
- function "<=" (L: SFix; R: UFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.8. UFix <= SFix
- function "<=" (L: UFix; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.9. SFix <= signed
- function "<=" (L: SFix; R: signed) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.10. signed <= SFix
- function "<=" (L: signed; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.11. SFix <= integer
- function "<=" (L: SFix; R: integer) return boolean is
- begin
- return not (R < L);
- end;
-
- -- R.6.12. integer <= SFix
- function "<=" (L: integer; R: SFix) return boolean is
- begin
- return not (R < L);
- end;
-
- ------------------------------------------------------------------
- -- C. Concatenation operators between fixed-point operands, and
- -- between fixed-point operands and other reasonable types.
- -- Unlike the implicitly defined "&" operator, they preserve
- -- place value and return an appropriately aligned subtype.
- -- Preservation of place value means that some concatenation
- -- operations are illegal. In particular, operations
- -- [SFix & SFix] and [UFix & SFix] are illegal, and
- -- the place values of operands in [SFix & UFix] and
- -- [UFix & UFix] must match up - the rightmost subscript of
- -- the left operand must be one higher than the leftmost
- -- subscript of the right operand.
- -- Single bits of type std_ulogic may be concatenated with
- -- fixed-point types where there is no risk of losing
- -- sign-extension information.
- -- Because of the way VHDL defines implicit concatenation,
- -- it is impossible to detect all these errors at compile time.
- -- Instead they are detected by assertion statements at run time.
- -- Tool vendors may choose to implement compile-time checks
- -- so that the run-time checking overhead can be avoided.
- ------------------------------------------------------------------
-
- -- C.1.1. UFix := UFix & UFix
- function "&" (L: UFix; R: UFix) return UFix is
- begin
- return UFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.1.2. UFix := UFix & std_ulogic
- function "&" (L: UFix; R: std_ulogic) return UFix is
- begin
- return UFix(concat(std_logic_vector(L), R));
- end;
-
- -- C.1.3. UFix := std_ulogic & UFix
- function "&" (L: std_ulogic; R: UFix) return UFix is
- begin
- return UFix(concat(L, std_logic_vector(R)));
- end;
-
-
- -- C.2.1. SFix := SFix & UFix
- function "&" (L: SFix; R: UFix) return SFix is
- begin
- return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.2.2. SFix := SFix & SFix -- ILLEGAL
- function "&" (L: SFix; R: SFix) return SFix is
- begin
- report concat_signLS_msg
- severity concat_severity;
- return SFix(concat(std_logic_vector(L), std_logic_vector(R)));
- end;
-
- -- C.2.3. SFix := SFix & std_ulogic
- function "&" (L: SFix; R: std_ulogic) return SFix is
- begin
- return SFix(concat(std_logic_vector(L), R));
- end;
-
- -- C.2.4. SFix := std_ulogic & SFix
- function "&" (L: std_ulogic; R: SFix) return SFix is
- begin
- assert std_match(L, R(R'LEFT))
- report concat_sxt_msg
- severity concat_severity;
- return SFix(concat(L, std_logic_vector(R)));
- end;
-
-
-end; -- package body fix_std;
diff --git a/lib/fixed/fixed_util_pkg.vhd b/lib/fixed/fixed_util_pkg.vhd
deleted file mode 100644
index 584f186..0000000
--- a/lib/fixed/fixed_util_pkg.vhd
+++ /dev/null
@@ -1,159 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use IEEE.MATH_REAL.ALL;
-
-library ieee_proposed;
-use ieee_proposed.math_utility_pkg.all;
-use ieee_proposed.fixed_pkg.all;
-
-package fixed_util_pkg is
-
- -------------------------------------------------------------
- -- Frequently used constants
- constant pi : real := 3.141592653589793e+000;
- constant sqrt2 : real := 1.414213562373095e+000;
- constant sqrt2_inv : real := 7.071067811865475e-001;
-
- -- Constructor helpers
- -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range);
- function uproto (nbits : integer; nbits_frac : integer) return ufixed;
-
- -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range);
- function sproto (nbits : integer; nbits_frac : integer) return sfixed;
-
- -- Safe variant of uproto
- function uhi (nbits : integer; nbits_frac : integer) return integer;
- function ulo (nbits : integer; nbits_frac : integer) return integer;
-
- -- Safe variant of sproto
- function shi (nbits : integer; nbits_frac : integer) return integer;
- function slo (nbits : integer; nbits_frac : integer) return integer;
-
- function to_unsigned (src : ufixed) return UNSIGNED;
- function to_signed (src : sfixed) return SIGNED;
-
- type real_array_t is array (natural range <>) of real;
- type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
- type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
- function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t;
- function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t;
-
- -- Slicing functions for unconstrained array types
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed;
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed;
-
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
-
-package body fixed_util_pkg is
-
- -------------------------------------------------------------
- -- Constuctor helpers
- function uproto (nbits : integer; nbits_frac : integer) return ufixed is
- constant result : ufixed (uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac)) := (others => '0');
- begin
- return result(uhi(nbits,nbits_frac) downto ulo(nbits,nbits_frac));
- end uproto;
-
- -------------------------------------------------------------
- function sproto (nbits : integer; nbits_frac : integer) return sfixed is
- constant result : sfixed (shi(nbits,nbits_frac) downto slo(nbits,nbits_frac)) := (others => '0');
- begin
- return result(shi(nbits,nbits_frac) downto slo(nbits,nbits_frac));
- end sproto;
-
- -------------------------------------------------------------
- function uhi (nbits : integer; nbits_frac : integer) return integer is
- begin
- return nbits-nbits_frac-1;
- end uhi;
-
- -------------------------------------------------------------
- function ulo (nbits : integer; nbits_frac : integer) return integer is
- begin
- return -nbits_frac;
- end ulo;
-
- -------------------------------------------------------------
- function shi (nbits : integer; nbits_frac : integer) return integer is
- begin
- return nbits-nbits_frac;
- end shi;
-
- -------------------------------------------------------------
- function slo (nbits : integer; nbits_frac : integer) return integer is
- begin
- return -nbits_frac+1;
- end slo;
-
- -------------------------------------------------------------
- function to_unsigned (src : ufixed) return UNSIGNED is
- subtype t is UNSIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return UNSIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_unsigned;
-
- -------------------------------------------------------------
- function to_signed (src : sfixed) return SIGNED is
- subtype t is SIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return SIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_signed;
-
- function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is
- variable res : sfixed_array_t(0 to x'length-1, proto'range);
- variable tt : sfixed(proto'range);
- begin
- for i in x'range loop
- tt := to_sfixed(x(i), proto);
- for j in proto'range loop
- res(i,j) := tt(j);
- end loop;
- end loop;
- return res;
- end to_sfixed_array;
-
- ---------------------------------------------------------------------------
- function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is
- variable p : sfixed(shi(nbits, nbits_int) downto slo(nbits, nbits_int));
- begin
- return to_sfixed_array(x, p);
- end to_sfixed_array;
-
- -------------------------------------------------------------------------------
- -- ufixed <= ufixed_array(i)
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is
- variable dst : ufixed(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------------------------
- -- sfixed <= sfixed_array(i)
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is
- variable dst : sfixed(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_sfixed;
-
--------------------------------------------------------------------------------
-end; -- package fixed_util_pkg;
diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd
deleted file mode 100644
index bcd2700..0000000
--- a/lib/fixed_ja/fixed_ja.vhd
+++ /dev/null
@@ -1,322 +0,0 @@
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-package fixed_ja is
-
-
- type ufixed_t is array (integer range <>) of STD_LOGIC;
- type sfixed_t is array (integer range <>) of STD_LOGIC;
- type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
- type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC;
-
- type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent);
- type saturate_mode_t is (none, saturate);
-
- -- Declare functions and procedure
-
- constant ASSERT_NO_WARN : boolean := false;
- constant default_round_mode : round_mode_t := none;
- constant default_saturate_mode : saturate_mode_t := none;
-
- -- null array constants
- constant NAUF : ufixed_t (0 downto 1) := (others => '0');
- constant NASF : sfixed_t (0 downto 1) := (others => '0');
- constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-
- -- Constructor helpers
- -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range);
- function uproto (nbits : integer; nbits_int : integer) return ufixed_t;
-
- -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range);
- function sproto (nbits : integer; nbits_int : integer) return sfixed_t;
-
- function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t;
- function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t;
-
- -- Conversion Functions
- function to_ufixed(src : ufixed_t) return ufixed_t;
- function to_sfixed(src : sfixed_t) return sfixed_t;
- function to_ufixed(src : sfixed_t) return ufixed_t;
- function to_sfixed(src : ufixed_t) return sfixed_t;
-
- function to_ufixed
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_ufixed
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_sfixed
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- function to_sfixed
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- -- fixed <= integer
- function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t;
-
- -- fixed <= integer
- function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t;
-
- -- ufixed <= unsigned
- function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t;
-
- -- sfixed <= signed
- function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t;
-
- -- fixed <= slv
- function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t;
- function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t;
- function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t;
- function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t;
-
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- function to_ufixed
- (
- src : real;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t;
-
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- function to_sfixed
- (
- src : real;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t;
-
- -- Slicing functions for unconstrained array types
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t;
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t;
-
- -- ufixed <= string
- function to_ufixed (src : string) return ufixed_t;
-
- -- sfixed <= string
- function to_sfixed (src : string) return sfixed_t;
-
- -- real <= ufixed
- function to_real(src : ufixed_t) return real;
-
- -- real <= sfixed
- function to_real(src : sfixed_t) return real;
-
- -- slv <= ufixed
- function to_slv(src : ufixed_t) return std_logic_vector;
-
- -- slv <= sfixed
- function to_slv(src : sfixed_t) return std_logic_vector;
-
- -- UNSIGNED <= ufixed
- function to_unsigned (src : ufixed_t) return UNSIGNED;
-
- -- SIGNED <= sfixed
- function to_signed (src : sfixed_t) return SIGNED;
-
- -- integer <= ufixed
- function to_integer (src : ufixed_t) return integer;
-
- -- integer <= sfixed
- function to_integer (src : sfixed_t) return integer;
-
- function to_string(src : ufixed_t) return string;
- function to_string(src : sfixed_t) return string;
- function to_string(src : std_logic_vector) return string;
-
- -------------------------------------------------------------
- -- Arithmetic shift left
- -------------------------------------------------------------
- function "sla" (src : ufixed_t; count : integer) return ufixed_t;
- function "sla" (src : sfixed_t; count : integer) return sfixed_t;
-
- -------------------------------------------------------------
- -- Arithmetic shift right
- -------------------------------------------------------------
- function "sra" (src : ufixed_t; count : integer) return ufixed_t;
- function "sra" (src : sfixed_t; count : integer) return sfixed_t;
-
- -------------------------------------------------------------
- -- Multiplication
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Sum
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : integer) return ufixed_t;
- function "+" (a : sfixed_t; b : integer) return sfixed_t;
- function "+" (a : ufixed_t; b : unsigned) return ufixed_t;
- function "+" (a : sfixed_t; b : signed) return sfixed_t;
- function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t;
- function "+" (a : ufixed_t; b : std_logic) return ufixed_t;
- function "+" (a : sfixed_t; b : std_logic) return sfixed_t;
-
-
- -------------------------------------------------------------
- -- Difference
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : integer) return ufixed_t;
- function "-" (a : sfixed_t; b : integer) return sfixed_t;
- function "-" (a : ufixed_t; b : unsigned) return ufixed_t;
- function "-" (a : sfixed_t; b : signed) return sfixed_t;
- function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t;
- function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t;
- function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t;
- function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t;
- function "-" (a : ufixed_t; b : std_logic) return ufixed_t;
- function "-" (a : sfixed_t; b : std_logic) return sfixed_t;
-
- -------------------------------------------------------------
- -- Equality
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Inequality
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "/=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "/=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "/=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Less than
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : ufixed_t) return boolean;
- function "<" (a : sfixed_t; b : sfixed_t) return boolean;
- function "<" (a : ufixed_t; b : sfixed_t) return boolean;
- function "<" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Greater than
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : ufixed_t) return boolean;
- function ">" (a : sfixed_t; b : sfixed_t) return boolean;
- function ">" (a : ufixed_t; b : sfixed_t) return boolean;
- function ">" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Less or equal than
- -------------------------------------------------------------
- function "<=" (a : ufixed_t; b : ufixed_t) return boolean;
- function "<=" (a : sfixed_t; b : sfixed_t) return boolean;
- function "<=" (a : ufixed_t; b : sfixed_t) return boolean;
- function "<=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Greater or equal than
- -------------------------------------------------------------
- function ">=" (a : ufixed_t; b : ufixed_t) return boolean;
- function ">=" (a : sfixed_t; b : sfixed_t) return boolean;
- function ">=" (a : ufixed_t; b : sfixed_t) return boolean;
- function ">=" (a : sfixed_t; b : ufixed_t) return boolean;
-
- -------------------------------------------------------------
- -- Unary Arithmetic Operators
- -------------------------------------------------------------
- function "abs" (src : sfixed_t) return sfixed_t;
- function "-" (src : ufixed_t) return sfixed_t;
- function "-" (src : sfixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Misc. Operators
- -------------------------------------------------------------
- function ipart (src : ufixed_t) return ufixed_t;
- function fpart (src : ufixed_t) return ufixed_t;
- function ipart (src : sfixed_t) return sfixed_t;
- function fpart (src : sfixed_t) return sfixed_t;
-
- -------------------------------------------------------------
- -- Print function
- -------------------------------------------------------------
- procedure print_info(src : in ufixed_t; prefix : in string);
- procedure print_info(src : in sfixed_t; prefix : in string);
- procedure print_info(src : in string; prefix : in string);
-
- -------------------------------------------------------------
- -- Helpers
- -------------------------------------------------------------
- function cmsb(src : ufixed_t) return integer;
- function clsb(src : ufixed_t) return integer;
-
- function MIN (X, Y: INTEGER) return INTEGER;
- function MAX (X, Y: INTEGER) return INTEGER;
-
- function "MOD" (X, Y: in REAL ) return REAL;
- function ipart(src : real) return real;
- function fpart(src : real) return real;
-
- function and_red(arg : ufixed_t) return STD_ULOGIC;
- function nand_red(arg : ufixed_t) return STD_ULOGIC;
- function or_red(arg : ufixed_t) return STD_ULOGIC;
- function nor_red(arg : ufixed_t) return STD_ULOGIC;
- function xor_red(arg : ufixed_t) return STD_ULOGIC;
- function xnor_red(arg : ufixed_t) return STD_ULOGIC;
- function and_red(arg : sfixed_t) return STD_ULOGIC;
- function nand_red(arg : sfixed_t) return STD_ULOGIC;
- function or_red(arg : sfixed_t) return STD_ULOGIC;
- function nor_red(arg : sfixed_t) return STD_ULOGIC;
- function xor_red(arg : sfixed_t) return STD_ULOGIC;
- function xnor_red(arg : sfixed_t) return STD_ULOGIC;
-
- --------------------------------------------------------------
-
-end; -- package fixed_ja;
-
diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd
deleted file mode 100644
index a85b626..0000000
--- a/lib/fixed_ja/fixed_ja_body.vhd
+++ /dev/null
@@ -1,1921 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-use ieee.math_real.all;
-use std.textio.all;
-
-package body fixed_ja is
-
- -------------------------------------------------------------
- -- Local Procedures
- -------------------------------------------------------------
- -- adds 1 to the LSB of the number
- procedure round_up
- (
- src : in ufixed_t;
- result : out ufixed_t;
- overflowx : out BOOLEAN ) is
-
- variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0');
- begin -- round_up
- srcuns (srcuns'high-1 downto 0) := to_unsigned (src);
- resuns := srcuns + 1;
-
- result := to_ufixed(resuns(src'high-src'low downto 0), src);
- overflowx := (resuns(resuns'high) = '1');
-
- end procedure round_up;
-
- -------------------------------------------------------------
- -- adds 1 to the LSB of the number
- procedure round_up
- (
- src : in sfixed_t;
- result : out sfixed_t;
- overflowx : out BOOLEAN ) is
-
- variable srcs, ress : SIGNED (src'high-src'low+1 downto 0);
- begin -- round_up
- srcs (srcs'high-1 downto 0) := to_signed (src);
- srcs(srcs'high) := src(src'high); -- sign extend
- ress := srcs + 1;
-
- result := to_sfixed(ress (ress'high-1 downto 0), src);
- overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0'));
-
- end procedure round_up;
-
- -------------------------------------------------------------
- -- Local functions
- -------------------------------------------------------------
- -- round_fixed()
--- function round_fixed
--- (
--- src : ufixed_t;
--- remainder : ufixed_t;
--- rnd_mode : round_mode_t := default_round_mode
--- ) return ufixed_t is
--- variable res : ufixed_t(src'range);
--- begin
--- return res;
---
--- end round_fixed;
-
- -------------------------------------------------------------
--- function round_fixed
--- (
--- src : sfixed_t;
--- remainder : sfixed_t;
--- rnd_mode : round_mode_t := default_round_mode
--- ) return sfixed_t is
--- variable res : signed(src'length-1 downto 0);
--- begin
--- return src;
---
--- end round_fixed;
-
- -------------------------------------------------------------
- function reshape
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0');
- variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0');
- variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0');
- variable ovf, isTruncLo, isTruncHi : boolean := false;
- begin
-
- if proto'high < -1 then
- assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error;
- end if;
-
- -- Check for high and low truncation
- isTruncLo := (src'low < dst'low);
- isTruncHi := (src'high > dst'high);
-
- -- Reshape
- dst := (others => '0');
- dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low));
- tmp := dst;
-
- -- Get low remainder
- if isTruncLo then
- RemainLow := src(RemainLow'range);
- end if;
-
- -- Get high remainder
- if isTruncHi then
- RemainHigh := src(RemainHigh'range);
- end if;
-
- ovf := false;
-
- -- Rounding
- if isTruncLo then
-
- case rnd_mode is
-
- -- Round to positive infinity (round ceiling)
- when round_pos_infinity =>
- if or_red(RemainLow) = '1' then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round Half-up
- -- Round nearest
- when round_half_up | round_nearest =>
- if (RemainLow(RemainLow'high) = '1') then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round convergent
- when round_convergent =>
- if RemainLow(RemainLow'high) = '1' then
- if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
- round_up(tmp, dst, ovf);
- elsif tmp(dst'low) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round to zero
- when round_to_zero | none => null;
-
- when others =>
- assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-
- end case;
- end if;
-
- -- Saturating
- if sat_mode = saturate then
-
- -- Check overflow
- if isTruncHi then
- ovf := ovf or or_red(RemainHigh) = '1';
- end if;
-
- -- Saturate
- if ovf then
- dst := (others => '1');
- end if;
-
- end if;
-
- return dst;
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- begin
- return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode);
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0');
- variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0');
- variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0');
- variable ovf, isTruncLo, isTruncHi : boolean := false;
- variable sign : std_logic;
- begin
-
- if proto'high < 0 then
- assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error;
- end if;
-
- -- Check for high and low truncation
- isTruncLo := (src'low < dst'low);
- isTruncHi := (src'high > dst'high);
-
- -- Reshape
- sign := src(src'high);
- dst := (others => '0');
- dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low));
- tmp := dst;
-
- -- Get low remainder
- if isTruncLo then
- RemainLow := src(RemainLow'range);
- end if;
-
- -- Get high remainder
- if isTruncHi then
- RemainHigh := src(RemainHigh'range);
- end if;
-
- ovf := false;
-
- -- Rounding
- if isTruncLo then
-
- case rnd_mode is
-
- -- Round to positive infinity (round ceiling)
- when round_pos_infinity =>
- round_up(tmp, dst, ovf);
- if ovf then
- dst(dst'high) := '0';
- end if;
-
- -- Round Half-up
- when round_half_up =>
- if RemainLow(RemainLow'high) = '1' then
- round_up(tmp, dst, ovf);
- end if;
-
- -- Round nearest
- when round_nearest =>
- if RemainLow(RemainLow'high) = '1' then
- if RemainLow'length = 1 then
- if sign = '0' then
- round_up(tmp, dst, ovf);
- end if;
- elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round convergent
- when round_convergent =>
- if RemainLow(RemainLow'high) = '1' then
- if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then
- round_up(tmp, dst, ovf);
- elsif tmp(dst'low) = '1' then
- round_up(tmp, dst, ovf);
- end if;
- end if;
-
- -- Round to zero
- when round_to_zero =>
- if (or_red(RemainLow) = '1' and sign = '1') then
- round_up(tmp, dst, ovf);
- end if;
-
- -- No Round
- when none =>
- -- Same as RoundToZero but overflow detection is omitted
- dst := tmp + (or_red(RemainLow) and sign);
-
- when others =>
- assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error;
-
- end case;
-
- -- Check negative zero
- if dst(dst'high) = '1' then
- if or_red(dst(dst'high-1 downto dst'low)) = '0' then
- dst(dst'high) := '0';
- -- assert false report "Reshape(S): -0 detected" severity note;
- end if;
- end if;
- end if;
-
- -- Saturating
- if sat_mode = saturate then
-
- -- Check overflow
- if isTruncHi then
- ovf := ovf or
- (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or
- (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or
- (sign = '0' and or_red(RemainHigh) = '1');
- end if;
-
- -- Saturate
- if ovf then
- if (sign = '1') then
- dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1';
- else
- dst := '0' & (dst'high-1 downto dst'low => '1');
- end if;
- end if;
-
- end if;
-
- return dst;
-
- end reshape;
-
- -------------------------------------------------------------
- function reshape
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- begin
- return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
-
- end reshape;
-
- -------------------------------------------------------------
- -- Constuctor helpers
- -------------------------------------------------------------
- function uproto (nbits : integer; nbits_int : integer) return ufixed_t is
- constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0');
- begin
- return result(nbits_int-1 downto nbits_int-nbits);
- end uproto;
-
- -------------------------------------------------------------
- function sproto (nbits : integer; nbits_int : integer) return sfixed_t is
- constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0');
- begin
- return result(nbits_int downto nbits_int-nbits+1);
- end sproto;
-
- -------------------------------------------------------------
- function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is
- constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
- variable hi, lo : integer := 0;
-
- begin
-
- case op is
- when '+' =>
- hi := max(a'high, b'high);
- if a'high = b'high then
- hi := hi + 1;
- end if;
- lo := min(a'low, b'low);
-
- when '-' =>
- hi := max(a'high, b'high);
- lo := min(a'low, b'low);
-
- when '*' =>
- hi := a'high + b'high + 1;
- if (a'high < 0 or b'high < 0) then
- if (hi > -1) then
- hi := hi-1;
- end if;
- end if;
- lo := hi - a'length - b'length + 1;
-
- when others => null;
-
- end case;
-
- return result(hi downto lo);
- end uproto;
-
- -------------------------------------------------------------
- function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is
- constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0');
- variable hi, lo : integer := 0;
-
- begin
-
- case op is
- when '+' =>
- hi := max(a'high, b'high);
- if a'high = b'high then
- hi := hi + 1;
- end if;
- lo := min(a'low, b'low);
-
- when '-' =>
- hi := max(a'high, b'high);
- lo := min(a'low, b'low);
-
- when '*' =>
- hi := a'high + b'high;
- if (a'high = 0 or b'high = 0) then
- if (hi > 0) then
- hi := hi-1;
- end if;
- end if;
- lo := hi - a'length - b'length + 1;
-
- when others => null;
-
- end case;
-
- return result(hi downto lo);
- end sproto;
-
- -------------------------------------------------------------
- -- Type conversions
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed(src : ufixed_t) return ufixed_t is
- begin
- return to_ufixed(src, src);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= sfixed
- function to_ufixed(src : sfixed_t) return ufixed_t is
- variable dst : ufixed_t(src'range) := (others => '0');
- begin
- dst := ufixed_t(abs(src));
- return dst(src'high-1 downto src'low);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed(src : sfixed_t) return sfixed_t is
- begin
- return src;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= ufixed
- function to_sfixed(src : ufixed_t) return sfixed_t is
- variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0');
- begin
- dst(src'range) := sfixed_t(src);
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed
- (
- src : ufixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= ufixed
- function to_ufixed
- (
- src : ufixed_t;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return reshape(src, proto, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed
- (
- src : sfixed_t;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return reshape(src, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= sfixed
- function to_sfixed
- (
- src : sfixed_t;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return reshape(src, proto, rnd_mode, sat_mode);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= integer
- function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end to_ufixed;
-
- function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is
- begin
- return to_ufixed(to_unsigned(src, proto'length), proto);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= unsigned
- function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- ufixed <= unsigned
- function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is
- variable dst : ufixed_t(proto'high downto proto'low) := (others => '0');
- begin
-
- dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0));
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= integer
- function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
-
- function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is
- begin
-
- return to_sfixed(to_signed(src, proto'length), proto);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= signed
- function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- sfixed <= signed
- function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is
- variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
- begin
-
- dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0));
- dst(dst'high) := src(src'high);
-
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is
- variable result : ufixed_t (proto'left downto proto'right);
- begin
- if (result'length < 1) then
- return result;
- else
- result := to_ufixed (unsigned(src), proto);
- return result;
- end if;
-
- end function to_ufixed;
-
- -------------------------------------------------------------
- function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is
- begin
- return to_ufixed(src, uproto(nbits, nbits_int));
-
- end function to_ufixed;
-
- -------------------------------------------------------------
- function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is
- variable result : sfixed_t (proto'left downto proto'right);
- begin
- if (result'length < 1) then
- return result;
- else
- result := to_sfixed (signed(src), proto);
- return result;
- end if;
-
- end function to_sfixed;
-
- -------------------------------------------------------------
- function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int));
-
- end to_sfixed;
- -------------------------------------------------------------
-
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
-
- constant nbits_ext : integer := nbits + 1;
- constant fix_hi : integer := nbits_int - 1;
- constant fix_lo : integer := nbits_int - nbits_ext;
-
- variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0');
- variable i : integer := 0;
- variable remain : real := 0.0;
-
- begin
-
- if (nbits_int < 0) then
- assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error;
- end if;
-
- if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then
--- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning;
--- print_info(dst, "dst: ");
- end if;
-
- remain := abs(src);
- for i in dst'range loop
- if remain >= 2.0**i then
- dst(i) := '1';
- remain := remain - 2.0**i;
- else
- dst(i) := '0';
- end if;
- end loop;
-
- return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- proto : sfixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
-
- variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0');
- variable dst : sfixed_t(proto'high downto proto'low) := (others => '0');
-
- begin
- utmp := to_ufixed(src, utmp, rnd_mode, sat_mode);
- if (src < 0.0) then
- dst := -to_sfixed(utmp);
- else
- dst := to_sfixed(utmp);
- end if;
-
- return dst;
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= real
- function to_ufixed
- (
- src : real;
- proto : ufixed_t;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return ufixed_t is
- begin
- return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode);
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= real
- function to_sfixed
- (
- src : real;
- nbits : integer;
- nbits_int : integer;
- rnd_mode : round_mode_t := default_round_mode;
- sat_mode : saturate_mode_t := default_saturate_mode
- ) return sfixed_t is
- begin
- return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode);
- end to_sfixed;
-
- -------------------------------------------------------------------------------
- -- ufixed <= ufixed_array(i)
- function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is
- variable dst : ufixed_t(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_ufixed;
-
- -------------------------------------------------------------------------------
- -- sfixed <= sfixed_array(i)
- function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is
- variable dst : sfixed_t(src'range(2));
- begin
- for j in src'range(2) loop
- dst(j) := src(index, j);
- end loop;
-
- return dst;
-
- end to_sfixed;
-
- -------------------------------------------------------------
- -- ufixed <= string
- function to_ufixed (src : string) return ufixed_t is
-
- variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
- variable dst : unsigned(src'length downto 0) := (others => '0');
- variable dp_found : boolean := false;
- begin
-
- for i in src'reverse_range loop
- case src(i) is
- when '.' =>
- if dp_found then
- assert false report "More than one DP not found." severity error;
- else
- dp_found := true;
- nbits_frac := j;
- end if;
-
- when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
- when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
- when others =>
- assert false report "Illegal character in binary string." severity error;
-
- end case;
-
- end loop ;
- if not dp_found then
- assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
- end if;
-
- nbits_int := nbits - nbits_frac;
-
- return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int);
-
- end to_ufixed;
-
- -------------------------------------------------------------
- -- sfixed <= string
- function to_sfixed (src : string) return sfixed_t is
-
- variable i, j, nbits, nbits_int, nbits_frac : integer := 0;
- variable dst : signed(src'length downto 0) := (others => '0');
- variable dp_found : boolean := false;
- variable is_neg : boolean := false;
- begin
-
- is_neg := src(src'left) = '-';
-
- for i in src'reverse_range loop
- case src(i) is
- when '-' => null;
- when '+' => null;
-
- when '.' =>
- if dp_found then
- assert false report "More than one DP not found." severity error;
- else
- dp_found := true;
- nbits_frac := j;
- end if;
-
- when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1;
- when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1;
- when others =>
- assert false report "Illegal character in binary string." severity error;
- end case;
- end loop ;
- nbits := nbits + 1;
-
- if not dp_found then
- assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning;
- end if;
-
- nbits_int := nbits - nbits_frac-1;
-
- if is_neg then
- dst(nbits-1 downto 0) := -dst(nbits-1 downto 0);
- end if;
-
- return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int);
-
- end to_sfixed;
-
- -------------------------------------------------------------
- function to_unsigned (src : ufixed_t) return UNSIGNED is
- subtype t is UNSIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return UNSIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_unsigned;
-
- -------------------------------------------------------------
- function to_signed (src : sfixed_t) return SIGNED is
- subtype t is SIGNED(src'high - src'low downto 0);
- variable slv : t;
- begin
- slv := t(src);
- return SIGNED(to_X01(std_logic_vector(slv)));
-
- end function to_signed;
-
- -------------------------------------------------------------
- -- integer <= ufixed
- function to_integer (src : ufixed_t) return integer is
- begin
- return to_integer(to_unsigned(src));
- end to_integer;
-
- -------------------------------------------------------------
- -- integer <= sfixed
- function to_integer (src : sfixed_t) return integer is
- begin
- return to_integer(to_signed(src));
- end to_integer;
-
- -------------------------------------------------------------
- -- to_real
- function to_real(src : ufixed_t) return real is
- variable dst : real := 0.0;
- begin
- for i in src'range loop
- if (src(i) = '1') then
- dst := dst + real(2.0**i);
- end if;
- end loop;
- return dst;
-
- end to_real;
-
- -------------------------------------------------------------
- function to_real(src : sfixed_t) return real is
- variable dst : real := 0.0;
- begin
- dst := to_real(to_ufixed(src));
-
- if (src(src'high) = '1') then
- dst := -dst;
- end if;
-
- return dst;
-
- end to_real;
-
- -------------------------------------------------------------
- -- to_slv
- function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is
- subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
- variable slv : t;
- begin
- if src'length < 1 then
- return NSLV;
- end if;
- slv := t (src);
- return slv;
-
- end function to_slv;
-
- -------------------------------------------------------------
- -- to_slv
- function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is
- subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0);
- variable slv : t;
- begin
- if src'length < 1 then
- return NSLV;
- end if;
- slv := t (src);
- return slv;
-
- end function to_slv;
-
- -------------------------------------------------------------
- function to_string(src : ufixed_t) return string is
- variable str : string(src'length+1 downto 1) := (others => '0');
- variable i, j : integer := 0;
-
- begin
- j := src'length+1;
- for i in src'high downto 0 loop
- if (src(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- str(j) := '.';
- j := j - 1;
-
- for i in -1 downto src'low loop
- if (src(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- return str;
-
- end to_string;
-
- -------------------------------------------------------------
- function to_string(src : sfixed_t) return string is
- variable str : string(src'length+1 downto 1) := (others => '0');
- variable i, j, start : integer := 0;
- variable strlen : integer := 0;
- variable src_abs : sfixed_t(src'range) := (others => '0');
-
- begin
- if (src'high < 0) then
- assert false report "Illegal signed fix point number" severity error;
- end if;
-
- start := src'high;
- strlen := src'length;
-
- j := src'length+1;
- if (src(start) = '1') then
- str(j) := '-';
- j := j - 1;
- start := start - 1;
- strlen := strlen + 1;
- end if;
-
- src_abs := abs(src);
-
- for i in start downto 0 loop
- if (src_abs(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- str(j) := '.';
- j := j - 1;
-
- for i in -1 downto src'low loop
- if (src_abs(i) = '1') then
- str(j) := '1';
- end if;
- j := j - 1;
- end loop;
-
- return str(strlen downto 1);
-
- end to_string;
-
- -------------------------------------------------------------
- function to_string(src : std_logic_vector) return string is
- variable str : string(src'length downto 1) := (others => '0');
- variable i : integer := 0;
-
- begin
- for i in src'range loop
- if (src(i) = '1') then
- str(i+1) := '1';
- end if;
- end loop;
-
- return str;
-
- end to_string;
-
- -------------------------------------------------------------
- -- Binary Operators
- -------------------------------------------------------------
- function "sla" (src : ufixed_t; count : integer) return ufixed_t is
- variable result : ufixed_t (src'high downto src'low) := (others => '0');
-
- begin
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sra -count;
- elsif (count < src'length) then
- result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0');
- end if;
- return result;
-
- end "sla";
-
- -------------------------------------------------------------
- function "sla" (src : sfixed_t; count : integer) return sfixed_t is
- variable result : sfixed_t (src'high downto src'low) := (others => '0');
- variable sign : std_logic := '0';
-
- begin
- sign := src(src'high);
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sra -count;
- elsif (count < src'length-1) then
- result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0');
- end if;
- return result;
-
- end "sla";
-
- -------------------------------------------------------------
- function "sra" (src : ufixed_t; count : integer) return ufixed_t is
- variable result : ufixed_t (src'high downto src'low) := (others => '0');
-
- begin
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sla -count;
- elsif (count < src'length) then
- result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count);
- end if;
- return result;
-
- end "sra";
-
- -------------------------------------------------------------
- function "sra" (src : sfixed_t; count : integer) return sfixed_t is
- variable result : sfixed_t (src'high downto src'low) := (others => '0');
- variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0');
- variable sign, do_sub : std_logic := '0';
-
- begin
- src_slv := to_signed(src);
- sign := src(src'high);
- do_sub := src(src'high) and src(src'low);
- if (count = 0) then
- result := src;
- elsif (count < 0) then
- result := src sla -count;
- elsif (count < src'length-1) then
- res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count);
- if (do_sub = '1') then
- result(src'high downto src'low) := to_sfixed(res_slv+1, result);
- else
- result(src'high downto src'low) := to_sfixed(res_slv, result);
- end if;
- end if;
- return result;
-
- end "sra";
-
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low);
-
- begin
- if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then
- result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1;
- else
- result := to_ufixed(to_unsigned(a) * to_unsigned(b), result);
- end if;
- return result;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low);
-
- begin
- if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then
- result := to_sfixed(signed(a) * signed(b), result) sla 2;
- else
- result := to_sfixed(signed(a) * signed(b), result) sla 1;
- end if;
- return result;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
- begin
- return to_sfixed(a) * b;
-
- end "*";
-
- -------------------------------------------------------------
- function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return b * a;
-
- end "*";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low);
-
- begin
- result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result)));
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low);
-
- begin
- result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result);
--- result := to_sfixed(signed(a) + signed(b), result);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is
-
- begin
- return to_sfixed(a) + b;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return b + a;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : unsigned) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) + b);
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : signed) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) + b);
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : integer) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) + to_unsigned(b, a'length));
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : integer) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) + to_signed(b, a'length));
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : ufixed_t; b : std_logic) return ufixed_t is
- variable result : ufixed_t (a'high downto a'low);
- variable buns : unsigned(a'length-1 downto 0);
-
- begin
- buns := (a'length-1 downto 1 => '0') & b;
- result := ufixed_t(to_unsigned(a) + buns);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "+" (a : sfixed_t; b : std_logic) return sfixed_t is
- variable result : sfixed_t (a'high downto a'low);
- variable bs : signed(a'length-1 downto 0);
-
- begin
- bs := (a'length-1 downto 1 => '0') & b;
- result := sfixed_t(to_signed(a) + bs);
- return result;
-
- end "+";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is
- variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low);
- begin
- result := to_ufixed(to_sfixed(a) - to_sfixed(b));
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is
- variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low);
-
- begin
- result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(a) - b;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is
-
- begin
- return a - to_sfixed(b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : unsigned) return ufixed_t is
-
- begin
- return ufixed_t(unsigned(a) - b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : signed) return sfixed_t is
-
- begin
- return sfixed_t(signed(a) - b);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : integer) return ufixed_t is
-
- begin
-
- return ufixed_t(unsigned(a) - to_unsigned(b, a'length));
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : integer) return sfixed_t is
-
- begin
-
- return sfixed_t(signed(a) - to_signed(b, a'length));
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : ufixed_t; b : std_logic) return ufixed_t is
- variable result : ufixed_t (a'high downto a'low);
- variable buns : unsigned(a'length-1 downto 0);
-
- begin
- buns := (a'length-1 downto 1 => '0') & b;
- result := ufixed_t(unsigned(a) - buns);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (a : sfixed_t; b : std_logic) return sfixed_t is
- variable result : sfixed_t (a'high downto a'low);
- variable bs : signed(a'length-1 downto 0);
-
- begin
- bs := (a'length-1 downto 1 => '0') & b;
- result := sfixed_t(signed(a) - bs);
- return result;
-
- end "-";
-
- -------------------------------------------------------------
- -- Unary Operators
- -------------------------------------------------------------
- function "abs" (src : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(abs(signed(src)), src);
-
- end "abs";
-
- -------------------------------------------------------------
- function "-" (src : ufixed_t) return sfixed_t is
- begin
- return -to_sfixed(src);
-
- end "-";
-
- -------------------------------------------------------------
- function "-" (src : sfixed_t) return sfixed_t is
- begin
- return to_sfixed(-signed(src), src);
-
- end "-";
-
- -------------------------------------------------------------
- -- Binary Equality
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) = to_unsigned(tb);
-
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) = to_signed(tb);
-
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) = b;
- end "=";
-
- -------------------------------------------------------------
- function "=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return b = a;
- end "=";
-
- -------------------------------------------------------------
- -- Binary Inequality
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a = b);
-
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a = b);
-
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a = b);
- end "/=";
-
- -------------------------------------------------------------
- function "/=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a = b);
- end "/=";
-
- -------------------------------------------------------------
- -- Binary less than
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) < to_unsigned(tb);
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) < to_signed(tb);
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) < b;
-
- end "<";
-
- -------------------------------------------------------------
- function "<" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return a < to_sfixed(b);
-
- end "<";
-
- -------------------------------------------------------------
- -- Binary greater than
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : ufixed_t) return boolean is
- variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_ufixed(a, ta);
- tb := to_ufixed(b, tb);
- return to_unsigned(ta) > to_unsigned(tb);
-
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : sfixed_t; b : sfixed_t) return boolean is
- variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low));
- begin
- ta := (others => '0');
- tb := (others => '0');
- ta := to_sfixed(a, ta);
- tb := to_sfixed(b, tb);
- return to_signed(ta) > to_signed(tb);
-
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return to_sfixed(a) > b;
- end ">";
-
- -------------------------------------------------------------
- function ">" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return a > to_sfixed(b);
- end ">";
-
- -------------------------------------------------------------
- -- Binary less equal than
- -------------------------------------------------------------
- function "<=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- function "<=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a > b);
- end "<=";
-
- -------------------------------------------------------------
- -- Binary greater or equal than
- -------------------------------------------------------------
- function ">=" (a : ufixed_t; b : ufixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : sfixed_t; b : sfixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : ufixed_t; b : sfixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- function ">=" (a : sfixed_t; b : ufixed_t) return boolean is
- begin
- return not (a < b);
- end ">=";
-
- -------------------------------------------------------------
- -- Misc. Operators
- -------------------------------------------------------------
- function ipart (src : ufixed_t) return ufixed_t is
- begin
- return src(src'high downto 0);
- end ipart;
-
- function fpart (src : ufixed_t) return ufixed_t is
- begin
- return src(-1 downto src'low);
- end fpart;
-
- function ipart (src : sfixed_t) return sfixed_t is
- begin
- return src(src'high-1 downto 0);
- end ipart;
-
- function fpart (src : sfixed_t) return sfixed_t is
- begin
- return src(-1 downto src'low);
- end fpart;
-
- -------------------------------------------------------------
- -- Print functions
- -------------------------------------------------------------
- procedure print_info(src : in ufixed_t; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'value = B");write (L, to_string(src));
- writeline (output, L);
-
- write (L, prefix & "'value = ");write (L, to_real(src));
- writeline (output, L);
-
- -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
- -- writeline (output, L);
-
- -- write (L, prefix & "'clsb = ");write (L, clsb(src));
- -- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- procedure print_info(src : in sfixed_t; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'value = B");write (L, to_string(src));
- writeline (output, L);
-
- write (L, prefix & "'value = ");write (L, to_real(src));
- writeline (output, L);
-
- -- write (L, prefix & "'cmsb = ");write (L, cmsb(src));
- -- writeline (output, L);
-
- -- write (L, prefix & "'clsb = ");write (L, clsb(src));
- -- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- procedure print_info(src : in string; prefix : in string) is
- variable L : line;
-
- begin
- write (L, prefix & "'length = ");write (L, src'length);
- writeline (output, L);
-
- write (L, prefix & "'high(left) = ");
- write (L, src'high);
- write (L, '(');
- write (L, src'left);
- write (L, ')');
- writeline (output, L);
-
- write (L, prefix & "'low(right) = ");
- write (L, src'low);
- write (L, '(');
- write (L, src'right);
- write (L, ')');
- writeline (output, L);
-
- writeline (output, L);
-
- end print_info;
-
- -------------------------------------------------------------
- -- Helpers
- -------------------------------------------------------------
- -- Count significant bits for integer part
- function cmsb(src : ufixed_t) return integer is
- variable j, i : integer := src'high;
- begin
- for i in src'range loop
- if src(i) = '1' then
- exit;
- end if;
- j := j - 1;
- end loop;
-
- -- LRM nachlesen: hier is i=src'high re-initialisert
-
- return j;
-
- end cmsb;
-
- -------------------------------------------------------------
- -- Count significant bits for fractional part
- function clsb(src : ufixed_t) return integer is
- variable j, i : integer := src'low;
- begin
- for i in src'reverse_range loop
- if src(i) = '1' then
- exit;
- end if;
- j := j + 1;
- end loop;
-
- -- LRM nachlesen: hier is i=src'low re-initialisert
-
- return j;
-
- end clsb;
-
- -------------------------------------------------------------
- function MIN (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y < X then
- res := Y;
- end if;
-
- return res;
-
- end MIN;
-
- -------------------------------------------------------------
- function MAX (X, Y: INTEGER) return INTEGER is
- variable res : integer := X;
- begin
- if Y > X then
- res := Y;
- end if;
-
- return res;
-
- end MAX;
-
- -------------------------------------------------------------
- function "MOD" (X, Y: in REAL ) return REAL is
- -- Description:
- -- See function declaration in IEEE Std 1076.2-1996
- -- Notes:
- -- a) Returns 0.0 on error
-
- variable XNEGATIVE : BOOLEAN := X < 0.0;
- variable YNEGATIVE : BOOLEAN := Y < 0.0;
- variable VALUE : REAL;
- begin
- -- Check validity of input arguments
- if (Y = 0.0) then
- assert FALSE
- report "MOD(X, 0.0) is undefined"
- severity ERROR;
- return 0.0;
- end if;
-
- -- Compute value
- if ( XNEGATIVE ) then
- if ( YNEGATIVE ) then
- VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
- else
- VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
- end if;
- else
- if ( YNEGATIVE ) then
- VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y);
- else
- VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y);
- end if;
- end if;
-
- return VALUE;
-
- end "MOD";
-
- -------------------------------------------------------------
- -- misc. conversion
- function ipart(src : real) return real is
- begin
- return floor(src);
-
- end ipart;
-
- -------------------------------------------------------------
- function fpart(src : real) return real is
- begin
- return src - floor(src);
-
- end fpart;
-
- -------------------------------------------------------------
- function or_red (arg : STD_LOGIC_VECTOR)
- return STD_LOGIC is
- variable Upper, Lower : STD_LOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_LOGIC;
- begin
- if (arg'length < 1) then -- In the case of a NULL range
- Result := '0';
- else
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := or_red (BUS_int (BUS_int'left downto Half));
- Lower := or_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper or Lower;
- end if;
- end if;
- return Result;
-
- end function or_red;
-
- -------------------------------------------------------------
- function and_red (arg : STD_LOGIC_VECTOR)
- return STD_LOGIC is
- variable Upper, Lower : STD_LOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_LOGIC;
- begin
- if (arg'length < 1) then -- In the case of a NULL range
- Result := '1';
- else
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := and_red (BUS_int (BUS_int'left downto Half));
- Lower := and_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper and Lower;
- end if;
- end if;
- return Result;
-
- end function and_red;
-
- -------------------------------------------------------------
- function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
- variable Upper, Lower : STD_ULOGIC;
- variable Half : INTEGER;
- variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
- variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
- begin
- if (arg'length >= 1) then
- BUS_int := to_ux01 (arg);
- if (BUS_int'length = 1) then
- Result := BUS_int (BUS_int'left);
- elsif (BUS_int'length = 2) then
- Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
- else
- Half := (BUS_int'length + 1) / 2 + BUS_int'right;
- Upper := xor_red (BUS_int (BUS_int'left downto Half));
- Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right));
- Result := Upper xor Lower;
- end if;
- end if;
- return Result;
-
- end function xor_red;
-
- -------------------------------------------------------------
- -- Reduction operators, same as numeric_std functions
- function and_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return and_red (to_slv(arg));
- end function and_red;
-
- function nand_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not and_red (to_slv(arg));
- end function nand_red;
-
- function or_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return or_red (to_slv(arg));
- end function or_red;
-
- function nor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not or_red (to_slv(arg));
- end function nor_red;
-
- function xor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return xor_red (to_slv(arg));
- end function xor_red;
-
- function xnor_red(arg : ufixed_t) return STD_ULOGIC is
- begin
- return not xor_red (to_slv(arg));
- end function xnor_red;
-
- function and_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return and_red (to_slv(arg));
- end function and_red;
-
- function nand_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not and_red (to_slv(arg));
- end function nand_red;
-
- function or_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return or_red (to_slv(arg));
- end function or_red;
-
- function nor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not or_red (to_slv(arg));
- end function nor_red;
-
- function xor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return xor_red (to_slv(arg));
- end function xor_red;
-
- function xnor_red(arg : sfixed_t) return STD_ULOGIC is
- begin
- return not xor_red (to_slv(arg));
- end function xnor_red;
-
- -------------------------------------------------------------
-
-end; -- package body fixed_ja;
diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm
deleted file mode 100644
index 01c36c4..0000000
--- a/lib/jasm/cg.inc.jsm
+++ /dev/null
@@ -1,72 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xio-address equates for
-; reg_cg_char_addr: equ 0xXX ; RW
-; reg_cg_line_addr: equ 0xXX ; RW
-; reg_cg_data: equ 0xXX ; RW
-; reg_cg_ctrl: equ 0xXX ; WO
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-cg_clr_line: push R0
- mov R0, 2
- xout (reg_cg_ctrl), R0
- pop R0
- ret
-
-; -------------------------------------------------
-cg_clr_screen: push R0
- mov R0, 1
- xout (reg_cg_ctrl), R0
- pop R0
- ret
-
-; -------------------------------------------------
-; R0 : char address
-; R1 : line address
-cg_set_addr: call cg_wait_rdy
- xout (reg_cg_line_addr), R1
- xout (reg_cg_char_addr), R0
- ret
-
-; -------------------------------------------------
-; R0 : character
-cg_putchar: call cg_wait_rdy
- xout (reg_cg_data), R0
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts: push R0
-cg_p_lp: movx R0, (R1)
- inc R1
- tst R0
- jz ex_cgp
- call cg_putchar
- jmp cg_p_lp
-ex_cgp: pop R0
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_clr_puts: call cg_clr_line
- call cg_puts
- ret
-
-; -------------------------------------------------
-; R1 : ptr to string
-cg_puts_clr: call cg_puts
- call cg_clr_line
- ret
-
-; -------------------------------------------------
-cg_wait_rdy: push R0
-cg_wr_lp: xin R0, (reg_hwstat)
- and R0, 0x02
- jz cg_wr_lp
- pop R0
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm
deleted file mode 100644
index 06d39d9..0000000
--- a/lib/jasm/cregs.inc.jsm
+++ /dev/null
@@ -1,7 +0,0 @@
-; JCPU On-Chip register
-cpu_revision: equ 0x00 ; RO
-cpu_control: equ 0x01 ; R/W
-cpu_status: equ 0x02 ; RO
-cpu_int_ctrl: equ 0x03 ; RW
-cpu_cmem_high: equ 0x04 ; RW
-cpu_stack_high: equ 0x05 ; RW
diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm
deleted file mode 100644
index 6f002ee..0000000
--- a/lib/jasm/delays.inc.jsm
+++ /dev/null
@@ -1,64 +0,0 @@
-; -------------------------------------------------
-; Delays
-; -------------------------------------------------
-delay1s: push R15
- mov R15, 10
-loop1s: call delay100ms
- dec R15
- jnz loop1s
- pop R15
- ret
-
-delay100ms: push R15
- mov R15, 10
-loop100ms: call delay10ms
- dec R15
- jnz loop100ms
- pop R15
- ret
-
-delay10ms: push R15
- mov R15, 10
-loop10ms: call delay1ms
- dec R15
- jnz loop10ms
- pop R15
- ret
-
-delay1ms: push R15
- mov R15, 10
-loop1ms: call delay100us
- dec R15
- jnz loop1ms
- pop R15
- ret
-
-delay100us: push R15
- mov R15, 10
-loop100us: call delay10us
- dec R15
- jnz loop100us
- pop R15
- ret
-
-delay10us: push R15
- mov R15, 99
-loop10us: nop
- nop
- nop
- dec R15
- jnz loop10us
- pop R15
- ret
-
-delay1us: push R15
- mov R15, 9
-loop1us: nop
- nop
- nop
- dec R15
- jnz loop1us
- pop R15
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm
deleted file mode 100644
index d2883fa..0000000
--- a/lib/jasm/lcd.inc.jsm
+++ /dev/null
@@ -1,208 +0,0 @@
-; -------------------------------------------------
-; lcd.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - lcd_port (LCD-Base)
-
-; needs delay.inc.jsm
-
-; -------------------------------------------------
-lcd_cmd: equ 0x00
-lcd_rd: equ 0x20
-lcd_data: equ 0x40
-lcd_enable: equ 0x80
-
-LCD_CMD_Z1: equ 0x80
-LCD_CMD_Z2: equ 0xC0
-LCD_CMD_CLEAR: equ 0x01
-
-; -------------------------------------------------
-; Init LCD
-; -------------------------------------------------
-LCD_init: mov R2, 0x00
- mov R0, 0x03
- call _write_lcd
- call delay10ms
- mov R2, 0x00
- mov R0, 0x03
- call _write_lcd
- call delay10ms
-
- mov R2, 0x00
- mov R0, 0x02
- call _write_lcd
- call delay1ms
-
- ; 1. Function set: 4-Bit mode, two display lines
- mov R0, 0x28
- call LCD_writecmd
-
- ; 2. Display on, no cursor
- mov R0, 0x0C
- call LCD_writecmd
-
- ; 3. Cursor shift during write
- mov R0, 0x06
- call LCD_writecmd
-
- ; 4. Display clear
- mov R0, 0x01
- call LCD_writecmd
-
- ret
-
-; -------------------------------------------------
-; LCD_waitbsy
-; -------------------------------------------------
-LCD_waitbsy: push R0
-bsy_loop: call LCD_readstat
- and R0, 0x80
- jz ex_bsy
- call delay1us
- jmp bsy_loop
-ex_bsy: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_writecmd
-; -------------------------------------------------
-; R0 = cmd
-LCD_writeaddr:
-LCD_writecmd: push R2
- mov R2, lcd_cmd
- call LCD_write
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_putsx
-; -------------------------------------------------
-; R1 = address of null-terminated string in XMEM
-LCD_putsx: push R0
-putsx_loop: movx R0, (R1)
- inc R1
- tst R0
- jz putsx_ex
- call LCD_writechar
- jmp putsx_loop
-putsx_ex: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_putsc
-; -------------------------------------------------
-; R1 = address of null-terminated string in CMEM
-LCD_putsc: push R0
-putsc_loop: movc R0, (R1)
- inc R1
- tst R0
- jz putsc_ex
- call LCD_writechar
- jmp putsc_loop
-putsc_ex: pop R0
- ret
-
-; -------------------------------------------------
-; LCD_writechar
-; -------------------------------------------------
-; R0 = char
-LCD_writedata:
-LCD_writechar: push R2
- mov R2, lcd_data
- call LCD_write
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_write
-; -------------------------------------------------
-; R0 = input
-; R2 = register
-LCD_write: call LCD_waitbsy
- push R0
- swap R0
- call _write_lcd
- pop R0
- call _write_lcd
- ret
-
-; -------------------------------------------------
-; LCD_readstat
-; -------------------------------------------------
-; R0 = status
-LCD_readstat: push R2
- mov R2, lcd_cmd
- call LCD_read
- pop R2
- ret
-
-; -------------------------------------------------
-; LCD_read
-; -------------------------------------------------
-; R0 = output
-; R2 = register
-LCD_read: call _read_lcd
- swap R0
- push R0
- call _read_lcd
- pop R2
- or R0, R2
- ret
-
-; -------------------------------------------------
-; _write
-; -------------------------------------------------
-; R0 = input
-_write_lcd: push R1
-
- and R0, 0x0F
- mov R1, R0
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- mov R1, R0
- or R1, R2
- or R1, lcd_enable
- xout (lcd_port), R1
- call delay1us
-
- mov R1, R0
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- or R1, lcd_rd
- xout (lcd_port), R1
-
- pop R1
- ret
-
-; -------------------------------------------------
-; _read
-; -------------------------------------------------
-; R0 = output
-_read_lcd: push R1
-
- mov R1, lcd_rd
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- mov R1, lcd_rd
- or R1, R2
- or R1, lcd_enable
- xout (lcd_port), R1
- call delay1us
- xin R0, (lcd_port)
- and R0, 0x0F
-
- mov R1, lcd_rd
- or R1, R2
- xout (lcd_port), R1
- call delay1us
-
- pop R1
- ret
-
-
\ No newline at end of file
diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm
deleted file mode 100644
index 2f66e2a..0000000
--- a/lib/jasm/mul8x8.inc.jsm
+++ /dev/null
@@ -1,42 +0,0 @@
-; -------------------------------------------------
-; mul8x8.inc.jsm
-; -------------------------------------------------
-
-; -------------------------------------------------
-; Parameter:
-; R0 : operand 1
-; R1 : operand 2
-; Return:
-; R0 : product low
-; R1 : product high
-mul8x8: push R2
- push R3
- push R4
-
- mov R4, R1
- mov R1, 0
- mov R2, 0
- mov R3, 0
-
-loop1: cmp R4, 0x01
- jeq ende1
-
- shr R4
- jnc next1
-
- add R2, R0
- addc R3, R1
-
-next1: shl R0
- rolc R1
- jmp loop1
-
-ende1: add R0, R2
- addc R1, R3
-
- pop R4
- pop R3
- pop R2
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm
deleted file mode 100644
index df557b1..0000000
--- a/lib/jasm/uart.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; uart.inc.jsm
-; -------------------------------------------------
-; needs xmem-address definition for
-; - uart_status (Status register)
-; - uart_data (Data register)
-
-; -------------------------------------------------
-; sout
-; -------------------------------------------------
-; R0 = input
-sout: push R1
-sout1: xin R1, (uart_status)
- and R1, 0x02
- jnz sout1
- xout (uart_data), R0
- pop R1
- ret
-
-; -------------------------------------------------
-; sin
-; -------------------------------------------------
-; R0 = output
-sin: push R1
-sin1: xin R1, (uart_status)
- and R1, 0x10
- jz sin1
- xin R0, (uart_data)
- pop R1
- ret
-
-; -------------------------------------------------
diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm
deleted file mode 100644
index f354d7c..0000000
--- a/lib/jasm/utils.inc.jsm
+++ /dev/null
@@ -1,32 +0,0 @@
-; -------------------------------------------------
-; utils.inc.jsm
-; -------------------------------------------------
-
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value in lower nibble
-; Return
-; R0 : Hex character representing lower nibble
-nibble2hex: and R0, 0x0F
- cmp R0, 0x0A
- jlt isNum1
- add R0, 0x07
-isNum1: add R0, 0x30
- ret
-
-; -------------------------------------------------
-; Parameter
-; R0 : Bin value
-; Return
-; R0 : Hex character high
-; R1 : Hex character low
-bin2hex: push R0
- call nibble2hex
- mov R1, R0
- pop R0
- swap R0
- call nibble2hex
- ret
-
-; -------------------------------------------------
diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
deleted file mode 100644
index efc8e75..0000000
--- a/lib/misc/async_port_wb.vhd
+++ /dev/null
@@ -1,295 +0,0 @@
------------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.4 2009-01-18 21:44:57 Jens Exp $
------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.async_types.all;
-
- ------------------------------------------------------------------
-entity async_port_wb is
- Generic
- (
- addr_width : natural := 32;
- data_width : natural := 32;
- byte_sel_width : natural := 4;
- async_timespec : async_timespec_t
- );
- Port
- (
- CLK_I : in STD_LOGIC;
- RST_I : in STD_LOGIC;
- CYC_I : in STD_LOGIC;
- STB_I : in STD_LOGIC;
- WE_I : in STD_LOGIC;
- ACK_O : out STD_LOGIC;
- SRDY_O : out STD_LOGIC;
- MRDY_I : in STD_LOGIC;
- SEL_I : in unsigned(3 downto 0);
- ADDR_I : in unsigned(31 downto 0);
- DAT_I : in unsigned(31 downto 0);
- DAT_O : out unsigned(31 downto 0);
- async_a : out unsigned(addr_width-1 downto 0);
- async_d : inout unsigned(data_width-1 downto 0);
- async_cs : out std_logic;
- async_wr : out unsigned(byte_sel_width-1 downto 0);
- async_rd : out std_logic;
- async_rst : out std_logic
- );
-end async_port_wb;
-
-architecture Behavioral of async_port_wb is
-
- type async_t is record
- cs : std_logic;
- wr : std_logic;
- rd : std_logic;
- rst : std_logic;
- drive_d : std_logic;
- end record;
-
- type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
-
- signal s, sn : async_state_t;
- signal as : async_t;
- signal ack : std_logic;
- signal cc_rst : std_logic;
- signal cycle_cnt : natural range 0 to 15;
- signal cycle_reload : natural range 0 to 15;
- signal rdy : std_logic;
- signal rdyo : std_logic;
- signal en : std_logic;
- signal data_reg : unsigned(data_width-1 downto 0);
- signal byte_en : unsigned(byte_sel_width-1 downto 0);
-
- ------------------------------------------------------------------
- begin
-
- SRDY_O <= CYC_I and rdyo;
- en <= CYC_I and STB_I;
-
- proc_cycle_counter:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if cc_rst = '1' then
- cycle_cnt <= cycle_reload;
- elsif cycle_cnt /= 0 then
- cycle_cnt <= cycle_cnt - 1;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- proc_state_next:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- s <= start;
- else
- s <= sn;
- end if;
- end if;
- end process;
-
- proc_state:
- process(s, cycle_cnt, en, WE_I)
- begin
-
- cycle_reload <= async_timespec.ncyc_pulse_rst;
- cc_rst <= '0';
- as.rst <= '0';
- as.cs <= '0';
- as.wr <= '0';
- as.rd <= '0';
- as.drive_d <= '0';
- ack <= '0';
- rdy <= '0';
-
- sn <= s;
- case s is
-
- when start =>
- cc_rst <= '1';
- sn <= reset;
- when reset =>
- as.rst <= '1';
- if cycle_cnt = 0 then
- sn <= idle;
- end if;
- when idle =>
- rdy <= '1';
- if en = '1' then
- as.cs <= '1';
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_access-1;
- if WE_I = '0' then
- sn <= leadin_rd;
- else
- sn <= leadin_wr;
- end if;
- end if;
-
- when leadin_rd =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_pulse_rd-1;
- as.rd <= '1';
- sn <= read;
- end if;
-
- when leadin_wr =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_pulse_wr-1;
- as.wr <= '1';
- as.drive_d <= '1';
- sn <= write;
- end if;
-
- when read =>
- as.cs <= '1';
- as.rd <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_cs_hold-1;
--- as.rd <= '0';
- sn <= leadout_rd;
- ack <= '1';
- end if;
-
- when write =>
- as.drive_d <= '1';
- as.cs <= '1';
- as.wr <= '1';
- if cycle_cnt = 0 then
- as.wr <= '0';
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_cs_hold-1;
- sn <= leadout_wr;
--- ack <= '1';
- end if;
-
- when leadout_rd =>
- as.cs <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_release-1;
- sn <= release;
- as.cs <= '0';
- end if;
-
- when leadout_wr =>
- as.cs <= '1';
- as.drive_d <= '1';
- if cycle_cnt = 0 then
- cc_rst <= '1';
- cycle_reload <= async_timespec.ncyc_release-1;
- sn <= release;
- as.cs <= '0';
- end if;
-
- when release =>
- if cycle_cnt = 0 then
- sn <= idle;
- end if;
-
- when others =>
- sn <= idle;
-
- end case;
- end process;
-
- ------------------------------------------------------------------
- output_ctrl:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- async_cs <= (not async_timespec.pol_cs) xor as.cs;
- async_wr <= ((byte_sel_width-1 downto 0 => as.wr) and byte_en) xor (byte_sel_width-1 downto 0 => not async_timespec.pol_we);
- async_rd <= (not async_timespec.pol_oe) xor as.rd;
- async_rst <= (not async_timespec.pol_rst) xor as.rst;
- end if;
- end process;
-
- ------------------------------------------------------------------
- din_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if as.rd = '1' then
- DAT_O(data_width-1 downto 0) <= async_d;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_addr:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- async_a <= (others => '0');
- byte_en <= (others => '0');
- elsif en = '1' and rdy = '1' then
- async_a <= ADDR_I(addr_width-1 downto 0);
- byte_en <= SEL_I(byte_sel_width-1 downto 0);
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- data_register:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if en = '1' and rdy = '1' then
- data_reg <= DAT_I(data_width-1 downto 0);
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_SRDY:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- rdyo <= '1';
- elsif en = '1' then
- rdyo <= rdy and not rdyo;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_ACK:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- if RST_I = '1' then
- ACK_O <= '0';
- else
- ACK_O <= ack;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
- output_data:
- process(CLK_I)
- begin
- if rising_edge(CLK_I) then
- async_d <= (others => 'Z');
- if as.drive_d = '1' then
- async_d <= data_reg;
- end if;
- end if;
- end process;
-
- ------------------------------------------------------------------
-
-end Behavioral;
diff --git a/lib/misc/async_types.vhd b/lib/misc/async_types.vhd
deleted file mode 100644
index af6eb9a..0000000
--- a/lib/misc/async_types.vhd
+++ /dev/null
@@ -1,43 +0,0 @@
--------------------------------------------------------------------------
--- Project: MIPS System controller
--- This file:
---
--- Copyright (C) 2008 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see
-#include
-#include
-#include
-
-#define INT8 char
-#define INT16 short
-#define INT32 long
-#define UINT8 unsigned char
-#define UINT16 unsigned short
-#define UINT32 unsigned long
-#define INT int
-#define UINT unsigned int
-#define FLOAT32 float
-#define FLOAT64 double
-
-#define SDRAM_BASE 0x40000000
-#define FLASH_OFFSET 0x00000000
-
-// --------------------------------------------------------------
-typedef struct _sflash_img_hdr_t
-{
- UINT8 magic[4];
- UINT32 target_addr;
- UINT32 img_offset;
- UINT32 img_size;
- UINT32 hdr_next;
- UINT8 img_name[128];
- UINT8 res[108];
-
-} flash_img_hdr_t;
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
- int i, size;
-
- size = strlen(pSrc);
-
- while(pSrc[size] != '.')
- size--;
-
- for (i=0; i < size; i++)
- pDst[i] = pSrc[i];
-
- pDst[i] = 0;
-
-}
-
-// --------------------------------------------------------------
-int main(int argc, char *argv[])
-{
- char *pFilenameIn;
- char name_flash[1024];
- char name_prj[1024];
- char *pBuf;
- flash_img_hdr_t img_hdr = {0};
-
- FILE *pFile;
- int filesize;
- long start, end;
- int i;
-
- if (argc < 2)
- {
- fprintf(stderr, "Usage: flashgen
-#include
-#include
-#include
-
-#define ARCH_NAME "data"
-#define ENT_NAME "ram"
-#define JTAG_ADDR_WIDTH 16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
- int i, size;
-
- size = strlen(pSrc);
-
- while(pSrc[size] != '.')
- size--;
-
- for (i=0; i < size; i++)
- pDst[i] = pSrc[i];
-
- pDst[i] = 0;
-
-}
-
-int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, filesize, romsize;
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "LIBRARY IEEE;\n");
- fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
- fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
- fprintf(pFileOut, "\tPort\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
- fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "END %s;\n", ENT_NAME);
- fprintf(pFileOut, "\n");
-
-
- fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
- fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
- fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- word = 0;
- for (; i < romsize; i += sizeof(int))
- {
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "begin\n", ARCH_NAME);
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(clk)\n");
- fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
- fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
- fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
- return 0;
-}
-
-int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, filesize, romsize;
-
- char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "LIBRARY IEEE;\n");
- fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
- fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "library UNISIM;\n");
- fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
- fprintf(pFileOut, "\tPort\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "END %s;\n", ENT_NAME);
- fprintf(pFileOut, "\n");
-
-
- fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
- fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
- fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
- fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
- fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
- fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
- fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- word = 0;
- for (; i < romsize; i += sizeof(int))
- {
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "begin\n", ARCH_NAME);
-
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(clk)\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
- fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "\n");
- fputs(tpl, pFileOut);
-
- fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
- fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
- fprintf(pFileOut, "\t\t\telse\n");
- fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "end %s;\n", ARCH_NAME);
- return 0;
-}
-
-int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, word_addr, filesize, romsize;
- char binstr_addr[33];
- char binstr_data[33];
-
- char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fputs(tpl, pFileOut);
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
- fprintf(pFileOut, "# ---------------------------------------------------------------\n");
- fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
- fprintf(pFileOut, "# User 2\n");
- fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
-
- word_addr = 0;
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
- word_addr++;
- }
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
- fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
- fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
- fprintf(pFileOut, "exit\n");
-
- return 0;
-}
-
-int main(int argc, char *argv[])
-{
- char *pFilenameIn;
- char name_prj[1024];
- char name_rom_tcl[1024];
- char name_rom[1024];
- char name_rom_v4ld[1024];
-
- FILE *pFileIn;
- int filesize, romsize, nbits_addr, nbits_data;
- long start, end;
- int word, i;
-
- if (argc < 2)
- {
- fprintf(stderr, "Usage: ramgen \n");
- return 1;
- }
-
- pFilenameIn = argv[1];
- if (argc == 3)
- nbits_addr = atoi(argv[2]);
-
-
- basename(pFilenameIn, name_prj);
- sprintf(name_rom, "%s.vhd", name_prj);
- sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
- sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
- SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
- SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
- return 0;
-}
-
diff --git a/projects/mips_sys/tools/src/romgen.c b/projects/mips_sys/tools/src/romgen.c
deleted file mode 100644
index a59e705..0000000
--- a/projects/mips_sys/tools/src/romgen.c
+++ /dev/null
@@ -1,368 +0,0 @@
-#include
-#include
-#include
-#include
-
-#define ARCH_NAME "data"
-#define ENT_NAME "rom"
-#define JTAG_ADDR_WIDTH 16
-
-// --------------------------------------------------------------
-void basename(char *pSrc, char *pDst)
-{
- int i, size;
-
- size = strlen(pSrc);
-
- while(pSrc[size] != '.')
- size--;
-
- for (i=0; i < size; i++)
- pDst[i] = pSrc[i];
-
- pDst[i] = 0;
-
-}
-
-int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, filesize, romsize;
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "LIBRARY IEEE;\n");
- fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
- fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
- fprintf(pFileOut, "\tPort\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "END %s;\n", ENT_NAME);
- fprintf(pFileOut, "\n");
-
-
- fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
- fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- word = 0;
- for (; i < romsize; i += sizeof(int))
- {
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "begin\n", ARCH_NAME);
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(clk)\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
- fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "end %s;\n", ARCH_NAME);
-
- return 0;
-}
-
-int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, filesize, romsize;
-
- char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "LIBRARY IEEE;\n");
- fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
- fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "library UNISIM;\n");
- fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
- fprintf(pFileOut, "\tPort\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
- fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "END %s;\n", ENT_NAME);
- fprintf(pFileOut, "\n");
-
-
- fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
-
- fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
- fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
- fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
- fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
- fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
- fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
- fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
- fprintf(pFileOut, "\t(\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- word = 0;
- for (; i < romsize; i += sizeof(int))
- {
- fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
- if (i < (romsize-sizeof(int)))
- fprintf(pFileOut, ", -- %8.8X\n", i);
- else
- fprintf(pFileOut, " -- %8.8X\n", i);
- }
- fprintf(pFileOut, "\t);\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "begin\n", ARCH_NAME);
-
- fprintf(pFileOut, "\n");
- fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(clk)\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
- fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "\n");
- fputs(tpl, pFileOut);
-
- fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
- fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
- fprintf(pFileOut, "\tbegin\n");
- fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
- fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
- fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
- fprintf(pFileOut, "\t\t\telse\n");
- fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
- fprintf(pFileOut, "\t\t\tend if;\n");
- fprintf(pFileOut, "\t\tend if;\n");
- fprintf(pFileOut, "\tend process;\n");
- fprintf(pFileOut, "\n");
-
- fprintf(pFileOut, "end %s;\n", ARCH_NAME);
- return 0;
-}
-
-int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
-{
- FILE *pFileIn, *pFileOut;
- long start, end;
- int i, word, word_addr, filesize, romsize;
- char binstr_addr[33];
- char binstr_data[33];
-
- char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
-
- pFileIn = fopen(pFilenameIn, "rb");
- if (!pFileIn)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameIn);
- return 1;
- }
-
- pFileOut = fopen(pFilenameOut, "wb");
- if (!pFileOut)
- {
- fprintf(stderr, "Error opening file %s\n", pFilenameOut);
- return 1;
- }
-
- fseek(pFileIn, 0, SEEK_SET);
- start = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_END);
- end = ftell(pFileIn);
- fseek(pFileIn, 0, SEEK_SET);
-
- filesize = (end-start);
- romsize = (int)pow(2, nbits_addr+2);
-
- // -------------------------------------------------------------------------
- // Header
-
- // -------------------------------------------------------------------------
- fputs(tpl, pFileOut);
-
- // -------------------------------------------------------------------------
- // ROM part
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
- fprintf(pFileOut, "# ---------------------------------------------------------------\n");
- fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
- fprintf(pFileOut, "# User 1\n");
- fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
-
- word_addr = 0;
- for (i=0; i < filesize; i += sizeof(int))
- {
- fread(&word, 1, sizeof(int), pFileIn);
- fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
- word_addr++;
- }
- fprintf(pFileOut, "\n");
-
- // -------------------------------------------------------------------------
- // Trailer
- // -------------------------------------------------------------------------
- fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
- fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
- fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
- fprintf(pFileOut, "exit\n");
-
- return 0;
-}
-
-int main(int argc, char *argv[])
-{
- char *pFilenameIn;
- char name_prj[1024];
- char name_rom[1024];
- char name_rom_v4ld[1024];
- char name_rom_tcl[1024];
-
- FILE *pFileIn;
- int filesize, romsize, nbits_addr, nbits_data;
- long start, end;
- int word, i;
-
- if (argc < 2)
- {
- fprintf(stderr, "Usage: romgen \n");
- return 1;
- }
-
- pFilenameIn = argv[1];
- if (argc == 3)
- nbits_addr = atoi(argv[2]);
-
-
- basename(pFilenameIn, name_prj);
- sprintf(name_rom, "%s.vhd", name_prj);
- sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
- sprintf(name_rom_tcl, "%s.tcl", name_prj);
-
- SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
- SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
- SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
-
-
- return 0;
-}
-