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- added 'page_mode_en' for async_port

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git-svn-id: http://moon:8086/svn/vhdl/trunk@551 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-28 22:45:36 +00:00
parent 9ea208eaf0
commit a3d54edf64
3 changed files with 452 additions and 435 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+5
View File
@@ -98,6 +98,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
signal sram_d : unsigned(31 downto 0);
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
signal flash_d : unsigned(31 downto 0);
signal flash_page_mode_en : std_logic;
signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0);
@@ -132,8 +133,10 @@ mem_mux:
process(ADDR_O)
begin
mem_area <= mem_dead;
flash_page_mode_en <= '0';
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
flash_page_mode_en <= '1';
elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
@@ -281,6 +284,7 @@ inst_flash_port : entity work.async_port_wb
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_flash,
page_mode_en => flash_page_mode_en,
async_a => flash_a,
async_d => flash_d,
async_cs => flash_cs_n,
@@ -312,6 +316,7 @@ inst_sram_port : entity work.async_port_wb
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_O_sram,
page_mode_en => '0',
async_a => sram_a,
async_d => sram_d,
async_cs => sram_cs_n,
projects/mips_sys/src/mips_sys.vhd
+8 -1
View File
@@ -204,6 +204,7 @@ ARCHITECTURE behavior OF mips_sys IS
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
@@ -326,7 +327,9 @@ ARCHITECTURE behavior OF mips_sys IS
signal usb_addr : unsigned(31 downto 0);
signal flash_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic;
signal mem_mapped_io : std_logic;
signal flash_rstn : std_logic;
signal flash_page_mode_en : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -458,6 +461,7 @@ BEGIN
sys_flash_byten <= '1';
usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O;
@@ -519,9 +523,11 @@ mem_mux:
process(ADDR_O)
begin
mem_area <= mem_dead;
mem_mapped_io <= '0';
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"A" then
mem_mapped_io <= '1';
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio;
@@ -543,7 +549,6 @@ mem_mux:
end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram;
end if;
@@ -707,6 +712,7 @@ inst_flash_port : async_port_wb
ADDR_I => flash_addr,
DAT_I => MDAT_O,
DAT_O => SDAT_O_flash,
page_mode_en => flash_page_mode_en,
async_a => sys_flash_a,
async_d => sys_flash_d,
async_cs => sys_flash_ce,
@@ -738,6 +744,7 @@ inst_usb_port : async_port_wb
ADDR_I => usb_addr,
DAT_I => MDAT_O,
DAT_O => SDAT_O_usb,
page_mode_en => '0',
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,
projects/mips_sys/src/mips_sys_sim.vhd
+5
View File
@@ -213,6 +213,7 @@ ARCHITECTURE behavior OF mips_sys IS
ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic;
@@ -382,6 +383,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_we_n : std_logic;
signal flash_d_drv : std_logic;
signal flash_bsy : std_logic;
signal flash_page_mode_en : std_logic;
-- Arbiter
constant ARB_MAX_MASTER : natural := 2;
@@ -599,8 +601,10 @@ mem_mux:
process(ADDR_O)
begin
mem_area <= mem_dead;
flash_page_mode_en <= '0';
if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash;
flash_page_mode_en <= '1';
elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then
@@ -834,6 +838,7 @@ inst_usb_port : async_port_wb
ADDR_I => ADDR_I_usb,
DAT_I => MDAT_O,
DAT_O => SDAT_O_usb,
page_mode_en => '0',
async_a => sys_usb_a,
async_d => sys_usb_d,
async_cs => sys_usb_csn,