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- added 'page_mode_en' for async_port

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git-svn-id: http://moon:8086/svn/vhdl/trunk@551 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-28 22:45:36 +00:00
parent 9ea208eaf0
commit a3d54edf64
3 changed files with 452 additions and 435 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/tb_mips_top.vhd
+160 -155
View File
@@ -41,73 +41,74 @@ ARCHITECTURE behavior OF tb_mips_top IS
constant SRAM_ADDR_WIDTH : integer := 17; -- bits constant SRAM_ADDR_WIDTH : integer := 17; -- bits
constant FLASH_ADDR_WIDTH : integer := 17; -- bits constant FLASH_ADDR_WIDTH : integer := 17; -- bits
signal debug : unsigned(1 downto 0); signal debug : unsigned(1 downto 0);
-- Master -- Master
signal nmi : STD_LOGIC := '0'; signal nmi : STD_LOGIC := '0';
signal rst : STD_LOGIC := '1'; signal rst : STD_LOGIC := '1';
signal clk : STD_LOGIC := '0'; signal clk : STD_LOGIC := '0';
signal eb : STD_LOGIC := '1'; signal eb : STD_LOGIC := '1';
signal ACK_I : STD_LOGIC := '0'; signal ACK_I : STD_LOGIC := '0';
signal SRDY_I : STD_LOGIC := '0'; signal SRDY_I : STD_LOGIC := '0';
signal ADDR_O : unsigned(31 downto 0); signal ADDR_O : unsigned(31 downto 0);
signal DAT_I : unsigned(31 downto 0) := (others => '0'); signal DAT_I : unsigned(31 downto 0) := (others => '0');
signal DAT_O : unsigned(31 downto 0); signal DAT_O : unsigned(31 downto 0);
signal WE_O : STD_LOGIC; signal WE_O : STD_LOGIC;
signal SEL_O : unsigned(3 downto 0); signal SEL_O : unsigned(3 downto 0);
signal CYC_O : STD_LOGIC; signal CYC_O : STD_LOGIC;
signal STB_O : STD_LOGIC; signal STB_O : STD_LOGIC;
signal MRDY_O : STD_LOGIC; signal MRDY_O : STD_LOGIC;
signal INT : unsigned (5 downto 0) := (others => '0'); signal INT : unsigned (5 downto 0) := (others => '0');
-- Slaves -- Slaves
signal CYC_I_rom : std_logic; signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic; signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic; signal SRDY_O_rom : std_logic;
signal DAT_O_rom : unsigned(31 downto 0); signal DAT_O_rom : unsigned(31 downto 0);
signal CYC_I_flash : std_logic; signal CYC_I_flash : std_logic;
signal ACK_O_flash : std_logic; signal ACK_O_flash : std_logic;
signal SRDY_O_flash : std_logic; signal SRDY_O_flash : std_logic;
signal DAT_O_flash : unsigned(31 downto 0); signal DAT_O_flash : unsigned(31 downto 0);
signal CYC_I_sram : std_logic; signal CYC_I_sram : std_logic;
signal ACK_O_sram : std_logic; signal ACK_O_sram : std_logic;
signal SRDY_O_sram : std_logic; signal SRDY_O_sram : std_logic;
signal DAT_O_sram : unsigned(31 downto 0); signal DAT_O_sram : unsigned(31 downto 0);
signal CYC_I_gpio : std_logic; signal CYC_I_gpio : std_logic;
signal ACK_O_gpio : std_logic; signal ACK_O_gpio : std_logic;
signal SRDY_O_gpio : std_logic; signal SRDY_O_gpio : std_logic;
signal DAT_O_gpio : unsigned(31 downto 0); signal DAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart : std_logic; signal CYC_I_uart : std_logic;
signal ACK_O_uart : std_logic; signal ACK_O_uart : std_logic;
signal SRDY_O_uart : std_logic; signal SRDY_O_uart : std_logic;
signal DAT_O_uart : unsigned(31 downto 0); signal DAT_O_uart : unsigned(31 downto 0);
signal flash_cs_n : std_logic; signal flash_cs_n : std_logic;
signal flash_we_n : std_logic; signal flash_we_n : std_logic;
signal flash_oe_n : std_logic; signal flash_oe_n : std_logic;
signal flash_be_n : unsigned(3 downto 0); signal flash_be_n : unsigned(3 downto 0);
signal sram_cs_n : std_logic; signal sram_cs_n : std_logic;
signal sram_be_n : unsigned(3 downto 0); signal sram_be_n : unsigned(3 downto 0);
signal sram_wr_n : std_logic; signal sram_wr_n : std_logic;
signal sram_oe_n : std_logic; signal sram_oe_n : std_logic;
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0); signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
signal sram_d : unsigned(31 downto 0); signal sram_d : unsigned(31 downto 0);
signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0); signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
signal flash_d : unsigned(31 downto 0); signal flash_d : unsigned(31 downto 0);
signal flash_page_mode_en : std_logic;
signal gpo0 : unsigned(31 downto 0); signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0); signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0) := (others => '0'); signal gpi0 : unsigned(31 downto 0) := (others => '0');
signal gpi1 : unsigned(31 downto 0) := (others => '0'); signal gpi1 : unsigned(31 downto 0) := (others => '0');
signal int_timer : std_logic; signal int_timer : std_logic;
signal int_uart : std_logic; signal int_uart : std_logic;
signal rx : std_logic := '1'; signal rx : std_logic := '1';
signal tx : std_logic; signal tx : std_logic;
type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart); type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
signal mem_area : mem_area_t; signal mem_area : mem_area_t;
@@ -131,9 +132,11 @@ CLK_GEN: process
mem_mux: mem_mux:
process(ADDR_O) process(ADDR_O)
begin begin
mem_area <= mem_dead; mem_area <= mem_dead;
flash_page_mode_en <= '0';
if ADDR_O(31 downto 28) = X"0" then if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash; mem_area <= mem_flash;
flash_page_mode_en <= '1';
elsif ADDR_O(31 downto 28) = X"A" then elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then if ADDR_O(18 downto 16) = "000" then
@@ -197,27 +200,27 @@ signal_mux:
uut: entity work.mips_top uut: entity work.mips_top
GENERIC MAP GENERIC MAP
( (
icache_size => 1024, -- words icache_size => 1024, -- words
dcache_size => 1024 -- words dcache_size => 1024 -- words
) )
PORT MAP PORT MAP
( (
debug => debug, debug => debug,
eb => eb, eb => eb,
RST_I => rst, RST_I => rst,
CLK_I => clk, CLK_I => clk,
ACK_I => ACK_I, ACK_I => ACK_I,
SRDY_I => SRDY_I, SRDY_I => SRDY_I,
ADDR_O => ADDR_O, ADDR_O => ADDR_O,
DAT_I => DAT_I, DAT_I => DAT_I,
DAT_O => DAT_O, DAT_O => DAT_O,
WE_O => WE_O, WE_O => WE_O,
SEL_O => SEL_O, SEL_O => SEL_O,
CYC_O => CYC_O, CYC_O => CYC_O,
STB_O => STB_O, STB_O => STB_O,
MRDY_O => MRDY_O, MRDY_O => MRDY_O,
INT => INT, INT => INT,
nmi => nmi nmi => nmi
); );
INT(1) <= int_uart; INT(1) <= int_uart;
INT(5) <= int_timer; INT(5) <= int_timer;
@@ -225,38 +228,38 @@ uut: entity work.mips_top
inst_rom : entity work.rom_wb inst_rom : entity work.rom_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_rom, CYC_I => CYC_I_rom,
STB_I => STB_O, STB_I => STB_O,
ACK_O => ACK_O_rom, ACK_O => ACK_O_rom,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom, SRDY_O => SRDY_O_rom,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_O => DAT_O_rom DAT_O => DAT_O_rom
); );
inst_gpio : entity work.gpio_wb inst_gpio : entity work.gpio_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_gpio, CYC_I => CYC_I_gpio,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_gpio, ACK_O => ACK_O_gpio,
SRDY_O => SRDY_O_gpio, SRDY_O => SRDY_O_gpio,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => DAT_O, DAT_I => DAT_O,
DAT_O => DAT_O_gpio, DAT_O => DAT_O_gpio,
INT_TIM_O => int_timer, INT_TIM_O => int_timer,
sys_gpo0 => gpo0, sys_gpo0 => gpo0,
sys_gpo1 => gpo1, sys_gpo1 => gpo1,
sys_gpi0 => gpi0, sys_gpi0 => gpi0,
sys_gpi1 => gpi1 sys_gpi1 => gpi1
); );
inst_flash_port : entity work.async_port_wb inst_flash_port : entity work.async_port_wb
@@ -269,25 +272,26 @@ inst_flash_port : entity work.async_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_flash, CYC_I => CYC_I_flash,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_flash, ACK_O => ACK_O_flash,
SRDY_O => SRDY_O_flash, SRDY_O => SRDY_O_flash,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SEL_I => SEL_O, SEL_I => SEL_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => DAT_O, DAT_I => DAT_O,
DAT_O => DAT_O_flash, DAT_O => DAT_O_flash,
async_a => flash_a, page_mode_en => flash_page_mode_en,
async_d => flash_d, async_a => flash_a,
async_cs => flash_cs_n, async_d => flash_d,
async_wr => flash_we_n, async_cs => flash_cs_n,
async_rd => flash_oe_n, async_wr => flash_we_n,
async_be => flash_be_n, async_rd => flash_oe_n,
async_rst => open async_be => flash_be_n,
async_rst => open
); );
inst_sram_port : entity work.async_port_wb inst_sram_port : entity work.async_port_wb
@@ -300,45 +304,46 @@ inst_sram_port : entity work.async_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_sram, CYC_I => CYC_I_sram,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_sram, ACK_O => ACK_O_sram,
SRDY_O => SRDY_O_sram, SRDY_O => SRDY_O_sram,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SEL_I => SEL_O, SEL_I => SEL_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => DAT_O, DAT_I => DAT_O,
DAT_O => DAT_O_sram, DAT_O => DAT_O_sram,
async_a => sram_a, page_mode_en => '0',
async_d => sram_d, async_a => sram_a,
async_cs => sram_cs_n, async_d => sram_d,
async_wr => sram_wr_n, async_cs => sram_cs_n,
async_rd => sram_oe_n, async_wr => sram_wr_n,
async_be => sram_be_n, async_rd => sram_oe_n,
async_rst => open async_be => sram_be_n,
async_rst => open
); );
inst_uart : entity work.uart_wb inst_uart : entity work.uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_uart, CYC_I => CYC_I_uart,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_uart, ACK_O => ACK_O_uart,
SRDY_O => SRDY_O_uart, SRDY_O => SRDY_O_uart,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => DAT_O, DAT_I => DAT_O,
DAT_O => DAT_O_uart, DAT_O => DAT_O_uart,
INT_O => int_uart, INT_O => int_uart,
ser_rx => rx, ser_rx => rx,
ser_tx => tx ser_tx => tx
); );
------------------------------------------------------------------ ------------------------------------------------------------------
projects/mips_sys/src/mips_sys.vhd
+284 -277
View File
@@ -132,22 +132,22 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT mips_top COMPONENT mips_top
Port Port
( (
debug : out unsigned(1 downto 0); debug : out unsigned(1 downto 0);
eb : in STD_LOGIC; eb : in STD_LOGIC;
nmi : in STD_LOGIC; nmi : in STD_LOGIC;
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
ACK_I : in STD_LOGIC; ACK_I : in STD_LOGIC;
SRDY_I : in STD_LOGIC; SRDY_I : in STD_LOGIC;
ADDR_O : out word_t; ADDR_O : out word_t;
DAT_I : in word_t; DAT_I : in word_t;
DAT_O : out word_t; DAT_O : out word_t;
WE_O : out STD_LOGIC; WE_O : out STD_LOGIC;
SEL_O : out unsigned(3 downto 0); SEL_O : out unsigned(3 downto 0);
CYC_O : out STD_LOGIC; CYC_O : out STD_LOGIC;
STB_O : out STD_LOGIC; STB_O : out STD_LOGIC;
MRDY_O : out STD_LOGIC; MRDY_O : out STD_LOGIC;
INT : in unsigned (5 downto 0) INT : in unsigned (5 downto 0)
); );
END COMPONENT; END COMPONENT;
@@ -155,30 +155,30 @@ ARCHITECTURE behavior OF mips_sys IS
COMPONENT rom_wb COMPONENT rom_wb
PORT PORT
( (
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC; CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC; STB_I : in STD_LOGIC;
ACK_O : out STD_LOGIC; ACK_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC; MRDY_I : in STD_LOGIC;
SRDY_O : out STD_LOGIC; SRDY_O : out STD_LOGIC;
ADDR_I : in unsigned(31 downto 0); ADDR_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0) DAT_O : out unsigned(31 downto 0)
); );
END COMPONENT; END COMPONENT;
COMPONENT lcd_port COMPONENT lcd_port
PORT PORT
( (
rst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
we : in std_logic; we : in std_logic;
din : in unsigned(7 downto 0); din : in unsigned(7 downto 0);
dout : out unsigned(7 downto 0); dout : out unsigned(7 downto 0);
lcd_d : inout unsigned(3 downto 0); lcd_d : inout unsigned(3 downto 0);
lcd_e : out std_logic; lcd_e : out std_logic;
lcd_rs : out std_logic; lcd_rs : out std_logic;
lcd_rw : out std_logic lcd_rw : out std_logic
); );
END COMPONENT; END COMPONENT;
@@ -192,25 +192,26 @@ ARCHITECTURE behavior OF mips_sys IS
); );
PORT PORT
( (
CLK_I : in STD_LOGIC; CLK_I : in STD_LOGIC;
RST_I : in STD_LOGIC; RST_I : in STD_LOGIC;
CYC_I : in STD_LOGIC; CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC; STB_I : in STD_LOGIC;
WE_I : in STD_LOGIC; WE_I : in STD_LOGIC;
ACK_O : out STD_LOGIC; ACK_O : out STD_LOGIC;
SRDY_O : out STD_LOGIC; SRDY_O : out STD_LOGIC;
MRDY_I : in STD_LOGIC; MRDY_I : in STD_LOGIC;
SEL_I : in unsigned(3 downto 0); SEL_I : in unsigned(3 downto 0);
ADDR_I : in unsigned(31 downto 0); ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0);
async_a : out unsigned(addr_width-1 downto 0); page_mode_en : in STD_LOGIC;
async_d : inout unsigned(data_width-1 downto 0); async_a : out unsigned(addr_width-1 downto 0);
async_cs : out std_logic; async_d : inout unsigned(data_width-1 downto 0);
async_wr : out std_logic; async_cs : out std_logic;
async_rd : out std_logic; async_wr : out std_logic;
async_be : out unsigned(byte_sel_width-1 downto 0); async_rd : out std_logic;
async_rst : out std_logic async_be : out unsigned(byte_sel_width-1 downto 0);
async_rst : out std_logic
); );
END COMPONENT; END COMPONENT;
@@ -310,123 +311,125 @@ ARCHITECTURE behavior OF mips_sys IS
); );
END COMPONENT; END COMPONENT;
signal nmi : std_logic; signal nmi : std_logic;
signal rst : std_logic; signal rst : std_logic;
signal clk : std_logic; signal clk : std_logic;
signal eb : std_logic; signal eb : std_logic;
signal clk270 : std_logic; signal clk270 : std_logic;
signal clk270var : std_logic; signal clk270var : std_logic;
signal rst_in : std_logic; signal rst_in : std_logic;
signal int_timer : std_logic; signal int_timer : std_logic;
signal int_uart0 : std_logic; signal int_uart0 : std_logic;
signal int_uart1 : std_logic; signal int_uart1 : std_logic;
signal uart1_tx : std_logic; signal uart1_tx : std_logic;
signal uart1_rx : std_logic; signal uart1_rx : std_logic;
signal locked : std_logic; signal locked : std_logic;
signal usb_addr : unsigned(31 downto 0); signal usb_addr : unsigned(31 downto 0);
signal flash_addr : unsigned(31 downto 0); signal flash_addr : unsigned(31 downto 0);
signal ac97_rstn : std_logic; signal ac97_rstn : std_logic;
signal flash_rstn : std_logic; signal mem_mapped_io : std_logic;
signal flash_rstn : std_logic;
signal flash_page_mode_en : std_logic;
-- Arbiter -- Arbiter
constant ARB_MAX_MASTER : natural := 2; constant ARB_MAX_MASTER : natural := 2;
signal arb_idx : natural range 0 to ARB_MAX_MASTER-1; signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0); signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0);
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0); signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
-- J-Bus signals -- J-Bus signals
signal INT : unsigned(5 downto 0); signal INT : unsigned(5 downto 0);
signal MDAT_I : word_t; signal MDAT_I : word_t;
signal MDAT_O : word_t; signal MDAT_O : word_t;
signal ADDR_O : word_t; signal ADDR_O : word_t;
signal SEL_O : unsigned(3 downto 0); signal SEL_O : unsigned(3 downto 0);
signal WE_O : std_logic; signal WE_O : std_logic;
signal CYC_O : std_logic; signal CYC_O : std_logic;
signal STB_O : std_logic; signal STB_O : std_logic;
signal ACK_I : std_logic; signal ACK_I : std_logic;
signal SRDY_I : std_logic; signal SRDY_I : std_logic;
signal MRDY_O : std_logic; signal MRDY_O : std_logic;
-- CPU Master -- CPU Master
signal MRDY_O_cpu : std_logic; signal MRDY_O_cpu : std_logic;
signal MDAT_O_cpu : word_t; signal MDAT_O_cpu : word_t;
signal ADDR_O_cpu : word_t; signal ADDR_O_cpu : word_t;
signal SEL_O_cpu : unsigned(3 downto 0); signal SEL_O_cpu : unsigned(3 downto 0);
signal WE_O_cpu : std_logic; signal WE_O_cpu : std_logic;
signal CYC_O_cpu : std_logic; signal CYC_O_cpu : std_logic;
signal STB_O_cpu : std_logic; signal STB_O_cpu : std_logic;
signal SRDY_I_cpu : std_logic; signal SRDY_I_cpu : std_logic;
signal ACK_I_cpu : std_logic; signal ACK_I_cpu : std_logic;
-- VGA Master -- VGA Master
signal MRDY_O_vga : std_logic; signal MRDY_O_vga : std_logic;
signal ADDR_O_vga : word_t; signal ADDR_O_vga : word_t;
signal SEL_O_vga : unsigned(7 downto 0); signal SEL_O_vga : unsigned(7 downto 0);
signal WE_O_vga : std_logic; signal WE_O_vga : std_logic;
signal CYC_O_vga : std_logic; signal CYC_O_vga : std_logic;
signal STB_O_vga : std_logic; signal STB_O_vga : std_logic;
signal SRDY_I_vga : std_logic; signal SRDY_I_vga : std_logic;
signal ACK_I_vga : std_logic; signal ACK_I_vga : std_logic;
signal MDAT_I_vga : unsigned(63 downto 0); signal MDAT_I_vga : unsigned(63 downto 0);
signal MDAT_O_vga : unsigned(63 downto 0); signal MDAT_O_vga : unsigned(63 downto 0);
-- Slaves -- Slaves
signal CYC_I_flash : std_logic; signal CYC_I_flash : std_logic;
signal ACK_O_flash : std_logic; signal ACK_O_flash : std_logic;
signal SRDY_O_flash : std_logic; signal SRDY_O_flash : std_logic;
signal SDAT_O_flash : unsigned(31 downto 0); signal SDAT_O_flash : unsigned(31 downto 0);
signal CYC_I_usb : std_logic; signal CYC_I_usb : std_logic;
signal ACK_O_usb : std_logic; signal ACK_O_usb : std_logic;
signal SRDY_O_usb : std_logic; signal SRDY_O_usb : std_logic;
signal SDAT_O_usb : unsigned(31 downto 0); signal SDAT_O_usb : unsigned(31 downto 0);
signal CYC_I_sdram : std_logic; signal CYC_I_sdram : std_logic;
signal ACK_O_sdram : std_logic; signal ACK_O_sdram : std_logic;
signal SRDY_O_sdram : std_logic; signal SRDY_O_sdram : std_logic;
signal SDAT_O_sdram : unsigned(63 downto 0); signal SDAT_O_sdram : unsigned(63 downto 0);
signal SDAT_I_sdram : unsigned(63 downto 0); signal SDAT_I_sdram : unsigned(63 downto 0);
signal SEL_I_sdram : unsigned(7 downto 0); signal SEL_I_sdram : unsigned(7 downto 0);
signal CYC_I_rom : std_logic; signal CYC_I_rom : std_logic;
signal ACK_O_rom : std_logic; signal ACK_O_rom : std_logic;
signal SRDY_O_rom : std_logic; signal SRDY_O_rom : std_logic;
signal SDAT_O_rom : unsigned(31 downto 0); signal SDAT_O_rom : unsigned(31 downto 0);
signal CYC_I_gpio : std_logic; signal CYC_I_gpio : std_logic;
signal ACK_O_gpio : std_logic; signal ACK_O_gpio : std_logic;
signal SRDY_O_gpio : std_logic; signal SRDY_O_gpio : std_logic;
signal SDAT_O_gpio : unsigned(31 downto 0); signal SDAT_O_gpio : unsigned(31 downto 0);
signal CYC_I_uart0 : std_logic; signal CYC_I_uart0 : std_logic;
signal ACK_O_uart0 : std_logic; signal ACK_O_uart0 : std_logic;
signal SRDY_O_uart0 : std_logic; signal SRDY_O_uart0 : std_logic;
signal SDAT_O_uart0 : unsigned(31 downto 0); signal SDAT_O_uart0 : unsigned(31 downto 0);
signal CYC_I_uart1 : std_logic; signal CYC_I_uart1 : std_logic;
signal ACK_O_uart1 : std_logic; signal ACK_O_uart1 : std_logic;
signal SRDY_O_uart1 : std_logic; signal SRDY_O_uart1 : std_logic;
signal SDAT_O_uart1 : unsigned(31 downto 0); signal SDAT_O_uart1 : unsigned(31 downto 0);
signal CYC_I_vga : std_logic; signal CYC_I_vga : std_logic;
signal ACK_O_vga : std_logic; signal ACK_O_vga : std_logic;
signal SRDY_O_vga : std_logic; signal SRDY_O_vga : std_logic;
signal SDAT_O_vga : unsigned(31 downto 0); signal SDAT_O_vga : unsigned(31 downto 0);
signal INT_O_ac97 : std_logic; signal INT_O_ac97 : std_logic;
signal CYC_I_ac97 : std_logic; signal CYC_I_ac97 : std_logic;
signal ACK_O_ac97 : std_logic; signal ACK_O_ac97 : std_logic;
signal SRDY_O_ac97 : std_logic; signal SRDY_O_ac97 : std_logic;
signal SDAT_O_ac97 : unsigned(31 downto 0); signal SDAT_O_ac97 : unsigned(31 downto 0);
signal gpo0 : unsigned(31 downto 0); signal gpo0 : unsigned(31 downto 0);
signal gpo1 : unsigned(31 downto 0); signal gpo1 : unsigned(31 downto 0);
signal gpi0 : unsigned(31 downto 0); signal gpi0 : unsigned(31 downto 0);
signal gpi1 : unsigned(31 downto 0); signal gpi1 : unsigned(31 downto 0);
signal debug : unsigned(1 downto 0); signal debug : unsigned(1 downto 0);
-- DDR SDRAM -- DDR SDRAM
constant BURST_LEN : natural := 2; constant BURST_LEN : natural := 2;
-- attribute rom_style: string; -- attribute rom_style: string;
@@ -446,27 +449,28 @@ BEGIN
-- 2 : AC97 interrupt enable -- 2 : AC97 interrupt enable
-- others : reserved -- others : reserved
------------------------------------ ------------------------------------
eb <= sys_dip(7); eb <= sys_dip(7);
gpi0(4 downto 0) <= sys_btn; gpi0(4 downto 0) <= sys_btn;
gpi1(7 downto 0) <= sys_dip; gpi1(7 downto 0) <= sys_dip;
sys_led <= gpo0(8 downto 0); sys_led <= gpo0(8 downto 0);
sys_error <= debug; sys_error <= debug;
nmi <= not sys_rst_n_in; nmi <= not sys_rst_n_in;
rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2); rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
rst <= not locked; rst <= not locked;
sys_usb_rstn <= not gpo1(0); sys_usb_rstn <= not gpo1(0);
sys_flash_byten <= '1'; sys_flash_byten <= '1';
usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2); usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0'; flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
flash_page_mode_en <= not mem_mapped_io;
SDAT_I_sdram <= MDAT_O & MDAT_O; SDAT_I_sdram <= MDAT_O & MDAT_O;
SEL_I_sdram <= "0000" & SEL_O; SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn; sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart1_tx <= uart1_tx; sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx; sys_uart2_tx <= uart1_tx;
uart1_rx <= sys_uart1_rx and sys_uart2_rx; uart1_rx <= sys_uart1_rx and sys_uart2_rx;
sys_uart3_tx <= sys_uart3_rx; sys_uart3_tx <= sys_uart3_rx;
--------------------------------------------------------------- ---------------------------------------------------------------
-- Arbiter -- Arbiter
@@ -518,10 +522,12 @@ int_sample:
mem_mux: mem_mux:
process(ADDR_O) process(ADDR_O)
begin begin
mem_area <= mem_dead; mem_area <= mem_dead;
mem_mapped_io <= '0';
if ADDR_O(31 downto 28) = X"0" then if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash; mem_area <= mem_flash;
elsif ADDR_O(31 downto 28) = X"A" then elsif ADDR_O(31 downto 28) = X"A" then
mem_mapped_io <= '1';
if ADDR_O(27 downto 26) = "00" then if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then if ADDR_O(18 downto 16) = "000" then
mem_area <= mem_gpio; mem_area <= mem_gpio;
@@ -543,7 +549,6 @@ mem_mux:
end if; end if;
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
mem_area <= mem_rom; mem_area <= mem_rom;
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
mem_area <= mem_sdram; mem_area <= mem_sdram;
end if; end if;
@@ -636,53 +641,53 @@ inst_mips_top: mips_top
inst_rom_wb : rom_wb inst_rom_wb : rom_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_rom, CYC_I => CYC_I_rom,
STB_I => STB_O, STB_I => STB_O,
ACK_O => ACK_O_rom, ACK_O => ACK_O_rom,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SRDY_O => SRDY_O_rom, SRDY_O => SRDY_O_rom,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_O => SDAT_O_rom DAT_O => SDAT_O_rom
); );
inst_lcd_port: lcd_port inst_lcd_port: lcd_port
PORT MAP PORT MAP
( (
clk => clk, clk => clk,
rst => rst, rst => rst,
we => '0', we => '0',
din => X"00", din => X"00",
dout => open, dout => open,
lcd_d => sys_lcd_d, lcd_d => sys_lcd_d,
lcd_e => sys_lcd_e, lcd_e => sys_lcd_e,
lcd_rs => sys_lcd_rs, lcd_rs => sys_lcd_rs,
lcd_rw => sys_lcd_rw lcd_rw => sys_lcd_rw
); );
inst_gpio_wb : gpio_wb inst_gpio_wb : gpio_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_gpio, CYC_I => CYC_I_gpio,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_gpio, ACK_O => ACK_O_gpio,
SRDY_O => SRDY_O_gpio, SRDY_O => SRDY_O_gpio,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_gpio, DAT_O => SDAT_O_gpio,
INT_TIM_O => int_timer, INT_TIM_O => int_timer,
sys_gpo0 => gpo0, sys_gpo0 => gpo0,
sys_gpo1 => gpo1, sys_gpo1 => gpo1,
sys_gpi0 => gpi0, sys_gpi0 => gpi0,
sys_gpi1 => gpi1 sys_gpi1 => gpi1
); );
inst_flash_port : async_port_wb inst_flash_port : async_port_wb
@@ -695,25 +700,26 @@ inst_flash_port : async_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_flash, CYC_I => CYC_I_flash,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_flash, ACK_O => ACK_O_flash,
SRDY_O => SRDY_O_flash, SRDY_O => SRDY_O_flash,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SEL_I => SEL_O, SEL_I => SEL_O,
ADDR_I => flash_addr, ADDR_I => flash_addr,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_flash, DAT_O => SDAT_O_flash,
async_a => sys_flash_a, page_mode_en => flash_page_mode_en,
async_d => sys_flash_d, async_a => sys_flash_a,
async_cs => sys_flash_ce, async_d => sys_flash_d,
async_wr => sys_flash_wrn, async_cs => sys_flash_ce,
async_rd => sys_flash_rdn, async_wr => sys_flash_wrn,
async_be => open, async_rd => sys_flash_rdn,
async_rst => flash_rstn async_be => open,
async_rst => flash_rstn
); );
inst_usb_port : async_port_wb inst_usb_port : async_port_wb
@@ -726,74 +732,75 @@ inst_usb_port : async_port_wb
) )
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_usb, CYC_I => CYC_I_usb,
STB_I => STB_O, STB_I => STB_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_usb, ACK_O => ACK_O_usb,
SRDY_O => SRDY_O_usb, SRDY_O => SRDY_O_usb,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
SEL_I => SEL_O, SEL_I => SEL_O,
ADDR_I => usb_addr, ADDR_I => usb_addr,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_usb, DAT_O => SDAT_O_usb,
async_a => sys_usb_a, page_mode_en => '0',
async_d => sys_usb_d, async_a => sys_usb_a,
async_cs => sys_usb_csn, async_d => sys_usb_d,
async_wr => sys_usb_wrn, async_cs => sys_usb_csn,
async_rd => sys_usb_rdn, async_wr => sys_usb_wrn,
async_be => open, async_rd => sys_usb_rdn,
async_rst => open async_be => open,
async_rst => open
); );
inst_uart_wb_0 : uart_wb inst_uart_wb_0 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_uart0, CYC_I => CYC_I_uart0,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_uart0, ACK_O => ACK_O_uart0,
SRDY_O => SRDY_O_uart0, SRDY_O => SRDY_O_uart0,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_uart0, DAT_O => SDAT_O_uart0,
INT_O => int_uart0, INT_O => int_uart0,
ser_rx => sys_uart0_rx, ser_rx => sys_uart0_rx,
ser_tx => sys_uart0_tx ser_tx => sys_uart0_tx
); );
inst_uart_wb_1 : uart_wb inst_uart_wb_1 : uart_wb
PORT MAP PORT MAP
( (
CLK_I => clk, CLK_I => clk,
RST_I => rst, RST_I => rst,
CYC_I => CYC_I_uart1, CYC_I => CYC_I_uart1,
STB_I => STB_O, STB_I => STB_O,
SEL_I => SEL_O, SEL_I => SEL_O,
WE_I => WE_O, WE_I => WE_O,
ACK_O => ACK_O_uart1, ACK_O => ACK_O_uart1,
SRDY_O => SRDY_O_uart1, SRDY_O => SRDY_O_uart1,
MRDY_I => MRDY_O, MRDY_I => MRDY_O,
ADDR_I => ADDR_O, ADDR_I => ADDR_O,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_uart1, DAT_O => SDAT_O_uart1,
INT_O => int_uart1, INT_O => int_uart1,
ser_rx => uart1_rx, ser_rx => uart1_rx,
ser_tx => uart1_tx ser_tx => uart1_tx
); );
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
GENERIC MAP GENERIC MAP
( (
BL => BURST_LEN, BL => BURST_LEN,
f_sysclk => ddr_frequency_hz, f_sysclk => ddr_frequency_hz,
fifo_depth => 5 fifo_depth => 5
) )
PORT MAP PORT MAP
( (
projects/mips_sys/src/mips_sys_sim.vhd
+5
View File
@@ -213,6 +213,7 @@ ARCHITECTURE behavior OF mips_sys IS
ADDR_I : in unsigned(31 downto 0); ADDR_I : in unsigned(31 downto 0);
DAT_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0);
DAT_O : out unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0);
page_mode_en : in STD_LOGIC;
async_a : out unsigned(addr_width-1 downto 0); async_a : out unsigned(addr_width-1 downto 0);
async_d : inout unsigned(data_width-1 downto 0); async_d : inout unsigned(data_width-1 downto 0);
async_cs : out std_logic; async_cs : out std_logic;
@@ -382,6 +383,7 @@ ARCHITECTURE behavior OF mips_sys IS
signal flash_we_n : std_logic; signal flash_we_n : std_logic;
signal flash_d_drv : std_logic; signal flash_d_drv : std_logic;
signal flash_bsy : std_logic; signal flash_bsy : std_logic;
signal flash_page_mode_en : std_logic;
-- Arbiter -- Arbiter
constant ARB_MAX_MASTER : natural := 2; constant ARB_MAX_MASTER : natural := 2;
@@ -599,8 +601,10 @@ mem_mux:
process(ADDR_O) process(ADDR_O)
begin begin
mem_area <= mem_dead; mem_area <= mem_dead;
flash_page_mode_en <= '0';
if ADDR_O(31 downto 28) = X"0" then if ADDR_O(31 downto 28) = X"0" then
mem_area <= mem_flash; mem_area <= mem_flash;
flash_page_mode_en <= '1';
elsif ADDR_O(31 downto 28) = X"A" then elsif ADDR_O(31 downto 28) = X"A" then
if ADDR_O(27 downto 26) = "00" then if ADDR_O(27 downto 26) = "00" then
if ADDR_O(18 downto 16) = "000" then if ADDR_O(18 downto 16) = "000" then
@@ -834,6 +838,7 @@ inst_usb_port : async_port_wb
ADDR_I => ADDR_I_usb, ADDR_I => ADDR_I_usb,
DAT_I => MDAT_O, DAT_I => MDAT_O,
DAT_O => SDAT_O_usb, DAT_O => SDAT_O_usb,
page_mode_en => '0',
async_a => sys_usb_a, async_a => sys_usb_a,
async_d => sys_usb_d, async_d => sys_usb_d,
async_cs => sys_usb_csn, async_cs => sys_usb_csn,