- added 'page_mode_en' for async_port
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@551 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+286
-279
@@ -132,22 +132,22 @@ ARCHITECTURE behavior OF mips_sys IS
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COMPONENT mips_top
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Port
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(
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debug : out unsigned(1 downto 0);
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eb : in STD_LOGIC;
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nmi : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out word_t;
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DAT_I : in word_t;
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DAT_O : out word_t;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(3 downto 0);
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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INT : in unsigned (5 downto 0)
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debug : out unsigned(1 downto 0);
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eb : in STD_LOGIC;
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nmi : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out word_t;
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DAT_I : in word_t;
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DAT_O : out word_t;
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WE_O : out STD_LOGIC;
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SEL_O : out unsigned(3 downto 0);
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CYC_O : out STD_LOGIC;
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STB_O : out STD_LOGIC;
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MRDY_O : out STD_LOGIC;
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INT : in unsigned (5 downto 0)
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);
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END COMPONENT;
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@@ -155,30 +155,30 @@ ARCHITECTURE behavior OF mips_sys IS
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COMPONENT rom_wb
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PORT
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0)
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);
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END COMPONENT;
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COMPONENT lcd_port
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PORT
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(
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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lcd_d : inout unsigned(3 downto 0);
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lcd_e : out std_logic;
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lcd_rs : out std_logic;
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lcd_rw : out std_logic
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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lcd_d : inout unsigned(3 downto 0);
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lcd_e : out std_logic;
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lcd_rs : out std_logic;
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lcd_rw : out std_logic
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);
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END COMPONENT;
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@@ -192,25 +192,26 @@ ARCHITECTURE behavior OF mips_sys IS
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);
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PORT
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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async_a : out unsigned(addr_width-1 downto 0);
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async_d : inout unsigned(data_width-1 downto 0);
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async_cs : out std_logic;
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async_wr : out std_logic;
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async_rd : out std_logic;
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async_be : out unsigned(byte_sel_width-1 downto 0);
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async_rst : out std_logic
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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SEL_I : in unsigned(3 downto 0);
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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page_mode_en : in STD_LOGIC;
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async_a : out unsigned(addr_width-1 downto 0);
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async_d : inout unsigned(data_width-1 downto 0);
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async_cs : out std_logic;
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async_wr : out std_logic;
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async_rd : out std_logic;
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async_be : out unsigned(byte_sel_width-1 downto 0);
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async_rst : out std_logic
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);
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END COMPONENT;
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@@ -310,123 +311,125 @@ ARCHITECTURE behavior OF mips_sys IS
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);
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END COMPONENT;
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signal nmi : std_logic;
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signal rst : std_logic;
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signal clk : std_logic;
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signal eb : std_logic;
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signal clk270 : std_logic;
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signal clk270var : std_logic;
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signal rst_in : std_logic;
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signal int_timer : std_logic;
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signal int_uart0 : std_logic;
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signal int_uart1 : std_logic;
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signal uart1_tx : std_logic;
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signal uart1_rx : std_logic;
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signal locked : std_logic;
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signal usb_addr : unsigned(31 downto 0);
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signal flash_addr : unsigned(31 downto 0);
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signal ac97_rstn : std_logic;
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signal flash_rstn : std_logic;
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signal nmi : std_logic;
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signal rst : std_logic;
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signal clk : std_logic;
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signal eb : std_logic;
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signal clk270 : std_logic;
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signal clk270var : std_logic;
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signal rst_in : std_logic;
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signal int_timer : std_logic;
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signal int_uart0 : std_logic;
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signal int_uart1 : std_logic;
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signal uart1_tx : std_logic;
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signal uart1_rx : std_logic;
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signal locked : std_logic;
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signal usb_addr : unsigned(31 downto 0);
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signal flash_addr : unsigned(31 downto 0);
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signal ac97_rstn : std_logic;
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signal mem_mapped_io : std_logic;
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signal flash_rstn : std_logic;
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signal flash_page_mode_en : std_logic;
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-- Arbiter
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constant ARB_MAX_MASTER : natural := 2;
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signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
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signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0);
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signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
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constant ARB_MAX_MASTER : natural := 2;
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signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
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signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0);
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signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
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-- J-Bus signals
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signal INT : unsigned(5 downto 0);
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signal MDAT_I : word_t;
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signal MDAT_O : word_t;
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signal ADDR_O : word_t;
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signal SEL_O : unsigned(3 downto 0);
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signal WE_O : std_logic;
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signal CYC_O : std_logic;
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signal STB_O : std_logic;
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signal ACK_I : std_logic;
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signal SRDY_I : std_logic;
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signal MRDY_O : std_logic;
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signal INT : unsigned(5 downto 0);
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signal MDAT_I : word_t;
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signal MDAT_O : word_t;
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signal ADDR_O : word_t;
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signal SEL_O : unsigned(3 downto 0);
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signal WE_O : std_logic;
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signal CYC_O : std_logic;
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signal STB_O : std_logic;
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signal ACK_I : std_logic;
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signal SRDY_I : std_logic;
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signal MRDY_O : std_logic;
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-- CPU Master
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signal MRDY_O_cpu : std_logic;
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signal MDAT_O_cpu : word_t;
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signal ADDR_O_cpu : word_t;
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signal SEL_O_cpu : unsigned(3 downto 0);
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signal WE_O_cpu : std_logic;
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signal CYC_O_cpu : std_logic;
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signal STB_O_cpu : std_logic;
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signal SRDY_I_cpu : std_logic;
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signal ACK_I_cpu : std_logic;
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signal MRDY_O_cpu : std_logic;
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signal MDAT_O_cpu : word_t;
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signal ADDR_O_cpu : word_t;
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signal SEL_O_cpu : unsigned(3 downto 0);
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signal WE_O_cpu : std_logic;
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signal CYC_O_cpu : std_logic;
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signal STB_O_cpu : std_logic;
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signal SRDY_I_cpu : std_logic;
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signal ACK_I_cpu : std_logic;
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-- VGA Master
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signal MRDY_O_vga : std_logic;
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signal ADDR_O_vga : word_t;
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signal SEL_O_vga : unsigned(7 downto 0);
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signal WE_O_vga : std_logic;
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signal CYC_O_vga : std_logic;
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signal STB_O_vga : std_logic;
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signal SRDY_I_vga : std_logic;
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signal ACK_I_vga : std_logic;
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signal MDAT_I_vga : unsigned(63 downto 0);
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signal MDAT_O_vga : unsigned(63 downto 0);
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signal MRDY_O_vga : std_logic;
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signal ADDR_O_vga : word_t;
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signal SEL_O_vga : unsigned(7 downto 0);
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signal WE_O_vga : std_logic;
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signal CYC_O_vga : std_logic;
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signal STB_O_vga : std_logic;
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signal SRDY_I_vga : std_logic;
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signal ACK_I_vga : std_logic;
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signal MDAT_I_vga : unsigned(63 downto 0);
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signal MDAT_O_vga : unsigned(63 downto 0);
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-- Slaves
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal SDAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal SDAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_usb : std_logic;
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signal ACK_O_usb : std_logic;
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signal SRDY_O_usb : std_logic;
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signal SDAT_O_usb : unsigned(31 downto 0);
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signal CYC_I_usb : std_logic;
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signal ACK_O_usb : std_logic;
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signal SRDY_O_usb : std_logic;
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signal SDAT_O_usb : unsigned(31 downto 0);
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signal CYC_I_sdram : std_logic;
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signal ACK_O_sdram : std_logic;
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signal SRDY_O_sdram : std_logic;
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signal SDAT_O_sdram : unsigned(63 downto 0);
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signal SDAT_I_sdram : unsigned(63 downto 0);
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signal SEL_I_sdram : unsigned(7 downto 0);
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signal CYC_I_sdram : std_logic;
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signal ACK_O_sdram : std_logic;
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signal SRDY_O_sdram : std_logic;
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signal SDAT_O_sdram : unsigned(63 downto 0);
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signal SDAT_I_sdram : unsigned(63 downto 0);
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signal SEL_I_sdram : unsigned(7 downto 0);
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal SDAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal SDAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal SDAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal SDAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_uart0 : std_logic;
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signal ACK_O_uart0 : std_logic;
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signal SRDY_O_uart0 : std_logic;
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signal SDAT_O_uart0 : unsigned(31 downto 0);
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signal CYC_I_uart1 : std_logic;
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signal ACK_O_uart1 : std_logic;
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signal SRDY_O_uart1 : std_logic;
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signal SDAT_O_uart1 : unsigned(31 downto 0);
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signal CYC_I_uart0 : std_logic;
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signal ACK_O_uart0 : std_logic;
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signal SRDY_O_uart0 : std_logic;
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signal SDAT_O_uart0 : unsigned(31 downto 0);
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signal CYC_I_uart1 : std_logic;
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signal ACK_O_uart1 : std_logic;
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signal SRDY_O_uart1 : std_logic;
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signal SDAT_O_uart1 : unsigned(31 downto 0);
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signal CYC_I_vga : std_logic;
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signal ACK_O_vga : std_logic;
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signal SRDY_O_vga : std_logic;
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signal SDAT_O_vga : unsigned(31 downto 0);
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signal CYC_I_vga : std_logic;
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signal ACK_O_vga : std_logic;
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signal SRDY_O_vga : std_logic;
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signal SDAT_O_vga : unsigned(31 downto 0);
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signal INT_O_ac97 : std_logic;
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signal CYC_I_ac97 : std_logic;
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signal ACK_O_ac97 : std_logic;
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signal SRDY_O_ac97 : std_logic;
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signal SDAT_O_ac97 : unsigned(31 downto 0);
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signal INT_O_ac97 : std_logic;
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signal CYC_I_ac97 : std_logic;
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signal ACK_O_ac97 : std_logic;
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signal SRDY_O_ac97 : std_logic;
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signal SDAT_O_ac97 : unsigned(31 downto 0);
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0);
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signal gpi1 : unsigned(31 downto 0);
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0);
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signal gpi1 : unsigned(31 downto 0);
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signal debug : unsigned(1 downto 0);
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signal debug : unsigned(1 downto 0);
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-- DDR SDRAM
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constant BURST_LEN : natural := 2;
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constant BURST_LEN : natural := 2;
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-- attribute rom_style: string;
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@@ -446,27 +449,28 @@ BEGIN
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-- 2 : AC97 interrupt enable
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-- others : reserved
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------------------------------------
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eb <= sys_dip(7);
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gpi0(4 downto 0) <= sys_btn;
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gpi1(7 downto 0) <= sys_dip;
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sys_led <= gpo0(8 downto 0);
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sys_error <= debug;
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nmi <= not sys_rst_n_in;
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rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
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rst <= not locked;
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sys_usb_rstn <= not gpo1(0);
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sys_flash_byten <= '1';
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usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
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flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
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eb <= sys_dip(7);
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gpi0(4 downto 0) <= sys_btn;
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gpi1(7 downto 0) <= sys_dip;
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sys_led <= gpo0(8 downto 0);
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sys_error <= debug;
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nmi <= not sys_rst_n_in;
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rst_in <= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
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rst <= not locked;
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sys_usb_rstn <= not gpo1(0);
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sys_flash_byten <= '1';
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usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
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flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
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flash_page_mode_en <= not mem_mapped_io;
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SDAT_I_sdram <= MDAT_O & MDAT_O;
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SEL_I_sdram <= "0000" & SEL_O;
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sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
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sys_uart1_tx <= uart1_tx;
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sys_uart2_tx <= uart1_tx;
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uart1_rx <= sys_uart1_rx and sys_uart2_rx;
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sys_uart3_tx <= sys_uart3_rx;
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SDAT_I_sdram <= MDAT_O & MDAT_O;
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SEL_I_sdram <= "0000" & SEL_O;
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sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
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sys_uart1_tx <= uart1_tx;
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sys_uart2_tx <= uart1_tx;
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uart1_rx <= sys_uart1_rx and sys_uart2_rx;
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sys_uart3_tx <= sys_uart3_rx;
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---------------------------------------------------------------
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||||
-- Arbiter
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||||
@@ -518,10 +522,12 @@ int_sample:
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mem_mux:
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||||
process(ADDR_O)
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||||
begin
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||||
mem_area <= mem_dead;
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||||
mem_area <= mem_dead;
|
||||
mem_mapped_io <= '0';
|
||||
if ADDR_O(31 downto 28) = X"0" then
|
||||
mem_area <= mem_flash;
|
||||
mem_area <= mem_flash;
|
||||
elsif ADDR_O(31 downto 28) = X"A" then
|
||||
mem_mapped_io <= '1';
|
||||
if ADDR_O(27 downto 26) = "00" then
|
||||
if ADDR_O(18 downto 16) = "000" then
|
||||
mem_area <= mem_gpio;
|
||||
@@ -543,7 +549,6 @@ mem_mux:
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
-- elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
@@ -636,53 +641,53 @@ inst_mips_top: mips_top
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_rom,
|
||||
STB_I => STB_O,
|
||||
ACK_O => ACK_O_rom,
|
||||
MRDY_I => MRDY_O,
|
||||
SRDY_O => SRDY_O_rom,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => SDAT_O_rom
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_rom,
|
||||
STB_I => STB_O,
|
||||
ACK_O => ACK_O_rom,
|
||||
MRDY_I => MRDY_O,
|
||||
SRDY_O => SRDY_O_rom,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => SDAT_O_rom
|
||||
);
|
||||
|
||||
|
||||
inst_lcd_port: lcd_port
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
we => '0',
|
||||
din => X"00",
|
||||
dout => open,
|
||||
lcd_d => sys_lcd_d,
|
||||
lcd_e => sys_lcd_e,
|
||||
lcd_rs => sys_lcd_rs,
|
||||
lcd_rw => sys_lcd_rw
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
we => '0',
|
||||
din => X"00",
|
||||
dout => open,
|
||||
lcd_d => sys_lcd_d,
|
||||
lcd_e => sys_lcd_e,
|
||||
lcd_rs => sys_lcd_rs,
|
||||
lcd_rw => sys_lcd_rw
|
||||
);
|
||||
|
||||
inst_gpio_wb : gpio_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_gpio,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_gpio,
|
||||
SRDY_O => SRDY_O_gpio,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_gpio,
|
||||
INT_TIM_O => int_timer,
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_gpio,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_gpio,
|
||||
SRDY_O => SRDY_O_gpio,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_gpio,
|
||||
INT_TIM_O => int_timer,
|
||||
|
||||
sys_gpo0 => gpo0,
|
||||
sys_gpo1 => gpo1,
|
||||
sys_gpi0 => gpi0,
|
||||
sys_gpi1 => gpi1
|
||||
sys_gpo0 => gpo0,
|
||||
sys_gpo1 => gpo1,
|
||||
sys_gpi0 => gpi0,
|
||||
sys_gpi1 => gpi1
|
||||
);
|
||||
|
||||
inst_flash_port : async_port_wb
|
||||
@@ -695,25 +700,26 @@ inst_flash_port : async_port_wb
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_flash,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_flash,
|
||||
SRDY_O => SRDY_O_flash,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => flash_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_flash,
|
||||
async_a => sys_flash_a,
|
||||
async_d => sys_flash_d,
|
||||
async_cs => sys_flash_ce,
|
||||
async_wr => sys_flash_wrn,
|
||||
async_rd => sys_flash_rdn,
|
||||
async_be => open,
|
||||
async_rst => flash_rstn
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_flash,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_flash,
|
||||
SRDY_O => SRDY_O_flash,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => flash_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_flash,
|
||||
page_mode_en => flash_page_mode_en,
|
||||
async_a => sys_flash_a,
|
||||
async_d => sys_flash_d,
|
||||
async_cs => sys_flash_ce,
|
||||
async_wr => sys_flash_wrn,
|
||||
async_rd => sys_flash_rdn,
|
||||
async_be => open,
|
||||
async_rst => flash_rstn
|
||||
);
|
||||
|
||||
inst_usb_port : async_port_wb
|
||||
@@ -726,74 +732,75 @@ inst_usb_port : async_port_wb
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_usb,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_usb,
|
||||
SRDY_O => SRDY_O_usb,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => usb_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_usb,
|
||||
async_a => sys_usb_a,
|
||||
async_d => sys_usb_d,
|
||||
async_cs => sys_usb_csn,
|
||||
async_wr => sys_usb_wrn,
|
||||
async_rd => sys_usb_rdn,
|
||||
async_be => open,
|
||||
async_rst => open
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_usb,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_usb,
|
||||
SRDY_O => SRDY_O_usb,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => usb_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_usb,
|
||||
page_mode_en => '0',
|
||||
async_a => sys_usb_a,
|
||||
async_d => sys_usb_d,
|
||||
async_cs => sys_usb_csn,
|
||||
async_wr => sys_usb_wrn,
|
||||
async_rd => sys_usb_rdn,
|
||||
async_be => open,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
inst_uart_wb_0 : uart_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart0,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart0,
|
||||
SRDY_O => SRDY_O_uart0,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_uart0,
|
||||
INT_O => int_uart0,
|
||||
ser_rx => sys_uart0_rx,
|
||||
ser_tx => sys_uart0_tx
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart0,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart0,
|
||||
SRDY_O => SRDY_O_uart0,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_uart0,
|
||||
INT_O => int_uart0,
|
||||
ser_rx => sys_uart0_rx,
|
||||
ser_tx => sys_uart0_tx
|
||||
);
|
||||
|
||||
inst_uart_wb_1 : uart_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart1,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart1,
|
||||
SRDY_O => SRDY_O_uart1,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_uart1,
|
||||
INT_O => int_uart1,
|
||||
ser_rx => uart1_rx,
|
||||
ser_tx => uart1_tx
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart1,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart1,
|
||||
SRDY_O => SRDY_O_uart1,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_uart1,
|
||||
INT_O => int_uart1,
|
||||
ser_rx => uart1_rx,
|
||||
ser_tx => uart1_tx
|
||||
);
|
||||
|
||||
|
||||
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
f_sysclk => ddr_frequency_hz,
|
||||
fifo_depth => 5
|
||||
BL => BURST_LEN,
|
||||
f_sysclk => ddr_frequency_hz,
|
||||
fifo_depth => 5
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
|
||||
Reference in New Issue
Block a user