- added 'page_mode_en' for async_port
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@551 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+161
-156
@@ -41,73 +41,74 @@ ARCHITECTURE behavior OF tb_mips_top IS
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constant SRAM_ADDR_WIDTH : integer := 17; -- bits
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constant FLASH_ADDR_WIDTH : integer := 17; -- bits
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signal debug : unsigned(1 downto 0);
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signal debug : unsigned(1 downto 0);
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-- Master
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signal nmi : STD_LOGIC := '0';
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signal rst : STD_LOGIC := '1';
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signal clk : STD_LOGIC := '0';
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signal eb : STD_LOGIC := '1';
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signal ACK_I : STD_LOGIC := '0';
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signal SRDY_I : STD_LOGIC := '0';
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signal ADDR_O : unsigned(31 downto 0);
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signal DAT_I : unsigned(31 downto 0) := (others => '0');
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signal DAT_O : unsigned(31 downto 0);
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signal WE_O : STD_LOGIC;
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signal SEL_O : unsigned(3 downto 0);
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signal CYC_O : STD_LOGIC;
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signal STB_O : STD_LOGIC;
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signal MRDY_O : STD_LOGIC;
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signal INT : unsigned (5 downto 0) := (others => '0');
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signal nmi : STD_LOGIC := '0';
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signal rst : STD_LOGIC := '1';
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signal clk : STD_LOGIC := '0';
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signal eb : STD_LOGIC := '1';
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signal ACK_I : STD_LOGIC := '0';
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signal SRDY_I : STD_LOGIC := '0';
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signal ADDR_O : unsigned(31 downto 0);
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signal DAT_I : unsigned(31 downto 0) := (others => '0');
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signal DAT_O : unsigned(31 downto 0);
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signal WE_O : STD_LOGIC;
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signal SEL_O : unsigned(3 downto 0);
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signal CYC_O : STD_LOGIC;
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signal STB_O : STD_LOGIC;
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signal MRDY_O : STD_LOGIC;
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signal INT : unsigned (5 downto 0) := (others => '0');
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-- Slaves
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal DAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_rom : std_logic;
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signal ACK_O_rom : std_logic;
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signal SRDY_O_rom : std_logic;
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signal DAT_O_rom : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal DAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_flash : std_logic;
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signal ACK_O_flash : std_logic;
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signal SRDY_O_flash : std_logic;
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signal DAT_O_flash : unsigned(31 downto 0);
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signal CYC_I_sram : std_logic;
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signal ACK_O_sram : std_logic;
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signal SRDY_O_sram : std_logic;
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signal DAT_O_sram : unsigned(31 downto 0);
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signal CYC_I_sram : std_logic;
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signal ACK_O_sram : std_logic;
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signal SRDY_O_sram : std_logic;
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signal DAT_O_sram : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal DAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_gpio : std_logic;
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signal ACK_O_gpio : std_logic;
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signal SRDY_O_gpio : std_logic;
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signal DAT_O_gpio : unsigned(31 downto 0);
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signal CYC_I_uart : std_logic;
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signal ACK_O_uart : std_logic;
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signal SRDY_O_uart : std_logic;
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signal DAT_O_uart : unsigned(31 downto 0);
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signal CYC_I_uart : std_logic;
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signal ACK_O_uart : std_logic;
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signal SRDY_O_uart : std_logic;
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signal DAT_O_uart : unsigned(31 downto 0);
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signal flash_cs_n : std_logic;
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signal flash_we_n : std_logic;
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signal flash_oe_n : std_logic;
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signal flash_be_n : unsigned(3 downto 0);
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signal sram_cs_n : std_logic;
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signal sram_be_n : unsigned(3 downto 0);
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signal sram_wr_n : std_logic;
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signal sram_oe_n : std_logic;
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signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
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signal sram_d : unsigned(31 downto 0);
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signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
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signal flash_d : unsigned(31 downto 0);
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signal flash_cs_n : std_logic;
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signal flash_we_n : std_logic;
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signal flash_oe_n : std_logic;
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signal flash_be_n : unsigned(3 downto 0);
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signal sram_cs_n : std_logic;
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signal sram_be_n : unsigned(3 downto 0);
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signal sram_wr_n : std_logic;
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signal sram_oe_n : std_logic;
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signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
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signal sram_d : unsigned(31 downto 0);
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signal flash_a : unsigned(FLASH_ADDR_WIDTH-1 downto 0);
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signal flash_d : unsigned(31 downto 0);
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signal flash_page_mode_en : std_logic;
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0) := (others => '0');
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signal gpi1 : unsigned(31 downto 0) := (others => '0');
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signal gpo0 : unsigned(31 downto 0);
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signal gpo1 : unsigned(31 downto 0);
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signal gpi0 : unsigned(31 downto 0) := (others => '0');
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signal gpi1 : unsigned(31 downto 0) := (others => '0');
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signal int_timer : std_logic;
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signal int_uart : std_logic;
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signal rx : std_logic := '1';
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signal tx : std_logic;
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signal int_timer : std_logic;
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signal int_uart : std_logic;
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signal rx : std_logic := '1';
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signal tx : std_logic;
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type mem_area_t is (mem_dead, mem_flash, mem_sram, mem_rom, mem_gpio, mem_uart);
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signal mem_area : mem_area_t;
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@@ -131,9 +132,11 @@ CLK_GEN: process
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mem_mux:
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process(ADDR_O)
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begin
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mem_area <= mem_dead;
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mem_area <= mem_dead;
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flash_page_mode_en <= '0';
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if ADDR_O(31 downto 28) = X"0" then
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mem_area <= mem_flash;
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mem_area <= mem_flash;
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flash_page_mode_en <= '1';
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elsif ADDR_O(31 downto 28) = X"A" then
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if ADDR_O(27 downto 26) = "00" then
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if ADDR_O(18 downto 16) = "000" then
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@@ -197,27 +200,27 @@ signal_mux:
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uut: entity work.mips_top
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GENERIC MAP
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(
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icache_size => 1024, -- words
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dcache_size => 1024 -- words
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icache_size => 1024, -- words
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dcache_size => 1024 -- words
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)
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PORT MAP
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(
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debug => debug,
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eb => eb,
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RST_I => rst,
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CLK_I => clk,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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MRDY_O => MRDY_O,
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INT => INT,
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nmi => nmi
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debug => debug,
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eb => eb,
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RST_I => rst,
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CLK_I => clk,
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ACK_I => ACK_I,
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SRDY_I => SRDY_I,
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ADDR_O => ADDR_O,
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DAT_I => DAT_I,
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DAT_O => DAT_O,
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WE_O => WE_O,
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SEL_O => SEL_O,
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CYC_O => CYC_O,
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STB_O => STB_O,
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MRDY_O => MRDY_O,
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INT => INT,
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nmi => nmi
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);
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INT(1) <= int_uart;
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INT(5) <= int_timer;
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@@ -225,38 +228,38 @@ uut: entity work.mips_top
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inst_rom : entity work.rom_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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ACK_O => ACK_O_rom,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_rom,
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ADDR_I => ADDR_O,
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DAT_O => DAT_O_rom
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_rom,
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STB_I => STB_O,
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ACK_O => ACK_O_rom,
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MRDY_I => MRDY_O,
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SRDY_O => SRDY_O_rom,
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ADDR_I => ADDR_O,
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DAT_O => DAT_O_rom
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);
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inst_gpio : entity work.gpio_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_gpio,
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SRDY_O => SRDY_O_gpio,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_gpio,
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INT_TIM_O => int_timer,
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_gpio,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_gpio,
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SRDY_O => SRDY_O_gpio,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_gpio,
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INT_TIM_O => int_timer,
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sys_gpo0 => gpo0,
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sys_gpo1 => gpo1,
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sys_gpi0 => gpi0,
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sys_gpi1 => gpi1
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sys_gpo0 => gpo0,
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sys_gpo1 => gpo1,
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sys_gpi0 => gpi0,
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sys_gpi1 => gpi1
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);
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inst_flash_port : entity work.async_port_wb
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@@ -269,25 +272,26 @@ inst_flash_port : entity work.async_port_wb
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_flash,
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SRDY_O => SRDY_O_flash,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_flash,
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async_a => flash_a,
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async_d => flash_d,
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async_cs => flash_cs_n,
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async_wr => flash_we_n,
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async_rd => flash_oe_n,
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async_be => flash_be_n,
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async_rst => open
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_flash,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_flash,
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SRDY_O => SRDY_O_flash,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_flash,
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page_mode_en => flash_page_mode_en,
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async_a => flash_a,
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async_d => flash_d,
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async_cs => flash_cs_n,
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async_wr => flash_we_n,
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async_rd => flash_oe_n,
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async_be => flash_be_n,
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async_rst => open
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);
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inst_sram_port : entity work.async_port_wb
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@@ -300,45 +304,46 @@ inst_sram_port : entity work.async_port_wb
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)
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_sram,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_sram,
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SRDY_O => SRDY_O_sram,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_sram,
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async_a => sram_a,
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async_d => sram_d,
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async_cs => sram_cs_n,
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async_wr => sram_wr_n,
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async_rd => sram_oe_n,
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async_be => sram_be_n,
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async_rst => open
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_sram,
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STB_I => STB_O,
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WE_I => WE_O,
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ACK_O => ACK_O_sram,
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SRDY_O => SRDY_O_sram,
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MRDY_I => MRDY_O,
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SEL_I => SEL_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_sram,
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page_mode_en => '0',
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async_a => sram_a,
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async_d => sram_d,
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async_cs => sram_cs_n,
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async_wr => sram_wr_n,
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async_rd => sram_oe_n,
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async_be => sram_be_n,
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async_rst => open
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);
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inst_uart : entity work.uart_wb
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PORT MAP
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(
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_uart,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_uart,
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SRDY_O => SRDY_O_uart,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_uart,
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INT_O => int_uart,
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ser_rx => rx,
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ser_tx => tx
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CLK_I => clk,
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RST_I => rst,
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CYC_I => CYC_I_uart,
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STB_I => STB_O,
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SEL_I => SEL_O,
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WE_I => WE_O,
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ACK_O => ACK_O_uart,
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SRDY_O => SRDY_O_uart,
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MRDY_I => MRDY_O,
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ADDR_I => ADDR_O,
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DAT_I => DAT_O,
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DAT_O => DAT_O_uart,
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INT_O => int_uart,
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ser_rx => rx,
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ser_tx => tx
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);
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------------------------------------------------------------------
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Reference in New Issue
Block a user