diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index c7ff146..da12efa 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -147,6 +147,7 @@ architecture behavior of biu is
 	signal DAT_I_dmem_rd	: word_t;
 	signal DAT_O_dmem_wr	: word_t;
 	signal SEL_O_dmem_wr	: unsigned(3 downto 0);
+	signal SEL_O_dmem_rd	: unsigned(3 downto 0);
 	signal dcached			: std_logic;
 	signal dcache_en		: std_logic;
 	signal uncached_access	: std_logic;
@@ -308,7 +309,9 @@ inst_bout_fifo: entity work.fifo_sync_dist
 						   ADDR_O_dcache when dcache_mem_gnt = '1' else
 						   ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
 
-	bout_fifo_sel_in	<= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
+	bout_fifo_sel_in	<= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
+						   SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
+
 	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
 
 -- Instantiate synchronous FIFO
@@ -382,6 +385,7 @@ dmem_rd_regs:
 		if rising_edge(CLK_I) then
 			if cpu_dmem_en = '1' and busy = '0' then
 				ADDR_O_dmem_rd		<= cpu_dmem_addr;
+				SEL_O_dmem_rd		<= cpu_dmem_be;
 			end if;
 		end if;
 	end process;