diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd
index 3488c2f..74b156a 100644
--- a/lib/filter/src/fir_stage_sys.vhd
+++ b/lib/filter/src/fir_stage_sys.vhd
@@ -43,10 +43,12 @@ Generic
 	nbits_out		: integer := 12;
 	nbits_out_frac	: integer := 12;
 	input_latency	: integer := 1;
+	coef_latency	: integer := 1;
 	pipe_latency	: integer := 2
 );
 Port
 (
+	rst			: in std_logic;
 	clk			: in std_logic;
 	x_in		: in sfixed;
 	y_in		: in sfixed;
@@ -66,8 +68,10 @@ subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_i
 subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
 
 type input_pipe_t is array (0 to input_latency) of in_t;
+type coef_pipe_t is array (0 to coef_latency) of in_t;
 type mult_pipe_t is array (0 to mult_latency) of out_t;
 
+signal h_pipe		: input_pipe_t;
 signal x_pipe		: input_pipe_t;
 signal mult_pipe	: mult_pipe_t;
 
@@ -84,12 +88,12 @@ begin
 
 	prod		<= mult_pipe(mult_latency);
 	yin			<= resize(y_in, yin);
-	hin			<= resize(h_in, hin);
+	hin			<= h_pipe(coef_latency);
 	xin			<= x_pipe(input_latency);
 	x_out	 	<= resize(xin, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
 
 ------------------------------------------------------------
-	proc_in_reg: process(clk, x_in)
+	proc_xin: process(clk, x_in)
 	begin
 		x_pipe(0)	<= resize(x_in, x_pipe(0));
 		if rising_edge(clk) then
@@ -100,6 +104,18 @@ begin
 		
 	end process;
 
+------------------------------------------------------------
+	proc_hin: process(clk, h_in)
+	begin
+		h_pipe(0)	<= resize(h_in, h_pipe(0));
+		if rising_edge(clk) then
+			for i in 1 to coef_latency loop
+				h_pipe(i)	<= h_pipe(i-1);
+			end loop;
+		end if;
+		
+	end process;
+
 ------------------------------------------------------------
 	proc_pipe_reg: process(clk, xin, hin)
 	begin
@@ -117,7 +133,11 @@ begin
 	begin
 		if rising_edge(clk) then
 			yout := resize(yin + prod, yout, fixed_wrap, fixed_truncate);
-			y_out <= yout;
+			if rst = '1' then
+				y_out <= to_sfixed(0, yout);
+			else
+				y_out <= yout;
+			end if;
 		end	if;
 	end process;