From a0ad9a91820c5acdea46ca0b12005c37affb4449 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 24 May 2015 10:15:01 +0000 Subject: [PATCH] - fixed mips_sys.vhd due to SDRAM changes git-svn-id: http://moon:8086/svn/vhdl/trunk@1201 cc03376c-175c-47c8-b038-4cd826a8556b --- .../mips_sys/ise101/mips_sys/project/mips_sys.prj | 11 ++++++----- .../mips_sys/ise101/mips_sys/project/mips_sys.ucf | 2 +- projects/mips_sys/src/mips_sys.vhd | 12 ++++++------ 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj index 981fc88..b1d75fa 100644 --- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj +++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.prj @@ -5,6 +5,12 @@ vhdl work "../../../../lib/FIFO/src/gray_counter.vhd" vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd" +vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd" vhdl work "../../../../lib/rams/dpram_1w1r2c_ra_xil.vhd" vhdl work "../../../../lib/misc/utils_pkg.vhd" vhdl work "../../../../lib/misc/singleshot.vhd" @@ -15,9 +21,6 @@ vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" vhdl work "../../../../lib/uart/kcuart_tx.vhd" vhdl work "../../../../lib/uart/kcuart_rx.vhd" vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" vhdl work "../../../../lib/rams/dpram_1w1r2c_ro_xil.vhd" vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd" vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" @@ -32,7 +35,6 @@ vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd" vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd" vhdl work "../../../../lib/uart/uart_tx.vhd" vhdl work "../../../../lib/uart/uart_rx.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" vhdl work "../../../../lib/ps2_port/src/ps2_core.vhd" vhdl work "../../../../lib/ps2_port/src/debounce.vhd" vhdl work "../../../../lib/misc/async_types.vhd" @@ -43,7 +45,6 @@ vhdl work "../../src/clockgen.vhd" vhdl work "../../src/async_defs.vhd" vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd" vhdl work "../../../../lib/uart/uart_wb.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" vhdl work "../../../../lib/ps2_port/src/ps2_wb.vhd" vhdl work "../../../../lib/ps2_port/src/ps2_phy_virtex.vhd" vhdl work "../../../../lib/misc/rom_wb.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf index 8240808..4f17ac2 100644 --- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf +++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf @@ -23,7 +23,7 @@ CONFIG STEPPING = "ES"; NET "CLK_O" TNM_NET = "sys_clk"; TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %; -NET "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_phy/clk0" TNM_NET = "sdram_clk"; +NET "inst_sdram_ctrl_wb64/inst_sdram_phy/clk0" TNM_NET = "sdram_clk"; TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %; TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG; diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd index 16d8a3f..61c0b6b 100644 --- a/projects/mips_sys/src/mips_sys.vhd +++ b/projects/mips_sys/src/mips_sys.vhd @@ -927,13 +927,13 @@ inst_clockgen_vga : entity work.clockgen clk_out => vga_clk ); -inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb +inst_sdram_ctrl_wb64 : entity work.ctrl_ddr_wb64 GENERIC MAP ( - BL => BURST_LEN, - f_sysclk => sys_freq_in, - f_sdrclk => sys_freq_in, - fifo_depth => 5 + BURST_LEN => BURST_LEN, + F_SYSCLK => sys_freq_in, + F_SDRCLK => sys_freq_in, + FIFO_DEPTH => 5 ) PORT MAP ( @@ -941,7 +941,7 @@ inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb CLK_I => CLK_O, SDRAM_CLK_I => CLK_O, - SDRAM_CLK_FB_I => sys_sdr_clk_fb, + SDRAM_CLK_FB_I => sys_sdr_clk_fb, CYC_I => CYC_I_sdram, STB_I => STB_O,