- added some comments

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git-svn-id: http://moon:8086/svn/vhdl/trunk@524 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/mips_cop.vhd

@@ -149,7 +149,8 @@ begin
 	eflags.RI		<= ctrl_in.events.illegal;
 	eflags.Int		<= ctrl_in.events.int;
 
-proc_nmi_state_next:
+-- NMI/RST transition detector
+proc_nmi_transition:
 	process(clk)
 	begin
 		if rising_edge(clk) then
@@ -170,6 +171,7 @@ proc_nmi_state_next:
 	end process;
 
 
+-- Main exception FSM
 proc_exc_state:
 	process(exc_state, ctrl_in, cop_pipe_ID)
 	begin
@@ -254,6 +256,7 @@ proc_exc_state_next:
 		end if;
 	end process;
 
+-- Endian switch sampled at hard reset
 sample_endian:
 	process(clk)
 	begin
@@ -264,6 +267,7 @@ sample_endian:
 		end if;
 	end process;
 
+-- Sample imem_addr for later use
 exception_last_imem_addr:
 	process(clk)
 	begin
@@ -274,6 +278,7 @@ exception_last_imem_addr:
 		end if;
 	end process;
 
+-- EPC reg and BD-bit write
 cop_exception_epc_write:
 	process(clk)
 	begin
@@ -292,6 +297,7 @@ cop_exception_epc_write:
 		end if;
 	end process;
 
+-- BadVaddr and exception code write
 cop_exception_map:
 	process(clk)
 	begin
@@ -330,6 +336,7 @@ cop_exception_map:
 	ctrl_out.icache.inv_addr	<= test_reg;
 	ctrl_out.dcache.inv_addr	<= test_reg;
 	
+-- Custom I/D-Cache operations:  invalidate all/line
 cop_cache_op:
 	process(clk)
 	begin
@@ -355,6 +362,7 @@ cop_cache_op:
 		end if;
 	end process;
 
+-- IP register write and signalling Int to pipeline
 cop_ip_reg_write:
 	process(clk)
 	variable ip_v  : unsigned(7 downto 0);
@@ -376,6 +384,7 @@ cop_ip_reg_write:
 		end if;
 	end process;
 
+-- Exception vector dispatch
 cop_exc_vector:
 	process(clk)
 	begin
@@ -395,6 +404,7 @@ cop_exc_vector:
 		end if;
 	end process;
 
+-- Cop pipeline
 cop_pipe:
 	process(clk)
 	begin
@@ -415,6 +425,7 @@ cop_pipe:
 		end if;
 	end process;
 
+-- COP Register read
 cop_register_read:
 	process(reg_rptr, BadVAddr, status, cause, epc, dcache_info, icache_info, test_reg)
 	variable reg : word_t;
@@ -448,6 +459,7 @@ cop_register_read:
 
 	end process;
 
+-- COP Register write strobe generation
 cop_we_gen:
 	process(clk)
 	begin
@@ -479,6 +491,7 @@ cop_we_gen:
 		end if;	
 	end process;
 
+-- COP Test Register
 cop_test_reg_write:
 	process(clk)
 	begin
@@ -493,6 +506,7 @@ cop_test_reg_write:
 		end if;
 	end process;
 
+-- COP Status Register
 cop_status_reg_write:
 	process(clk)
 	begin