diff --git a/lib/JBUS/src/busmaster_sync.vhd b/lib/JBUS/src/busmaster_sync.vhd
index 5e6ed9a..b003685 100644
--- a/lib/JBUS/src/busmaster_sync.vhd
+++ b/lib/JBUS/src/busmaster_sync.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.3 2013-05-28 11:23:15 jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/busmaster_sync.vhd,v 1.4 2013-07-21 09:10:13 jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -103,15 +103,29 @@ begin
 	CYC_O				<= cycle_busy;
 	cmd_cycle_finished	<= not cycle_busy;
 	
+-- proc_bus_read_counter:
+-- 	process(clk)
+-- 	begin
+-- 		if rising_edge(clk) then
+-- 			if rst = '1' then
+-- 				read_cnt	<= 0;
+-- 			elsif cmd_read_en = '1' and read_fifo_we = '0' then
+-- 				read_cnt <= read_cnt + 1;
+-- 			elsif cmd_read_en = '0' and read_fifo_we = '1' then
+-- 				read_cnt <= read_cnt - 1;
+-- 			end if;	
+-- 		end if;
+-- 	end process;	
+
 proc_bus_read_counter:
 	process(clk)
 	begin
 		if rising_edge(clk) then
 			if rst = '1' then
 				read_cnt	<= 0;
-			elsif cmd_read_en = '1' and read_fifo_we = '0' then
+			elsif cmd_read_en = '1' and dout_re = '0' then
 				read_cnt <= read_cnt + 1;
-			elsif cmd_read_en = '0' and read_fifo_we = '1' then
+			elsif cmd_read_en = '0' and dout_re = '1' and read_fifo_empty = '0' then
 				read_cnt <= read_cnt - 1;
 			end if;	
 		end if;
diff --git a/lib/JBUS/src/tb_busmaster_sync.vhd b/lib/JBUS/src/tb_busmaster_sync.vhd
index 2301d2b..1e656f6 100644
--- a/lib/JBUS/src/tb_busmaster_sync.vhd
+++ b/lib/JBUS/src/tb_busmaster_sync.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.2 2013-05-27 11:16:22 jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_busmaster_sync.vhd,v 1.3 2013-07-21 09:10:13 jens Exp $
 -----------------------------------------------------------------------
 
 LIBRARY ieee;
@@ -207,7 +207,7 @@ inst_uut : entity work.busmaster_sync
 	GENERIC MAP
 	(
 		DATA_WIDTH					=> 32,
-		FIFO_DEPTH					=> 4
+		FIFO_DEPTH					=> 2
 	)
 	PORT MAP
 	(
@@ -275,7 +275,7 @@ CLK_GEN: process
 						else
 							res			:= ram_data(31 downto 0) & ram_data(63 downto 32);
 						end if;
-					else -- WE=1
+					elsif MRDY_O = '1' then -- WE=1
 						ram_data := ram64(to_integer(ADDR_O(31 downto 3)));
 						ram_data := (others => '-');
 						if ADDR_O(2) = '0' then
@@ -297,7 +297,9 @@ CLK_GEN: process
 						end if;
 					end if;
 				end if;
-				MDAT_I_64	<= res;
+				if (CYC_O and MRDY_O) = '1' then
+					MDAT_I_64	<= res;
+				end if;
 			end if;
 		end if;
 	end process;
@@ -324,6 +326,8 @@ STIMULUS: process
 	
 		din				<= data;
 		din_we			<= '1';
+		wait until rising_edge(CLK_O) and din_rdy = '1';
+		din_we			<= '0';
 
 		cmd_in.rw		<= '1';
 		cmd_in.sel		<= sel;
@@ -331,7 +335,6 @@ STIMULUS: process
 		cmd_we			<= '1';
 		wait until rising_edge(CLK_O) and cmd_rdy = '1';
 		cmd_we			<= '0';
-		din_we			<= '0';
 
 	end procedure cmd_write_single;