diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.ise b/projects/eval_asyn_fifo/project/eval_asyn_fifo.ise
new file mode 100644
index 0000000..ae5d56c
Binary files /dev/null and b/projects/eval_asyn_fifo/project/eval_asyn_fifo.ise differ
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.lso b/projects/eval_asyn_fifo/project/eval_asyn_fifo.lso
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+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo.lso
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+work
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.prj b/projects/eval_asyn_fifo/project/eval_asyn_fifo.prj
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index 0000000..5f7b809
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+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo.prj
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+vhdl work "../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
+vhdl work "../../lib/FIFO/src/gray_counter.vhd"
+vhdl work "../../lib/FIFO/src/fifo_sync_ctrl.vhd"
+vhdl work "../../lib/FIFO/src/fifo_async_ctrl.vhd"
+vhdl work "../../lib/FIFO/src/dpram_1w1r.vhd"
+vhdl work "../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../lib/FIFO/src/fifo_async.vhd"
+vhdl work "eval_asyn_fifo.vhd"
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.ucf b/projects/eval_asyn_fifo/project/eval_asyn_fifo.ucf
new file mode 100644
index 0000000..a997614
--- /dev/null
+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo.ucf
@@ -0,0 +1,6 @@
+# Bus clock nets
+NET "clk_w" TNM_NET = "write_clk";
+TIMESPEC "TS_write_clk" = PERIOD "write_clk" 4.0 ns HIGH 50 %;
+
+NET "clk_r" TNM_NET = "read_clk";
+TIMESPEC "TS_read_clk" = PERIOD "read_clk" 4.0 ns HIGH 50 %;
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.vhd b/projects/eval_asyn_fifo/project/eval_asyn_fifo.vhd
new file mode 100644
index 0000000..0cacce9
--- /dev/null
+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo.vhd
@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    10:29:16 02/12/2010 
+-- Design Name: 
+-- Module Name:    eval_asyn_fifo - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_asyn_fifo is
+    Port (
+    		din : in  unsigned (31 downto 0);
+           dout : out  unsigned (31 downto 0);
+           rst : in  STD_LOGIC;
+           clk_w : in  STD_LOGIC;
+           clk_r : in  STD_LOGIC;
+           full : out  STD_LOGIC;
+           empty : out  STD_LOGIC;
+           read : in  STD_LOGIC;
+           write : in  STD_LOGIC);
+end eval_asyn_fifo;
+
+architecture Behavioral of eval_asyn_fifo is
+
+	signal read0	: std_logic;
+	signal empty0	: std_logic;
+	signal write1	: std_logic;
+	signal full1	: std_logic;
+	signal dout0	: unsigned (31 downto 0);
+
+begin
+
+	read0	<= not full1;
+	write1	<= not empty0;
+	
+	uut0: entity work.fifo_async
+	GENERIC MAP
+	(
+		addr_width			=> 4,
+		data_width			=> 32,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2,
+		allow_full_writes	=> false,
+		allow_empty_reads	=> false,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk_w		=>	clk_w,
+		clk_r		=>	clk_r,
+		we			=>	write,
+		re			=>	read0,
+		data_w		=>	din,
+		data_r		=>	dout0,
+		fifo_full	=>	full,
+		fifo_empty	=>	empty0,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open
+
+	);
+
+	uut1: entity work.fifo_sync
+	GENERIC MAP
+	(
+		addr_width			=> 10,
+		data_width			=> 32,
+		almost_full_thresh	=> 6,
+		almost_empty_thresh	=> 2,
+		allow_full_writes	=> false,
+		allow_empty_reads	=> false,
+		do_last_read_update	=> true
+	)
+	PORT MAP
+	(
+		rst			=>	rst,
+		clk			=>	clk_r,
+		we			=>	write1,
+		re			=>	read,
+		data_w		=>	dout0,
+		data_r		=>	dout,
+		fifo_full	=>	full1,
+		fifo_empty	=>	empty,
+		fifo_afull	=>	open,
+		fifo_aempty	=>	open
+
+	);
+
+end Behavioral;
+
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo.xst b/projects/eval_asyn_fifo/project/eval_asyn_fifo.xst
new file mode 100644
index 0000000..4a97fc5
--- /dev/null
+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo.xst
@@ -0,0 +1,60 @@
+set -tmpdir "W:/vhdl/projects/eval_asyn_fifo/xst/projnav.tmp"
+set -xsthdpdir "W:/vhdl/projects/eval_asyn_fifo/xst"
+run
+-ifn eval_asyn_fifo.prj
+-ifmt mixed
+-ofn eval_asyn_fifo
+-ofmt NGC
+-p xc4vsx35-10-ff668
+-top eval_asyn_fifo
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-lso eval_asyn_fifo.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract YES
+-resource_sharing YES
+-async_to_sync NO
+-use_dsp48 auto
+-iobuf YES
+-max_fanout 500
+-bufg 32
+-bufr 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/projects/eval_asyn_fifo/project/eval_asyn_fifo_vhdl.prj b/projects/eval_asyn_fifo/project/eval_asyn_fifo_vhdl.prj
new file mode 100644
index 0000000..a6b6f56
--- /dev/null
+++ b/projects/eval_asyn_fifo/project/eval_asyn_fifo_vhdl.prj
@@ -0,0 +1,8 @@
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
+vhdl work "W:\vhdl\projects\eval_asyn_fifo\eval_asyn_fifo.vhd"