From 9cbdedff8e1c45f82d7897303bb956d5e29b9da7 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 17 May 2015 11:19:06 +0000
Subject: [PATCH] - added single clock variant

git-svn-id: http://moon:8086/svn/vhdl/trunk@1108 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/rams/dpram_1w1r1c_ra_sim.vhd | 71 ++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 lib/rams/dpram_1w1r1c_ra_sim.vhd

diff --git a/lib/rams/dpram_1w1r1c_ra_sim.vhd b/lib/rams/dpram_1w1r1c_ra_sim.vhd
new file mode 100644
index 0000000..26c1f4a
--- /dev/null
+++ b/lib/rams/dpram_1w1r1c_ra_sim.vhd
@@ -0,0 +1,71 @@
+-------------------------------------------------------------------------
+-- Project: Dual-Port RAM with 1 clock latency for simulation
+-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address
+
+-- Copyright (C) 2007 J. Ahrensfeld
+
+-- This library is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU Lesser General Public
+-- License as published by the Free Software Foundation; either
+-- version 2.1 of the License, or (at your option) any later version.
+
+-- This library is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+-- Lesser General Public License for more details.
+
+-- You should have received a copy of the GNU Lesser General Public
+-- License along with this library; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+-- For questions and ideas, please contact the author at jens@jayfield.org
+
+-----------------------------------------------------------------------
+-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_sim.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
+-----------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+entity dpram_1w1r1c_ra is
+	Generic
+	(
+		addr_width : integer := 3;
+		data_width : integer := 8
+	);
+	Port (
+		clk		: in  STD_LOGIC;
+		en		: in  STD_LOGIC;
+		we		: in  STD_LOGIC;
+		addr		: in  unsigned (addr_width-1 downto 0);
+		din		: in  unsigned (data_width-1 downto 0);
+		dout		: out unsigned (data_width-1 downto 0)
+	);
+end dpram_1w1r1c_ra;
+
+architecture Behavioral of dpram_1w1r1c_ra is
+
+	constant depth : integer := 2**addr_width;
+	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal RAM : RAMtype;
+	signal addr_reg : unsigned (addr_width-1 downto 0);
+	
+begin
+
+	dout <= RAM(to_integer(addr_reg));
+
+process (clk)
+begin
+if clk'event and clk = '1' then
+	if en = '1' then
+		if we = '1' then
+			RAM(to_integer(addr)) <= din;
+		end if;
+		addr_reg	<= addr;
+	end if;
+end if;
+end process;
+
+end Behavioral;
+