- ram_sim.vhd deleted

- ram_wb has it's own ram implementation

git-svn-id: http://moon:8086/svn/vhdl/trunk@1107 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/ram_sim.vhd

@@ -1,88 +0,0 @@
--------------------------------------------------------------------------
--- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
--- This file: The ROM file for use in your VHDL design
---
--- Copyright (C) 2007 J. Ahrensfeld
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--- For questions and ideas, please contact the author at jens@jayfield.org
---
---------------------------------------------------------------------------
-
-LIBRARY ieee;
-use IEEE.STD_LOGIC_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-
-ENTITY ram IS
-	Generic 
-	(
-		word_addr_width 	: integer := 6
-	);
-	Port 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-END ram;
-
-ARCHITECTURE behavior OF ram IS 
-
-	constant depth : natural := 2**word_addr_width;
-	
-	type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
-
-	function sram_clear return sram_t is
-
-	variable result : sram_t;
-	begin
-		for i in 0 to sram_t'length-1 loop
-			result(i) := (others => '0');
-		end loop;
-		return result;
-	end sram_clear;
-
-	signal sram : sram_t := sram_clear;
-	
-BEGIN
-
-
-SRAM_RW:
-	process(clk)
-	variable index : natural range 0 to depth-1;
-	begin
-		if rising_edge(clk) and ce = '1' then
-			index := to_integer(addr(word_addr_width+1 downto 2));
-			if we(0) = '1' then
-				sram(index)(7 downto 0)		<= din(7 downto 0);
-			end if;	
-			if we(1) = '1' then
-				sram(index)(15 downto 8)	<= din(15 downto 8);
-			end if;	
-			if we(2) = '1' then
-				sram(index)(23 downto 16)	<= din(23 downto 16);
-			end if;	
-			if we(3) = '1' then
-				sram(index)(31 downto 24)	<= din(31 downto 24);
-			end if;	
-			dout <= sram(index);
-		end if;	
-	end process;
-	
-end behavior;

lib/misc/ram_wb.vhd

@@ -29,22 +29,7 @@ END ram_wb;
 
 ARCHITECTURE behavior OF ram_wb IS
 
-	COMPONENT ram
+	constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
-	GENERIC 
-	(
-		word_addr_width 	: integer
-	);
-	PORT 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
 	signal data_en : std_logic;
 	signal we : unsigned(3 downto 0);
 
@@ -67,21 +52,69 @@ data_valid_register:
 		end if;
 	end process;
 
-inst_ram : ram
+inst_ram_0 : entity work.dpram_1w1r1c_ra
 	GENERIC MAP 
 	(
-		word_addr_width	=> NextExpBaseTwo(NUM_WORDS)
+		addr_width => addr_width,
+		data_width => 8
 	)
 	PORT MAP 
 	(
 		clk		=> CLK_I,
-		ce		=> data_en,
+		en		=> data_en,
-		we		=> we,
+		we		=> we(0),
-		addr	=> ADDR_I,
+		addr		=> ADDR_I(addr_width+1 downto 2),
-		din		=> DAT_I,
+		din		=> DAT_I(7 downto 0),
-		dout	=> DAT_O
+		dout		=> DAT_O(7 downto 0)
+	);
+
+inst_ram_1 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(1),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(15 downto 8),
+		dout		=> DAT_O(15 downto 8)
+	);
+
+inst_ram_2 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(2),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(23 downto 16),
+		dout		=> DAT_O(23 downto 16)
+	);
+
+inst_ram_3 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(3),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(31 downto 24),
+		dout		=> DAT_O(31 downto 24)
 	);
 
 
-
 end behavior;