- ram_sim.vhd deleted

- ram_wb has it's own ram implementation git-svn-id: http://moon:8086/svn/vhdl/trunk@1107 cc03376c-175c-47c8-b038-4cd826a8556b
2015-05-17 11:15:59 +00:00
parent eaec09fd09
commit 9c0bdbd6be
2 changed files with 57 additions and 112 deletions
@@ -29,22 +29,7 @@ END ram_wb;

 ARCHITECTURE behavior OF ram_wb IS

-	COMPONENT ram
-	GENERIC 
-	(
-		word_addr_width 	: integer
-	);
-	PORT 
-	(
-		clk			: in  STD_LOGIC;
-		ce			: in  STD_LOGIC;
-		we			: in  unsigned(3 downto 0);
-		addr		: in  unsigned(31 downto 0);
-		din			: in  unsigned(31 downto 0);
-		dout		: out unsigned(31 downto 0)
-	);
-	END COMPONENT;
-
+	constant addr_width : natural := NextExpBaseTwo(NUM_WORDS);
 	signal data_en : std_logic;
 	signal we : unsigned(3 downto 0);

@@ -67,21 +52,69 @@ data_valid_register:
 		end if;
 	end process;

-inst_ram : ram
+inst_ram_0 : entity work.dpram_1w1r1c_ra
 	GENERIC MAP 
 	(
-		word_addr_width	=> NextExpBaseTwo(NUM_WORDS)
+		addr_width => addr_width,
+		data_width => 8
 	)
 	PORT MAP 
 	(
 		clk		=> CLK_I,
-		ce		=> data_en,
-		we		=> we,
-		addr	=> ADDR_I,
-		din		=> DAT_I,
-		dout	=> DAT_O
+		en		=> data_en,
+		we		=> we(0),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(7 downto 0),
+		dout		=> DAT_O(7 downto 0)
+	);
+
+inst_ram_1 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(1),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(15 downto 8),
+		dout		=> DAT_O(15 downto 8)
+	);
+
+inst_ram_2 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(2),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(23 downto 16),
+		dout		=> DAT_O(23 downto 16)
+	);
+
+inst_ram_3 : entity work.dpram_1w1r1c_ra
+	GENERIC MAP 
+	(
+		addr_width => addr_width,
+		data_width => 8
+	)
+	PORT MAP 
+	(
+		clk		=> CLK_I,
+		en		=> data_en,
+		we		=> we(3),
+		addr		=> ADDR_I(addr_width+1 downto 2),
+		din		=> DAT_I(31 downto 24),
+		dout		=> DAT_O(31 downto 24)
 	);


-
 end behavior;