From 9a7ffd09ac3731575bd6993ed252fb7b5f84c67c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 28 Dec 2008 16:28:38 +0000 Subject: [PATCH] - Intital revision git-svn-id: http://moon:8086/svn/vhdl/trunk@152 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/radio/nco/src/mix_cordic.vhd | 202 +++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 lib/radio/nco/src/mix_cordic.vhd diff --git a/lib/radio/nco/src/mix_cordic.vhd b/lib/radio/nco/src/mix_cordic.vhd new file mode 100644 index 0000000..068a46e --- /dev/null +++ b/lib/radio/nco/src/mix_cordic.vhd @@ -0,0 +1,202 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:16:14 10/02/05 +-- Design Name: +-- Module Name: cordic_stage - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; +use work.fixed_pkg.all; +use work.cordic_pkg.all; +use work.nco_pkg.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mix is +Generic +( + nbits_wave_in : integer := 18; + nbits_wave_in_frac : integer := 16; + nbits_wave_out : integer := 18; + nbits_wave_out_frac : integer := 16; + nbits_phase : integer := 16 +); +Port +( + srst : in std_logic; + clk : in std_logic; + pacc_clr : in std_logic; + pacc_inc : in std_logic; + freq_in : in unsigned(nbits_phase-1 downto 0); + freq_load : in std_logic; + phase_in : in unsigned(nbits_phase-1 downto 0); + phase_load : in std_logic; + wave_in_i : in sfixed; + wave_in_q : in sfixed; + wave_out_i : out sfixed; + wave_out_q : out sfixed; + out_valid : out std_logic +); +end mix; + +architecture Behavioral of mix is + + COMPONENT cordic_pipe_top + GENERIC + ( + cordic_mode : cordic_mode_t; + z_range : real; + gain_corr_mode : gain_corr_mode_t; + nstages : integer; + nbits_x_in : integer; + nbits_y_in : integer; + nbits_z_in : integer; + nbits_frac_x_in : integer; + nbits_frac_y_in : integer; + nbits_frac_z_in : integer; + nbits_x_out : integer; + nbits_y_out : integer; + nbits_z_out : integer; + nbits_frac_x_out : integer; + nbits_frac_y_out : integer; + nbits_frac_z_out : integer + ); + PORT + ( + rst : in std_logic; + clk : in std_logic; + vld_in : in std_logic; + xin : in sfixed; + yin : in sfixed; + zin : in sfixed; + xout : out sfixed; + yout : out sfixed; + zout : out sfixed; + vld_out : out std_logic + ); + END COMPONENT; + +------------------------------------------------------------------------------- + constant nbits_phase_frac : integer := nbits_phase; + +------------------------------------------------------------------------------- + signal phase : signed(nbits_phase-1 downto 0); + signal freq_in_r : signed(nbits_phase-1 downto 0); + signal phase_in_r : signed(nbits_phase-1 downto 0); + signal xin, yin : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); + signal xout, yout : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); + + signal wave_out_valid : std_logic; + + signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); + signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); + +------------------------------------------------------------------------------- +begin + + wave_out_i <= xout; + wave_out_q <= yout; + xin <= wave_in_i; + yin <= wave_in_q; + + out_valid <= wave_out_valid; + +------------------------------------------------------------ + proc_phase_accu: process(clk) + variable phase_accu : signed(nbits_phase-1 downto 0); + + begin + if rising_edge(clk) then + if srst = '1' then + phase_accu := (others => '0'); + else + phase <= phase_accu + phase_in_r; + if pacc_clr = '1' then + phase_accu := (others => '0'); + elsif pacc_inc = '1' then + phase_accu := phase_accu + freq_in_r; + end if; + end if; + end if; + zin <= sfixed(phase); + end process; + +------------------------------------------------------------ + freq_in_reg: process(srst, clk, freq_load, freq_in) + begin + if rising_edge(clk) then + if srst = '1' then + freq_in_r <= (others => '0'); + elsif freq_load = '1' then + freq_in_r <= signed(freq_in); + end if; + end if; + end process; + +------------------------------------------------------------ + phase_in_reg: process(srst, clk, phase_load, phase_in) + begin + if rising_edge(clk) then + if srst = '1' then + phase_in_r <= (others => '0'); + elsif phase_load = '1' then + phase_in_r <= signed(phase_in); + end if; + end if; + end process; + +------------------------------------------------------------ + inst_cordic_ud: cordic_pipe_top + GENERIC MAP + ( + cordic_mode => cordic_mode_rotate, + z_range => 1.0, + gain_corr_mode => gain_mode_disabled, + nstages => nbits_phase, + nbits_x_in => nbits_wave_in, + nbits_frac_x_in => nbits_wave_in_frac, + nbits_y_in => nbits_wave_in, + nbits_frac_y_in => nbits_wave_in_frac, + nbits_z_in => nbits_phase, + nbits_frac_z_in => nbits_phase_frac, + nbits_x_out => nbits_wave_out, + nbits_frac_x_out => nbits_wave_out_frac, + nbits_y_out => nbits_wave_out, + nbits_frac_y_out => nbits_wave_out_frac, + nbits_z_out => nbits_phase, + nbits_frac_z_out => nbits_phase_frac + ) + PORT MAP + ( + rst => srst, + clk => clk, + vld_in => '1', + xin => xin, + yin => yin, + zin => zin, + xout => xout, + yout => yout, + zout => zout, + vld_out => wave_out_valid + ); + +------------------------------------------------------------ +end Behavioral;