[J-Uart]

- use LSB first for UART
- Uart_wb: added generic for default baudrate and fifo depth

git-svn-id: http://moon:8086/svn/vhdl/trunk@1358 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/juart_rx.vhd

@@ -142,7 +142,7 @@ begin
 		if rst = '1' then
 			shiftreg	<= (others => '0');
 		elsif shiftreg_en = '1' and bit_sample = '1' and en_16_x_baud = '1' then
-			shiftreg <= shiftreg(shiftreg'left-1 downto 0) & ser_in;
+			shiftreg <= ser_in & shiftreg(shiftreg'left downto 1);
 		end if;
 	end if;
 end process;

lib/uart/juart_tx.vhd

@@ -51,7 +51,7 @@ signal bit_count			: unsigned (3 downto 0);
 --
 --
 begin
-ser_out		<= shiftreg(shiftreg'left);
+ser_out		<= shiftreg(0);
 Tx_complete	<= not busy;
 
 shift_enable_counter:
@@ -103,9 +103,9 @@ begin
 		elsif shift_enable = '1' then
 			if start = '1' then
 				start		<= '0';
-				shiftreg	<= '0' & dinreg & '1';
+				shiftreg	<= '1' & dinreg & '0';
 			elsif bit_count /= 0 then
-				shiftreg	<= shiftreg(shiftreg'left-1 downto 0) & '1';
+				shiftreg	<= '1' & shiftreg(shiftreg'left downto 1);
 				if bit_count = 1 then
 					busy	<= '0';
 				end if;

lib/uart/uart.vhd

@@ -7,6 +7,10 @@ USE WORK.uart_types.all;
 
 ------------------------------------------------------------------------------------
 ENTITY uart IS
+	Generic 
+	(
+		fifo_depth_bits	: integer := 4
+	);
 	Port
 	(
 		clk			: in  STD_LOGIC;
@@ -55,6 +59,10 @@ begin
 end process;
 
 inst_uart_tx : entity work.uart_tx
+	GENERIC MAP 
+	(
+		fifo_depth_bits	=> fifo_depth_bits
+	)
 	PORT MAP
 	(
 		rst					=> rst,
@@ -70,6 +78,10 @@ inst_uart_tx : entity work.uart_tx
 	);
 
 inst_uart_rx : entity work.uart_rx
+	GENERIC MAP 
+	(
+		fifo_depth_bits	=> fifo_depth_bits
+	)
 	PORT MAP
 	(
 		rst					=> rst,

lib/uart/uart_wb.vhd

@@ -6,6 +6,12 @@ LIBRARY WORK;
 USE WORK.uart_types.all;
 
 ENTITY uart_wb IS
+	Generic 
+	(
+		f_sysclk			: real := 100.0e6;
+		baudrate_default	: real := 115200.0;
+		fifo_depth_bits		: integer := 4
+	);
 	Port
 	(
 		CLK_I		: in  STD_LOGIC;
@@ -86,7 +92,7 @@ registers_write:
 		if rising_edge(CLK_I) then
 			reg_we_uart_tx	<= '0';
 			if RST_I = '1' then
-				reg_uart_baud	<= to_unsigned(53, 16);
+				reg_uart_baud	<= to_unsigned(integer(0.5+f_sysclk/(16.0*baudrate_default))-1, 16);
 				rx_int_en		<= '0';
 				tx_int_en		<= '0';
 			elsif (STB_I and CYC_I and WE_I) = '1' then