From 9975fbd6ccac2485d559dedb3003f3e5ec1597ed Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 9 Nov 2009 19:15:25 +0000 Subject: [PATCH] - changes due to packing of resx, resy and fps into one 32-bit register Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@651 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/src/tb_vga_frontend64.vhd | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd index 5ae7e39..9639deb 100644 --- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd @@ -187,21 +187,12 @@ STIMULUS: process wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; - -- Read resolution X + -- Read resolution CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; - ADDR_O <= X"0000_0018"; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '0'; - - -- Read resolution Y - CYC_O <= '1'; - wait until rising_edge(CLK_O) and SRDY_I = '1'; - STB_O <= '1'; - WE_O <= '0'; - ADDR_O <= X"0000_001C"; + ADDR_O <= X"0000_0014"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0';