From 9870f78e511c69b50ea3dd327b9f0c95d2a3db11 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 18 Aug 2013 08:15:42 +0000
Subject: [PATCH] This commit was manufactured by cvs2svn to create branch
 'BRANCH_MIPS_TLB'.

git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1007 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/CPUs/MIPS/sim/tb_mips_top.wdo | 223 ++++++++++++++++++++++++++++++
 1 file changed, 223 insertions(+)
 create mode 100644 lib/CPUs/MIPS/sim/tb_mips_top.wdo

diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
new file mode 100644
index 0000000..12b16c3
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo
@@ -0,0 +1,223 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {TOP interface}
+add wave -noupdate -format Logic /tb_mips_top/nmi
+add wave -noupdate -format Logic /tb_mips_top/rst
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal /tb_mips_top/debug
+add wave -noupdate -format Logic /tb_mips_top/stb_o
+add wave -noupdate -format Logic /tb_mips_top/ack_i
+add wave -noupdate -format Logic /tb_mips_top/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o
+add wave -noupdate -format Logic /tb_mips_top/we_o
+add wave -noupdate -format Literal /tb_mips_top/sel_o
+add wave -noupdate -format Logic /tb_mips_top/cyc_o
+add wave -noupdate -format Logic /tb_mips_top/mrdy_o
+add wave -noupdate -format Literal /tb_mips_top/int
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_shifter/dout
+add wave -noupdate -format Logic /tb_mips_top/uut/biu_rst
+add wave -noupdate -format Logic /tb_mips_top/uut/cpu_rst
+add wave -noupdate -format Logic /tb_mips_top/uut/cpu_run
+add wave -noupdate -divider BIU
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bout_fifo_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bout_rdy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/bus_timeout_cnt
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_timeout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_err
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_imem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_imem_din
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_err
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_rdy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/cpu_dmem_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_dout
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/cpu_dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/cpu_dmem_addr
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bus_idle
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/dmem_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/bin_fifo_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/bin_fifo_empty
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/write_fifo_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_re
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_full
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/write_fifo_empty
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/read_cycle
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en2
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcache_en
+add wave -noupdate -divider {External components}
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi_0
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo_0
+add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_complete
+add wave -noupdate -format Logic /tb_mips_top/inst_uart/tx_empty
+add wave -noupdate -format Literal /tb_mips_top/inst_uart/uart_status_port
+add wave -noupdate -format Logic /tb_mips_top/rx
+add wave -noupdate -format Logic /tb_mips_top/tx
+add wave -noupdate -divider {Interrupt Timer}
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack
+add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal /tb_mips_top/mem_area
+add wave -noupdate -format Literal /tb_mips_top/inst_flash_port/s
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/ack
+add wave -noupdate -format Logic /tb_mips_top/stb_o
+add wave -noupdate -format Logic /tb_mips_top/srdy_i
+add wave -noupdate -format Logic /tb_mips_top/we_o
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/we_i_r
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_flash_port/addr_i_r
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/page_mode_en
+add wave -noupdate -format Logic /tb_mips_top/inst_flash_port/rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
+add wave -noupdate -format Logic /tb_mips_top/ack_i
+add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
+add wave -noupdate -format Logic /tb_mips_top/flash_we_n
+add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
+add wave -noupdate -format Literal /tb_mips_top/flash_be_n
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d
+add wave -noupdate -format Logic /tb_mips_top/ack_i
+add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
+add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
+add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
+add wave -noupdate -format Literal /tb_mips_top/sram_be_n
+add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/page_mode_en_r
+add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/do_page_read
+add wave -noupdate -format Logic /tb_mips_top/inst_sram_port/rdy
+add wave -noupdate -format Literal /tb_mips_top/inst_sram_port/s
+add wave -noupdate -divider ALU
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/sdu
+add wave -noupdate -divider PC
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic -radix hexadecimal /tb_mips_top/uut/inst_pipeline/ex_stage.ctrl.branch
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/branch_ce
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc
+add wave -noupdate -divider COP0
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/ir_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ir
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/test_reg
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/test_reg_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/icache_info
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state
+add wave -noupdate -divider Pipestages
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/id_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
+add wave -noupdate -divider I-Cache
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/request_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/fill_addr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/data_ram_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/inst_tag_ram/ram
+add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_mips_top/clk
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/mrdy_o
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/request_addr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/fill_addr
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg
+add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din
+add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {Cursor {5877623 ps} 0}
+configure wave -namecolwidth 188
+configure wave -valuecolwidth 154
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {5846736 ps} {5910641 ps}