diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf
index 9dcf9ce..dc8dcaf 100644
--- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf
+++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf
@@ -23,7 +23,7 @@ CONFIG STEPPING = "ES";
 NET "CLK_O" TNM_NET = "sys_clk";
 TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
 
-NET "sdram_clk0" TNM_NET = "sdram_clk";
+NET "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_phy/clk0" TNM_NET = "sdram_clk";
 TIMESPEC "TS_sdram_clk" = PERIOD "sdram_clk" 7.5 ns HIGH 50 %;
 TIMESPEC "TS_unrelate_SDRAM" = FROM sys_clk TO sdram_clk TIG;
 
@@ -31,10 +31,6 @@ NET "vga_clk" TNM_NET = "vga_clk";
 TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
 TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
 
-NET "cpu_clk" TNM_NET = "cpu_clk";
-TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
-#TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
-
 NET "sys_clk_in" LOC = "AE14";
 NET sys_clk_in IOSTANDARD = LVCMOS33;
 NET "sys_rst_n_in" LOC = "D6";
diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
index 2725592..569bf2c 100644
--- a/projects/mips_sys/src/mips_sys.vhd
+++ b/projects/mips_sys/src/mips_sys.vhd
@@ -504,7 +504,6 @@ ARCHITECTURE behavior OF mips_sys IS
 
 	attribute KEEP : string;
 	attribute KEEP of vga_clk		: signal is "TRUE";
-	attribute KEEP of sdram_clk0	: signal is "TRUE";
 	attribute KEEP of CLK_O			: signal is "TRUE";
 	attribute KEEP of RST_O			: signal is "TRUE";