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- added MII-FIFO read delay. To avoid tx_en-gaps during FCS calculation

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git-svn-id: http://moon:8086/svn/vhdl/trunk@888 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-08 19:06:11 +00:00
parent 11a46a6ef8
commit 964b08a53c
1 changed files with 20 additions and 6 deletions
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lib/emac/src/emac_tx.vhd
+20 -6
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@@ -115,6 +115,7 @@ ARCHITECTURE behavior OF emac_tx IS
signal mii_fifo_re : std_logic;
signal mii_fifo_full : std_logic;
signal mii_fifo_empty : std_logic;
signal mii_fifo_re_dly : unsigned(7 downto 0);
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
@@ -125,7 +126,7 @@ ARCHITECTURE behavior OF emac_tx IS
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_finish);
type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
signal xfer_s, xfer_sn : xfer_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
@@ -517,13 +518,13 @@ xfer_state:
end if;
when xfer_start =>
xfer_set <= '1';
fcs_rst <= '1';
if cmd_fifo_empty = '0' and ifg_idle = '1' then
xfer_sn <= xfer_preamble0;
end if;
when xfer_preamble0 =>
xfer_set <= '1';
fcs_rst <= '1';
preamble_addr <= 0;
preamble_en <= '1';
piso32_din_vld <= '1';
@@ -543,7 +544,12 @@ xfer_state:
when xfer_active =>
piso32_din_vld <= xfer_bsy;
xfer_en <= '1';
if xfer_bsy = '0' and piso32_dout_vld = '0' then
if xfer_bsy = '0' then
xfer_sn <= xfer_stop;
end if;
when xfer_stop =>
if piso32_dout_vld = '0' then
xfer_sn <= xfer_crc;
end if;
@@ -656,7 +662,15 @@ inst_fcs: entity work.crc32
);
mii_fifo_re <= '1' when Gbps_en = '1' else piso8_din_rdy;
mii_fifo_re_dly_gen:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
end if;
end process;
mii_fifo_re <= mii_fifo_re_dly(mii_fifo_re_dly'left) when Gbps_en = '1' else (piso8_din_rdy and mii_fifo_re_dly(mii_fifo_re_dly'left));
mii_fifo_we <= piso32_dout_vld;
-- Instantiate synchronous FIFO
@@ -701,7 +715,7 @@ inst_piso8 : entity work.piso
dout => piso8_dout
);
piso8_din_vld <= not mii_fifo_empty;
piso8_din_vld <= not mii_fifo_empty and mii_fifo_re_dly(mii_fifo_re_dly'left);
mii_output_register:
process(mii_tx_clk)