From 9485906877b1f572ec6127c701e675a393957502 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Thu, 5 Nov 2009 11:55:53 +0000 Subject: [PATCH] - removed clkgen. VGA-clock generated in TB Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@606 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/VGA_ctrl/sim/tb_vga_frontend.fdo | 1 - lib/VGA_ctrl/sim/tb_vga_frontend64.fdo | 1 - lib/VGA_ctrl/src/tb_vga_frontend.vhd | 36 +++++++++++--------------- lib/VGA_ctrl/src/tb_vga_frontend64.vhd | 35 ++++++++++--------------- 4 files changed, 29 insertions(+), 44 deletions(-) diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo index afeeea5..151b8dd 100644 --- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo +++ b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo @@ -10,7 +10,6 @@ vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/clkgen_virtex4.vhd" vcom -explicit -93 "../src/char_gen.vhd" vcom -explicit -93 "../src/vga_sync.vhd" vcom -explicit -93 "../src/vga_timing.vhd" diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo index 6b5b656..79f0b4a 100644 --- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo +++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo @@ -10,7 +10,6 @@ vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async.vhd" vcom -explicit -93 "../src/fonts/char_rom_c64.vhd" vcom -explicit -93 "../src/vga_types.vhd" -vcom -explicit -93 "../src/clkgen_virtex4.vhd" vcom -explicit -93 "../src/char_gen.vhd" vcom -explicit -93 "../src/vga_sync.vhd" vcom -explicit -93 "../src/vga_timing.vhd" diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd index 01bdf94..a89f7a4 100644 --- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd +++ b/lib/VGA_ctrl/src/tb_vga_frontend.vhd @@ -33,7 +33,9 @@ END tb_vga_frontend; ARCHITECTURE behavior OF tb_vga_frontend IS + constant tsvga : vga_timespec_t := ts_vga_testbench; constant CLK_PERIOD : time := 10 ns; + constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns; signal CLK_O : std_logic := '1'; signal RST_O : std_logic := '1'; @@ -62,7 +64,7 @@ ARCHITECTURE behavior OF tb_vga_frontend IS signal SDAT_O : unsigned(31 downto 0) := (others => '-'); -- VGA signals - signal vga_clk : std_logic; + signal vga_clk : std_logic := '1'; signal vga_red : unsigned(7 downto 0); signal vga_green : unsigned(7 downto 0); signal vga_blue : unsigned(7 downto 0); @@ -70,18 +72,17 @@ ARCHITECTURE behavior OF tb_vga_frontend IS signal vga_sync_n : std_logic; signal vga_hsync : std_logic; signal vga_vsync : std_logic; - signal dcm_locked : std_logic; + signal vga_en : std_logic; - constant tsvga : vga_timespec_t := ts_vga_800_600_72; BEGIN inst_vga_frontend : entity work.vga_frontend GENERIC MAP ( - fifo_depth => 2048, - fifo_almost_full_thresh => 2000, - fifo_almost_empty_thresh => 48, + fifo_depth => 256, + fifo_almost_full_thresh => 240, + fifo_almost_empty_thresh => 16, tsvga => tsvga ) PORT MAP @@ -116,7 +117,7 @@ inst_vga_frontend : entity work.vga_frontend -- VGA signals vga_clk_in => vga_clk, - vga_clk_ce => dcm_locked, + vga_clk_ce => vga_en, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -126,26 +127,19 @@ inst_vga_frontend : entity work.vga_frontend vga_vsync => vga_vsync ); - + vga_en <= not RST_O; + CLK_GEN: process begin wait for CLK_PERIOD/2; CLK_O <= not CLK_O; end process; -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - clk_in_freq_hz => 100E6, - clk_out_freq_hz => tsvga.f_pxl_clk - ) - PORT MAP - ( - rst => RST_O, - clk_in => CLK_O, - clk_out => vga_clk, - locked => dcm_locked - ); +VGA_CLK_GEN: process + begin + wait for VGA_CLK_PERIOD/2; + vga_clk <= not vga_clk after 3 ns; + end process; -- Slave SRDY_O <= CYC_I; diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd index 55c5cba..d03cfa9 100644 --- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd +++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd @@ -33,7 +33,9 @@ END tb_vga_frontend64; ARCHITECTURE behavior OF tb_vga_frontend64 IS + constant tsvga : vga_timespec_t := ts_vga_testbench; constant CLK_PERIOD : time := 10 ns; + constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns; signal CLK_O : std_logic := '1'; signal RST_O : std_logic := '1'; @@ -62,7 +64,7 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS signal SDAT_O : unsigned(31 downto 0) := (others => '-'); -- VGA signals - signal vga_clk : std_logic; + signal vga_clk : std_logic := '1'; signal vga_red : unsigned(7 downto 0); signal vga_green : unsigned(7 downto 0); signal vga_blue : unsigned(7 downto 0); @@ -70,18 +72,16 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS signal vga_sync_n : std_logic; signal vga_hsync : std_logic; signal vga_vsync : std_logic; - signal dcm_locked : std_logic; + signal vga_en : std_logic; - constant tsvga : vga_timespec_t := ts_vga_800_600_72; - BEGIN inst_vga_frontend64 : entity work.vga_frontend64 GENERIC MAP ( - fifo_depth => 2048, - fifo_almost_full_thresh => 2000, - fifo_almost_empty_thresh => 48, + fifo_depth => 256, + fifo_almost_full_thresh => 240, + fifo_almost_empty_thresh => 16, tsvga => tsvga ) PORT MAP @@ -116,7 +116,7 @@ inst_vga_frontend64 : entity work.vga_frontend64 -- VGA signals vga_clk_in => vga_clk, - vga_clk_ce => dcm_locked, + vga_clk_ce => vga_en, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, @@ -126,6 +126,7 @@ inst_vga_frontend64 : entity work.vga_frontend64 vga_vsync => vga_vsync ); + vga_en <= not RST_O; CLK_GEN: process begin @@ -133,19 +134,11 @@ CLK_GEN: process CLK_O <= not CLK_O; end process; -inst_clkgen: entity work.clkgen - GENERIC MAP - ( - clk_in_freq_hz => 100E6, - clk_out_freq_hz => tsvga.f_pxl_clk - ) - PORT MAP - ( - rst => RST_O, - clk_in => CLK_O, - clk_out => vga_clk, - locked => dcm_locked - ); +VGA_CLK_GEN: process + begin + wait for VGA_CLK_PERIOD/2; + vga_clk <= not vga_clk after 3 ns; + end process; -- Slave SRDY_O <= CYC_I;