From 94665d9c194788fdbd63e18f6685a6f219a08cd3 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Fri, 22 May 2015 17:49:58 +0000 Subject: [PATCH] [SDRAM-Controller] - refactored: moved clockgen into phy - removed async resets git-svn-id: http://moon:8086/svn/vhdl/trunk@1153 cc03376c-175c-47c8-b038-4cd826a8556b --- .../sim/tb_sdram_ctrl_frontend64_wb.wdo | 23 ++- .../sim/tb_sdram_ctrl_frontend_wb.wdo | 35 ++-- .../ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd | 178 +++++++++++------- .../src/sdram_ctrl_frontend64_wb.vhd | 20 +- .../src/sdram_ctrl_frontend_wb.vhd | 22 +-- lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd | 34 ++-- .../src/tb_sdram_ctrl_frontend64_wb.vhd | 50 +---- .../src/tb_sdram_ctrl_frontend_wb.vhd | 49 +---- 8 files changed, 202 insertions(+), 209 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo index f576e65..fb51533 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend64_wb.wdo @@ -14,11 +14,10 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_fb -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk0_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk270var_o +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk_fb +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk0 +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_rst0 add wave -noupdate -divider Part add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n @@ -29,13 +28,13 @@ add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {38990166 ps} 0} diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo index 20af0f9..96f2000 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_sdram_ctrl_frontend_wb.wdo @@ -15,18 +15,17 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt add wave -noupdate -divider DEBUG -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_din -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_re -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_we -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_empty -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk270var_o +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_din +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_dout +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_re +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_we +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_full +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_empty +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk_fb +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk0 +add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_rst0 add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk0_o add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n @@ -36,13 +35,13 @@ add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/bank_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {199582900 ps} 0} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd index 11021bc..f11b0ac 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd @@ -31,15 +31,21 @@ use work.sdram_types.all; Library UNISIM; use UNISIM.vcomponents.all; -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; +entity sdram_phy is + Generic + ( + f_sdrclk : real := 100.0 + ); + Port + ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + clk_fb : in STD_LOGIC; + clk0_out : out STD_LOGIC; + rst0_out : out STD_LOGIC; u_tag_in : in user_tag_t; u_tag_rd : out user_tag_t; u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; phy_ctrl : in phy_ctrl_t; part_ctrl : in part_ctrl_t; sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); @@ -60,9 +66,9 @@ entity ddr_phy is part_ras_n : out STD_LOGIC; part_cke : out STD_LOGIC ); -end ddr_phy; +end sdram_phy; -architecture tech of ddr_phy is +architecture tech of sdram_phy is signal dqs_drive : std_logic; signal drive : std_logic; @@ -77,16 +83,56 @@ architecture tech of ddr_phy is signal we_reg : std_logic; signal read_en : std_logic; + signal clk0 : std_logic; + signal rst0 : std_logic; + signal clk_rd : std_logic; + signal clk_wr : std_logic; + + signal locked : std_logic; + signal error : std_logic; + type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; signal u_tag_pipe : u_tag_array_t; begin + clk0_out <= clk0; + rst0_out <= rst0; + +------------------------------------------------------------------------------------------------------------------------------------------------ +inst_clockgen : entity work.clockgen + GENERIC MAP + ( + clk_in_freq => f_sdrclk, + clk0_out_phaseshift => 0, + clk1_out_phaseshift => 0 + ) + PORT MAP + ( + -- Clocks and Reset + rst => rst, -- external async reset, low active + clk_in => clk, -- system clock (e.g. 100MHz), from board + clk_fb_in => clk_fb, -- feedback clock + clk0_0_out => clk0, -- System clock #0, dcm#0 output 0° + clk0_270_out => clk_wr, -- System clock #0, dcm#0 output 270° + clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° + clk1_270_out => clk_rd, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° + locked_out => locked, -- DCM locked status + error_out => error + ); +rst0_gen: + process(clk0) + begin + if rising_edge(clk0) then + rst0 <= not locked; + end if; + end process; + ------------------------------------------------------------------------------------------------------------------------------------------------ utag_pipe: - process(sys_rst, sys_clk0) + process(clk0) begin - if rising_edge(sys_clk0) then + if rising_edge(clk0) then for i in u_tag_pipe'length-1 downto 1 loop u_tag_pipe(i) <= u_tag_pipe(i-1); end loop; @@ -97,29 +143,31 @@ utag_pipe: end process; WE_REGISTER: - process(sys_rst, sys_clk0) + process(clk0) begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; + if rising_edge(clk0) then + if rst0 = '1' then + we_reg <= '0'; + else + we_reg <= phy_ctrl.we; + end if; end if; end process; DATA_DRIVE_GEN: - process(sys_clk0) + process(clk0) begin - if falling_edge(sys_clk0) then + if falling_edge(clk0) then dqs_rst <= not we_reg; drive <= we_reg; end if; end process; DQS_DRIVE_GEN: - process(sys_clk0) + process(clk0) variable p : unsigned(1 downto 0); begin - if rising_edge(sys_clk0) then + if rising_edge(clk0) then if phy_ctrl.drive_en = '1' then p := (others => '1'); else @@ -140,7 +188,7 @@ ODDR_clk_p : ODDR ) port map ( Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input + C => clk0, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '1', -- 1-bit data input (positive edge) D2 => '0', -- 1-bit data input (negative edge) @@ -157,7 +205,7 @@ ODDR_clk_n : ODDR ) port map ( Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input + C => clk0, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) @@ -179,7 +227,7 @@ gen_ddr_data_out: ) port map ( Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input + C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) D2 => sdr_data_w(n), -- 1-bit data input (negative edge) @@ -189,9 +237,9 @@ gen_ddr_data_out: end generate gen_ddr_data_out; -- Sample tristate on clock90 - process (sys_clk270) + process (clk_wr) begin - if rising_edge(sys_clk270) then + if rising_edge(clk_wr) then for n in 0 to DDR_DATA_WIDTH-1 loop drive270(n) <= drive; end loop; @@ -218,10 +266,10 @@ gen_ddr_dm_out: ) port map ( Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input + C => clk_wr, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) + D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) + D2 => sdr_dm(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -241,7 +289,7 @@ gen_dqs_out: ) port map ( Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input + C => clk0, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D2 => '0', -- 1-bit data input (positive edge) D1 => '1', -- 1-bit data input (negative edge) @@ -251,10 +299,10 @@ gen_dqs_out: end generate gen_dqs_out; -- Tristate-Control fuer dqs - process (sys_clk0) is + process (clk0) is variable zctrl : boolean; begin - if rising_edge(sys_clk0) then + if rising_edge(clk0) then if dqs_drive = '1' then zctrl := false; else @@ -275,21 +323,23 @@ gen_out_mux_dqs: end generate gen_out_mux_dqs; ------------------------------------------------------------------------------------------------------------------------------------------------ - process (sys_rst, sys_clk0) is + process (clk0) is begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; + if rising_edge(clk0) then + if rst0 = '1' then + part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); + part_ctrl_reg.ba <= (others=>'0'); + part_ctrl_reg.addr <= (others=>'0'); + part_ctrl_reg.cke <= '0'; + else + part_ctrl_reg <= part_ctrl; + end if; end if; end process; - process (sys_clk0) is + process (clk0) is begin - if falling_edge(sys_clk0) then + if falling_edge(clk0) then part_ras_n <= part_ctrl_reg.cmd.ras_n; part_cas_n <= part_ctrl_reg.cmd.cas_n; part_we_n <= part_ctrl_reg.cmd.we_n; @@ -318,7 +368,7 @@ gen_ddr_data_in: ( Q1 => data_r(n), -- 1-bit output for positive edge of clock Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input + C => clk_rd, -- 1-bit clock input CE => read_en, -- 1-bit clock enable input D => part_data(n), -- 1-bit DDR data input R => '0', -- 1-bit reset @@ -328,37 +378,39 @@ gen_ddr_data_in: data_sample_stage: - process (sys_clk0) + process (clk0) begin - if falling_edge(sys_clk0) then + if falling_edge(clk0) then data_reg_r <= data_r; end if; end process; misc_flags_and_data_out: - process (sys_rst, sys_clk0) + process (clk0) variable p : unsigned(3 downto 0); begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; + if rising_edge(clk0) then + if rst0 = '1' then + p := (others => '0'); + read_en <= '0'; + sdr_data_vld <= '0'; + sdr_data_req_w <= '0'; else - p := p(p'left-1 downto 0) & '0'; + sdr_data_r <= data_reg_r; + if p(3) = '1' then + u_tag_rd <= u_tag_pipe(4); + end if; + if phy_ctrl.we = '1' then + u_tag_wr <= u_tag_pipe(0); + end if; + sdr_data_req_w <= phy_ctrl.we; + sdr_data_vld <= p(3); + read_en <= p(1); + if phy_ctrl.re = '1' then + p := p(p'left-1 downto 0) & '1'; + else + p := p(p'left-1 downto 0) & '0'; + end if; end if; end if; end process; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index 5d997c3..197ef82 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -41,9 +41,8 @@ entity sdram_ctrl_frontend64_wb is ( RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; - SDRAM_CLK0_I : in STD_LOGIC; - SDRAM_CLK270_I : in STD_LOGIC; - SDRAM_CLK270VAR_I : in STD_LOGIC; + SDRAM_CLK_I : in STD_LOGIC; + SDRAM_CLK_FB_I : in STD_LOGIC; CYC_I : in STD_LOGIC; STB_I : in STD_LOGIC; @@ -75,7 +74,8 @@ end sdram_ctrl_frontend64_wb; architecture struct of sdram_ctrl_frontend64_wb is - -- Number of user data words for simulation + signal SDRAM_CLK0 : std_logic; + signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; signal u_tag_rd : user_tag_t; @@ -167,7 +167,7 @@ begin ( rst => RST_I, clk_w => CLK_I, - clk_r => SDRAM_CLK0_I, + clk_r => SDRAM_CLK0, we => write_fifo_we, re => write_fifo_re, fifo_full => write_fifo_full, @@ -188,7 +188,7 @@ begin PORT MAP ( rst => RST_I, - clk_w => SDRAM_CLK0_I, + clk_w => SDRAM_CLK0, clk_r => CLK_I, we => read_fifo_we, re => read_fifo_re, @@ -201,7 +201,7 @@ begin ); -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top + inst_sdram_ctrl_top : entity work.sdram_ctrl_top Generic map ( BL => BL, @@ -215,9 +215,9 @@ begin sys_rst_in => RST_I, sys_clk_in => CLK_I, - sdram_clk0_in => SDRAM_CLK0_I, - sdram_clk270_in => SDRAM_CLK270_I, - sdram_clk270_rd_in => SDRAM_CLK270VAR_I, + sdram_clk => SDRAM_CLK_I, + sdram_clk_fb => SDRAM_CLK_FB_I, + sdram_clk_out => SDRAM_CLK0, -- User interface u_data_vld => u_data_vld, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index 57002b9..754fad3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -41,9 +41,8 @@ entity sdram_ctrl_frontend_wb is ( RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; - SDRAM_CLK0_I : in STD_LOGIC; - SDRAM_CLK270_I : in STD_LOGIC; - SDRAM_CLK270VAR_I : in STD_LOGIC; + SDRAM_CLK_I : in STD_LOGIC; + SDRAM_CLK_FB_I : in STD_LOGIC; CYC_I : in STD_LOGIC; STB_I : in STD_LOGIC; @@ -75,7 +74,8 @@ end sdram_ctrl_frontend_wb; architecture struct of sdram_ctrl_frontend_wb is - -- Number of user data words for simulation + signal SDRAM_CLK0 : std_logic; + signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; signal u_tag_rd : user_tag_t; @@ -167,7 +167,7 @@ begin ( rst => RST_I, clk_w => CLK_I, - clk_r => SDRAM_CLK0_I, + clk_r => SDRAM_CLK0, we => write_fifo_we, re => write_fifo_re, fifo_full => write_fifo_full, @@ -188,7 +188,7 @@ begin PORT MAP ( rst => RST_I, - clk_w => SDRAM_CLK0_I, + clk_w => SDRAM_CLK0, clk_r => CLK_I, we => read_fifo_we, re => read_fifo_re, @@ -201,7 +201,7 @@ begin ); -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top + inst_sdram_ctrl_top : entity work.sdram_ctrl_top Generic map ( BL => BL, @@ -215,10 +215,10 @@ begin sys_rst_in => RST_I, sys_clk_in => CLK_I, - sdram_clk0_in => SDRAM_CLK0_I, - sdram_clk270_in => SDRAM_CLK270_I, - sdram_clk270_rd_in => SDRAM_CLK270VAR_I, - + sdram_clk => SDRAM_CLK_I, + sdram_clk_fb => SDRAM_CLK_FB_I, + sdram_clk_out => SDRAM_CLK0, + -- User interface u_data_vld => u_data_vld, u_data_req_w => u_req_wr, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index 8d4a9a4..07e2b7e 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -41,9 +41,9 @@ entity sdram_ctrl_top is sys_rst_in : in STD_LOGIC; sys_clk_in : in STD_LOGIC; - sdram_clk0_in : in STD_LOGIC; - sdram_clk270_in : in STD_LOGIC; - sdram_clk270_rd_in : in STD_LOGIC; + sdram_clk : in STD_LOGIC; + sdram_clk_fb : in STD_LOGIC; + sdram_clk_out : out STD_LOGIC; -- User interface u_data_vld : out STD_LOGIC; @@ -79,6 +79,8 @@ end sdram_ctrl_top; architecture rtl of sdram_ctrl_top is + signal sdram_clk0 : std_logic; + signal sdram_rst0 : std_logic; signal phy_ctrl : phy_ctrl_t; signal u_tag : user_tag_t; @@ -115,7 +117,8 @@ architecture rtl of sdram_ctrl_top is alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); begin - + sdram_clk_out <= sdram_clk0; + --------------------------------- part_ctrl.cmd <= cmd_ctrl; part_ctrl.ba <= ba; @@ -163,9 +166,9 @@ begin ) PORT MAP ( - rst => sys_rst_in, + rst => sdram_rst0, clk_w => sys_clk_in, - clk_r => sdram_clk0_in, + clk_r => sdram_clk0, we => cmd_fifo_we, re => cmd_fifo_re, fifo_full => cmd_fifo_full, @@ -185,8 +188,8 @@ begin ) Port map ( - rst => sys_rst_in, - clk => sdram_clk0_in, + rst => sdram_rst0, + clk => sdram_clk0, u_tag_in => sd_tag_fifo_out, u_tag_out => u_tag, phy_ctrl => phy_ctrl, @@ -202,16 +205,21 @@ begin ); -- DDR phy - inst_ddr_phy : entity work.ddr_phy + inst_sdram_phy : entity work.sdram_phy + Generic map + ( + f_sdrclk => f_sdrclk + ) Port map ( - sys_rst => sys_rst_in, - sys_clk0 => sdram_clk0_in, - sys_clk270 => sdram_clk270_in, + rst => sys_rst_in, + clk => sdram_clk, + clk_fb => sdram_clk_fb, + clk0_out => sdram_clk0, + rst0_out => sdram_rst0, u_tag_in => u_tag, u_tag_rd => u_tag_rd, u_tag_wr => u_tag_wr, - read_clk => sdram_clk270_rd_in, phy_ctrl => phy_ctrl, part_ctrl => part_ctrl, sdr_data_req_w => u_data_req_w, diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd index c938268..f8efc0c 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd @@ -25,7 +25,6 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; -use work.fifo_ctrl_pkg.all; use work.sdram_config.all; use work.sdram_types.all; @@ -34,18 +33,12 @@ end; architecture struct of tb_sdram_ctrl_frontend64_wb is - -- Number of user data words for simulation constant CLK_PERIOD : time := 10 ns; constant SDCLK_PERIOD : time := 7.5 ns; constant BURST_LEN : natural := 2; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; signal sdclk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; + signal sdclk_fb : std_logic; signal part_clk_p : std_logic; signal part_clk_n : std_logic; signal part_cke : std_logic; @@ -59,11 +52,8 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal CLK_O : std_logic; - signal CLK0_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; + signal CLK_O : std_logic := '1'; + signal RST_O : std_logic := '1'; signal CYC_O : std_logic := '0'; signal STB_O : std_logic := '0'; signal WE_O : std_logic := '0'; @@ -119,30 +109,8 @@ begin end if; end process; -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => 100.0, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => sdclk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° - clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); + sdclk_fb <= part_clk_p after 1 ns; - clk_fb <= part_clk_p after 1 ns; - CLK_O <= clk; - RST_O <= not locked; DAT_O <= X"DEADBEEF" & sddat; SEL_O <= "0000" & sdsel; @@ -159,9 +127,9 @@ inst_clockgen : entity work.clockgen ( RST_I => RST_O, CLK_I => CLK_O, - SDRAM_CLK0_I => CLK0_O, - SDRAM_CLK270_I => CLK270_O, - SDRAM_CLK270VAR_I => CLK270VAR_O, + SDRAM_CLK_I => sdclk, + SDRAM_CLK_FB_I => sdclk_fb, + CYC_I => CYC_O, STB_I => STB_O, SEL_I => SEL_O, @@ -228,7 +196,7 @@ i_mt46v16m16_1 : entity work.mt46v16m16 CLK_GEN: process begin wait for CLK_PERIOD/2; - clk <= not clk; + CLK_O <= not CLK_O; end process; SDCLK_GEN: process @@ -257,7 +225,7 @@ STIMULUS: process begin wait for 3*CLK_PERIOD; - rst <= '0'; + RST_O <= '0'; wait until RST_O = '0'; -- 8 single cycles diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd index 804f761..3544e01 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd @@ -25,7 +25,6 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; -use work.fifo_ctrl_pkg.all; use work.sdram_config.all; use work.sdram_types.all; @@ -39,13 +38,8 @@ architecture struct of tb_sdram_ctrl_frontend_wb is constant SDCLK_PERIOD : time := 8 ns; constant BURST_LEN : natural := 2; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; signal sdclk : std_logic := '1'; - signal locked : std_logic; - signal error : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; + signal sdclk_fb : std_logic; signal part_clk_p : std_logic; signal part_clk_n : std_logic; signal part_cke : std_logic; @@ -59,11 +53,8 @@ architecture struct of tb_sdram_ctrl_frontend_wb is signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal CLK_O : std_logic; - signal CLK0_O : std_logic; - signal CLK270_O : std_logic; - signal CLK270VAR_O : std_logic; - signal RST_O : std_logic; + signal CLK_O : std_logic := '1'; + signal RST_O : std_logic := '1'; signal CYC_O : std_logic := '0'; signal STB_O : std_logic := '0'; signal WE_O : std_logic := '0'; @@ -116,30 +107,7 @@ begin end if; end process; -inst_clockgen : entity work.clockgen - GENERIC MAP - ( - clk_in_freq => 100.0, - clk0_out_phaseshift => 0, - clk1_out_phaseshift => 0 - ) - PORT MAP - ( - -- Clocks and Reset - rst => rst, -- external async reset, low active - clk_in => sdclk, -- system clock (e.g. 100MHz), from board - clk_fb_in => clk_fb, -- feedback clock - clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0° - clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270° - clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0° - clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270° - locked_out => locked, -- DCM locked status - error_out => error - ); - - clk_fb <= part_clk_p after 1 ns; - RST_O <= not locked; - CLK_O <= clk; + sdclk_fb <= part_clk_p after 1 ns; -- DDR SDRAM Controller Core sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb @@ -154,9 +122,8 @@ inst_clockgen : entity work.clockgen ( RST_I => RST_O, CLK_I => CLK_O, - SDRAM_CLK0_I => CLK0_O, - SDRAM_CLK270_I => CLK270_O, - SDRAM_CLK270VAR_I => CLK270VAR_O, + SDRAM_CLK_I => sdclk, + SDRAM_CLK_FB_I => sdclk_fb, CYC_I => CYC_O, STB_I => STB_O, @@ -224,7 +191,7 @@ i_mt46v16m16_1 : entity work.mt46v16m16 CLK_GEN: process begin wait for CLK_PERIOD/2; - clk <= not clk; + CLK_O <= not CLK_O; end process; SDCLK_GEN: process @@ -253,7 +220,7 @@ STIMULUS: process begin wait for 3*CLK_PERIOD; - rst <= '0'; + RST_O <= '0'; wait until RST_O = '0'; -- 8 single cycles