diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par index 4ea9ab9..8c1082d 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.par +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -1,7 +1,7 @@ Release 10.1.03 par K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -JUPITER:: Tue Feb 09 12:58:54 2010 +JUPITER:: Sun Feb 14 18:14:54 2010 par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd mips_sys.pcf @@ -31,8 +31,8 @@ Device Utilization Summary: Number of OLOGICs 182 out of 448 40% Number of RAMB16s 51 out of 192 26% - Number of Slices 6053 out of 15360 39% - Number of SLICEMs 549 out of 7680 7% + Number of Slices 6008 out of 15360 39% + Number of SLICEMs 558 out of 7680 7% @@ -44,54 +44,38 @@ Finished initial Timing Analysis. REAL time: 14 secs Starting Router -Phase 1: 48053 unrouted; REAL time: 16 secs +Phase 1: 48218 unrouted; REAL time: 15 secs -Phase 2: 40978 unrouted; REAL time: 16 secs +Phase 2: 41114 unrouted; REAL time: 16 secs -Phase 3: 15724 unrouted; REAL time: 24 secs +Phase 3: 15775 unrouted; REAL time: 22 secs -Phase 4: 15724 unrouted; (426198) REAL time: 24 secs +Phase 4: 15775 unrouted; (290927) REAL time: 23 secs -Phase 5: 16453 unrouted; (4039) REAL time: 27 secs +Phase 5: 16549 unrouted; (7681) REAL time: 26 secs -Phase 6: 16476 unrouted; (459) REAL time: 27 secs +Phase 6: 16600 unrouted; (0) REAL time: 26 secs -Phase 7: 0 unrouted; (12926) REAL time: 55 secs +Phase 7: 0 unrouted; (942) REAL time: 53 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 8: 0 unrouted; (7751) REAL time: 1 mins 38 secs +Phase 8: 0 unrouted; (942) REAL time: 1 mins 14 secs -Phase 9: 0 unrouted; (4297) REAL time: 2 mins 14 secs +Phase 9: 0 unrouted; (942) REAL time: 1 mins 20 secs -Phase 10: 0 unrouted; (4297) REAL time: 3 mins 13 secs +Phase 10: 0 unrouted; (0) REAL time: 1 mins 26 secs + +Phase 11: 0 unrouted; (0) REAL time: 1 mins 27 secs Updating file: mips_sys.ncd with current fully routed design. -Phase 11: 0 unrouted; (3077) REAL time: 3 mins 31 secs +Phase 12: 0 unrouted; (0) REAL time: 1 mins 46 secs -Phase 12: 0 unrouted; (1330) REAL time: 3 mins 38 secs +Phase 13: 0 unrouted; (0) REAL time: 1 mins 52 secs -Phase 13: 0 unrouted; (1330) REAL time: 3 mins 39 secs - -Updating file: mips_sys.ncd with current fully routed design. - -Phase 14: 0 unrouted; (1207) REAL time: 5 mins 31 secs - -Updating file: mips_sys.ncd with current fully routed design. - -Phase 15: 0 unrouted; (0) REAL time: 8 mins 27 secs - -Phase 16: 0 unrouted; (0) REAL time: 8 mins 28 secs - -Updating file: mips_sys.ncd with current fully routed design. - -Phase 17: 0 unrouted; (0) REAL time: 8 mins 47 secs - -Phase 18: 0 unrouted; (0) REAL time: 8 mins 53 secs - -Total REAL time to Router completion: 8 mins 55 secs -Total CPU time to Router completion: 8 mins 32 secs +Total REAL time to Router completion: 1 mins 54 secs +Total CPU time to Router completion: 1 mins 49 secs Partition Implementation Status ------------------------------- @@ -109,28 +93,28 @@ Generating Clock Report +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ +| cpu_clk |BUFGCTRL_X0Y12| No | 1638 | 0.443 | 4.049 | ++---------------------+--------------+------+------+------------+-------------+ +| CLK_O | BUFGCTRL_X0Y2| No | 2331 | 0.533 | 3.922 | ++---------------------+--------------+------+------+------------+-------------+ +| vga_clk |BUFGCTRL_X0Y11| No | 167 | 0.287 | 3.881 | ++---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_clk1 | BUFGCTRL_X0Y0| No | 72 | 0.251 | 3.733 | +| /bs_clk1 | BUFGCTRL_X0Y0| No | 75 | 0.416 | 3.851 | +---------------------+--------------+------+------+------------+-------------+ -| CLK_O | BUFGCTRL_X0Y2| No | 2351 | 0.515 | 3.904 | -+---------------------+--------------+------+------+------------+-------------+ -| cpu_clk |BUFGCTRL_X0Y12| No | 1601 | 0.402 | 4.005 | -+---------------------+--------------+------+------+------------+-------------+ -| vga_clk |BUFGCTRL_X0Y11| No | 175 | 0.394 | 3.881 | +| sdram_clk0 |BUFGCTRL_X0Y31| No | 241 | 0.494 | 3.933 | +---------------------+--------------+------+------+------------+-------------+ |sys_ac97_bit_clk_IBU | | | | | | -| F | BUFGCTRL_X0Y8| No | 262 | 0.414 | 3.851 | +| F | BUFGCTRL_X0Y8| No | 251 | 0.356 | 3.903 | +---------------------+--------------+------+------+------------+-------------+ -| sdram_clk0 |BUFGCTRL_X0Y31| No | 233 | 0.527 | 3.933 | +| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 62 | 0.223 | 3.686 | +---------------------+--------------+------+------+------------+-------------+ -| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 59 | 0.346 | 3.799 | -+---------------------+--------------+------+------+------------+-------------+ -| sdram_clk270 |BUFGCTRL_X0Y16| No | 67 | 0.174 | 3.932 | +| sdram_clk270 |BUFGCTRL_X0Y16| No | 65 | 0.160 | 3.932 | +---------------------+--------------+------+------+------------+-------------+ | sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 | +---------------------+--------------+------+------+------------+-------------+ |inst_rom_wb/inst_rom | | | | | | -| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.018 | 3.605 | +| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.146 | 3.628 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing @@ -149,27 +133,27 @@ Asterisk (*) preceding a constraint indicates it was not met. Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ - TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.001ns| 9.899ns| 0| 0 - ns HIGH 50% | HOLD | 0.309ns| | 0| 0 + TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | 0.018ns| 9.864ns| 0| 0 + ns HIGH 50% | HOLD | 0.314ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.020ns| 9.880ns| 0| 0 - HIGH 50% | HOLD | 0.359ns| | 0| 0 + TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.054ns| 7.392ns| 0| 0 + 7.5 ns HIGH 50% | HOLD | 0.518ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.077ns| 7.923ns| 0| 0 - s HIGH 50% | HOLD | 0.490ns| | 0| 0 + TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.109ns| 7.891ns| 0| 0 + s HIGH 50% | HOLD | 0.480ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.152ns| 7.348ns| 0| 0 - 7.5 ns HIGH 50% | HOLD | 0.511ns| | 0| 0 + TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.166ns| 9.734ns| 0| 0 + HIGH 50% | HOLD | 0.333ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.794ns| 9.594ns| 0| 0 - ns HIGH 50% | HOLD | 0.509ns| | 0| 0 + NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 35.896ns| 8.208ns| 0| 0 + ns HIGH 50% | HOLD | 0.518ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 73.898ns| 6.102ns| 0| 0 - ns HIGH 50% | HOLD | 0.852ns| | 0| 0 + TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 75.311ns| 4.689ns| 0| 0 + ns HIGH 50% | HOLD | 0.783ns| | 0| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.779ns| N/A| 0 + PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.588ns| N/A| 0 ------------------------------------------------------------------------------------------------------ - PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.002ns| N/A| 0 + PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.296ns| N/A| 0 ------------------------------------------------------------------------------------------------------ @@ -182,10 +166,10 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 9 mins 7 secs -Total CPU time to PAR completion: 8 mins 40 secs +Total REAL time to PAR completion: 2 mins 3 secs +Total CPU time to PAR completion: 1 mins 55 secs -Peak Memory Usage: 425 MB +Peak Memory Usage: 453 MB Placer: Placement generated during map. Routing: Completed - No errors found. diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr index 71ac1df..1957dc4 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.syr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.11 secs --> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.11 secs --> Reading design: mips_sys.prj @@ -157,8 +157,7 @@ Architecture low_level_definition of Entity kcuart_tx is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work. Architecture behavioral of Entity debounce is up to date. Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture behavioral of Entity ps2_core is up to date. Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work. Architecture behavioral of Entity fifo_sync is up to date. Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work. @@ -176,8 +175,7 @@ Architecture macro_level_definition of Entity uart_rx is up to date. Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work. Architecture async_types of Entity async_types is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture data of Entity rom is up to date. Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work. Architecture mips_types of Entity mips_types is up to date. Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work. @@ -186,8 +184,7 @@ Architecture behavior of Entity rom_wb is up to date. Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work. Architecture behavioral of Entity lcd_port is up to date. Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture behavior of Entity gpio_wb is up to date. Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work. Architecture behavioral of Entity async_port_wb is up to date. Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work. @@ -326,21 +323,30 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 30 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 72 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 64 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. BL = 2 @@ -364,21 +370,30 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. addr_width = 11 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 256 almost_full_thresh = 1920 data_width = 64 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 9 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 64 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. addr_width = 2 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 105 + do_last_read_update = false Analyzing hierarchy for entity in library (architecture ) with generics. CHARACTER_SCALE = 1 @@ -406,9 +421,12 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. addr_width = 8 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 25 almost_full_thresh = 230 data_width = 18 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ). @@ -452,9 +470,12 @@ Analyzing hierarchy for entity in library (architecture in library (architecture ) with generics. addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 32 + do_last_read_update = true Analyzing hierarchy for entity in library (architecture ) with generics. BL = 2 @@ -881,9 +902,12 @@ Entity analyzed. Unit gene Analyzing generic Entity in library (Architecture ). addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 30 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -899,9 +923,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 72 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -922,9 +949,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 64 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -948,9 +978,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 5 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 32 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -1240,7 +1273,7 @@ WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconn WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_afull' of component 'fifo_sync'. WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. -WARNING:Xst:819 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 435: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: +WARNING:Xst:819 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 436: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: Entity analyzed. Unit generated. @@ -1292,9 +1325,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 11 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 256 almost_full_thresh = 1920 data_width = 64 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -1315,9 +1351,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 9 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 64 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -1333,9 +1372,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 2 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 4 almost_full_thresh = 12 data_width = 105 + do_last_read_update = false Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -1389,9 +1431,12 @@ Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). addr_width = 8 + allow_empty_reads = false + allow_full_writes = false almost_empty_thresh = 25 almost_full_thresh = 230 data_width = 18 + do_last_read_update = true Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). @@ -1644,15 +1689,15 @@ WARNING:Xst:1780 - Signal is never used or assigned. This unconnected s Found 1-bit register for signal . Found 6-bit updown counter for signal . Found 1-bit register for signal . - Found 6-bit comparator lessequal for signal created at line 108. - Found 6-bit comparator greatequal for signal created at line 94. + Found 6-bit comparator lessequal for signal created at line 104. + Found 6-bit comparator greatequal for signal created at line 90. Found 1-bit register for signal . Found 5-bit register for signal . - Found 5-bit adder for signal created at line 196. - Found 5-bit comparator equal for signal created at line 144. - Found 5-bit comparator equal for signal created at line 139. + Found 5-bit adder for signal created at line 192. + Found 5-bit comparator equal for signal created at line 140. + Found 5-bit comparator equal for signal created at line 135. Found 5-bit register for signal . - Found 5-bit adder for signal created at line 178. + Found 5-bit adder for signal created at line 174. Found 1-bit register for signal . Summary: inferred 1 Counter(s). @@ -1684,18 +1729,16 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found 6-bit register for signal . - Found 6-bit register for signal . Found 6-bit register for signal . - Found 6-bit adder for signal created at line 80. + Found 6-bit register for signal . + Found 6-bit adder for signal created at line 78. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Summary: - inferred 18 D-type flip-flop(s). + inferred 12 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. @@ -1862,11 +1905,9 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd". -WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. - Found 12-bit register for signal . - Found 12-bit register for signal . Found 12-bit register for signal . - Found 12-bit adder for signal created at line 80. + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 78. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. @@ -1879,7 +1920,7 @@ WARNING:Xst:646 - Signal is assigned but never used. This unconnected sig Found 1-bit xor2 for signal created at line 48. Found 1-bit xor2 for signal created at line 48. Summary: - inferred 36 D-type flip-flop(s). + inferred 24 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). Unit synthesized. @@ -1892,15 +1933,15 @@ WARNING:Xst:1780 - Signal is never used or assigned. This unconnected s Found 1-bit register for signal . Found 10-bit updown counter for signal . Found 1-bit register for signal . - Found 10-bit comparator lessequal for signal created at line 108. - Found 10-bit comparator greatequal for signal created at line 94. + Found 10-bit comparator lessequal for signal created at line 104. + Found 10-bit comparator greatequal for signal created at line 90. Found 1-bit register for signal . Found 9-bit register for signal . - Found 9-bit adder for signal created at line 196. - Found 9-bit comparator equal for signal created at line 144. - Found 9-bit comparator equal for signal created at line 139. + Found 9-bit adder for signal created at line 192. + Found 9-bit comparator equal for signal created at line 140. + Found 9-bit comparator equal for signal created at line 135. Found 9-bit register for signal . - Found 9-bit adder for signal created at line 178. + Found 9-bit adder for signal created at line 174. Found 1-bit register for signal . Summary: inferred 1 Counter(s). @@ -1927,14 +1968,14 @@ WARNING:Xst:1780 - Signal is never used or assigned. This unconnected s Found 1-bit register for signal . Found 3-bit updown counter for signal . Found 1-bit register for signal . - Found 3-bit comparator lessequal for signal created at line 108. + Found 3-bit comparator lessequal for signal created at line 104. Found 1-bit register for signal . Found 2-bit register for signal . - Found 2-bit adder for signal created at line 196. - Found 2-bit comparator equal for signal created at line 144. - Found 2-bit comparator equal for signal created at line 139. + Found 2-bit adder for signal created at line 192. + Found 2-bit comparator equal for signal created at line 140. + Found 2-bit comparator equal for signal created at line 135. Found 2-bit register for signal . - Found 2-bit adder for signal created at line 178. + Found 2-bit adder for signal created at line 174. Found 1-bit register for signal . Summary: inferred 1 Counter(s). @@ -1982,15 +2023,15 @@ WARNING:Xst:1780 - Signal is never used or assigned. This unconnected s Found 1-bit register for signal . Found 9-bit updown counter for signal . Found 1-bit register for signal . - Found 9-bit comparator lessequal for signal created at line 108. - Found 9-bit comparator greatequal for signal created at line 94. + Found 9-bit comparator lessequal for signal created at line 104. + Found 9-bit comparator greatequal for signal created at line 90. Found 1-bit register for signal . Found 8-bit register for signal . - Found 8-bit adder for signal created at line 196. - Found 8-bit comparator equal for signal created at line 144. - Found 8-bit comparator equal for signal created at line 139. + Found 8-bit adder for signal created at line 192. + Found 8-bit comparator equal for signal created at line 140. + Found 8-bit comparator equal for signal created at line 135. Found 8-bit register for signal . - Found 8-bit adder for signal created at line 178. + Found 8-bit adder for signal created at line 174. Found 1-bit register for signal . Summary: inferred 1 Counter(s). @@ -2216,6 +2257,7 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. @@ -2227,13 +2269,13 @@ Synthesizing Unit . Found 6-bit register for signal . Found 6-bit register for signal . Found 6-bit adder for signal . - Found 6-bit subtractor for signal created at line 192. + Found 6-bit subtractor for signal created at line 189. Found 6-bit register for signal . Found 6-bit adder for signal . - Found 6-bit subtractor for signal created at line 212. + Found 6-bit subtractor for signal created at line 209. Found 1-bit register for signal . - Found 6-bit comparator lessequal for signal created at line 207. - Found 6-bit comparator greatequal for signal created at line 187. + Found 6-bit comparator lessequal for signal created at line 204. + Found 6-bit comparator greatequal for signal created at line 184. Found 1-bit register for signal . Found 6-bit register for signal . Found 6-bit register for signal . @@ -2245,8 +2287,8 @@ Synthesizing Unit . Found 6-bit register for signal . Found 6-bit register for signal . Found 6-bit register for signal . - Found 6-bit comparator equal for signal created at line 147. - Found 6-bit comparator equal for signal created at line 137. + Found 6-bit comparator equal for signal created at line 144. + Found 6-bit comparator equal for signal created at line 134. Summary: inferred 88 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). @@ -2296,6 +2338,7 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. @@ -2419,13 +2462,13 @@ Synthesizing Unit . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit adder for signal . - Found 12-bit subtractor for signal created at line 192. + Found 12-bit subtractor for signal created at line 189. Found 12-bit register for signal . Found 12-bit adder for signal . - Found 12-bit subtractor for signal created at line 212. + Found 12-bit subtractor for signal created at line 209. Found 1-bit register for signal . - Found 12-bit comparator lessequal for signal created at line 207. - Found 12-bit comparator greatequal for signal created at line 187. + Found 12-bit comparator lessequal for signal created at line 204. + Found 12-bit comparator greatequal for signal created at line 184. Found 1-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . @@ -2437,8 +2480,8 @@ Synthesizing Unit . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . - Found 12-bit comparator equal for signal created at line 147. - Found 12-bit comparator equal for signal created at line 137. + Found 12-bit comparator equal for signal created at line 144. + Found 12-bit comparator equal for signal created at line 134. Summary: inferred 172 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). @@ -2449,6 +2492,7 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. @@ -2541,18 +2585,21 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. @@ -2578,6 +2625,7 @@ Unit synthesized. Synthesizing Unit . Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. Unit synthesized. @@ -2668,38 +2716,38 @@ WARNING:Xst:653 - Signal is used but never assigned. This sourceless sign Found 32-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . - Found 32-bit adder for signal created at line 639. - Found 32-bit comparator equal for signal created at line 638. - Found 32-bit comparator not equal for signal created at line 638. + Found 32-bit adder for signal created at line 640. + Found 32-bit comparator equal for signal created at line 639. + Found 32-bit comparator not equal for signal created at line 639. Found 32-bit up counter for signal . Found 1-bit register for signal . - Found 32-bit comparator not equal for signal created at line 642. + Found 32-bit comparator not equal for signal created at line 643. Found 32-bit up accumulator for signal . - Found 32-bit comparator equal for signal created at line 642. + Found 32-bit comparator equal for signal created at line 643. Found 32-bit register for signal . - Found 32-bit adder for signal created at line 640. + Found 32-bit adder for signal created at line 641. Found 4-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . - Found 32-bit adder for signal created at line 609. - Found 32-bit comparator equal for signal created at line 608. - Found 32-bit comparator not equal for signal created at line 608. + Found 32-bit adder for signal created at line 610. + Found 32-bit comparator equal for signal created at line 609. + Found 32-bit comparator not equal for signal created at line 609. Found 32-bit up counter for signal . Found 1-bit register for signal . - Found 32-bit comparator not equal for signal created at line 612. + Found 32-bit comparator not equal for signal created at line 613. Found 32-bit up accumulator for signal . - Found 32-bit comparator equal for signal created at line 612. + Found 32-bit comparator equal for signal created at line 613. Found 32-bit register for signal . - Found 32-bit adder for signal created at line 610. + Found 32-bit adder for signal created at line 611. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . - Found 29-bit comparator equal for signal created at line 549. + Found 29-bit comparator equal for signal created at line 550. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . @@ -2872,10 +2920,10 @@ Macro Statistics 9-bit updown counter : 1 # Accumulators : 2 32-bit up loadable accumulator : 2 -# Registers : 739 +# Registers : 731 1-bit register : 493 105-bit register : 1 - 12-bit register : 20 + 12-bit register : 18 13-bit register : 5 16-bit register : 6 18-bit register : 1 @@ -2888,7 +2936,7 @@ Macro Statistics 4-bit register : 15 48-bit register : 2 5-bit register : 9 - 6-bit register : 61 + 6-bit register : 55 64-bit register : 5 7-bit register : 4 72-bit register : 1 @@ -3196,7 +3244,7 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 32-word x 30-bit | | | mode | write-first | | | clkA | connected to signal | rise | - | weA | connected to signal | high | + | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- @@ -3206,7 +3254,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 32-word x 30-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3233,7 +3280,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 32-word x 72-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3260,7 +3306,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 32-word x 64-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3287,7 +3332,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 2048-word x 64-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3304,7 +3348,7 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 512-word x 64-bit | | | mode | write-first | | | clkA | connected to signal | rise | - | weA | connected to signal | high | + | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- @@ -3314,7 +3358,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 512-word x 64-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3330,7 +3373,7 @@ INFO:Xst - The small RAM will be implemented on LUTs in order to maxi | Port A | | aspect ratio | 4-word x 105-bit | | | clkA | connected to signal | rise | - | weA | connected to signal | high | + | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- @@ -3376,7 +3419,7 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 256-word x 18-bit | | | mode | write-first | | | clkA | connected to signal | rise | - | weA | connected to signal | high | + | weA | connected to signal | high | | addrA | connected to signal | | | diA | connected to signal | | ----------------------------------------------------------------------- @@ -3386,7 +3429,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 256-word x 18-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3413,7 +3455,6 @@ INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the | aspect ratio | 32-word x 32-bit | | | mode | read-first | | | clkB | connected to signal | rise | - | enB | connected to signal | high | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- @@ -3455,25 +3496,7 @@ WARNING:Xst:2677 - Node of sequential type is unconnected in block WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : WARNING:Xst:2677 - Node of sequential type is unconnected in block . -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : @@ -4224,8 +4247,8 @@ Optimizing unit ... Optimizing unit ... Optimizing unit ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Optimizing unit ... @@ -4235,8 +4258,8 @@ WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a WARNING:Xst:2677 - Node of sequential type is unconnected in block . Optimizing unit ... -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Optimizing unit ... @@ -4538,22 +4561,22 @@ Found area constraint ratio of 100 (+ 5) on block mips_sys, actual ratio is 19. Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/Mcount_count_cy<0> Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/Mcount_count_cy<0> Forward register balancing over carry chain inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/Madd_nxtb_addsub0000_cy<0> -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : -INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : @@ -4566,7 +4589,7 @@ Pipelining and Register Balancing Report ... Processing Unit : Register(s) inst_vga_frontend/s_FSM_FFd4 inst_vga_frontend/s_FSM_FFd1 has(ve) been forward balanced into : inst_vga_frontend/s_FSM_Out51_FRB. Register(s) inst_ac97_wb/ac_cmd_addr_19 has(ve) been backward balanced into : inst_ac97_wb/ac_cmd_addr_19_BRB0. - Register(s) inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19 has(ve) been backward balanced into : inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB1. + Register(s) inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19 has(ve) been backward balanced into : inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB1 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB2. Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3. Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB2 . Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB2 . @@ -4580,9 +4603,10 @@ Processing Unit : Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB3. Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB1. Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB1. - Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB2. - Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB2. - Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg_3_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_3_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_3_BRB2. + Register(s) inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full has(ve) been backward balanced into : inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB0 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB1 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/full_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB1. @@ -4596,6 +4620,10 @@ Processing Unit : Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB1. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_6_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_7_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_8_BRB2. Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB2. Register(s) inst_vga_frontend/inst_vga_backend/hsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/hsync_r_BRB0 inst_vga_frontend/inst_vga_backend/hsync_r_BRB1. Register(s) inst_vga_frontend/inst_vga_backend/vsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/vsync_r_BRB0. @@ -4610,9 +4638,9 @@ Replicating register inst_usb_port/Mtrien_async_d to handle IOB=TRUE attribute Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0 to handle IOB=TRUE attribute Replicating register inst_flash_port/Mtrien_async_d to handle IOB=TRUE attribute -FlipFlop arb_gnt_0 has been replicated 1 time(s) +FlipFlop arb_gnt_0 has been replicated 2 time(s) FlipFlop arb_gnt_1 has been replicated 1 time(s) -FlipFlop inst_clockgen/sys_rst_out has been replicated 11 time(s) +FlipFlop inst_clockgen/sys_rst_out has been replicated 14 time(s) FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s) FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s) FlipFlop inst_vga_frontend/s_FSM_Out51_FRB has been replicated 1 time(s) @@ -4623,7 +4651,7 @@ Processing Unit : Found 4-bit shift register for signal . Found 3-bit shift register for signal . Found 3-bit shift register for signal . - Found 3-bit shift register for signal . + Found 3-bit shift register for signal . Found 3-bit shift register for signal . Found 3-bit shift register for signal . Found 3-bit shift register for signal . @@ -4718,17 +4746,17 @@ Processing Unit : Found 3-bit shift register for signal . Found 3-bit shift register for signal . Found 3-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . - Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . Unit processed. ========================================================================= Final Register Report Macro Statistics -# Registers : 3548 - Flip-Flops : 3548 +# Registers : 3559 + Flip-Flops : 3559 # Shift Registers : 101 2-bit shift register : 3 20-bit shift register : 3 @@ -4763,38 +4791,38 @@ Design Statistics # IOs : 226 Cell Usage : -# BELS : 6434 +# BELS : 6423 # GND : 1 -# INV : 95 +# INV : 93 # LUT1 : 352 -# LUT2 : 537 -# LUT2_D : 3 +# LUT2 : 539 +# LUT2_D : 4 # LUT2_L : 3 -# LUT3 : 1062 -# LUT3_D : 14 -# LUT3_L : 7 -# LUT4 : 2160 +# LUT3 : 1056 +# LUT3_D : 10 +# LUT3_L : 6 +# LUT4 : 2167 # LUT4_D : 33 -# LUT4_L : 48 +# LUT4_L : 55 # MULT_AND : 6 # MUXCY : 1017 -# MUXF5 : 260 +# MUXF5 : 245 # MUXF6 : 2 # VCC : 1 # XORCY : 833 -# FlipFlops/Latches : 3789 -# FD : 312 +# FlipFlops/Latches : 3800 +# FD : 318 # FD_1 : 85 # FDC : 268 # FDC_1 : 20 # FDCE : 255 # FDCPE : 4 -# FDE : 1372 +# FDE : 1373 # FDP : 78 -# FDPE : 18 +# FDPE : 21 # FDR : 192 # FDR_1 : 1 -# FDRE : 936 +# FDRE : 937 # FDRS : 58 # FDRSE : 6 # FDS : 26 @@ -4828,10 +4856,10 @@ Device utilization summary: Selected Device : 4vsx35ff668-10 - Number of Slices: 2790 out of 15360 18% - Number of Slice Flip Flops: 3504 out of 30720 11% - Number of 4 input LUTs: 4696 out of 30720 15% - Number used as logic: 4314 + Number of Slices: 2787 out of 15360 18% + Number of Slice Flip Flops: 3515 out of 30720 11% + Number of 4 input LUTs: 4700 out of 30720 15% + Number used as logic: 4318 Number used as Shift registers: 176 Number used as RAMs: 206 Number of IOs: 226 @@ -4863,48 +4891,48 @@ Clock Information: -----------------------------------+---------------------------------------------------------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+---------------------------------------------------------------------------+-------+ -sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3382 | +sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3392 | sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68 | inst_rom_wb/inst_rom/bs_clk0 | BUFG | 98 | sys_clk_in | inst_clockgen/inst_DCM_VGA_FX:CLKFX | 252 | -sys_ac97_bit_clk | IBUF+BUFG | 269 | +sys_ac97_bit_clk | IBUF+BUFG | 270 | sys_sdr_clk_fb | inst_clockgen/inst_DCM_SDRCLK_1:CLK270 | 32 | inst_rom_wb/inst_rom/bs_update0 | BUFG | 4 | -----------------------------------+---------------------------------------------------------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ -Control Signal | Buffer(FF name) | Load | ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ -RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_1) | 290 | -inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_22) | 96 | -RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1)| 74 | -inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_7) | 52 | -inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pW_3) | 29 | -inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_1) | 21 | -inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 | -inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift8) | 20 | -rst_in(rst_in1:O) | NONE(rst_in_shift1) | 20 | -inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 17 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | -inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | ------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+ +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ +RST_O_7(inst_clockgen/sys_rst_out_13:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0)| 289 | +inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_18) | 96 | +RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl/was_write) | 75 | +inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out) | 52 | +inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_4) | 29 | +inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW_5) | 21 | +inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/sdr0_lock_inv_shift10) | 20 | +inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/reset_cnt_0) | 20 | +inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift18) | 20 | +rst_in(rst_in1:O) | NONE(rst_in_shift2) | 20 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +-----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+ Timing Summary: --------------- Speed Grade: -10 - Minimum period: 10.566ns (Maximum Frequency: 94.648MHz) - Minimum input arrival time before clock: 8.069ns - Maximum output required time after clock: 10.889ns - Maximum combinational path delay: 10.497ns + Minimum period: 9.187ns (Maximum Frequency: 108.846MHz) + Minimum input arrival time before clock: 8.055ns + Maximum output required time after clock: 10.710ns + Maximum combinational path delay: 10.288ns Timing Detail: -------------- @@ -4912,34 +4940,24 @@ All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'sys_clk_in' - Clock period: 10.566ns (frequency: 94.648MHz) - Total number of paths / destination ports: 299031 / 8697 + Clock period: 9.187ns (frequency: 108.846MHz) + Total number of paths / destination ports: 289830 / 8693 ------------------------------------------------------------------------- -Delay: 5.283ns (Levels of Logic = 10) - Source: inst_clockgen/sys_rst_out_1 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 (RAM) - Source Clock: sys_clk_in rising - Destination Clock: sys_clk_in rising 0.4X +Delay: 2.297ns (Levels of Logic = 0) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32 (FF) + Source Clock: sys_clk_in falling + Destination Clock: sys_clk_in rising +270 - Data Path: inst_clockgen/sys_rst_out_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 + Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDPE:C->Q 5 0.360 0.546 inst_clockgen/sys_rst_out_1 (RST_O_0) - LUT4:I3->O 10 0.195 0.713 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 (inst_vga_frontend/inst_linefifo/ptr_r<0>) - LUT3:I1->O 2 0.195 0.602 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0>) - LUT4:I2->O 1 0.195 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0>) - MUXCY:S->O 1 0.366 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0>) - MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1>) - MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2>) - MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3>) - MUXCY:CI->O 1 0.044 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4>) - MUXCY:CI->O 2 0.263 0.377 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> (inst_vga_frontend/inst_linefifo/pre_empty) - INV:I->O 7 0.358 0.416 inst_vga_frontend/inst_linefifo/mem_rd_en1_INV_0 (inst_vga_frontend/inst_linefifo/mem_rd_en) - RAMB16:ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 + FD_1:C->Q 32 0.307 0.928 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive (inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive) + FDR:R 1.062 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32 ---------------------------------------- - Total 5.283ns (2.629ns logic, 2.654ns route) - (49.8% logic, 50.2% route) + Total 2.297ns (1.369ns logic, 0.928ns route) + (59.6% logic, 40.4% route) ========================================================================= Timing constraint: Default period analysis for Clock 'inst_rom_wb/inst_rom/bs_clk0' @@ -4964,10 +4982,10 @@ Delay: 2.225ns (Levels of Logic = 0) ========================================================================= Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk' - Clock period: 5.858ns (frequency: 170.696MHz) - Total number of paths / destination ports: 3598 / 516 + Clock period: 5.862ns (frequency: 170.582MHz) + Total number of paths / destination ports: 3505 / 518 ------------------------------------------------------------------------- -Delay: 5.858ns (Levels of Logic = 6) +Delay: 5.862ns (Levels of Logic = 6) Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (FF) Destination: inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF) Source Clock: sys_ac97_bit_clk rising @@ -4977,44 +4995,45 @@ Delay: 5.858ns (Levels of Logic = 6) Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FDRE:C->Q 41 0.360 1.291 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0) - LUT3:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27) - LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26) - LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1312) - MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105) - LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169) - MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>) - FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_9 + FDRE:C->Q 42 0.360 1.295 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_0) + LUT3_D:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27) + LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>26) + LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105_G (N1375) + MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>105) + LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169) + MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<8>) + FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_8 ---------------------------------------- - Total 5.858ns (1.910ns logic, 3.948ns route) + Total 5.862ns (1.910ns logic, 3.952ns route) (32.6% logic, 67.4% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in' - Total number of paths / destination ports: 44076 / 2325 + Total number of paths / destination ports: 44049 / 2324 ------------------------------------------------------------------------- -Offset: 8.069ns (Levels of Logic = 8) - Source: inst_mips_top:ADDR_O<29> (PAD) +Offset: 8.055ns (Levels of Logic = 9) + Source: inst_mips_top:ADDR_O<28> (PAD) Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF) Destination Clock: sys_clk_in rising - Data Path: inst_mips_top:ADDR_O<29> to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 + Data Path: inst_mips_top:ADDR_O<28> to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - mips_top:ADDR_O<29> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<29>) - LUT4_D:I0->O 3 0.195 0.756 Mmux_ADDR_O221 (ADDR_O<29>) - LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1490) - LUT4:I2->O 40 0.195 1.287 CYC_I_flash (CYC_I_flash) - LUT4:I1->O 1 0.195 0.523 SRDY_I26 (SRDY_I26) - LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1500) - LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read1 (inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read) - LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N391) + mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>) + LUT4_D:I0->O 5 0.195 0.711 Mmux_ADDR_O211 (ADDR_O<28>) + LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N403) + LUT4_D:I2->O 1 0.195 0.523 CYC_I_ac971_1 (CYC_I_ac971) + LUT3_L:I2->LO 1 0.195 0.225 SRDY_I26_SW0 (N739) + LUT4:I2->O 1 0.195 0.523 SRDY_I26 (SRDY_I26) + LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1558) + LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/rinc1 (inst_vga_frontend/inst_bus_fifo/rinc) + LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N405) LUT3:I2->O 103 0.195 1.205 inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en) FDE:CE 0.540 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 ---------------------------------------- - Total 8.069ns (2.100ns logic, 5.969ns route) - (26.0% logic, 74.0% route) + Total 8.055ns (2.295ns logic, 5.760ns route) + (28.5% logic, 71.5% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_clk0' @@ -5067,7 +5086,7 @@ Offset: 6.702ns (Levels of Logic = 1) Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N397) + IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N407) IDDR:D 5.377 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data ---------------------------------------- Total 6.702ns (6.342ns logic, 0.360ns route) @@ -5094,9 +5113,9 @@ Offset: 1.341ns (Levels of Logic = 0) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in' - Total number of paths / destination ports: 19933 / 226 + Total number of paths / destination ports: 19309 / 226 ------------------------------------------------------------------------- -Offset: 10.889ns (Levels of Logic = 12) +Offset: 10.710ns (Levels of Logic = 12) Source: inst_vga_frontend/s_FSM_FFd2_1 (FF) Destination: inst_mips_top:DAT_I<13> (PAD) Source Clock: sys_clk_in rising @@ -5106,22 +5125,22 @@ Offset: 10.889ns (Levels of Logic = 12) Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRS:C->Q 1 0.360 0.585 inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1) - LUT2:I0->O 1 0.195 0.523 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src) - LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1493) - LUT4:I3->O 8 0.195 0.608 CYC_O1 (CYC_O) - LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N57) - LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) - LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155) + LUT2_D:I0->O 3 0.195 0.538 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src) + LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1553) + LUT4:I3->O 9 0.195 0.632 CYC_O1 (CYC_O) + LUT4_D:I3->O 17 0.195 0.743 CYC_I_ac971 (N57) + LUT4_D:I3->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1207) LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) - LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887) - LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274) + LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N903) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1340) LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) - LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N875) LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) mips_top:DAT_I<13> 0.000 inst_mips_top ---------------------------------------- - Total 10.889ns (2.700ns logic, 8.189ns route) - (24.8% logic, 75.2% route) + Total 10.710ns (2.700ns logic, 8.010ns route) + (25.2% logic, 74.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk' @@ -5165,7 +5184,7 @@ Offset: 0.720ns (Levels of Logic = 0) Timing constraint: Default path analysis Total number of paths / destination ports: 5396 / 38 ------------------------------------------------------------------------- -Delay: 10.497ns (Levels of Logic = 11) +Delay: 10.288ns (Levels of Logic = 11) Source: inst_mips_top:ADDR_O<28> (PAD) Destination: inst_mips_top:DAT_I<13> (PAD) @@ -5174,33 +5193,33 @@ Delay: 10.497ns (Levels of Logic = 11) Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>) - LUT4_D:I0->O 4 0.195 0.702 Mmux_ADDR_O211 (ADDR_O<28>) - LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N389) - LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N57) - LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) - LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1155) + LUT4_D:I0->O 5 0.195 0.711 Mmux_ADDR_O211 (ADDR_O<28>) + LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N403) + LUT4_D:I2->O 17 0.195 0.743 CYC_I_ac971 (N57) + LUT4_D:I3->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>36_SW0 (N1207) LUT4:I0->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) - LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N887) - LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1274) + LUT4:I2->O 1 0.195 0.741 MDAT_I<13>84_SW0 (N903) + LUT4:I0->O 1 0.195 0.741 MDAT_I<13>84_SW1 (N1340) LUT4:I0->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) - LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N859) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N875) LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) mips_top:DAT_I<13> 0.000 inst_mips_top ---------------------------------------- - Total 10.497ns (2.145ns logic, 8.352ns route) - (20.4% logic, 79.6% route) + Total 10.288ns (2.145ns logic, 8.143ns route) + (20.8% logic, 79.2% route) ========================================================================= -Total REAL time to Xst completion: 123.00 secs -Total CPU time to Xst completion: 122.59 secs +Total REAL time to Xst completion: 126.00 secs +Total CPU time to Xst completion: 126.49 secs --> -Total memory usage is 338676 kilobytes +Total memory usage is 371060 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 998 ( 0 filtered) -Number of infos : 144 ( 0 filtered) +Number of warnings : 1003 ( 0 filtered) +Number of infos : 126 ( 0 filtered) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr index 5f3c4a2..2c3a3e4 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.twr +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.twr @@ -28,95 +28,95 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on ================================================================================ Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%; - 3548 paths analyzed, 640 endpoints analyzed, 0 failing endpoints + 3447 paths analyzed, 643 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.594ns. + Minimum period is 8.208ns. -------------------------------------------------------------------------------- -Slack: 35.794ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF) +Slack: 35.896ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 (FF) Requirement: 40.000ns - Data Path Delay: 4.039ns (Levels of Logic = 0) - Clock Path Skew: -0.167ns (2.638 - 2.805) + Data Path Delay: 4.041ns (Levels of Logic = 0) + Clock Path Skew: -0.063ns (2.774 - 2.837) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X15Y74.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 - SLICE_X54Y45.BY net (fanout=13) 3.473 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> - SLICE_X54Y45.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15> - inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 + SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 + SLICE_X17Y86.BY net (fanout=14) 3.442 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X17Y86.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_2_11 ------------------------------------------------- --------------------------- - Total 4.039ns (0.566ns logic, 3.473ns route) - (14.0% logic, 86.0% route) + Total 4.041ns (0.599ns logic, 3.442ns route) + (14.8% logic, 85.2% route) -------------------------------------------------------------------------------- -Slack: 35.912ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 (FF) +Slack: 36.344ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 (FF) Requirement: 40.000ns - Data Path Delay: 3.938ns (Levels of Logic = 0) - Clock Path Skew: -0.150ns (2.642 - 2.792) + Data Path Delay: 3.616ns (Levels of Logic = 0) + Clock Path Skew: -0.040ns (2.797 - 2.837) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X12Y74.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<14> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_14 - SLICE_X54Y43.BY net (fanout=13) 3.351 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<14> - SLICE_X54Y43.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<14> - inst_ac97_wb/inst_ac_io/inst_ac_in/tag_14 + SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 + SLICE_X15Y82.BY net (fanout=14) 3.017 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X15Y82.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_3_11 ------------------------------------------------- --------------------------- - Total 3.938ns (0.587ns logic, 3.351ns route) - (14.9% logic, 85.1% route) + Total 3.616ns (0.599ns logic, 3.017ns route) + (16.6% logic, 83.4% route) -------------------------------------------------------------------------------- -Slack: 36.239ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 (FF) - Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 (FF) +Slack: 36.860ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 (FF) Requirement: 40.000ns - Data Path Delay: 3.656ns (Levels of Logic = 0) - Clock Path Skew: -0.105ns (2.645 - 2.750) + Data Path Delay: 3.100ns (Levels of Logic = 0) + Clock Path Skew: -0.040ns (2.797 - 2.837) Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns Clock Uncertainty: 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X18Y78.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<13> - inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_13 - SLICE_X54Y41.BY net (fanout=13) 3.069 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<13> - SLICE_X54Y41.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<13> - inst_ac97_wb/inst_ac_io/inst_ac_in/tag_13 + SLICE_X10Y115.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 + SLICE_X14Y82.BY net (fanout=14) 2.513 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X14Y82.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_12_11 ------------------------------------------------- --------------------------- - Total 3.656ns (0.587ns logic, 3.069ns route) - (16.1% logic, 83.9% route) + Total 3.100ns (0.587ns logic, 2.513ns route) + (18.9% logic, 81.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%; - 455768 paths analyzed, 11147 endpoints analyzed, 0 failing endpoints + 450917 paths analyzed, 11152 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.880ns. + Minimum period is 9.734ns. -------------------------------------------------------------------------------- -Slack: 0.020ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full (FF) +Slack: 0.166ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/s_FSM_FFd6 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 (FF) Requirement: 9.900ns - Data Path Delay: 9.771ns (Levels of Logic = 7) + Data Path Delay: 9.625ns (Levels of Logic = 9) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -128,46 +128,53 @@ Slack: 0.020ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full + Maximum Data Path: inst_vga_frontend/s_FSM_FFd6 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - RAMB16_X3Y13.DOB19 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r/Mram_RAM - SLICE_X28Y112.F1 net (fanout=3) 1.559 inst_sdram_ctrl_frontend_wb/cat_fifo_dout<19> - SLICE_X28Y112.COUT Topcyf 0.576 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_lut<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> - SLICE_X28Y113.CIN net (fanout=1) 0.000 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<5> - SLICE_X28Y113.XB Tcinxb 0.399 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> - SLICE_X21Y134.F4 net (fanout=8) 1.528 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/Mcompar_st_ctrl_cmp_ne0000_cy<6> - SLICE_X21Y134.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/winc74 - SLICE_X19Y154.G1 net (fanout=11) 1.273 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/winc - SLICE_X19Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<3> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<4>1 - SLICE_X19Y156.G1 net (fanout=2) 0.566 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/bnxt<4> - SLICE_X19Y156.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtg<4>1 - SLICE_X19Y156.F3 net (fanout=1) 0.222 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_w<4> - SLICE_X19Y156.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6104 - SLICE_X18Y158.F1 net (fanout=1) 0.557 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6104 - SLICE_X18Y158.CLK Tfck 0.215 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_full6107 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/full + SLICE_X43Y67.XQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd6 + inst_vga_frontend/s_FSM_FFd6 + SLICE_X46Y81.F4 net (fanout=10) 1.470 inst_vga_frontend/s_FSM_FFd6 + SLICE_X46Y81.X Tilo 0.195 N379 + inst_vga_frontend/inst_blitfifo/mem_wr_en1_SW0 + SLICE_X54Y96.F1 net (fanout=1) 1.438 N379 + SLICE_X54Y96.X Tilo 0.195 inst_ps2_wb_1/ACK_O + inst_vga_frontend/inst_blitfifo/mem_wr_en1 + SLICE_X59Y126.G4 net (fanout=20) 1.112 inst_vga_frontend/read_cnt_and0000 + SLICE_X59Y126.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/cntb<0> + inst_vga_frontend/inst_linefifo/mem_wr_en1 + SLICE_X58Y128.G3 net (fanout=41) 0.492 inst_vga_frontend/inst_linefifo/mem_wr_en + SLICE_X58Y128.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<0>_FRB + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<1>1 + SLICE_X59Y131.G2 net (fanout=3) 0.513 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<1> + SLICE_X59Y131.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<5>_FRB + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X59Y132.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X59Y132.XMUX Tcinx 0.438 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<6>_FRB + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> + SLICE_X60Y131.F1 net (fanout=2) 0.785 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> + SLICE_X60Y131.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<4>_FRB + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X60Y132.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X60Y132.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5_BRB2 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<4> + SLICE_X63Y132.G3 net (fanout=1) 0.457 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<4> + SLICE_X63Y132.CLK Tgck 0.231 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<4>1 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_4 ------------------------------------------------- --------------------------- - Total 9.771ns (4.066ns logic, 5.705ns route) - (41.6% logic, 58.4% route) + Total 9.625ns (3.358ns logic, 6.267ns route) + (34.9% logic, 65.1% route) -------------------------------------------------------------------------------- -Slack: 0.134ns (requirement - (data path - clock path skew + uncertainty)) +Slack: 0.169ns (requirement - (data path - clock path skew + uncertainty)) Source: inst_vga_frontend/s_FSM_FFd5 (FF) - Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F (RAM) + Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 (FF) Requirement: 9.900ns - Data Path Delay: 9.657ns (Levels of Logic = 7) + Data Path Delay: 9.622ns (Levels of Logic = 12) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns @@ -179,45 +186,62 @@ Slack: 0.134ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F + Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X45Y73.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 + SLICE_X43Y73.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 inst_vga_frontend/s_FSM_FFd5 - SLICE_X44Y73.F4 net (fanout=50) 0.422 inst_vga_frontend/s_FSM_FFd5 - SLICE_X44Y73.X Tilo 0.195 inst_ac97_wb/int_en_tx + SLICE_X43Y72.G3 net (fanout=49) 0.433 inst_vga_frontend/s_FSM_FFd5 + SLICE_X43Y72.Y Tilo 0.194 inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pW<0> inst_vga_frontend/s_FSM_Out61 - SLICE_X37Y67.G4 net (fanout=1) 0.986 inst_vga_frontend/CYC_O_blit_src - SLICE_X37Y67.Y Tilo 0.194 CYC_O + SLICE_X38Y65.G4 net (fanout=4) 1.002 inst_vga_frontend/CYC_O_blit_src + SLICE_X38Y65.Y Tilo 0.195 CYC_O inst_vga_frontend/CYC_O1 - SLICE_X37Y67.F4 net (fanout=7) 0.186 CYC_O_vga - SLICE_X37Y67.X Tilo 0.194 CYC_O + SLICE_X38Y65.F3 net (fanout=8) 0.236 CYC_O_vga + SLICE_X38Y65.X Tilo 0.195 CYC_O CYC_O1 - SLICE_X37Y68.G4 net (fanout=6) 0.380 CYC_O - SLICE_X37Y68.Y Tilo 0.194 N71 - CYC_I_rom - SLICE_X37Y129.F1 net (fanout=40) 2.228 CYC_I_rom - SLICE_X37Y129.X Tilo 0.194 inst_ps2_wb_1/reg_ps2_tx<1> - MDAT_I<28>23_SW0 - SLICE_X36Y80.G4 net (fanout=1) 1.130 N821 - SLICE_X36Y80.XMUX Tif5x 0.560 MDAT_I<28> - MDAT_I<28>752 - MDAT_I<28>75_f5 - SLICE_X36Y40.BY net (fanout=1) 1.392 MDAT_I<28> - SLICE_X36Y40.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<28> - inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F + SLICE_X39Y64.F1 net (fanout=6) 0.670 CYC_O + SLICE_X39Y64.X Tilo 0.194 N701 + SRDY_I16_SW0 + SLICE_X39Y65.G2 net (fanout=2) 0.503 N701 + SLICE_X39Y65.Y Tilo 0.194 SRDY_I_cpu + SRDY_I26_SW1 + SLICE_X39Y65.F4 net (fanout=1) 0.159 SRDY_I26_SW1/O + SLICE_X39Y65.X Tilo 0.194 SRDY_I_cpu + SRDY_I_cpu1 + SLICE_X39Y51.G4 net (fanout=2) 0.578 SRDY_I_cpu + SLICE_X39Y51.Y Tilo 0.194 ADDR_O_cpu<4> + inst_mips_top/inst_biu/bout_fifo_re1 + SLICE_X37Y52.G4 net (fanout=4) 0.386 inst_mips_top/inst_biu/bout_fifo_re + SLICE_X37Y52.Y Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<3> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>_bdd0 + SLICE_X37Y53.G4 net (fanout=2) 0.331 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>_bdd0 + SLICE_X37Y53.Y Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<4> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bnxt<4>11 + SLICE_X37Y53.F4 net (fanout=1) 0.159 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/bnxt_r<4> + SLICE_X37Y53.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<4> + inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en41 + SLICE_X39Y50.BX net (fanout=1) 0.336 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en_bdd4 + SLICE_X39Y50.XMUX Tbxx 0.511 ADDR_O_cpu<11> + inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en21_f5 + SLICE_X39Y48.F4 net (fanout=2) 0.403 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en_bdd0 + SLICE_X39Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<0> + inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en11 + SLICE_X38Y33.CE net (fanout=38) 0.885 inst_mips_top/inst_biu/inst_bout_fifo/mem_rd_en + SLICE_X38Y33.CLK Tceck 0.554 MDAT_O_cpu<10> + inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/dout_b_42 ------------------------------------------------- --------------------------- - Total 9.657ns (2.933ns logic, 6.724ns route) - (30.4% logic, 69.6% route) + Total 9.622ns (3.541ns logic, 6.081ns route) + (36.8% logic, 63.2% route) -------------------------------------------------------------------------------- -Slack: 0.148ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/s_FSM_FFd2 (FF) - Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F (RAM) +Slack: 0.173ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty (FF) + Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 (FF) Requirement: 9.900ns - Data Path Delay: 9.643ns (Levels of Logic = 7) - Clock Path Skew: 0.000ns + Data Path Delay: 9.458ns (Levels of Logic = 8) + Clock Path Skew: -0.160ns (2.487 - 2.647) Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 9.900ns Clock Uncertainty: 0.109ns @@ -228,55 +252,60 @@ Slack: 0.148ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/s_FSM_FFd2 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F + Maximum Data Path: inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X45Y72.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd2 - inst_vga_frontend/s_FSM_FFd2 - SLICE_X44Y73.F3 net (fanout=39) 0.408 inst_vga_frontend/s_FSM_FFd2 - SLICE_X44Y73.X Tilo 0.195 inst_ac97_wb/int_en_tx - inst_vga_frontend/s_FSM_Out61 - SLICE_X37Y67.G4 net (fanout=1) 0.986 inst_vga_frontend/CYC_O_blit_src - SLICE_X37Y67.Y Tilo 0.194 CYC_O - inst_vga_frontend/CYC_O1 - SLICE_X37Y67.F4 net (fanout=7) 0.186 CYC_O_vga - SLICE_X37Y67.X Tilo 0.194 CYC_O - CYC_O1 - SLICE_X37Y68.G4 net (fanout=6) 0.380 CYC_O - SLICE_X37Y68.Y Tilo 0.194 N71 - CYC_I_rom - SLICE_X37Y129.F1 net (fanout=40) 2.228 CYC_I_rom - SLICE_X37Y129.X Tilo 0.194 inst_ps2_wb_1/reg_ps2_tx<1> - MDAT_I<28>23_SW0 - SLICE_X36Y80.G4 net (fanout=1) 1.130 N821 - SLICE_X36Y80.XMUX Tif5x 0.560 MDAT_I<28> - MDAT_I<28>752 - MDAT_I<28>75_f5 - SLICE_X36Y40.BY net (fanout=1) 1.392 MDAT_I<28> - SLICE_X36Y40.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<28> - inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM29.SLICEM_F + SLICE_X39Y53.YQ Tcko 0.340 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<2> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/empty + SLICE_X39Y52.G4 net (fanout=7) 0.398 inst_mips_top/inst_biu/bout_fifo_empty + SLICE_X39Y52.Y Tilo 0.194 ADDR_O_cpu<30> + inst_mips_top/inst_biu/CYC_O1 + SLICE_X38Y63.F3 net (fanout=7) 0.805 CYC_O_cpu + SLICE_X38Y63.X Tilo 0.195 N113 + CYC_O1_SW2 + SLICE_X36Y62.G1 net (fanout=2) 1.238 N113 + SLICE_X36Y62.Y Tilo 0.195 N104 + CYC_I_flash_1 + SLICE_X39Y71.G2 net (fanout=41) 0.992 CYC_I_flash + SLICE_X39Y71.Y Tilo 0.194 N843 + SRDY_I26 + SLICE_X39Y84.G4 net (fanout=1) 0.726 SRDY_I26 + SLICE_X39Y84.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pR<0> + SRDY_I36 + SLICE_X39Y92.G3 net (fanout=3) 0.604 SRDY_I + SLICE_X39Y92.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pR<1> + inst_vga_frontend/inst_bus_fifo/rinc1 + SLICE_X39Y93.G2 net (fanout=5) 0.358 inst_vga_frontend/inst_bus_fifo/rinc + SLICE_X39Y93.Y Tilo 0.194 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pW<0> + inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 + SLICE_X38Y92.F1 net (fanout=2) 0.396 N405 + SLICE_X38Y92.X Tilo 0.195 inst_vga_frontend/inst_bus_fifo/mem_rd_en + inst_vga_frontend/inst_bus_fifo/mem_rd_en1 + SLICE_X40Y69.CE net (fanout=103) 1.492 inst_vga_frontend/inst_bus_fifo/mem_rd_en + SLICE_X40Y69.CLK Tceck 0.554 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b<12> + inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_12 ------------------------------------------------- --------------------------- - Total 9.643ns (2.933ns logic, 6.710ns route) - (30.4% logic, 69.6% route) + Total 9.458ns (2.449ns logic, 7.009ns route) + (25.9% logic, 74.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%; - 1810 paths analyzed, 439 endpoints analyzed, 0 failing endpoints + 1524 paths analyzed, 435 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.348ns. + Minimum period is 7.392ns. -------------------------------------------------------------------------------- -Slack: 0.152ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Requirement: 7.500ns - Data Path Delay: 7.224ns (Levels of Logic = 6) +Slack: 0.054ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 (FF) + Requirement: 3.750ns + Data Path Delay: 3.572ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 rising at 7.500ns + Destination Clock: sdram_clk0 falling at 3.750ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -285,46 +314,31 @@ Slack: 0.152ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - RAMB16_X0Y16.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - SLICE_X7Y135.G1 net (fanout=15) 0.708 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26> - SLICE_X7Y135.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0 - SLICE_X6Y138.G2 net (fanout=7) 0.548 N314 - SLICE_X6Y138.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc - SLICE_X6Y138.F4 net (fanout=7) 0.184 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc - SLICE_X6Y138.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<1>1 - SLICE_X6Y141.F1 net (fanout=2) 0.605 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/ptr_r<1> - SLICE_X6Y141.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<1>1 - SLICE_X6Y140.F3 net (fanout=1) 0.213 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<1> - SLICE_X6Y140.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<3> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en31_SW0 - SLICE_X7Y136.G2 net (fanout=2) 0.531 N694 - SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X6Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X0Y167.G1 net (fanout=9) 1.296 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X0Y167.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_8_mux00041 + OLOGIC_X0Y185.D1 net (fanout=1) 1.094 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 + OLOGIC_X0Y185.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<8> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_8 ------------------------------------------------- --------------------------- - Total 7.224ns (3.786ns logic, 3.438ns route) - (52.4% logic, 47.6% route) + Total 3.572ns (1.182ns logic, 2.390ns route) + (33.1% logic, 66.9% route) -------------------------------------------------------------------------------- -Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Requirement: 7.500ns - Data Path Delay: 7.212ns (Levels of Logic = 5) +Slack: 0.248ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 (FF) + Requirement: 3.750ns + Data Path Delay: 3.378ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 rising at 7.500ns + Destination Clock: sdram_clk0 falling at 3.750ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -333,43 +347,31 @@ Slack: 0.164ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - RAMB16_X0Y16.DOB24 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - SLICE_X6Y134.F3 net (fanout=16) 0.719 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<24> - SLICE_X6Y134.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cmd_ack21 - SLICE_X6Y136.G1 net (fanout=3) 0.583 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 - SLICE_X6Y136.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<5> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>_SW0 - SLICE_X6Y142.F1 net (fanout=2) 0.763 N395 - SLICE_X6Y142.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 - SLICE_X7Y138.G4 net (fanout=2) 0.511 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<4> - SLICE_X7Y138.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3> - _LC_0_0 - SLICE_X7Y136.G3 net (fanout=1) 0.396 _LC_0_0 - SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X6Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X2Y164.F3 net (fanout=9) 1.090 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X2Y164.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB0 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_6_mux00041 + OLOGIC_X0Y188.D1 net (fanout=1) 1.106 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 + OLOGIC_X0Y188.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<6> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 ------------------------------------------------- --------------------------- - Total 7.212ns (3.591ns logic, 3.621ns route) - (49.8% logic, 50.2% route) + Total 3.378ns (1.182ns logic, 2.196ns route) + (35.0% logic, 65.0% route) -------------------------------------------------------------------------------- -Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM) - Requirement: 7.500ns - Data Path Delay: 7.212ns (Levels of Logic = 6) +Slack: 0.275ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 (FF) + Requirement: 3.750ns + Data Path Delay: 3.351ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: sdram_clk0 rising at 0.000ns - Destination Clock: sdram_clk0 rising at 7.500ns + Destination Clock: sdram_clk0 falling at 3.750ns Clock Uncertainty: 0.124ns Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -378,36 +380,21 @@ Slack: 0.164ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - RAMB16_X0Y16.DOB24 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - SLICE_X6Y134.F3 net (fanout=16) 0.719 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<24> - SLICE_X6Y134.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cmd_ack21 - SLICE_X6Y138.G4 net (fanout=3) 0.524 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N111 - SLICE_X6Y138.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc - SLICE_X6Y138.F4 net (fanout=7) 0.184 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/rinc - SLICE_X6Y138.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<1>1 - SLICE_X6Y141.F1 net (fanout=2) 0.605 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/ptr_r<1> - SLICE_X6Y141.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<1> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<1>1 - SLICE_X6Y140.F3 net (fanout=1) 0.213 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<1> - SLICE_X6Y140.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<3> - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en31_SW0 - SLICE_X7Y136.G2 net (fanout=2) 0.531 N694 - SLICE_X7Y136.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en_bdd0 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.ENB net (fanout=1) 0.649 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/mem_rd_en - RAMB16_X0Y16.CLKB Trcck_ENB 0.518 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM + SLICE_X2Y162.XQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 + SLICE_X3Y154.G1 net (fanout=9) 1.248 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 + SLICE_X3Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB2 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_3_mux00041 + OLOGIC_X0Y179.D1 net (fanout=1) 0.922 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3 + OLOGIC_X0Y179.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<3> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_3 ------------------------------------------------- --------------------------- - Total 7.212ns (3.787ns logic, 3.425ns route) - (52.5% logic, 47.5% route) + Total 3.351ns (1.181ns logic, 2.170ns route) + (35.2% logic, 64.8% route) -------------------------------------------------------------------------------- @@ -417,44 +404,11 @@ Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG; 24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 9.779ns (data path - clock path skew + uncertainty) - Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) - Data Path Delay: 3.255ns (Levels of Logic = 2) - Clock Path Skew: -6.280ns (-2.404 - 3.876) - Source Clock: CLK_O rising - Destination Clock: sdram_clk0 rising - Clock Uncertainty: 0.244ns - - Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.248ns - Phase Error (PE): 0.120ns - - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X13Y175.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X6Y154.F2 net (fanout=20) 1.559 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X6Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X9Y154.F2 net (fanout=1) 0.926 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X9Y154.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 - ------------------------------------------------- --------------------------- - Total 3.255ns (0.770ns logic, 2.485ns route) - (23.7% logic, 76.3% route) - --------------------------------------------------------------------------------- -Delay: 9.603ns (data path - clock path skew + uncertainty) +Delay: 9.588ns (data path - clock path skew + uncertainty) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) - Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) - Data Path Delay: 3.061ns (Levels of Logic = 2) - Clock Path Skew: -6.298ns (-2.404 - 3.894) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) + Data Path Delay: 3.045ns (Levels of Logic = 1) + Clock Path Skew: -6.299ns (-2.395 - 3.904) Source Clock: CLK_O rising Destination Clock: sdram_clk0 rising Clock Uncertainty: 0.244ns @@ -465,29 +419,28 @@ Delay: 9.603ns (data path - clock path skew + uncertainty) Discrete Jitter (DJ): 0.248ns Phase Error (PE): 0.120ns - Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X12Y160.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X13Y172.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X6Y154.F1 net (fanout=9) 1.345 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 - SLICE_X6Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X9Y154.F2 net (fanout=1) 0.926 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 - SLICE_X9Y154.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 - inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + SLICE_X5Y154.G3 net (fanout=9) 1.527 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X5Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 + SLICE_X4Y155.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X4Y155.CLK Tceck 0.554 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 ------------------------------------------------- --------------------------- - Total 3.061ns (0.790ns logic, 2.271ns route) - (25.8% logic, 74.2% route) + Total 3.045ns (1.088ns logic, 1.957ns route) + (35.7% logic, 64.3% route) -------------------------------------------------------------------------------- -Delay: 9.343ns (data path - clock path skew + uncertainty) +Delay: 9.568ns (data path - clock path skew + uncertainty) Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) - Data Path Delay: 2.824ns (Levels of Logic = 1) - Clock Path Skew: -6.275ns (-2.399 - 3.876) + Data Path Delay: 3.049ns (Levels of Logic = 1) + Clock Path Skew: -6.275ns (-2.395 - 3.880) Source Clock: CLK_O rising Destination Clock: sdram_clk0 rising Clock Uncertainty: 0.244ns @@ -502,33 +455,66 @@ Delay: 9.343ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X13Y175.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X11Y185.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X5Y155.G3 net (fanout=20) 1.461 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 - SLICE_X5Y155.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + SLICE_X5Y154.G2 net (fanout=20) 1.531 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X5Y154.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 - SLICE_X4Y155.CE net (fanout=1) 0.275 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X4Y155.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke SLICE_X4Y155.CLK Tceck 0.554 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 ------------------------------------------------- --------------------------- - Total 2.824ns (1.088ns logic, 1.736ns route) - (38.5% logic, 61.5% route) + Total 3.049ns (1.088ns logic, 1.961ns route) + (35.7% logic, 64.3% route) + +-------------------------------------------------------------------------------- +Delay: 9.480ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) + Data Path Delay: 2.940ns (Levels of Logic = 2) + Clock Path Skew: -6.296ns (-2.392 - 3.904) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X13Y172.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X8Y162.F3 net (fanout=9) 1.362 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X8Y162.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X7Y162.F1 net (fanout=1) 0.808 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X7Y162.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + ------------------------------------------------- --------------------------- + Total 2.940ns (0.770ns logic, 2.170ns route) + (26.2% logic, 73.8% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%; - 14750 paths analyzed, 701 endpoints analyzed, 0 failing endpoints + 12615 paths analyzed, 692 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 7.923ns. + Minimum period is 7.891ns. -------------------------------------------------------------------------------- -Slack: 0.077ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) +Slack: 0.109ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_char_gen/char_draw_en (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_red_0 (FF) Requirement: 8.000ns - Data Path Delay: 7.550ns (Levels of Logic = 6) - Clock Path Skew: -0.238ns (0.902 - 1.140) + Data Path Delay: 7.756ns (Levels of Logic = 2) + Clock Path Skew: 0.000ns Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -539,49 +525,32 @@ Slack: 0.077ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + Maximum Data Path: inst_vga_frontend/inst_char_gen/char_draw_en to inst_vga_frontend/inst_vga_backend/vga_red_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X65Y138.XQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_2 - SLICE_X64Y139.F1 net (fanout=3) 0.581 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> - SLICE_X64Y139.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2>_rt - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> - SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> - SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 - SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> - SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 - SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> - SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + SLICE_X62Y105.YQ Tcko 0.360 inst_vga_frontend/inst_char_gen/char_draw_en + inst_vga_frontend/inst_char_gen/char_draw_en + SLICE_X64Y129.G3 net (fanout=25) 1.143 inst_vga_frontend/inst_char_gen/char_draw_en + SLICE_X64Y129.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>13 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<0>11 + SLICE_X44Y98.F1 net (fanout=24) 3.269 inst_vga_frontend/inst_vga_backend/N6 + SLICE_X44Y98.X Tilo 0.195 inst_vga_frontend/blit_dimx_src_1<25> + inst_vga_frontend/inst_vga_backend/vga_red_mux0003<0>13 + OLOGIC_X0Y97.D1 net (fanout=1) 1.967 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<0>13 + OLOGIC_X0Y97.CLK Todck 0.627 inst_vga_frontend/inst_vga_backend/vga_red<0> + inst_vga_frontend/inst_vga_backend/vga_red_0 ------------------------------------------------- --------------------------- - Total 7.550ns (2.916ns logic, 4.634ns route) - (38.6% logic, 61.4% route) + Total 7.756ns (1.377ns logic, 6.379ns route) + (17.8% logic, 82.2% route) -------------------------------------------------------------------------------- -Slack: 0.105ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) +Slack: 0.141ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_char_gen/char_draw_en (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_red_2 (FF) Requirement: 8.000ns - Data Path Delay: 7.518ns (Levels of Logic = 7) - Clock Path Skew: -0.242ns (0.902 - 1.144) + Data Path Delay: 7.724ns (Levels of Logic = 2) + Clock Path Skew: 0.000ns Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -592,53 +561,32 @@ Slack: 0.105ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + Maximum Data Path: inst_vga_frontend/inst_char_gen/char_draw_en to inst_vga_frontend/inst_vga_backend/vga_red_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X65Y136.XQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_0 - SLICE_X64Y138.F3 net (fanout=3) 0.460 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> - SLICE_X64Y138.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_lut<0>_INV_0 - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<0> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - SLICE_X64Y139.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> - SLICE_X64Y139.COUT Tbyp 0.089 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> - SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> - SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 - SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> - SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 - SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> - SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + SLICE_X62Y105.YQ Tcko 0.360 inst_vga_frontend/inst_char_gen/char_draw_en + inst_vga_frontend/inst_char_gen/char_draw_en + SLICE_X64Y129.G3 net (fanout=25) 1.143 inst_vga_frontend/inst_char_gen/char_draw_en + SLICE_X64Y129.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>13 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<0>11 + SLICE_X39Y99.G4 net (fanout=24) 3.281 inst_vga_frontend/inst_vga_backend/N6 + SLICE_X39Y99.Y Tilo 0.194 MDAT_O<44> + inst_vga_frontend/inst_vga_backend/vga_red_mux0003<2>13 + OLOGIC_X0Y99.D1 net (fanout=1) 1.924 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<2>13 + OLOGIC_X0Y99.CLK Todck 0.627 inst_vga_frontend/inst_vga_backend/vga_red<2> + inst_vga_frontend/inst_vga_backend/vga_red_2 ------------------------------------------------- --------------------------- - Total 7.518ns (3.005ns logic, 4.513ns route) - (40.0% logic, 60.0% route) + Total 7.724ns (1.376ns logic, 6.348ns route) + (17.8% logic, 82.2% route) -------------------------------------------------------------------------------- -Slack: 0.107ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 (FF) - Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 (RAM) +Slack: 0.199ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_2 (FF) Requirement: 8.000ns - Data Path Delay: 7.520ns (Levels of Logic = 6) - Clock Path Skew: -0.238ns (0.902 - 1.140) + Data Path Delay: 7.666ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns Source Clock: vga_clk rising at 0.000ns Destination Clock: vga_clk rising at 8.000ns Clock Uncertainty: 0.135ns @@ -649,40 +597,21 @@ Slack: 0.107ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.270ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 to inst_vga_frontend/inst_vga_backend/vga_blue_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X65Y138.YQ Tcko 0.340 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_3 - SLICE_X64Y139.G2 net (fanout=3) 0.566 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3> - SLICE_X64Y139.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<3>_rt - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> - SLICE_X64Y140.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<4> - SLICE_X65Y143.F1 net (fanout=1) 1.040 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<4> - SLICE_X65Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<4>1 - SLICE_X67Y138.F2 net (fanout=10) 0.725 inst_vga_frontend/inst_linefifo/ptr_r<4> - SLICE_X67Y138.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<4>1 - SLICE_X61Y139.F3 net (fanout=1) 0.815 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<4> - SLICE_X61Y139.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> - SLICE_X61Y140.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> - inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> - RAMB16_X4Y16.ENB net (fanout=8) 1.473 inst_vga_frontend/inst_linefifo/pre_empty - RAMB16_X4Y16.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 - inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM6 + SLICE_X73Y112.XQ Tcko 0.340 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + SLICE_X56Y131.G2 net (fanout=8) 1.941 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + SLICE_X56Y131.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/stat_scan_inv + inst_vga_frontend/inst_vga_backend/stat_scan_inv1 + OLOGIC_X0Y105.SR net (fanout=24) 3.893 inst_vga_frontend/inst_vga_backend/stat_scan_inv + OLOGIC_X0Y105.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<2> + inst_vga_frontend/inst_vga_backend/vga_blue_2 ------------------------------------------------- --------------------------- - Total 7.520ns (2.901ns logic, 4.619ns route) - (38.6% logic, 61.4% route) + Total 7.666ns (1.832ns logic, 5.834ns route) + (23.9% logic, 76.1% route) -------------------------------------------------------------------------------- @@ -692,10 +621,10 @@ Timing constraint: PATH "TS_unrelate_VGA_path" TIG; 64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) -------------------------------------------------------------------------------- -Delay: 6.002ns (data path - clock path skew + uncertainty) +Delay: 6.296ns (data path - clock path skew + uncertainty) Source: inst_vga_frontend/cg_color_2_6 (FF) Destination: inst_vga_frontend/inst_vga_backend/vga_blue_6 (FF) - Data Path Delay: 5.461ns (Levels of Logic = 1) + Data Path Delay: 5.755ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -711,55 +640,23 @@ Delay: 6.002ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X50Y118.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_6 + SLICE_X48Y110.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_6 inst_vga_frontend/cg_color_2_6 - SLICE_X67Y150.G4 net (fanout=2) 1.983 inst_vga_frontend/cg_color_2_6 - SLICE_X67Y150.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + SLICE_X67Y140.G1 net (fanout=2) 2.063 inst_vga_frontend/cg_color_2_6 + SLICE_X67Y140.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 - OLOGIC_X2Y172.REV net (fanout=1) 1.627 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + OLOGIC_X2Y172.REV net (fanout=1) 1.841 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 OLOGIC_X2Y172.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<6> inst_vga_frontend/inst_vga_backend/vga_blue_6 ------------------------------------------------- --------------------------- - Total 5.461ns (1.851ns logic, 3.610ns route) - (33.9% logic, 66.1% route) + Total 5.755ns (1.851ns logic, 3.904ns route) + (32.2% logic, 67.8% route) -------------------------------------------------------------------------------- -Delay: 5.938ns (data path - clock path skew + uncertainty) - Source: inst_vga_frontend/cg_color_1_5 (FF) - Destination: inst_vga_frontend/inst_vga_backend/vga_green_5 (FF) - Data Path Delay: 5.397ns (Levels of Logic = 1) - Clock Path Skew: 0.000ns - Source Clock: CLK_O rising - Destination Clock: vga_clk rising - Clock Uncertainty: 0.541ns - - Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.347ns - Phase Error (PE): 0.367ns - - Maximum Data Path: inst_vga_frontend/cg_color_1_5 to inst_vga_frontend/inst_vga_backend/vga_green_5 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X49Y106.YQ Tcko 0.340 inst_vga_frontend/cg_color_1_5 - inst_vga_frontend/cg_color_1_5 - SLICE_X69Y134.G1 net (fanout=2) 2.365 inst_vga_frontend/cg_color_1_5 - SLICE_X69Y134.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 - inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 - OLOGIC_X2Y150.REV net (fanout=1) 1.201 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<5>0 - OLOGIC_X2Y150.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_green<5> - inst_vga_frontend/inst_vga_backend/vga_green_5 - ------------------------------------------------- --------------------------- - Total 5.397ns (1.831ns logic, 3.566ns route) - (33.9% logic, 66.1% route) - --------------------------------------------------------------------------------- -Delay: 5.936ns (data path - clock path skew + uncertainty) +Delay: 6.118ns (data path - clock path skew + uncertainty) Source: inst_vga_frontend/cg_color_2_5 (FF) Destination: inst_vga_frontend/inst_vga_backend/vga_blue_5 (FF) - Data Path Delay: 5.395ns (Levels of Logic = 1) + Data Path Delay: 5.577ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: CLK_O rising Destination Clock: vga_clk rising @@ -775,35 +672,67 @@ Delay: 5.936ns (data path - clock path skew + uncertainty) Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X52Y117.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_5 + SLICE_X52Y110.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_5 inst_vga_frontend/cg_color_2_5 - SLICE_X68Y150.F1 net (fanout=2) 2.252 inst_vga_frontend/cg_color_2_5 - SLICE_X68Y150.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bcnt2_ar<4> + SLICE_X67Y150.F3 net (fanout=2) 2.105 inst_vga_frontend/cg_color_2_5 + SLICE_X67Y150.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 - OLOGIC_X2Y171.REV net (fanout=1) 1.291 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + OLOGIC_X2Y171.REV net (fanout=1) 1.621 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 OLOGIC_X2Y171.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<5> inst_vga_frontend/inst_vga_backend/vga_blue_5 ------------------------------------------------- --------------------------- - Total 5.395ns (1.852ns logic, 3.543ns route) - (34.3% logic, 65.7% route) + Total 5.577ns (1.851ns logic, 3.726ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Delay: 5.925ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_2_7 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_7 (FF) + Data Path Delay: 5.384ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising + Destination Clock: vga_clk rising + Clock Uncertainty: 0.541ns + + Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.347ns + Phase Error (PE): 0.367ns + + Maximum Data Path: inst_vga_frontend/cg_color_2_7 to inst_vga_frontend/inst_vga_backend/vga_blue_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X47Y118.YQ Tcko 0.340 inst_vga_frontend/cg_color_2_7 + inst_vga_frontend/cg_color_2_7 + SLICE_X67Y150.G2 net (fanout=2) 2.065 inst_vga_frontend/cg_color_2_7 + SLICE_X67Y150.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<7>0 + OLOGIC_X2Y173.REV net (fanout=1) 1.488 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<7>0 + OLOGIC_X2Y173.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<7> + inst_vga_frontend/inst_vga_backend/vga_blue_7 + ------------------------------------------------- --------------------------- + Total 5.384ns (1.831ns logic, 3.553ns route) + (34.0% logic, 66.0% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%; - 857751 paths analyzed, 11767 endpoints analyzed, 0 failing endpoints + 862302 paths analyzed, 11634 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 9.899ns. + Minimum period is 9.864ns. -------------------------------------------------------------------------------- -Slack: 0.001ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 (RAM) - Destination: inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 (FF) - Requirement: 9.900ns - Data Path Delay: 9.839ns (Levels of Logic = 8) - Clock Path Skew: 0.000ns +Slack: 0.018ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) + Destination: inst_mips_top/inst_pipeline/pc.branch_take_2 (FF) + Requirement: 4.950ns + Data Path Delay: 4.777ns (Levels of Logic = 5) + Clock Path Skew: -0.095ns (1.163 - 1.258) Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns + Destination Clock: cpu_clk falling at 4.950ns Clock Uncertainty: 0.060ns Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -812,51 +741,49 @@ Slack: 0.001ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.120ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 to inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - RAMB16_X2Y0.DOB1 Trcko_DOWB 2.100 inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 - inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram/Mram_RAM1 - SLICE_X16Y7.G3 net (fanout=1) 0.911 inst_mips_top/inst_biu/dcache_dout<17> - SLICE_X16Y7.Y Tilo 0.195 inst_mips_top/inst_cop/test_reg<17> - inst_mips_top/inst_biu/cpu_dmem_din<17>1 - SLICE_X14Y11.F3 net (fanout=4) 0.672 inst_mips_top/dmem_din<17> - SLICE_X14Y11.X Tilo 0.195 inst_mips_top/inst_pipeline/bcu_op_b<4> - inst_mips_top/inst_pipeline/stage10_mux0000<17>1 - SLICE_X21Y11.G2 net (fanout=2) 0.821 inst_mips_top/inst_pipeline/stage10_mux0000<17> - SLICE_X21Y11.Y Tilo 0.194 inst_mips_top/inst_pipeline/WB_stage.data_1 - inst_mips_top/inst_pipeline/data4_1_mux000223 - SLICE_X21Y11.F4 net (fanout=1) 0.159 inst_mips_top/inst_pipeline/data4_1_mux000223/O - SLICE_X21Y11.X Tilo 0.194 inst_mips_top/inst_pipeline/WB_stage.data_1 - inst_mips_top/inst_pipeline/data4_1_mux000227 - SLICE_X17Y8.G1 net (fanout=4) 1.320 inst_mips_top/inst_pipeline/MEM_stage_data<1> - SLICE_X17Y8.XMUX Tif5x 0.574 inst_mips_top/inst_pipeline/EX_stage.reg_a_1 - inst_mips_top/inst_pipeline/ID_stage_reg_a<1>68_F - inst_mips_top/inst_pipeline/ID_stage_reg_a<1>68 - SLICE_X6Y7.G4 net (fanout=3) 0.998 inst_mips_top/inst_pipeline/ID_stage_reg_a<1> - SLICE_X6Y7.Y Tilo 0.195 inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000 - inst_mips_top/inst_pipeline/data3_mux0000<1>1 - SLICE_X6Y8.G4 net (fanout=5) 0.400 inst_mips_top/inst_pipeline/data3_mux0000<1> - SLICE_X6Y8.Y Tilo 0.195 inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 - inst_mips_top/inst_pipeline/Madd_EX_stage.shift_ctrl.shamt_rnd_addsub0000_cy<2>11_SW0 - SLICE_X6Y8.F2 net (fanout=1) 0.501 inst_mips_top/inst_pipeline/Madd_EX_stage.shift_ctrl.shamt_rnd_addsub0000_cy<2>11_SW0/O - SLICE_X6Y8.CLK Tfck 0.215 inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 - inst_mips_top/inst_pipeline/EX_stage_shift_ctrl_shamt_rnd_mux0001<3>1 - inst_mips_top/inst_pipeline/EX_stage.shift_ctrl.shamt_rnd_3 + SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> + inst_mips_top/inst_pipeline/bcu_op_a_16 + SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> + SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> + SLICE_X26Y15.G4 net (fanout=2) 0.789 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X26Y15.XMUX Tif5x 0.560 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux000267_F + inst_mips_top/inst_pipeline/pc_branch_take_mux000267 + SLICE_X29Y14.BY net (fanout=3) 0.658 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X29Y14.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 + inst_mips_top/inst_pipeline/pc.branch_take_2 ------------------------------------------------- --------------------------- - Total 9.839ns (4.057ns logic, 5.782ns route) - (41.2% logic, 58.8% route) + Total 4.777ns (2.093ns logic, 2.684ns route) + (43.8% logic, 56.2% route) -------------------------------------------------------------------------------- -Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 (FF) - Destination: inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 (RAM) - Requirement: 9.900ns - Data Path Delay: 9.556ns (Levels of Logic = 23) - Clock Path Skew: -0.274ns (2.666 - 2.940) +Slack: 0.018ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) + Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF) + Requirement: 4.950ns + Data Path Delay: 4.777ns (Levels of Logic = 5) + Clock Path Skew: -0.095ns (1.163 - 1.258) Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns + Destination Clock: cpu_clk falling at 4.950ns Clock Uncertainty: 0.060ns Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -865,114 +792,49 @@ Slack: 0.010ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.120ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 to inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X17Y13.YQ Tcko 0.340 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - SLICE_X16Y11.F2 net (fanout=12) 0.783 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - SLICE_X16Y11.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X16Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X16Y12.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X16Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X16Y13.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X16Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X16Y14.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<6> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X16Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X16Y15.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X16Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X16Y16.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<0> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X16Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X16Y17.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<6> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X16Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X16Y18.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X16Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X16Y19.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X16Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X16Y20.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X16Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X16Y21.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X16Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X16Y22.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X16Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X16Y23.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X16Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X16Y24.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X16Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X16Y25.COUT Tbyp 0.089 inst_mips_top/inst_biu/inst_dcache/tag_reg<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X16Y26.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X16Y26.YMUX Tciny 0.513 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> - SLICE_X14Y31.F2 net (fanout=4) 0.968 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> - SLICE_X14Y31.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf - inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X13Y32.G4 net (fanout=1) 0.371 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf - SLICE_X13Y32.Y Tilo 0.194 inst_mips_top/RST_I_shift3 - inst_mips_top/inst_pipeline/EX_stage_exc23 - SLICE_X13Y32.F3 net (fanout=17) 0.245 inst_mips_top/inst_pipeline/EX_stage_exc - SLICE_X13Y32.X Tilo 0.194 inst_mips_top/RST_I_shift3 - inst_mips_top/inst_pipeline/sdu_ID_nop - SLICE_X14Y34.G4 net (fanout=15) 0.405 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - SLICE_X14Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/cop_pipe_ID_RFE31 - SLICE_X14Y34.F4 net (fanout=6) 0.169 inst_mips_top/inst_cop/cop_pipe_ID_RFE - SLICE_X14Y34.X Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/ctrl_out_exc_commit11 - SLICE_X16Y34.G2 net (fanout=1) 0.583 inst_mips_top/inst_cop/exc_state_FSM_FFd3-In - SLICE_X16Y34.Y Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req - inst_mips_top/inst_pipeline/imem_en47 - SLICE_X16Y34.F4 net (fanout=2) 0.164 inst_mips_top/imem_en - SLICE_X16Y34.X Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req - inst_mips_top/inst_biu/inst_icache/ram_read_en1 - RAMB16_X3Y6.ENB net (fanout=18) 1.312 inst_mips_top/inst_biu/inst_icache/ram_read_en - RAMB16_X3Y6.CLKB Trcck_ENB 0.518 inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 - inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> + inst_mips_top/inst_pipeline/bcu_op_a_16 + SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> + SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> + SLICE_X26Y15.G4 net (fanout=2) 0.789 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X26Y15.XMUX Tif5x 0.560 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux000267_F + inst_mips_top/inst_pipeline/pc_branch_take_mux000267 + SLICE_X29Y14.BX net (fanout=3) 0.669 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X29Y14.CLK Tdick 0.331 inst_mips_top/inst_pipeline/pc.branch_take_1 + inst_mips_top/inst_pipeline/pc.branch_take_1 ------------------------------------------------- --------------------------- - Total 9.556ns (4.556ns logic, 5.000ns route) - (47.7% logic, 52.3% route) + Total 4.777ns (2.082ns logic, 2.695ns route) + (43.6% logic, 56.4% route) -------------------------------------------------------------------------------- -Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 (FF) - Destination: inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 (RAM) - Requirement: 9.900ns - Data Path Delay: 9.556ns (Levels of Logic = 23) - Clock Path Skew: -0.274ns (2.666 - 2.940) +Slack: 0.036ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/bcu_op_a_16 (FF) + Destination: inst_mips_top/inst_pipeline/pc.branch_take_2 (FF) + Requirement: 4.950ns + Data Path Delay: 4.759ns (Levels of Logic = 5) + Clock Path Skew: -0.095ns (1.163 - 1.258) Source Clock: cpu_clk rising at 0.000ns - Destination Clock: cpu_clk rising at 9.900ns + Destination Clock: cpu_clk falling at 4.950ns Clock Uncertainty: 0.060ns Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -981,104 +843,39 @@ Slack: 0.010ns (requirement - (data path - clock path skew + un Discrete Jitter (DJ): 0.120ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 to inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_16 to inst_mips_top/inst_pipeline/pc.branch_take_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X17Y13.YQ Tcko 0.340 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - SLICE_X16Y11.F2 net (fanout=12) 0.783 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 - SLICE_X16Y11.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X16Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> - SLICE_X16Y12.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<1> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X16Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> - SLICE_X16Y13.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X16Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> - SLICE_X16Y14.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<6> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X16Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> - SLICE_X16Y15.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X16Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> - SLICE_X16Y16.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<0> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X16Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> - SLICE_X16Y17.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<6> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X16Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> - SLICE_X16Y18.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<3> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X16Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> - SLICE_X16Y19.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X16Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> - SLICE_X16Y20.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<9> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X16Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> - SLICE_X16Y21.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X16Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> - SLICE_X16Y22.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X16Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> - SLICE_X16Y23.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X16Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> - SLICE_X16Y24.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X16Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> - SLICE_X16Y25.COUT Tbyp 0.089 inst_mips_top/inst_biu/inst_dcache/tag_reg<5> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X16Y26.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> - SLICE_X16Y26.YMUX Tciny 0.513 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> - inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> - SLICE_X13Y30.F4 net (fanout=4) 0.917 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> - SLICE_X13Y30.X Tilo 0.194 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_ovf - inst_mips_top/inst_pipeline/EX_events_alu_alu_ovf - SLICE_X13Y32.G3 net (fanout=1) 0.423 inst_mips_top/inst_pipeline/EX_events_alu_alu_ovf - SLICE_X13Y32.Y Tilo 0.194 inst_mips_top/RST_I_shift3 - inst_mips_top/inst_pipeline/EX_stage_exc23 - SLICE_X13Y32.F3 net (fanout=17) 0.245 inst_mips_top/inst_pipeline/EX_stage_exc - SLICE_X13Y32.X Tilo 0.194 inst_mips_top/RST_I_shift3 - inst_mips_top/inst_pipeline/sdu_ID_nop - SLICE_X14Y34.G4 net (fanout=15) 0.405 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop - SLICE_X14Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/cop_pipe_ID_RFE31 - SLICE_X14Y34.F4 net (fanout=6) 0.169 inst_mips_top/inst_cop/cop_pipe_ID_RFE - SLICE_X14Y34.X Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 - inst_mips_top/inst_cop/ctrl_out_exc_commit11 - SLICE_X16Y34.G2 net (fanout=1) 0.583 inst_mips_top/inst_cop/exc_state_FSM_FFd3-In - SLICE_X16Y34.Y Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req - inst_mips_top/inst_pipeline/imem_en47 - SLICE_X16Y34.F4 net (fanout=2) 0.164 inst_mips_top/imem_en - SLICE_X16Y34.X Tilo 0.195 inst_mips_top/inst_biu/inst_icache/cache_req - inst_mips_top/inst_biu/inst_icache/ram_read_en1 - RAMB16_X3Y6.ENB net (fanout=18) 1.312 inst_mips_top/inst_biu/inst_icache/ram_read_en - RAMB16_X3Y6.CLKB Trcck_ENB 0.518 inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 - inst_mips_top/inst_biu/inst_icache/inst_data_ram/Mram_RAM7 + SLICE_X22Y19.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<16> + inst_mips_top/inst_pipeline/bcu_op_a_16 + SLICE_X23Y13.F3 net (fanout=1) 1.237 inst_mips_top/inst_pipeline/bcu_op_a<16> + SLICE_X23Y13.COUT Topcyf 0.573 inst_mips_top/inst_pipeline/EX_stage.reg_a_17 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9> + SLICE_X23Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11> + SLICE_X23Y15.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/fill_addr<8> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13> + SLICE_X23Y16.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_19 + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14> + inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15> + SLICE_X26Y15.F4 net (fanout=2) 0.776 inst_mips_top/inst_pipeline/bcu_flags_eq + SLICE_X26Y15.XMUX Tif5x 0.555 inst_mips_top/inst_pipeline/pc.branch_take + inst_mips_top/inst_pipeline/pc_branch_take_mux000267_G + inst_mips_top/inst_pipeline/pc_branch_take_mux000267 + SLICE_X29Y14.BY net (fanout=3) 0.658 inst_mips_top/inst_pipeline/pc_branch_take_mux0002 + SLICE_X29Y14.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1 + inst_mips_top/inst_pipeline/pc.branch_take_2 ------------------------------------------------- --------------------------- - Total 9.556ns (4.555ns logic, 5.001ns route) - (47.7% logic, 52.3% route) + Total 4.759ns (2.088ns logic, 2.671ns route) + (43.9% logic, 56.1% route) -------------------------------------------------------------------------------- @@ -1087,13 +884,13 @@ Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%; 787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum period is 6.102ns. + Minimum period is 4.689ns. -------------------------------------------------------------------------------- -Slack: 73.898ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_1 (FF) - Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) +Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_7 (FF) Requirement: 80.000ns - Data Path Delay: 5.993ns (Levels of Logic = 4) + Data Path Delay: 4.580ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -1105,37 +902,79 @@ Slack: 73.898ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_1 to inst_ac97_wb/inst_ac_io/cnt_9 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X56Y22.YQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> - inst_ac97_wb/inst_ac_io/cnt_1 - SLICE_X56Y27.G1 net (fanout=8) 0.877 inst_ac97_wb/inst_ac_io/cnt<1> - SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> + inst_ac97_wb/inst_ac_io/cnt_6 + SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> + SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 - SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 + SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> + SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> - inst_ac97_wb/inst_ac_io/cnt_9 + SLICE_X55Y12.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X55Y12.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<6> + inst_ac97_wb/inst_ac_io/cnt_7 ------------------------------------------------- --------------------------- - Total 5.993ns (1.694ns logic, 4.299ns route) - (28.3% logic, 71.7% route) + Total 4.580ns (1.670ns logic, 2.910ns route) + (36.5% logic, 63.5% route) -------------------------------------------------------------------------------- -Slack: 73.898ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_1 (FF) +Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) + Requirement: 80.000ns + Data Path Delay: 4.580ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 80.000ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> + inst_ac97_wb/inst_ac_io/cnt_6 + SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> + SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 + SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 + SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 + SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 + SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + inst_ac97_wb/inst_ac_io/cnt_not00021 + SLICE_X55Y13.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X55Y13.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> + inst_ac97_wb/inst_ac_io/cnt_9 + ------------------------------------------------- --------------------------- + Total 4.580ns (1.670ns logic, 2.910ns route) + (36.5% logic, 63.5% route) + +-------------------------------------------------------------------------------- +Slack: 75.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_6 (FF) Destination: inst_ac97_wb/inst_ac_io/cnt_8 (FF) Requirement: 80.000ns - Data Path Delay: 5.993ns (Levels of Logic = 4) + Data Path Delay: 4.580ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: CLK_O rising at 0.000ns Destination Clock: CLK_O rising at 80.000ns @@ -1147,72 +986,30 @@ Slack: 73.898ns (requirement - (data path - clock path skew + u Discrete Jitter (DJ): 0.217ns Phase Error (PE): 0.000ns - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_1 to inst_ac97_wb/inst_ac_io/cnt_8 + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_6 to inst_ac97_wb/inst_ac_io/cnt_8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X56Y22.YQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> - inst_ac97_wb/inst_ac_io/cnt_1 - SLICE_X56Y27.G1 net (fanout=8) 0.877 inst_ac97_wb/inst_ac_io/cnt<1> - SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + SLICE_X55Y12.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<6> + inst_ac97_wb/inst_ac_io/cnt_6 + SLICE_X55Y8.G2 net (fanout=5) 0.750 inst_ac97_wb/inst_ac_io/cnt<6> + SLICE_X55Y8.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 - SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 + SLICE_X55Y8.F3 net (fanout=1) 0.222 N1018 + SLICE_X55Y8.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> + SLICE_X54Y12.G1 net (fanout=3) 0.598 inst_ac97_wb/inst_ac_io/N9 + SLICE_X54Y12.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> + SLICE_X53Y18.G3 net (fanout=10) 0.666 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y18.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> + SLICE_X55Y13.CE net (fanout=5) 0.674 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X55Y13.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8> inst_ac97_wb/inst_ac_io/cnt_8 ------------------------------------------------- --------------------------- - Total 5.993ns (1.694ns logic, 4.299ns route) - (28.3% logic, 71.7% route) - --------------------------------------------------------------------------------- -Slack: 74.014ns (requirement - (data path - clock path skew + uncertainty)) - Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) - Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF) - Requirement: 80.000ns - Data Path Delay: 5.877ns (Levels of Logic = 4) - Clock Path Skew: 0.000ns - Source Clock: CLK_O rising at 0.000ns - Destination Clock: CLK_O rising at 80.000ns - Clock Uncertainty: 0.109ns - - Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.000ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.217ns - Phase Error (PE): 0.000ns - - Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_9 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X56Y22.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> - inst_ac97_wb/inst_ac_io/cnt_0 - SLICE_X56Y27.G2 net (fanout=9) 0.761 inst_ac97_wb/inst_ac_io/cnt<0> - SLICE_X56Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 - inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 - SLICE_X56Y27.F3 net (fanout=1) 0.213 N966 - SLICE_X56Y27.X Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_out/data_array_11_17 - inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 - SLICE_X54Y24.G1 net (fanout=3) 0.825 inst_ac97_wb/inst_ac_io/N9 - SLICE_X54Y24.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8> - inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 - SLICE_X50Y34.G3 net (fanout=10) 1.102 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 - SLICE_X50Y34.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/inst_ac_in/bitcnt<0> - inst_ac97_wb/inst_ac_io/cnt_not00021 - SLICE_X56Y26.CE net (fanout=5) 1.282 inst_ac97_wb/inst_ac_io/cnt_not0002 - SLICE_X56Y26.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<8> - inst_ac97_wb/inst_ac_io/cnt_9 - ------------------------------------------------- --------------------------- - Total 5.877ns (1.694ns logic, 4.183ns route) - (28.8% logic, 71.2% route) + Total 4.580ns (1.670ns logic, 2.910ns route) + (36.5% logic, 63.5% route) -------------------------------------------------------------------------------- @@ -1229,7 +1026,7 @@ Clock to Setup on destination clock sys_ac97_bit_clk | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -sys_ac97_bit_clk| 9.594| 4.206| | 2.132| +sys_ac97_bit_clk| 7.481| 4.104| | 3.221| ----------------+---------+---------+---------+---------+ Clock to Setup on destination clock sys_clk_in @@ -1237,7 +1034,7 @@ Clock to Setup on destination clock sys_clk_in | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ -sys_clk_in | 9.899| 4.847| 4.836| 2.953| +sys_clk_in | 9.851| 4.837| 4.932| 3.398| ---------------+---------+---------+---------+---------+ @@ -1246,23 +1043,23 @@ Timing summary: Timing errors: 0 Score: 0 -Constraints cover 1334502 paths, 0 nets, and 42622 connections +Constraints cover 1331680 paths, 0 nets, and 42800 connections Design statistics: - Minimum period: 9.899ns{1} (Maximum frequency: 101.020MHz) + Minimum period: 9.864ns{1} (Maximum frequency: 101.379MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Tue Feb 09 13:08:32 2010 +Analysis completed Sun Feb 14 18:17:22 2010 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings -Peak Memory Usage: 347 MB +Peak Memory Usage: 349 MB diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp index 43ab881..d86ce62 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -10,27 +10,28 @@ Target Device : xc4vsx35 Target Package : ff668 Target Speed : -10 Stepping Level : ES -Mapper Version : virtex4 -- $Revision: 1.3 $ -Mapped Date : Tue Feb 09 12:50:04 2010 +Mapper Version : virtex4 -- $Revision: 1.4 $ +Mapped Date : Sun Feb 14 18:06:35 2010 Design Summary -------------- Number of errors: 0 -Number of warnings: 69 +Number of warnings: 68 Logic Utilization: - Number of Slice Flip Flops: 5,374 out of 30,720 17% - Number of 4 input LUTs: 8,573 out of 30,720 27% + Number of Slice Flip Flops: 5,411 out of 30,720 17% + Number of 4 input LUTs: 8,647 out of 30,720 28% Logic Distribution: - Number of occupied Slices: 6,053 out of 15,360 39% - Number of Slices containing only related logic: 6,053 out of 6,053 100% - Number of Slices containing unrelated logic: 0 out of 6,053 0% + Number of occupied Slices: 6,008 out of 15,360 39% + Number of Slices containing only related logic: 6,008 out of 6,008 100% + Number of Slices containing unrelated logic: 0 out of 6,008 0% *See NOTES below for an explanation of the effects of unrelated logic. - Total Number of 4 input LUTs: 8,971 out of 30,720 29% - Number used as logic: 7,573 - Number used as a route-thru: 398 + Total Number of 4 input LUTs: 9,036 out of 30,720 29% + Number used as logic: 7,647 + Number used as a route-thru: 389 + Number used as 16x1 RAMs: 6 Number used for Dual Port RAMs: 792 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 208 + Number used as Shift registers: 202 Number of bonded IOBs: 226 out of 448 50% IOB Flip Flops: 350 IOB Dual-Data Rate Flops: 42 @@ -41,9 +42,9 @@ Logic Distribution: Number of DCM_ADVs: 4 out of 8 50% Number of BSCAN_VIRTEX4s: 1 out of 4 25% -Peak Memory Usage: 512 MB -Total REAL time to MAP completion: 8 mins 30 secs -Total CPU time to MAP completion: 8 mins 17 secs +Peak Memory Usage: 533 MB +Total REAL time to MAP completion: 8 mins 4 secs +Total CPU time to MAP completion: 7 mins 55 secs Table of Contents ----------------- @@ -521,11 +522,6 @@ WARNING:Place:838 - An IO Bus with more than one IO standard is found. Comp: sys_vga_red<7> IOSTANDARD = LVCMOS25 -WARNING:Place:957 - Placer has detected that XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING - has been set. This environment variable has been deprecated. An ERROR in - clock placement rules can be demoted to a WARNING by using the - CLOCK_DEDICATED_ROUTE constraint on a specific component pin in the .ucf - file. WARNING:PhysDesignRules:1236 - Unknown DCM_ADV feedback loop. The signal sys_sdr_clk_fb_IBUFG on the CLKFB pin of DCM_ADV comp inst_clockgen/inst_DCM_SDRCLK_0 was driven by an IOB site but the signal loop could not be traced back to the CLK0 pin of comp inst_clockgen/inst_DCM_SDRCLK_0. The signal out the CLK0 pin must drive an IOB input pin with @@ -1500,16 +1496,17 @@ Area Group "AG_inst_mips_top" RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X 3Y0:RAMB16_X3Y6 Area Group Logic Utilization: - Number of Slice Flip Flops: 1,922 out of 4,320 44% + Number of Slice Flip Flops: 1,951 out of 4,320 45% Logic Distribution: - Number of occupied Slices: 2,124 out of 2,160 98% - Number of Slices containing only related logic: 2,124 out of 2,124 100% - Total Number of 4 input LUTs: 4,218 out of 4,320 97% - Number used as logic: 3,549 - Number used as route-thru: 58 + Number of occupied Slices: 2,157 out of 2,160 99% + Number of Slices containing only related logic: 2,157 out of 2,157 100% + Total Number of 4 input LUTs: 4,308 out of 4,320 99% + Number used as logic: 3,648 + Number used as route-thru: 49 + Number used as 16x1 RAMs: 2 Number used as Dual Port RAMs: 586 (Two LUTs used per Dual Port RAM) - Number used as Shift registers: 25 + Number used as Shift registers: 23 Number of Block RAMs: 27 out of 28 96% @@ -1542,34 +1539,34 @@ Section 14 - Utilization by Hierarchy +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| mips_sys/ | | 1416/8338 | 28/5374 | 891/8971 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | -| +inst_ac97_wb | | 181/838 | 118/671 | 185/617 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | -| ++inst_ac_io | | 21/623 | 13/524 | 29/378 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | -| +++inst_ac_in | | 285/290 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | +| mips_sys/ | | 1395/8308 | 28/5411 | 849/9036 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | +| +inst_ac97_wb | | 183/796 | 118/672 | 186/631 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | +| ++inst_ac_io | | 20/574 | 13/525 | 29/380 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | +| +++inst_ac_in | | 261/265 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | | ++++singleshot_inst1 | | 2/2 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | -| ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | -| +++inst_ac_out | | 309/312 | 247/249 | 244/246 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | +| ++++singleshot_inst2 | | 2/2 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | +| +++inst_ac_out | | 286/289 | 248/250 | 246/248 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | | ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 | -| ++inst_tx_fifo | | 1/34 | 0/29 | 1/54 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | -| +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 32/32 | 29/29 | 52/52 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | -| +inst_clockgen | | 41/47 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | +| ++inst_tx_fifo | | 1/39 | 0/29 | 1/65 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 38/38 | 29/29 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | +| +inst_clockgen | | 44/50 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | | ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 | | ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 | | ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 | | ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 | | ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 | | ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 | -| +inst_flash_port | | 81/81 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | -| +inst_gpio_wb | | 299/299 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | -| +inst_mips_top | | 25/2831 | 22/1920 | 13/4123 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | +| +inst_flash_port | | 80/80 | 65/65 | 54/54 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | +| +inst_gpio_wb | | 301/301 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | +| +inst_mips_top | | 26/2930 | 22/1950 | 12/4222 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | | ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 | | ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 | | ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 | -| ++inst_biu | | 193/811 | 97/534 | 209/915 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | -| +++inst_bin_fifo | | 4/96 | 0/62 | 4/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | -| ++++inst_dpram_1w1r | | 53/53 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 12/39 | 12/30 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | +| ++inst_biu | | 191/816 | 97/561 | 210/926 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | +| +++inst_bin_fifo | | 2/97 | 0/62 | 2/106 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | +| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 12/38 | 12/30 | 6/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1581,10 +1578,10 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 9/9 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_bout_fifo | | 4/148 | 0/97 | 4/178 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | -| ++++inst_dpram_1w1r | | 103/103 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 12/41 | 12/30 | 5/40 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | +| +++++inst_gray_counter_w | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_bout_fifo | | 6/150 | 0/97 | 6/177 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | +| ++++inst_dpram_1w1r | | 105/105 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 10/39 | 12/30 | 3/37 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1595,46 +1592,46 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | -| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 11/11 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +++inst_dcache | | 180/180 | 120/120 | 148/148 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | +| +++++inst_gray_counter_r | | 9/9 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_w | | 10/10 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_dcache | | 174/174 | 147/147 | 149/149 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | | ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram | | ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram | | ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram | | ++++gen_data_ram[3].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram | | ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram | -| +++inst_icache | | 113/113 | 81/81 | 121/121 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | +| +++inst_icache | | 117/117 | 81/81 | 123/123 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | | ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram | | ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram | -| +++inst_write_fifo | | 1/81 | 0/77 | 1/152 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | -| ++++inst_dpram_1w1r | | 67/67 | 66/66 | 133/133 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | -| ++++inst_fifo_sync_ctrl | | 13/13 | 11/11 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | -| ++inst_cop | | 214/214 | 190/190 | 239/239 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | -| ++inst_pipeline | | 854/1778 | 646/1174 | 1297/2953 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | -| +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | +| +++inst_write_fifo | | 2/87 | 0/77 | 2/161 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | +| ++++inst_dpram_1w1r | | 66/66 | 66/66 | 132/132 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | +| ++++inst_fifo_sync_ctrl | | 19/19 | 11/11 | 27/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | +| ++inst_cop | | 239/239 | 190/190 | 237/237 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | +| ++inst_pipeline | | 921/1846 | 650/1177 | 1386/3044 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | +| +++inst_alu | | 62/62 | 0/0 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | | +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu | -| +++inst_muldiv | | 563/563 | 526/526 | 1025/1025 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | +| +++inst_muldiv | | 572/572 | 527/527 | 1027/1027 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | | +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual | -| +++inst_shifter | | 162/162 | 1/1 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | -| +inst_ps2_phy_0 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | +| +++inst_shifter | | 155/155 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | +| +inst_ps2_phy_0 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | | ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | -| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | -| +inst_ps2_phy_1 | | 0/13 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | +| ++Inst_debounce_data | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | +| +inst_ps2_phy_1 | | 0/12 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | | ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | -| ++Inst_debounce_data | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | -| +inst_ps2_wb_0 | | 36/158 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | +| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | +| +inst_ps2_wb_0 | | 35/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | | ++inst_ps2_core | | 122/122 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | -| +inst_ps2_wb_1 | | 32/151 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | -| ++inst_ps2_core | | 119/119 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | -| +inst_rom_wb | | 1/73 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | -| ++inst_rom | | 72/72 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | -| +inst_sdram_ctrl_frontend_wb | | 109/676 | 0/455 | 145/598 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | -| ++inst_cat_fifo | | 1/16 | 0/13 | 1/24 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | -| +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 14/14 | 13/13 | 22/22 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | -| ++inst_read_fifo | | 5/57 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | +| +inst_ps2_wb_1 | | 32/150 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | +| ++inst_ps2_core | | 118/118 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | +| +inst_rom_wb | | 1/76 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | +| ++inst_rom | | 75/75 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | +| +inst_sdram_ctrl_frontend_wb | | 110/669 | 0/455 | 145/593 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | +| ++inst_cat_fifo | | 2/17 | 0/13 | 2/23 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 15/15 | 13/13 | 21/21 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | +| ++inst_read_fifo | | 2/54 | 0/36 | 2/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 18/52 | 14/36 | 10/52 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1649,15 +1646,15 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | | ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_sdram_ctrl | | 0/436 | 0/370 | 0/319 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | -| +++inst_ddr_phy | | 171/172 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | +| ++inst_sdram_ctrl | | 0/433 | 0/370 | 0/317 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | +| +++inst_ddr_phy | | 179/180 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | | ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 | -| +++inst_sd_cmd_fifo | | 3/67 | 0/41 | 4/60 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | +| +++inst_sd_cmd_fifo | | 4/64 | 0/41 | 6/58 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | | ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r | -| ++++inst_fifo_async_ctrl | | 23/64 | 17/41 | 11/56 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | +| ++++inst_fifo_async_ctrl | | 21/60 | 17/41 | 9/52 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | | +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | -| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | | +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | | +++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | | +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | @@ -1666,16 +1663,16 @@ Section 14 - Utilization by Hierarchy | +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | +++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| +++++Mshreg_p2_2_BRB0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB0 | -| +++++Mshreg_p2_2_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB1 | -| +++++Mshreg_p2_2_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB2 | -| +++++inst_gray_counter_r | | 15/15 | 13/13 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| +++++inst_gray_counter_w | | 12/12 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++++Mshreg_p2_3_BRB0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB0 | +| +++++Mshreg_p2_3_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB1 | +| +++++Mshreg_p2_3_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_3_BRB2 | +| +++++inst_gray_counter_r | | 14/14 | 13/13 | 14/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | | +++inst_sdram_cmd | | 46/46 | 13/13 | 65/65 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | -| +++inst_sdram_ctrl | | 151/151 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | -| ++inst_write_fifo | | 5/58 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | +| +++inst_sdram_ctrl | | 143/143 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | +| ++inst_write_fifo | | 3/55 | 0/36 | 3/54 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 18/53 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 19/52 | 14/36 | 9/51 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | | ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | | ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | | ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | @@ -1688,31 +1685,31 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | | ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | | ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | -| ++++inst_gray_counter_r | | 12/12 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | | ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| +inst_uart_wb_0 | | 59/104 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | -| ++inst_uart_rx | | 0/27 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | +| +inst_uart_wb_0 | | 59/105 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | +| ++inst_uart_rx | | 0/29 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf | -| +++kcuart | | 19/19 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/18 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | +| +++kcuart | | 21/21 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf | -| +++kcuart | | 10/10 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | -| +inst_uart_wb_1 | | 61/107 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | +| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | +| +inst_uart_wb_1 | | 56/103 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | | ++inst_uart_rx | | 0/28 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf | | +++kcuart | | 20/20 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | -| ++inst_uart_tx | | 0/18 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | +| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | | +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf | -| +++kcuart | | 10/10 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | +| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | | +inst_usb_port | | 37/37 | 27/27 | 31/31 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | -| +inst_vga_frontend | | 868/1495 | 793/1245 | 766/1554 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | -| ++inst_blitfifo | | 1/25 | 0/21 | 1/40 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | +| +inst_vga_frontend | | 802/1436 | 793/1251 | 762/1553 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | +| ++inst_blitfifo | | 4/31 | 0/23 | 4/45 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 24/24 | 21/21 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | -| ++inst_bus_fifo | | 2/115 | 0/110 | 2/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | -| +++inst_dpram_1w1r | | 104/104 | 103/103 | 207/207 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | -| +++inst_fifo_sync_ctrl | | 9/9 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | -| ++inst_char_gen | | 196/208 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | +| +++inst_fifo_sync_ctrl | | 27/27 | 23/23 | 41/41 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | +| ++inst_bus_fifo | | 3/116 | 0/110 | 3/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | +| +++inst_dpram_1w1r | | 103/103 | 103/103 | 206/206 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 10/10 | 7/7 | 10/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | +| ++inst_char_gen | | 194/206 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | | +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 | | +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 | | +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 | @@ -1727,9 +1724,9 @@ Section 14 - Utilization by Hierarchy | +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 | | +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram | | +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom | -| ++inst_linefifo | | 1/173 | 0/145 | 1/179 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | +| ++inst_linefifo | | 2/178 | 0/149 | 2/177 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | | +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r | -| +++inst_fifo_async_ctrl | | 83/172 | 87/145 | 84/178 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | +| +++inst_fifo_async_ctrl | | 83/176 | 91/149 | 81/175 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | | ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 | | ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 | | ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 | @@ -1776,12 +1773,12 @@ Section 14 - Utilization by Hierarchy | ++++Mshreg_gcnt2_w_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7 | | ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 | | ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 | -| ++++inst_gray_counter_r | | 22/22 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | -| ++++inst_gray_counter_w | | 21/21 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | -| ++inst_vga_backend | | 65/106 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | -| +++inst_vga_timing | | 0/41 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | -| ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | -| ++++inst_vga_sync_v | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 27/27 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_vga_backend | | 61/103 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | +| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | +| ++++inst_vga_sync_h | | 20/20 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | +| ++++inst_vga_sync_v | | 22/22 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slices can be packed with basic elements from multiple hierarchies. diff --git a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf index 3a5602d..8357676 100644 --- a/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf +++ b/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf @@ -53,6 +53,16 @@ NET "RST_O" TIG; #INST inst_clockgen/inst_DCM_BASE_0 LOC = DCM_ADV_X0Y4; #INST inst_clockgen/inst_DCM_BASE_1 LOC = DCM_ADV_X0Y3; +# --------------------------------------------------------------------------------- +# Floor planning +# --------------------------------------------------------------------------------- +#INST "inst_vga_frontend" AREA_GROUP = "AG_inst_vga_frontend" ; +#AREA_GROUP "AG_inst_vga_frontend" RANGE = SLICE_X8Y191:SLICE_X30Y141 ; +#AREA_GROUP "AG_inst_vga_frontend" RANGE = RAMB16_X0Y18:RAMB16_X0Y23, RAMB16_X1Y18:RAMB16_X1Y23, RAMB16_X2Y18:RAMB16_X2Y23 ; + +#INST "inst_sdram_ctrl_frontend_wb" AREA_GROUP = "AG_inst_sdram_ctrl_frontend_wb" ; +#AREA_GROUP "AG_inst_sdram_ctrl_frontend_wb" RANGE = SLICE_X0Y191:SLICE_X7Y141 ; + INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ; # GOOD 1 #AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ; diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo index 3a874c7..988f8b6 100644 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ b/projects/mips_sys/sim/tb_mips_sys.wdo @@ -44,6 +44,18 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_flash +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_usb +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_sdram +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_rom +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_gpio +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart0 +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart1 +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_uart2 +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ssram +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ac97 +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_i_ps2 add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o add wave -noupdate -divider {Clock Gen} add wave -noupdate -format Logic /tb_mips_sys/uut/inst_clockgen/rst_in @@ -142,6 +154,7 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fif add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_full add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bin_fifo_empty +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_biu/bus_idle add wave -noupdate -divider USB add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn @@ -233,7 +246,7 @@ add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/ add wave -noupdate -divider D-Cache add wave -noupdate -format Logic /tb_mips_sys/uut/clk_o TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {73611245 ps} 0} {{Cursor 100} {29884668 ps} 0} {{Cursor 3} {4840402000 ps} 0} +WaveRestoreCursors {{Cursor 2} {23544064 ps} 0} {{Cursor 100} {997024491 ps} 0} {{Cursor 3} {4840402000 ps} 0} configure wave -namecolwidth 187 configure wave -valuecolwidth 64 configure wave -justifyvalue left @@ -247,4 +260,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {4840006260 ps} {4842142452 ps} +WaveRestoreZoom {23318965 ps} {23757718 ps}