diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd
index aabc7e8..4bd0ecb 100644
--- a/lib/filter/src/fir_semi_parallel.vhd
+++ b/lib/filter/src/fir_semi_parallel.vhd
@@ -58,7 +58,7 @@ Port
 	din_vld		: in std_logic;
 	din			: in sfixed;
 	dout_vld	: out std_logic;
-	start		: in std_logic;
+	start		: in  std_logic;
 	rdy			: out std_logic;
 	dout		: out sfixed
 );
@@ -92,7 +92,7 @@ architecture Behavioral of fir_semi_parallel is
 
 	signal en			: std_logic;
 	signal accu_load	: std_logic;
-	signal accu_ld_pipe	: unsigned(input_latency+coef_latency+pipe_latency downto 0);
+	signal accu_ld_pipe	: unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0);
 	
 	signal din_r 		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
 	signal coef_we 		: unsigned(nstages-1 downto 0);
@@ -104,11 +104,10 @@ architecture Behavioral of fir_semi_parallel is
 	-------------------------------------------------------------------------------
 begin
 
-	assert nstages > 0 report "nstages  must be greater than 0!" severity failure;
 	assert ntaps_per_stage = NextPowerOfTwo(ntaps_per_stage) report "ntaps_per_stage must be of form 2**R!" severity failure;
 	assert ntaps_per_stage >= 4 report "ntaps_per_stage must be greater than 4" severity failure;
 
-	x(0)		<= resize(din, x(0));
+	x(0)		<= resize(din_r, x(0));
 	y(0)		<= to_sfixed(0.0, y(0));
 
 	accu_load	<= accu_ld_pipe(accu_ld_pipe'left);
@@ -130,7 +129,7 @@ accu_load_pipe:
 			if rst = '1' then
 				accu_ld_pipe <= (others => '0');
 			elsif en = '1' then
-				accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & ce_array(nstages-1);
+				accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & ce0;
 			end if;	
 		end if;
 	end process;
@@ -170,7 +169,7 @@ counter:
 				end if;	
 			else
 				en	<= '0';
-				if start = '1' then
+				if din_vld = '1' then
 					en	<= '1';
 					cnt := 0;
 					ce0	<= '1';
@@ -258,29 +257,10 @@ gen_stages:
 	end generate;
 					
 
-inst_first_delay_line : entity work.delay_line(ram_based)
-	GENERIC MAP
-	(
-		nbits		=> nbits_stages,
-		nbits_frac	=> nbits_stages_frac,
-		ntaps		=> ntaps_per_stage,
-		delay_fix	=> 0
-	)
-	PORT MAP
-	(
-		rst			=> rst,
-		clk			=> clk,
-		ce			=> '1',
-		shift_en	=> din_vld,
-		delay		=> count_array(0),
-		din			=> x(0),
-		dout		=> x(1)
-	);
-
 gen_delays:
-	for i in 1 to nstages-1 generate
+	for i in 0 to nstages-1 generate
 	begin
-		inst_delay_lines : entity work.delay_line(ram_based)
+		inst_delay_line : entity work.delay_line(ram_based)
 		GENERIC MAP
 		(
 			nbits		=> nbits_stages,