jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added Blitter registers

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@669 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-21 10:06:51 +00:00
parent 717239c086
commit 935645a97e
1 changed files with 150 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/vga_frontend64.vhd
+150 -37
View File
@@ -132,14 +132,31 @@ architecture Behavioral of vga_frontend64 is
signal vga_fb_front : unsigned(31 downto 0);
signal host_fb_front : unsigned(31 downto 0);
signal host_fb_back : unsigned(31 downto 0);
signal blit_addr_src_0 : unsigned(31 downto 0);
signal blit_addr_src_1 : unsigned(31 downto 0);
signal blit_addr_dst : unsigned(31 downto 0);
signal blit_dimx_src_0 : unsigned(31 downto 0);
signal blit_dimx_src_1 : unsigned(31 downto 0);
signal blit_dimx_dst : unsigned(31 downto 0);
signal blit_nx : unsigned(31 downto 0);
signal blit_ny : unsigned(31 downto 0);
signal blit_func_sel : unsigned(3 downto 0);
signal blit_comb_sel : unsigned(3 downto 0);
signal blit_request : std_logic;
signal blit_request_set : std_logic;
signal blit_request_clr : std_logic;
signal blit_complete : std_logic;
signal blit_complete_ack : std_logic;
signal blit_complete_inten : std_logic;
signal vga_scan_rdy : std_logic;
signal vga_master_en : std_logic;
signal request_cnt_rst : std_logic;
signal request_cnt_en : std_logic;
signal request_en : std_logic;
signal pixel_cnt_rst : std_logic;
signal read_bus_en : std_logic;
signal request_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal read_cnt : natural range 0 to MAX_REQUEST_CNT-1;
signal request_cnt : unsigned(28 downto 0);
signal read_cnt : unsigned(28 downto 0);
signal bus_read_fin : std_logic;
signal STB_O_scan : std_logic;
signal ADDR_O_scan : unsigned(31 downto 0);
@@ -187,6 +204,17 @@ proc_bufchg_irq:
end if;
end process;
proc_blit_flags:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
blit_request <= '0';
blit_complete <= '0';
end if;
end if;
end process;
inst_vga_backend : entity work.vga_backend
GENERIC MAP
(
@@ -297,7 +325,7 @@ inst_bus_fifo: entity work.fifo_sync
);
bus_rdy <= not bus_fifo_full;
bus_fifo_re <= not bus_fifo_empty and SRDY_I;
bus_fifo_we <= STB_O_scan and request_cnt_en;
bus_fifo_we <= request_en;
bus_fifo_data_in <= (others => '-');
bus_fifo_addr_in <= ADDR_O_scan;
bus_fifo_sel_in <= (others => '1');
@@ -317,14 +345,14 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, read_cnt, request_cnt)
process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin)
begin
CYC_O <= '0';
STB_O_scan <= '0';
pixel_cnt_rst <= '0';
request_cnt_rst <= '0';
request_cnt_en <= '0';
request_en <= '0';
read_bus_en <= '0';
sn <= s;
@@ -349,7 +377,7 @@ vga_master:
when bus_request =>
CYC_O <= '1';
STB_O_scan <= '1';
request_cnt_en <= '1';
request_en <= '1';
read_bus_en <= '1';
if fifo_almost_full = '1' then
sn <= bus_data;
@@ -357,7 +385,7 @@ vga_master:
when bus_data =>
CYC_O <= '1';
read_bus_en <= '1';
if read_cnt = request_cnt then
if bus_read_fin = '1' then
sn <= rdy;
if vga_master_en = '0' then
sn <= idle;
@@ -369,35 +397,42 @@ vga_master:
end case;
end process;
request_counter:
proc_bus_request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= 0;
elsif request_cnt_en = '1' and bus_rdy = '1' then
if request_cnt /= MAX_REQUEST_CNT-1 then
request_cnt <= request_cnt + 1;
end if;
request_cnt <= (others => '0');
elsif request_en = '1' and bus_rdy = '1' then
request_cnt <= request_cnt + 1;
end if;
end if;
end process;
read_counter:
proc_bus_read_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= 0;
read_cnt <= (others => '0');
elsif read_bus_en = '1' and ACK_I = '1' then
if read_cnt /= MAX_REQUEST_CNT-1 then
read_cnt <= read_cnt + 1;
end if;
read_cnt <= read_cnt + 1;
end if;
end if;
end process;
addr_gen_scan:
proc_bus_read_finish:
process(CLK_I)
begin
if rising_edge(CLK_I) then
bus_read_fin <= '0';
if read_cnt = request_cnt then
bus_read_fin <= '1';
end if;
end if;
end process;
proc_scan_addr:
process(CLK_I)
begin
if rising_edge(CLK_I) then
@@ -405,7 +440,7 @@ addr_gen_scan:
if pixel_cnt_rst = '1' then
pixel_cnt <= 0;
front <= host_fb_front;
elsif request_cnt_en = '1' and bus_rdy = '1' then
elsif request_en = '1' and bus_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt <= pixel_cnt + 1;
else
@@ -471,10 +506,15 @@ registers_read:
-- sys_vga_ctrl 0
when "0000" =>
SDAT_O(0) <= cg_rdy;
SDAT_O(1) <= vga_master_en;
SDAT_O(2) <= bufchg_irq_en;
SDAT_O(3) <= bufchg_flag;
SDAT_O(0) <= cg_rdy;
SDAT_O(1) <= vga_master_en;
SDAT_O(2) <= bufchg_irq_en;
SDAT_O(3) <= bufchg_flag;
SDAT_O(8) <= blit_request;
SDAT_O(9) <= blit_complete;
SDAT_O(10) <= blit_complete_inten;
SDAT_O(23 downto 20) <= blit_comb_sel;
SDAT_O(19 downto 16) <= blit_func_sel;
-- sys_vga_ascii 4
when "0001" =>
@@ -504,13 +544,44 @@ registers_read:
when "0111" =>
SDAT_O <= vga_fb_back;
-- sys_blit_addr_src_0 32
when "1000" =>
SDAT_O <= blit_addr_src_0;
-- sys_blit_addr_src_1 36
when "1001" =>
SDAT_O <= blit_addr_src_1;
-- sys_blit_addr_dst 40
when "1010" =>
SDAT_O <= blit_addr_dst;
-- sys_blit_dimx_src_0 44
when "1011" =>
SDAT_O <= blit_dimx_src_0;
-- sys_blit_dimx_src_1 48
when "1100" =>
SDAT_O <= blit_dimx_src_1;
-- sys_blit_dimx_dst 52
when "1101" =>
SDAT_O <= blit_dimx_dst;
-- sys_blit_nx 56
when "1110" =>
SDAT_O <= blit_nx;
-- sys_blit_ny 60
when "1111" =>
SDAT_O <= blit_ny;
when others => null;
end case;
end if;
end if;
end process;
registers_write:
process(CLK_I)
begin
@@ -521,23 +592,33 @@ registers_write:
cg_clr_screen <= '0';
cg_clr_line <= '0';
bufchg_flag_ack <= '0';
blit_request_set <= '0';
blit_complete_ack <= '0';
if RST_I = '1' then
cg_din <= (others => '0');
vga_master_en <= '0';
bufchg_irq_en <= '0';
host_fb_front <= X"40000000";
host_fb_back <= X"40010000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
cg_din <= (others => '0');
vga_master_en <= '0';
bufchg_irq_en <= '0';
blit_complete_inten <= '0';
blit_func_sel <= (others => '0');
blit_comb_sel <= (others => '0');
host_fb_front <= X"40000000";
host_fb_back <= X"40010000";
cg_color <= (X"FF", X"FF", X"FF", X"FF");
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
-- sys_vga_ctrl 0
when "0000" =>
vga_master_en <= SDAT_I(1);
bufchg_irq_en <= SDAT_I(2);
bufchg_flag_ack <= SDAT_I(3);
cg_clr_screen <= SDAT_I(4);
cg_clr_line <= SDAT_I(5);
vga_master_en <= SDAT_I(1);
bufchg_irq_en <= SDAT_I(2);
bufchg_flag_ack <= SDAT_I(3);
cg_clr_screen <= SDAT_I(4);
cg_clr_line <= SDAT_I(5);
blit_request_set <= SDAT_I(8);
blit_complete_ack <= SDAT_I(9);
blit_complete_inten <= SDAT_I(10);
blit_func_sel <= SDAT_I(19 downto 16);
blit_comb_sel <= SDAT_I(23 downto 20);
-- sys_vga_ascii 4
when "0001" =>
@@ -567,6 +648,38 @@ registers_write:
bufchg_flag_ack <= '1';
host_fb_back <= SDAT_I(31 downto 2) & "00";
-- sys_blit_addr_src_0 32
when "1000" =>
blit_addr_src_0 <= SDAT_I;
-- sys_blit_addr_src_1 36
when "1001" =>
blit_addr_src_1 <= SDAT_I;
-- sys_blit_addr_dst 40
when "1010" =>
blit_addr_dst <= SDAT_I;
-- sys_blit_dimx_src_0 44
when "1011" =>
blit_dimx_src_0 <= SDAT_I;
-- sys_blit_dimx_src_1 48
when "1100" =>
blit_dimx_src_1 <= SDAT_I;
-- sys_blit_dimx_dst 52
when "1101" =>
blit_dimx_dst <= SDAT_I;
-- sys_blit_nx 56
when "1110" =>
blit_nx <= SDAT_I;
-- sys_blit_ny 60
when "1111" =>
blit_ny <= SDAT_I;
when others => null;
end case;