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- removed edge trigger capabilty

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git-svn-id: http://moon:8086/svn/vhdl/trunk@365 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-28 12:43:53 +00:00
parent 0f52e03f7b
commit 92a1179fee
2 changed files with 6 additions and 47 deletions
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lib/CPUs/JCpu/src/core/chipreg.vhd
+1 -3
View File
@@ -69,7 +69,6 @@ proc_reg_write:
reg_bank_sel <= (others => '0'); reg_bank_sel <= (others => '0');
reg_int_ctrl.enable <= '0'; reg_int_ctrl.enable <= '0';
reg_int_ctrl.polarity <= '1'; reg_int_ctrl.polarity <= '1';
reg_int_ctrl.edge_sens <= '1';
elsif rising_edge(clk) then elsif rising_edge(clk) then
reg_int_ctrl.request <= '0'; reg_int_ctrl.request <= '0';
if we = '1' then if we = '1' then
@@ -79,7 +78,6 @@ proc_reg_write:
when X"03" => when X"03" =>
reg_int_ctrl.enable <= din(0); reg_int_ctrl.enable <= din(0);
reg_int_ctrl.polarity <= din(1); reg_int_ctrl.polarity <= din(1);
reg_int_ctrl.edge_sens <= din(2);
reg_int_ctrl.request <= din(7); reg_int_ctrl.request <= din(7);
when X"04" => when X"04" =>
reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0);
@@ -103,7 +101,7 @@ proc_reg_read:
when X"02" => -- CPU status when X"02" => -- CPU status
dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero; dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero;
when X"03" => -- Interrupt control when X"03" => -- Interrupt control
dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable; dout <= "000000" & reg_int_ctrl.polarity & reg_int_ctrl.enable;
when X"04" => -- Upper stack bits out when X"04" => -- Upper stack bits out
dout <= "0000" & reg_cmem_high; dout <= "0000" & reg_cmem_high;
when X"05" => -- Upper cmem bits out when X"05" => -- Upper cmem bits out
lib/CPUs/JCpu/src/core/int_ctrl.vhd
+5 -44
View File
@@ -48,13 +48,11 @@ end int_ctrl;
architecture Behavioral of int_ctrl is architecture Behavioral of int_ctrl is
type int_state_t is (int_idle, int_inject, int_active, int_release); type int_state_t is (int_idle, int_inject, int_active, int_release);
type pin_state_t is (pin_s0, pin_s1, pin_s2);
signal int_state, int_state_next : int_state_t; signal int_state, int_state_next : int_state_t;
signal pin_state, pin_state_next : pin_state_t;
signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC; signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC;
signal int_request : std_logic; signal int_request : std_logic;
signal int_sampled : std_logic;
begin begin
@@ -74,7 +72,6 @@ irg_ctrl_fsm:
pc_load <= '0'; pc_load <= '0';
stk_push <= '0'; stk_push <= '0';
stk_pop <= '0'; stk_pop <= '0';
case int_state is case int_state is
when int_idle => when int_idle =>
@@ -121,46 +118,10 @@ pin_sample:
process (clk) process (clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
int_sampled <= int_in xor (not ctrl_in.polarity); int_request <= '0';
end if; if ctrl_in.enable = '1' then
end process; int_request <= (int_in xor (not ctrl_in.polarity)) or ctrl_in.request;
end if;
-----------------------------------------------------------------------
pin_fsm:
process (pin_state, int_sampled, int_ack, ctrl_in)
begin
int_request <= '0';
pin_state_next <= pin_state;
case pin_state is
when pin_s0 =>
if int_sampled = '1' or ctrl_in.request = '1' then
if ctrl_in.enable = '1' then
pin_state_next <= pin_s1;
end if;
end if;
when pin_s1 =>
int_request <= '1';
if int_ack = '1' then
pin_state_next <= pin_s2;
end if;
when pin_s2 =>
if ctrl_in.edge_sens = '0' then
pin_state_next <= pin_s0;
elsif int_sampled = '0' then
pin_state_next <= pin_s0;
end if;
when others =>
pin_state_next <= pin_s0;
end case;
end process;
pin_states:
process (rst, clk, pin_state_next)
begin
if rst = '1' then
pin_state <= pin_s0;
elsif rising_edge(clk) then
pin_state <= pin_state_next;
end if; end if;
end process; end process;