From 92781859e1a3e69547dccb25c0c09373b6a86728 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 30 Mar 2021 09:17:34 +0000 Subject: [PATCH] - added more constraints git-svn-id: http://moon:8086/svn/vhdl/trunk@1599 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf index 8677362..9735c82 100644 --- a/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf +++ b/projects/mips_sys/ise101/mips_sys/project/mips_sys.ucf @@ -35,12 +35,17 @@ NET "gmii_clk" TNM_NET = "gmii_clk"; TIMESPEC "TS_gmii_clk" = PERIOD "gmii_clk" 8.0 ns HIGH 50 %; TIMESPEC "TS_unrelate_GMII" = FROM sys_clk TO gmii_clk TIG; +NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk"; +TIMESPEC "TS_ac97_clk" = PERIOD "ac97_clk" 80 ns HIGH 50 %; +TIMESPEC "TS_unrelate_AC97" = FROM sys_clk TO ac97_clk TIG; + NET "sys_clk_in" LOC = "AE14"; NET sys_clk_in IOSTANDARD = LVCMOS33; NET "sys_rst_n_in" LOC = "D6"; NET sys_rst_n_in PULLUP; NET "sys_rst_n_in" TIG; NET "RST_O" TIG; +NET "vga_rst" TIG; #NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE; #PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; @@ -536,9 +541,6 @@ NET sys_vga_sync_n IOSTANDARD = LVCMOS33; #------------------------------------------------------------------------------ # IO Pad Location Constraints / Properties for AC97 Sound Controller #------------------------------------------------------------------------------ -NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk"; -TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %; - NET sys_ac97_bit_clk LOC = AE10; NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33; NET sys_ac97_bit_clk PERIOD = 80;