jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- minor changes to make ISE meet timing

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@652 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-09 20:29:54 +00:00
parent 9975fbd6cc
commit 9253fd1df8
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/vga_frontend64.vhd
+2 -2
View File
@@ -154,10 +154,10 @@ proc_bufchg_irq:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if RST_I = '1' or bufchg_flag_ack = '1' then if pixel_cnt_rst = '1' or bufchg_flag_ack = '1' then
bufchg_flag <= '0'; bufchg_flag <= '0';
elsif bufchg = '1' then elsif bufchg = '1' then
bufchg_flag <= vga_master_en; bufchg_flag <= '1';
end if; end if;
INT_O <= bufchg_flag and bufchg_irq_en; INT_O <= bufchg_flag and bufchg_irq_en;
end if; end if;