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- added states of pins clk and data to status register

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git-svn-id: http://moon:8086/svn/vhdl/trunk@693 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2009-12-06 15:22:01 +00:00
parent a1d88baad4
commit 922ade83b7
1 changed files with 5 additions and 1 deletions
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lib/ps2_port/src/ps2_wb.vhd
+5 -1
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@@ -46,6 +46,8 @@ ARCHITECTURE behavior OF ps2_wb IS
signal tx_empty : std_logic;
signal rx_err_flag : std_logic;
signal rx_err_par : std_logic;
signal stat_clk : std_logic;
signal stat_data : std_logic;
begin
@@ -108,6 +110,8 @@ irq_register:
INT_O <= irq_rx or irq_tx;
irq_tx <= tx_empty and tx_int_en;
irq_rx <= rx_data_present and rx_int_en;
stat_clk <= clk_rx;
stat_data <= data_rx;
end if;
end process;
@@ -134,6 +138,6 @@ inst_ps2_core: entity work.ps2_core
ps2_data_tx => data_tx
);
ps2_status_port <= rx_err_flag & "000" & rx_err_par & '0' & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & '0' & '0' & rx_data_present & '0' & tx_empty;
ps2_status_port <= rx_err_flag & "000" & rx_err_par & '0' & irq_rx & irq_tx & '0' & rx_int_en & tx_int_en & stat_data & stat_clk & rx_data_present & '0' & tx_empty;
end behavior;