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Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@300 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-30 21:43:29 +00:00
parent f3d47b0bb9
commit 917db4cc8b
4 changed files with 6 additions and 6 deletions
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projects/mips_sys/ise101/mips_sys/mips_sys.prj
+2 -2
View File
@@ -6,8 +6,8 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
vhdl work "../../../../lib/misc/utils_pkg.vhd"
vhdl work "../../../../lib/misc/singleshot.vhd"
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
@@ -20,7 +20,7 @@ vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
vhdl work "../../src/ram_ld.vhd"
projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj
+2 -2
View File
@@ -6,8 +6,8 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
@@ -20,7 +20,7 @@ vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"