- uses common fixed_pkg
git-svn-id: http://moon:8086/svn/vhdl/trunk@242 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -1,8 +1,10 @@
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vmap ieee_proposed ../../../../Common/sim/ieee_proposed
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vlib work
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vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
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vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
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vcom -explicit -93 "../../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/mix_pkg.vhd"
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vcom -explicit -93 "../src/mix_cpx.vhd"
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vcom -explicit -93 "../src/tb_mix_cpx.vhd"
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vsim -t 1ps -lib work tb_mix_cpx
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@@ -1,8 +1,10 @@
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vmap ieee_proposed ../../../../Common/sim/ieee_proposed
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vlib work
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vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd"
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vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
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vcom -explicit -93 "../../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd"
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vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
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vcom -explicit -93 "../src/mix_pkg.vhd"
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vcom -explicit -93 "../src/mix_real.vhd"
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vcom -explicit -93 "../src/tb_mix_real.vhd"
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vsim -t 1ps -lib work tb_mix_real
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@@ -21,8 +21,13 @@ library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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@@ -39,8 +44,8 @@ Generic
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has_in_reg : boolean := false;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false;
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rounding : boolean := true;
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saturating : boolean := true
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rounding : fixed_round_style_type := fixed_round;
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saturating : fixed_overflow_style_type := fixed_saturate
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);
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Port
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(
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@@ -141,8 +146,8 @@ begin
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variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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begin
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sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating);
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sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating);
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sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, saturating, rounding);
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sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, saturating, rounding);
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if has_out_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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@@ -21,8 +21,13 @@ library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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@@ -39,8 +44,8 @@ Generic
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has_in_reg : boolean := false;
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has_pipe_reg : boolean := false;
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has_out_reg : boolean := false;
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rounding : boolean := true;
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saturating : boolean := true
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rounding : fixed_round_style_type := fixed_round;
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saturating : fixed_overflow_style_type := fixed_saturate
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);
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Port
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(
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@@ -130,8 +135,8 @@ begin
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variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low);
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begin
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sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating);
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sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating);
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sum_re := resize(scalb(p_re_left, nbits_scale_z), re, saturating, rounding);
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sum_im := resize(scalb(p_im_left, nbits_scale_z), im, saturating, rounding);
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if has_out_reg = true then
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if rising_edge(clk) then
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if srst = '1' then
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@@ -17,9 +17,12 @@ use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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use work.fixed_util_pkg.all;
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use work.PCK_FIO.all;
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ENTITY tb_mix_cpx IS
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@@ -32,8 +35,8 @@ ENTITY tb_mix_cpx IS
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has_in_reg : boolean := true;
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has_pipe_reg : boolean := true;
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has_out_reg : boolean := true;
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rounding : boolean := true;
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saturating : boolean := true
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rounding : fixed_round_style_type := fixed_round;
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saturating : fixed_overflow_style_type := fixed_saturate
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);
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END tb_mix_cpx;
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@@ -51,8 +54,8 @@ ARCHITECTURE behavior OF tb_mix_cpx IS
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has_in_reg : boolean;
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has_pipe_reg : boolean;
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has_out_reg : boolean;
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rounding : boolean;
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saturating : boolean
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rounding : fixed_round_style_type;
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saturating : fixed_overflow_style_type
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);
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PORT
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(
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@@ -17,9 +17,12 @@ use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_pkg.all;
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use work.mix_pkg.all;
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use work.fixed_util_pkg.all;
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use work.PCK_FIO.all;
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ENTITY tb_mix_real IS
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@@ -32,8 +35,8 @@ ENTITY tb_mix_real IS
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has_in_reg : boolean := true;
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has_pipe_reg : boolean := true;
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has_out_reg : boolean := true;
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rounding : boolean := true;
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saturating : boolean := true
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rounding : fixed_round_style_type := fixed_round;
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saturating : fixed_overflow_style_type := fixed_saturate
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);
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END tb_mix_real;
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@@ -51,8 +54,8 @@ ARCHITECTURE behavior OF tb_mix_real IS
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has_in_reg : boolean;
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has_pipe_reg : boolean;
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has_out_reg : boolean;
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rounding : boolean;
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saturating : boolean
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rounding : fixed_round_style_type;
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saturating : fixed_overflow_style_type
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);
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PORT
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(
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