From 91347dd60e3467600471d259cc84f32c98c6eeea Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sun, 12 Oct 2008 18:04:36 +0000
Subject: [PATCH] - Output pre_empty and pre_full for safer DPRAM control

git-svn-id: http://moon:8086/svn/vhdl/trunk@54 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/FIFO/src/sync_fifo_ctrl.vhd | 32 ++++++++++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd
index ef8661f..c533377 100644
--- a/lib/FIFO/src/sync_fifo_ctrl.vhd
+++ b/lib/FIFO/src/sync_fifo_ctrl.vhd
@@ -21,7 +21,7 @@
 -- For questions and ideas, please contact the author at jens@jayfield.org
 
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.2 2008-10-12 18:04:36 Jens Exp $
 -----------------------------------------------------------------------
 
 library IEEE;
@@ -42,6 +42,8 @@ entity sync_fifo_ctrl is
 		re				: in  STD_LOGIC;
 		ptr_w			: out unsigned (addr_width-1 downto 0);
 		ptr_r			: out unsigned (addr_width-1 downto 0);
+		fifo_pre_full	: out STD_LOGIC;
+		fifo_pre_empty	: out STD_LOGIC;
 		fifo_full		: out STD_LOGIC;
 		fifo_empty		: out STD_LOGIC;
 		fifo_afull		: out STD_LOGIC;
@@ -61,11 +63,13 @@ architecture Behavioral of sync_fifo_ctrl is
 	
 begin
 
-	read <= '1' when re = '1' and empty = '0' else '0';
-	write <= '1' when we = '1' and full = '0' else '0';
+	read	<= re and not empty;
+	write	<= we and not full;
 
-	fifo_full <= full;
-	fifo_empty <= empty;
+	fifo_full		<= full;
+	fifo_empty		<= empty;
+	fifo_pre_full	<= pre_full;
+	fifo_pre_empty	<= pre_empty;
 
 
 proc_diff_gen:
@@ -131,14 +135,14 @@ proc_empty_reg:
 	end process;
 	
 proc_status_w:
-	process(was_write, pW_next, pR_next, pW, pR, we, re)
+	process(was_write, pW_next, pR_next, pW, pR, write, read)
 	begin
-		if (pW_next = pR) and (we = '1' or was_write = '1') then
+		if (pW_next = pR) and (write = '1' or was_write = '1') then
 			pre_full <= '1';
 		else
 			pre_full <= '0';
 		end if;
-		if (pR_next = pW) and (re = '1' or was_write = '0') then
+		if (pR_next = pW) and (read = '1' or was_write = '0') then
 			pre_empty <= '1';
 		else
 			pre_empty <= '0';
@@ -160,36 +164,36 @@ proc_flag_write:
 	end process;
 	
 proc_ptr_w:
-	process(rst, clk, pW, we, full)
+	process(rst, clk, pW, write, full)
 	begin
 		if rst = '1' then
 			pW <= to_unsigned(0, addr_width);
 			pW_next <= to_unsigned(0, addr_width);
 		elsif rising_edge(clk) then
-			if we = '1' then 
+			if write = '1' then 
 				pW <= pW_next;
 			end if;
 		end if;
 		pW_next <= pW;
-		if we = '1' and full = '0' then 
+		if write = '1' then 
 			pW_next <= pW + 1;
 		end if;
 		ptr_w		<= pW;
 	end process;
 
 proc_ptr_r:
-	process(rst, clk, pR_next, pR, re, empty)
+	process(rst, clk, pR_next, pR, read, empty)
 	begin
 		if rst = '1' then
 			pR <= to_unsigned(0, addr_width);
 			pR_next <= to_unsigned(0, addr_width);
 		elsif rising_edge(clk) then
-			if re = '1' then
+			if read = '1' then
 				pR <= pR_next;
 			end if;	
 		end if;
 		pR_next	<= pR;
-		if re = '1' and empty = '0' then
+		if read = '1' then
 			pR_next	<= pR + 1;
 		end if;
 		ptr_r		<= pR_next;