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- fixed wrong EPC for ITLB and DTLB

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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1030 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-31 10:49:37 +00:00
parent 007c2ade02
commit 90b9112c5b
1 changed files with 16 additions and 16 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+15 -15
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@@ -159,6 +159,7 @@ architecture Behavioral of pipeline is
signal EX_events_instr : event_t; signal EX_events_instr : event_t;
signal EX_events_alu : event_t; signal EX_events_alu : event_t;
signal EX_events_mem : event_t; signal EX_events_mem : event_t;
signal EX_events_DTLB : event_t;
signal EX_events : event_t; signal EX_events : event_t;
signal MEM_events : event_t; signal MEM_events : event_t;
signal stage_rst : unsigned(3 downto 0); signal stage_rst : unsigned(3 downto 0);
@@ -453,9 +454,9 @@ proc_ID_except:
ID_stage.events <= events_clr; ID_stage.events <= events_clr;
ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0)); ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0));
ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode); ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode);
ID_stage.events.ITLB_LOAD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write; ID_stage.events.ITLB_LOAD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write;
ID_stage.events.ITLB_STORE <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write; ID_stage.events.ITLB_STORE <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write;
ID_stage.events.ITLB_MOD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty; ID_stage.events.ITLB_MOD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty;
end process; end process;
proc_stage_hdu: proc_stage_hdu:
@@ -570,14 +571,7 @@ inst_reg_dual: reg_dual
EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR);
EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR);
EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result; EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
EX_stage_tlb_query_results:
process(clk_1)
begin
if rising_edge(clk_1) then
EX_stage.dtlb_qry <= dtlb_qry_in; EX_stage.dtlb_qry <= dtlb_qry_in;
end if;
end process;
proc_stage_ID_EX_1: proc_stage_ID_EX_1:
process(clk_1) process(clk_1)
@@ -614,7 +608,7 @@ proc_stage_ID_EX_1:
end process; end process;
proc_stage_EX_instr_except: proc_stage_EX_instr_except:
process(EX_stage, ctrl_in) process(EX_stage)
begin begin
EX_events_instr <= events_clr; EX_events_instr <= events_clr;
EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal; EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal;
@@ -622,6 +616,15 @@ proc_stage_EX_instr_except:
EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall; EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall;
end process; end process;
proc_stage_EX_DTLB_except:
process(EX_stage)
begin
EX_events_DTLB <= events_clr;
EX_events_DTLB.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write;
EX_events_DTLB.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write;
EX_events_DTLB.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty;
end process;
proc_stage_EX_alu_except: proc_stage_EX_alu_except:
process(EX_stage) process(EX_stage)
begin begin
@@ -682,7 +685,7 @@ proc_stage_DMEM_ADDR:
end if; end if;
end if; end if;
end process; end process;
EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in; EX_stage.events <= EX_events_DTLB or EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
EX_stage.exc <= event_is_active(EX_stage.events); EX_stage.exc <= event_is_active(EX_stage.events);
-------------------------------------------------------------------------- --------------------------------------------------------------------------
@@ -897,9 +900,6 @@ proc_stage_MEM_except:
MEM_stage.events <= MEM_stage.events_in; MEM_stage.events <= MEM_stage.events_in;
MEM_stage.events.Int <= ctrl_in.int; MEM_stage.events.Int <= ctrl_in.int;
MEM_stage.events.NMI <= ctrl_in.NMI; MEM_stage.events.NMI <= ctrl_in.NMI;
MEM_stage.events.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write;
MEM_stage.events.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write;
MEM_stage.events.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty;
end process; end process;
MEM_stage.exc <= event_is_active(MEM_stage.events); MEM_stage.exc <= event_is_active(MEM_stage.events);