- fixed wrong EPC for ITLB and DTLB
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1030 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -159,6 +159,7 @@ architecture Behavioral of pipeline is
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signal EX_events_instr : event_t;
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signal EX_events_alu : event_t;
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signal EX_events_mem : event_t;
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signal EX_events_DTLB : event_t;
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signal EX_events : event_t;
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signal MEM_events : event_t;
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signal stage_rst : unsigned(3 downto 0);
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@@ -453,9 +454,9 @@ proc_ID_except:
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ID_stage.events <= events_clr;
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ID_stage.events.inst_load_err <= not ctrl_in.exc_pending and (ID_stage.pcn(1) or ID_stage.pcn(0));
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ID_stage.events.inst_priv_addr <= not ctrl_in.exc_pending and (ID_stage.pcn(word_t'left) and ctrl_in.user_mode);
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ID_stage.events.ITLB_LOAD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write;
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ID_stage.events.ITLB_STORE <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write;
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ID_stage.events.ITLB_MOD <= ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty;
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ID_stage.events.ITLB_LOAD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and not ID_stage.itlb_qry.write;
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ID_stage.events.ITLB_STORE <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.miss and ID_stage.itlb_qry.write;
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ID_stage.events.ITLB_MOD <= not ctrl_in.exc_pending and ID_stage.itlb_qry.vld and ID_stage.itlb_qry.dirty;
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end process;
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proc_stage_hdu:
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@@ -570,15 +571,8 @@ inst_reg_dual: reg_dual
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EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR);
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EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR);
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EX_stage.result <= alu_result when EX_stage.ctrl.mul_access = '0' else mul_result;
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EX_stage.dtlb_qry <= dtlb_qry_in;
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EX_stage_tlb_query_results:
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process(clk_1)
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begin
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if rising_edge(clk_1) then
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EX_stage.dtlb_qry <= dtlb_qry_in;
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end if;
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end process;
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proc_stage_ID_EX_1:
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process(clk_1)
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begin
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@@ -614,7 +608,7 @@ proc_stage_ID_EX_1:
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end process;
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proc_stage_EX_instr_except:
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process(EX_stage, ctrl_in)
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process(EX_stage)
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begin
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EX_events_instr <= events_clr;
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EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal;
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@@ -622,6 +616,15 @@ proc_stage_EX_instr_except:
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EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall;
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end process;
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proc_stage_EX_DTLB_except:
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process(EX_stage)
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begin
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EX_events_DTLB <= events_clr;
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EX_events_DTLB.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write;
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EX_events_DTLB.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write;
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EX_events_DTLB.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty;
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end process;
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proc_stage_EX_alu_except:
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process(EX_stage)
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begin
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@@ -682,7 +685,7 @@ proc_stage_DMEM_ADDR:
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end if;
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end if;
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end process;
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EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
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EX_stage.events <= EX_events_DTLB or EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
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EX_stage.exc <= event_is_active(EX_stage.events);
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--------------------------------------------------------------------------
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@@ -897,9 +900,6 @@ proc_stage_MEM_except:
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MEM_stage.events <= MEM_stage.events_in;
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MEM_stage.events.Int <= ctrl_in.int;
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MEM_stage.events.NMI <= ctrl_in.NMI;
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MEM_stage.events.DTLB_LOAD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and not EX_stage.dtlb_qry.write;
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MEM_stage.events.DTLB_STORE <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.miss and EX_stage.dtlb_qry.write;
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MEM_stage.events.DTLB_MOD <= EX_stage.dtlb_qry.vld and EX_stage.dtlb_qry.dirty;
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end process;
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MEM_stage.exc <= event_is_active(MEM_stage.events);
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