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- put reset-logic outside pipeline

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git-svn-id: http://moon:8086/svn/vhdl/trunk@339 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-02-11 09:52:55 +00:00
parent 3def04d376
commit 905094be8b
2 changed files with 31 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+5 -26
View File
@@ -33,7 +33,7 @@ entity pipeline is
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
ce : in STD_LOGIC;
int : in unsigned(5 downto 0);
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC;
@@ -174,13 +174,11 @@ architecture Behavioral of pipeline is
signal clk_2, clk_1 : STD_LOGIC;
signal hdu : hdu_t;
signal sdu : sdu_t;
signal cpu_rst : STD_LOGIC;
signal reg_a : word_t;
signal reg_b : word_t;
signal ctrl_lines : ctrl_lines_t;
signal cpu_run : STD_LOGIC;
signal branch_ce : STD_LOGIC;
signal run_en : STD_LOGIC;
signal cpu_run : STD_LOGIC;
signal mul_dep : STD_LOGIC;
signal imem_dep : STD_LOGIC;
signal dmem_dep : STD_LOGIC;
@@ -213,7 +211,7 @@ begin
clk_1 <= clk;
clk_2 <= not clk;
cpu_run <= run_en;
cpu_run <= ce;
-- Stall Detection Unit ---------------------------------------------------
sdu.ID_nop <= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc;
@@ -238,7 +236,7 @@ begin
inst_muldiv: muldiv
PORT MAP
(
rst => cpu_rst,
rst => rst,
clk => clk,
hilo_we => EX_stage.ctrl.mul_hilo_we,
din_hi => EX_stage.reg_a,
@@ -257,7 +255,7 @@ inst_muldiv: muldiv
inst_cop: cop
PORT MAP
(
rst => cpu_rst,
rst => rst,
clk => clk,
sdu => sdu,
events => MEM_stage.events,
@@ -362,25 +360,6 @@ proc_stage_branch:
end if;
end process;
process(rst, clk_1)
variable reset_delay : unsigned (5 downto 0);
begin
if rising_edge(clk_1) then
if rst = '1' then
reset_delay := (others => '1');
cpu_rst <= '1';
run_en <= '0';
elsif reset_delay /= (5 downto 0 => '0') then
reset_delay := reset_delay - 1;
else
cpu_rst <= '0';
end if;
if reset_delay(reset_delay'left-1) = '0' then
run_en <= '1';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- ID stage
--------------------------------------------------------------------------
lib/CPUs/MIPS/src/core/mips_top.vhd
+26 -4
View File
@@ -61,7 +61,7 @@ architecture rtl of mips_top is
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
halt : in STD_LOGIC;
ce : in STD_LOGIC;
int : in unsigned (5 downto 0);
imem_err : in STD_LOGIC;
imem_rdy : in STD_LOGIC;
@@ -92,6 +92,9 @@ architecture rtl of mips_top is
signal dmem_din : word_t;
signal dmem_be : unsigned(3 downto 0);
signal cpu_rst : STD_LOGIC;
signal cpu_run : STD_LOGIC;
COMPONENT biu
GENERIC
(
@@ -134,12 +137,31 @@ begin
debug(0) <= imem_err;
debug(1) <= dmem_err;
process(CLK_I)
variable reset_delay : unsigned (5 downto 0);
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
reset_delay := (others => '1');
cpu_rst <= '1';
cpu_run <= '0';
elsif reset_delay /= (5 downto 0 => '0') then
reset_delay := reset_delay - 1;
else
cpu_rst <= '0';
end if;
if reset_delay(reset_delay'left-1) = '0' then
cpu_run <= '1';
end if;
end if;
end process;
inst_pipeline: pipeline
PORT MAP
(
rst => RST_I,
rst => cpu_rst,
clk => CLK_I,
halt => '0',
ce => cpu_run,
int => INT,
imem_err => imem_err,
imem_rdy => imem_rdy,
@@ -164,7 +186,7 @@ inst_biu: biu
)
PORT MAP
(
RST_I => RST_I,
RST_I => cpu_rst,
CLK_I => CLK_I,
ACK_I => ACK_I,
SRDY_I => SRDY_I,