From 904ec64a52ef130245d4f8934e6aa39dd2127b91 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 28 Mar 2010 23:27:06 +0000 Subject: [PATCH] - assigned INT_O - register interface still under construction Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@844 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/emac_top_jb.vhd | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/lib/emac/src/emac_top_jb.vhd b/lib/emac/src/emac_top_jb.vhd index e862b90..050b2a7 100644 --- a/lib/emac/src/emac_top_jb.vhd +++ b/lib/emac/src/emac_top_jb.vhd @@ -62,12 +62,15 @@ ARCHITECTURE behavior OF emac_top_jb IS signal irq_rx : std_logic; signal irq_tx : std_logic; + signal ready : std_logic; + begin - SRDY_O <= CYC_I; - INT_O <= irq_rx or irq_tx; + SRDY_O <= CYC_I and ready; mii_gtx_clk <= '0'; + ready <= not tx_ctrl_in.pkt_alloc_en; + ------------------------------------------------------------------ registers_write: process(CLK_I) @@ -123,7 +126,7 @@ registers_read: case ADDR_I(5 downto 2) is when "0000" => - ACK_O <= '1'; + ACK_O <= ready; DAT_O <= (others => '0'); DAT_O(31) <= tx_ctrl_in.tx_er; DAT_O(30) <= mii_rx_er; @@ -155,8 +158,9 @@ irq_register: process(CLK_I) begin if rising_edge(CLK_I) then - irq_tx <= tx_int_en; - irq_rx <= rx_int_en; + INT_O <= irq_rx or irq_tx; + irq_tx <= tx_int_en and tx_ctrl_out.pkt_done; + irq_rx <= rx_int_en and rx_ctrl_out.pkt_avail; end if; end process;