From 8f283ae097a35a099db42f539d85286b42277bb5 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 6 Apr 2010 13:29:27 +0000 Subject: [PATCH] - simplified: removed MII-FIFO. Connected RAM to MII-domain Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@857 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/emac/src/emac_rx.vhd | 384 ++++++++++----------------------------- 1 file changed, 95 insertions(+), 289 deletions(-) diff --git a/lib/emac/src/emac_rx.vhd b/lib/emac/src/emac_rx.vhd index 38a1adb..a445f11 100644 --- a/lib/emac/src/emac_rx.vhd +++ b/lib/emac/src/emac_rx.vhd @@ -37,13 +37,6 @@ ARCHITECTURE behavior OF emac_rx IS subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0); -- Signals for EMAC connections - signal mii_fifo_din : unsigned(31 downto 0); - signal mii_fifo_dout : unsigned(31 downto 0); - signal mii_fifo_we : std_logic; - signal mii_fifo_re : std_logic; - signal mii_fifo_empty : std_logic; - signal mii_fifo_full : std_logic; - signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0); signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0); signal cmd_fifo_we : std_logic; @@ -60,24 +53,19 @@ ARCHITECTURE behavior OF emac_rx IS signal xfer_ram_limit : word_ptr_t; signal xfer_ram_full : std_logic; signal xfer_base : word_ptr_t; - signal xfer_size : word_ptr_t; signal xfer_ptr : word_ptr_t; - signal xfer_ptr_set : std_logic; - signal xfer_ptr_adv : std_logic; - signal xfer_cnt_set : std_logic; - signal xfer_cnt_adv : std_logic; - signal xfer_rdy : std_logic; + signal xfer_en : std_logic; + signal xfer_set : std_logic; signal xfer_vld : std_logic; + signal xfer_promiscious : std_logic; signal ram_en_a : std_logic; signal ram_we_a : std_logic; signal ram_addr_a : word_ptr_t; signal ram_din_a : unsigned(31 downto 0); - signal ram_dout_a : unsigned(31 downto 0); + signal ram_dout_b : unsigned(31 downto 0); signal ram_en_b : std_logic; - signal ram_we_b : std_logic; signal ram_addr_b : word_ptr_t; - signal ram_din_b : unsigned(31 downto 0); signal sipo_32bit_dout : unsigned(31 downto 0); signal sipo_32bit_dout_be : unsigned(3 downto 0); @@ -96,16 +84,6 @@ ARCHITECTURE behavior OF emac_rx IS signal byte_count : word_ptr_t; signal byte_count_reg : word_ptr_t; - signal word_count : word_ptr_t; - signal word_count_en : std_logic; - - signal size_fifo_full : std_logic; - signal size_fifo_empty : std_logic; - signal size_fifo_we : std_logic; - signal size_fifo_re : std_logic; - signal size_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0); - signal size_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0); - signal reset_pipe : unsigned(31 downto 0); signal preamble_rst : std_logic; @@ -125,36 +103,21 @@ ARCHITECTURE behavior OF emac_rx IS type host_state_t is (host_init, host_flush, host_idle); signal host_s, host_sn : host_state_t; - type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free); + type xfer_state_t is (xfer_init, xfer_reset, xfer_idle, xfer_setup, xfer_active, xfer_stop, xfer_finish); signal xfer_s, xfer_sn : xfer_state_t; - type stream_state_t is (stream_init, stream_reset, stream_idle, stream_active, stream_stop, stream_finish); - signal stream_s, stream_sn : stream_state_t; - alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left); alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1); - alias cmd_invalid_in is cmd_fifo_din(cmd_fifo_din'left-2); + alias cmd_pkt_lost_in is cmd_fifo_din(cmd_fifo_din'left-2); alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0); alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length); alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left); alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1); - alias cmd_invalid_out is cmd_fifo_dout(cmd_fifo_dout'left-2); + alias cmd_pkt_lost_out is cmd_fifo_dout(cmd_fifo_dout'left-2); alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0); alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length); - alias stream_mac_ok_in is size_fifo_din(size_fifo_din'left); - alias stream_broadcast_in is size_fifo_din(size_fifo_din'left-1); - alias stream_badcrc_in is size_fifo_din(size_fifo_din'left-2); - alias stream_nbytes_in is size_fifo_din(word_ptr_t'length-1 downto 0); - alias stream_nwords_in is size_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length); - - alias stream_mac_ok_out is size_fifo_dout(size_fifo_dout'left); - alias stream_broadcast_out is size_fifo_dout(size_fifo_dout'left-1); - alias stream_badcrc_out is size_fifo_dout(size_fifo_dout'left-2); - alias stream_nbytes_out is size_fifo_dout(word_ptr_t'length-1 downto 0); - alias stream_nwords_out is size_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length); - begin ctrl_out.rx_size <= resize(cmd_nbytes_out, 16); @@ -163,37 +126,29 @@ begin ctrl_out.reset_busy <= reset_en; ctrl_out.pkt_bcast <= cmd_bcast_out; ctrl_out.pkt_mac_match <= cmd_mac_ok_out; - - dout <= ram_dout_a; - - mii_fifo_din <= sipo_32bit_dout; - mii_fifo_we <= word_count_en and sipo_32bit_dout_vld; - - ram_en_a <= '1'; - ram_din_a <= (others => '-'); - ram_addr_a <= fill_ptr; - ram_we_a <= '0'; + ctrl_out.pkt_lost <= cmd_pkt_lost_out; + + dout <= ram_dout_b; ram_en_b <= '1'; - ram_din_b <= mii_fifo_dout; - ram_addr_b <= xfer_ptr; - ram_we_b <= xfer_ptr_adv; + ram_addr_b <= fill_ptr; + + ram_en_a <= '1'; + ram_din_a <= sipo_32bit_dout; + ram_addr_a <= xfer_ptr; + ram_we_a <= xfer_en and sipo_32bit_dout_vld; + xfer_vld <= not xfer_ram_full and (mac_chk_OK or mac_chk_BC or ctrl_in.promiscious); cmd_fifo_we <= commit_en; cmd_fifo_re <= ctrl_in.pkt_free_en; - cmd_mac_ok_in <= stream_mac_ok_out; - cmd_bcast_in <= stream_broadcast_out; - cmd_invalid_in <= stream_badcrc_out; - cmd_nbytes_in <= stream_nbytes_out; + cmd_mac_ok_in <= mac_chk_OK; + cmd_bcast_in <= mac_chk_BC; + cmd_nbytes_in <= byte_count_reg; cmd_base_in <= xfer_base; + cmd_pkt_lost_in <= xfer_ram_full; - stream_nbytes_in <= byte_count_reg; - stream_nwords_in <= word_count; - stream_mac_ok_in <= mac_chk_OK; - stream_broadcast_in <= mac_chk_BC; - stream_badcrc_in <= '0'; - + reset_en <= reset_pipe(reset_pipe'left); ------------------------------------------------------------------ @@ -228,100 +183,19 @@ fill_pointer: ------------------------------------------------------------------ -- Transfer stuff ------------------------------------------------------------------ -xfer_state_next: - process(clk) +host2xfer_sync_register: + process(mii_rx_clk) begin - if rising_edge(clk) then - if reset_en = '1' then - xfer_s <= xfer_init; - else - xfer_s <= xfer_sn; - end if; - end if; - end process; - -xfer_state: - process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_vld, xfer_ram_full) - begin - - commit_en <= '0'; - xfer_ptr_set <= '0'; - xfer_ptr_adv <= '0'; - xfer_cnt_set <= '0'; - xfer_cnt_adv <= '0'; - size_fifo_re <= '0'; - mii_fifo_re <= '0'; - - xfer_sn <= xfer_s; - - case xfer_s is - - when xfer_init => - xfer_sn <= xfer_idle; - - when xfer_idle => - if mii_fifo_empty = '0' then - xfer_sn <= xfer_setup; - end if; - - when xfer_setup => - xfer_cnt_set <= '1'; - xfer_ptr_set <= '1'; - xfer_sn <= xfer_active; - - when xfer_active => - mii_fifo_re <= '1'; - xfer_cnt_adv <= not mii_fifo_empty; - xfer_ptr_adv <= not mii_fifo_empty; - if xfer_ram_full = '1' then - xfer_sn <= xfer_drop; - elsif size_fifo_empty = '0' then - if xfer_rdy = '1' then - xfer_sn <= xfer_free; - end if; - end if; - - when xfer_drop => - mii_fifo_re <= '1'; - xfer_cnt_adv <= not mii_fifo_empty; - if size_fifo_empty = '0' then - if xfer_rdy = '1' then - xfer_sn <= xfer_free; - end if; - end if; - - when xfer_free => - size_fifo_re <= '1'; - commit_en <= not xfer_ram_full and xfer_vld; - xfer_sn <= xfer_idle; - - when others => - xfer_sn <= xfer_idle; - end case; - - end process; - ------------------------------------------------------------------- -pkt_lost_register: - process(clk) - begin - if rising_edge(clk) then - if reset_en = '1' then - ctrl_out.pkt_lost <= '0'; - elsif size_fifo_re = '1' and xfer_ram_full = '1' then - ctrl_out.pkt_lost <= '1'; - elsif ctrl_in.pkt_free_en = '1' then - ctrl_out.pkt_lost <= '0'; - end if; + if rising_edge(mii_rx_clk) then + xfer_promiscious <= ctrl_in.promiscious; end if; - end process; xfer_limit_register: - process(clk) + process(mii_rx_clk) begin - if rising_edge(clk) then - if xfer_ptr_set = '1' then + if rising_edge(mii_rx_clk) then + if xfer_set = '1' then if cmd_fifo_empty = '1' then xfer_ram_limit <= xfer_base - 1; else @@ -333,12 +207,12 @@ xfer_limit_register: end process; xfer_ram_full_detect: - process(clk) + process(mii_rx_clk) begin - if rising_edge(clk) then - if xfer_ptr_set = '1' or reset_en = '1' then + if rising_edge(mii_rx_clk) then + if xfer_set = '1' or reset_en = '1' then xfer_ram_full <= '0'; - elsif xfer_ptr_adv = '1' then + elsif xfer_en = '1' and sipo_32bit_dout_vld = '1' then if xfer_ptr = xfer_ram_limit then xfer_ram_full <= '1'; end if; @@ -347,43 +221,10 @@ xfer_ram_full_detect: end process; -xfer_counter: - process(clk) - begin - if rising_edge(clk) then - if xfer_cnt_set = '1' then - xfer_rdy <= '0'; - xfer_vld <= '0'; - elsif xfer_size = stream_nwords_out then - xfer_rdy <= '1'; - xfer_vld <= stream_mac_ok_out or stream_broadcast_out or ctrl_in.promiscious; - end if; - if xfer_cnt_set = '1' then - xfer_size <= (others => '0'); - elsif xfer_cnt_adv = '1' then - xfer_size <= xfer_size + 1; - end if; - end if; - - end process; - -xfer_pointer: - process(clk) - begin - if rising_edge(clk) then - if xfer_ptr_set = '1' then - xfer_ptr <= xfer_base; - elsif xfer_ptr_adv = '1' then - xfer_ptr <= xfer_ptr + 1; - end if; - end if; - - end process; - xfer_base_logic: - process(clk) + process(mii_rx_clk) begin - if rising_edge(clk) then + if rising_edge(mii_rx_clk) then if reset_en = '1' then xfer_base <= (others => '0'); elsif commit_en = '1' then @@ -392,6 +233,19 @@ xfer_base_logic: end if; end process; +xfer_pointer: + process(mii_rx_clk) + begin + if rising_edge(mii_rx_clk) then + if xfer_set = '1' then + xfer_ptr <= xfer_base; + elsif xfer_en = '1' and sipo_32bit_dout_vld = '1' then + xfer_ptr <= xfer_ptr + 1; + end if; + end if; + + end process; + ------------------------------------------------------------------ byte_counter: process(mii_rx_clk) @@ -415,18 +269,6 @@ byte_count_register: end if; end process; -word_counter: - process(mii_rx_clk) - begin - if rising_edge(mii_rx_clk) then - if sipo_32bit_rst = '1' then - word_count <= (others => '0'); - elsif word_count_en = '1' and sipo_32bit_dout_vld = '1' then - word_count <= word_count + 1; - end if; - end if; - end process; - preamble_sync_logic: process(mii_rx_clk) begin @@ -487,88 +329,97 @@ mac_check_logic: end process; ------------------------------------------------------------------ -stream_state_next: +xfer_state_next: process(mii_rx_clk) begin if rising_edge(mii_rx_clk) then if reset_en = '1' then - stream_s <= stream_init; + xfer_s <= xfer_init; else - stream_s <= stream_sn; + xfer_s <= xfer_sn; end if; end if; end process; -stream_state: - process(stream_s, reset_en, sipo_8bit_dout_en, sipo_8bit_dout, sipo_32bit_dout_en, sipo_32bit_dout_vld, preamble_rdy, preamble_OK) +xfer_state: + process(xfer_s, reset_en, sipo_8bit_dout_en, sipo_8bit_dout, sipo_32bit_dout_en, sipo_32bit_dout_vld, preamble_rdy, preamble_OK, xfer_ram_full, xfer_vld) begin + commit_en <= '0'; + xfer_set <= '0'; + xfer_en <= '0'; sipo_32bit_en <= '0'; sipo_32bit_rst <= reset_en; sipo_8bit_rst <= reset_en; - word_count_en <= '0'; byte_count_en <= '0'; - size_fifo_we <= '0'; preamble_rst <= reset_en; mac_chk_rst <= reset_en; sipo_32bit_en <= sipo_8bit_dout_en; - stream_sn <= stream_s; + xfer_sn <= xfer_s; - case stream_s is + case xfer_s is - when stream_init => + when xfer_init => if sipo_8bit_dout_en = '0' then - stream_sn <= stream_reset; + xfer_sn <= xfer_reset; end if; - when stream_reset => + when xfer_reset => sipo_32bit_rst <= '1'; sipo_8bit_rst <= '1'; preamble_rst <= '1'; - stream_sn <= stream_idle; + xfer_sn <= xfer_idle; - when stream_idle => + when xfer_idle => sipo_32bit_en <= '0'; if preamble_rdy = '1' then - stream_sn <= stream_init; + xfer_sn <= xfer_init; if preamble_OK = '1' then byte_count_en <= '1'; mac_chk_rst <= '1'; sipo_32bit_rst <= '1'; - stream_sn <= stream_active; + xfer_sn <= xfer_setup; end if; end if; - when stream_active => - word_count_en <= sipo_32bit_dout_en; + when xfer_setup => + xfer_set <= '1'; + xfer_en <= sipo_32bit_dout_en; byte_count_en <= sipo_8bit_dout_en; - if sipo_8bit_dout_en = '0' then - stream_sn <= stream_stop; + xfer_sn <= xfer_active; + + when xfer_active => + xfer_en <= sipo_32bit_dout_en; + byte_count_en <= sipo_8bit_dout_en; + if xfer_ram_full = '1' then + xfer_sn <= xfer_finish; + elsif sipo_8bit_dout_en = '0' then + xfer_sn <= xfer_stop; sipo_8bit_rst <= '1'; end if; - when stream_stop => - word_count_en <= sipo_32bit_dout_en; + when xfer_stop => + xfer_en <= sipo_32bit_dout_en; byte_count_en <= sipo_8bit_dout_en; if sipo_32bit_dout_en = '0' then - stream_sn <= stream_finish; + xfer_sn <= xfer_finish; end if; - when stream_finish => - size_fifo_we <= '1'; - stream_sn <= stream_init; + when xfer_finish => + commit_en <= xfer_vld; + xfer_sn <= xfer_init; when others => - stream_sn <= stream_init; + xfer_sn <= xfer_init; end case; end process; ------------------------------------------------------------------ -- Instantiate synchronous FIFO -inst_cmd_fifo: entity work.fifo_sync +inst_cmd_fifo: entity work.fifo_async GENERIC MAP ( addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words) @@ -578,7 +429,8 @@ inst_cmd_fifo: entity work.fifo_sync PORT MAP ( rst => reset_en, - clk => clk, + clk_w => mii_rx_clk, + clk_r => clk, we => cmd_fifo_we, re => cmd_fifo_re, fifo_full => cmd_fifo_full, @@ -597,61 +449,15 @@ inst_ram : entity work.dpram_1w1r ) PORT MAP ( - clka => clk, + clka => mii_rx_clk, clkb => clk, - en_a => ram_en_b, - en_b => ram_en_a, - we_a => ram_we_b, - addr_a => ram_addr_b, - addr_b => ram_addr_a, - din_a => ram_din_b, - dout_b => ram_dout_a - ); - --- Instantiate synchronous FIFO -inst_mii_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => 4, - data_width => mii_fifo_din'length, - do_last_read_update => true - ) - PORT MAP - ( - rst => reset_en, - clk_w => mii_rx_clk, - clk_r => clk, - we => mii_fifo_we, - re => mii_fifo_re, - fifo_full => mii_fifo_full, - fifo_empty => mii_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => mii_fifo_din, - data_r => mii_fifo_dout - ); - --- Instantiate synchronous FIFO -inst_size_fifo: entity work.fifo_async - GENERIC MAP - ( - addr_width => 1, - data_width => size_fifo_din'length, - do_last_read_update => true - ) - PORT MAP - ( - rst => reset_en, - clk_w => mii_rx_clk, - clk_r => clk, - we => size_fifo_we, - re => size_fifo_re, - fifo_full => size_fifo_full, - fifo_empty => size_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => size_fifo_din, - data_r => size_fifo_dout + en_a => ram_en_a, + en_b => ram_en_b, + we_a => ram_we_a, + addr_a => ram_addr_a, + addr_b => ram_addr_b, + din_a => ram_din_a, + dout_b => ram_dout_b ); inst_sipo : entity work.sipo